Mercurial > public > ostc4

comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c @ 128:c78bcbd5deda FlipDisplay

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
parents
children
comparison
equal deleted inserted replaced
127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_sram.c
4 * @author MCD Application Team
5 * @brief SRAM HAL module driver.
6 * This file provides a generic firmware to drive SRAM memories
7 * mounted as external device.
8 *
9 @verbatim
10 ==============================================================================
11 ##### How to use this driver #####
12 ==============================================================================
13 [..]
14 This driver is a generic layered driver which contains a set of APIs used to
15 control SRAM memories. It uses the FMC layer functions to interface
16 with SRAM devices.
17 The following sequence should be followed to configure the FMC/FSMC to interface
18 with SRAM/PSRAM memories:
19
20 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
21 SRAM_HandleTypeDef hsram; and:
22
23 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
24 values of the structure member.
25
26 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
27 base register instance for NOR or SRAM device
28
29 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
30 base register instance for NOR or SRAM extended mode
31
32 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
33 mode timings; for example:
34 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
35 and fill its fields with the allowed values of the structure member.
36
37 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
38 performs the following sequence:
39
40 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
41 (##) Control register configuration using the FMC NORSRAM interface function
42 FMC_NORSRAM_Init()
43 (##) Timing register configuration using the FMC NORSRAM interface function
44 FMC_NORSRAM_Timing_Init()
45 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
46 FMC_NORSRAM_Extended_Timing_Init()
47 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
48
49 (#) At this stage you can perform read/write accesses from/to the memory connected
50 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
51 following APIs:
52 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
53 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
54
55 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
56 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
57
58 (#) You can continuously monitor the SRAM device HAL state by calling the function
59 HAL_SRAM_GetState()
60
61 @endverbatim
62 ******************************************************************************
63 * @attention
64 *
65 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
66 *
67 * Redistribution and use in source and binary forms, with or without modification,
68 * are permitted provided that the following conditions are met:
69 * 1. Redistributions of source code must retain the above copyright notice,
70 * this list of conditions and the following disclaimer.
71 * 2. Redistributions in binary form must reproduce the above copyright notice,
72 * this list of conditions and the following disclaimer in the documentation
73 * and/or other materials provided with the distribution.
74 * 3. Neither the name of STMicroelectronics nor the names of its contributors
75 * may be used to endorse or promote products derived from this software
76 * without specific prior written permission.
77 *
78 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
79 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
80 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
81 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
82 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
83 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
84 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
85 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
86 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
88 *
89 ******************************************************************************
90 */
91
92 /* Includes ------------------------------------------------------------------*/
93 #include "stm32f4xx_hal.h"
94
95 /** @addtogroup STM32F4xx_HAL_Driver
96 * @{
97 */
98
99 /** @defgroup SRAM SRAM
100 * @brief SRAM driver modules
101 * @{
102 */
103 #ifdef HAL_SRAM_MODULE_ENABLED
104
105 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
106 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
107 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
108 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
109
110 /* Private typedef -----------------------------------------------------------*/
111 /* Private define ------------------------------------------------------------*/
112 /* Private macro -------------------------------------------------------------*/
113 /* Private variables ---------------------------------------------------------*/
114 /* Private functions ---------------------------------------------------------*/
115
116 /* Exported functions --------------------------------------------------------*/
117 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
118 * @{
119 */
120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
121 * @brief Initialization and Configuration functions
122 *
123 @verbatim
124 ==============================================================================
125 ##### SRAM Initialization and de_initialization functions #####
126 ==============================================================================
127 [..] This section provides functions allowing to initialize/de-initialize
128 the SRAM memory
129
130 @endverbatim
131 * @{
132 */
133
134 /**
135 * @brief Performs the SRAM device initialization sequence
136 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
137 * the configuration information for SRAM module.
138 * @param Timing Pointer to SRAM control timing structure
139 * @param ExtTiming Pointer to SRAM extended mode timing structure
140 * @retval HAL status
141 */
142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
143 {
144 /* Check the SRAM handle parameter */
145 if(hsram == NULL)
146 {
147 return HAL_ERROR;
148 }
149
150 if(hsram->State == HAL_SRAM_STATE_RESET)
151 {
152 /* Allocate lock resource and initialize it */
153 hsram->Lock = HAL_UNLOCKED;
154 /* Initialize the low level hardware (MSP) */
155 HAL_SRAM_MspInit(hsram);
156 }
157
158 /* Initialize SRAM control Interface */
159 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
160
161 /* Initialize SRAM timing Interface */
162 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
163
164 /* Initialize SRAM extended mode timing Interface */
165 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
166
167 /* Enable the NORSRAM device */
168 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
169
170 return HAL_OK;
171 }
172
173 /**
174 * @brief Performs the SRAM device De-initialization sequence.
175 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
176 * the configuration information for SRAM module.
177 * @retval HAL status
178 */
179 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
180 {
181 /* De-Initialize the low level hardware (MSP) */
182 HAL_SRAM_MspDeInit(hsram);
183
184 /* Configure the SRAM registers with their reset values */
185 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
186
187 hsram->State = HAL_SRAM_STATE_RESET;
188
189 /* Release Lock */
190 __HAL_UNLOCK(hsram);
191
192 return HAL_OK;
193 }
194
195 /**
196 * @brief SRAM MSP Init.
197 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
198 * the configuration information for SRAM module.
199 * @retval None
200 */
201 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
202 {
203 /* Prevent unused argument(s) compilation warning */
204 UNUSED(hsram);
205 /* NOTE : This function Should not be modified, when the callback is needed,
206 the HAL_SRAM_MspInit could be implemented in the user file
207 */
208 }
209
210 /**
211 * @brief SRAM MSP DeInit.
212 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
213 * the configuration information for SRAM module.
214 * @retval None
215 */
216 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
217 {
218 /* Prevent unused argument(s) compilation warning */
219 UNUSED(hsram);
220 /* NOTE : This function Should not be modified, when the callback is needed,
221 the HAL_SRAM_MspDeInit could be implemented in the user file
222 */
223 }
224
225 /**
226 * @brief DMA transfer complete callback.
227 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
228 * the configuration information for SRAM module.
229 * @retval None
230 */
231 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
232 {
233 /* Prevent unused argument(s) compilation warning */
234 UNUSED(hdma);
235 /* NOTE : This function Should not be modified, when the callback is needed,
236 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
237 */
238 }
239
240 /**
241 * @brief DMA transfer complete error callback.
242 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
243 * the configuration information for SRAM module.
244 * @retval None
245 */
246 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
247 {
248 /* Prevent unused argument(s) compilation warning */
249 UNUSED(hdma);
250 /* NOTE : This function Should not be modified, when the callback is needed,
251 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
252 */
253 }
254
255 /**
256 * @}
257 */
258
259 /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
260 * @brief Input Output and memory control functions
261 *
262 @verbatim
263 ==============================================================================
264 ##### SRAM Input and Output functions #####
265 ==============================================================================
266 [..]
267 This section provides functions allowing to use and control the SRAM memory
268
269 @endverbatim
270 * @{
271 */
272
273 /**
274 * @brief Reads 8-bit buffer from SRAM memory.
275 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
276 * the configuration information for SRAM module.
277 * @param pAddress Pointer to read start address
278 * @param pDstBuffer Pointer to destination buffer
279 * @param BufferSize Size of the buffer to read from memory
280 * @retval HAL status
281 */
282 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
283 {
284 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
285
286 /* Process Locked */
287 __HAL_LOCK(hsram);
288
289 /* Update the SRAM controller state */
290 hsram->State = HAL_SRAM_STATE_BUSY;
291
292 /* Read data from memory */
293 for(; BufferSize != 0U; BufferSize--)
294 {
295 *pDstBuffer = *(__IO uint8_t *)pSramAddress;
296 pDstBuffer++;
297 pSramAddress++;
298 }
299
300 /* Update the SRAM controller state */
301 hsram->State = HAL_SRAM_STATE_READY;
302
303 /* Process unlocked */
304 __HAL_UNLOCK(hsram);
305
306 return HAL_OK;
307 }
308
309 /**
310 * @brief Writes 8-bit buffer to SRAM memory.
311 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
312 * the configuration information for SRAM module.
313 * @param pAddress Pointer to write start address
314 * @param pSrcBuffer Pointer to source buffer to write
315 * @param BufferSize Size of the buffer to write to memory
316 * @retval HAL status
317 */
318 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
319 {
320 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
321
322 /* Check the SRAM controller state */
323 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
324 {
325 return HAL_ERROR;
326 }
327
328 /* Process Locked */
329 __HAL_LOCK(hsram);
330
331 /* Update the SRAM controller state */
332 hsram->State = HAL_SRAM_STATE_BUSY;
333
334 /* Write data to memory */
335 for(; BufferSize != 0U; BufferSize--)
336 {
337 *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
338 pSrcBuffer++;
339 pSramAddress++;
340 }
341
342 /* Update the SRAM controller state */
343 hsram->State = HAL_SRAM_STATE_READY;
344
345 /* Process unlocked */
346 __HAL_UNLOCK(hsram);
347
348 return HAL_OK;
349 }
350
351 /**
352 * @brief Reads 16-bit buffer from SRAM memory.
353 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
354 * the configuration information for SRAM module.
355 * @param pAddress Pointer to read start address
356 * @param pDstBuffer Pointer to destination buffer
357 * @param BufferSize Size of the buffer to read from memory
358 * @retval HAL status
359 */
360 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
361 {
362 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
363
364 /* Process Locked */
365 __HAL_LOCK(hsram);
366
367 /* Update the SRAM controller state */
368 hsram->State = HAL_SRAM_STATE_BUSY;
369
370 /* Read data from memory */
371 for(; BufferSize != 0U; BufferSize--)
372 {
373 *pDstBuffer = *(__IO uint16_t *)pSramAddress;
374 pDstBuffer++;
375 pSramAddress++;
376 }
377
378 /* Update the SRAM controller state */
379 hsram->State = HAL_SRAM_STATE_READY;
380
381 /* Process unlocked */
382 __HAL_UNLOCK(hsram);
383
384 return HAL_OK;
385 }
386
387 /**
388 * @brief Writes 16-bit buffer to SRAM memory.
389 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
390 * the configuration information for SRAM module.
391 * @param pAddress Pointer to write start address
392 * @param pSrcBuffer Pointer to source buffer to write
393 * @param BufferSize Size of the buffer to write to memory
394 * @retval HAL status
395 */
396 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
397 {
398 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
399
400 /* Check the SRAM controller state */
401 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
402 {
403 return HAL_ERROR;
404 }
405
406 /* Process Locked */
407 __HAL_LOCK(hsram);
408
409 /* Update the SRAM controller state */
410 hsram->State = HAL_SRAM_STATE_BUSY;
411
412 /* Write data to memory */
413 for(; BufferSize != 0U; BufferSize--)
414 {
415 *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
416 pSrcBuffer++;
417 pSramAddress++;
418 }
419
420 /* Update the SRAM controller state */
421 hsram->State = HAL_SRAM_STATE_READY;
422
423 /* Process unlocked */
424 __HAL_UNLOCK(hsram);
425
426 return HAL_OK;
427 }
428
429 /**
430 * @brief Reads 32-bit buffer from SRAM memory.
431 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
432 * the configuration information for SRAM module.
433 * @param pAddress Pointer to read start address
434 * @param pDstBuffer Pointer to destination buffer
435 * @param BufferSize Size of the buffer to read from memory
436 * @retval HAL status
437 */
438 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
439 {
440 /* Process Locked */
441 __HAL_LOCK(hsram);
442
443 /* Update the SRAM controller state */
444 hsram->State = HAL_SRAM_STATE_BUSY;
445
446 /* Read data from memory */
447 for(; BufferSize != 0U; BufferSize--)
448 {
449 *pDstBuffer = *(__IO uint32_t *)pAddress;
450 pDstBuffer++;
451 pAddress++;
452 }
453
454 /* Update the SRAM controller state */
455 hsram->State = HAL_SRAM_STATE_READY;
456
457 /* Process unlocked */
458 __HAL_UNLOCK(hsram);
459
460 return HAL_OK;
461 }
462
463 /**
464 * @brief Writes 32-bit buffer to SRAM memory.
465 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
466 * the configuration information for SRAM module.
467 * @param pAddress Pointer to write start address
468 * @param pSrcBuffer Pointer to source buffer to write
469 * @param BufferSize Size of the buffer to write to memory
470 * @retval HAL status
471 */
472 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
473 {
474 /* Check the SRAM controller state */
475 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
476 {
477 return HAL_ERROR;
478 }
479
480 /* Process Locked */
481 __HAL_LOCK(hsram);
482
483 /* Update the SRAM controller state */
484 hsram->State = HAL_SRAM_STATE_BUSY;
485
486 /* Write data to memory */
487 for(; BufferSize != 0U; BufferSize--)
488 {
489 *(__IO uint32_t *)pAddress = *pSrcBuffer;
490 pSrcBuffer++;
491 pAddress++;
492 }
493
494 /* Update the SRAM controller state */
495 hsram->State = HAL_SRAM_STATE_READY;
496
497 /* Process unlocked */
498 __HAL_UNLOCK(hsram);
499
500 return HAL_OK;
501 }
502
503 /**
504 * @brief Reads a Words data from the SRAM memory using DMA transfer.
505 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
506 * the configuration information for SRAM module.
507 * @param pAddress Pointer to read start address
508 * @param pDstBuffer Pointer to destination buffer
509 * @param BufferSize Size of the buffer to read from memory
510 * @retval HAL status
511 */
512 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
513 {
514 /* Process Locked */
515 __HAL_LOCK(hsram);
516
517 /* Update the SRAM controller state */
518 hsram->State = HAL_SRAM_STATE_BUSY;
519
520 /* Configure DMA user callbacks */
521 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
522 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
523
524 /* Enable the DMA Stream */
525 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
526
527 /* Update the SRAM controller state */
528 hsram->State = HAL_SRAM_STATE_READY;
529
530 /* Process unlocked */
531 __HAL_UNLOCK(hsram);
532
533 return HAL_OK;
534 }
535
536 /**
537 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
538 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
539 * the configuration information for SRAM module.
540 * @param pAddress Pointer to write start address
541 * @param pSrcBuffer Pointer to source buffer to write
542 * @param BufferSize Size of the buffer to write to memory
543 * @retval HAL status
544 */
545 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
546 {
547 /* Check the SRAM controller state */
548 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
549 {
550 return HAL_ERROR;
551 }
552
553 /* Process Locked */
554 __HAL_LOCK(hsram);
555
556 /* Update the SRAM controller state */
557 hsram->State = HAL_SRAM_STATE_BUSY;
558
559 /* Configure DMA user callbacks */
560 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
561 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
562
563 /* Enable the DMA Stream */
564 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
565
566 /* Update the SRAM controller state */
567 hsram->State = HAL_SRAM_STATE_READY;
568
569 /* Process unlocked */
570 __HAL_UNLOCK(hsram);
571
572 return HAL_OK;
573 }
574
575 /**
576 * @}
577 */
578
579 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
580 * @brief management functions
581 *
582 @verbatim
583 ==============================================================================
584 ##### SRAM Control functions #####
585 ==============================================================================
586 [..]
587 This subsection provides a set of functions allowing to control dynamically
588 the SRAM interface.
589
590 @endverbatim
591 * @{
592 */
593
594 /**
595 * @brief Enables dynamically SRAM write operation.
596 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
597 * the configuration information for SRAM module.
598 * @retval HAL status
599 */
600 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
601 {
602 /* Process Locked */
603 __HAL_LOCK(hsram);
604
605 /* Enable write operation */
606 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
607
608 /* Update the SRAM controller state */
609 hsram->State = HAL_SRAM_STATE_READY;
610
611 /* Process unlocked */
612 __HAL_UNLOCK(hsram);
613
614 return HAL_OK;
615 }
616
617 /**
618 * @brief Disables dynamically SRAM write operation.
619 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
620 * the configuration information for SRAM module.
621 * @retval HAL status
622 */
623 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
624 {
625 /* Process Locked */
626 __HAL_LOCK(hsram);
627
628 /* Update the SRAM controller state */
629 hsram->State = HAL_SRAM_STATE_BUSY;
630
631 /* Disable write operation */
632 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
633
634 /* Update the SRAM controller state */
635 hsram->State = HAL_SRAM_STATE_PROTECTED;
636
637 /* Process unlocked */
638 __HAL_UNLOCK(hsram);
639
640 return HAL_OK;
641 }
642
643 /**
644 * @}
645 */
646
647 /** @defgroup SRAM_Exported_Functions_Group4 State functions
648 * @brief Peripheral State functions
649 *
650 @verbatim
651 ==============================================================================
652 ##### SRAM State functions #####
653 ==============================================================================
654 [..]
655 This subsection permits to get in run-time the status of the SRAM controller
656 and the data flow.
657
658 @endverbatim
659 * @{
660 */
661
662 /**
663 * @brief Returns the SRAM controller state
664 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
665 * the configuration information for SRAM module.
666 * @retval HAL state
667 */
668 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
669 {
670 return hsram->State;
671 }
672 /**
673 * @}
674 */
675
676 /**
677 * @}
678 */
679 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
680 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
681 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
682 #endif /* HAL_SRAM_MODULE_ENABLED */
683 /**
684 * @}
685 */
686
687 /**
688 * @}
689 */
690
691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/