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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_sdram.c
4 * @author MCD Application Team
5 * @brief SDRAM HAL module driver.
6 * This file provides a generic firmware to drive SDRAM memories mounted
7 * as external device.
8 *
9 @verbatim
10 ==============================================================================
11 ##### How to use this driver #####
12 ==============================================================================
13 [..]
14 This driver is a generic layered driver which contains a set of APIs used to
15 control SDRAM memories. It uses the FMC layer functions to interface
16 with SDRAM devices.
17 The following sequence should be followed to configure the FMC to interface
18 with SDRAM memories:
19
20 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
21 SDRAM_HandleTypeDef hdsram
22
23 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
24 values of the structure member.
25
26 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
27 base register instance for NOR or SDRAM device
28
29 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
30 FMC_SDRAM_TimingTypeDef Timing;
31 and fill its fields with the allowed values of the structure member.
32
33 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
34 performs the following sequence:
35
36 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
37 (##) Control register configuration using the FMC SDRAM interface function
38 FMC_SDRAM_Init()
39 (##) Timing register configuration using the FMC SDRAM interface function
40 FMC_SDRAM_Timing_Init()
41 (##) Program the SDRAM external device by applying its initialization sequence
42 according to the device plugged in your hardware. This step is mandatory
43 for accessing the SDRAM device.
44
45 (#) At this stage you can perform read/write accesses from/to the memory connected
46 to the SDRAM Bank. You can perform either polling or DMA transfer using the
47 following APIs:
48 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
49 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
50
51 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
52 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
53 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
54 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
55 structure.
56
57 (#) You can continuously monitor the SDRAM device HAL state by calling the function
58 HAL_SDRAM_GetState()
59
60 @endverbatim
61 ******************************************************************************
62 * @attention
63 *
64 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
65 *
66 * Redistribution and use in source and binary forms, with or without modification,
67 * are permitted provided that the following conditions are met:
68 * 1. Redistributions of source code must retain the above copyright notice,
69 * this list of conditions and the following disclaimer.
70 * 2. Redistributions in binary form must reproduce the above copyright notice,
71 * this list of conditions and the following disclaimer in the documentation
72 * and/or other materials provided with the distribution.
73 * 3. Neither the name of STMicroelectronics nor the names of its contributors
74 * may be used to endorse or promote products derived from this software
75 * without specific prior written permission.
76 *
77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
78 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
79 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
80 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
81 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
82 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
83 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
84 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
85 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
86 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
87 *
88 ******************************************************************************
89 */
90
91 /* Includes ------------------------------------------------------------------*/
92 #include "stm32f4xx_hal.h"
93
94 /** @addtogroup STM32F4xx_HAL_Driver
95 * @{
96 */
97
98 /** @defgroup SDRAM SDRAM
99 * @brief SDRAM driver modules
100 * @{
101 */
102 #ifdef HAL_SDRAM_MODULE_ENABLED
103 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
104 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
105
106 /* Private typedef -----------------------------------------------------------*/
107 /* Private define ------------------------------------------------------------*/
108 /* Private macro -------------------------------------------------------------*/
109 /* Private variables ---------------------------------------------------------*/
110 /* Private functions ---------------------------------------------------------*/
111 /* Exported functions --------------------------------------------------------*/
112 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
113 * @{
114 */
115
116 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
117 * @brief Initialization and Configuration functions
118 *
119 @verbatim
120 ==============================================================================
121 ##### SDRAM Initialization and de_initialization functions #####
122 ==============================================================================
123 [..]
124 This section provides functions allowing to initialize/de-initialize
125 the SDRAM memory
126
127 @endverbatim
128 * @{
129 */
130
131 /**
132 * @brief Performs the SDRAM device initialization sequence.
133 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
134 * the configuration information for SDRAM module.
135 * @param Timing Pointer to SDRAM control timing structure
136 * @retval HAL status
137 */
138 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
139 {
140 /* Check the SDRAM handle parameter */
141 if(hsdram == NULL)
142 {
143 return HAL_ERROR;
144 }
145
146 if(hsdram->State == HAL_SDRAM_STATE_RESET)
147 {
148 /* Allocate lock resource and initialize it */
149 hsdram->Lock = HAL_UNLOCKED;
150 /* Initialize the low level hardware (MSP) */
151 HAL_SDRAM_MspInit(hsdram);
152 }
153
154 /* Initialize the SDRAM controller state */
155 hsdram->State = HAL_SDRAM_STATE_BUSY;
156
157 /* Initialize SDRAM control Interface */
158 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
159
160 /* Initialize SDRAM timing Interface */
161 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
162
163 /* Update the SDRAM controller state */
164 hsdram->State = HAL_SDRAM_STATE_READY;
165
166 return HAL_OK;
167 }
168
169 /**
170 * @brief Perform the SDRAM device initialization sequence.
171 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
172 * the configuration information for SDRAM module.
173 * @retval HAL status
174 */
175 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
176 {
177 /* Initialize the low level hardware (MSP) */
178 HAL_SDRAM_MspDeInit(hsdram);
179
180 /* Configure the SDRAM registers with their reset values */
181 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
182
183 /* Reset the SDRAM controller state */
184 hsdram->State = HAL_SDRAM_STATE_RESET;
185
186 /* Release Lock */
187 __HAL_UNLOCK(hsdram);
188
189 return HAL_OK;
190 }
191
192 /**
193 * @brief SDRAM MSP Init.
194 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
195 * the configuration information for SDRAM module.
196 * @retval None
197 */
198 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
199 {
200 /* Prevent unused argument(s) compilation warning */
201 UNUSED(hsdram);
202 /* NOTE: This function Should not be modified, when the callback is needed,
203 the HAL_SDRAM_MspInit could be implemented in the user file
204 */
205 }
206
207 /**
208 * @brief SDRAM MSP DeInit.
209 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
210 * the configuration information for SDRAM module.
211 * @retval None
212 */
213 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
214 {
215 /* Prevent unused argument(s) compilation warning */
216 UNUSED(hsdram);
217 /* NOTE: This function Should not be modified, when the callback is needed,
218 the HAL_SDRAM_MspDeInit could be implemented in the user file
219 */
220 }
221
222 /**
223 * @brief This function handles SDRAM refresh error interrupt request.
224 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
225 * the configuration information for SDRAM module.
226 * @retval HAL status
227 */
228 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
229 {
230 /* Check SDRAM interrupt Rising edge flag */
231 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
232 {
233 /* SDRAM refresh error interrupt callback */
234 HAL_SDRAM_RefreshErrorCallback(hsdram);
235
236 /* Clear SDRAM refresh error interrupt pending bit */
237 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
238 }
239 }
240
241 /**
242 * @brief SDRAM Refresh error callback.
243 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
244 * the configuration information for SDRAM module.
245 * @retval None
246 */
247 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
248 {
249 /* Prevent unused argument(s) compilation warning */
250 UNUSED(hsdram);
251 /* NOTE: This function Should not be modified, when the callback is needed,
252 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
253 */
254 }
255
256 /**
257 * @brief DMA transfer complete callback.
258 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
259 * the configuration information for the specified DMA module.
260 * @retval None
261 */
262 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
263 {
264 /* Prevent unused argument(s) compilation warning */
265 UNUSED(hdma);
266 /* NOTE: This function Should not be modified, when the callback is needed,
267 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
268 */
269 }
270
271 /**
272 * @brief DMA transfer complete error callback.
273 * @param hdma DMA handle
274 * @retval None
275 */
276 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
277 {
278 /* Prevent unused argument(s) compilation warning */
279 UNUSED(hdma);
280 /* NOTE: This function Should not be modified, when the callback is needed,
281 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
282 */
283 }
284 /**
285 * @}
286 */
287
288 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
289 * @brief Input Output and memory control functions
290 *
291 @verbatim
292 ==============================================================================
293 ##### SDRAM Input and Output functions #####
294 ==============================================================================
295 [..]
296 This section provides functions allowing to use and control the SDRAM memory
297
298 @endverbatim
299 * @{
300 */
301
302 /**
303 * @brief Reads 8-bit data buffer from the SDRAM memory.
304 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
305 * the configuration information for SDRAM module.
306 * @param pAddress Pointer to read start address
307 * @param pDstBuffer Pointer to destination buffer
308 * @param BufferSize Size of the buffer to read from memory
309 * @retval HAL status
310 */
311 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
312 {
313 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
314
315 /* Process Locked */
316 __HAL_LOCK(hsdram);
317
318 /* Check the SDRAM controller state */
319 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
320 {
321 return HAL_BUSY;
322 }
323 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
324 {
325 return HAL_ERROR;
326 }
327
328 /* Read data from source */
329 for(; BufferSize != 0U; BufferSize--)
330 {
331 *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
332 pDstBuffer++;
333 pSdramAddress++;
334 }
335
336 /* Process Unlocked */
337 __HAL_UNLOCK(hsdram);
338
339 return HAL_OK;
340 }
341
342 /**
343 * @brief Writes 8-bit data buffer to SDRAM memory.
344 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
345 * the configuration information for SDRAM module.
346 * @param pAddress Pointer to write start address
347 * @param pSrcBuffer Pointer to source buffer to write
348 * @param BufferSize Size of the buffer to write to memory
349 * @retval HAL status
350 */
351 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
352 {
353 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
354 uint32_t tmp = 0U;
355
356 /* Process Locked */
357 __HAL_LOCK(hsdram);
358
359 /* Check the SDRAM controller state */
360 tmp = hsdram->State;
361
362 if(tmp == HAL_SDRAM_STATE_BUSY)
363 {
364 return HAL_BUSY;
365 }
366 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
367 {
368 return HAL_ERROR;
369 }
370
371 /* Write data to memory */
372 for(; BufferSize != 0U; BufferSize--)
373 {
374 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
375 pSrcBuffer++;
376 pSdramAddress++;
377 }
378
379 /* Process Unlocked */
380 __HAL_UNLOCK(hsdram);
381
382 return HAL_OK;
383 }
384
385 /**
386 * @brief Reads 16-bit data buffer from the SDRAM memory.
387 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
388 * the configuration information for SDRAM module.
389 * @param pAddress Pointer to read start address
390 * @param pDstBuffer Pointer to destination buffer
391 * @param BufferSize Size of the buffer to read from memory
392 * @retval HAL status
393 */
394 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
395 {
396 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
397
398 /* Process Locked */
399 __HAL_LOCK(hsdram);
400
401 /* Check the SDRAM controller state */
402 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
403 {
404 return HAL_BUSY;
405 }
406 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
407 {
408 return HAL_ERROR;
409 }
410
411 /* Read data from source */
412 for(; BufferSize != 0U; BufferSize--)
413 {
414 *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
415 pDstBuffer++;
416 pSdramAddress++;
417 }
418
419 /* Process Unlocked */
420 __HAL_UNLOCK(hsdram);
421
422 return HAL_OK;
423 }
424
425 /**
426 * @brief Writes 16-bit data buffer to SDRAM memory.
427 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
428 * the configuration information for SDRAM module.
429 * @param pAddress Pointer to write start address
430 * @param pSrcBuffer Pointer to source buffer to write
431 * @param BufferSize Size of the buffer to write to memory
432 * @retval HAL status
433 */
434 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
435 {
436 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
437 uint32_t tmp = 0U;
438
439 /* Process Locked */
440 __HAL_LOCK(hsdram);
441
442 /* Check the SDRAM controller state */
443 tmp = hsdram->State;
444
445 if(tmp == HAL_SDRAM_STATE_BUSY)
446 {
447 return HAL_BUSY;
448 }
449 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
450 {
451 return HAL_ERROR;
452 }
453
454 /* Write data to memory */
455 for(; BufferSize != 0U; BufferSize--)
456 {
457 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
458 pSrcBuffer++;
459 pSdramAddress++;
460 }
461
462 /* Process Unlocked */
463 __HAL_UNLOCK(hsdram);
464
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Reads 32-bit data buffer from the SDRAM memory.
470 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
471 * the configuration information for SDRAM module.
472 * @param pAddress Pointer to read start address
473 * @param pDstBuffer Pointer to destination buffer
474 * @param BufferSize Size of the buffer to read from memory
475 * @retval HAL status
476 */
477 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
478 {
479 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
480
481 /* Process Locked */
482 __HAL_LOCK(hsdram);
483
484 /* Check the SDRAM controller state */
485 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
486 {
487 return HAL_BUSY;
488 }
489 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
490 {
491 return HAL_ERROR;
492 }
493
494 /* Read data from source */
495 for(; BufferSize != 0U; BufferSize--)
496 {
497 *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
498 pDstBuffer++;
499 pSdramAddress++;
500 }
501
502 /* Process Unlocked */
503 __HAL_UNLOCK(hsdram);
504
505 return HAL_OK;
506 }
507
508 /**
509 * @brief Writes 32-bit data buffer to SDRAM memory.
510 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
511 * the configuration information for SDRAM module.
512 * @param pAddress Pointer to write start address
513 * @param pSrcBuffer Pointer to source buffer to write
514 * @param BufferSize Size of the buffer to write to memory
515 * @retval HAL status
516 */
517 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
518 {
519 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
520 uint32_t tmp = 0U;
521
522 /* Process Locked */
523 __HAL_LOCK(hsdram);
524
525 /* Check the SDRAM controller state */
526 tmp = hsdram->State;
527
528 if(tmp == HAL_SDRAM_STATE_BUSY)
529 {
530 return HAL_BUSY;
531 }
532 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
533 {
534 return HAL_ERROR;
535 }
536
537 /* Write data to memory */
538 for(; BufferSize != 0U; BufferSize--)
539 {
540 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
541 pSrcBuffer++;
542 pSdramAddress++;
543 }
544
545 /* Process Unlocked */
546 __HAL_UNLOCK(hsdram);
547
548 return HAL_OK;
549 }
550
551 /**
552 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
553 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
554 * the configuration information for SDRAM module.
555 * @param pAddress Pointer to read start address
556 * @param pDstBuffer Pointer to destination buffer
557 * @param BufferSize Size of the buffer to read from memory
558 * @retval HAL status
559 */
560 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
561 {
562 uint32_t tmp = 0U;
563
564 /* Process Locked */
565 __HAL_LOCK(hsdram);
566
567 /* Check the SDRAM controller state */
568 tmp = hsdram->State;
569
570 if(tmp == HAL_SDRAM_STATE_BUSY)
571 {
572 return HAL_BUSY;
573 }
574 else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
575 {
576 return HAL_ERROR;
577 }
578
579 /* Configure DMA user callbacks */
580 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
581 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
582
583 /* Enable the DMA Stream */
584 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
585
586 /* Process Unlocked */
587 __HAL_UNLOCK(hsdram);
588
589 return HAL_OK;
590 }
591
592 /**
593 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
594 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
595 * the configuration information for SDRAM module.
596 * @param pAddress Pointer to write start address
597 * @param pSrcBuffer Pointer to source buffer to write
598 * @param BufferSize Size of the buffer to write to memory
599 * @retval HAL status
600 */
601 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
602 {
603 uint32_t tmp = 0U;
604
605 /* Process Locked */
606 __HAL_LOCK(hsdram);
607
608 /* Check the SDRAM controller state */
609 tmp = hsdram->State;
610
611 if(tmp == HAL_SDRAM_STATE_BUSY)
612 {
613 return HAL_BUSY;
614 }
615 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
616 {
617 return HAL_ERROR;
618 }
619
620 /* Configure DMA user callbacks */
621 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
622 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
623
624 /* Enable the DMA Stream */
625 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
626
627 /* Process Unlocked */
628 __HAL_UNLOCK(hsdram);
629
630 return HAL_OK;
631 }
632 /**
633 * @}
634 */
635
636 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
637 * @brief management functions
638 *
639 @verbatim
640 ==============================================================================
641 ##### SDRAM Control functions #####
642 ==============================================================================
643 [..]
644 This subsection provides a set of functions allowing to control dynamically
645 the SDRAM interface.
646
647 @endverbatim
648 * @{
649 */
650
651 /**
652 * @brief Enables dynamically SDRAM write protection.
653 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
654 * the configuration information for SDRAM module.
655 * @retval HAL status
656 */
657 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
658 {
659 /* Check the SDRAM controller state */
660 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
661 {
662 return HAL_BUSY;
663 }
664
665 /* Update the SDRAM state */
666 hsdram->State = HAL_SDRAM_STATE_BUSY;
667
668 /* Enable write protection */
669 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
670
671 /* Update the SDRAM state */
672 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
673
674 return HAL_OK;
675 }
676
677 /**
678 * @brief Disables dynamically SDRAM write protection.
679 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
680 * the configuration information for SDRAM module.
681 * @retval HAL status
682 */
683 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
684 {
685 /* Check the SDRAM controller state */
686 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
687 {
688 return HAL_BUSY;
689 }
690
691 /* Update the SDRAM state */
692 hsdram->State = HAL_SDRAM_STATE_BUSY;
693
694 /* Disable write protection */
695 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
696
697 /* Update the SDRAM state */
698 hsdram->State = HAL_SDRAM_STATE_READY;
699
700 return HAL_OK;
701 }
702
703 /**
704 * @brief Sends Command to the SDRAM bank.
705 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
706 * the configuration information for SDRAM module.
707 * @param Command SDRAM command structure
708 * @param Timeout Timeout duration
709 * @retval HAL status
710 */
711 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
712 {
713 /* Check the SDRAM controller state */
714 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
715 {
716 return HAL_BUSY;
717 }
718
719 /* Update the SDRAM state */
720 hsdram->State = HAL_SDRAM_STATE_BUSY;
721
722 /* Send SDRAM command */
723 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
724
725 /* Update the SDRAM controller state */
726 if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
727 {
728 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
729 }
730 else
731 {
732 hsdram->State = HAL_SDRAM_STATE_READY;
733 }
734
735 return HAL_OK;
736 }
737
738 /**
739 * @brief Programs the SDRAM Memory Refresh rate.
740 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
741 * the configuration information for SDRAM module.
742 * @param RefreshRate The SDRAM refresh rate value
743 * @retval HAL status
744 */
745 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
746 {
747 /* Check the SDRAM controller state */
748 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
749 {
750 return HAL_BUSY;
751 }
752
753 /* Update the SDRAM state */
754 hsdram->State = HAL_SDRAM_STATE_BUSY;
755
756 /* Program the refresh rate */
757 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
758
759 /* Update the SDRAM state */
760 hsdram->State = HAL_SDRAM_STATE_READY;
761
762 return HAL_OK;
763 }
764
765 /**
766 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
767 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
768 * the configuration information for SDRAM module.
769 * @param AutoRefreshNumber The SDRAM auto Refresh number
770 * @retval HAL status
771 */
772 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
773 {
774 /* Check the SDRAM controller state */
775 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
776 {
777 return HAL_BUSY;
778 }
779
780 /* Update the SDRAM state */
781 hsdram->State = HAL_SDRAM_STATE_BUSY;
782
783 /* Set the Auto-Refresh number */
784 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
785
786 /* Update the SDRAM state */
787 hsdram->State = HAL_SDRAM_STATE_READY;
788
789 return HAL_OK;
790 }
791
792 /**
793 * @brief Returns the SDRAM memory current mode.
794 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
795 * the configuration information for SDRAM module.
796 * @retval The SDRAM memory mode.
797 */
798 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
799 {
800 /* Return the SDRAM memory current mode */
801 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
802 }
803
804 /**
805 * @}
806 */
807
808 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
809 * @brief Peripheral State functions
810 *
811 @verbatim
812 ==============================================================================
813 ##### SDRAM State functions #####
814 ==============================================================================
815 [..]
816 This subsection permits to get in run-time the status of the SDRAM controller
817 and the data flow.
818
819 @endverbatim
820 * @{
821 */
822
823 /**
824 * @brief Returns the SDRAM state.
825 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
826 * the configuration information for SDRAM module.
827 * @retval HAL state
828 */
829 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
830 {
831 return hsdram->State;
832 }
833
834 /**
835 * @}
836 */
837
838 /**
839 * @}
840 */
841 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
842 #endif /* HAL_SDRAM_MODULE_ENABLED */
843 /**
844 * @}
845 */
846
847 /**
848 * @}
849 */
850
851 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/