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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_nor.c
4 * @author MCD Application Team
5 * @brief NOR HAL module driver.
6 * This file provides a generic firmware to drive NOR memories mounted
7 * as external device.
8 *
9 @verbatim
10 ==============================================================================
11 ##### How to use this driver #####
12 ==============================================================================
13 [..]
14 This driver is a generic layered driver which contains a set of APIs used to
15 control NOR flash memories. It uses the FMC/FSMC layer functions to interface
16 with NOR devices. This driver is used as follows:
17
18 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
19 with control and timing parameters for both normal and extended mode.
20
21 (+) Read NOR flash memory manufacturer code and device IDs using the function
22 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
23 structure declared by the function caller.
24
25 (+) Access NOR flash memory by read/write data unit operations using the functions
26 HAL_NOR_Read(), HAL_NOR_Program().
27
28 (+) Perform NOR flash erase block/chip operations using the functions
29 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
30
31 (+) Read the NOR flash CFI (common flash interface) IDs using the function
32 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
33 structure declared by the function caller.
34
35 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
36 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
37
38 (+) You can monitor the NOR device HAL state by calling the function
39 HAL_NOR_GetState()
40 [..]
41 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
42 If a NOR flash device contains different operations and/or implementations,
43 it should be implemented separately.
44
45 *** NOR HAL driver macros list ***
46 =============================================
47 [..]
48 Below the list of most used macros in NOR HAL driver.
49
50 (+) NOR_WRITE : NOR memory write data to specified address
51
52 @endverbatim
53 ******************************************************************************
54 * @attention
55 *
56 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
57 *
58 * Redistribution and use in source and binary forms, with or without modification,
59 * are permitted provided that the following conditions are met:
60 * 1. Redistributions of source code must retain the above copyright notice,
61 * this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright notice,
63 * this list of conditions and the following disclaimer in the documentation
64 * and/or other materials provided with the distribution.
65 * 3. Neither the name of STMicroelectronics nor the names of its contributors
66 * may be used to endorse or promote products derived from this software
67 * without specific prior written permission.
68 *
69 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
70 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
72 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
73 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
74 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
75 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
76 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
77 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
78 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
79 *
80 ******************************************************************************
81 */
82
83 /* Includes ------------------------------------------------------------------*/
84 #include "stm32f4xx_hal.h"
85
86 /** @addtogroup STM32F4xx_HAL_Driver
87 * @{
88 */
89
90 /** @defgroup NOR NOR
91 * @brief NOR driver modules
92 * @{
93 */
94 #ifdef HAL_NOR_MODULE_ENABLED
95 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
96 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
97 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
98 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
99 /* Private typedef -----------------------------------------------------------*/
100 /* Private define ------------------------------------------------------------*/
101
102 /** @defgroup NOR_Private_Defines NOR Private Defines
103 * @{
104 */
105
106 /* Constants to define address to set to write a command */
107 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
108 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
109 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
110 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
111 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
112 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
113 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
114
115 /* Constants to define data to program a command */
116 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
117 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
118 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
119 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
120 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
123 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
124 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
125 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
126
127 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
128 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
129 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
130
131 /* Mask on NOR STATUS REGISTER */
132 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
133 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
134
135 /**
136 * @}
137 */
138
139 /* Private macro -------------------------------------------------------------*/
140 /* Private variables ---------------------------------------------------------*/
141 /** @defgroup NOR_Private_Variables NOR Private Variables
142 * @{
143 */
144
145 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
146
147 /**
148 * @}
149 */
150
151 /* Private functions ---------------------------------------------------------*/
152 /* Exported functions --------------------------------------------------------*/
153 /** @defgroup NOR_Exported_Functions NOR Exported Functions
154 * @{
155 */
156
157 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
158 * @brief Initialization and Configuration functions
159 *
160 @verbatim
161 ==============================================================================
162 ##### NOR Initialization and de_initialization functions #####
163 ==============================================================================
164 [..]
165 This section provides functions allowing to initialize/de-initialize
166 the NOR memory
167
168 @endverbatim
169 * @{
170 */
171
172 /**
173 * @brief Perform the NOR memory Initialization sequence
174 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
175 * the configuration information for NOR module.
176 * @param Timing pointer to NOR control timing structure
177 * @param ExtTiming pointer to NOR extended mode timing structure
178 * @retval HAL status
179 */
180 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
181 {
182 /* Check the NOR handle parameter */
183 if(hnor == NULL)
184 {
185 return HAL_ERROR;
186 }
187
188 if(hnor->State == HAL_NOR_STATE_RESET)
189 {
190 /* Allocate lock resource and initialize it */
191 hnor->Lock = HAL_UNLOCKED;
192 /* Initialize the low level hardware (MSP) */
193 HAL_NOR_MspInit(hnor);
194 }
195
196 /* Initialize NOR control Interface */
197 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
198
199 /* Initialize NOR timing Interface */
200 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
201
202 /* Initialize NOR extended mode timing Interface */
203 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
204
205 /* Enable the NORSRAM device */
206 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
207
208 /* Initialize NOR Memory Data Width*/
209 if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
210 {
211 uwNORMemoryDataWidth = NOR_MEMORY_8B;
212 }
213 else
214 {
215 uwNORMemoryDataWidth = NOR_MEMORY_16B;
216 }
217
218 /* Check the NOR controller state */
219 hnor->State = HAL_NOR_STATE_READY;
220
221 return HAL_OK;
222 }
223
224 /**
225 * @brief Perform NOR memory De-Initialization sequence
226 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
227 * the configuration information for NOR module.
228 * @retval HAL status
229 */
230 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
231 {
232 /* De-Initialize the low level hardware (MSP) */
233 HAL_NOR_MspDeInit(hnor);
234
235 /* Configure the NOR registers with their reset values */
236 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
237
238 /* Update the NOR controller state */
239 hnor->State = HAL_NOR_STATE_RESET;
240
241 /* Release Lock */
242 __HAL_UNLOCK(hnor);
243
244 return HAL_OK;
245 }
246
247 /**
248 * @brief NOR MSP Init
249 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
250 * the configuration information for NOR module.
251 * @retval None
252 */
253 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
254 {
255 /* Prevent unused argument(s) compilation warning */
256 UNUSED(hnor);
257 /* NOTE : This function Should not be modified, when the callback is needed,
258 the HAL_NOR_MspInit could be implemented in the user file
259 */
260 }
261
262 /**
263 * @brief NOR MSP DeInit
264 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
265 * the configuration information for NOR module.
266 * @retval None
267 */
268 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
269 {
270 /* Prevent unused argument(s) compilation warning */
271 UNUSED(hnor);
272 /* NOTE : This function Should not be modified, when the callback is needed,
273 the HAL_NOR_MspDeInit could be implemented in the user file
274 */
275 }
276
277 /**
278 * @brief NOR MSP Wait for Ready/Busy signal
279 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
280 * the configuration information for NOR module.
281 * @param Timeout Maximum timeout value
282 * @retval None
283 */
284 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
285 {
286 /* Prevent unused argument(s) compilation warning */
287 UNUSED(hnor);
288 UNUSED(Timeout);
289
290 /* NOTE : This function Should not be modified, when the callback is needed,
291 the HAL_NOR_MspWait could be implemented in the user file
292 */
293 }
294
295 /**
296 * @}
297 */
298
299 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
300 * @brief Input Output and memory control functions
301 *
302 @verbatim
303 ==============================================================================
304 ##### NOR Input and Output functions #####
305 ==============================================================================
306 [..]
307 This section provides functions allowing to use and control the NOR memory
308
309 @endverbatim
310 * @{
311 */
312
313 /**
314 * @brief Read NOR flash IDs
315 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
316 * the configuration information for NOR module.
317 * @param pNOR_ID pointer to NOR ID structure
318 * @retval HAL status
319 */
320 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
321 {
322 uint32_t deviceaddress = 0U;
323
324 /* Process Locked */
325 __HAL_LOCK(hnor);
326
327 /* Check the NOR controller state */
328 if(hnor->State == HAL_NOR_STATE_BUSY)
329 {
330 return HAL_BUSY;
331 }
332
333 /* Select the NOR device address */
334 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
335 {
336 deviceaddress = NOR_MEMORY_ADRESS1;
337 }
338 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
339 {
340 deviceaddress = NOR_MEMORY_ADRESS2;
341 }
342 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
343 {
344 deviceaddress = NOR_MEMORY_ADRESS3;
345 }
346 else /* FMC_NORSRAM_BANK4 */
347 {
348 deviceaddress = NOR_MEMORY_ADRESS4;
349 }
350
351 /* Update the NOR controller state */
352 hnor->State = HAL_NOR_STATE_BUSY;
353
354 /* Send read ID command */
355 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
356 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
357 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
358
359 /* Read the NOR IDs */
360 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
361 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
362 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
363 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
364
365 /* Check the NOR controller state */
366 hnor->State = HAL_NOR_STATE_READY;
367
368 /* Process unlocked */
369 __HAL_UNLOCK(hnor);
370
371 return HAL_OK;
372 }
373
374 /**
375 * @brief Returns the NOR memory to Read mode.
376 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
377 * the configuration information for NOR module.
378 * @retval HAL status
379 */
380 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
381 {
382 uint32_t deviceaddress = 0U;
383
384 /* Process Locked */
385 __HAL_LOCK(hnor);
386
387 /* Check the NOR controller state */
388 if(hnor->State == HAL_NOR_STATE_BUSY)
389 {
390 return HAL_BUSY;
391 }
392
393 /* Select the NOR device address */
394 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
395 {
396 deviceaddress = NOR_MEMORY_ADRESS1;
397 }
398 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
399 {
400 deviceaddress = NOR_MEMORY_ADRESS2;
401 }
402 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
403 {
404 deviceaddress = NOR_MEMORY_ADRESS3;
405 }
406 else /* FMC_NORSRAM_BANK4 */
407 {
408 deviceaddress = NOR_MEMORY_ADRESS4;
409 }
410
411 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
412
413 /* Check the NOR controller state */
414 hnor->State = HAL_NOR_STATE_READY;
415
416 /* Process unlocked */
417 __HAL_UNLOCK(hnor);
418
419 return HAL_OK;
420 }
421
422 /**
423 * @brief Read data from NOR memory
424 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
425 * the configuration information for NOR module.
426 * @param pAddress pointer to Device address
427 * @param pData pointer to read data
428 * @retval HAL status
429 */
430 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
431 {
432 uint32_t deviceaddress = 0U;
433
434 /* Process Locked */
435 __HAL_LOCK(hnor);
436
437 /* Check the NOR controller state */
438 if(hnor->State == HAL_NOR_STATE_BUSY)
439 {
440 return HAL_BUSY;
441 }
442
443 /* Select the NOR device address */
444 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
445 {
446 deviceaddress = NOR_MEMORY_ADRESS1;
447 }
448 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
449 {
450 deviceaddress = NOR_MEMORY_ADRESS2;
451 }
452 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
453 {
454 deviceaddress = NOR_MEMORY_ADRESS3;
455 }
456 else /* FMC_NORSRAM_BANK4 */
457 {
458 deviceaddress = NOR_MEMORY_ADRESS4;
459 }
460
461 /* Update the NOR controller state */
462 hnor->State = HAL_NOR_STATE_BUSY;
463
464 /* Send read data command */
465 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
466 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
467 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
468
469 /* Read the data */
470 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
471
472 /* Check the NOR controller state */
473 hnor->State = HAL_NOR_STATE_READY;
474
475 /* Process unlocked */
476 __HAL_UNLOCK(hnor);
477
478 return HAL_OK;
479 }
480
481 /**
482 * @brief Program data to NOR memory
483 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
484 * the configuration information for NOR module.
485 * @param pAddress Device address
486 * @param pData pointer to the data to write
487 * @retval HAL status
488 */
489 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
490 {
491 uint32_t deviceaddress = 0U;
492
493 /* Process Locked */
494 __HAL_LOCK(hnor);
495
496 /* Check the NOR controller state */
497 if(hnor->State == HAL_NOR_STATE_BUSY)
498 {
499 return HAL_BUSY;
500 }
501
502 /* Select the NOR device address */
503 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
504 {
505 deviceaddress = NOR_MEMORY_ADRESS1;
506 }
507 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
508 {
509 deviceaddress = NOR_MEMORY_ADRESS2;
510 }
511 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
512 {
513 deviceaddress = NOR_MEMORY_ADRESS3;
514 }
515 else /* FMC_NORSRAM_BANK4 */
516 {
517 deviceaddress = NOR_MEMORY_ADRESS4;
518 }
519
520 /* Update the NOR controller state */
521 hnor->State = HAL_NOR_STATE_BUSY;
522
523 /* Send program data command */
524 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
525 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
526 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
527
528 /* Write the data */
529 NOR_WRITE(pAddress, *pData);
530
531 /* Check the NOR controller state */
532 hnor->State = HAL_NOR_STATE_READY;
533
534 /* Process unlocked */
535 __HAL_UNLOCK(hnor);
536
537 return HAL_OK;
538 }
539
540 /**
541 * @brief Reads a half-word buffer from the NOR memory.
542 * @param hnor pointer to the NOR handle
543 * @param uwAddress NOR memory internal address to read from.
544 * @param pData pointer to the buffer that receives the data read from the
545 * NOR memory.
546 * @param uwBufferSize number of Half word to read.
547 * @retval HAL status
548 */
549 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
550 {
551 uint32_t deviceaddress = 0U;
552
553 /* Process Locked */
554 __HAL_LOCK(hnor);
555
556 /* Check the NOR controller state */
557 if(hnor->State == HAL_NOR_STATE_BUSY)
558 {
559 return HAL_BUSY;
560 }
561
562 /* Select the NOR device address */
563 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
564 {
565 deviceaddress = NOR_MEMORY_ADRESS1;
566 }
567 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
568 {
569 deviceaddress = NOR_MEMORY_ADRESS2;
570 }
571 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
572 {
573 deviceaddress = NOR_MEMORY_ADRESS3;
574 }
575 else /* FMC_NORSRAM_BANK4 */
576 {
577 deviceaddress = NOR_MEMORY_ADRESS4;
578 }
579
580 /* Update the NOR controller state */
581 hnor->State = HAL_NOR_STATE_BUSY;
582
583 /* Send read data command */
584 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
585 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
586 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
587
588 /* Read buffer */
589 while( uwBufferSize > 0U)
590 {
591 *pData++ = *(__IO uint16_t *)uwAddress;
592 uwAddress += 2U;
593 uwBufferSize--;
594 }
595
596 /* Check the NOR controller state */
597 hnor->State = HAL_NOR_STATE_READY;
598
599 /* Process unlocked */
600 __HAL_UNLOCK(hnor);
601
602 return HAL_OK;
603 }
604
605 /**
606 * @brief Writes a half-word buffer to the NOR memory. This function must be used
607 only with S29GL128P NOR memory.
608 * @param hnor pointer to the NOR handle
609 * @param uwAddress NOR memory internal start write address
610 * @param pData pointer to source data buffer.
611 * @param uwBufferSize Size of the buffer to write
612 * @retval HAL status
613 */
614 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
615 {
616 uint16_t * p_currentaddress = (uint16_t *)NULL;
617 uint16_t * p_endaddress = (uint16_t *)NULL;
618 uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
619
620 /* Process Locked */
621 __HAL_LOCK(hnor);
622
623 /* Check the NOR controller state */
624 if(hnor->State == HAL_NOR_STATE_BUSY)
625 {
626 return HAL_BUSY;
627 }
628
629 /* Select the NOR device address */
630 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
631 {
632 deviceaddress = NOR_MEMORY_ADRESS1;
633 }
634 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
635 {
636 deviceaddress = NOR_MEMORY_ADRESS2;
637 }
638 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
639 {
640 deviceaddress = NOR_MEMORY_ADRESS3;
641 }
642 else /* FMC_NORSRAM_BANK4 */
643 {
644 deviceaddress = NOR_MEMORY_ADRESS4;
645 }
646
647 /* Update the NOR controller state */
648 hnor->State = HAL_NOR_STATE_BUSY;
649
650 /* Initialize variables */
651 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
652 p_endaddress = p_currentaddress + (uwBufferSize-1U);
653 lastloadedaddress = (uint32_t)(uwAddress);
654
655 /* Issue unlock command sequence */
656 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
657 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
658
659 /* Write Buffer Load Command */
660 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
661 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U));
662
663 /* Load Data into NOR Buffer */
664 while(p_currentaddress <= p_endaddress)
665 {
666 /* Store last loaded address & data value (for polling) */
667 lastloadedaddress = (uint32_t)p_currentaddress;
668
669 NOR_WRITE(p_currentaddress, *pData++);
670
671 p_currentaddress ++;
672 }
673
674 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
675
676 /* Check the NOR controller state */
677 hnor->State = HAL_NOR_STATE_READY;
678
679 /* Process unlocked */
680 __HAL_UNLOCK(hnor);
681
682 return HAL_OK;
683
684 }
685
686 /**
687 * @brief Erase the specified block of the NOR memory
688 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
689 * the configuration information for NOR module.
690 * @param BlockAddress Block to erase address
691 * @param Address Device address
692 * @retval HAL status
693 */
694 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
695 {
696 uint32_t deviceaddress = 0U;
697
698 /* Process Locked */
699 __HAL_LOCK(hnor);
700
701 /* Check the NOR controller state */
702 if(hnor->State == HAL_NOR_STATE_BUSY)
703 {
704 return HAL_BUSY;
705 }
706
707 /* Select the NOR device address */
708 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
709 {
710 deviceaddress = NOR_MEMORY_ADRESS1;
711 }
712 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
713 {
714 deviceaddress = NOR_MEMORY_ADRESS2;
715 }
716 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
717 {
718 deviceaddress = NOR_MEMORY_ADRESS3;
719 }
720 else /* FMC_NORSRAM_BANK4 */
721 {
722 deviceaddress = NOR_MEMORY_ADRESS4;
723 }
724
725 /* Update the NOR controller state */
726 hnor->State = HAL_NOR_STATE_BUSY;
727
728 /* Send block erase command sequence */
729 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
730 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
731 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
732 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
733 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
734 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
735
736 /* Check the NOR memory status and update the controller state */
737 hnor->State = HAL_NOR_STATE_READY;
738
739 /* Process unlocked */
740 __HAL_UNLOCK(hnor);
741
742 return HAL_OK;
743
744 }
745
746 /**
747 * @brief Erase the entire NOR chip.
748 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
749 * the configuration information for NOR module.
750 * @param Address Device address
751 * @retval HAL status
752 */
753 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
754 {
755 uint32_t deviceaddress = 0U;
756
757 /* Prevent unused argument(s) compilation warning */
758 UNUSED(Address);
759
760 /* Process Locked */
761 __HAL_LOCK(hnor);
762
763 /* Check the NOR controller state */
764 if(hnor->State == HAL_NOR_STATE_BUSY)
765 {
766 return HAL_BUSY;
767 }
768
769 /* Select the NOR device address */
770 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
771 {
772 deviceaddress = NOR_MEMORY_ADRESS1;
773 }
774 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
775 {
776 deviceaddress = NOR_MEMORY_ADRESS2;
777 }
778 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
779 {
780 deviceaddress = NOR_MEMORY_ADRESS3;
781 }
782 else /* FMC_NORSRAM_BANK4 */
783 {
784 deviceaddress = NOR_MEMORY_ADRESS4;
785 }
786
787 /* Update the NOR controller state */
788 hnor->State = HAL_NOR_STATE_BUSY;
789
790 /* Send NOR chip erase command sequence */
791 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
792 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
793 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
794 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
795 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
796 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
797
798 /* Check the NOR memory status and update the controller state */
799 hnor->State = HAL_NOR_STATE_READY;
800
801 /* Process unlocked */
802 __HAL_UNLOCK(hnor);
803
804 return HAL_OK;
805 }
806
807 /**
808 * @brief Read NOR flash CFI IDs
809 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
810 * the configuration information for NOR module.
811 * @param pNOR_CFI pointer to NOR CFI IDs structure
812 * @retval HAL status
813 */
814 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
815 {
816 uint32_t deviceaddress = 0U;
817
818 /* Process Locked */
819 __HAL_LOCK(hnor);
820
821 /* Check the NOR controller state */
822 if(hnor->State == HAL_NOR_STATE_BUSY)
823 {
824 return HAL_BUSY;
825 }
826
827 /* Select the NOR device address */
828 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
829 {
830 deviceaddress = NOR_MEMORY_ADRESS1;
831 }
832 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
833 {
834 deviceaddress = NOR_MEMORY_ADRESS2;
835 }
836 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
837 {
838 deviceaddress = NOR_MEMORY_ADRESS3;
839 }
840 else /* FMC_NORSRAM_BANK4 */
841 {
842 deviceaddress = NOR_MEMORY_ADRESS4;
843 }
844
845 /* Update the NOR controller state */
846 hnor->State = HAL_NOR_STATE_BUSY;
847
848 /* Send read CFI query command */
849 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
850
851 /* read the NOR CFI information */
852 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
853 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
854 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
855 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
856
857 /* Check the NOR controller state */
858 hnor->State = HAL_NOR_STATE_READY;
859
860 /* Process unlocked */
861 __HAL_UNLOCK(hnor);
862
863 return HAL_OK;
864 }
865
866 /**
867 * @}
868 */
869
870 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
871 * @brief management functions
872 *
873 @verbatim
874 ==============================================================================
875 ##### NOR Control functions #####
876 ==============================================================================
877 [..]
878 This subsection provides a set of functions allowing to control dynamically
879 the NOR interface.
880
881 @endverbatim
882 * @{
883 */
884
885 /**
886 * @brief Enables dynamically NOR write operation.
887 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
888 * the configuration information for NOR module.
889 * @retval HAL status
890 */
891 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
892 {
893 /* Process Locked */
894 __HAL_LOCK(hnor);
895
896 /* Enable write operation */
897 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
898
899 /* Update the NOR controller state */
900 hnor->State = HAL_NOR_STATE_READY;
901
902 /* Process unlocked */
903 __HAL_UNLOCK(hnor);
904
905 return HAL_OK;
906 }
907
908 /**
909 * @brief Disables dynamically NOR write operation.
910 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
911 * the configuration information for NOR module.
912 * @retval HAL status
913 */
914 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
915 {
916 /* Process Locked */
917 __HAL_LOCK(hnor);
918
919 /* Update the SRAM controller state */
920 hnor->State = HAL_NOR_STATE_BUSY;
921
922 /* Disable write operation */
923 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
924
925 /* Update the NOR controller state */
926 hnor->State = HAL_NOR_STATE_PROTECTED;
927
928 /* Process unlocked */
929 __HAL_UNLOCK(hnor);
930
931 return HAL_OK;
932 }
933
934 /**
935 * @}
936 */
937
938 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
939 * @brief Peripheral State functions
940 *
941 @verbatim
942 ==============================================================================
943 ##### NOR State functions #####
944 ==============================================================================
945 [..]
946 This subsection permits to get in run-time the status of the NOR controller
947 and the data flow.
948
949 @endverbatim
950 * @{
951 */
952
953 /**
954 * @brief return the NOR controller state
955 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
956 * the configuration information for NOR module.
957 * @retval NOR controller state
958 */
959 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
960 {
961 return hnor->State;
962 }
963
964 /**
965 * @brief Returns the NOR operation status.
966 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
967 * the configuration information for NOR module.
968 * @param Address Device address
969 * @param Timeout NOR programming Timeout
970 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
971 * or HAL_NOR_STATUS_TIMEOUT
972 */
973 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
974 {
975 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
976 uint16_t tmpSR1 = 0, tmpSR2 = 0;
977 uint32_t tickstart = 0U;
978
979 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
980 HAL_NOR_MspWait(hnor, Timeout);
981
982 /* Get the NOR memory operation status -------------------------------------*/
983
984 /* Get tick */
985 tickstart = HAL_GetTick();
986 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
987 {
988 /* Check for the Timeout */
989 if(Timeout != HAL_MAX_DELAY)
990 {
991 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
992 {
993 status = HAL_NOR_STATUS_TIMEOUT;
994 }
995 }
996
997 /* Read NOR status register (DQ6 and DQ5) */
998 tmpSR1 = *(__IO uint16_t *)Address;
999 tmpSR2 = *(__IO uint16_t *)Address;
1000
1001 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
1002 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
1003 {
1004 return HAL_NOR_STATUS_SUCCESS ;
1005 }
1006
1007 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
1008 {
1009 status = HAL_NOR_STATUS_ONGOING;
1010 }
1011
1012 tmpSR1 = *(__IO uint16_t *)Address;
1013 tmpSR2 = *(__IO uint16_t *)Address;
1014
1015 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
1016 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
1017 {
1018 return HAL_NOR_STATUS_SUCCESS;
1019 }
1020 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
1021 {
1022 return HAL_NOR_STATUS_ERROR;
1023 }
1024 }
1025
1026 /* Return the operation status */
1027 return status;
1028 }
1029
1030 /**
1031 * @}
1032 */
1033
1034 /**
1035 * @}
1036 */
1037 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
1038 STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
1039 STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx ||\
1040 STM32F423xx */
1041 #endif /* HAL_NOR_MODULE_ENABLED */
1042 /**
1043 * @}
1044 */
1045
1046 /**
1047 * @}
1048 */
1049
1050 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/