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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State, Mode and Error functions
11 *
12 @verbatim
13 ==============================================================================
14 ##### How to use this driver #####
15 ==============================================================================
16 [..]
17 The I2C HAL driver can be used as follows:
18
19 (#) Declare a I2C_HandleTypeDef handle structure, for example:
20 I2C_HandleTypeDef hi2c;
21
22 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
23 (##) Enable the I2Cx interface clock
24 (##) I2C pins configuration
25 (+++) Enable the clock for the I2C GPIOs
26 (+++) Configure I2C pins as alternate function open-drain
27 (##) NVIC configuration if you need to use interrupt process
28 (+++) Configure the I2Cx interrupt priority
29 (+++) Enable the NVIC I2C IRQ Channel
30 (##) DMA Configuration if you need to use DMA process
31 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
32 (+++) Enable the DMAx interface clock using
33 (+++) Configure the DMA handle parameters
34 (+++) Configure the DMA Tx or Rx Stream
35 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
36 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
37 the DMA Tx or Rx Stream
38
39 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
40 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
41
42 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
43 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
44
45 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
46
47 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
48
49 *** Polling mode IO operation ***
50 =================================
51 [..]
52 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
53 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
54 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
55 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
56
57 *** Polling mode IO MEM operation ***
58 =====================================
59 [..]
60 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
61 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
62
63
64 *** Interrupt mode IO operation ***
65 ===================================
66 [..]
67 (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
68 (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
69 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
70 (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
71 (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
72 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
73 (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
74 (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
75 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
76 (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
77 (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
78 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
79 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
80 add his own code by customization of function pointer HAL_I2C_ErrorCallback
81 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
82 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
83 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
84
85 *** Interrupt mode IO sequential operation ***
86 ==============================================
87 [..]
88 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
89 when a direction change during transfer
90 [..]
91 (+) A specific option field manage the different steps of a sequential transfer
92 (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
93 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
94 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
95 and data to transfer without a final stop condition
96 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
97 and with new data to transfer if the direction change or manage only the new data to transfer
98 if no direction change and without a final stop condition in both cases
99 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
100 and with new data to transfer if the direction change or manage only the new data to transfer
101 if no direction change and with a final stop condition in both cases
102
103 (+) Differents sequential I2C interfaces are listed below:
104 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
105 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
106 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
107 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
108 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
109 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
110 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
111 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
112 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
113 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
114 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
115 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
116 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
117 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
118 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
119 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
120 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
121 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
122 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
123 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
124 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
125 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
126 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
127 (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
128 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
129
130 *** Interrupt mode IO MEM operation ***
131 =======================================
132 [..]
133 (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
134 HAL_I2C_Mem_Write_IT()
135 (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
136 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
137 (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
138 HAL_I2C_Mem_Read_IT()
139 (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
140 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
141 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
142 add his own code by customization of function pointer HAL_I2C_ErrorCallback
143
144 *** DMA mode IO operation ***
145 ==============================
146 [..]
147 (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
148 HAL_I2C_Master_Transmit_DMA()
149 (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
150 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
151 (+) Receive in master mode an amount of data in non blocking mode (DMA) using
152 HAL_I2C_Master_Receive_DMA()
153 (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
154 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
155 (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
156 HAL_I2C_Slave_Transmit_DMA()
157 (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
158 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
159 (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
160 HAL_I2C_Slave_Receive_DMA()
161 (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
162 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
163 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
164 add his own code by customization of function pointer HAL_I2C_ErrorCallback
165 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
166 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
167 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
168
169 *** DMA mode IO MEM operation ***
170 =================================
171 [..]
172 (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
173 HAL_I2C_Mem_Write_DMA()
174 (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
175 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
176 (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
177 HAL_I2C_Mem_Read_DMA()
178 (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
179 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
180 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
181 add his own code by customization of function pointer HAL_I2C_ErrorCallback
182
183
184 *** I2C HAL driver macros list ***
185 ==================================
186 [..]
187 Below the list of most used macros in I2C HAL driver.
188
189 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
190 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
191 (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
192 (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
193 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
194 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
195
196 [..]
197 (@) You can refer to the I2C HAL driver header file for more useful macros
198
199
200 @endverbatim
201 ******************************************************************************
202 * @attention
203 *
204 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
205 *
206 * Redistribution and use in source and binary forms, with or without modification,
207 * are permitted provided that the following conditions are met:
208 * 1. Redistributions of source code must retain the above copyright notice,
209 * this list of conditions and the following disclaimer.
210 * 2. Redistributions in binary form must reproduce the above copyright notice,
211 * this list of conditions and the following disclaimer in the documentation
212 * and/or other materials provided with the distribution.
213 * 3. Neither the name of STMicroelectronics nor the names of its contributors
214 * may be used to endorse or promote products derived from this software
215 * without specific prior written permission.
216 *
217 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
218 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
219 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
220 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
221 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
222 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
223 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
224 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
225 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
226 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
227 *
228 ******************************************************************************
229 */
230
231 /* Includes ------------------------------------------------------------------*/
232 #include "stm32f4xx_hal.h"
233
234 /** @addtogroup STM32F4xx_HAL_Driver
235 * @{
236 */
237
238 /** @defgroup I2C I2C
239 * @brief I2C HAL module driver
240 * @{
241 */
242
243 #ifdef HAL_I2C_MODULE_ENABLED
244
245 /* Private typedef -----------------------------------------------------------*/
246 /* Private define ------------------------------------------------------------*/
247 /** @addtogroup I2C_Private_Define
248 * @{
249 */
250 #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
251 #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
252 #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
253
254 /* Private define for @ref PreviousState usage */
255 #define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
256 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
257 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
258 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
259 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
260 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
261
262 /**
263 * @}
264 */
265
266 /* Private macro -------------------------------------------------------------*/
267 /* Private variables ---------------------------------------------------------*/
268 /* Private function prototypes -----------------------------------------------*/
269 /** @addtogroup I2C_Private_Functions
270 * @{
271 */
272 /* Private functions to handle DMA transfer */
273 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
274 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
275 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
276
277 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
278
279 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
280 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
281 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
282 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
283 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
284 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
285 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
286 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
287 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
288 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
289 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
290
291 /* Private functions for I2C transfer IRQ handler */
292 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
293 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
294 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
295 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
296 static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
297 static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
298 static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
299
300 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
301 static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
302 static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
303 static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
304 static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
305 static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
306 static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
307 /**
308 * @}
309 */
310
311 /* Exported functions --------------------------------------------------------*/
312 /** @defgroup I2C_Exported_Functions I2C Exported Functions
313 * @{
314 */
315
316 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
317 * @brief Initialization and Configuration functions
318 *
319 @verbatim
320 ===============================================================================
321 ##### Initialization and de-initialization functions #####
322 ===============================================================================
323 [..] This subsection provides a set of functions allowing to initialize and
324 de-initialize the I2Cx peripheral:
325
326 (+) User must Implement HAL_I2C_MspInit() function in which he configures
327 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
328
329 (+) Call the function HAL_I2C_Init() to configure the selected device with
330 the selected configuration:
331 (++) Communication Speed
332 (++) Duty cycle
333 (++) Addressing mode
334 (++) Own Address 1
335 (++) Dual Addressing mode
336 (++) Own Address 2
337 (++) General call mode
338 (++) Nostretch mode
339
340 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
341 of the selected I2Cx peripheral.
342
343 @endverbatim
344 * @{
345 */
346
347 /**
348 * @brief Initializes the I2C according to the specified parameters
349 * in the I2C_InitTypeDef and create the associated handle.
350 * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
351 * the configuration information for I2C module
352 * @retval HAL status
353 */
354 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
355 {
356 uint32_t freqrange = 0U;
357 uint32_t pclk1 = 0U;
358
359 /* Check the I2C handle allocation */
360 if(hi2c == NULL)
361 {
362 return HAL_ERROR;
363 }
364
365 /* Check the parameters */
366 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
367 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
368 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
369 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
370 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
371 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
372 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
373 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
374 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
375
376 if(hi2c->State == HAL_I2C_STATE_RESET)
377 {
378 /* Allocate lock resource and initialize it */
379 hi2c->Lock = HAL_UNLOCKED;
380 /* Init the low level hardware : GPIO, CLOCK, NVIC */
381 HAL_I2C_MspInit(hi2c);
382 }
383
384 hi2c->State = HAL_I2C_STATE_BUSY;
385
386 /* Disable the selected I2C peripheral */
387 __HAL_I2C_DISABLE(hi2c);
388
389 /* Get PCLK1 frequency */
390 pclk1 = HAL_RCC_GetPCLK1Freq();
391
392 /* Calculate frequency range */
393 freqrange = I2C_FREQRANGE(pclk1);
394
395 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
396 /* Configure I2Cx: Frequency range */
397 hi2c->Instance->CR2 = freqrange;
398
399 /*---------------------------- I2Cx TRISE Configuration --------------------*/
400 /* Configure I2Cx: Rise Time */
401 hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
402
403 /*---------------------------- I2Cx CCR Configuration ----------------------*/
404 /* Configure I2Cx: Speed */
405 hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
406
407 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
408 /* Configure I2Cx: Generalcall and NoStretch mode */
409 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
410
411 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
412 /* Configure I2Cx: Own Address1 and addressing mode */
413 hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
414
415 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
416 /* Configure I2Cx: Dual mode and Own Address2 */
417 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
418
419 /* Enable the selected I2C peripheral */
420 __HAL_I2C_ENABLE(hi2c);
421
422 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
423 hi2c->State = HAL_I2C_STATE_READY;
424 hi2c->PreviousState = I2C_STATE_NONE;
425 hi2c->Mode = HAL_I2C_MODE_NONE;
426
427 return HAL_OK;
428 }
429
430 /**
431 * @brief DeInitializes the I2C peripheral.
432 * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
433 * the configuration information for I2C module
434 * @retval HAL status
435 */
436 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
437 {
438 /* Check the I2C handle allocation */
439 if(hi2c == NULL)
440 {
441 return HAL_ERROR;
442 }
443
444 /* Check the parameters */
445 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
446
447 hi2c->State = HAL_I2C_STATE_BUSY;
448
449 /* Disable the I2C Peripheral Clock */
450 __HAL_I2C_DISABLE(hi2c);
451
452 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
453 HAL_I2C_MspDeInit(hi2c);
454
455 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
456 hi2c->State = HAL_I2C_STATE_RESET;
457 hi2c->PreviousState = I2C_STATE_NONE;
458 hi2c->Mode = HAL_I2C_MODE_NONE;
459
460 /* Release Lock */
461 __HAL_UNLOCK(hi2c);
462
463 return HAL_OK;
464 }
465
466 /**
467 * @brief I2C MSP Init.
468 * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
469 * the configuration information for I2C module
470 * @retval None
471 */
472 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
473 {
474 /* Prevent unused argument(s) compilation warning */
475 UNUSED(hi2c);
476 /* NOTE : This function Should not be modified, when the callback is needed,
477 the HAL_I2C_MspInit could be implemented in the user file
478 */
479 }
480
481 /**
482 * @brief I2C MSP DeInit
483 * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
484 * the configuration information for I2C module
485 * @retval None
486 */
487 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
488 {
489 /* Prevent unused argument(s) compilation warning */
490 UNUSED(hi2c);
491 /* NOTE : This function Should not be modified, when the callback is needed,
492 the HAL_I2C_MspDeInit could be implemented in the user file
493 */
494 }
495
496 /**
497 * @}
498 */
499
500 /** @defgroup I2C_Exported_Functions_Group2 IO operation functions
501 * @brief Data transfers functions
502 *
503 @verbatim
504 ===============================================================================
505 ##### IO operation functions #####
506 ===============================================================================
507 [..]
508 This subsection provides a set of functions allowing to manage the I2C data
509 transfers.
510
511 (#) There are two modes of transfer:
512 (++) Blocking mode : The communication is performed in the polling mode.
513 The status of all data processing is returned by the same function
514 after finishing transfer.
515 (++) No-Blocking mode : The communication is performed using Interrupts
516 or DMA. These functions return the status of the transfer startup.
517 The end of the data processing will be indicated through the
518 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
519 using DMA mode.
520
521 (#) Blocking mode functions are :
522 (++) HAL_I2C_Master_Transmit()
523 (++) HAL_I2C_Master_Receive()
524 (++) HAL_I2C_Slave_Transmit()
525 (++) HAL_I2C_Slave_Receive()
526 (++) HAL_I2C_Mem_Write()
527 (++) HAL_I2C_Mem_Read()
528 (++) HAL_I2C_IsDeviceReady()
529
530 (#) No-Blocking mode functions with Interrupt are :
531 (++) HAL_I2C_Master_Transmit_IT()
532 (++) HAL_I2C_Master_Receive_IT()
533 (++) HAL_I2C_Slave_Transmit_IT()
534 (++) HAL_I2C_Slave_Receive_IT()
535 (++) HAL_I2C_Master_Sequential_Transmit_IT()
536 (++) HAL_I2C_Master_Sequential_Receive_IT()
537 (++) HAL_I2C_Slave_Sequential_Transmit_IT()
538 (++) HAL_I2C_Slave_Sequential_Receive_IT()
539 (++) HAL_I2C_Mem_Write_IT()
540 (++) HAL_I2C_Mem_Read_IT()
541
542 (#) No-Blocking mode functions with DMA are :
543 (++) HAL_I2C_Master_Transmit_DMA()
544 (++) HAL_I2C_Master_Receive_DMA()
545 (++) HAL_I2C_Slave_Transmit_DMA()
546 (++) HAL_I2C_Slave_Receive_DMA()
547 (++) HAL_I2C_Mem_Write_DMA()
548 (++) HAL_I2C_Mem_Read_DMA()
549
550 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
551 (++) HAL_I2C_MemTxCpltCallback()
552 (++) HAL_I2C_MemRxCpltCallback()
553 (++) HAL_I2C_MasterTxCpltCallback()
554 (++) HAL_I2C_MasterRxCpltCallback()
555 (++) HAL_I2C_SlaveTxCpltCallback()
556 (++) HAL_I2C_SlaveRxCpltCallback()
557 (++) HAL_I2C_ErrorCallback()
558 (++) HAL_I2C_AbortCpltCallback()
559
560 @endverbatim
561 * @{
562 */
563
564 /**
565 * @brief Transmits in master mode an amount of data in blocking mode.
566 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
567 * the configuration information for the specified I2C.
568 * @param DevAddress Target device address The device 7 bits address value
569 * in datasheet must be shifted to the left before calling the interface
570 * @param pData Pointer to data buffer
571 * @param Size Amount of data to be sent
572 * @param Timeout Timeout duration
573 * @retval HAL status
574 */
575 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
576 {
577 uint32_t tickstart = 0x00U;
578
579 /* Init tickstart for timeout management*/
580 tickstart = HAL_GetTick();
581
582 if(hi2c->State == HAL_I2C_STATE_READY)
583 {
584 /* Wait until BUSY flag is reset */
585 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
586 {
587 return HAL_BUSY;
588 }
589
590 /* Process Locked */
591 __HAL_LOCK(hi2c);
592
593 /* Check if the I2C is already enabled */
594 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
595 {
596 /* Enable I2C peripheral */
597 __HAL_I2C_ENABLE(hi2c);
598 }
599
600 /* Disable Pos */
601 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
602
603 hi2c->State = HAL_I2C_STATE_BUSY_TX;
604 hi2c->Mode = HAL_I2C_MODE_MASTER;
605 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
606
607 /* Prepare transfer parameters */
608 hi2c->pBuffPtr = pData;
609 hi2c->XferCount = Size;
610 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
611 hi2c->XferSize = hi2c->XferCount;
612
613 /* Send Slave Address */
614 if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
615 {
616 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
617 {
618 /* Process Unlocked */
619 __HAL_UNLOCK(hi2c);
620 return HAL_ERROR;
621 }
622 else
623 {
624 /* Process Unlocked */
625 __HAL_UNLOCK(hi2c);
626 return HAL_TIMEOUT;
627 }
628 }
629
630 /* Clear ADDR flag */
631 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
632
633 while(hi2c->XferSize > 0U)
634 {
635 /* Wait until TXE flag is set */
636 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
637 {
638 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
639 {
640 /* Generate Stop */
641 hi2c->Instance->CR1 |= I2C_CR1_STOP;
642 return HAL_ERROR;
643 }
644 else
645 {
646 return HAL_TIMEOUT;
647 }
648 }
649
650 /* Write data to DR */
651 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
652 hi2c->XferCount--;
653 hi2c->XferSize--;
654
655 if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
656 {
657 /* Write data to DR */
658 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
659 hi2c->XferCount--;
660 hi2c->XferSize--;
661 }
662
663 /* Wait until BTF flag is set */
664 if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
665 {
666 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
667 {
668 /* Generate Stop */
669 hi2c->Instance->CR1 |= I2C_CR1_STOP;
670 return HAL_ERROR;
671 }
672 else
673 {
674 return HAL_TIMEOUT;
675 }
676 }
677 }
678
679 /* Generate Stop */
680 hi2c->Instance->CR1 |= I2C_CR1_STOP;
681
682 hi2c->State = HAL_I2C_STATE_READY;
683 hi2c->Mode = HAL_I2C_MODE_NONE;
684
685 /* Process Unlocked */
686 __HAL_UNLOCK(hi2c);
687
688 return HAL_OK;
689 }
690 else
691 {
692 return HAL_BUSY;
693 }
694 }
695
696 /**
697 * @brief Receives in master mode an amount of data in blocking mode.
698 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
699 * the configuration information for the specified I2C.
700 * @param DevAddress Target device address The device 7 bits address value
701 * in datasheet must be shifted to the left before calling the interface
702 * @param pData Pointer to data buffer
703 * @param Size Amount of data to be sent
704 * @param Timeout Timeout duration
705 * @retval HAL status
706 */
707 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
708 {
709 uint32_t tickstart = 0x00U;
710
711 /* Init tickstart for timeout management*/
712 tickstart = HAL_GetTick();
713
714 if(hi2c->State == HAL_I2C_STATE_READY)
715 {
716 /* Wait until BUSY flag is reset */
717 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
718 {
719 return HAL_BUSY;
720 }
721
722 /* Process Locked */
723 __HAL_LOCK(hi2c);
724
725 /* Check if the I2C is already enabled */
726 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
727 {
728 /* Enable I2C peripheral */
729 __HAL_I2C_ENABLE(hi2c);
730 }
731
732 /* Disable Pos */
733 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
734
735 hi2c->State = HAL_I2C_STATE_BUSY_RX;
736 hi2c->Mode = HAL_I2C_MODE_MASTER;
737 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
738
739 /* Prepare transfer parameters */
740 hi2c->pBuffPtr = pData;
741 hi2c->XferCount = Size;
742 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
743 hi2c->XferSize = hi2c->XferCount;
744
745 /* Send Slave Address */
746 if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
747 {
748 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
749 {
750 /* Process Unlocked */
751 __HAL_UNLOCK(hi2c);
752 return HAL_ERROR;
753 }
754 else
755 {
756 /* Process Unlocked */
757 __HAL_UNLOCK(hi2c);
758 return HAL_TIMEOUT;
759 }
760 }
761
762 if(hi2c->XferSize == 0U)
763 {
764 /* Clear ADDR flag */
765 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
766
767 /* Generate Stop */
768 hi2c->Instance->CR1 |= I2C_CR1_STOP;
769 }
770 else if(hi2c->XferSize == 1U)
771 {
772 /* Disable Acknowledge */
773 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
774
775 /* Clear ADDR flag */
776 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
777
778 /* Generate Stop */
779 hi2c->Instance->CR1 |= I2C_CR1_STOP;
780 }
781 else if(hi2c->XferSize == 2U)
782 {
783 /* Disable Acknowledge */
784 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
785
786 /* Enable Pos */
787 hi2c->Instance->CR1 |= I2C_CR1_POS;
788
789 /* Clear ADDR flag */
790 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
791 }
792 else
793 {
794 /* Enable Acknowledge */
795 hi2c->Instance->CR1 |= I2C_CR1_ACK;
796
797 /* Clear ADDR flag */
798 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
799 }
800
801 while(hi2c->XferSize > 0U)
802 {
803 if(hi2c->XferSize <= 3U)
804 {
805 /* One byte */
806 if(hi2c->XferSize == 1U)
807 {
808 /* Wait until RXNE flag is set */
809 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
810 {
811 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
812 {
813 return HAL_TIMEOUT;
814 }
815 else
816 {
817 return HAL_ERROR;
818 }
819 }
820
821 /* Read data from DR */
822 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
823 hi2c->XferSize--;
824 hi2c->XferCount--;
825 }
826 /* Two bytes */
827 else if(hi2c->XferSize == 2U)
828 {
829 /* Wait until BTF flag is set */
830 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
831 {
832 return HAL_TIMEOUT;
833 }
834
835 /* Generate Stop */
836 hi2c->Instance->CR1 |= I2C_CR1_STOP;
837
838 /* Read data from DR */
839 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
840 hi2c->XferSize--;
841 hi2c->XferCount--;
842
843 /* Read data from DR */
844 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
845 hi2c->XferSize--;
846 hi2c->XferCount--;
847 }
848 /* 3 Last bytes */
849 else
850 {
851 /* Wait until BTF flag is set */
852 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
853 {
854 return HAL_TIMEOUT;
855 }
856
857 /* Disable Acknowledge */
858 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
859
860 /* Read data from DR */
861 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
862 hi2c->XferSize--;
863 hi2c->XferCount--;
864
865 /* Wait until BTF flag is set */
866 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
867 {
868 return HAL_TIMEOUT;
869 }
870
871 /* Generate Stop */
872 hi2c->Instance->CR1 |= I2C_CR1_STOP;
873
874 /* Read data from DR */
875 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
876 hi2c->XferSize--;
877 hi2c->XferCount--;
878
879 /* Read data from DR */
880 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
881 hi2c->XferSize--;
882 hi2c->XferCount--;
883 }
884 }
885 else
886 {
887 /* Wait until RXNE flag is set */
888 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
889 {
890 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
891 {
892 return HAL_TIMEOUT;
893 }
894 else
895 {
896 return HAL_ERROR;
897 }
898 }
899
900 /* Read data from DR */
901 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
902 hi2c->XferSize--;
903 hi2c->XferCount--;
904
905 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
906 {
907 /* Read data from DR */
908 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
909 hi2c->XferSize--;
910 hi2c->XferCount--;
911 }
912 }
913 }
914
915 hi2c->State = HAL_I2C_STATE_READY;
916 hi2c->Mode = HAL_I2C_MODE_NONE;
917
918 /* Process Unlocked */
919 __HAL_UNLOCK(hi2c);
920
921 return HAL_OK;
922 }
923 else
924 {
925 return HAL_BUSY;
926 }
927 }
928
929 /**
930 * @brief Transmits in slave mode an amount of data in blocking mode.
931 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
932 * the configuration information for the specified I2C.
933 * @param pData Pointer to data buffer
934 * @param Size Amount of data to be sent
935 * @param Timeout Timeout duration
936 * @retval HAL status
937 */
938 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
939 {
940 uint32_t tickstart = 0x00U;
941
942 /* Init tickstart for timeout management*/
943 tickstart = HAL_GetTick();
944
945 if(hi2c->State == HAL_I2C_STATE_READY)
946 {
947 if((pData == NULL) || (Size == 0U))
948 {
949 return HAL_ERROR;
950 }
951
952 /* Process Locked */
953 __HAL_LOCK(hi2c);
954
955 /* Check if the I2C is already enabled */
956 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
957 {
958 /* Enable I2C peripheral */
959 __HAL_I2C_ENABLE(hi2c);
960 }
961
962 /* Disable Pos */
963 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
964
965 hi2c->State = HAL_I2C_STATE_BUSY_TX;
966 hi2c->Mode = HAL_I2C_MODE_SLAVE;
967 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
968
969 /* Prepare transfer parameters */
970 hi2c->pBuffPtr = pData;
971 hi2c->XferCount = Size;
972 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
973 hi2c->XferSize = hi2c->XferCount;
974
975 /* Enable Address Acknowledge */
976 hi2c->Instance->CR1 |= I2C_CR1_ACK;
977
978 /* Wait until ADDR flag is set */
979 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
980 {
981 return HAL_TIMEOUT;
982 }
983
984 /* Clear ADDR flag */
985 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
986
987 /* If 10bit addressing mode is selected */
988 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
989 {
990 /* Wait until ADDR flag is set */
991 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
992 {
993 return HAL_TIMEOUT;
994 }
995
996 /* Clear ADDR flag */
997 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
998 }
999
1000 while(hi2c->XferSize > 0U)
1001 {
1002 /* Wait until TXE flag is set */
1003 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1004 {
1005 /* Disable Address Acknowledge */
1006 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
1007
1008 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1009 {
1010 return HAL_ERROR;
1011 }
1012 else
1013 {
1014 return HAL_TIMEOUT;
1015 }
1016 }
1017
1018 /* Write data to DR */
1019 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
1020 hi2c->XferCount--;
1021 hi2c->XferSize--;
1022
1023 if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1024 {
1025 /* Write data to DR */
1026 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
1027 hi2c->XferCount--;
1028 hi2c->XferSize--;
1029 }
1030 }
1031
1032 /* Wait until AF flag is set */
1033 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1034 {
1035 return HAL_TIMEOUT;
1036 }
1037
1038 /* Clear AF flag */
1039 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1040
1041 /* Disable Address Acknowledge */
1042 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
1043
1044 hi2c->State = HAL_I2C_STATE_READY;
1045 hi2c->Mode = HAL_I2C_MODE_NONE;
1046
1047 /* Process Unlocked */
1048 __HAL_UNLOCK(hi2c);
1049
1050 return HAL_OK;
1051 }
1052 else
1053 {
1054 return HAL_BUSY;
1055 }
1056 }
1057
1058 /**
1059 * @brief Receive in slave mode an amount of data in blocking mode
1060 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1061 * the configuration information for the specified I2C.
1062 * @param pData Pointer to data buffer
1063 * @param Size Amount of data to be sent
1064 * @param Timeout Timeout duration
1065 * @retval HAL status
1066 */
1067 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1068 {
1069 uint32_t tickstart = 0x00U;
1070
1071 /* Init tickstart for timeout management*/
1072 tickstart = HAL_GetTick();
1073
1074 if(hi2c->State == HAL_I2C_STATE_READY)
1075 {
1076 if((pData == NULL) || (Size == 0))
1077 {
1078 return HAL_ERROR;
1079 }
1080
1081 /* Process Locked */
1082 __HAL_LOCK(hi2c);
1083
1084 /* Check if the I2C is already enabled */
1085 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1086 {
1087 /* Enable I2C peripheral */
1088 __HAL_I2C_ENABLE(hi2c);
1089 }
1090
1091 /* Disable Pos */
1092 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1093
1094 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1095 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1096 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1097
1098 /* Prepare transfer parameters */
1099 hi2c->pBuffPtr = pData;
1100 hi2c->XferCount = Size;
1101 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1102 hi2c->XferSize = hi2c->XferCount;
1103
1104 /* Enable Address Acknowledge */
1105 hi2c->Instance->CR1 |= I2C_CR1_ACK;
1106
1107 /* Wait until ADDR flag is set */
1108 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1109 {
1110 return HAL_TIMEOUT;
1111 }
1112
1113 /* Clear ADDR flag */
1114 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1115
1116 while(hi2c->XferSize > 0U)
1117 {
1118 /* Wait until RXNE flag is set */
1119 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1120 {
1121 /* Disable Address Acknowledge */
1122 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
1123
1124 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
1125 {
1126 return HAL_TIMEOUT;
1127 }
1128 else
1129 {
1130 return HAL_ERROR;
1131 }
1132 }
1133
1134 /* Read data from DR */
1135 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
1136 hi2c->XferSize--;
1137 hi2c->XferCount--;
1138
1139 if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
1140 {
1141 /* Read data from DR */
1142 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
1143 hi2c->XferSize--;
1144 hi2c->XferCount--;
1145 }
1146 }
1147
1148 /* Wait until STOP flag is set */
1149 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1150 {
1151 /* Disable Address Acknowledge */
1152 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
1153
1154 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1155 {
1156 return HAL_ERROR;
1157 }
1158 else
1159 {
1160 return HAL_TIMEOUT;
1161 }
1162 }
1163
1164 /* Clear STOP flag */
1165 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1166
1167 /* Disable Address Acknowledge */
1168 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
1169
1170 hi2c->State = HAL_I2C_STATE_READY;
1171 hi2c->Mode = HAL_I2C_MODE_NONE;
1172
1173 /* Process Unlocked */
1174 __HAL_UNLOCK(hi2c);
1175
1176 return HAL_OK;
1177 }
1178 else
1179 {
1180 return HAL_BUSY;
1181 }
1182 }
1183
1184 /**
1185 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1186 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1187 * the configuration information for the specified I2C.
1188 * @param DevAddress Target device address The device 7 bits address value
1189 * in datasheet must be shifted to the left before calling the interface
1190 * @param pData Pointer to data buffer
1191 * @param Size Amount of data to be sent
1192 * @retval HAL status
1193 */
1194 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1195 {
1196 __IO uint32_t count = 0U;
1197
1198 if(hi2c->State == HAL_I2C_STATE_READY)
1199 {
1200 /* Wait until BUSY flag is reset */
1201 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1202 do
1203 {
1204 if(count-- == 0U)
1205 {
1206 hi2c->PreviousState = I2C_STATE_NONE;
1207 hi2c->State= HAL_I2C_STATE_READY;
1208
1209 /* Process Unlocked */
1210 __HAL_UNLOCK(hi2c);
1211
1212 return HAL_TIMEOUT;
1213 }
1214 }
1215 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1216
1217 /* Process Locked */
1218 __HAL_LOCK(hi2c);
1219
1220 /* Check if the I2C is already enabled */
1221 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1222 {
1223 /* Enable I2C peripheral */
1224 __HAL_I2C_ENABLE(hi2c);
1225 }
1226
1227 /* Disable Pos */
1228 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1229
1230 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1231 hi2c->Mode = HAL_I2C_MODE_MASTER;
1232 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1233
1234 /* Prepare transfer parameters */
1235 hi2c->pBuffPtr = pData;
1236 hi2c->XferCount = Size;
1237 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1238 hi2c->XferSize = hi2c->XferCount;
1239 hi2c->Devaddress = DevAddress;
1240
1241 /* Generate Start */
1242 hi2c->Instance->CR1 |= I2C_CR1_START;
1243
1244 /* Process Unlocked */
1245 __HAL_UNLOCK(hi2c);
1246
1247 /* Note : The I2C interrupts must be enabled after unlocking current process
1248 to avoid the risk of I2C interrupt handle execution before current
1249 process unlock */
1250 /* Enable EVT, BUF and ERR interrupt */
1251 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1252
1253 return HAL_OK;
1254 }
1255 else
1256 {
1257 return HAL_BUSY;
1258 }
1259 }
1260
1261 /**
1262 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1263 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1264 * the configuration information for the specified I2C.
1265 * @param DevAddress Target device address The device 7 bits address value
1266 * in datasheet must be shifted to the left before calling the interface
1267 * @param pData Pointer to data buffer
1268 * @param Size Amount of data to be sent
1269 * @retval HAL status
1270 */
1271 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1272 {
1273 __IO uint32_t count = 0U;
1274
1275 if(hi2c->State == HAL_I2C_STATE_READY)
1276 {
1277 /* Wait until BUSY flag is reset */
1278 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1279 do
1280 {
1281 if(count-- == 0U)
1282 {
1283 hi2c->PreviousState = I2C_STATE_NONE;
1284 hi2c->State= HAL_I2C_STATE_READY;
1285
1286 /* Process Unlocked */
1287 __HAL_UNLOCK(hi2c);
1288
1289 return HAL_TIMEOUT;
1290 }
1291 }
1292 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1293
1294 /* Process Locked */
1295 __HAL_LOCK(hi2c);
1296
1297 /* Check if the I2C is already enabled */
1298 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1299 {
1300 /* Enable I2C peripheral */
1301 __HAL_I2C_ENABLE(hi2c);
1302 }
1303
1304 /* Disable Pos */
1305 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1306
1307 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1308 hi2c->Mode = HAL_I2C_MODE_MASTER;
1309 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1310
1311 /* Prepare transfer parameters */
1312 hi2c->pBuffPtr = pData;
1313 hi2c->XferCount = Size;
1314 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1315 hi2c->XferSize = hi2c->XferCount;
1316 hi2c->Devaddress = DevAddress;
1317
1318 /* Enable Acknowledge */
1319 hi2c->Instance->CR1 |= I2C_CR1_ACK;
1320
1321 /* Generate Start */
1322 hi2c->Instance->CR1 |= I2C_CR1_START;
1323
1324 /* Process Unlocked */
1325 __HAL_UNLOCK(hi2c);
1326
1327 /* Note : The I2C interrupts must be enabled after unlocking current process
1328 to avoid the risk of I2C interrupt handle execution before current
1329 process unlock */
1330
1331 /* Enable EVT, BUF and ERR interrupt */
1332 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1333
1334 return HAL_OK;
1335 }
1336 else
1337 {
1338 return HAL_BUSY;
1339 }
1340 }
1341
1342 /**
1343 * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
1344 * @note This interface allow to manage repeated start condition when a direction change during transfer
1345 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1346 * the configuration information for the specified I2C.
1347 * @param DevAddress Target device address The device 7 bits address value
1348 * in datasheet must be shifted to the left before calling the interface
1349 * @param pData Pointer to data buffer
1350 * @param Size Amount of data to be sent
1351 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
1352 * @retval HAL status
1353 */
1354 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
1355 {
1356 __IO uint32_t Prev_State = 0x00U;
1357 __IO uint32_t count = 0x00U;
1358
1359 /* Check the parameters */
1360 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
1361
1362 if(hi2c->State == HAL_I2C_STATE_READY)
1363 {
1364 /* Check Busy Flag only if FIRST call of Master interface */
1365 if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
1366 {
1367 /* Wait until BUSY flag is reset */
1368 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1369 do
1370 {
1371 if(count-- == 0U)
1372 {
1373 hi2c->PreviousState = I2C_STATE_NONE;
1374 hi2c->State= HAL_I2C_STATE_READY;
1375
1376 /* Process Unlocked */
1377 __HAL_UNLOCK(hi2c);
1378
1379 return HAL_TIMEOUT;
1380 }
1381 }
1382 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1383 }
1384
1385 /* Process Locked */
1386 __HAL_LOCK(hi2c);
1387
1388 /* Check if the I2C is already enabled */
1389 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1390 {
1391 /* Enable I2C peripheral */
1392 __HAL_I2C_ENABLE(hi2c);
1393 }
1394
1395 /* Disable Pos */
1396 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1397
1398 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1399 hi2c->Mode = HAL_I2C_MODE_MASTER;
1400 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1401
1402 /* Prepare transfer parameters */
1403 hi2c->pBuffPtr = pData;
1404 hi2c->XferCount = Size;
1405 hi2c->XferOptions = XferOptions;
1406 hi2c->XferSize = hi2c->XferCount;
1407 hi2c->Devaddress = DevAddress;
1408
1409 Prev_State = hi2c->PreviousState;
1410
1411 /* Generate Start */
1412 if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
1413 {
1414 /* Generate Start condition if first transfer */
1415 if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
1416 {
1417 /* Generate Start */
1418 hi2c->Instance->CR1 |= I2C_CR1_START;
1419 }
1420 else
1421 {
1422 /* Generate ReStart */
1423 hi2c->Instance->CR1 |= I2C_CR1_START;
1424 }
1425 }
1426
1427 /* Process Unlocked */
1428 __HAL_UNLOCK(hi2c);
1429
1430 /* Note : The I2C interrupts must be enabled after unlocking current process
1431 to avoid the risk of I2C interrupt handle execution before current
1432 process unlock */
1433
1434 /* Enable EVT, BUF and ERR interrupt */
1435 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1436
1437 return HAL_OK;
1438 }
1439 else
1440 {
1441 return HAL_BUSY;
1442 }
1443 }
1444
1445 /**
1446 * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
1447 * @note This interface allow to manage repeated start condition when a direction change during transfer
1448 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1449 * the configuration information for the specified I2C.
1450 * @param DevAddress Target device address The device 7 bits address value
1451 * in datasheet must be shifted to the left before calling the interface
1452 * @param pData Pointer to data buffer
1453 * @param Size Amount of data to be sent
1454 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
1455 * @retval HAL status
1456 */
1457 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
1458 {
1459 __IO uint32_t count = 0U;
1460
1461 /* Check the parameters */
1462 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
1463
1464 if(hi2c->State == HAL_I2C_STATE_READY)
1465 {
1466 /* Check Busy Flag only if FIRST call of Master interface */
1467 if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
1468 {
1469 /* Wait until BUSY flag is reset */
1470 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1471 do
1472 {
1473 if(count-- == 0U)
1474 {
1475 hi2c->PreviousState = I2C_STATE_NONE;
1476 hi2c->State= HAL_I2C_STATE_READY;
1477
1478 /* Process Unlocked */
1479 __HAL_UNLOCK(hi2c);
1480
1481 return HAL_TIMEOUT;
1482 }
1483 }
1484 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1485 }
1486
1487 /* Process Locked */
1488 __HAL_LOCK(hi2c);
1489
1490 /* Check if the I2C is already enabled */
1491 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1492 {
1493 /* Enable I2C peripheral */
1494 __HAL_I2C_ENABLE(hi2c);
1495 }
1496
1497 /* Disable Pos */
1498 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1499
1500 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1501 hi2c->Mode = HAL_I2C_MODE_MASTER;
1502 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1503
1504 /* Prepare transfer parameters */
1505 hi2c->pBuffPtr = pData;
1506 hi2c->XferCount = Size;
1507 hi2c->XferOptions = XferOptions;
1508 hi2c->XferSize = hi2c->XferCount;
1509 hi2c->Devaddress = DevAddress;
1510
1511 if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
1512 {
1513 /* Generate Start condition if first transfer */
1514 if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME))
1515 {
1516 /* Enable Acknowledge */
1517 hi2c->Instance->CR1 |= I2C_CR1_ACK;
1518
1519 /* Generate Start */
1520 hi2c->Instance->CR1 |= I2C_CR1_START;
1521 }
1522 else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
1523 {
1524 /* Enable Acknowledge */
1525 hi2c->Instance->CR1 |= I2C_CR1_ACK;
1526
1527 /* Generate ReStart */
1528 hi2c->Instance->CR1 |= I2C_CR1_START;
1529 }
1530 }
1531
1532 /* Process Unlocked */
1533 __HAL_UNLOCK(hi2c);
1534
1535 /* Note : The I2C interrupts must be enabled after unlocking current process
1536 to avoid the risk of I2C interrupt handle execution before current
1537 process unlock */
1538
1539 /* Enable EVT, BUF and ERR interrupt */
1540 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1541
1542 return HAL_OK;
1543 }
1544 else
1545 {
1546 return HAL_BUSY;
1547 }
1548 }
1549
1550 /**
1551 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1552 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1553 * the configuration information for the specified I2C.
1554 * @param pData Pointer to data buffer
1555 * @param Size Amount of data to be sent
1556 * @retval HAL status
1557 */
1558 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1559 {
1560 __IO uint32_t count = 0U;
1561
1562 if(hi2c->State == HAL_I2C_STATE_READY)
1563 {
1564 if((pData == NULL) || (Size == 0U))
1565 {
1566 return HAL_ERROR;
1567 }
1568
1569 /* Wait until BUSY flag is reset */
1570 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1571 do
1572 {
1573 if(count-- == 0U)
1574 {
1575 hi2c->PreviousState = I2C_STATE_NONE;
1576 hi2c->State= HAL_I2C_STATE_READY;
1577
1578 /* Process Unlocked */
1579 __HAL_UNLOCK(hi2c);
1580
1581 return HAL_TIMEOUT;
1582 }
1583 }
1584 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1585
1586 /* Process Locked */
1587 __HAL_LOCK(hi2c);
1588
1589 /* Check if the I2C is already enabled */
1590 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1591 {
1592 /* Enable I2C peripheral */
1593 __HAL_I2C_ENABLE(hi2c);
1594 }
1595
1596 /* Disable Pos */
1597 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1598
1599 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1600 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1601 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1602
1603 /* Prepare transfer parameters */
1604 hi2c->pBuffPtr = pData;
1605 hi2c->XferCount = Size;
1606 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1607 hi2c->XferSize = hi2c->XferCount;
1608
1609 /* Enable Address Acknowledge */
1610 hi2c->Instance->CR1 |= I2C_CR1_ACK;
1611
1612 /* Process Unlocked */
1613 __HAL_UNLOCK(hi2c);
1614
1615 /* Note : The I2C interrupts must be enabled after unlocking current process
1616 to avoid the risk of I2C interrupt handle execution before current
1617 process unlock */
1618
1619 /* Enable EVT, BUF and ERR interrupt */
1620 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1621
1622 return HAL_OK;
1623 }
1624 else
1625 {
1626 return HAL_BUSY;
1627 }
1628 }
1629
1630 /**
1631 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1632 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1633 * the configuration information for the specified I2C.
1634 * @param pData Pointer to data buffer
1635 * @param Size Amount of data to be sent
1636 * @retval HAL status
1637 */
1638 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1639 {
1640 __IO uint32_t count = 0U;
1641
1642 if(hi2c->State == HAL_I2C_STATE_READY)
1643 {
1644 if((pData == NULL) || (Size == 0U))
1645 {
1646 return HAL_ERROR;
1647 }
1648
1649 /* Wait until BUSY flag is reset */
1650 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1651 do
1652 {
1653 if(count-- == 0U)
1654 {
1655 hi2c->PreviousState = I2C_STATE_NONE;
1656 hi2c->State= HAL_I2C_STATE_READY;
1657
1658 /* Process Unlocked */
1659 __HAL_UNLOCK(hi2c);
1660
1661 return HAL_TIMEOUT;
1662 }
1663 }
1664 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1665
1666 /* Process Locked */
1667 __HAL_LOCK(hi2c);
1668
1669 /* Check if the I2C is already enabled */
1670 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1671 {
1672 /* Enable I2C peripheral */
1673 __HAL_I2C_ENABLE(hi2c);
1674 }
1675
1676 /* Disable Pos */
1677 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1678
1679 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1680 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1681 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1682
1683 /* Prepare transfer parameters */
1684 hi2c->pBuffPtr = pData;
1685 hi2c->XferSize = Size;
1686 hi2c->XferCount = Size;
1687 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1688
1689 /* Enable Address Acknowledge */
1690 hi2c->Instance->CR1 |= I2C_CR1_ACK;
1691
1692 /* Process Unlocked */
1693 __HAL_UNLOCK(hi2c);
1694
1695 /* Note : The I2C interrupts must be enabled after unlocking current process
1696 to avoid the risk of I2C interrupt handle execution before current
1697 process unlock */
1698
1699 /* Enable EVT, BUF and ERR interrupt */
1700 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1701
1702 return HAL_OK;
1703 }
1704 else
1705 {
1706 return HAL_BUSY;
1707 }
1708 }
1709
1710 /**
1711 * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
1712 * @note This interface allow to manage repeated start condition when a direction change during transfer
1713 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1714 * the configuration information for I2C module
1715 * @param pData Pointer to data buffer
1716 * @param Size Amount of data to be sent
1717 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
1718 * @retval HAL status
1719 */
1720 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
1721 {
1722 /* Check the parameters */
1723 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
1724
1725 if(hi2c->State == HAL_I2C_STATE_LISTEN)
1726 {
1727 if((pData == NULL) || (Size == 0U))
1728 {
1729 return HAL_ERROR;
1730 }
1731
1732 /* Process Locked */
1733 __HAL_LOCK(hi2c);
1734
1735 /* Check if the I2C is already enabled */
1736 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1737 {
1738 /* Enable I2C peripheral */
1739 __HAL_I2C_ENABLE(hi2c);
1740 }
1741
1742 /* Disable Pos */
1743 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1744
1745 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
1746 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1747 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1748
1749 /* Prepare transfer parameters */
1750 hi2c->pBuffPtr = pData;
1751 hi2c->XferCount = Size;
1752 hi2c->XferOptions = XferOptions;
1753 hi2c->XferSize = hi2c->XferCount;
1754
1755 /* Clear ADDR flag */
1756 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1757
1758 /* Process Unlocked */
1759 __HAL_UNLOCK(hi2c);
1760
1761 /* Note : The I2C interrupts must be enabled after unlocking current process
1762 to avoid the risk of I2C interrupt handle execution before current
1763 process unlock */
1764
1765 /* Enable EVT, BUF and ERR interrupt */
1766 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1767
1768 return HAL_OK;
1769 }
1770 else
1771 {
1772 return HAL_BUSY;
1773 }
1774 }
1775
1776 /**
1777 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
1778 * @note This interface allow to manage repeated start condition when a direction change during transfer
1779 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1780 * the configuration information for the specified I2C.
1781 * @param pData Pointer to data buffer
1782 * @param Size Amount of data to be sent
1783 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
1784 * @retval HAL status
1785 */
1786 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
1787 {
1788 /* Check the parameters */
1789 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
1790
1791 if(hi2c->State == HAL_I2C_STATE_LISTEN)
1792 {
1793 if((pData == NULL) || (Size == 0U))
1794 {
1795 return HAL_ERROR;
1796 }
1797
1798 /* Process Locked */
1799 __HAL_LOCK(hi2c);
1800
1801 /* Check if the I2C is already enabled */
1802 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1803 {
1804 /* Enable I2C peripheral */
1805 __HAL_I2C_ENABLE(hi2c);
1806 }
1807
1808 /* Disable Pos */
1809 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1810
1811 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
1812 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1813 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1814
1815 /* Prepare transfer parameters */
1816 hi2c->pBuffPtr = pData;
1817 hi2c->XferCount = Size;
1818 hi2c->XferOptions = XferOptions;
1819 hi2c->XferSize = hi2c->XferCount;
1820
1821 /* Clear ADDR flag */
1822 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1823
1824 /* Process Unlocked */
1825 __HAL_UNLOCK(hi2c);
1826
1827 /* Note : The I2C interrupts must be enabled after unlocking current process
1828 to avoid the risk of I2C interrupt handle execution before current
1829 process unlock */
1830
1831 /* Enable EVT, BUF and ERR interrupt */
1832 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1833
1834 return HAL_OK;
1835 }
1836 else
1837 {
1838 return HAL_BUSY;
1839 }
1840 }
1841
1842 /**
1843 * @brief Enable the Address listen mode with Interrupt.
1844 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1845 * the configuration information for the specified I2C.
1846 * @retval HAL status
1847 */
1848 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
1849 {
1850 if(hi2c->State == HAL_I2C_STATE_READY)
1851 {
1852 hi2c->State = HAL_I2C_STATE_LISTEN;
1853
1854 /* Check if the I2C is already enabled */
1855 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1856 {
1857 /* Enable I2C peripheral */
1858 __HAL_I2C_ENABLE(hi2c);
1859 }
1860
1861 /* Enable Address Acknowledge */
1862 hi2c->Instance->CR1 |= I2C_CR1_ACK;
1863
1864 /* Enable EVT and ERR interrupt */
1865 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
1866
1867 return HAL_OK;
1868 }
1869 else
1870 {
1871 return HAL_BUSY;
1872 }
1873 }
1874
1875 /**
1876 * @brief Disable the Address listen mode with Interrupt.
1877 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1878 * the configuration information for the specified I2C.
1879 * @retval HAL status
1880 */
1881 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
1882 {
1883 /* Declaration of tmp to prevent undefined behavior of volatile usage */
1884 uint32_t tmp;
1885
1886 /* Disable Address listen mode only if a transfer is not ongoing */
1887 if(hi2c->State == HAL_I2C_STATE_LISTEN)
1888 {
1889 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
1890 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
1891 hi2c->State = HAL_I2C_STATE_READY;
1892 hi2c->Mode = HAL_I2C_MODE_NONE;
1893
1894 /* Disable Address Acknowledge */
1895 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
1896
1897 /* Disable EVT and ERR interrupt */
1898 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
1899
1900 return HAL_OK;
1901 }
1902 else
1903 {
1904 return HAL_BUSY;
1905 }
1906 }
1907
1908 /**
1909 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1910 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1911 * the configuration information for the specified I2C.
1912 * @param DevAddress Target device address The device 7 bits address value
1913 * in datasheet must be shifted to the left before calling the interface
1914 * @param pData Pointer to data buffer
1915 * @param Size Amount of data to be sent
1916 * @retval HAL status
1917 */
1918 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1919 {
1920 __IO uint32_t count = 0U;
1921
1922 if(hi2c->State == HAL_I2C_STATE_READY)
1923 {
1924 /* Wait until BUSY flag is reset */
1925 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1926 do
1927 {
1928 if(count-- == 0U)
1929 {
1930 hi2c->PreviousState = I2C_STATE_NONE;
1931 hi2c->State= HAL_I2C_STATE_READY;
1932
1933 /* Process Unlocked */
1934 __HAL_UNLOCK(hi2c);
1935
1936 return HAL_TIMEOUT;
1937 }
1938 }
1939 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1940
1941 /* Process Locked */
1942 __HAL_LOCK(hi2c);
1943
1944 /* Check if the I2C is already enabled */
1945 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1946 {
1947 /* Enable I2C peripheral */
1948 __HAL_I2C_ENABLE(hi2c);
1949 }
1950
1951 /* Disable Pos */
1952 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
1953
1954 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1955 hi2c->Mode = HAL_I2C_MODE_MASTER;
1956 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1957
1958 /* Prepare transfer parameters */
1959 hi2c->pBuffPtr = pData;
1960 hi2c->XferCount = Size;
1961 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1962 hi2c->XferSize = hi2c->XferCount;
1963 hi2c->Devaddress = DevAddress;
1964
1965 if(hi2c->XferSize > 0U)
1966 {
1967 /* Set the I2C DMA transfer complete callback */
1968 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
1969
1970 /* Set the DMA error callback */
1971 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1972
1973 /* Set the unused DMA callbacks to NULL */
1974 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1975 hi2c->hdmatx->XferM1CpltCallback = NULL;
1976 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
1977 hi2c->hdmatx->XferAbortCallback = NULL;
1978
1979 /* Enable the DMA Stream */
1980 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
1981
1982 /* Enable Acknowledge */
1983 hi2c->Instance->CR1 |= I2C_CR1_ACK;
1984
1985 /* Generate Start */
1986 hi2c->Instance->CR1 |= I2C_CR1_START;
1987
1988 /* Process Unlocked */
1989 __HAL_UNLOCK(hi2c);
1990
1991 /* Note : The I2C interrupts must be enabled after unlocking current process
1992 to avoid the risk of I2C interrupt handle execution before current
1993 process unlock */
1994
1995 /* Enable EVT and ERR interrupt */
1996 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
1997
1998 /* Enable DMA Request */
1999 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2000 }
2001 else
2002 {
2003 /* Enable Acknowledge */
2004 hi2c->Instance->CR1 |= I2C_CR1_ACK;
2005
2006 /* Generate Start */
2007 hi2c->Instance->CR1 |= I2C_CR1_START;
2008
2009 /* Process Unlocked */
2010 __HAL_UNLOCK(hi2c);
2011
2012 /* Note : The I2C interrupts must be enabled after unlocking current process
2013 to avoid the risk of I2C interrupt handle execution before current
2014 process unlock */
2015
2016 /* Enable EVT, BUF and ERR interrupt */
2017 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2018 }
2019
2020 return HAL_OK;
2021 }
2022 else
2023 {
2024 return HAL_BUSY;
2025 }
2026 }
2027
2028 /**
2029 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2030 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2031 * the configuration information for the specified I2C.
2032 * @param DevAddress Target device address The device 7 bits address value
2033 * in datasheet must be shifted to the left before calling the interface
2034 * @param pData Pointer to data buffer
2035 * @param Size Amount of data to be sent
2036 * @retval HAL status
2037 */
2038 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2039 {
2040 __IO uint32_t count = 0U;
2041
2042 if(hi2c->State == HAL_I2C_STATE_READY)
2043 {
2044 /* Wait until BUSY flag is reset */
2045 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
2046 do
2047 {
2048 if(count-- == 0U)
2049 {
2050 hi2c->PreviousState = I2C_STATE_NONE;
2051 hi2c->State= HAL_I2C_STATE_READY;
2052
2053 /* Process Unlocked */
2054 __HAL_UNLOCK(hi2c);
2055
2056 return HAL_TIMEOUT;
2057 }
2058 }
2059 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2060
2061 /* Process Locked */
2062 __HAL_LOCK(hi2c);
2063
2064 /* Check if the I2C is already enabled */
2065 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2066 {
2067 /* Enable I2C peripheral */
2068 __HAL_I2C_ENABLE(hi2c);
2069 }
2070
2071 /* Disable Pos */
2072 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
2073
2074 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2075 hi2c->Mode = HAL_I2C_MODE_MASTER;
2076 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2077
2078 /* Prepare transfer parameters */
2079 hi2c->pBuffPtr = pData;
2080 hi2c->XferCount = Size;
2081 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2082 hi2c->XferSize = hi2c->XferCount;
2083 hi2c->Devaddress = DevAddress;
2084
2085 if(hi2c->XferSize > 0U)
2086 {
2087 /* Set the I2C DMA transfer complete callback */
2088 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2089
2090 /* Set the DMA error callback */
2091 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2092
2093 /* Set the unused DMA callbacks to NULL */
2094 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2095 hi2c->hdmarx->XferM1CpltCallback = NULL;
2096 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2097 hi2c->hdmarx->XferAbortCallback = NULL;
2098
2099 /* Enable the DMA Stream */
2100 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2101
2102 /* Enable Acknowledge */
2103 hi2c->Instance->CR1 |= I2C_CR1_ACK;
2104
2105 /* Generate Start */
2106 hi2c->Instance->CR1 |= I2C_CR1_START;
2107
2108 /* Process Unlocked */
2109 __HAL_UNLOCK(hi2c);
2110
2111 /* Note : The I2C interrupts must be enabled after unlocking current process
2112 to avoid the risk of I2C interrupt handle execution before current
2113 process unlock */
2114
2115 /* Enable EVT and ERR interrupt */
2116 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2117
2118 /* Enable DMA Request */
2119 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2120 }
2121 else
2122 {
2123 /* Enable Acknowledge */
2124 hi2c->Instance->CR1 |= I2C_CR1_ACK;
2125
2126 /* Generate Start */
2127 hi2c->Instance->CR1 |= I2C_CR1_START;
2128
2129 /* Process Unlocked */
2130 __HAL_UNLOCK(hi2c);
2131
2132 /* Note : The I2C interrupts must be enabled after unlocking current process
2133 to avoid the risk of I2C interrupt handle execution before current
2134 process unlock */
2135
2136 /* Enable EVT, BUF and ERR interrupt */
2137 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2138 }
2139
2140 return HAL_OK;
2141 }
2142 else
2143 {
2144 return HAL_BUSY;
2145 }
2146 }
2147
2148 /**
2149 * @brief Abort a master I2C process communication with Interrupt.
2150 * @note This abort can be called only if state is ready
2151 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2152 * the configuration information for the specified I2C.
2153 * @param DevAddress Target device address The device 7 bits address value
2154 * in datasheet must be shifted to the left before calling the interface
2155 * @retval HAL status
2156 */
2157 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
2158 {
2159 /* Prevent unused argument(s) compilation warning */
2160 UNUSED(DevAddress);
2161
2162 /* Abort Master transfer during Receive or Transmit process */
2163 if(hi2c->Mode == HAL_I2C_MODE_MASTER)
2164 {
2165 /* Process Locked */
2166 __HAL_LOCK(hi2c);
2167
2168 hi2c->PreviousState = I2C_STATE_NONE;
2169 hi2c->State = HAL_I2C_STATE_ABORT;
2170
2171 /* Disable Acknowledge */
2172 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
2173
2174 /* Generate Stop */
2175 hi2c->Instance->CR1 |= I2C_CR1_STOP;
2176
2177 hi2c->XferCount = 0U;
2178
2179 /* Disable EVT, BUF and ERR interrupt */
2180 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2181
2182 /* Process Unlocked */
2183 __HAL_UNLOCK(hi2c);
2184
2185 /* Call the corresponding callback to inform upper layer of End of Transfer */
2186 I2C_ITError(hi2c);
2187
2188 return HAL_OK;
2189 }
2190 else
2191 {
2192 /* Wrong usage of abort function */
2193 /* This function should be used only in case of abort monitored by master device */
2194 return HAL_ERROR;
2195 }
2196 }
2197
2198 /**
2199 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2200 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2201 * the configuration information for the specified I2C.
2202 * @param pData Pointer to data buffer
2203 * @param Size Amount of data to be sent
2204 * @retval HAL status
2205 */
2206 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2207 {
2208 __IO uint32_t count = 0U;
2209
2210 if(hi2c->State == HAL_I2C_STATE_READY)
2211 {
2212 if((pData == NULL) || (Size == 0U))
2213 {
2214 return HAL_ERROR;
2215 }
2216
2217 /* Wait until BUSY flag is reset */
2218 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
2219 do
2220 {
2221 if(count-- == 0U)
2222 {
2223 hi2c->PreviousState = I2C_STATE_NONE;
2224 hi2c->State= HAL_I2C_STATE_READY;
2225
2226 /* Process Unlocked */
2227 __HAL_UNLOCK(hi2c);
2228
2229 return HAL_TIMEOUT;
2230 }
2231 }
2232 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2233
2234 /* Process Locked */
2235 __HAL_LOCK(hi2c);
2236
2237 /* Check if the I2C is already enabled */
2238 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2239 {
2240 /* Enable I2C peripheral */
2241 __HAL_I2C_ENABLE(hi2c);
2242 }
2243
2244 /* Disable Pos */
2245 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
2246
2247 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2248 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2249 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2250
2251 /* Prepare transfer parameters */
2252 hi2c->pBuffPtr = pData;
2253 hi2c->XferCount = Size;
2254 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2255 hi2c->XferSize = hi2c->XferCount;
2256
2257 /* Set the I2C DMA transfer complete callback */
2258 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2259
2260 /* Set the DMA error callback */
2261 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2262
2263 /* Set the unused DMA callbacks to NULL */
2264 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2265 hi2c->hdmatx->XferM1CpltCallback = NULL;
2266 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2267 hi2c->hdmatx->XferAbortCallback = NULL;
2268
2269 /* Enable the DMA Stream */
2270 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2271
2272 /* Enable Address Acknowledge */
2273 hi2c->Instance->CR1 |= I2C_CR1_ACK;
2274
2275 /* Process Unlocked */
2276 __HAL_UNLOCK(hi2c);
2277
2278 /* Note : The I2C interrupts must be enabled after unlocking current process
2279 to avoid the risk of I2C interrupt handle execution before current
2280 process unlock */
2281 /* Enable EVT and ERR interrupt */
2282 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2283
2284 /* Enable DMA Request */
2285 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2286
2287 return HAL_OK;
2288 }
2289 else
2290 {
2291 return HAL_BUSY;
2292 }
2293 }
2294
2295 /**
2296 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2297 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2298 * the configuration information for the specified I2C.
2299 * @param pData Pointer to data buffer
2300 * @param Size Amount of data to be sent
2301 * @retval HAL status
2302 */
2303 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2304 {
2305 __IO uint32_t count = 0U;
2306
2307 if(hi2c->State == HAL_I2C_STATE_READY)
2308 {
2309 if((pData == NULL) || (Size == 0U))
2310 {
2311 return HAL_ERROR;
2312 }
2313
2314 /* Wait until BUSY flag is reset */
2315 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
2316 do
2317 {
2318 if(count-- == 0U)
2319 {
2320 hi2c->PreviousState = I2C_STATE_NONE;
2321 hi2c->State= HAL_I2C_STATE_READY;
2322
2323 /* Process Unlocked */
2324 __HAL_UNLOCK(hi2c);
2325
2326 return HAL_TIMEOUT;
2327 }
2328 }
2329 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2330
2331 /* Process Locked */
2332 __HAL_LOCK(hi2c);
2333
2334 /* Check if the I2C is already enabled */
2335 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2336 {
2337 /* Enable I2C peripheral */
2338 __HAL_I2C_ENABLE(hi2c);
2339 }
2340
2341 /* Disable Pos */
2342 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
2343
2344 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2345 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2346 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2347
2348 /* Prepare transfer parameters */
2349 hi2c->pBuffPtr = pData;
2350 hi2c->XferCount = Size;
2351 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2352 hi2c->XferSize = hi2c->XferCount;
2353
2354 /* Set the I2C DMA transfer complete callback */
2355 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2356
2357 /* Set the DMA error callback */
2358 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2359
2360 /* Set the unused DMA callbacks to NULL */
2361 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2362 hi2c->hdmarx->XferM1CpltCallback = NULL;
2363 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2364 hi2c->hdmarx->XferAbortCallback = NULL;
2365
2366 /* Enable the DMA Stream */
2367 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2368
2369 /* Enable Address Acknowledge */
2370 hi2c->Instance->CR1 |= I2C_CR1_ACK;
2371
2372 /* Process Unlocked */
2373 __HAL_UNLOCK(hi2c);
2374
2375 /* Note : The I2C interrupts must be enabled after unlocking current process
2376 to avoid the risk of I2C interrupt handle execution before current
2377 process unlock */
2378 /* Enable EVT and ERR interrupt */
2379 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2380
2381 /* Enable DMA Request */
2382 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2383
2384 return HAL_OK;
2385 }
2386 else
2387 {
2388 return HAL_BUSY;
2389 }
2390 }
2391 /**
2392 * @brief Write an amount of data in blocking mode to a specific memory address
2393 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2394 * the configuration information for the specified I2C.
2395 * @param DevAddress Target device address
2396 * @param MemAddress Internal memory address
2397 * @param MemAddSize Size of internal memory address
2398 * @param pData Pointer to data buffer
2399 * @param Size Amount of data to be sent
2400 * @param Timeout Timeout duration
2401 * @retval HAL status
2402 */
2403 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2404 {
2405 uint32_t tickstart = 0x00U;
2406
2407 /* Init tickstart for timeout management*/
2408 tickstart = HAL_GetTick();
2409
2410 /* Check the parameters */
2411 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2412
2413 if(hi2c->State == HAL_I2C_STATE_READY)
2414 {
2415 /* Wait until BUSY flag is reset */
2416 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2417 {
2418 return HAL_BUSY;
2419 }
2420
2421 /* Process Locked */
2422 __HAL_LOCK(hi2c);
2423
2424 /* Check if the I2C is already enabled */
2425 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2426 {
2427 /* Enable I2C peripheral */
2428 __HAL_I2C_ENABLE(hi2c);
2429 }
2430
2431 /* Disable Pos */
2432 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
2433
2434 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2435 hi2c->Mode = HAL_I2C_MODE_MEM;
2436 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2437
2438 /* Prepare transfer parameters */
2439 hi2c->pBuffPtr = pData;
2440 hi2c->XferCount = Size;
2441 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2442 hi2c->XferSize = hi2c->XferCount;
2443
2444 /* Send Slave Address and Memory Address */
2445 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2446 {
2447 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2448 {
2449 /* Process Unlocked */
2450 __HAL_UNLOCK(hi2c);
2451 return HAL_ERROR;
2452 }
2453 else
2454 {
2455 /* Process Unlocked */
2456 __HAL_UNLOCK(hi2c);
2457 return HAL_TIMEOUT;
2458 }
2459 }
2460
2461 while(hi2c->XferSize > 0U)
2462 {
2463 /* Wait until TXE flag is set */
2464 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2465 {
2466 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2467 {
2468 /* Generate Stop */
2469 hi2c->Instance->CR1 |= I2C_CR1_STOP;
2470 return HAL_ERROR;
2471 }
2472 else
2473 {
2474 return HAL_TIMEOUT;
2475 }
2476 }
2477
2478 /* Write data to DR */
2479 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
2480 hi2c->XferSize--;
2481 hi2c->XferCount--;
2482
2483 if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2484 {
2485 /* Write data to DR */
2486 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
2487 hi2c->XferSize--;
2488 hi2c->XferCount--;
2489 }
2490 }
2491
2492 /* Wait until BTF flag is set */
2493 if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2494 {
2495 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2496 {
2497 /* Generate Stop */
2498 hi2c->Instance->CR1 |= I2C_CR1_STOP;
2499 return HAL_ERROR;
2500 }
2501 else
2502 {
2503 return HAL_TIMEOUT;
2504 }
2505 }
2506
2507 /* Generate Stop */
2508 hi2c->Instance->CR1 |= I2C_CR1_STOP;
2509
2510 hi2c->State = HAL_I2C_STATE_READY;
2511 hi2c->Mode = HAL_I2C_MODE_NONE;
2512
2513 /* Process Unlocked */
2514 __HAL_UNLOCK(hi2c);
2515
2516 return HAL_OK;
2517 }
2518 else
2519 {
2520 return HAL_BUSY;
2521 }
2522 }
2523
2524 /**
2525 * @brief Read an amount of data in blocking mode from a specific memory address
2526 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2527 * the configuration information for the specified I2C.
2528 * @param DevAddress Target device address
2529 * @param MemAddress Internal memory address
2530 * @param MemAddSize Size of internal memory address
2531 * @param pData Pointer to data buffer
2532 * @param Size Amount of data to be sent
2533 * @param Timeout Timeout duration
2534 * @retval HAL status
2535 */
2536 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2537 {
2538 uint32_t tickstart = 0x00U;
2539
2540 /* Init tickstart for timeout management*/
2541 tickstart = HAL_GetTick();
2542
2543 /* Check the parameters */
2544 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2545
2546 if(hi2c->State == HAL_I2C_STATE_READY)
2547 {
2548 /* Wait until BUSY flag is reset */
2549 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2550 {
2551 return HAL_BUSY;
2552 }
2553
2554 /* Process Locked */
2555 __HAL_LOCK(hi2c);
2556
2557 /* Check if the I2C is already enabled */
2558 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2559 {
2560 /* Enable I2C peripheral */
2561 __HAL_I2C_ENABLE(hi2c);
2562 }
2563
2564 /* Disable Pos */
2565 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
2566
2567 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2568 hi2c->Mode = HAL_I2C_MODE_MEM;
2569 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2570
2571 /* Prepare transfer parameters */
2572 hi2c->pBuffPtr = pData;
2573 hi2c->XferCount = Size;
2574 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2575 hi2c->XferSize = hi2c->XferCount;
2576
2577 /* Send Slave Address and Memory Address */
2578 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2579 {
2580 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2581 {
2582 /* Process Unlocked */
2583 __HAL_UNLOCK(hi2c);
2584 return HAL_ERROR;
2585 }
2586 else
2587 {
2588 /* Process Unlocked */
2589 __HAL_UNLOCK(hi2c);
2590 return HAL_TIMEOUT;
2591 }
2592 }
2593
2594 if(hi2c->XferSize == 0U)
2595 {
2596 /* Clear ADDR flag */
2597 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2598
2599 /* Generate Stop */
2600 hi2c->Instance->CR1 |= I2C_CR1_STOP;
2601 }
2602 else if(hi2c->XferSize == 1U)
2603 {
2604 /* Disable Acknowledge */
2605 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
2606
2607 /* Clear ADDR flag */
2608 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2609
2610 /* Generate Stop */
2611 hi2c->Instance->CR1 |= I2C_CR1_STOP;
2612 }
2613 else if(hi2c->XferSize == 2U)
2614 {
2615 /* Disable Acknowledge */
2616 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
2617
2618 /* Enable Pos */
2619 hi2c->Instance->CR1 |= I2C_CR1_POS;
2620
2621 /* Clear ADDR flag */
2622 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2623 }
2624 else
2625 {
2626 /* Clear ADDR flag */
2627 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2628 }
2629
2630 while(hi2c->XferSize > 0U)
2631 {
2632 if(hi2c->XferSize <= 3U)
2633 {
2634 /* One byte */
2635 if(hi2c->XferSize== 1U)
2636 {
2637 /* Wait until RXNE flag is set */
2638 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2639 {
2640 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
2641 {
2642 return HAL_TIMEOUT;
2643 }
2644 else
2645 {
2646 return HAL_ERROR;
2647 }
2648 }
2649
2650 /* Read data from DR */
2651 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2652 hi2c->XferSize--;
2653 hi2c->XferCount--;
2654 }
2655 /* Two bytes */
2656 else if(hi2c->XferSize == 2U)
2657 {
2658 /* Wait until BTF flag is set */
2659 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2660 {
2661 return HAL_TIMEOUT;
2662 }
2663
2664 /* Generate Stop */
2665 hi2c->Instance->CR1 |= I2C_CR1_STOP;
2666
2667 /* Read data from DR */
2668 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2669 hi2c->XferSize--;
2670 hi2c->XferCount--;
2671
2672 /* Read data from DR */
2673 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2674 hi2c->XferSize--;
2675 hi2c->XferCount--;
2676 }
2677 /* 3 Last bytes */
2678 else
2679 {
2680 /* Wait until BTF flag is set */
2681 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2682 {
2683 return HAL_TIMEOUT;
2684 }
2685
2686 /* Disable Acknowledge */
2687 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
2688
2689 /* Read data from DR */
2690 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2691 hi2c->XferSize--;
2692 hi2c->XferCount--;
2693
2694 /* Wait until BTF flag is set */
2695 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2696 {
2697 return HAL_TIMEOUT;
2698 }
2699
2700 /* Generate Stop */
2701 hi2c->Instance->CR1 |= I2C_CR1_STOP;
2702
2703 /* Read data from DR */
2704 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2705 hi2c->XferSize--;
2706 hi2c->XferCount--;
2707
2708 /* Read data from DR */
2709 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2710 hi2c->XferSize--;
2711 hi2c->XferCount--;
2712 }
2713 }
2714 else
2715 {
2716 /* Wait until RXNE flag is set */
2717 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2718 {
2719 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
2720 {
2721 return HAL_TIMEOUT;
2722 }
2723 else
2724 {
2725 return HAL_ERROR;
2726 }
2727 }
2728
2729 /* Read data from DR */
2730 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2731 hi2c->XferSize--;
2732 hi2c->XferCount--;
2733
2734 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2735 {
2736 /* Read data from DR */
2737 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2738 hi2c->XferSize--;
2739 hi2c->XferCount--;
2740 }
2741 }
2742 }
2743
2744 hi2c->State = HAL_I2C_STATE_READY;
2745 hi2c->Mode = HAL_I2C_MODE_NONE;
2746
2747 /* Process Unlocked */
2748 __HAL_UNLOCK(hi2c);
2749
2750 return HAL_OK;
2751 }
2752 else
2753 {
2754 return HAL_BUSY;
2755 }
2756 }
2757
2758 /**
2759 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2760 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2761 * the configuration information for the specified I2C.
2762 * @param DevAddress Target device address
2763 * @param MemAddress Internal memory address
2764 * @param MemAddSize Size of internal memory address
2765 * @param pData Pointer to data buffer
2766 * @param Size Amount of data to be sent
2767 * @retval HAL status
2768 */
2769 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2770 {
2771 __IO uint32_t count = 0U;
2772
2773 /* Check the parameters */
2774 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2775
2776 if(hi2c->State == HAL_I2C_STATE_READY)
2777 {
2778 /* Wait until BUSY flag is reset */
2779 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
2780 do
2781 {
2782 if(count-- == 0U)
2783 {
2784 hi2c->PreviousState = I2C_STATE_NONE;
2785 hi2c->State= HAL_I2C_STATE_READY;
2786
2787 /* Process Unlocked */
2788 __HAL_UNLOCK(hi2c);
2789
2790 return HAL_TIMEOUT;
2791 }
2792 }
2793 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2794
2795 /* Process Locked */
2796 __HAL_LOCK(hi2c);
2797
2798 /* Check if the I2C is already enabled */
2799 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2800 {
2801 /* Enable I2C peripheral */
2802 __HAL_I2C_ENABLE(hi2c);
2803 }
2804
2805 /* Disable Pos */
2806 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
2807
2808 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2809 hi2c->Mode = HAL_I2C_MODE_MEM;
2810 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2811
2812 /* Prepare transfer parameters */
2813 hi2c->pBuffPtr = pData;
2814 hi2c->XferSize = Size;
2815 hi2c->XferCount = Size;
2816 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2817 hi2c->Devaddress = DevAddress;
2818 hi2c->Memaddress = MemAddress;
2819 hi2c->MemaddSize = MemAddSize;
2820 hi2c->EventCount = 0U;
2821
2822 /* Generate Start */
2823 hi2c->Instance->CR1 |= I2C_CR1_START;
2824
2825 /* Process Unlocked */
2826 __HAL_UNLOCK(hi2c);
2827
2828 /* Note : The I2C interrupts must be enabled after unlocking current process
2829 to avoid the risk of I2C interrupt handle execution before current
2830 process unlock */
2831
2832 /* Enable EVT, BUF and ERR interrupt */
2833 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2834
2835 return HAL_OK;
2836 }
2837 else
2838 {
2839 return HAL_BUSY;
2840 }
2841 }
2842
2843 /**
2844 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2845 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2846 * the configuration information for the specified I2C.
2847 * @param DevAddress Target device address
2848 * @param MemAddress Internal memory address
2849 * @param MemAddSize Size of internal memory address
2850 * @param pData Pointer to data buffer
2851 * @param Size Amount of data to be sent
2852 * @retval HAL status
2853 */
2854 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2855 {
2856 __IO uint32_t count = 0U;
2857
2858 /* Check the parameters */
2859 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2860
2861 if(hi2c->State == HAL_I2C_STATE_READY)
2862 {
2863 /* Wait until BUSY flag is reset */
2864 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
2865 do
2866 {
2867 if(count-- == 0U)
2868 {
2869 hi2c->PreviousState = I2C_STATE_NONE;
2870 hi2c->State= HAL_I2C_STATE_READY;
2871
2872 /* Process Unlocked */
2873 __HAL_UNLOCK(hi2c);
2874
2875 return HAL_TIMEOUT;
2876 }
2877 }
2878 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2879
2880 /* Process Locked */
2881 __HAL_LOCK(hi2c);
2882
2883 /* Check if the I2C is already enabled */
2884 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2885 {
2886 /* Enable I2C peripheral */
2887 __HAL_I2C_ENABLE(hi2c);
2888 }
2889
2890 /* Disable Pos */
2891 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
2892
2893 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2894 hi2c->Mode = HAL_I2C_MODE_MEM;
2895 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2896
2897 /* Prepare transfer parameters */
2898 hi2c->pBuffPtr = pData;
2899 hi2c->XferSize = Size;
2900 hi2c->XferCount = Size;
2901 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2902 hi2c->Devaddress = DevAddress;
2903 hi2c->Memaddress = MemAddress;
2904 hi2c->MemaddSize = MemAddSize;
2905 hi2c->EventCount = 0U;
2906
2907 /* Enable Acknowledge */
2908 hi2c->Instance->CR1 |= I2C_CR1_ACK;
2909
2910 /* Generate Start */
2911 hi2c->Instance->CR1 |= I2C_CR1_START;
2912
2913 /* Process Unlocked */
2914 __HAL_UNLOCK(hi2c);
2915
2916 if(hi2c->XferSize > 0U)
2917 {
2918 /* Note : The I2C interrupts must be enabled after unlocking current process
2919 to avoid the risk of I2C interrupt handle execution before current
2920 process unlock */
2921
2922 /* Enable EVT, BUF and ERR interrupt */
2923 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2924 }
2925 return HAL_OK;
2926 }
2927 else
2928 {
2929 return HAL_BUSY;
2930 }
2931 }
2932
2933 /**
2934 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2935 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2936 * the configuration information for the specified I2C.
2937 * @param DevAddress Target device address
2938 * @param MemAddress Internal memory address
2939 * @param MemAddSize Size of internal memory address
2940 * @param pData Pointer to data buffer
2941 * @param Size Amount of data to be sent
2942 * @retval HAL status
2943 */
2944 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2945 {
2946 __IO uint32_t count = 0U;
2947
2948 uint32_t tickstart = 0x00U;
2949
2950 /* Init tickstart for timeout management*/
2951 tickstart = HAL_GetTick();
2952
2953 /* Check the parameters */
2954 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2955
2956 if(hi2c->State == HAL_I2C_STATE_READY)
2957 {
2958 /* Wait until BUSY flag is reset */
2959 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
2960 do
2961 {
2962 if(count-- == 0U)
2963 {
2964 hi2c->PreviousState = I2C_STATE_NONE;
2965 hi2c->State= HAL_I2C_STATE_READY;
2966
2967 /* Process Unlocked */
2968 __HAL_UNLOCK(hi2c);
2969
2970 return HAL_TIMEOUT;
2971 }
2972 }
2973 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2974
2975 /* Process Locked */
2976 __HAL_LOCK(hi2c);
2977
2978 /* Check if the I2C is already enabled */
2979 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2980 {
2981 /* Enable I2C peripheral */
2982 __HAL_I2C_ENABLE(hi2c);
2983 }
2984
2985 /* Disable Pos */
2986 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
2987
2988 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2989 hi2c->Mode = HAL_I2C_MODE_MEM;
2990 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2991
2992 /* Prepare transfer parameters */
2993 hi2c->pBuffPtr = pData;
2994 hi2c->XferSize = Size;
2995 hi2c->XferCount = Size;
2996 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2997
2998 if(hi2c->XferSize > 0U)
2999 {
3000 /* Set the I2C DMA transfer complete callback */
3001 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3002
3003 /* Set the DMA error callback */
3004 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3005
3006 /* Set the unused DMA callbacks to NULL */
3007 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3008 hi2c->hdmatx->XferM1CpltCallback = NULL;
3009 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
3010 hi2c->hdmatx->XferAbortCallback = NULL;
3011
3012 /* Enable the DMA Stream */
3013 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3014
3015 /* Send Slave Address and Memory Address */
3016 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3017 {
3018 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3019 {
3020 /* Process Unlocked */
3021 __HAL_UNLOCK(hi2c);
3022 return HAL_ERROR;
3023 }
3024 else
3025 {
3026 /* Process Unlocked */
3027 __HAL_UNLOCK(hi2c);
3028 return HAL_TIMEOUT;
3029 }
3030 }
3031
3032 /* Clear ADDR flag */
3033 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3034
3035 /* Process Unlocked */
3036 __HAL_UNLOCK(hi2c);
3037
3038 /* Note : The I2C interrupts must be enabled after unlocking current process
3039 to avoid the risk of I2C interrupt handle execution before current
3040 process unlock */
3041 /* Enable ERR interrupt */
3042 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3043
3044 /* Enable DMA Request */
3045 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3046 }
3047 return HAL_OK;
3048 }
3049 else
3050 {
3051 return HAL_BUSY;
3052 }
3053 }
3054
3055 /**
3056 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3057 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3058 * the configuration information for the specified I2C.
3059 * @param DevAddress Target device address
3060 * @param MemAddress Internal memory address
3061 * @param MemAddSize Size of internal memory address
3062 * @param pData Pointer to data buffer
3063 * @param Size Amount of data to be read
3064 * @retval HAL status
3065 */
3066 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3067 {
3068 uint32_t tickstart = 0x00U;
3069 __IO uint32_t count = 0U;
3070
3071 /* Init tickstart for timeout management*/
3072 tickstart = HAL_GetTick();
3073
3074 /* Check the parameters */
3075 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3076
3077 if(hi2c->State == HAL_I2C_STATE_READY)
3078 {
3079 /* Wait until BUSY flag is reset */
3080 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
3081 do
3082 {
3083 if(count-- == 0U)
3084 {
3085 hi2c->PreviousState = I2C_STATE_NONE;
3086 hi2c->State= HAL_I2C_STATE_READY;
3087
3088 /* Process Unlocked */
3089 __HAL_UNLOCK(hi2c);
3090
3091 return HAL_TIMEOUT;
3092 }
3093 }
3094 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3095
3096 /* Process Locked */
3097 __HAL_LOCK(hi2c);
3098
3099 /* Check if the I2C is already enabled */
3100 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3101 {
3102 /* Enable I2C peripheral */
3103 __HAL_I2C_ENABLE(hi2c);
3104 }
3105
3106 /* Disable Pos */
3107 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
3108
3109 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3110 hi2c->Mode = HAL_I2C_MODE_MEM;
3111 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3112
3113 /* Prepare transfer parameters */
3114 hi2c->pBuffPtr = pData;
3115 hi2c->XferCount = Size;
3116 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3117 hi2c->XferSize = hi2c->XferCount;
3118
3119 if(hi2c->XferSize > 0U)
3120 {
3121 /* Set the I2C DMA transfer complete callback */
3122 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3123
3124 /* Set the DMA error callback */
3125 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3126
3127 /* Set the unused DMA callbacks to NULL */
3128 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3129 hi2c->hdmarx->XferM1CpltCallback = NULL;
3130 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
3131 hi2c->hdmarx->XferAbortCallback = NULL;
3132
3133 /* Enable the DMA Stream */
3134 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3135
3136 /* Send Slave Address and Memory Address */
3137 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3138 {
3139 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3140 {
3141 /* Process Unlocked */
3142 __HAL_UNLOCK(hi2c);
3143 return HAL_ERROR;
3144 }
3145 else
3146 {
3147 /* Process Unlocked */
3148 __HAL_UNLOCK(hi2c);
3149 return HAL_TIMEOUT;
3150 }
3151 }
3152
3153 if(Size == 1U)
3154 {
3155 /* Disable Acknowledge */
3156 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
3157 }
3158 else
3159 {
3160 /* Enable Last DMA bit */
3161 hi2c->Instance->CR2 |= I2C_CR2_LAST;
3162 }
3163
3164 /* Clear ADDR flag */
3165 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3166
3167 /* Process Unlocked */
3168 __HAL_UNLOCK(hi2c);
3169
3170 /* Note : The I2C interrupts must be enabled after unlocking current process
3171 to avoid the risk of I2C interrupt handle execution before current
3172 process unlock */
3173 /* Enable ERR interrupt */
3174 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3175
3176 /* Enable DMA Request */
3177 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3178 }
3179 else
3180 {
3181 /* Send Slave Address and Memory Address */
3182 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3183 {
3184 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3185 {
3186 /* Process Unlocked */
3187 __HAL_UNLOCK(hi2c);
3188 return HAL_ERROR;
3189 }
3190 else
3191 {
3192 /* Process Unlocked */
3193 __HAL_UNLOCK(hi2c);
3194 return HAL_TIMEOUT;
3195 }
3196 }
3197
3198 /* Clear ADDR flag */
3199 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3200
3201 /* Generate Stop */
3202 hi2c->Instance->CR1 |= I2C_CR1_STOP;
3203
3204 hi2c->State = HAL_I2C_STATE_READY;
3205
3206 /* Process Unlocked */
3207 __HAL_UNLOCK(hi2c);
3208 }
3209
3210 return HAL_OK;
3211 }
3212 else
3213 {
3214 return HAL_BUSY;
3215 }
3216 }
3217
3218 /**
3219 * @brief Checks if target device is ready for communication.
3220 * @note This function is used with Memory devices
3221 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3222 * the configuration information for the specified I2C.
3223 * @param DevAddress Target device address
3224 * @param Trials Number of trials
3225 * @param Timeout Timeout duration
3226 * @retval HAL status
3227 */
3228 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3229 {
3230 uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
3231
3232 /* Get tick */
3233 tickstart = HAL_GetTick();
3234
3235 if(hi2c->State == HAL_I2C_STATE_READY)
3236 {
3237 /* Wait until BUSY flag is reset */
3238 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3239 {
3240 return HAL_BUSY;
3241 }
3242
3243 /* Process Locked */
3244 __HAL_LOCK(hi2c);
3245
3246 /* Check if the I2C is already enabled */
3247 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3248 {
3249 /* Enable I2C peripheral */
3250 __HAL_I2C_ENABLE(hi2c);
3251 }
3252
3253 /* Disable Pos */
3254 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
3255
3256 hi2c->State = HAL_I2C_STATE_BUSY;
3257 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3258 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3259
3260 do
3261 {
3262 /* Generate Start */
3263 hi2c->Instance->CR1 |= I2C_CR1_START;
3264
3265 /* Wait until SB flag is set */
3266 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3267 {
3268 return HAL_TIMEOUT;
3269 }
3270
3271 /* Send slave address */
3272 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3273
3274 /* Wait until ADDR or AF flag are set */
3275 /* Get tick */
3276 tickstart = HAL_GetTick();
3277
3278 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3279 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3280 tmp3 = hi2c->State;
3281 while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
3282 {
3283 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
3284 {
3285 hi2c->State = HAL_I2C_STATE_TIMEOUT;
3286 }
3287 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3288 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3289 tmp3 = hi2c->State;
3290 }
3291
3292 hi2c->State = HAL_I2C_STATE_READY;
3293
3294 /* Check if the ADDR flag has been set */
3295 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3296 {
3297 /* Generate Stop */
3298 hi2c->Instance->CR1 |= I2C_CR1_STOP;
3299
3300 /* Clear ADDR Flag */
3301 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3302
3303 /* Wait until BUSY flag is reset */
3304 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3305 {
3306 return HAL_TIMEOUT;
3307 }
3308
3309 hi2c->State = HAL_I2C_STATE_READY;
3310
3311 /* Process Unlocked */
3312 __HAL_UNLOCK(hi2c);
3313
3314 return HAL_OK;
3315 }
3316 else
3317 {
3318 /* Generate Stop */
3319 hi2c->Instance->CR1 |= I2C_CR1_STOP;
3320
3321 /* Clear AF Flag */
3322 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3323
3324 /* Wait until BUSY flag is reset */
3325 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3326 {
3327 return HAL_TIMEOUT;
3328 }
3329 }
3330 }while(I2C_Trials++ < Trials);
3331
3332 hi2c->State = HAL_I2C_STATE_READY;
3333
3334 /* Process Unlocked */
3335 __HAL_UNLOCK(hi2c);
3336
3337 return HAL_ERROR;
3338 }
3339 else
3340 {
3341 return HAL_BUSY;
3342 }
3343 }
3344
3345 /**
3346 * @brief This function handles I2C event interrupt request.
3347 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3348 * the configuration information for the specified I2C.
3349 * @retval None
3350 */
3351 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
3352 {
3353 uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
3354 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
3355 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
3356
3357 uint32_t CurrentMode = hi2c->Mode;
3358
3359 /* Master or Memory mode selected */
3360 if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
3361 {
3362 /* SB Set ----------------------------------------------------------------*/
3363 if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3364 {
3365 I2C_Master_SB(hi2c);
3366 }
3367 /* ADD10 Set -------------------------------------------------------------*/
3368 else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3369 {
3370 I2C_Master_ADD10(hi2c);
3371 }
3372 /* ADDR Set --------------------------------------------------------------*/
3373 else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3374 {
3375 I2C_Master_ADDR(hi2c);
3376 }
3377
3378 /* I2C in mode Transmitter -----------------------------------------------*/
3379 if((sr2itflags & I2C_FLAG_TRA) != RESET)
3380 {
3381 /* TXE set and BTF reset -----------------------------------------------*/
3382 if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
3383 {
3384 I2C_MasterTransmit_TXE(hi2c);
3385 }
3386 /* BTF set -------------------------------------------------------------*/
3387 else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3388 {
3389 I2C_MasterTransmit_BTF(hi2c);
3390 }
3391 }
3392 /* I2C in mode Receiver --------------------------------------------------*/
3393 else
3394 {
3395 /* RXNE set and BTF reset -----------------------------------------------*/
3396 if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
3397 {
3398 I2C_MasterReceive_RXNE(hi2c);
3399 }
3400 /* BTF set -------------------------------------------------------------*/
3401 else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3402 {
3403 I2C_MasterReceive_BTF(hi2c);
3404 }
3405 }
3406 }
3407 /* Slave mode selected */
3408 else
3409 {
3410 /* ADDR set --------------------------------------------------------------*/
3411 if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3412 {
3413 I2C_Slave_ADDR(hi2c);
3414 }
3415 /* STOPF set --------------------------------------------------------------*/
3416 else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3417 {
3418 I2C_Slave_STOPF(hi2c);
3419 }
3420 /* I2C in mode Transmitter -----------------------------------------------*/
3421 else if((sr2itflags & I2C_FLAG_TRA) != RESET)
3422 {
3423 /* TXE set and BTF reset -----------------------------------------------*/
3424 if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
3425 {
3426 I2C_SlaveTransmit_TXE(hi2c);
3427 }
3428 /* BTF set -------------------------------------------------------------*/
3429 else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3430 {
3431 I2C_SlaveTransmit_BTF(hi2c);
3432 }
3433 }
3434 /* I2C in mode Receiver --------------------------------------------------*/
3435 else
3436 {
3437 /* RXNE set and BTF reset ----------------------------------------------*/
3438 if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
3439 {
3440 I2C_SlaveReceive_RXNE(hi2c);
3441 }
3442 /* BTF set -------------------------------------------------------------*/
3443 else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3444 {
3445 I2C_SlaveReceive_BTF(hi2c);
3446 }
3447 }
3448 }
3449 }
3450
3451 /**
3452 * @brief This function handles I2C error interrupt request.
3453 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3454 * the configuration information for the specified I2C.
3455 * @retval None
3456 */
3457 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
3458 {
3459 uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
3460 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
3461 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
3462
3463 /* I2C Bus error interrupt occurred ----------------------------------------*/
3464 if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
3465 {
3466 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
3467
3468 /* Clear BERR flag */
3469 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
3470 }
3471
3472 /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
3473 if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
3474 {
3475 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
3476
3477 /* Clear ARLO flag */
3478 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
3479 }
3480
3481 /* I2C Acknowledge failure error interrupt occurred ------------------------*/
3482 if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
3483 {
3484 tmp1 = hi2c->Mode;
3485 tmp2 = hi2c->XferCount;
3486 tmp3 = hi2c->State;
3487 tmp4 = hi2c->PreviousState;
3488 if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
3489 ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
3490 ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
3491 {
3492 I2C_Slave_AF(hi2c);
3493 }
3494 else
3495 {
3496 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3497
3498 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
3499 if(hi2c->Mode == HAL_I2C_MODE_MASTER)
3500 {
3501 /* Generate Stop */
3502 SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
3503 }
3504
3505 /* Clear AF flag */
3506 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3507 }
3508 }
3509
3510 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
3511 if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
3512 {
3513 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
3514 /* Clear OVR flag */
3515 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
3516 }
3517
3518 /* Call the Error Callback in case of Error detected -----------------------*/
3519 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
3520 {
3521 I2C_ITError(hi2c);
3522 }
3523 }
3524
3525 /**
3526 * @brief Master Tx Transfer completed callback.
3527 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3528 * the configuration information for the specified I2C.
3529 * @retval None
3530 */
3531 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
3532 {
3533 /* Prevent unused argument(s) compilation warning */
3534 UNUSED(hi2c);
3535
3536 /* NOTE : This function should not be modified, when the callback is needed,
3537 the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
3538 */
3539 }
3540
3541 /**
3542 * @brief Master Rx Transfer completed callback.
3543 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3544 * the configuration information for the specified I2C.
3545 * @retval None
3546 */
3547 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
3548 {
3549 /* Prevent unused argument(s) compilation warning */
3550 UNUSED(hi2c);
3551
3552 /* NOTE : This function should not be modified, when the callback is needed,
3553 the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
3554 */
3555 }
3556
3557 /** @brief Slave Tx Transfer completed callback.
3558 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3559 * the configuration information for the specified I2C.
3560 * @retval None
3561 */
3562 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
3563 {
3564 /* Prevent unused argument(s) compilation warning */
3565 UNUSED(hi2c);
3566
3567 /* NOTE : This function should not be modified, when the callback is needed,
3568 the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
3569 */
3570 }
3571
3572 /**
3573 * @brief Slave Rx Transfer completed callback.
3574 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3575 * the configuration information for the specified I2C.
3576 * @retval None
3577 */
3578 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
3579 {
3580 /* Prevent unused argument(s) compilation warning */
3581 UNUSED(hi2c);
3582
3583 /* NOTE : This function should not be modified, when the callback is needed,
3584 the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
3585 */
3586 }
3587
3588 /**
3589 * @brief Slave Address Match callback.
3590 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3591 * the configuration information for the specified I2C.
3592 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
3593 * @param AddrMatchCode Address Match Code
3594 * @retval None
3595 */
3596 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
3597 {
3598 /* Prevent unused argument(s) compilation warning */
3599 UNUSED(hi2c);
3600 UNUSED(TransferDirection);
3601 UNUSED(AddrMatchCode);
3602
3603 /* NOTE : This function should not be modified, when the callback is needed,
3604 the HAL_I2C_AddrCallback can be implemented in the user file
3605 */
3606 }
3607
3608 /**
3609 * @brief Listen Complete callback.
3610 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3611 * the configuration information for the specified I2C.
3612 * @retval None
3613 */
3614 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
3615 {
3616 /* Prevent unused argument(s) compilation warning */
3617 UNUSED(hi2c);
3618
3619 /* NOTE : This function should not be modified, when the callback is needed,
3620 the HAL_I2C_ListenCpltCallback can be implemented in the user file
3621 */
3622 }
3623
3624 /**
3625 * @brief Memory Tx Transfer completed callback.
3626 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3627 * the configuration information for the specified I2C.
3628 * @retval None
3629 */
3630 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
3631 {
3632 /* Prevent unused argument(s) compilation warning */
3633 UNUSED(hi2c);
3634
3635 /* NOTE : This function should not be modified, when the callback is needed,
3636 the HAL_I2C_MemTxCpltCallback can be implemented in the user file
3637 */
3638 }
3639
3640 /**
3641 * @brief Memory Rx Transfer completed callback.
3642 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3643 * the configuration information for the specified I2C.
3644 * @retval None
3645 */
3646 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
3647 {
3648 /* Prevent unused argument(s) compilation warning */
3649 UNUSED(hi2c);
3650
3651 /* NOTE : This function should not be modified, when the callback is needed,
3652 the HAL_I2C_MemRxCpltCallback can be implemented in the user file
3653 */
3654 }
3655
3656 /**
3657 * @brief I2C error callback.
3658 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3659 * the configuration information for the specified I2C.
3660 * @retval None
3661 */
3662 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
3663 {
3664 /* Prevent unused argument(s) compilation warning */
3665 UNUSED(hi2c);
3666
3667 /* NOTE : This function should not be modified, when the callback is needed,
3668 the HAL_I2C_ErrorCallback can be implemented in the user file
3669 */
3670 }
3671
3672 /**
3673 * @brief I2C abort callback.
3674 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3675 * the configuration information for the specified I2C.
3676 * @retval None
3677 */
3678 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
3679 {
3680 /* Prevent unused argument(s) compilation warning */
3681 UNUSED(hi2c);
3682
3683 /* NOTE : This function should not be modified, when the callback is needed,
3684 the HAL_I2C_AbortCpltCallback could be implemented in the user file
3685 */
3686 }
3687
3688 /**
3689 * @}
3690 */
3691
3692 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
3693 * @brief Peripheral State and Errors functions
3694 *
3695 @verbatim
3696 ===============================================================================
3697 ##### Peripheral State, Mode and Error functions #####
3698 ===============================================================================
3699 [..]
3700 This subsection permits to get in run-time the status of the peripheral
3701 and the data flow.
3702
3703 @endverbatim
3704 * @{
3705 */
3706
3707 /**
3708 * @brief Return the I2C handle state.
3709 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3710 * the configuration information for the specified I2C.
3711 * @retval HAL state
3712 */
3713 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
3714 {
3715 /* Return I2C handle state */
3716 return hi2c->State;
3717 }
3718
3719 /**
3720 * @brief Return the I2C Master, Slave, Memory or no mode.
3721 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3722 * the configuration information for I2C module
3723 * @retval HAL mode
3724 */
3725 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
3726 {
3727 return hi2c->Mode;
3728 }
3729
3730 /**
3731 * @brief Return the I2C error code
3732 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3733 * the configuration information for the specified I2C.
3734 * @retval I2C Error Code
3735 */
3736 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
3737 {
3738 return hi2c->ErrorCode;
3739 }
3740
3741 /**
3742 * @}
3743 */
3744
3745 /**
3746 * @brief Handle TXE flag for Master
3747 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3748 * the configuration information for I2C module
3749 * @retval HAL status
3750 */
3751 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
3752 {
3753 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
3754 uint32_t CurrentState = hi2c->State;
3755 uint32_t CurrentMode = hi2c->Mode;
3756 uint32_t CurrentXferOptions = hi2c->XferOptions;
3757
3758 if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
3759 {
3760 /* Call TxCpltCallback() directly if no stop mode is set */
3761 if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
3762 {
3763 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3764
3765 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
3766 hi2c->Mode = HAL_I2C_MODE_NONE;
3767 hi2c->State = HAL_I2C_STATE_READY;
3768
3769 HAL_I2C_MasterTxCpltCallback(hi2c);
3770 }
3771 else /* Generate Stop condition then Call TxCpltCallback() */
3772 {
3773 /* Disable EVT, BUF and ERR interrupt */
3774 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3775
3776 /* Generate Stop */
3777 hi2c->Instance->CR1 |= I2C_CR1_STOP;
3778
3779 hi2c->PreviousState = I2C_STATE_NONE;
3780 hi2c->State = HAL_I2C_STATE_READY;
3781
3782 if(hi2c->Mode == HAL_I2C_MODE_MEM)
3783 {
3784 hi2c->Mode = HAL_I2C_MODE_NONE;
3785 HAL_I2C_MemTxCpltCallback(hi2c);
3786 }
3787 else
3788 {
3789 hi2c->Mode = HAL_I2C_MODE_NONE;
3790 HAL_I2C_MasterTxCpltCallback(hi2c);
3791 }
3792 }
3793 }
3794 else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
3795 ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
3796 {
3797 if(hi2c->XferCount == 0U)
3798 {
3799 /* Disable BUF interrupt */
3800 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
3801 }
3802 else
3803 {
3804 if(hi2c->Mode == HAL_I2C_MODE_MEM)
3805 {
3806 if(hi2c->EventCount == 0)
3807 {
3808 /* If Memory address size is 8Bit */
3809 if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
3810 {
3811 /* Send Memory Address */
3812 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
3813
3814 hi2c->EventCount += 2;
3815 }
3816 /* If Memory address size is 16Bit */
3817 else
3818 {
3819 /* Send MSB of Memory Address */
3820 hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
3821
3822 hi2c->EventCount++;
3823 }
3824 }
3825 else if(hi2c->EventCount == 1)
3826 {
3827 /* Send LSB of Memory Address */
3828 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
3829
3830 hi2c->EventCount++;
3831 }
3832 else if(hi2c->EventCount == 2)
3833 {
3834 if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
3835 {
3836 /* Generate Restart */
3837 hi2c->Instance->CR1 |= I2C_CR1_START;
3838 }
3839 else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
3840 {
3841 /* Write data to DR */
3842 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
3843 hi2c->XferCount--;
3844 }
3845 }
3846 }
3847 else
3848 {
3849 /* Write data to DR */
3850 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
3851 hi2c->XferCount--;
3852 }
3853 }
3854 }
3855 return HAL_OK;
3856 }
3857
3858 /**
3859 * @brief Handle BTF flag for Master transmitter
3860 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3861 * the configuration information for I2C module
3862 * @retval HAL status
3863 */
3864 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
3865 {
3866 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
3867 uint32_t CurrentXferOptions = hi2c->XferOptions;
3868
3869 if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
3870 {
3871 if(hi2c->XferCount != 0U)
3872 {
3873 /* Write data to DR */
3874 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
3875 hi2c->XferCount--;
3876 }
3877 else
3878 {
3879 /* Call TxCpltCallback() directly if no stop mode is set */
3880 if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
3881 {
3882 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3883
3884 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
3885 hi2c->Mode = HAL_I2C_MODE_NONE;
3886 hi2c->State = HAL_I2C_STATE_READY;
3887
3888 HAL_I2C_MasterTxCpltCallback(hi2c);
3889 }
3890 else /* Generate Stop condition then Call TxCpltCallback() */
3891 {
3892 /* Disable EVT, BUF and ERR interrupt */
3893 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3894
3895 /* Generate Stop */
3896 hi2c->Instance->CR1 |= I2C_CR1_STOP;
3897
3898 hi2c->PreviousState = I2C_STATE_NONE;
3899 hi2c->State = HAL_I2C_STATE_READY;
3900
3901 if(hi2c->Mode == HAL_I2C_MODE_MEM)
3902 {
3903 hi2c->Mode = HAL_I2C_MODE_NONE;
3904
3905 HAL_I2C_MemTxCpltCallback(hi2c);
3906 }
3907 else
3908 {
3909 hi2c->Mode = HAL_I2C_MODE_NONE;
3910
3911 HAL_I2C_MasterTxCpltCallback(hi2c);
3912 }
3913 }
3914 }
3915 }
3916 return HAL_OK;
3917 }
3918
3919 /**
3920 * @brief Handle RXNE flag for Master
3921 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3922 * the configuration information for I2C module
3923 * @retval HAL status
3924 */
3925 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
3926 {
3927 if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
3928 {
3929 uint32_t tmp = 0U;
3930
3931 tmp = hi2c->XferCount;
3932 if(tmp > 3U)
3933 {
3934 /* Read data from DR */
3935 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
3936 hi2c->XferCount--;
3937
3938 if(hi2c->XferCount == 3)
3939 {
3940 /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
3941 on BTF subroutine */
3942 /* Disable BUF interrupt */
3943 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
3944 }
3945 }
3946 else if((tmp == 1U) || (tmp == 0U))
3947 {
3948 /* Disable Acknowledge */
3949 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
3950
3951 /* Disable EVT, BUF and ERR interrupt */
3952 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3953
3954 /* Read data from DR */
3955 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
3956 hi2c->XferCount--;
3957
3958 hi2c->State = HAL_I2C_STATE_READY;
3959 hi2c->PreviousState = I2C_STATE_NONE;
3960
3961 if(hi2c->Mode == HAL_I2C_MODE_MEM)
3962 {
3963 hi2c->Mode = HAL_I2C_MODE_NONE;
3964 HAL_I2C_MemRxCpltCallback(hi2c);
3965 }
3966 else
3967 {
3968 hi2c->Mode = HAL_I2C_MODE_NONE;
3969 HAL_I2C_MasterRxCpltCallback(hi2c);
3970 }
3971 }
3972 }
3973 return HAL_OK;
3974 }
3975
3976 /**
3977 * @brief Handle BTF flag for Master receiver
3978 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3979 * the configuration information for I2C module
3980 * @retval HAL status
3981 */
3982 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
3983 {
3984 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
3985 uint32_t CurrentXferOptions = hi2c->XferOptions;
3986
3987 if(hi2c->XferCount == 4U)
3988 {
3989 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
3990 on BTF subroutine if there is a reception delay between N-1 and N byte */
3991 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
3992
3993 /* Read data from DR */
3994 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
3995 hi2c->XferCount--;
3996 }
3997 else if(hi2c->XferCount == 3U)
3998 {
3999 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
4000 on BTF subroutine if there is a reception delay between N-1 and N byte */
4001 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
4002
4003 /* Disable Acknowledge */
4004 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4005
4006 /* Read data from DR */
4007 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4008 hi2c->XferCount--;
4009 }
4010 else if(hi2c->XferCount == 2U)
4011 {
4012 /* Prepare next transfer or stop current transfer */
4013 if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME))
4014 {
4015 /* Disable Acknowledge */
4016 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4017
4018 /* Generate ReStart */
4019 hi2c->Instance->CR1 |= I2C_CR1_START;
4020 }
4021 else
4022 {
4023 /* Generate Stop */
4024 hi2c->Instance->CR1 |= I2C_CR1_STOP;
4025 }
4026
4027 /* Read data from DR */
4028 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4029 hi2c->XferCount--;
4030
4031 /* Read data from DR */
4032 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4033 hi2c->XferCount--;
4034
4035 /* Disable EVT and ERR interrupt */
4036 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4037
4038 hi2c->State = HAL_I2C_STATE_READY;
4039 hi2c->PreviousState = I2C_STATE_NONE;
4040
4041 if(hi2c->Mode == HAL_I2C_MODE_MEM)
4042 {
4043 hi2c->Mode = HAL_I2C_MODE_NONE;
4044
4045 HAL_I2C_MemRxCpltCallback(hi2c);
4046 }
4047 else
4048 {
4049 hi2c->Mode = HAL_I2C_MODE_NONE;
4050
4051 HAL_I2C_MasterRxCpltCallback(hi2c);
4052 }
4053 }
4054 else
4055 {
4056 /* Read data from DR */
4057 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4058 hi2c->XferCount--;
4059 }
4060 return HAL_OK;
4061 }
4062
4063 /**
4064 * @brief Handle SB flag for Master
4065 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4066 * the configuration information for I2C module
4067 * @retval HAL status
4068 */
4069 static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
4070 {
4071 if(hi2c->Mode == HAL_I2C_MODE_MEM)
4072 {
4073 if(hi2c->EventCount == 0U)
4074 {
4075 /* Send slave address */
4076 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
4077 }
4078 else
4079 {
4080 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
4081 }
4082 }
4083 else
4084 {
4085 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
4086 {
4087 /* Send slave 7 Bits address */
4088 if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
4089 {
4090 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
4091 }
4092 else
4093 {
4094 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
4095 }
4096 }
4097 else
4098 {
4099 if(hi2c->EventCount == 0U)
4100 {
4101 /* Send header of slave address */
4102 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
4103 }
4104 else if(hi2c->EventCount == 1U)
4105 {
4106 /* Send header of slave address */
4107 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
4108 }
4109 }
4110 }
4111
4112 return HAL_OK;
4113 }
4114
4115 /**
4116 * @brief Handle ADD10 flag for Master
4117 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4118 * the configuration information for I2C module
4119 * @retval HAL status
4120 */
4121 static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
4122 {
4123 /* Send slave address */
4124 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
4125
4126 return HAL_OK;
4127 }
4128
4129 /**
4130 * @brief Handle ADDR flag for Master
4131 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4132 * the configuration information for I2C module
4133 * @retval HAL status
4134 */
4135 static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
4136 {
4137 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
4138 uint32_t CurrentMode = hi2c->Mode;
4139 uint32_t CurrentXferOptions = hi2c->XferOptions;
4140 uint32_t Prev_State = hi2c->PreviousState;
4141
4142 if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
4143 {
4144 if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
4145 {
4146 /* Clear ADDR flag */
4147 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4148 }
4149 else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
4150 {
4151 /* Clear ADDR flag */
4152 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4153
4154 /* Generate Restart */
4155 hi2c->Instance->CR1 |= I2C_CR1_START;
4156
4157 hi2c->EventCount++;
4158 }
4159 else
4160 {
4161 if(hi2c->XferCount == 0U)
4162 {
4163 /* Clear ADDR flag */
4164 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4165
4166 /* Generate Stop */
4167 hi2c->Instance->CR1 |= I2C_CR1_STOP;
4168 }
4169 else if(hi2c->XferCount == 1U)
4170 {
4171 if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
4172 {
4173 /* Disable Acknowledge */
4174 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4175
4176 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4177 {
4178 /* Disable Acknowledge */
4179 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4180
4181 /* Clear ADDR flag */
4182 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4183 }
4184 else
4185 {
4186 /* Clear ADDR flag */
4187 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4188
4189 /* Generate Stop */
4190 hi2c->Instance->CR1 |= I2C_CR1_STOP;
4191 }
4192 }
4193 /* Prepare next transfer or stop current transfer */
4194 else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
4195 && (Prev_State != I2C_STATE_MASTER_BUSY_RX))
4196 {
4197 if(hi2c->XferOptions != I2C_NEXT_FRAME)
4198 {
4199 /* Disable Acknowledge */
4200 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4201 }
4202 else
4203 {
4204 /* Enable Acknowledge */
4205 hi2c->Instance->CR1 |= I2C_CR1_ACK;
4206 }
4207
4208 /* Clear ADDR flag */
4209 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4210 }
4211 else
4212 {
4213 /* Disable Acknowledge */
4214 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4215
4216 /* Clear ADDR flag */
4217 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4218
4219 /* Generate Stop */
4220 hi2c->Instance->CR1 |= I2C_CR1_STOP;
4221 }
4222 }
4223 else if(hi2c->XferCount == 2U)
4224 {
4225 if(hi2c->XferOptions != I2C_NEXT_FRAME)
4226 {
4227 /* Disable Acknowledge */
4228 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4229
4230 /* Enable Pos */
4231 hi2c->Instance->CR1 |= I2C_CR1_POS;
4232 }
4233 else
4234 {
4235 /* Enable Acknowledge */
4236 hi2c->Instance->CR1 |= I2C_CR1_ACK;
4237 }
4238
4239 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4240 {
4241 /* Enable Last DMA bit */
4242 hi2c->Instance->CR2 |= I2C_CR2_LAST;
4243 }
4244
4245 /* Clear ADDR flag */
4246 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4247 }
4248 else
4249 {
4250 /* Enable Acknowledge */
4251 hi2c->Instance->CR1 |= I2C_CR1_ACK;
4252
4253 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4254 {
4255 /* Enable Last DMA bit */
4256 hi2c->Instance->CR2 |= I2C_CR2_LAST;
4257 }
4258
4259 /* Clear ADDR flag */
4260 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4261 }
4262
4263 /* Reset Event counter */
4264 hi2c->EventCount = 0U;
4265 }
4266 }
4267 else
4268 {
4269 /* Clear ADDR flag */
4270 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4271 }
4272
4273 return HAL_OK;
4274 }
4275
4276 /**
4277 * @brief Handle TXE flag for Slave
4278 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4279 * the configuration information for I2C module
4280 * @retval HAL status
4281 */
4282 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
4283 {
4284 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4285 uint32_t CurrentState = hi2c->State;
4286
4287 if(hi2c->XferCount != 0U)
4288 {
4289 /* Write data to DR */
4290 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
4291 hi2c->XferCount--;
4292
4293 if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
4294 {
4295 /* Last Byte is received, disable Interrupt */
4296 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
4297
4298 /* Set state at HAL_I2C_STATE_LISTEN */
4299 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
4300 hi2c->State = HAL_I2C_STATE_LISTEN;
4301
4302 /* Call the Tx complete callback to inform upper layer of the end of receive process */
4303 HAL_I2C_SlaveTxCpltCallback(hi2c);
4304 }
4305 }
4306 return HAL_OK;
4307 }
4308
4309 /**
4310 * @brief Handle BTF flag for Slave transmitter
4311 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4312 * the configuration information for I2C module
4313 * @retval HAL status
4314 */
4315 static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
4316 {
4317 if(hi2c->XferCount != 0U)
4318 {
4319 /* Write data to DR */
4320 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
4321 hi2c->XferCount--;
4322 }
4323 return HAL_OK;
4324 }
4325
4326 /**
4327 * @brief Handle RXNE flag for Slave
4328 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4329 * the configuration information for I2C module
4330 * @retval HAL status
4331 */
4332 static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
4333 {
4334 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4335 uint32_t CurrentState = hi2c->State;
4336
4337 if(hi2c->XferCount != 0U)
4338 {
4339 /* Read data from DR */
4340 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4341 hi2c->XferCount--;
4342
4343 if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
4344 {
4345 /* Last Byte is received, disable Interrupt */
4346 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
4347
4348 /* Set state at HAL_I2C_STATE_LISTEN */
4349 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
4350 hi2c->State = HAL_I2C_STATE_LISTEN;
4351
4352 /* Call the Rx complete callback to inform upper layer of the end of receive process */
4353 HAL_I2C_SlaveRxCpltCallback(hi2c);
4354 }
4355 }
4356 return HAL_OK;
4357 }
4358
4359 /**
4360 * @brief Handle BTF flag for Slave receiver
4361 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4362 * the configuration information for I2C module
4363 * @retval HAL status
4364 */
4365 static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
4366 {
4367 if(hi2c->XferCount != 0U)
4368 {
4369 /* Read data from DR */
4370 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4371 hi2c->XferCount--;
4372 }
4373 return HAL_OK;
4374 }
4375
4376 /**
4377 * @brief Handle ADD flag for Slave
4378 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4379 * the configuration information for I2C module
4380 * @retval HAL status
4381 */
4382 static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
4383 {
4384 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
4385 uint16_t SlaveAddrCode = 0U;
4386
4387 /* Transfer Direction requested by Master */
4388 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
4389 {
4390 TransferDirection = I2C_DIRECTION_TRANSMIT;
4391 }
4392
4393 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
4394 {
4395 SlaveAddrCode = hi2c->Init.OwnAddress1;
4396 }
4397 else
4398 {
4399 SlaveAddrCode = hi2c->Init.OwnAddress2;
4400 }
4401
4402 /* Call Slave Addr callback */
4403 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
4404
4405 return HAL_OK;
4406 }
4407
4408 /**
4409 * @brief Handle STOPF flag for Slave
4410 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4411 * the configuration information for I2C module
4412 * @retval HAL status
4413 */
4414 static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
4415 {
4416 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
4417 uint32_t CurrentState = hi2c->State;
4418
4419 /* Disable EVT, BUF and ERR interrupt */
4420 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4421
4422 /* Clear STOPF flag */
4423 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
4424
4425 /* Disable Acknowledge */
4426 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4427
4428 /* If a DMA is ongoing, Update handle size context */
4429 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4430 {
4431 if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
4432 {
4433 hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
4434 }
4435 else
4436 {
4437 hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
4438 }
4439 }
4440
4441 /* All data are not transferred, so set error code accordingly */
4442 if(hi2c->XferCount != 0U)
4443 {
4444 /* Store Last receive data if any */
4445 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
4446 {
4447 /* Read data from DR */
4448 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4449 hi2c->XferCount--;
4450 }
4451
4452 /* Store Last receive data if any */
4453 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
4454 {
4455 /* Read data from DR */
4456 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4457 hi2c->XferCount--;
4458 }
4459
4460 /* Set ErrorCode corresponding to a Non-Acknowledge */
4461 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4462 }
4463
4464 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4465 {
4466 /* Call the corresponding callback to inform upper layer of End of Transfer */
4467 I2C_ITError(hi2c);
4468 }
4469 else
4470 {
4471 if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
4472 (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
4473 {
4474 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4475 hi2c->PreviousState = I2C_STATE_NONE;
4476 hi2c->State = HAL_I2C_STATE_READY;
4477 hi2c->Mode = HAL_I2C_MODE_NONE;
4478
4479 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4480 HAL_I2C_ListenCpltCallback(hi2c);
4481 }
4482 else
4483 {
4484 if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
4485 {
4486 hi2c->PreviousState = I2C_STATE_NONE;
4487 hi2c->State = HAL_I2C_STATE_READY;
4488 hi2c->Mode = HAL_I2C_MODE_NONE;
4489
4490 HAL_I2C_SlaveRxCpltCallback(hi2c);
4491 }
4492 }
4493 }
4494 return HAL_OK;
4495 }
4496
4497 /**
4498 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4499 * the configuration information for I2C module
4500 * @retval HAL status
4501 */
4502 static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
4503 {
4504 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4505 uint32_t CurrentState = hi2c->State;
4506 uint32_t CurrentXferOptions = hi2c->XferOptions;
4507
4508 if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
4509 (CurrentState == HAL_I2C_STATE_LISTEN))
4510 {
4511 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4512
4513 /* Disable EVT, BUF and ERR interrupt */
4514 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4515
4516 /* Clear AF flag */
4517 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4518
4519 /* Disable Acknowledge */
4520 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4521
4522 hi2c->PreviousState = I2C_STATE_NONE;
4523 hi2c->State = HAL_I2C_STATE_READY;
4524 hi2c->Mode = HAL_I2C_MODE_NONE;
4525
4526 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4527 HAL_I2C_ListenCpltCallback(hi2c);
4528 }
4529 else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
4530 {
4531 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4532 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
4533 hi2c->State = HAL_I2C_STATE_READY;
4534 hi2c->Mode = HAL_I2C_MODE_NONE;
4535
4536 /* Disable EVT, BUF and ERR interrupt */
4537 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4538
4539 /* Clear AF flag */
4540 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4541
4542 /* Disable Acknowledge */
4543 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
4544
4545 HAL_I2C_SlaveTxCpltCallback(hi2c);
4546 }
4547 else
4548 {
4549 /* Clear AF flag only */
4550 /* State Listen, but XferOptions == FIRST or NEXT */
4551 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4552 }
4553
4554 return HAL_OK;
4555 }
4556
4557 /**
4558 * @brief I2C interrupts error process
4559 * @param hi2c I2C handle.
4560 * @retval None
4561 */
4562 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
4563 {
4564 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
4565 uint32_t CurrentState = hi2c->State;
4566
4567 if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
4568 {
4569 /* keep HAL_I2C_STATE_LISTEN */
4570 hi2c->PreviousState = I2C_STATE_NONE;
4571 hi2c->State = HAL_I2C_STATE_LISTEN;
4572 }
4573 else
4574 {
4575 /* If state is an abort treatment on going, don't change state */
4576 /* This change will be do later */
4577 if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
4578 {
4579 hi2c->State = HAL_I2C_STATE_READY;
4580 }
4581 hi2c->PreviousState = I2C_STATE_NONE;
4582 hi2c->Mode = HAL_I2C_MODE_NONE;
4583 }
4584
4585 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
4586 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
4587
4588 /* Abort DMA transfer */
4589 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4590 {
4591 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
4592
4593 if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
4594 {
4595 /* Set the DMA Abort callback :
4596 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4597 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4598
4599 if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4600 {
4601 /* Disable I2C peripheral to prevent dummy data in buffer */
4602 __HAL_I2C_DISABLE(hi2c);
4603
4604 hi2c->State = HAL_I2C_STATE_READY;
4605
4606 /* Call Directly XferAbortCallback function in case of error */
4607 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4608 }
4609 }
4610 else
4611 {
4612 /* Set the DMA Abort callback :
4613 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4614 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4615
4616 if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4617 {
4618 /* Store Last receive data if any */
4619 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
4620 {
4621 /* Read data from DR */
4622 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4623 }
4624
4625 /* Disable I2C peripheral to prevent dummy data in buffer */
4626 __HAL_I2C_DISABLE(hi2c);
4627
4628 hi2c->State = HAL_I2C_STATE_READY;
4629
4630 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
4631 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4632 }
4633 }
4634 }
4635 else if(hi2c->State == HAL_I2C_STATE_ABORT)
4636 {
4637 hi2c->State = HAL_I2C_STATE_READY;
4638 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4639
4640 /* Store Last receive data if any */
4641 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
4642 {
4643 /* Read data from DR */
4644 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4645 }
4646
4647 /* Disable I2C peripheral to prevent dummy data in buffer */
4648 __HAL_I2C_DISABLE(hi2c);
4649
4650 /* Call the corresponding callback to inform upper layer of End of Transfer */
4651 HAL_I2C_AbortCpltCallback(hi2c);
4652 }
4653 else
4654 {
4655 /* Store Last receive data if any */
4656 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
4657 {
4658 /* Read data from DR */
4659 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4660 }
4661
4662 /* Call user error callback */
4663 HAL_I2C_ErrorCallback(hi2c);
4664 }
4665 /* STOP Flag is not set after a NACK reception */
4666 /* So may inform upper layer that listen phase is stopped */
4667 /* during NACK error treatment */
4668 if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
4669 {
4670 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4671 hi2c->PreviousState = I2C_STATE_NONE;
4672 hi2c->State = HAL_I2C_STATE_READY;
4673 hi2c->Mode = HAL_I2C_MODE_NONE;
4674
4675 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4676 HAL_I2C_ListenCpltCallback(hi2c);
4677 }
4678 }
4679
4680 /**
4681 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4682 * the configuration information for I2C module
4683 * @param DevAddress Target device address The device 7 bits address value
4684 * in datasheet must be shifted to the left before calling the interface
4685 * @param Timeout Timeout duration
4686 * @param Tickstart Tick start value
4687 * @retval HAL status
4688 */
4689 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
4690 {
4691 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
4692 uint32_t CurrentXferOptions = hi2c->XferOptions;
4693
4694 /* Generate Start condition if first transfer */
4695 if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
4696 {
4697 /* Generate Start */
4698 hi2c->Instance->CR1 |= I2C_CR1_START;
4699 }
4700 else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
4701 {
4702 /* Generate ReStart */
4703 hi2c->Instance->CR1 |= I2C_CR1_START;
4704 }
4705
4706 /* Wait until SB flag is set */
4707 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4708 {
4709 return HAL_TIMEOUT;
4710 }
4711
4712 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
4713 {
4714 /* Send slave address */
4715 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
4716 }
4717 else
4718 {
4719 /* Send header of slave address */
4720 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
4721
4722 /* Wait until ADD10 flag is set */
4723 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
4724 {
4725 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4726 {
4727 return HAL_ERROR;
4728 }
4729 else
4730 {
4731 return HAL_TIMEOUT;
4732 }
4733 }
4734
4735 /* Send slave address */
4736 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
4737 }
4738
4739 /* Wait until ADDR flag is set */
4740 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4741 {
4742 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4743 {
4744 return HAL_ERROR;
4745 }
4746 else
4747 {
4748 return HAL_TIMEOUT;
4749 }
4750 }
4751
4752 return HAL_OK;
4753 }
4754
4755 /**
4756 * @brief Master sends target device address for read request.
4757 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4758 * the configuration information for I2C module
4759 * @param DevAddress Target device address The device 7 bits address value
4760 * in datasheet must be shifted to the left before calling the interface
4761 * @param Timeout Timeout duration
4762 * @param Tickstart Tick start value
4763 * @retval HAL status
4764 */
4765 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
4766 {
4767 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
4768 uint32_t CurrentXferOptions = hi2c->XferOptions;
4769
4770 /* Enable Acknowledge */
4771 hi2c->Instance->CR1 |= I2C_CR1_ACK;
4772
4773 /* Generate Start condition if first transfer */
4774 if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
4775 {
4776 /* Generate Start */
4777 hi2c->Instance->CR1 |= I2C_CR1_START;
4778 }
4779 else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
4780 {
4781 /* Generate ReStart */
4782 hi2c->Instance->CR1 |= I2C_CR1_START;
4783 }
4784
4785 /* Wait until SB flag is set */
4786 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4787 {
4788 return HAL_TIMEOUT;
4789 }
4790
4791 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
4792 {
4793 /* Send slave address */
4794 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
4795 }
4796 else
4797 {
4798 /* Send header of slave address */
4799 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
4800
4801 /* Wait until ADD10 flag is set */
4802 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
4803 {
4804 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4805 {
4806 return HAL_ERROR;
4807 }
4808 else
4809 {
4810 return HAL_TIMEOUT;
4811 }
4812 }
4813
4814 /* Send slave address */
4815 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
4816
4817 /* Wait until ADDR flag is set */
4818 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4819 {
4820 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4821 {
4822 return HAL_ERROR;
4823 }
4824 else
4825 {
4826 return HAL_TIMEOUT;
4827 }
4828 }
4829
4830 /* Clear ADDR flag */
4831 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4832
4833 /* Generate Restart */
4834 hi2c->Instance->CR1 |= I2C_CR1_START;
4835
4836 /* Wait until SB flag is set */
4837 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4838 {
4839 return HAL_TIMEOUT;
4840 }
4841
4842 /* Send header of slave address */
4843 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
4844 }
4845
4846 /* Wait until ADDR flag is set */
4847 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4848 {
4849 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4850 {
4851 return HAL_ERROR;
4852 }
4853 else
4854 {
4855 return HAL_TIMEOUT;
4856 }
4857 }
4858
4859 return HAL_OK;
4860 }
4861
4862 /**
4863 * @brief Master sends target device address followed by internal memory address for write request.
4864 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4865 * the configuration information for I2C module
4866 * @param DevAddress Target device address
4867 * @param MemAddress Internal memory address
4868 * @param MemAddSize Size of internal memory address
4869 * @param Timeout Timeout duration
4870 * @param Tickstart Tick start value
4871 * @retval HAL status
4872 */
4873 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
4874 {
4875 /* Generate Start */
4876 hi2c->Instance->CR1 |= I2C_CR1_START;
4877
4878 /* Wait until SB flag is set */
4879 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4880 {
4881 return HAL_TIMEOUT;
4882 }
4883
4884 /* Send slave address */
4885 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
4886
4887 /* Wait until ADDR flag is set */
4888 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4889 {
4890 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4891 {
4892 return HAL_ERROR;
4893 }
4894 else
4895 {
4896 return HAL_TIMEOUT;
4897 }
4898 }
4899
4900 /* Clear ADDR flag */
4901 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4902
4903 /* Wait until TXE flag is set */
4904 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
4905 {
4906 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4907 {
4908 /* Generate Stop */
4909 hi2c->Instance->CR1 |= I2C_CR1_STOP;
4910 return HAL_ERROR;
4911 }
4912 else
4913 {
4914 return HAL_TIMEOUT;
4915 }
4916 }
4917
4918 /* If Memory address size is 8Bit */
4919 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
4920 {
4921 /* Send Memory Address */
4922 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
4923 }
4924 /* If Memory address size is 16Bit */
4925 else
4926 {
4927 /* Send MSB of Memory Address */
4928 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
4929
4930 /* Wait until TXE flag is set */
4931 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
4932 {
4933 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4934 {
4935 /* Generate Stop */
4936 hi2c->Instance->CR1 |= I2C_CR1_STOP;
4937 return HAL_ERROR;
4938 }
4939 else
4940 {
4941 return HAL_TIMEOUT;
4942 }
4943 }
4944
4945 /* Send LSB of Memory Address */
4946 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
4947 }
4948
4949 return HAL_OK;
4950 }
4951
4952 /**
4953 * @brief Master sends target device address followed by internal memory address for read request.
4954 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4955 * the configuration information for I2C module
4956 * @param DevAddress Target device address
4957 * @param MemAddress Internal memory address
4958 * @param MemAddSize Size of internal memory address
4959 * @param Timeout Timeout duration
4960 * @param Tickstart Tick start value
4961 * @retval HAL status
4962 */
4963 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
4964 {
4965 /* Enable Acknowledge */
4966 hi2c->Instance->CR1 |= I2C_CR1_ACK;
4967
4968 /* Generate Start */
4969 hi2c->Instance->CR1 |= I2C_CR1_START;
4970
4971 /* Wait until SB flag is set */
4972 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4973 {
4974 return HAL_TIMEOUT;
4975 }
4976
4977 /* Send slave address */
4978 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
4979
4980 /* Wait until ADDR flag is set */
4981 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4982 {
4983 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4984 {
4985 return HAL_ERROR;
4986 }
4987 else
4988 {
4989 return HAL_TIMEOUT;
4990 }
4991 }
4992
4993 /* Clear ADDR flag */
4994 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4995
4996 /* Wait until TXE flag is set */
4997 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
4998 {
4999 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
5000 {
5001 /* Generate Stop */
5002 hi2c->Instance->CR1 |= I2C_CR1_STOP;
5003 return HAL_ERROR;
5004 }
5005 else
5006 {
5007 return HAL_TIMEOUT;
5008 }
5009 }
5010
5011 /* If Memory address size is 8Bit */
5012 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
5013 {
5014 /* Send Memory Address */
5015 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
5016 }
5017 /* If Memory address size is 16Bit */
5018 else
5019 {
5020 /* Send MSB of Memory Address */
5021 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
5022
5023 /* Wait until TXE flag is set */
5024 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5025 {
5026 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
5027 {
5028 /* Generate Stop */
5029 hi2c->Instance->CR1 |= I2C_CR1_STOP;
5030 return HAL_ERROR;
5031 }
5032 else
5033 {
5034 return HAL_TIMEOUT;
5035 }
5036 }
5037
5038 /* Send LSB of Memory Address */
5039 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
5040 }
5041
5042 /* Wait until TXE flag is set */
5043 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5044 {
5045 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
5046 {
5047 /* Generate Stop */
5048 hi2c->Instance->CR1 |= I2C_CR1_STOP;
5049 return HAL_ERROR;
5050 }
5051 else
5052 {
5053 return HAL_TIMEOUT;
5054 }
5055 }
5056
5057 /* Generate Restart */
5058 hi2c->Instance->CR1 |= I2C_CR1_START;
5059
5060 /* Wait until SB flag is set */
5061 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
5062 {
5063 return HAL_TIMEOUT;
5064 }
5065
5066 /* Send slave address */
5067 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
5068
5069 /* Wait until ADDR flag is set */
5070 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
5071 {
5072 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
5073 {
5074 return HAL_ERROR;
5075 }
5076 else
5077 {
5078 return HAL_TIMEOUT;
5079 }
5080 }
5081
5082 return HAL_OK;
5083 }
5084
5085 /**
5086 * @brief DMA I2C process complete callback.
5087 * @param hdma DMA handle
5088 * @retval None
5089 */
5090 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
5091 {
5092 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
5093
5094 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5095 uint32_t CurrentState = hi2c->State;
5096 uint32_t CurrentMode = hi2c->Mode;
5097
5098 if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
5099 {
5100 /* Disable DMA Request */
5101 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
5102
5103 hi2c->XferCount = 0U;
5104
5105 /* Enable EVT and ERR interrupt */
5106 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
5107 }
5108 else
5109 {
5110 /* Disable Acknowledge */
5111 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
5112
5113 /* Generate Stop */
5114 hi2c->Instance->CR1 |= I2C_CR1_STOP;
5115
5116 /* Disable Last DMA */
5117 hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
5118
5119 /* Disable DMA Request */
5120 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
5121
5122 hi2c->XferCount = 0U;
5123
5124 /* Check if Errors has been detected during transfer */
5125 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
5126 {
5127 HAL_I2C_ErrorCallback(hi2c);
5128 }
5129 else
5130 {
5131 hi2c->State = HAL_I2C_STATE_READY;
5132
5133 if(hi2c->Mode == HAL_I2C_MODE_MEM)
5134 {
5135 hi2c->Mode = HAL_I2C_MODE_NONE;
5136
5137 HAL_I2C_MemRxCpltCallback(hi2c);
5138 }
5139 else
5140 {
5141 hi2c->Mode = HAL_I2C_MODE_NONE;
5142
5143 HAL_I2C_MasterRxCpltCallback(hi2c);
5144 }
5145 }
5146 }
5147 }
5148
5149 /**
5150 * @brief DMA I2C communication error callback.
5151 * @param hdma DMA handle
5152 * @retval None
5153 */
5154 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
5155 {
5156 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
5157
5158 /* Ignore DMA FIFO error */
5159 if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
5160 {
5161 /* Disable Acknowledge */
5162 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
5163
5164 hi2c->XferCount = 0U;
5165
5166 hi2c->State = HAL_I2C_STATE_READY;
5167 hi2c->Mode = HAL_I2C_MODE_NONE;
5168
5169 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
5170
5171 HAL_I2C_ErrorCallback(hi2c);
5172 }
5173 }
5174
5175 /**
5176 * @brief DMA I2C communication abort callback
5177 * (To be called at end of DMA Abort procedure).
5178 * @param hdma DMA handle.
5179 * @retval None
5180 */
5181 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
5182 {
5183 I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
5184
5185 /* Disable Acknowledge */
5186 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
5187
5188 hi2c->XferCount = 0U;
5189
5190 /* Reset XferAbortCallback */
5191 hi2c->hdmatx->XferAbortCallback = NULL;
5192 hi2c->hdmarx->XferAbortCallback = NULL;
5193
5194 /* Check if come from abort from user */
5195 if(hi2c->State == HAL_I2C_STATE_ABORT)
5196 {
5197 hi2c->State = HAL_I2C_STATE_READY;
5198 hi2c->Mode = HAL_I2C_MODE_NONE;
5199 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
5200
5201 /* Disable I2C peripheral to prevent dummy data in buffer */
5202 __HAL_I2C_DISABLE(hi2c);
5203
5204 /* Call the corresponding callback to inform upper layer of End of Transfer */
5205 HAL_I2C_AbortCpltCallback(hi2c);
5206 }
5207 else
5208 {
5209 hi2c->State = HAL_I2C_STATE_READY;
5210 hi2c->Mode = HAL_I2C_MODE_NONE;
5211
5212 /* Disable I2C peripheral to prevent dummy data in buffer */
5213 __HAL_I2C_DISABLE(hi2c);
5214
5215 /* Call the corresponding callback to inform upper layer of End of Transfer */
5216 HAL_I2C_ErrorCallback(hi2c);
5217 }
5218 }
5219
5220 /**
5221 * @brief This function handles I2C Communication Timeout.
5222 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5223 * the configuration information for I2C module
5224 * @param Flag specifies the I2C flag to check.
5225 * @param Status The new Flag status (SET or RESET).
5226 * @param Timeout Timeout duration
5227 * @param Tickstart Tick start value
5228 * @retval HAL status
5229 */
5230 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
5231 {
5232 /* Wait until flag is set */
5233 while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
5234 {
5235 /* Check for the Timeout */
5236 if(Timeout != HAL_MAX_DELAY)
5237 {
5238 if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
5239 {
5240 hi2c->PreviousState = I2C_STATE_NONE;
5241 hi2c->State= HAL_I2C_STATE_READY;
5242 hi2c->Mode = HAL_I2C_MODE_NONE;
5243
5244 /* Process Unlocked */
5245 __HAL_UNLOCK(hi2c);
5246
5247 return HAL_TIMEOUT;
5248 }
5249 }
5250 }
5251
5252 return HAL_OK;
5253 }
5254
5255 /**
5256 * @brief This function handles I2C Communication Timeout for Master addressing phase.
5257 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5258 * the configuration information for I2C module
5259 * @param Flag specifies the I2C flag to check.
5260 * @param Timeout Timeout duration
5261 * @param Tickstart Tick start value
5262 * @retval HAL status
5263 */
5264 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
5265 {
5266 while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
5267 {
5268 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
5269 {
5270 /* Generate Stop */
5271 hi2c->Instance->CR1 |= I2C_CR1_STOP;
5272
5273 /* Clear AF Flag */
5274 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5275
5276 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
5277 hi2c->PreviousState = I2C_STATE_NONE;
5278 hi2c->State= HAL_I2C_STATE_READY;
5279
5280 /* Process Unlocked */
5281 __HAL_UNLOCK(hi2c);
5282
5283 return HAL_ERROR;
5284 }
5285
5286 /* Check for the Timeout */
5287 if(Timeout != HAL_MAX_DELAY)
5288 {
5289 if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
5290 {
5291 hi2c->PreviousState = I2C_STATE_NONE;
5292 hi2c->State= HAL_I2C_STATE_READY;
5293
5294 /* Process Unlocked */
5295 __HAL_UNLOCK(hi2c);
5296
5297 return HAL_TIMEOUT;
5298 }
5299 }
5300 }
5301 return HAL_OK;
5302 }
5303
5304 /**
5305 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
5306 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5307 * the configuration information for the specified I2C.
5308 * @param Timeout Timeout duration
5309 * @param Tickstart Tick start value
5310 * @retval HAL status
5311 */
5312 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
5313 {
5314 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
5315 {
5316 /* Check if a NACK is detected */
5317 if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
5318 {
5319 return HAL_ERROR;
5320 }
5321
5322 /* Check for the Timeout */
5323 if(Timeout != HAL_MAX_DELAY)
5324 {
5325 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
5326 {
5327 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
5328 hi2c->PreviousState = I2C_STATE_NONE;
5329 hi2c->State= HAL_I2C_STATE_READY;
5330
5331 /* Process Unlocked */
5332 __HAL_UNLOCK(hi2c);
5333
5334 return HAL_TIMEOUT;
5335 }
5336 }
5337 }
5338 return HAL_OK;
5339 }
5340
5341 /**
5342 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
5343 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5344 * the configuration information for the specified I2C.
5345 * @param Timeout Timeout duration
5346 * @param Tickstart Tick start value
5347 * @retval HAL status
5348 */
5349 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
5350 {
5351 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
5352 {
5353 /* Check if a NACK is detected */
5354 if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
5355 {
5356 return HAL_ERROR;
5357 }
5358
5359 /* Check for the Timeout */
5360 if(Timeout != HAL_MAX_DELAY)
5361 {
5362 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
5363 {
5364 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
5365 hi2c->PreviousState = I2C_STATE_NONE;
5366 hi2c->State= HAL_I2C_STATE_READY;
5367
5368 /* Process Unlocked */
5369 __HAL_UNLOCK(hi2c);
5370
5371 return HAL_TIMEOUT;
5372 }
5373 }
5374 }
5375 return HAL_OK;
5376 }
5377
5378 /**
5379 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
5380 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5381 * the configuration information for the specified I2C.
5382 * @param Timeout Timeout duration
5383 * @param Tickstart Tick start value
5384 * @retval HAL status
5385 */
5386 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
5387 {
5388 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
5389 {
5390 /* Check if a NACK is detected */
5391 if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
5392 {
5393 return HAL_ERROR;
5394 }
5395
5396 /* Check for the Timeout */
5397 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
5398 {
5399 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
5400 hi2c->PreviousState = I2C_STATE_NONE;
5401 hi2c->State= HAL_I2C_STATE_READY;
5402
5403 /* Process Unlocked */
5404 __HAL_UNLOCK(hi2c);
5405
5406 return HAL_TIMEOUT;
5407 }
5408 }
5409 return HAL_OK;
5410 }
5411
5412 /**
5413 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
5414 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5415 * the configuration information for the specified I2C.
5416 * @param Timeout Timeout duration
5417 * @param Tickstart Tick start value
5418 * @retval HAL status
5419 */
5420 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
5421 {
5422
5423 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
5424 {
5425 /* Check if a STOPF is detected */
5426 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
5427 {
5428 /* Clear STOP Flag */
5429 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
5430
5431 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
5432 hi2c->PreviousState = I2C_STATE_NONE;
5433 hi2c->State= HAL_I2C_STATE_READY;
5434
5435 /* Process Unlocked */
5436 __HAL_UNLOCK(hi2c);
5437
5438 return HAL_ERROR;
5439 }
5440
5441 /* Check for the Timeout */
5442 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
5443 {
5444 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
5445 hi2c->State= HAL_I2C_STATE_READY;
5446
5447 /* Process Unlocked */
5448 __HAL_UNLOCK(hi2c);
5449
5450 return HAL_TIMEOUT;
5451 }
5452 }
5453 return HAL_OK;
5454 }
5455
5456 /**
5457 * @brief This function handles Acknowledge failed detection during an I2C Communication.
5458 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5459 * the configuration information for the specified I2C.
5460 * @retval HAL status
5461 */
5462 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
5463 {
5464 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
5465 {
5466 /* Clear NACKF Flag */
5467 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5468
5469 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
5470 hi2c->PreviousState = I2C_STATE_NONE;
5471 hi2c->State= HAL_I2C_STATE_READY;
5472
5473 /* Process Unlocked */
5474 __HAL_UNLOCK(hi2c);
5475
5476 return HAL_ERROR;
5477 }
5478 return HAL_OK;
5479 }
5480 /**
5481 * @}
5482 */
5483
5484 #endif /* HAL_I2C_MODULE_ENABLED */
5485
5486 /**
5487 * @}
5488 */
5489
5490 /**
5491 * @}
5492 */
5493
5494 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/