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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_eth.c
4 * @author MCD Application Team
5 * @brief ETH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Ethernet (ETH) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 (#)Declare a ETH_HandleTypeDef handle structure, for example:
19 ETH_HandleTypeDef heth;
20
21 (#)Fill parameters of Init structure in heth handle
22
23 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
24
25 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
26 (##) Enable the Ethernet interface clock using
27 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
28 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
29 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
30
31 (##) Initialize the related GPIO clocks
32 (##) Configure Ethernet pin-out
33 (##) Configure Ethernet NVIC interrupt (IT mode)
34
35 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
36 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
37 (##) HAL_ETH_DMARxDescListInit(); for Reception process
38
39 (#)Enable MAC and DMA transmission and reception:
40 (##) HAL_ETH_Start();
41
42 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
43 the frame to MAC TX FIFO:
44 (##) HAL_ETH_TransmitFrame();
45
46 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
47 frame parameters
48 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
49
50 (#) Get a received frame when an ETH RX interrupt occurs:
51 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
52
53 (#) Communicate with external PHY device:
54 (##) Read a specific register from the PHY
55 HAL_ETH_ReadPHYRegister();
56 (##) Write data to a specific RHY register:
57 HAL_ETH_WritePHYRegister();
58
59 (#) Configure the Ethernet MAC after ETH peripheral initialization
60 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
61
62 (#) Configure the Ethernet DMA after ETH peripheral initialization
63 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
64
65 -@- The PTP protocol and the DMA descriptors ring mode are not supported
66 in this driver
67
68 @endverbatim
69 ******************************************************************************
70 * @attention
71 *
72 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
73 *
74 * Redistribution and use in source and binary forms, with or without modification,
75 * are permitted provided that the following conditions are met:
76 * 1. Redistributions of source code must retain the above copyright notice,
77 * this list of conditions and the following disclaimer.
78 * 2. Redistributions in binary form must reproduce the above copyright notice,
79 * this list of conditions and the following disclaimer in the documentation
80 * and/or other materials provided with the distribution.
81 * 3. Neither the name of STMicroelectronics nor the names of its contributors
82 * may be used to endorse or promote products derived from this software
83 * without specific prior written permission.
84 *
85 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
86 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
88 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
92 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
93 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
94 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
95 *
96 ******************************************************************************
97 */
98
99 /* Includes ------------------------------------------------------------------*/
100 #include "stm32f4xx_hal.h"
101
102 /** @addtogroup STM32F4xx_HAL_Driver
103 * @{
104 */
105
106 /** @defgroup ETH ETH
107 * @brief ETH HAL module driver
108 * @{
109 */
110
111 #ifdef HAL_ETH_MODULE_ENABLED
112
113 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
114 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
115
116 /* Private typedef -----------------------------------------------------------*/
117 /* Private define ------------------------------------------------------------*/
118 /** @defgroup ETH_Private_Constants ETH Private Constants
119 * @{
120 */
121 #define ETH_TIMEOUT_SWRESET 500U
122 #define ETH_TIMEOUT_LINKED_STATE 5000U
123 #define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
124
125 /**
126 * @}
127 */
128 /* Private macro -------------------------------------------------------------*/
129 /* Private variables ---------------------------------------------------------*/
130 /* Private function prototypes -----------------------------------------------*/
131 /** @defgroup ETH_Private_Functions ETH Private Functions
132 * @{
133 */
134 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
135 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
136 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
137 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
138 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
139 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
140 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
141 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
142 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
143 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
144 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
145 static void ETH_Delay(uint32_t mdelay);
146
147 /**
148 * @}
149 */
150 /* Private functions ---------------------------------------------------------*/
151
152 /** @defgroup ETH_Exported_Functions ETH Exported Functions
153 * @{
154 */
155
156 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
157 * @brief Initialization and Configuration functions
158 *
159 @verbatim
160 ===============================================================================
161 ##### Initialization and de-initialization functions #####
162 ===============================================================================
163 [..] This section provides functions allowing to:
164 (+) Initialize and configure the Ethernet peripheral
165 (+) De-initialize the Ethernet peripheral
166
167 @endverbatim
168 * @{
169 */
170
171 /**
172 * @brief Initializes the Ethernet MAC and DMA according to default
173 * parameters.
174 * @param heth pointer to a ETH_HandleTypeDef structure that contains
175 * the configuration information for ETHERNET module
176 * @retval HAL status
177 */
178 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
179 {
180 uint32_t tmpreg1 = 0U, phyreg = 0U;
181 uint32_t hclk = 60000000U;
182 uint32_t tickstart = 0U;
183 uint32_t err = ETH_SUCCESS;
184
185 /* Check the ETH peripheral state */
186 if(heth == NULL)
187 {
188 return HAL_ERROR;
189 }
190
191 /* Check parameters */
192 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
193 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
194 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
195 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
196
197 if(heth->State == HAL_ETH_STATE_RESET)
198 {
199 /* Allocate lock resource and initialize it */
200 heth->Lock = HAL_UNLOCKED;
201 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
202 HAL_ETH_MspInit(heth);
203 }
204
205 /* Enable SYSCFG Clock */
206 __HAL_RCC_SYSCFG_CLK_ENABLE();
207
208 /* Select MII or RMII Mode*/
209 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
210 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
211
212 /* Ethernet Software reset */
213 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
214 /* After reset all the registers holds their respective reset values */
215 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
216
217 /* Get tick */
218 tickstart = HAL_GetTick();
219
220 /* Wait for software reset */
221 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
222 {
223 /* Check for the Timeout */
224 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
225 {
226 heth->State= HAL_ETH_STATE_TIMEOUT;
227
228 /* Process Unlocked */
229 __HAL_UNLOCK(heth);
230
231 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
232 not available, please check your external PHY or the IO configuration */
233 return HAL_TIMEOUT;
234 }
235 }
236
237 /*-------------------------------- MAC Initialization ----------------------*/
238 /* Get the ETHERNET MACMIIAR value */
239 tmpreg1 = (heth->Instance)->MACMIIAR;
240 /* Clear CSR Clock Range CR[2:0] bits */
241 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
242
243 /* Get hclk frequency value */
244 hclk = HAL_RCC_GetHCLKFreq();
245
246 /* Set CR bits depending on hclk value */
247 if((hclk >= 20000000U)&&(hclk < 35000000U))
248 {
249 /* CSR Clock Range between 20-35 MHz */
250 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
251 }
252 else if((hclk >= 35000000U)&&(hclk < 60000000U))
253 {
254 /* CSR Clock Range between 35-60 MHz */
255 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
256 }
257 else if((hclk >= 60000000U)&&(hclk < 100000000U))
258 {
259 /* CSR Clock Range between 60-100 MHz */
260 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
261 }
262 else if((hclk >= 100000000U)&&(hclk < 150000000U))
263 {
264 /* CSR Clock Range between 100-150 MHz */
265 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
266 }
267 else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */
268 {
269 /* CSR Clock Range between 150-183 MHz */
270 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
271 }
272
273 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
274 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
275
276 /*-------------------- PHY initialization and configuration ----------------*/
277 /* Put the PHY in reset mode */
278 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
279 {
280 /* In case of write timeout */
281 err = ETH_ERROR;
282
283 /* Config MAC and DMA */
284 ETH_MACDMAConfig(heth, err);
285
286 /* Set the ETH peripheral state to READY */
287 heth->State = HAL_ETH_STATE_READY;
288
289 /* Return HAL_ERROR */
290 return HAL_ERROR;
291 }
292
293 /* Delay to assure PHY reset */
294 HAL_Delay(PHY_RESET_DELAY);
295
296 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
297 {
298 /* Get tick */
299 tickstart = HAL_GetTick();
300
301 /* We wait for linked status */
302 do
303 {
304 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
305
306 /* Check for the Timeout */
307 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
308 {
309 /* In case of write timeout */
310 err = ETH_ERROR;
311
312 /* Config MAC and DMA */
313 ETH_MACDMAConfig(heth, err);
314
315 heth->State= HAL_ETH_STATE_READY;
316
317 /* Process Unlocked */
318 __HAL_UNLOCK(heth);
319
320 return HAL_TIMEOUT;
321 }
322 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
323
324
325 /* Enable Auto-Negotiation */
326 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
327 {
328 /* In case of write timeout */
329 err = ETH_ERROR;
330
331 /* Config MAC and DMA */
332 ETH_MACDMAConfig(heth, err);
333
334 /* Set the ETH peripheral state to READY */
335 heth->State = HAL_ETH_STATE_READY;
336
337 /* Return HAL_ERROR */
338 return HAL_ERROR;
339 }
340
341 /* Get tick */
342 tickstart = HAL_GetTick();
343
344 /* Wait until the auto-negotiation will be completed */
345 do
346 {
347 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
348
349 /* Check for the Timeout */
350 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
351 {
352 /* In case of write timeout */
353 err = ETH_ERROR;
354
355 /* Config MAC and DMA */
356 ETH_MACDMAConfig(heth, err);
357
358 heth->State= HAL_ETH_STATE_READY;
359
360 /* Process Unlocked */
361 __HAL_UNLOCK(heth);
362
363 return HAL_TIMEOUT;
364 }
365
366 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
367
368 /* Read the result of the auto-negotiation */
369 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
370 {
371 /* In case of write timeout */
372 err = ETH_ERROR;
373
374 /* Config MAC and DMA */
375 ETH_MACDMAConfig(heth, err);
376
377 /* Set the ETH peripheral state to READY */
378 heth->State = HAL_ETH_STATE_READY;
379
380 /* Return HAL_ERROR */
381 return HAL_ERROR;
382 }
383
384 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
385 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
386 {
387 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
388 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
389 }
390 else
391 {
392 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
393 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
394 }
395 /* Configure the MAC with the speed fixed by the auto-negotiation process */
396 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
397 {
398 /* Set Ethernet speed to 10M following the auto-negotiation */
399 (heth->Init).Speed = ETH_SPEED_10M;
400 }
401 else
402 {
403 /* Set Ethernet speed to 100M following the auto-negotiation */
404 (heth->Init).Speed = ETH_SPEED_100M;
405 }
406 }
407 else /* AutoNegotiation Disable */
408 {
409 /* Check parameters */
410 assert_param(IS_ETH_SPEED(heth->Init.Speed));
411 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
412
413 /* Set MAC Speed and Duplex Mode */
414 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
415 (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
416 {
417 /* In case of write timeout */
418 err = ETH_ERROR;
419
420 /* Config MAC and DMA */
421 ETH_MACDMAConfig(heth, err);
422
423 /* Set the ETH peripheral state to READY */
424 heth->State = HAL_ETH_STATE_READY;
425
426 /* Return HAL_ERROR */
427 return HAL_ERROR;
428 }
429
430 /* Delay to assure PHY configuration */
431 HAL_Delay(PHY_CONFIG_DELAY);
432 }
433
434 /* Config MAC and DMA */
435 ETH_MACDMAConfig(heth, err);
436
437 /* Set ETH HAL State to Ready */
438 heth->State= HAL_ETH_STATE_READY;
439
440 /* Return function status */
441 return HAL_OK;
442 }
443
444 /**
445 * @brief De-Initializes the ETH peripheral.
446 * @param heth pointer to a ETH_HandleTypeDef structure that contains
447 * the configuration information for ETHERNET module
448 * @retval HAL status
449 */
450 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
451 {
452 /* Set the ETH peripheral state to BUSY */
453 heth->State = HAL_ETH_STATE_BUSY;
454
455 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
456 HAL_ETH_MspDeInit(heth);
457
458 /* Set ETH HAL state to Disabled */
459 heth->State= HAL_ETH_STATE_RESET;
460
461 /* Release Lock */
462 __HAL_UNLOCK(heth);
463
464 /* Return function status */
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Initializes the DMA Tx descriptors in chain mode.
470 * @param heth pointer to a ETH_HandleTypeDef structure that contains
471 * the configuration information for ETHERNET module
472 * @param DMATxDescTab Pointer to the first Tx desc list
473 * @param TxBuff Pointer to the first TxBuffer list
474 * @param TxBuffCount Number of the used Tx desc in the list
475 * @retval HAL status
476 */
477 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
478 {
479 uint32_t i = 0U;
480 ETH_DMADescTypeDef *dmatxdesc;
481
482 /* Process Locked */
483 __HAL_LOCK(heth);
484
485 /* Set the ETH peripheral state to BUSY */
486 heth->State = HAL_ETH_STATE_BUSY;
487
488 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
489 heth->TxDesc = DMATxDescTab;
490
491 /* Fill each DMATxDesc descriptor with the right values */
492 for(i=0U; i < TxBuffCount; i++)
493 {
494 /* Get the pointer on the ith member of the Tx Desc list */
495 dmatxdesc = DMATxDescTab + i;
496
497 /* Set Second Address Chained bit */
498 dmatxdesc->Status = ETH_DMATXDESC_TCH;
499
500 /* Set Buffer1 address pointer */
501 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
502
503 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
504 {
505 /* Set the DMA Tx descriptors checksum insertion */
506 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
507 }
508
509 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
510 if(i < (TxBuffCount-1U))
511 {
512 /* Set next descriptor address register with next descriptor base address */
513 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
514 }
515 else
516 {
517 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
518 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
519 }
520 }
521
522 /* Set Transmit Descriptor List Address Register */
523 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
524
525 /* Set ETH HAL State to Ready */
526 heth->State= HAL_ETH_STATE_READY;
527
528 /* Process Unlocked */
529 __HAL_UNLOCK(heth);
530
531 /* Return function status */
532 return HAL_OK;
533 }
534
535 /**
536 * @brief Initializes the DMA Rx descriptors in chain mode.
537 * @param heth pointer to a ETH_HandleTypeDef structure that contains
538 * the configuration information for ETHERNET module
539 * @param DMARxDescTab Pointer to the first Rx desc list
540 * @param RxBuff Pointer to the first RxBuffer list
541 * @param RxBuffCount Number of the used Rx desc in the list
542 * @retval HAL status
543 */
544 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
545 {
546 uint32_t i = 0U;
547 ETH_DMADescTypeDef *DMARxDesc;
548
549 /* Process Locked */
550 __HAL_LOCK(heth);
551
552 /* Set the ETH peripheral state to BUSY */
553 heth->State = HAL_ETH_STATE_BUSY;
554
555 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
556 heth->RxDesc = DMARxDescTab;
557
558 /* Fill each DMARxDesc descriptor with the right values */
559 for(i=0U; i < RxBuffCount; i++)
560 {
561 /* Get the pointer on the ith member of the Rx Desc list */
562 DMARxDesc = DMARxDescTab+i;
563
564 /* Set Own bit of the Rx descriptor Status */
565 DMARxDesc->Status = ETH_DMARXDESC_OWN;
566
567 /* Set Buffer1 size and Second Address Chained bit */
568 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
569
570 /* Set Buffer1 address pointer */
571 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
572
573 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
574 {
575 /* Enable Ethernet DMA Rx Descriptor interrupt */
576 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
577 }
578
579 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
580 if(i < (RxBuffCount-1U))
581 {
582 /* Set next descriptor address register with next descriptor base address */
583 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
584 }
585 else
586 {
587 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
588 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
589 }
590 }
591
592 /* Set Receive Descriptor List Address Register */
593 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
594
595 /* Set ETH HAL State to Ready */
596 heth->State= HAL_ETH_STATE_READY;
597
598 /* Process Unlocked */
599 __HAL_UNLOCK(heth);
600
601 /* Return function status */
602 return HAL_OK;
603 }
604
605 /**
606 * @brief Initializes the ETH MSP.
607 * @param heth pointer to a ETH_HandleTypeDef structure that contains
608 * the configuration information for ETHERNET module
609 * @retval None
610 */
611 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
612 {
613 /* Prevent unused argument(s) compilation warning */
614 UNUSED(heth);
615 /* NOTE : This function Should not be modified, when the callback is needed,
616 the HAL_ETH_MspInit could be implemented in the user file
617 */
618 }
619
620 /**
621 * @brief DeInitializes ETH MSP.
622 * @param heth pointer to a ETH_HandleTypeDef structure that contains
623 * the configuration information for ETHERNET module
624 * @retval None
625 */
626 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
627 {
628 /* Prevent unused argument(s) compilation warning */
629 UNUSED(heth);
630 /* NOTE : This function Should not be modified, when the callback is needed,
631 the HAL_ETH_MspDeInit could be implemented in the user file
632 */
633 }
634
635 /**
636 * @}
637 */
638
639 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
640 * @brief Data transfers functions
641 *
642 @verbatim
643 ==============================================================================
644 ##### IO operation functions #####
645 ==============================================================================
646 [..] This section provides functions allowing to:
647 (+) Transmit a frame
648 HAL_ETH_TransmitFrame();
649 (+) Receive a frame
650 HAL_ETH_GetReceivedFrame();
651 HAL_ETH_GetReceivedFrame_IT();
652 (+) Read from an External PHY register
653 HAL_ETH_ReadPHYRegister();
654 (+) Write to an External PHY register
655 HAL_ETH_WritePHYRegister();
656
657 @endverbatim
658
659 * @{
660 */
661
662 /**
663 * @brief Sends an Ethernet frame.
664 * @param heth pointer to a ETH_HandleTypeDef structure that contains
665 * the configuration information for ETHERNET module
666 * @param FrameLength Amount of data to be sent
667 * @retval HAL status
668 */
669 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
670 {
671 uint32_t bufcount = 0U, size = 0U, i = 0U;
672
673 /* Process Locked */
674 __HAL_LOCK(heth);
675
676 /* Set the ETH peripheral state to BUSY */
677 heth->State = HAL_ETH_STATE_BUSY;
678
679 if (FrameLength == 0U)
680 {
681 /* Set ETH HAL state to READY */
682 heth->State = HAL_ETH_STATE_READY;
683
684 /* Process Unlocked */
685 __HAL_UNLOCK(heth);
686
687 return HAL_ERROR;
688 }
689
690 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
691 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
692 {
693 /* OWN bit set */
694 heth->State = HAL_ETH_STATE_BUSY_TX;
695
696 /* Process Unlocked */
697 __HAL_UNLOCK(heth);
698
699 return HAL_ERROR;
700 }
701
702 /* Get the number of needed Tx buffers for the current frame */
703 if (FrameLength > ETH_TX_BUF_SIZE)
704 {
705 bufcount = FrameLength/ETH_TX_BUF_SIZE;
706 if (FrameLength % ETH_TX_BUF_SIZE)
707 {
708 bufcount++;
709 }
710 }
711 else
712 {
713 bufcount = 1U;
714 }
715 if (bufcount == 1U)
716 {
717 /* Set LAST and FIRST segment */
718 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
719 /* Set frame size */
720 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
721 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
722 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
723 /* Point to next descriptor */
724 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
725 }
726 else
727 {
728 for (i=0U; i< bufcount; i++)
729 {
730 /* Clear FIRST and LAST segment bits */
731 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
732
733 if (i == 0U)
734 {
735 /* Setting the first segment bit */
736 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
737 }
738
739 /* Program size */
740 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
741
742 if (i == (bufcount-1U))
743 {
744 /* Setting the last segment bit */
745 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
746 size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
747 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
748 }
749
750 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
751 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
752 /* point to next descriptor */
753 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
754 }
755 }
756
757 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
758 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
759 {
760 /* Clear TBUS ETHERNET DMA flag */
761 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
762 /* Resume DMA transmission*/
763 (heth->Instance)->DMATPDR = 0U;
764 }
765
766 /* Set ETH HAL State to Ready */
767 heth->State = HAL_ETH_STATE_READY;
768
769 /* Process Unlocked */
770 __HAL_UNLOCK(heth);
771
772 /* Return function status */
773 return HAL_OK;
774 }
775
776 /**
777 * @brief Checks for received frames.
778 * @param heth pointer to a ETH_HandleTypeDef structure that contains
779 * the configuration information for ETHERNET module
780 * @retval HAL status
781 */
782 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
783 {
784 uint32_t framelength = 0U;
785
786 /* Process Locked */
787 __HAL_LOCK(heth);
788
789 /* Check the ETH state to BUSY */
790 heth->State = HAL_ETH_STATE_BUSY;
791
792 /* Check if segment is not owned by DMA */
793 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
794 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
795 {
796 /* Check if last segment */
797 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
798 {
799 /* increment segment count */
800 (heth->RxFrameInfos).SegCount++;
801
802 /* Check if last segment is first segment: one segment contains the frame */
803 if ((heth->RxFrameInfos).SegCount == 1U)
804 {
805 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
806 }
807
808 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
809
810 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
811 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
812 heth->RxFrameInfos.length = framelength;
813
814 /* Get the address of the buffer start address */
815 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
816 /* point to next descriptor */
817 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
818
819 /* Set HAL State to Ready */
820 heth->State = HAL_ETH_STATE_READY;
821
822 /* Process Unlocked */
823 __HAL_UNLOCK(heth);
824
825 /* Return function status */
826 return HAL_OK;
827 }
828 /* Check if first segment */
829 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
830 {
831 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
832 (heth->RxFrameInfos).LSRxDesc = NULL;
833 (heth->RxFrameInfos).SegCount = 1U;
834 /* Point to next descriptor */
835 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
836 }
837 /* Check if intermediate segment */
838 else
839 {
840 (heth->RxFrameInfos).SegCount++;
841 /* Point to next descriptor */
842 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
843 }
844 }
845
846 /* Set ETH HAL State to Ready */
847 heth->State = HAL_ETH_STATE_READY;
848
849 /* Process Unlocked */
850 __HAL_UNLOCK(heth);
851
852 /* Return function status */
853 return HAL_ERROR;
854 }
855
856 /**
857 * @brief Gets the Received frame in interrupt mode.
858 * @param heth pointer to a ETH_HandleTypeDef structure that contains
859 * the configuration information for ETHERNET module
860 * @retval HAL status
861 */
862 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
863 {
864 uint32_t descriptorscancounter = 0U;
865
866 /* Process Locked */
867 __HAL_LOCK(heth);
868
869 /* Set ETH HAL State to BUSY */
870 heth->State = HAL_ETH_STATE_BUSY;
871
872 /* Scan descriptors owned by CPU */
873 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
874 {
875 /* Just for security */
876 descriptorscancounter++;
877
878 /* Check if first segment in frame */
879 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
880 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
881 {
882 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
883 heth->RxFrameInfos.SegCount = 1U;
884 /* Point to next descriptor */
885 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
886 }
887 /* Check if intermediate segment */
888 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
889 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
890 {
891 /* Increment segment count */
892 (heth->RxFrameInfos.SegCount)++;
893 /* Point to next descriptor */
894 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
895 }
896 /* Should be last segment */
897 else
898 {
899 /* Last segment */
900 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
901
902 /* Increment segment count */
903 (heth->RxFrameInfos.SegCount)++;
904
905 /* Check if last segment is first segment: one segment contains the frame */
906 if ((heth->RxFrameInfos.SegCount) == 1U)
907 {
908 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
909 }
910
911 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
912 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
913
914 /* Get the address of the buffer start address */
915 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
916
917 /* Point to next descriptor */
918 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
919
920 /* Set HAL State to Ready */
921 heth->State = HAL_ETH_STATE_READY;
922
923 /* Process Unlocked */
924 __HAL_UNLOCK(heth);
925
926 /* Return function status */
927 return HAL_OK;
928 }
929 }
930
931 /* Set HAL State to Ready */
932 heth->State = HAL_ETH_STATE_READY;
933
934 /* Process Unlocked */
935 __HAL_UNLOCK(heth);
936
937 /* Return function status */
938 return HAL_ERROR;
939 }
940
941 /**
942 * @brief This function handles ETH interrupt request.
943 * @param heth pointer to a ETH_HandleTypeDef structure that contains
944 * the configuration information for ETHERNET module
945 * @retval HAL status
946 */
947 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
948 {
949 /* Frame received */
950 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
951 {
952 /* Receive complete callback */
953 HAL_ETH_RxCpltCallback(heth);
954
955 /* Clear the Eth DMA Rx IT pending bits */
956 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
957
958 /* Set HAL State to Ready */
959 heth->State = HAL_ETH_STATE_READY;
960
961 /* Process Unlocked */
962 __HAL_UNLOCK(heth);
963
964 }
965 /* Frame transmitted */
966 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
967 {
968 /* Transfer complete callback */
969 HAL_ETH_TxCpltCallback(heth);
970
971 /* Clear the Eth DMA Tx IT pending bits */
972 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
973
974 /* Set HAL State to Ready */
975 heth->State = HAL_ETH_STATE_READY;
976
977 /* Process Unlocked */
978 __HAL_UNLOCK(heth);
979 }
980
981 /* Clear the interrupt flags */
982 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
983
984 /* ETH DMA Error */
985 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
986 {
987 /* Ethernet Error callback */
988 HAL_ETH_ErrorCallback(heth);
989
990 /* Clear the interrupt flags */
991 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
992
993 /* Set HAL State to Ready */
994 heth->State = HAL_ETH_STATE_READY;
995
996 /* Process Unlocked */
997 __HAL_UNLOCK(heth);
998 }
999 }
1000
1001 /**
1002 * @brief Tx Transfer completed callbacks.
1003 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1004 * the configuration information for ETHERNET module
1005 * @retval None
1006 */
1007 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
1008 {
1009 /* Prevent unused argument(s) compilation warning */
1010 UNUSED(heth);
1011 /* NOTE : This function Should not be modified, when the callback is needed,
1012 the HAL_ETH_TxCpltCallback could be implemented in the user file
1013 */
1014 }
1015
1016 /**
1017 * @brief Rx Transfer completed callbacks.
1018 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1019 * the configuration information for ETHERNET module
1020 * @retval None
1021 */
1022 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
1023 {
1024 /* Prevent unused argument(s) compilation warning */
1025 UNUSED(heth);
1026 /* NOTE : This function Should not be modified, when the callback is needed,
1027 the HAL_ETH_TxCpltCallback could be implemented in the user file
1028 */
1029 }
1030
1031 /**
1032 * @brief Ethernet transfer error callbacks
1033 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1034 * the configuration information for ETHERNET module
1035 * @retval None
1036 */
1037 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
1038 {
1039 /* Prevent unused argument(s) compilation warning */
1040 UNUSED(heth);
1041 /* NOTE : This function Should not be modified, when the callback is needed,
1042 the HAL_ETH_TxCpltCallback could be implemented in the user file
1043 */
1044 }
1045
1046 /**
1047 * @brief Reads a PHY register
1048 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1049 * the configuration information for ETHERNET module
1050 * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
1051 * This parameter can be one of the following values:
1052 * PHY_BCR: Transceiver Basic Control Register,
1053 * PHY_BSR: Transceiver Basic Status Register.
1054 * More PHY register could be read depending on the used PHY
1055 * @param RegValue PHY register value
1056 * @retval HAL status
1057 */
1058 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
1059 {
1060 uint32_t tmpreg1 = 0U;
1061 uint32_t tickstart = 0U;
1062
1063 /* Check parameters */
1064 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1065
1066 /* Check the ETH peripheral state */
1067 if(heth->State == HAL_ETH_STATE_BUSY_RD)
1068 {
1069 return HAL_BUSY;
1070 }
1071 /* Set ETH HAL State to BUSY_RD */
1072 heth->State = HAL_ETH_STATE_BUSY_RD;
1073
1074 /* Get the ETHERNET MACMIIAR value */
1075 tmpreg1 = heth->Instance->MACMIIAR;
1076
1077 /* Keep only the CSR Clock Range CR[2:0] bits value */
1078 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
1079
1080 /* Prepare the MII address register value */
1081 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1082 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1083 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
1084 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1085
1086 /* Write the result value into the MII Address register */
1087 heth->Instance->MACMIIAR = tmpreg1;
1088
1089 /* Get tick */
1090 tickstart = HAL_GetTick();
1091
1092 /* Check for the Busy flag */
1093 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1094 {
1095 /* Check for the Timeout */
1096 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
1097 {
1098 heth->State= HAL_ETH_STATE_READY;
1099
1100 /* Process Unlocked */
1101 __HAL_UNLOCK(heth);
1102
1103 return HAL_TIMEOUT;
1104 }
1105
1106 tmpreg1 = heth->Instance->MACMIIAR;
1107 }
1108
1109 /* Get MACMIIDR value */
1110 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
1111
1112 /* Set ETH HAL State to READY */
1113 heth->State = HAL_ETH_STATE_READY;
1114
1115 /* Return function status */
1116 return HAL_OK;
1117 }
1118
1119 /**
1120 * @brief Writes to a PHY register.
1121 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1122 * the configuration information for ETHERNET module
1123 * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
1124 * This parameter can be one of the following values:
1125 * PHY_BCR: Transceiver Control Register.
1126 * More PHY register could be written depending on the used PHY
1127 * @param RegValue the value to write
1128 * @retval HAL status
1129 */
1130 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
1131 {
1132 uint32_t tmpreg1 = 0U;
1133 uint32_t tickstart = 0U;
1134
1135 /* Check parameters */
1136 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1137
1138 /* Check the ETH peripheral state */
1139 if(heth->State == HAL_ETH_STATE_BUSY_WR)
1140 {
1141 return HAL_BUSY;
1142 }
1143 /* Set ETH HAL State to BUSY_WR */
1144 heth->State = HAL_ETH_STATE_BUSY_WR;
1145
1146 /* Get the ETHERNET MACMIIAR value */
1147 tmpreg1 = heth->Instance->MACMIIAR;
1148
1149 /* Keep only the CSR Clock Range CR[2:0] bits value */
1150 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
1151
1152 /* Prepare the MII register address value */
1153 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1154 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1155 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
1156 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1157
1158 /* Give the value to the MII data register */
1159 heth->Instance->MACMIIDR = (uint16_t)RegValue;
1160
1161 /* Write the result value into the MII Address register */
1162 heth->Instance->MACMIIAR = tmpreg1;
1163
1164 /* Get tick */
1165 tickstart = HAL_GetTick();
1166
1167 /* Check for the Busy flag */
1168 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1169 {
1170 /* Check for the Timeout */
1171 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
1172 {
1173 heth->State= HAL_ETH_STATE_READY;
1174
1175 /* Process Unlocked */
1176 __HAL_UNLOCK(heth);
1177
1178 return HAL_TIMEOUT;
1179 }
1180
1181 tmpreg1 = heth->Instance->MACMIIAR;
1182 }
1183
1184 /* Set ETH HAL State to READY */
1185 heth->State = HAL_ETH_STATE_READY;
1186
1187 /* Return function status */
1188 return HAL_OK;
1189 }
1190
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
1196 * @brief Peripheral Control functions
1197 *
1198 @verbatim
1199 ===============================================================================
1200 ##### Peripheral Control functions #####
1201 ===============================================================================
1202 [..] This section provides functions allowing to:
1203 (+) Enable MAC and DMA transmission and reception.
1204 HAL_ETH_Start();
1205 (+) Disable MAC and DMA transmission and reception.
1206 HAL_ETH_Stop();
1207 (+) Set the MAC configuration in runtime mode
1208 HAL_ETH_ConfigMAC();
1209 (+) Set the DMA configuration in runtime mode
1210 HAL_ETH_ConfigDMA();
1211
1212 @endverbatim
1213 * @{
1214 */
1215
1216 /**
1217 * @brief Enables Ethernet MAC and DMA reception/transmission
1218 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1219 * the configuration information for ETHERNET module
1220 * @retval HAL status
1221 */
1222 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
1223 {
1224 /* Process Locked */
1225 __HAL_LOCK(heth);
1226
1227 /* Set the ETH peripheral state to BUSY */
1228 heth->State = HAL_ETH_STATE_BUSY;
1229
1230 /* Enable transmit state machine of the MAC for transmission on the MII */
1231 ETH_MACTransmissionEnable(heth);
1232
1233 /* Enable receive state machine of the MAC for reception from the MII */
1234 ETH_MACReceptionEnable(heth);
1235
1236 /* Flush Transmit FIFO */
1237 ETH_FlushTransmitFIFO(heth);
1238
1239 /* Start DMA transmission */
1240 ETH_DMATransmissionEnable(heth);
1241
1242 /* Start DMA reception */
1243 ETH_DMAReceptionEnable(heth);
1244
1245 /* Set the ETH state to READY*/
1246 heth->State= HAL_ETH_STATE_READY;
1247
1248 /* Process Unlocked */
1249 __HAL_UNLOCK(heth);
1250
1251 /* Return function status */
1252 return HAL_OK;
1253 }
1254
1255 /**
1256 * @brief Stop Ethernet MAC and DMA reception/transmission
1257 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1258 * the configuration information for ETHERNET module
1259 * @retval HAL status
1260 */
1261 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
1262 {
1263 /* Process Locked */
1264 __HAL_LOCK(heth);
1265
1266 /* Set the ETH peripheral state to BUSY */
1267 heth->State = HAL_ETH_STATE_BUSY;
1268
1269 /* Stop DMA transmission */
1270 ETH_DMATransmissionDisable(heth);
1271
1272 /* Stop DMA reception */
1273 ETH_DMAReceptionDisable(heth);
1274
1275 /* Disable receive state machine of the MAC for reception from the MII */
1276 ETH_MACReceptionDisable(heth);
1277
1278 /* Flush Transmit FIFO */
1279 ETH_FlushTransmitFIFO(heth);
1280
1281 /* Disable transmit state machine of the MAC for transmission on the MII */
1282 ETH_MACTransmissionDisable(heth);
1283
1284 /* Set the ETH state*/
1285 heth->State = HAL_ETH_STATE_READY;
1286
1287 /* Process Unlocked */
1288 __HAL_UNLOCK(heth);
1289
1290 /* Return function status */
1291 return HAL_OK;
1292 }
1293
1294 /**
1295 * @brief Set ETH MAC Configuration.
1296 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1297 * the configuration information for ETHERNET module
1298 * @param macconf MAC Configuration structure
1299 * @retval HAL status
1300 */
1301 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
1302 {
1303 uint32_t tmpreg1 = 0U;
1304
1305 /* Process Locked */
1306 __HAL_LOCK(heth);
1307
1308 /* Set the ETH peripheral state to BUSY */
1309 heth->State= HAL_ETH_STATE_BUSY;
1310
1311 assert_param(IS_ETH_SPEED(heth->Init.Speed));
1312 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
1313
1314 if (macconf != NULL)
1315 {
1316 /* Check the parameters */
1317 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
1318 assert_param(IS_ETH_JABBER(macconf->Jabber));
1319 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
1320 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
1321 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
1322 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
1323 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
1324 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
1325 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
1326 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
1327 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
1328 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
1329 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
1330 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
1331 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
1332 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
1333 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
1334 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
1335 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
1336 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
1337 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
1338 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
1339 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
1340 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
1341 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
1342 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
1343 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
1344
1345 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1346 /* Get the ETHERNET MACCR value */
1347 tmpreg1 = (heth->Instance)->MACCR;
1348 /* Clear WD, PCE, PS, TE and RE bits */
1349 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
1350
1351 tmpreg1 |= (uint32_t)(macconf->Watchdog |
1352 macconf->Jabber |
1353 macconf->InterFrameGap |
1354 macconf->CarrierSense |
1355 (heth->Init).Speed |
1356 macconf->ReceiveOwn |
1357 macconf->LoopbackMode |
1358 (heth->Init).DuplexMode |
1359 macconf->ChecksumOffload |
1360 macconf->RetryTransmission |
1361 macconf->AutomaticPadCRCStrip |
1362 macconf->BackOffLimit |
1363 macconf->DeferralCheck);
1364
1365 /* Write to ETHERNET MACCR */
1366 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
1367
1368 /* Wait until the write operation will be taken into account :
1369 at least four TX_CLK/RX_CLK clock cycles */
1370 tmpreg1 = (heth->Instance)->MACCR;
1371 HAL_Delay(ETH_REG_WRITE_DELAY);
1372 (heth->Instance)->MACCR = tmpreg1;
1373
1374 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1375 /* Write to ETHERNET MACFFR */
1376 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
1377 macconf->SourceAddrFilter |
1378 macconf->PassControlFrames |
1379 macconf->BroadcastFramesReception |
1380 macconf->DestinationAddrFilter |
1381 macconf->PromiscuousMode |
1382 macconf->MulticastFramesFilter |
1383 macconf->UnicastFramesFilter);
1384
1385 /* Wait until the write operation will be taken into account :
1386 at least four TX_CLK/RX_CLK clock cycles */
1387 tmpreg1 = (heth->Instance)->MACFFR;
1388 HAL_Delay(ETH_REG_WRITE_DELAY);
1389 (heth->Instance)->MACFFR = tmpreg1;
1390
1391 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
1392 /* Write to ETHERNET MACHTHR */
1393 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
1394
1395 /* Write to ETHERNET MACHTLR */
1396 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
1397 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
1398
1399 /* Get the ETHERNET MACFCR value */
1400 tmpreg1 = (heth->Instance)->MACFCR;
1401 /* Clear xx bits */
1402 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
1403
1404 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
1405 macconf->ZeroQuantaPause |
1406 macconf->PauseLowThreshold |
1407 macconf->UnicastPauseFrameDetect |
1408 macconf->ReceiveFlowControl |
1409 macconf->TransmitFlowControl);
1410
1411 /* Write to ETHERNET MACFCR */
1412 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
1413
1414 /* Wait until the write operation will be taken into account :
1415 at least four TX_CLK/RX_CLK clock cycles */
1416 tmpreg1 = (heth->Instance)->MACFCR;
1417 HAL_Delay(ETH_REG_WRITE_DELAY);
1418 (heth->Instance)->MACFCR = tmpreg1;
1419
1420 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
1421 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
1422 macconf->VLANTagIdentifier);
1423
1424 /* Wait until the write operation will be taken into account :
1425 at least four TX_CLK/RX_CLK clock cycles */
1426 tmpreg1 = (heth->Instance)->MACVLANTR;
1427 HAL_Delay(ETH_REG_WRITE_DELAY);
1428 (heth->Instance)->MACVLANTR = tmpreg1;
1429 }
1430 else /* macconf == NULL : here we just configure Speed and Duplex mode */
1431 {
1432 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1433 /* Get the ETHERNET MACCR value */
1434 tmpreg1 = (heth->Instance)->MACCR;
1435
1436 /* Clear FES and DM bits */
1437 tmpreg1 &= ~(0x00004800U);
1438
1439 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
1440
1441 /* Write to ETHERNET MACCR */
1442 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
1443
1444 /* Wait until the write operation will be taken into account:
1445 at least four TX_CLK/RX_CLK clock cycles */
1446 tmpreg1 = (heth->Instance)->MACCR;
1447 HAL_Delay(ETH_REG_WRITE_DELAY);
1448 (heth->Instance)->MACCR = tmpreg1;
1449 }
1450
1451 /* Set the ETH state to Ready */
1452 heth->State= HAL_ETH_STATE_READY;
1453
1454 /* Process Unlocked */
1455 __HAL_UNLOCK(heth);
1456
1457 /* Return function status */
1458 return HAL_OK;
1459 }
1460
1461 /**
1462 * @brief Sets ETH DMA Configuration.
1463 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1464 * the configuration information for ETHERNET module
1465 * @param dmaconf DMA Configuration structure
1466 * @retval HAL status
1467 */
1468 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
1469 {
1470 uint32_t tmpreg1 = 0U;
1471
1472 /* Process Locked */
1473 __HAL_LOCK(heth);
1474
1475 /* Set the ETH peripheral state to BUSY */
1476 heth->State= HAL_ETH_STATE_BUSY;
1477
1478 /* Check parameters */
1479 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
1480 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
1481 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
1482 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
1483 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
1484 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
1485 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
1486 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
1487 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
1488 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
1489 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
1490 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
1491 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
1492 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
1493 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
1494 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
1495
1496 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
1497 /* Get the ETHERNET DMAOMR value */
1498 tmpreg1 = (heth->Instance)->DMAOMR;
1499 /* Clear xx bits */
1500 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
1501
1502 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
1503 dmaconf->ReceiveStoreForward |
1504 dmaconf->FlushReceivedFrame |
1505 dmaconf->TransmitStoreForward |
1506 dmaconf->TransmitThresholdControl |
1507 dmaconf->ForwardErrorFrames |
1508 dmaconf->ForwardUndersizedGoodFrames |
1509 dmaconf->ReceiveThresholdControl |
1510 dmaconf->SecondFrameOperate);
1511
1512 /* Write to ETHERNET DMAOMR */
1513 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
1514
1515 /* Wait until the write operation will be taken into account:
1516 at least four TX_CLK/RX_CLK clock cycles */
1517 tmpreg1 = (heth->Instance)->DMAOMR;
1518 HAL_Delay(ETH_REG_WRITE_DELAY);
1519 (heth->Instance)->DMAOMR = tmpreg1;
1520
1521 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
1522 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
1523 dmaconf->FixedBurst |
1524 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1525 dmaconf->TxDMABurstLength |
1526 dmaconf->EnhancedDescriptorFormat |
1527 (dmaconf->DescriptorSkipLength << 2U) |
1528 dmaconf->DMAArbitration |
1529 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1530
1531 /* Wait until the write operation will be taken into account:
1532 at least four TX_CLK/RX_CLK clock cycles */
1533 tmpreg1 = (heth->Instance)->DMABMR;
1534 HAL_Delay(ETH_REG_WRITE_DELAY);
1535 (heth->Instance)->DMABMR = tmpreg1;
1536
1537 /* Set the ETH state to Ready */
1538 heth->State= HAL_ETH_STATE_READY;
1539
1540 /* Process Unlocked */
1541 __HAL_UNLOCK(heth);
1542
1543 /* Return function status */
1544 return HAL_OK;
1545 }
1546
1547 /**
1548 * @}
1549 */
1550
1551 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
1552 * @brief Peripheral State functions
1553 *
1554 @verbatim
1555 ===============================================================================
1556 ##### Peripheral State functions #####
1557 ===============================================================================
1558 [..]
1559 This subsection permits to get in run-time the status of the peripheral
1560 and the data flow.
1561 (+) Get the ETH handle state:
1562 HAL_ETH_GetState();
1563
1564
1565 @endverbatim
1566 * @{
1567 */
1568
1569 /**
1570 * @brief Return the ETH HAL state
1571 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1572 * the configuration information for ETHERNET module
1573 * @retval HAL state
1574 */
1575 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
1576 {
1577 /* Return ETH state */
1578 return heth->State;
1579 }
1580
1581 /**
1582 * @}
1583 */
1584
1585 /**
1586 * @}
1587 */
1588
1589 /** @addtogroup ETH_Private_Functions
1590 * @{
1591 */
1592
1593 /**
1594 * @brief Configures Ethernet MAC and DMA with default parameters.
1595 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1596 * the configuration information for ETHERNET module
1597 * @param err Ethernet Init error
1598 * @retval HAL status
1599 */
1600 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
1601 {
1602 ETH_MACInitTypeDef macinit;
1603 ETH_DMAInitTypeDef dmainit;
1604 uint32_t tmpreg1 = 0U;
1605
1606 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
1607 {
1608 /* Set Ethernet duplex mode to Full-duplex */
1609 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
1610
1611 /* Set Ethernet speed to 100M */
1612 (heth->Init).Speed = ETH_SPEED_100M;
1613 }
1614
1615 /* Ethernet MAC default initialization **************************************/
1616 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
1617 macinit.Jabber = ETH_JABBER_ENABLE;
1618 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
1619 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
1620 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
1621 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
1622 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
1623 {
1624 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
1625 }
1626 else
1627 {
1628 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
1629 }
1630 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
1631 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
1632 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
1633 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
1634 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
1635 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
1636 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
1637 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
1638 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
1639 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
1640 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
1641 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
1642 macinit.HashTableHigh = 0x0U;
1643 macinit.HashTableLow = 0x0U;
1644 macinit.PauseTime = 0x0U;
1645 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
1646 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
1647 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
1648 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
1649 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
1650 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
1651 macinit.VLANTagIdentifier = 0x0U;
1652
1653 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1654 /* Get the ETHERNET MACCR value */
1655 tmpreg1 = (heth->Instance)->MACCR;
1656 /* Clear WD, PCE, PS, TE and RE bits */
1657 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
1658 /* Set the WD bit according to ETH Watchdog value */
1659 /* Set the JD: bit according to ETH Jabber value */
1660 /* Set the IFG bit according to ETH InterFrameGap value */
1661 /* Set the DCRS bit according to ETH CarrierSense value */
1662 /* Set the FES bit according to ETH Speed value */
1663 /* Set the DO bit according to ETH ReceiveOwn value */
1664 /* Set the LM bit according to ETH LoopbackMode value */
1665 /* Set the DM bit according to ETH Mode value */
1666 /* Set the IPCO bit according to ETH ChecksumOffload value */
1667 /* Set the DR bit according to ETH RetryTransmission value */
1668 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
1669 /* Set the BL bit according to ETH BackOffLimit value */
1670 /* Set the DC bit according to ETH DeferralCheck value */
1671 tmpreg1 |= (uint32_t)(macinit.Watchdog |
1672 macinit.Jabber |
1673 macinit.InterFrameGap |
1674 macinit.CarrierSense |
1675 (heth->Init).Speed |
1676 macinit.ReceiveOwn |
1677 macinit.LoopbackMode |
1678 (heth->Init).DuplexMode |
1679 macinit.ChecksumOffload |
1680 macinit.RetryTransmission |
1681 macinit.AutomaticPadCRCStrip |
1682 macinit.BackOffLimit |
1683 macinit.DeferralCheck);
1684
1685 /* Write to ETHERNET MACCR */
1686 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
1687
1688 /* Wait until the write operation will be taken into account:
1689 at least four TX_CLK/RX_CLK clock cycles */
1690 tmpreg1 = (heth->Instance)->MACCR;
1691 HAL_Delay(ETH_REG_WRITE_DELAY);
1692 (heth->Instance)->MACCR = tmpreg1;
1693
1694 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1695 /* Set the RA bit according to ETH ReceiveAll value */
1696 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
1697 /* Set the PCF bit according to ETH PassControlFrames value */
1698 /* Set the DBF bit according to ETH BroadcastFramesReception value */
1699 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
1700 /* Set the PR bit according to ETH PromiscuousMode value */
1701 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
1702 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
1703 /* Write to ETHERNET MACFFR */
1704 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
1705 macinit.SourceAddrFilter |
1706 macinit.PassControlFrames |
1707 macinit.BroadcastFramesReception |
1708 macinit.DestinationAddrFilter |
1709 macinit.PromiscuousMode |
1710 macinit.MulticastFramesFilter |
1711 macinit.UnicastFramesFilter);
1712
1713 /* Wait until the write operation will be taken into account:
1714 at least four TX_CLK/RX_CLK clock cycles */
1715 tmpreg1 = (heth->Instance)->MACFFR;
1716 HAL_Delay(ETH_REG_WRITE_DELAY);
1717 (heth->Instance)->MACFFR = tmpreg1;
1718
1719 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
1720 /* Write to ETHERNET MACHTHR */
1721 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
1722
1723 /* Write to ETHERNET MACHTLR */
1724 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
1725 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
1726
1727 /* Get the ETHERNET MACFCR value */
1728 tmpreg1 = (heth->Instance)->MACFCR;
1729 /* Clear xx bits */
1730 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
1731
1732 /* Set the PT bit according to ETH PauseTime value */
1733 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
1734 /* Set the PLT bit according to ETH PauseLowThreshold value */
1735 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
1736 /* Set the RFE bit according to ETH ReceiveFlowControl value */
1737 /* Set the TFE bit according to ETH TransmitFlowControl value */
1738 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
1739 macinit.ZeroQuantaPause |
1740 macinit.PauseLowThreshold |
1741 macinit.UnicastPauseFrameDetect |
1742 macinit.ReceiveFlowControl |
1743 macinit.TransmitFlowControl);
1744
1745 /* Write to ETHERNET MACFCR */
1746 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
1747
1748 /* Wait until the write operation will be taken into account:
1749 at least four TX_CLK/RX_CLK clock cycles */
1750 tmpreg1 = (heth->Instance)->MACFCR;
1751 HAL_Delay(ETH_REG_WRITE_DELAY);
1752 (heth->Instance)->MACFCR = tmpreg1;
1753
1754 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
1755 /* Set the ETV bit according to ETH VLANTagComparison value */
1756 /* Set the VL bit according to ETH VLANTagIdentifier value */
1757 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
1758 macinit.VLANTagIdentifier);
1759
1760 /* Wait until the write operation will be taken into account:
1761 at least four TX_CLK/RX_CLK clock cycles */
1762 tmpreg1 = (heth->Instance)->MACVLANTR;
1763 HAL_Delay(ETH_REG_WRITE_DELAY);
1764 (heth->Instance)->MACVLANTR = tmpreg1;
1765
1766 /* Ethernet DMA default initialization ************************************/
1767 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
1768 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
1769 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
1770 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
1771 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
1772 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
1773 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
1774 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
1775 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
1776 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
1777 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
1778 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
1779 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
1780 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
1781 dmainit.DescriptorSkipLength = 0x0U;
1782 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
1783
1784 /* Get the ETHERNET DMAOMR value */
1785 tmpreg1 = (heth->Instance)->DMAOMR;
1786 /* Clear xx bits */
1787 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
1788
1789 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
1790 /* Set the RSF bit according to ETH ReceiveStoreForward value */
1791 /* Set the DFF bit according to ETH FlushReceivedFrame value */
1792 /* Set the TSF bit according to ETH TransmitStoreForward value */
1793 /* Set the TTC bit according to ETH TransmitThresholdControl value */
1794 /* Set the FEF bit according to ETH ForwardErrorFrames value */
1795 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
1796 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
1797 /* Set the OSF bit according to ETH SecondFrameOperate value */
1798 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
1799 dmainit.ReceiveStoreForward |
1800 dmainit.FlushReceivedFrame |
1801 dmainit.TransmitStoreForward |
1802 dmainit.TransmitThresholdControl |
1803 dmainit.ForwardErrorFrames |
1804 dmainit.ForwardUndersizedGoodFrames |
1805 dmainit.ReceiveThresholdControl |
1806 dmainit.SecondFrameOperate);
1807
1808 /* Write to ETHERNET DMAOMR */
1809 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
1810
1811 /* Wait until the write operation will be taken into account:
1812 at least four TX_CLK/RX_CLK clock cycles */
1813 tmpreg1 = (heth->Instance)->DMAOMR;
1814 HAL_Delay(ETH_REG_WRITE_DELAY);
1815 (heth->Instance)->DMAOMR = tmpreg1;
1816
1817 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
1818 /* Set the AAL bit according to ETH AddressAlignedBeats value */
1819 /* Set the FB bit according to ETH FixedBurst value */
1820 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
1821 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
1822 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
1823 /* Set the DSL bit according to ETH DesciptorSkipLength value */
1824 /* Set the PR and DA bits according to ETH DMAArbitration value */
1825 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
1826 dmainit.FixedBurst |
1827 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1828 dmainit.TxDMABurstLength |
1829 dmainit.EnhancedDescriptorFormat |
1830 (dmainit.DescriptorSkipLength << 2U) |
1831 dmainit.DMAArbitration |
1832 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1833
1834 /* Wait until the write operation will be taken into account:
1835 at least four TX_CLK/RX_CLK clock cycles */
1836 tmpreg1 = (heth->Instance)->DMABMR;
1837 HAL_Delay(ETH_REG_WRITE_DELAY);
1838 (heth->Instance)->DMABMR = tmpreg1;
1839
1840 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
1841 {
1842 /* Enable the Ethernet Rx Interrupt */
1843 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
1844 }
1845
1846 /* Initialize MAC address in ethernet MAC */
1847 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
1848 }
1849
1850 /**
1851 * @brief Configures the selected MAC address.
1852 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1853 * the configuration information for ETHERNET module
1854 * @param MacAddr The MAC address to configure
1855 * This parameter can be one of the following values:
1856 * @arg ETH_MAC_Address0: MAC Address0
1857 * @arg ETH_MAC_Address1: MAC Address1
1858 * @arg ETH_MAC_Address2: MAC Address2
1859 * @arg ETH_MAC_Address3: MAC Address3
1860 * @param Addr Pointer to MAC address buffer data (6 bytes)
1861 * @retval HAL status
1862 */
1863 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
1864 {
1865 uint32_t tmpreg1;
1866
1867 /* Prevent unused argument(s) compilation warning */
1868 UNUSED(heth);
1869
1870 /* Check the parameters */
1871 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1872
1873 /* Calculate the selected MAC address high register */
1874 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
1875 /* Load the selected MAC address high register */
1876 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
1877 /* Calculate the selected MAC address low register */
1878 tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
1879
1880 /* Load the selected MAC address low register */
1881 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
1882 }
1883
1884 /**
1885 * @brief Enables the MAC transmission.
1886 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1887 * the configuration information for ETHERNET module
1888 * @retval None
1889 */
1890 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
1891 {
1892 __IO uint32_t tmpreg1 = 0U;
1893
1894 /* Enable the MAC transmission */
1895 (heth->Instance)->MACCR |= ETH_MACCR_TE;
1896
1897 /* Wait until the write operation will be taken into account:
1898 at least four TX_CLK/RX_CLK clock cycles */
1899 tmpreg1 = (heth->Instance)->MACCR;
1900 ETH_Delay(ETH_REG_WRITE_DELAY);
1901 (heth->Instance)->MACCR = tmpreg1;
1902 }
1903
1904 /**
1905 * @brief Disables the MAC transmission.
1906 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1907 * the configuration information for ETHERNET module
1908 * @retval None
1909 */
1910 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
1911 {
1912 __IO uint32_t tmpreg1 = 0U;
1913
1914 /* Disable the MAC transmission */
1915 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
1916
1917 /* Wait until the write operation will be taken into account:
1918 at least four TX_CLK/RX_CLK clock cycles */
1919 tmpreg1 = (heth->Instance)->MACCR;
1920 ETH_Delay(ETH_REG_WRITE_DELAY);
1921 (heth->Instance)->MACCR = tmpreg1;
1922 }
1923
1924 /**
1925 * @brief Enables the MAC reception.
1926 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1927 * the configuration information for ETHERNET module
1928 * @retval None
1929 */
1930 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
1931 {
1932 __IO uint32_t tmpreg1 = 0U;
1933
1934 /* Enable the MAC reception */
1935 (heth->Instance)->MACCR |= ETH_MACCR_RE;
1936
1937 /* Wait until the write operation will be taken into account:
1938 at least four TX_CLK/RX_CLK clock cycles */
1939 tmpreg1 = (heth->Instance)->MACCR;
1940 ETH_Delay(ETH_REG_WRITE_DELAY);
1941 (heth->Instance)->MACCR = tmpreg1;
1942 }
1943
1944 /**
1945 * @brief Disables the MAC reception.
1946 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1947 * the configuration information for ETHERNET module
1948 * @retval None
1949 */
1950 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
1951 {
1952 __IO uint32_t tmpreg1 = 0U;
1953
1954 /* Disable the MAC reception */
1955 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
1956
1957 /* Wait until the write operation will be taken into account:
1958 at least four TX_CLK/RX_CLK clock cycles */
1959 tmpreg1 = (heth->Instance)->MACCR;
1960 ETH_Delay(ETH_REG_WRITE_DELAY);
1961 (heth->Instance)->MACCR = tmpreg1;
1962 }
1963
1964 /**
1965 * @brief Enables the DMA transmission.
1966 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1967 * the configuration information for ETHERNET module
1968 * @retval None
1969 */
1970 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
1971 {
1972 /* Enable the DMA transmission */
1973 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
1974 }
1975
1976 /**
1977 * @brief Disables the DMA transmission.
1978 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1979 * the configuration information for ETHERNET module
1980 * @retval None
1981 */
1982 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
1983 {
1984 /* Disable the DMA transmission */
1985 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
1986 }
1987
1988 /**
1989 * @brief Enables the DMA reception.
1990 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1991 * the configuration information for ETHERNET module
1992 * @retval None
1993 */
1994 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
1995 {
1996 /* Enable the DMA reception */
1997 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
1998 }
1999
2000 /**
2001 * @brief Disables the DMA reception.
2002 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2003 * the configuration information for ETHERNET module
2004 * @retval None
2005 */
2006 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
2007 {
2008 /* Disable the DMA reception */
2009 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
2010 }
2011
2012 /**
2013 * @brief Clears the ETHERNET transmit FIFO.
2014 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2015 * the configuration information for ETHERNET module
2016 * @retval None
2017 */
2018 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
2019 {
2020 __IO uint32_t tmpreg1 = 0U;
2021
2022 /* Set the Flush Transmit FIFO bit */
2023 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
2024
2025 /* Wait until the write operation will be taken into account:
2026 at least four TX_CLK/RX_CLK clock cycles */
2027 tmpreg1 = (heth->Instance)->DMAOMR;
2028 ETH_Delay(ETH_REG_WRITE_DELAY);
2029 (heth->Instance)->DMAOMR = tmpreg1;
2030 }
2031
2032 /**
2033 * @brief This function provides delay (in milliseconds) based on CPU cycles method.
2034 * @param mdelay specifies the delay time length, in milliseconds.
2035 * @retval None
2036 */
2037 static void ETH_Delay(uint32_t mdelay)
2038 {
2039 __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
2040 do
2041 {
2042 __NOP();
2043 }
2044 while (Delay --);
2045 }
2046
2047 /**
2048 * @}
2049 */
2050
2051 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
2052 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
2053 #endif /* HAL_ETH_MODULE_ENABLED */
2054 /**
2055 * @}
2056 */
2057
2058 /**
2059 * @}
2060 */
2061
2062 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/