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comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_dma2d.c | |
4 * @author MCD Application Team | |
5 * @brief DMA2D HAL module driver. | |
6 * This file provides firmware functions to manage the following | |
7 * functionalities of the DMA2D peripheral: | |
8 * + Initialization and de-initialization functions | |
9 * + IO operation functions | |
10 * + Peripheral Control functions | |
11 * + Peripheral State and Errors functions | |
12 * | |
13 @verbatim | |
14 ============================================================================== | |
15 ##### How to use this driver ##### | |
16 ============================================================================== | |
17 [..] | |
18 (#) Program the required configuration through the following parameters: | |
19 the transfer mode, the output color mode and the output offset using | |
20 HAL_DMA2D_Init() function. | |
21 | |
22 (#) Program the required configuration through the following parameters: | |
23 the input color mode, the input color, the input alpha value, the alpha mode, | |
24 and the input offset using HAL_DMA2D_ConfigLayer() function for foreground | |
25 or/and background layer. | |
26 | |
27 *** Polling mode IO operation *** | |
28 ================================= | |
29 [..] | |
30 (#) Configure pdata parameter (explained hereafter), destination and data length | |
31 and enable the transfer using HAL_DMA2D_Start(). | |
32 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage | |
33 user can specify the value of timeout according to his end application. | |
34 | |
35 *** Interrupt mode IO operation *** | |
36 =================================== | |
37 [..] | |
38 (#) Configure pdata parameter, destination and data length and enable | |
39 the transfer using HAL_DMA2D_Start_IT(). | |
40 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine | |
41 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can | |
42 add his own function by customization of function pointer XferCpltCallback (member | |
43 of DMA2D handle structure). | |
44 (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback | |
45 XferErrorCallback. | |
46 | |
47 -@- In Register-to-Memory transfer mode, pdata parameter is the register | |
48 color, in Memory-to-memory or Memory-to-Memory with pixel format | |
49 conversion pdata is the source address. | |
50 | |
51 -@- Configure the foreground source address, the background source address, | |
52 the destination and data length then Enable the transfer using | |
53 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() | |
54 in interrupt mode | |
55 | |
56 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions | |
57 are used if the memory to memory with blending transfer mode is selected. | |
58 | |
59 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling | |
60 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode. | |
61 | |
62 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent() | |
63 | |
64 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two | |
65 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime() | |
66 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or | |
67 HAL_DMA2D_DisableDeadTime(). | |
68 | |
69 (#) The transfer can be suspended, resumed and aborted using the following | |
70 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). | |
71 | |
72 (#) The CLUT loading can be suspended, resumed and aborted using the following | |
73 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), | |
74 HAL_DMA2D_CLUTLoading_Abort(). | |
75 | |
76 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). | |
77 | |
78 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). | |
79 | |
80 *** DMA2D HAL driver macros list *** | |
81 ============================================= | |
82 [..] | |
83 Below the list of most used macros in DMA2D HAL driver : | |
84 | |
85 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. | |
86 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. | |
87 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. | |
88 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. | |
89 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. | |
90 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not | |
91 | |
92 [..] | |
93 (@) You can refer to the DMA2D HAL driver header file for more useful macros | |
94 | |
95 @endverbatim | |
96 ****************************************************************************** | |
97 * @attention | |
98 * | |
99 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
100 * | |
101 * Redistribution and use in source and binary forms, with or without modification, | |
102 * are permitted provided that the following conditions are met: | |
103 * 1. Redistributions of source code must retain the above copyright notice, | |
104 * this list of conditions and the following disclaimer. | |
105 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
106 * this list of conditions and the following disclaimer in the documentation | |
107 * and/or other materials provided with the distribution. | |
108 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
109 * may be used to endorse or promote products derived from this software | |
110 * without specific prior written permission. | |
111 * | |
112 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
113 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
114 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
115 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
116 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
117 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
118 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
119 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
120 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
121 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
122 * | |
123 ****************************************************************************** | |
124 */ | |
125 | |
126 /* Includes ------------------------------------------------------------------*/ | |
127 #include "stm32f4xx_hal.h" | |
128 | |
129 /** @addtogroup STM32F4xx_HAL_Driver | |
130 * @{ | |
131 */ | |
132 | |
133 /** @defgroup DMA2D DMA2D | |
134 * @brief DMA2D HAL module driver | |
135 * @{ | |
136 */ | |
137 | |
138 #ifdef HAL_DMA2D_MODULE_ENABLED | |
139 | |
140 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) | |
141 | |
142 /* Private types -------------------------------------------------------------*/ | |
143 /* Private define ------------------------------------------------------------*/ | |
144 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants | |
145 * @{ | |
146 */ | |
147 | |
148 /** @defgroup DMA2D_TimeOut DMA2D Time Out | |
149 * @{ | |
150 */ | |
151 #define DMA2D_TIMEOUT_ABORT 1000U /*!< 1s */ | |
152 #define DMA2D_TIMEOUT_SUSPEND 1000U /*!< 1s */ | |
153 /** | |
154 * @} | |
155 */ | |
156 | |
157 /** @defgroup DMA2D_Shifts DMA2D Shifts | |
158 * @{ | |
159 */ | |
160 #define DMA2D_POSITION_FGPFCCR_CS (uint32_t)DMA2D_FGPFCCR_CS_Pos /*!< Required left shift to set foreground CLUT size */ | |
161 #define DMA2D_POSITION_BGPFCCR_CS (uint32_t)DMA2D_BGPFCCR_CS_Pos /*!< Required left shift to set background CLUT size */ | |
162 | |
163 #define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)DMA2D_FGPFCCR_CCM_Pos /*!< Required left shift to set foreground CLUT color mode */ | |
164 #define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)DMA2D_BGPFCCR_CCM_Pos /*!< Required left shift to set background CLUT color mode */ | |
165 | |
166 #define DMA2D_POSITION_AMTCR_DT (uint32_t)DMA2D_AMTCR_DT_Pos /*!< Required left shift to set deadtime value */ | |
167 | |
168 #define DMA2D_POSITION_FGPFCCR_AM (uint32_t)DMA2D_FGPFCCR_AM_Pos /*!< Required left shift to set foreground alpha mode */ | |
169 #define DMA2D_POSITION_BGPFCCR_AM (uint32_t)DMA2D_BGPFCCR_AM_Pos /*!< Required left shift to set background alpha mode */ | |
170 | |
171 #define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)DMA2D_FGPFCCR_ALPHA_Pos /*!< Required left shift to set foreground alpha value */ | |
172 #define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)DMA2D_BGPFCCR_ALPHA_Pos /*!< Required left shift to set background alpha value */ | |
173 | |
174 #define DMA2D_POSITION_NLR_PL (uint32_t)DMA2D_NLR_PL_Pos /*!< Required left shift to set pixels per lines value */ | |
175 /** | |
176 * @} | |
177 */ | |
178 | |
179 /** | |
180 * @} | |
181 */ | |
182 | |
183 /* Private variables ---------------------------------------------------------*/ | |
184 /* Private constants ---------------------------------------------------------*/ | |
185 /* Private macro -------------------------------------------------------------*/ | |
186 /* Private function prototypes -----------------------------------------------*/ | |
187 /** @addtogroup DMA2D_Private_Functions_Prototypes | |
188 * @{ | |
189 */ | |
190 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); | |
191 /** | |
192 * @} | |
193 */ | |
194 | |
195 /* Private functions ---------------------------------------------------------*/ | |
196 /* Exported functions --------------------------------------------------------*/ | |
197 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions | |
198 * @{ | |
199 */ | |
200 | |
201 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions | |
202 * @brief Initialization and Configuration functions | |
203 * | |
204 @verbatim | |
205 =============================================================================== | |
206 ##### Initialization and Configuration functions ##### | |
207 =============================================================================== | |
208 [..] This section provides functions allowing to: | |
209 (+) Initialize and configure the DMA2D | |
210 (+) De-initialize the DMA2D | |
211 | |
212 @endverbatim | |
213 * @{ | |
214 */ | |
215 | |
216 /** | |
217 * @brief Initialize the DMA2D according to the specified | |
218 * parameters in the DMA2D_InitTypeDef and create the associated handle. | |
219 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
220 * the configuration information for the DMA2D. | |
221 * @retval HAL status | |
222 */ | |
223 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) | |
224 { | |
225 /* Check the DMA2D peripheral state */ | |
226 if(hdma2d == NULL) | |
227 { | |
228 return HAL_ERROR; | |
229 } | |
230 | |
231 /* Check the parameters */ | |
232 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); | |
233 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); | |
234 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); | |
235 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); | |
236 | |
237 if(hdma2d->State == HAL_DMA2D_STATE_RESET) | |
238 { | |
239 /* Allocate lock resource and initialize it */ | |
240 hdma2d->Lock = HAL_UNLOCKED; | |
241 /* Init the low level hardware */ | |
242 HAL_DMA2D_MspInit(hdma2d); | |
243 } | |
244 | |
245 /* Change DMA2D peripheral state */ | |
246 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
247 | |
248 /* DMA2D CR register configuration -------------------------------------------*/ | |
249 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); | |
250 | |
251 /* DMA2D OPFCCR register configuration ---------------------------------------*/ | |
252 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); | |
253 | |
254 /* DMA2D OOR register configuration ------------------------------------------*/ | |
255 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); | |
256 | |
257 /* Update error code */ | |
258 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; | |
259 | |
260 /* Initialize the DMA2D state*/ | |
261 hdma2d->State = HAL_DMA2D_STATE_READY; | |
262 | |
263 return HAL_OK; | |
264 } | |
265 | |
266 /** | |
267 * @brief Deinitializes the DMA2D peripheral registers to their default reset | |
268 * values. | |
269 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
270 * the configuration information for the DMA2D. | |
271 * @retval None | |
272 */ | |
273 | |
274 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) | |
275 { | |
276 /* Check the DMA2D peripheral state */ | |
277 if(hdma2d == NULL) | |
278 { | |
279 return HAL_ERROR; | |
280 } | |
281 | |
282 /* Before aborting any DMA2D transfer or CLUT loading, check | |
283 first whether or not DMA2D clock is enabled */ | |
284 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) | |
285 { | |
286 /* Abort DMA2D transfer if any */ | |
287 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) | |
288 { | |
289 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK) | |
290 { | |
291 /* Issue when aborting DMA2D transfer */ | |
292 return HAL_ERROR; | |
293 } | |
294 } | |
295 else | |
296 { | |
297 /* Abort background CLUT loading if any */ | |
298 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) | |
299 { | |
300 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK) | |
301 { | |
302 /* Issue when aborting background CLUT loading */ | |
303 return HAL_ERROR; | |
304 } | |
305 } | |
306 else | |
307 { | |
308 /* Abort foreground CLUT loading if any */ | |
309 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) | |
310 { | |
311 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK) | |
312 { | |
313 /* Issue when aborting foreground CLUT loading */ | |
314 return HAL_ERROR; | |
315 } | |
316 } | |
317 } | |
318 } | |
319 } | |
320 | |
321 /* Carry on with de-initialization of low level hardware */ | |
322 HAL_DMA2D_MspDeInit(hdma2d); | |
323 | |
324 /* Reset DMA2D control registers*/ | |
325 hdma2d->Instance->CR = 0U; | |
326 hdma2d->Instance->FGOR = 0U; | |
327 hdma2d->Instance->BGOR = 0U; | |
328 hdma2d->Instance->FGPFCCR = 0U; | |
329 hdma2d->Instance->BGPFCCR = 0U; | |
330 hdma2d->Instance->OPFCCR = 0U; | |
331 | |
332 /* Update error code */ | |
333 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; | |
334 | |
335 /* Initialize the DMA2D state*/ | |
336 hdma2d->State = HAL_DMA2D_STATE_RESET; | |
337 | |
338 /* Release Lock */ | |
339 __HAL_UNLOCK(hdma2d); | |
340 | |
341 return HAL_OK; | |
342 } | |
343 | |
344 /** | |
345 * @brief Initializes the DMA2D MSP. | |
346 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
347 * the configuration information for the DMA2D. | |
348 * @retval None | |
349 */ | |
350 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) | |
351 { | |
352 /* Prevent unused argument(s) compilation warning */ | |
353 UNUSED(hdma2d); | |
354 | |
355 /* NOTE : This function should not be modified; when the callback is needed, | |
356 the HAL_DMA2D_MspInit can be implemented in the user file. | |
357 */ | |
358 } | |
359 | |
360 /** | |
361 * @brief DeInitializes the DMA2D MSP. | |
362 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
363 * the configuration information for the DMA2D. | |
364 * @retval None | |
365 */ | |
366 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) | |
367 { | |
368 /* Prevent unused argument(s) compilation warning */ | |
369 UNUSED(hdma2d); | |
370 | |
371 /* NOTE : This function should not be modified; when the callback is needed, | |
372 the HAL_DMA2D_MspDeInit can be implemented in the user file. | |
373 */ | |
374 } | |
375 | |
376 /** | |
377 * @} | |
378 */ | |
379 | |
380 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions | |
381 * @brief IO operation functions | |
382 * | |
383 @verbatim | |
384 =============================================================================== | |
385 ##### IO operation functions ##### | |
386 =============================================================================== | |
387 [..] This section provides functions allowing to: | |
388 (+) Configure the pdata, destination address and data size then | |
389 start the DMA2D transfer. | |
390 (+) Configure the source for foreground and background, destination address | |
391 and data size then start a MultiBuffer DMA2D transfer. | |
392 (+) Configure the pdata, destination address and data size then | |
393 start the DMA2D transfer with interrupt. | |
394 (+) Configure the source for foreground and background, destination address | |
395 and data size then start a MultiBuffer DMA2D transfer with interrupt. | |
396 (+) Abort DMA2D transfer. | |
397 (+) Suspend DMA2D transfer. | |
398 (+) Resume DMA2D transfer. | |
399 (+) Enable CLUT transfer. | |
400 (+) Configure CLUT loading then start transfer in polling mode. | |
401 (+) Configure CLUT loading then start transfer in interrupt mode. | |
402 (+) Abort DMA2D CLUT loading. | |
403 (+) Suspend DMA2D CLUT loading. | |
404 (+) Resume DMA2D CLUT loading. | |
405 (+) Poll for transfer complete. | |
406 (+) handle DMA2D interrupt request. | |
407 (+) Transfer watermark callback. | |
408 (+) CLUT Transfer Complete callback. | |
409 | |
410 @endverbatim | |
411 * @{ | |
412 */ | |
413 | |
414 /** | |
415 * @brief Start the DMA2D Transfer. | |
416 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
417 * the configuration information for the DMA2D. | |
418 * @param pdata Configure the source memory Buffer address if | |
419 * Memory-to-Memory or Memory-to-Memory with pixel format | |
420 * conversion mode is selected, or configure | |
421 * the color value if Register-to-Memory mode is selected. | |
422 * @param DstAddress The destination memory Buffer address. | |
423 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). | |
424 * @param Height The height of data to be transferred from source to destination (expressed in number of lines). | |
425 * @retval HAL status | |
426 */ | |
427 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) | |
428 { | |
429 /* Check the parameters */ | |
430 assert_param(IS_DMA2D_LINE(Height)); | |
431 assert_param(IS_DMA2D_PIXEL(Width)); | |
432 | |
433 /* Process locked */ | |
434 __HAL_LOCK(hdma2d); | |
435 | |
436 /* Change DMA2D peripheral state */ | |
437 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
438 | |
439 /* Configure the source, destination address and the data size */ | |
440 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); | |
441 | |
442 /* Enable the Peripheral */ | |
443 __HAL_DMA2D_ENABLE(hdma2d); | |
444 | |
445 return HAL_OK; | |
446 } | |
447 | |
448 /** | |
449 * @brief Start the DMA2D Transfer with interrupt enabled. | |
450 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
451 * the configuration information for the DMA2D. | |
452 * @param pdata Configure the source memory Buffer address if | |
453 * the Memory-to-Memory or Memory-to-Memory with pixel format | |
454 * conversion mode is selected, or configure | |
455 * the color value if Register-to-Memory mode is selected. | |
456 * @param DstAddress The destination memory Buffer address. | |
457 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). | |
458 * @param Height The height of data to be transferred from source to destination (expressed in number of lines). | |
459 * @retval HAL status | |
460 */ | |
461 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) | |
462 { | |
463 /* Check the parameters */ | |
464 assert_param(IS_DMA2D_LINE(Height)); | |
465 assert_param(IS_DMA2D_PIXEL(Width)); | |
466 | |
467 /* Process locked */ | |
468 __HAL_LOCK(hdma2d); | |
469 | |
470 /* Change DMA2D peripheral state */ | |
471 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
472 | |
473 /* Configure the source, destination address and the data size */ | |
474 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); | |
475 | |
476 /* Enable the transfer complete, transfer error and configuration error interrupts */ | |
477 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); | |
478 | |
479 /* Enable the Peripheral */ | |
480 __HAL_DMA2D_ENABLE(hdma2d); | |
481 | |
482 return HAL_OK; | |
483 } | |
484 | |
485 /** | |
486 * @brief Start the multi-source DMA2D Transfer. | |
487 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
488 * the configuration information for the DMA2D. | |
489 * @param SrcAddress1 The source memory Buffer address for the foreground layer. | |
490 * @param SrcAddress2 The source memory Buffer address for the background layer. | |
491 * @param DstAddress The destination memory Buffer address. | |
492 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). | |
493 * @param Height The height of data to be transferred from source to destination (expressed in number of lines). | |
494 * @retval HAL status | |
495 */ | |
496 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) | |
497 { | |
498 /* Check the parameters */ | |
499 assert_param(IS_DMA2D_LINE(Height)); | |
500 assert_param(IS_DMA2D_PIXEL(Width)); | |
501 | |
502 /* Process locked */ | |
503 __HAL_LOCK(hdma2d); | |
504 | |
505 /* Change DMA2D peripheral state */ | |
506 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
507 | |
508 /* Configure DMA2D Stream source2 address */ | |
509 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); | |
510 | |
511 /* Configure the source, destination address and the data size */ | |
512 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); | |
513 | |
514 /* Enable the Peripheral */ | |
515 __HAL_DMA2D_ENABLE(hdma2d); | |
516 | |
517 return HAL_OK; | |
518 } | |
519 | |
520 /** | |
521 * @brief Start the multi-source DMA2D Transfer with interrupt enabled. | |
522 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
523 * the configuration information for the DMA2D. | |
524 * @param SrcAddress1 The source memory Buffer address for the foreground layer. | |
525 * @param SrcAddress2 The source memory Buffer address for the background layer. | |
526 * @param DstAddress The destination memory Buffer address. | |
527 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). | |
528 * @param Height The height of data to be transferred from source to destination (expressed in number of lines). | |
529 * @retval HAL status | |
530 */ | |
531 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) | |
532 { | |
533 /* Check the parameters */ | |
534 assert_param(IS_DMA2D_LINE(Height)); | |
535 assert_param(IS_DMA2D_PIXEL(Width)); | |
536 | |
537 /* Process locked */ | |
538 __HAL_LOCK(hdma2d); | |
539 | |
540 /* Change DMA2D peripheral state */ | |
541 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
542 | |
543 /* Configure DMA2D Stream source2 address */ | |
544 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); | |
545 | |
546 /* Configure the source, destination address and the data size */ | |
547 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); | |
548 | |
549 /* Enable the transfer complete, transfer error and configuration error interrupts */ | |
550 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); | |
551 | |
552 /* Enable the Peripheral */ | |
553 __HAL_DMA2D_ENABLE(hdma2d); | |
554 | |
555 return HAL_OK; | |
556 } | |
557 | |
558 /** | |
559 * @brief Abort the DMA2D Transfer. | |
560 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
561 * the configuration information for the DMA2D. | |
562 * @retval HAL status | |
563 */ | |
564 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) | |
565 { | |
566 uint32_t tickstart = 0U; | |
567 | |
568 /* Abort the DMA2D transfer */ | |
569 /* START bit is reset to make sure not to set it again, in the event the HW clears it | |
570 between the register read and the register write by the CPU (writing 0 has no | |
571 effect on START bitvalue) */ | |
572 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); | |
573 | |
574 /* Get tick */ | |
575 tickstart = HAL_GetTick(); | |
576 | |
577 /* Check if the DMA2D is effectively disabled */ | |
578 while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) | |
579 { | |
580 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) | |
581 { | |
582 /* Update error code */ | |
583 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; | |
584 | |
585 /* Change the DMA2D state */ | |
586 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; | |
587 | |
588 /* Process Unlocked */ | |
589 __HAL_UNLOCK(hdma2d); | |
590 | |
591 return HAL_TIMEOUT; | |
592 } | |
593 } | |
594 | |
595 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ | |
596 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); | |
597 | |
598 /* Change the DMA2D state*/ | |
599 hdma2d->State = HAL_DMA2D_STATE_READY; | |
600 | |
601 /* Process Unlocked */ | |
602 __HAL_UNLOCK(hdma2d); | |
603 | |
604 return HAL_OK; | |
605 } | |
606 | |
607 /** | |
608 * @brief Suspend the DMA2D Transfer. | |
609 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
610 * the configuration information for the DMA2D. | |
611 * @retval HAL status | |
612 */ | |
613 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) | |
614 { | |
615 uint32_t tickstart = 0U; | |
616 | |
617 /* Suspend the DMA2D transfer */ | |
618 /* START bit is reset to make sure not to set it again, in the event the HW clears it | |
619 between the register read and the register write by the CPU (writing 0 has no | |
620 effect on START bitvalue) */ | |
621 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); | |
622 | |
623 /* Get tick */ | |
624 tickstart = HAL_GetTick(); | |
625 | |
626 /* Check if the DMA2D is effectively suspended */ | |
627 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ | |
628 && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)) | |
629 { | |
630 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) | |
631 { | |
632 /* Update error code */ | |
633 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; | |
634 | |
635 /* Change the DMA2D state */ | |
636 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; | |
637 | |
638 return HAL_TIMEOUT; | |
639 } | |
640 } | |
641 | |
642 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ | |
643 if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) | |
644 { | |
645 hdma2d->State = HAL_DMA2D_STATE_SUSPEND; | |
646 } | |
647 else | |
648 { | |
649 /* Make sure SUSP bit is cleared since it is meaningless | |
650 when no tranfer is on-going */ | |
651 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); | |
652 } | |
653 | |
654 return HAL_OK; | |
655 } | |
656 | |
657 /** | |
658 * @brief Resume the DMA2D Transfer. | |
659 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
660 * the configuration information for the DMA2D. | |
661 * @retval HAL status | |
662 */ | |
663 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) | |
664 { | |
665 /* Check the SUSP and START bits */ | |
666 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) | |
667 { | |
668 /* Ongoing transfer is suspended: change the DMA2D state before resuming */ | |
669 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
670 } | |
671 | |
672 /* Resume the DMA2D transfer */ | |
673 /* START bit is reset to make sure not to set it again, in the event the HW clears it | |
674 between the register read and the register write by the CPU (writing 0 has no | |
675 effect on START bitvalue) */ | |
676 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); | |
677 | |
678 return HAL_OK; | |
679 } | |
680 | |
681 /** | |
682 * @brief Enable the DMA2D CLUT Transfer. | |
683 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
684 * the configuration information for the DMA2D. | |
685 * @param LayerIdx DMA2D Layer index. | |
686 * This parameter can be one of the following values: | |
687 * 0(background) / 1(foreground) | |
688 * @retval HAL status | |
689 */ | |
690 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) | |
691 { | |
692 /* Check the parameters */ | |
693 assert_param(IS_DMA2D_LAYER(LayerIdx)); | |
694 | |
695 /* Process locked */ | |
696 __HAL_LOCK(hdma2d); | |
697 | |
698 /* Change DMA2D peripheral state */ | |
699 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
700 | |
701 if(LayerIdx == 0U) | |
702 { | |
703 /* Enable the background CLUT loading */ | |
704 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); | |
705 } | |
706 else | |
707 { | |
708 /* Enable the foreground CLUT loading */ | |
709 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); | |
710 } | |
711 | |
712 return HAL_OK; | |
713 } | |
714 | |
715 /** | |
716 * @brief Start DMA2D CLUT Loading. | |
717 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
718 * the configuration information for the DMA2D. | |
719 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains | |
720 * the configuration information for the color look up table. | |
721 * @param LayerIdx DMA2D Layer index. | |
722 * This parameter can be one of the following values: | |
723 * 0(background) / 1(foreground) | |
724 * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). | |
725 * @retval HAL status | |
726 */ | |
727 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) | |
728 { | |
729 /* Check the parameters */ | |
730 assert_param(IS_DMA2D_LAYER(LayerIdx)); | |
731 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); | |
732 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); | |
733 | |
734 /* Process locked */ | |
735 __HAL_LOCK(hdma2d); | |
736 | |
737 /* Change DMA2D peripheral state */ | |
738 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
739 | |
740 /* Configure the CLUT of the background DMA2D layer */ | |
741 if(LayerIdx == 0U) | |
742 { | |
743 /* Write background CLUT memory address */ | |
744 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); | |
745 | |
746 /* Write background CLUT size and CLUT color mode */ | |
747 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), | |
748 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); | |
749 | |
750 /* Enable the CLUT loading for the background */ | |
751 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); | |
752 } | |
753 /* Configure the CLUT of the foreground DMA2D layer */ | |
754 else | |
755 { | |
756 /* Write foreground CLUT memory address */ | |
757 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); | |
758 | |
759 /* Write foreground CLUT size and CLUT color mode */ | |
760 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), | |
761 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); | |
762 | |
763 /* Enable the CLUT loading for the foreground */ | |
764 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); | |
765 } | |
766 | |
767 return HAL_OK; | |
768 } | |
769 | |
770 /** | |
771 * @brief Start DMA2D CLUT Loading with interrupt enabled. | |
772 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
773 * the configuration information for the DMA2D. | |
774 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains | |
775 * the configuration information for the color look up table. | |
776 * @param LayerIdx DMA2D Layer index. | |
777 * This parameter can be one of the following values: | |
778 * 0(background) / 1(foreground) | |
779 * @retval HAL status | |
780 */ | |
781 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) | |
782 { | |
783 /* Check the parameters */ | |
784 assert_param(IS_DMA2D_LAYER(LayerIdx)); | |
785 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); | |
786 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); | |
787 | |
788 /* Process locked */ | |
789 __HAL_LOCK(hdma2d); | |
790 | |
791 /* Change DMA2D peripheral state */ | |
792 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
793 | |
794 /* Configure the CLUT of the background DMA2D layer */ | |
795 if(LayerIdx == 0U) | |
796 { | |
797 /* Write background CLUT memory address */ | |
798 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); | |
799 | |
800 /* Write background CLUT size and CLUT color mode */ | |
801 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), | |
802 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); | |
803 | |
804 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ | |
805 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); | |
806 | |
807 /* Enable the CLUT loading for the background */ | |
808 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); | |
809 } | |
810 /* Configure the CLUT of the foreground DMA2D layer */ | |
811 else | |
812 { | |
813 /* Write foreground CLUT memory address */ | |
814 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); | |
815 | |
816 /* Write foreground CLUT size and CLUT color mode */ | |
817 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), | |
818 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); | |
819 | |
820 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ | |
821 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); | |
822 | |
823 /* Enable the CLUT loading for the foreground */ | |
824 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); | |
825 } | |
826 | |
827 return HAL_OK; | |
828 } | |
829 | |
830 /** | |
831 * @brief Abort the DMA2D CLUT loading. | |
832 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
833 * the configuration information for the DMA2D. | |
834 * @param LayerIdx DMA2D Layer index. | |
835 * This parameter can be one of the following values: | |
836 * 0(background) / 1(foreground) | |
837 * @retval HAL status | |
838 */ | |
839 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) | |
840 { | |
841 uint32_t tickstart = 0U; | |
842 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ | |
843 | |
844 /* Abort the CLUT loading */ | |
845 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); | |
846 | |
847 /* If foreground CLUT loading is considered, update local variables */ | |
848 if(LayerIdx == 1) | |
849 { | |
850 reg = &(hdma2d->Instance->FGPFCCR); | |
851 } | |
852 | |
853 /* Get tick */ | |
854 tickstart = HAL_GetTick(); | |
855 | |
856 /* Check if the CLUT loading is aborted */ | |
857 while((*reg & DMA2D_BGPFCCR_START) != RESET) | |
858 { | |
859 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) | |
860 { | |
861 /* Update error code */ | |
862 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; | |
863 | |
864 /* Change the DMA2D state */ | |
865 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; | |
866 | |
867 /* Process Unlocked */ | |
868 __HAL_UNLOCK(hdma2d); | |
869 | |
870 return HAL_TIMEOUT; | |
871 } | |
872 } | |
873 | |
874 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ | |
875 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); | |
876 | |
877 /* Change the DMA2D state*/ | |
878 hdma2d->State = HAL_DMA2D_STATE_READY; | |
879 | |
880 /* Process Unlocked */ | |
881 __HAL_UNLOCK(hdma2d); | |
882 | |
883 return HAL_OK; | |
884 } | |
885 | |
886 /** | |
887 * @brief Suspend the DMA2D CLUT loading. | |
888 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
889 * the configuration information for the DMA2D. | |
890 * @param LayerIdx DMA2D Layer index. | |
891 * This parameter can be one of the following values: | |
892 * 0(background) / 1(foreground) | |
893 * @retval HAL status | |
894 */ | |
895 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) | |
896 { | |
897 uint32_t tickstart = 0U; | |
898 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ | |
899 | |
900 /* Suspend the CLUT loading */ | |
901 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); | |
902 | |
903 /* If foreground CLUT loading is considered, update local variables */ | |
904 if(LayerIdx == 1U) | |
905 { | |
906 reg = &(hdma2d->Instance->FGPFCCR); | |
907 } | |
908 | |
909 /* Get tick */ | |
910 tickstart = HAL_GetTick(); | |
911 | |
912 /* Check if the CLUT loading is suspended */ | |
913 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ | |
914 && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)) | |
915 { | |
916 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) | |
917 { | |
918 /* Update error code */ | |
919 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; | |
920 | |
921 /* Change the DMA2D state */ | |
922 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; | |
923 | |
924 return HAL_TIMEOUT; | |
925 } | |
926 } | |
927 | |
928 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ | |
929 if ((*reg & DMA2D_BGPFCCR_START) != RESET) | |
930 { | |
931 hdma2d->State = HAL_DMA2D_STATE_SUSPEND; | |
932 } | |
933 else | |
934 { | |
935 /* Make sure SUSP bit is cleared since it is meaningless | |
936 when no tranfer is on-going */ | |
937 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); | |
938 } | |
939 | |
940 return HAL_OK; | |
941 } | |
942 | |
943 /** | |
944 * @brief Resume the DMA2D CLUT loading. | |
945 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
946 * the configuration information for the DMA2D. | |
947 * @param LayerIdx DMA2D Layer index. | |
948 * This parameter can be one of the following values: | |
949 * 0(background) / 1(foreground) | |
950 * @retval HAL status | |
951 */ | |
952 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) | |
953 { | |
954 /* Check the SUSP and START bits for background or foreground CLUT loading */ | |
955 if(LayerIdx == 0U) | |
956 { | |
957 /* Background CLUT loading suspension check */ | |
958 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) | |
959 && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)) | |
960 { | |
961 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ | |
962 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
963 } | |
964 } | |
965 else | |
966 { | |
967 /* Foreground CLUT loading suspension check */ | |
968 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) | |
969 && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)) | |
970 { | |
971 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ | |
972 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
973 } | |
974 } | |
975 | |
976 /* Resume the CLUT loading */ | |
977 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); | |
978 | |
979 return HAL_OK; | |
980 } | |
981 | |
982 /** | |
983 * @brief Polling for transfer complete or CLUT loading. | |
984 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
985 * the configuration information for the DMA2D. | |
986 * @param Timeout Timeout duration | |
987 * @retval HAL status | |
988 */ | |
989 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) | |
990 { | |
991 uint32_t tickstart = 0U; | |
992 __IO uint32_t isrflags = 0x0U; | |
993 | |
994 /* Polling for DMA2D transfer */ | |
995 if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) | |
996 { | |
997 /* Get tick */ | |
998 tickstart = HAL_GetTick(); | |
999 | |
1000 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) | |
1001 { | |
1002 isrflags = READ_REG(hdma2d->Instance->ISR); | |
1003 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) | |
1004 { | |
1005 if ((isrflags & DMA2D_FLAG_CE) != RESET) | |
1006 { | |
1007 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; | |
1008 } | |
1009 if ((isrflags & DMA2D_FLAG_TE) != RESET) | |
1010 { | |
1011 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; | |
1012 } | |
1013 /* Clear the transfer and configuration error flags */ | |
1014 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); | |
1015 | |
1016 /* Change DMA2D state */ | |
1017 hdma2d->State = HAL_DMA2D_STATE_ERROR; | |
1018 | |
1019 /* Process unlocked */ | |
1020 __HAL_UNLOCK(hdma2d); | |
1021 | |
1022 return HAL_ERROR; | |
1023 } | |
1024 /* Check for the Timeout */ | |
1025 if(Timeout != HAL_MAX_DELAY) | |
1026 { | |
1027 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) | |
1028 { | |
1029 /* Update error code */ | |
1030 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; | |
1031 | |
1032 /* Change the DMA2D state */ | |
1033 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; | |
1034 | |
1035 /* Process unlocked */ | |
1036 __HAL_UNLOCK(hdma2d); | |
1037 | |
1038 return HAL_TIMEOUT; | |
1039 } | |
1040 } | |
1041 } | |
1042 } | |
1043 /* Polling for CLUT loading (foreground or background) */ | |
1044 if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) || | |
1045 ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET)) | |
1046 { | |
1047 /* Get tick */ | |
1048 tickstart = HAL_GetTick(); | |
1049 | |
1050 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) | |
1051 { | |
1052 isrflags = READ_REG(hdma2d->Instance->ISR); | |
1053 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) | |
1054 { | |
1055 if ((isrflags & DMA2D_FLAG_CAE) != RESET) | |
1056 { | |
1057 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; | |
1058 } | |
1059 if ((isrflags & DMA2D_FLAG_CE) != RESET) | |
1060 { | |
1061 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; | |
1062 } | |
1063 if ((isrflags & DMA2D_FLAG_TE) != RESET) | |
1064 { | |
1065 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; | |
1066 } | |
1067 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ | |
1068 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); | |
1069 | |
1070 /* Change DMA2D state */ | |
1071 hdma2d->State= HAL_DMA2D_STATE_ERROR; | |
1072 | |
1073 /* Process unlocked */ | |
1074 __HAL_UNLOCK(hdma2d); | |
1075 | |
1076 return HAL_ERROR; | |
1077 } | |
1078 /* Check for the Timeout */ | |
1079 if(Timeout != HAL_MAX_DELAY) | |
1080 { | |
1081 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) | |
1082 { | |
1083 /* Update error code */ | |
1084 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; | |
1085 | |
1086 /* Change the DMA2D state */ | |
1087 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; | |
1088 | |
1089 /* Process unlocked */ | |
1090 __HAL_UNLOCK(hdma2d); | |
1091 | |
1092 return HAL_TIMEOUT; | |
1093 } | |
1094 } | |
1095 } | |
1096 } | |
1097 | |
1098 /* Clear the transfer complete and CLUT loading flags */ | |
1099 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); | |
1100 | |
1101 /* Change DMA2D state */ | |
1102 hdma2d->State = HAL_DMA2D_STATE_READY; | |
1103 | |
1104 /* Process unlocked */ | |
1105 __HAL_UNLOCK(hdma2d); | |
1106 | |
1107 return HAL_OK; | |
1108 } | |
1109 /** | |
1110 * @brief Handle DMA2D interrupt request. | |
1111 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
1112 * the configuration information for the DMA2D. | |
1113 * @retval HAL status | |
1114 */ | |
1115 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) | |
1116 { | |
1117 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); | |
1118 uint32_t crflags = READ_REG(hdma2d->Instance->CR); | |
1119 | |
1120 /* Transfer Error Interrupt management ***************************************/ | |
1121 if ((isrflags & DMA2D_FLAG_TE) != RESET) | |
1122 { | |
1123 if ((crflags & DMA2D_IT_TE) != RESET) | |
1124 { | |
1125 /* Disable the transfer Error interrupt */ | |
1126 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); | |
1127 | |
1128 /* Update error code */ | |
1129 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; | |
1130 | |
1131 /* Clear the transfer error flag */ | |
1132 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); | |
1133 | |
1134 /* Change DMA2D state */ | |
1135 hdma2d->State = HAL_DMA2D_STATE_ERROR; | |
1136 | |
1137 /* Process Unlocked */ | |
1138 __HAL_UNLOCK(hdma2d); | |
1139 | |
1140 if(hdma2d->XferErrorCallback != NULL) | |
1141 { | |
1142 /* Transfer error Callback */ | |
1143 hdma2d->XferErrorCallback(hdma2d); | |
1144 } | |
1145 } | |
1146 } | |
1147 /* Configuration Error Interrupt management **********************************/ | |
1148 if ((isrflags & DMA2D_FLAG_CE) != RESET) | |
1149 { | |
1150 if ((crflags & DMA2D_IT_CE) != RESET) | |
1151 { | |
1152 /* Disable the Configuration Error interrupt */ | |
1153 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); | |
1154 | |
1155 /* Clear the Configuration error flag */ | |
1156 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); | |
1157 | |
1158 /* Update error code */ | |
1159 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; | |
1160 | |
1161 /* Change DMA2D state */ | |
1162 hdma2d->State = HAL_DMA2D_STATE_ERROR; | |
1163 | |
1164 /* Process Unlocked */ | |
1165 __HAL_UNLOCK(hdma2d); | |
1166 | |
1167 if(hdma2d->XferErrorCallback != NULL) | |
1168 { | |
1169 /* Transfer error Callback */ | |
1170 hdma2d->XferErrorCallback(hdma2d); | |
1171 } | |
1172 } | |
1173 } | |
1174 /* CLUT access Error Interrupt management ***********************************/ | |
1175 if ((isrflags & DMA2D_FLAG_CAE) != RESET) | |
1176 { | |
1177 if ((crflags & DMA2D_IT_CAE) != RESET) | |
1178 { | |
1179 /* Disable the CLUT access error interrupt */ | |
1180 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); | |
1181 | |
1182 /* Clear the CLUT access error flag */ | |
1183 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); | |
1184 | |
1185 /* Update error code */ | |
1186 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; | |
1187 | |
1188 /* Change DMA2D state */ | |
1189 hdma2d->State = HAL_DMA2D_STATE_ERROR; | |
1190 | |
1191 /* Process Unlocked */ | |
1192 __HAL_UNLOCK(hdma2d); | |
1193 | |
1194 if(hdma2d->XferErrorCallback != NULL) | |
1195 { | |
1196 /* Transfer error Callback */ | |
1197 hdma2d->XferErrorCallback(hdma2d); | |
1198 } | |
1199 } | |
1200 } | |
1201 /* Transfer watermark Interrupt management **********************************/ | |
1202 if ((isrflags & DMA2D_FLAG_TW) != RESET) | |
1203 { | |
1204 if ((crflags & DMA2D_IT_TW) != RESET) | |
1205 { | |
1206 /* Disable the transfer watermark interrupt */ | |
1207 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); | |
1208 | |
1209 /* Clear the transfer watermark flag */ | |
1210 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); | |
1211 | |
1212 /* Transfer watermark Callback */ | |
1213 HAL_DMA2D_LineEventCallback(hdma2d); | |
1214 } | |
1215 } | |
1216 /* Transfer Complete Interrupt management ************************************/ | |
1217 if ((isrflags & DMA2D_FLAG_TC) != RESET) | |
1218 { | |
1219 if ((crflags & DMA2D_IT_TC) != RESET) | |
1220 { | |
1221 /* Disable the transfer complete interrupt */ | |
1222 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); | |
1223 | |
1224 /* Clear the transfer complete flag */ | |
1225 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); | |
1226 | |
1227 /* Update error code */ | |
1228 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; | |
1229 | |
1230 /* Change DMA2D state */ | |
1231 hdma2d->State = HAL_DMA2D_STATE_READY; | |
1232 | |
1233 /* Process Unlocked */ | |
1234 __HAL_UNLOCK(hdma2d); | |
1235 | |
1236 if(hdma2d->XferCpltCallback != NULL) | |
1237 { | |
1238 /* Transfer complete Callback */ | |
1239 hdma2d->XferCpltCallback(hdma2d); | |
1240 } | |
1241 } | |
1242 } | |
1243 /* CLUT Transfer Complete Interrupt management ******************************/ | |
1244 if ((isrflags & DMA2D_FLAG_CTC) != RESET) | |
1245 { | |
1246 if ((crflags & DMA2D_IT_CTC) != RESET) | |
1247 { | |
1248 /* Disable the CLUT transfer complete interrupt */ | |
1249 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); | |
1250 | |
1251 /* Clear the CLUT transfer complete flag */ | |
1252 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); | |
1253 | |
1254 /* Update error code */ | |
1255 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; | |
1256 | |
1257 /* Change DMA2D state */ | |
1258 hdma2d->State = HAL_DMA2D_STATE_READY; | |
1259 | |
1260 /* Process Unlocked */ | |
1261 __HAL_UNLOCK(hdma2d); | |
1262 | |
1263 /* CLUT Transfer complete Callback */ | |
1264 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); | |
1265 } | |
1266 } | |
1267 } | |
1268 | |
1269 /** | |
1270 * @brief Transfer watermark callback. | |
1271 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
1272 * the configuration information for the DMA2D. | |
1273 * @retval None | |
1274 */ | |
1275 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) | |
1276 { | |
1277 /* Prevent unused argument(s) compilation warning */ | |
1278 UNUSED(hdma2d); | |
1279 | |
1280 /* NOTE : This function should not be modified; when the callback is needed, | |
1281 the HAL_DMA2D_LineEventCallback can be implemented in the user file. | |
1282 */ | |
1283 } | |
1284 | |
1285 /** | |
1286 * @brief CLUT Transfer Complete callback. | |
1287 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
1288 * the configuration information for the DMA2D. | |
1289 * @retval None | |
1290 */ | |
1291 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) | |
1292 { | |
1293 /* Prevent unused argument(s) compilation warning */ | |
1294 UNUSED(hdma2d); | |
1295 | |
1296 /* NOTE : This function should not be modified; when the callback is needed, | |
1297 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. | |
1298 */ | |
1299 } | |
1300 | |
1301 /** | |
1302 * @} | |
1303 */ | |
1304 | |
1305 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions | |
1306 * @brief Peripheral Control functions | |
1307 * | |
1308 @verbatim | |
1309 =============================================================================== | |
1310 ##### Peripheral Control functions ##### | |
1311 =============================================================================== | |
1312 [..] This section provides functions allowing to: | |
1313 (+) Configure the DMA2D foreground or background layer parameters. | |
1314 (+) Configure the DMA2D CLUT transfer. | |
1315 (+) Configure the line watermark | |
1316 (+) Configure the dead time value. | |
1317 (+) Enable or disable the dead time value functionality. | |
1318 | |
1319 @endverbatim | |
1320 * @{ | |
1321 */ | |
1322 | |
1323 /** | |
1324 * @brief Configure the DMA2D Layer according to the specified | |
1325 * parameters in the DMA2D_InitTypeDef and create the associated handle. | |
1326 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
1327 * the configuration information for the DMA2D. | |
1328 * @param LayerIdx DMA2D Layer index. | |
1329 * This parameter can be one of the following values: | |
1330 * 0(background) / 1(foreground) | |
1331 * @retval HAL status | |
1332 */ | |
1333 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) | |
1334 { | |
1335 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; | |
1336 uint32_t regValue = 0U; | |
1337 | |
1338 /* Check the parameters */ | |
1339 assert_param(IS_DMA2D_LAYER(LayerIdx)); | |
1340 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset)); | |
1341 if(hdma2d->Init.Mode != DMA2D_R2M) | |
1342 { | |
1343 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode)); | |
1344 if(hdma2d->Init.Mode != DMA2D_M2M) | |
1345 { | |
1346 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode)); | |
1347 } | |
1348 } | |
1349 | |
1350 /* Process locked */ | |
1351 __HAL_LOCK(hdma2d); | |
1352 | |
1353 /* Change DMA2D peripheral state */ | |
1354 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
1355 | |
1356 /* DMA2D BGPFCR register configuration -----------------------------------*/ | |
1357 /* Prepare the value to be written to the BGPFCCR register */ | |
1358 | |
1359 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) | |
1360 { | |
1361 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); | |
1362 } | |
1363 else | |
1364 { | |
1365 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA); | |
1366 } | |
1367 | |
1368 /* Configure the background DMA2D layer */ | |
1369 if(LayerIdx == 0) | |
1370 { | |
1371 /* Write DMA2D BGPFCCR register */ | |
1372 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue); | |
1373 | |
1374 /* DMA2D BGOR register configuration -------------------------------------*/ | |
1375 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); | |
1376 | |
1377 /* DMA2D BGCOLR register configuration -------------------------------------*/ | |
1378 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) | |
1379 { | |
1380 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); | |
1381 } | |
1382 } | |
1383 /* Configure the foreground DMA2D layer */ | |
1384 else | |
1385 { | |
1386 /* Write DMA2D FGPFCCR register */ | |
1387 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue); | |
1388 | |
1389 /* DMA2D FGOR register configuration -------------------------------------*/ | |
1390 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); | |
1391 | |
1392 /* DMA2D FGCOLR register configuration -------------------------------------*/ | |
1393 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) | |
1394 { | |
1395 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); | |
1396 } | |
1397 } | |
1398 /* Initialize the DMA2D state*/ | |
1399 hdma2d->State = HAL_DMA2D_STATE_READY; | |
1400 | |
1401 /* Process unlocked */ | |
1402 __HAL_UNLOCK(hdma2d); | |
1403 | |
1404 return HAL_OK; | |
1405 } | |
1406 | |
1407 /** | |
1408 * @brief Configure the DMA2D CLUT Transfer. | |
1409 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
1410 * the configuration information for the DMA2D. | |
1411 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains | |
1412 * the configuration information for the color look up table. | |
1413 * @param LayerIdx DMA2D Layer index. | |
1414 * This parameter can be one of the following values: | |
1415 * 0(background) / 1(foreground) | |
1416 * @retval HAL status | |
1417 */ | |
1418 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) | |
1419 { | |
1420 /* Check the parameters */ | |
1421 assert_param(IS_DMA2D_LAYER(LayerIdx)); | |
1422 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); | |
1423 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); | |
1424 | |
1425 /* Process locked */ | |
1426 __HAL_LOCK(hdma2d); | |
1427 | |
1428 /* Change DMA2D peripheral state */ | |
1429 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
1430 | |
1431 /* Configure the CLUT of the background DMA2D layer */ | |
1432 if(LayerIdx == 0U) | |
1433 { | |
1434 /* Write background CLUT memory address */ | |
1435 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); | |
1436 | |
1437 /* Write background CLUT size and CLUT color mode */ | |
1438 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), | |
1439 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); | |
1440 } | |
1441 /* Configure the CLUT of the foreground DMA2D layer */ | |
1442 else | |
1443 { | |
1444 /* Write foreground CLUT memory address */ | |
1445 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); | |
1446 | |
1447 /* Write foreground CLUT size and CLUT color mode */ | |
1448 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), | |
1449 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); | |
1450 } | |
1451 | |
1452 /* Set the DMA2D state to Ready */ | |
1453 hdma2d->State = HAL_DMA2D_STATE_READY; | |
1454 | |
1455 /* Process unlocked */ | |
1456 __HAL_UNLOCK(hdma2d); | |
1457 | |
1458 return HAL_OK; | |
1459 } | |
1460 | |
1461 /** | |
1462 * @brief Configure the line watermark. | |
1463 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
1464 * the configuration information for the DMA2D. | |
1465 * @param Line Line Watermark configuration (maximum 16-bit long value expected). | |
1466 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. | |
1467 * @note The transfer watermark interrupt is disabled once it has occurred. | |
1468 * @retval HAL status | |
1469 */ | |
1470 | |
1471 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) | |
1472 { | |
1473 /* Check the parameters */ | |
1474 assert_param(IS_DMA2D_LINEWATERMARK(Line)); | |
1475 | |
1476 if (Line > DMA2D_LWR_LW) | |
1477 { | |
1478 return HAL_ERROR; | |
1479 } | |
1480 else | |
1481 { | |
1482 /* Process locked */ | |
1483 __HAL_LOCK(hdma2d); | |
1484 | |
1485 /* Change DMA2D peripheral state */ | |
1486 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
1487 | |
1488 /* Sets the Line watermark configuration */ | |
1489 WRITE_REG(hdma2d->Instance->LWR, Line); | |
1490 | |
1491 /* Enable the Line interrupt */ | |
1492 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); | |
1493 | |
1494 /* Initialize the DMA2D state */ | |
1495 hdma2d->State = HAL_DMA2D_STATE_READY; | |
1496 | |
1497 /* Process unlocked */ | |
1498 __HAL_UNLOCK(hdma2d); | |
1499 | |
1500 return HAL_OK; | |
1501 } | |
1502 } | |
1503 | |
1504 /** | |
1505 * @brief Enable DMA2D dead time feature. | |
1506 * @param hdma2d DMA2D handle. | |
1507 * @retval HAL status | |
1508 */ | |
1509 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) | |
1510 { | |
1511 /* Process Locked */ | |
1512 __HAL_LOCK(hdma2d); | |
1513 | |
1514 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
1515 | |
1516 /* Set DMA2D_AMTCR EN bit */ | |
1517 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); | |
1518 | |
1519 hdma2d->State = HAL_DMA2D_STATE_READY; | |
1520 | |
1521 /* Process Unlocked */ | |
1522 __HAL_UNLOCK(hdma2d); | |
1523 | |
1524 return HAL_OK; | |
1525 } | |
1526 | |
1527 /** | |
1528 * @brief Disable DMA2D dead time feature. | |
1529 * @param hdma2d DMA2D handle. | |
1530 * @retval HAL status | |
1531 */ | |
1532 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) | |
1533 { | |
1534 /* Process Locked */ | |
1535 __HAL_LOCK(hdma2d); | |
1536 | |
1537 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
1538 | |
1539 /* Clear DMA2D_AMTCR EN bit */ | |
1540 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); | |
1541 | |
1542 hdma2d->State = HAL_DMA2D_STATE_READY; | |
1543 | |
1544 /* Process Unlocked */ | |
1545 __HAL_UNLOCK(hdma2d); | |
1546 | |
1547 return HAL_OK; | |
1548 } | |
1549 | |
1550 /** | |
1551 * @brief Configure dead time. | |
1552 * @note The dead time value represents the guaranteed minimum number of cycles between | |
1553 * two consecutive transactions on the AHB bus. | |
1554 * @param hdma2d DMA2D handle. | |
1555 * @param DeadTime dead time value. | |
1556 * @retval HAL status | |
1557 */ | |
1558 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) | |
1559 { | |
1560 /* Process Locked */ | |
1561 __HAL_LOCK(hdma2d); | |
1562 | |
1563 hdma2d->State = HAL_DMA2D_STATE_BUSY; | |
1564 | |
1565 /* Set DMA2D_AMTCR DT field */ | |
1566 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT)); | |
1567 | |
1568 hdma2d->State = HAL_DMA2D_STATE_READY; | |
1569 | |
1570 /* Process Unlocked */ | |
1571 __HAL_UNLOCK(hdma2d); | |
1572 | |
1573 return HAL_OK; | |
1574 } | |
1575 | |
1576 /** | |
1577 * @} | |
1578 */ | |
1579 | |
1580 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions | |
1581 * @brief Peripheral State functions | |
1582 * | |
1583 @verbatim | |
1584 =============================================================================== | |
1585 ##### Peripheral State and Errors functions ##### | |
1586 =============================================================================== | |
1587 [..] | |
1588 This subsection provides functions allowing to : | |
1589 (+) Get the DMA2D state | |
1590 (+) Get the DMA2D error code | |
1591 | |
1592 @endverbatim | |
1593 * @{ | |
1594 */ | |
1595 | |
1596 /** | |
1597 * @brief Return the DMA2D state | |
1598 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
1599 * the configuration information for the DMA2D. | |
1600 * @retval HAL state | |
1601 */ | |
1602 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) | |
1603 { | |
1604 return hdma2d->State; | |
1605 } | |
1606 | |
1607 /** | |
1608 * @brief Return the DMA2D error code | |
1609 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains | |
1610 * the configuration information for DMA2D. | |
1611 * @retval DMA2D Error Code | |
1612 */ | |
1613 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) | |
1614 { | |
1615 return hdma2d->ErrorCode; | |
1616 } | |
1617 | |
1618 /** | |
1619 * @} | |
1620 */ | |
1621 | |
1622 /** | |
1623 * @} | |
1624 */ | |
1625 | |
1626 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions | |
1627 * @{ | |
1628 */ | |
1629 | |
1630 /** | |
1631 * @brief Set the DMA2D transfer parameters. | |
1632 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains | |
1633 * the configuration information for the specified DMA2D. | |
1634 * @param pdata The source memory Buffer address | |
1635 * @param DstAddress The destination memory Buffer address | |
1636 * @param Width The width of data to be transferred from source to destination. | |
1637 * @param Height The height of data to be transferred from source to destination. | |
1638 * @retval HAL status | |
1639 */ | |
1640 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) | |
1641 { | |
1642 uint32_t tmp = 0U; | |
1643 uint32_t tmp1 = 0U; | |
1644 uint32_t tmp2 = 0U; | |
1645 uint32_t tmp3 = 0U; | |
1646 uint32_t tmp4 = 0U; | |
1647 | |
1648 /* Configure DMA2D data size */ | |
1649 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL))); | |
1650 | |
1651 /* Configure DMA2D destination address */ | |
1652 WRITE_REG(hdma2d->Instance->OMAR, DstAddress); | |
1653 | |
1654 /* Register to memory DMA2D mode selected */ | |
1655 if (hdma2d->Init.Mode == DMA2D_R2M) | |
1656 { | |
1657 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; | |
1658 tmp2 = pdata & DMA2D_OCOLR_RED_1; | |
1659 tmp3 = pdata & DMA2D_OCOLR_GREEN_1; | |
1660 tmp4 = pdata & DMA2D_OCOLR_BLUE_1; | |
1661 | |
1662 /* Prepare the value to be written to the OCOLR register according to the color mode */ | |
1663 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) | |
1664 { | |
1665 tmp = (tmp3 | tmp2 | tmp1| tmp4); | |
1666 } | |
1667 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) | |
1668 { | |
1669 tmp = (tmp3 | tmp2 | tmp4); | |
1670 } | |
1671 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) | |
1672 { | |
1673 tmp2 = (tmp2 >> 19U); | |
1674 tmp3 = (tmp3 >> 10U); | |
1675 tmp4 = (tmp4 >> 3U); | |
1676 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); | |
1677 } | |
1678 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) | |
1679 { | |
1680 tmp1 = (tmp1 >> 31U); | |
1681 tmp2 = (tmp2 >> 19U); | |
1682 tmp3 = (tmp3 >> 11U); | |
1683 tmp4 = (tmp4 >> 3U); | |
1684 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); | |
1685 } | |
1686 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ | |
1687 { | |
1688 tmp1 = (tmp1 >> 28U); | |
1689 tmp2 = (tmp2 >> 20U); | |
1690 tmp3 = (tmp3 >> 12U); | |
1691 tmp4 = (tmp4 >> 4U); | |
1692 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); | |
1693 } | |
1694 /* Write to DMA2D OCOLR register */ | |
1695 WRITE_REG(hdma2d->Instance->OCOLR, tmp); | |
1696 } | |
1697 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ | |
1698 { | |
1699 /* Configure DMA2D source address */ | |
1700 WRITE_REG(hdma2d->Instance->FGMAR, pdata); | |
1701 } | |
1702 } | |
1703 | |
1704 /** | |
1705 * @} | |
1706 */ | |
1707 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ | |
1708 #endif /* HAL_DMA2D_MODULE_ENABLED */ | |
1709 /** | |
1710 * @} | |
1711 */ | |
1712 | |
1713 /** | |
1714 * @} | |
1715 */ | |
1716 | |
1717 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |