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comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_adc_ex.c | |
4 * @author MCD Application Team | |
5 * @brief This file provides firmware functions to manage the following | |
6 * functionalities of the ADC extension peripheral: | |
7 * + Extended features functions | |
8 * | |
9 @verbatim | |
10 ============================================================================== | |
11 ##### How to use this driver ##### | |
12 ============================================================================== | |
13 [..] | |
14 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): | |
15 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() | |
16 (##) ADC pins configuration | |
17 (+++) Enable the clock for the ADC GPIOs using the following function: | |
18 __HAL_RCC_GPIOx_CLK_ENABLE() | |
19 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() | |
20 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) | |
21 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() | |
22 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() | |
23 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() | |
24 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) | |
25 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() | |
26 (+++) Configure and enable two DMA streams stream for managing data | |
27 transfer from peripheral to memory (output stream) | |
28 (+++) Associate the initialized DMA handle to the ADC DMA handle | |
29 using __HAL_LINKDMA() | |
30 (+++) Configure the priority and enable the NVIC for the transfer complete | |
31 interrupt on the two DMA Streams. The output stream should have higher | |
32 priority than the input stream. | |
33 (#) Configure the ADC Prescaler, conversion resolution and data alignment | |
34 using the HAL_ADC_Init() function. | |
35 | |
36 (#) Configure the ADC Injected channels group features, use HAL_ADC_Init() | |
37 and HAL_ADC_ConfigChannel() functions. | |
38 | |
39 (#) Three operation modes are available within this driver : | |
40 | |
41 *** Polling mode IO operation *** | |
42 ================================= | |
43 [..] | |
44 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() | |
45 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage | |
46 user can specify the value of timeout according to his end application | |
47 (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function. | |
48 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop() | |
49 | |
50 *** Interrupt mode IO operation *** | |
51 =================================== | |
52 [..] | |
53 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() | |
54 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine | |
55 (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can | |
56 add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback | |
57 (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can | |
58 add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback | |
59 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() | |
60 | |
61 | |
62 *** DMA mode IO operation *** | |
63 ============================== | |
64 [..] | |
65 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length | |
66 of data to be transferred at each end of conversion | |
67 (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can | |
68 add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback | |
69 (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can | |
70 add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback | |
71 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA() | |
72 | |
73 *** Multi mode ADCs Regular channels configuration *** | |
74 ====================================================== | |
75 [..] | |
76 (+) Select the Multi mode ADC regular channels features (dual or triple mode) | |
77 and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. | |
78 (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length | |
79 of data to be transferred at each end of conversion | |
80 (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function. | |
81 | |
82 | |
83 @endverbatim | |
84 ****************************************************************************** | |
85 * @attention | |
86 * | |
87 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
88 * | |
89 * Redistribution and use in source and binary forms, with or without modification, | |
90 * are permitted provided that the following conditions are met: | |
91 * 1. Redistributions of source code must retain the above copyright notice, | |
92 * this list of conditions and the following disclaimer. | |
93 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
94 * this list of conditions and the following disclaimer in the documentation | |
95 * and/or other materials provided with the distribution. | |
96 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
97 * may be used to endorse or promote products derived from this software | |
98 * without specific prior written permission. | |
99 * | |
100 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
101 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
102 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
103 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
104 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
105 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
106 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
107 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
108 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
109 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
110 * | |
111 ****************************************************************************** | |
112 */ | |
113 | |
114 /* Includes ------------------------------------------------------------------*/ | |
115 #include "stm32f4xx_hal.h" | |
116 | |
117 /** @addtogroup STM32F4xx_HAL_Driver | |
118 * @{ | |
119 */ | |
120 | |
121 /** @defgroup ADCEx ADCEx | |
122 * @brief ADC Extended driver modules | |
123 * @{ | |
124 */ | |
125 | |
126 #ifdef HAL_ADC_MODULE_ENABLED | |
127 | |
128 /* Private typedef -----------------------------------------------------------*/ | |
129 /* Private define ------------------------------------------------------------*/ | |
130 /* Private macro -------------------------------------------------------------*/ | |
131 /* Private variables ---------------------------------------------------------*/ | |
132 /** @addtogroup ADCEx_Private_Functions | |
133 * @{ | |
134 */ | |
135 /* Private function prototypes -----------------------------------------------*/ | |
136 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma); | |
137 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma); | |
138 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); | |
139 /** | |
140 * @} | |
141 */ | |
142 | |
143 /* Exported functions --------------------------------------------------------*/ | |
144 /** @defgroup ADCEx_Exported_Functions ADC Exported Functions | |
145 * @{ | |
146 */ | |
147 | |
148 /** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions | |
149 * @brief Extended features functions | |
150 * | |
151 @verbatim | |
152 =============================================================================== | |
153 ##### Extended features functions ##### | |
154 =============================================================================== | |
155 [..] This section provides functions allowing to: | |
156 (+) Start conversion of injected channel. | |
157 (+) Stop conversion of injected channel. | |
158 (+) Start multimode and enable DMA transfer. | |
159 (+) Stop multimode and disable DMA transfer. | |
160 (+) Get result of injected channel conversion. | |
161 (+) Get result of multimode conversion. | |
162 (+) Configure injected channels. | |
163 (+) Configure multimode. | |
164 | |
165 @endverbatim | |
166 * @{ | |
167 */ | |
168 | |
169 /** | |
170 * @brief Enables the selected ADC software start conversion of the injected channels. | |
171 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
172 * the configuration information for the specified ADC. | |
173 * @retval HAL status | |
174 */ | |
175 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) | |
176 { | |
177 __IO uint32_t counter = 0U; | |
178 uint32_t tmp1 = 0U, tmp2 = 0U; | |
179 ADC_Common_TypeDef *tmpADC_Common; | |
180 | |
181 /* Process locked */ | |
182 __HAL_LOCK(hadc); | |
183 | |
184 /* Enable the ADC peripheral */ | |
185 | |
186 /* Check if ADC peripheral is disabled in order to enable it and wait during | |
187 Tstab time the ADC's stabilization */ | |
188 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) | |
189 { | |
190 /* Enable the Peripheral */ | |
191 __HAL_ADC_ENABLE(hadc); | |
192 | |
193 /* Delay for ADC stabilization time */ | |
194 /* Compute number of CPU cycles to wait for */ | |
195 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); | |
196 while(counter != 0U) | |
197 { | |
198 counter--; | |
199 } | |
200 } | |
201 | |
202 /* Start conversion if ADC is effectively enabled */ | |
203 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) | |
204 { | |
205 /* Set ADC state */ | |
206 /* - Clear state bitfield related to injected group conversion results */ | |
207 /* - Set state bitfield related to injected operation */ | |
208 ADC_STATE_CLR_SET(hadc->State, | |
209 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, | |
210 HAL_ADC_STATE_INJ_BUSY); | |
211 | |
212 /* Check if a regular conversion is ongoing */ | |
213 /* Note: On this device, there is no ADC error code fields related to */ | |
214 /* conversions on group injected only. In case of conversion on */ | |
215 /* going on group regular, no error code is reset. */ | |
216 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) | |
217 { | |
218 /* Reset ADC all error code fields */ | |
219 ADC_CLEAR_ERRORCODE(hadc); | |
220 } | |
221 | |
222 /* Process unlocked */ | |
223 /* Unlock before starting ADC conversions: in case of potential */ | |
224 /* interruption, to let the process to ADC IRQ Handler. */ | |
225 __HAL_UNLOCK(hadc); | |
226 | |
227 /* Clear injected group conversion flag */ | |
228 /* (To ensure of no unknown state from potential previous ADC operations) */ | |
229 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); | |
230 | |
231 /* Pointer to the common control register to which is belonging hadc */ | |
232 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ | |
233 /* control register) */ | |
234 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
235 | |
236 /* Check if Multimode enabled */ | |
237 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) | |
238 { | |
239 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); | |
240 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); | |
241 if(tmp1 && tmp2) | |
242 { | |
243 /* Enable the selected ADC software conversion for injected group */ | |
244 hadc->Instance->CR2 |= ADC_CR2_JSWSTART; | |
245 } | |
246 } | |
247 else | |
248 { | |
249 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); | |
250 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); | |
251 if((hadc->Instance == ADC1) && tmp1 && tmp2) | |
252 { | |
253 /* Enable the selected ADC software conversion for injected group */ | |
254 hadc->Instance->CR2 |= ADC_CR2_JSWSTART; | |
255 } | |
256 } | |
257 } | |
258 | |
259 /* Return function status */ | |
260 return HAL_OK; | |
261 } | |
262 | |
263 /** | |
264 * @brief Enables the interrupt and starts ADC conversion of injected channels. | |
265 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
266 * the configuration information for the specified ADC. | |
267 * | |
268 * @retval HAL status. | |
269 */ | |
270 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) | |
271 { | |
272 __IO uint32_t counter = 0U; | |
273 uint32_t tmp1 = 0U, tmp2 = 0U; | |
274 ADC_Common_TypeDef *tmpADC_Common; | |
275 | |
276 /* Process locked */ | |
277 __HAL_LOCK(hadc); | |
278 | |
279 /* Enable the ADC peripheral */ | |
280 | |
281 /* Check if ADC peripheral is disabled in order to enable it and wait during | |
282 Tstab time the ADC's stabilization */ | |
283 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) | |
284 { | |
285 /* Enable the Peripheral */ | |
286 __HAL_ADC_ENABLE(hadc); | |
287 | |
288 /* Delay for ADC stabilization time */ | |
289 /* Compute number of CPU cycles to wait for */ | |
290 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); | |
291 while(counter != 0U) | |
292 { | |
293 counter--; | |
294 } | |
295 } | |
296 | |
297 /* Start conversion if ADC is effectively enabled */ | |
298 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) | |
299 { | |
300 /* Set ADC state */ | |
301 /* - Clear state bitfield related to injected group conversion results */ | |
302 /* - Set state bitfield related to injected operation */ | |
303 ADC_STATE_CLR_SET(hadc->State, | |
304 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, | |
305 HAL_ADC_STATE_INJ_BUSY); | |
306 | |
307 /* Check if a regular conversion is ongoing */ | |
308 /* Note: On this device, there is no ADC error code fields related to */ | |
309 /* conversions on group injected only. In case of conversion on */ | |
310 /* going on group regular, no error code is reset. */ | |
311 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) | |
312 { | |
313 /* Reset ADC all error code fields */ | |
314 ADC_CLEAR_ERRORCODE(hadc); | |
315 } | |
316 | |
317 /* Process unlocked */ | |
318 /* Unlock before starting ADC conversions: in case of potential */ | |
319 /* interruption, to let the process to ADC IRQ Handler. */ | |
320 __HAL_UNLOCK(hadc); | |
321 | |
322 /* Clear injected group conversion flag */ | |
323 /* (To ensure of no unknown state from potential previous ADC operations) */ | |
324 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); | |
325 | |
326 /* Enable end of conversion interrupt for injected channels */ | |
327 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); | |
328 | |
329 /* Pointer to the common control register to which is belonging hadc */ | |
330 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ | |
331 /* control register) */ | |
332 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
333 | |
334 /* Check if Multimode enabled */ | |
335 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) | |
336 { | |
337 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); | |
338 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); | |
339 if(tmp1 && tmp2) | |
340 { | |
341 /* Enable the selected ADC software conversion for injected group */ | |
342 hadc->Instance->CR2 |= ADC_CR2_JSWSTART; | |
343 } | |
344 } | |
345 else | |
346 { | |
347 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); | |
348 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); | |
349 if((hadc->Instance == ADC1) && tmp1 && tmp2) | |
350 { | |
351 /* Enable the selected ADC software conversion for injected group */ | |
352 hadc->Instance->CR2 |= ADC_CR2_JSWSTART; | |
353 } | |
354 } | |
355 } | |
356 | |
357 /* Return function status */ | |
358 return HAL_OK; | |
359 } | |
360 | |
361 /** | |
362 * @brief Stop conversion of injected channels. Disable ADC peripheral if | |
363 * no regular conversion is on going. | |
364 * @note If ADC must be disabled and if conversion is on going on | |
365 * regular group, function HAL_ADC_Stop must be used to stop both | |
366 * injected and regular groups, and disable the ADC. | |
367 * @note If injected group mode auto-injection is enabled, | |
368 * function HAL_ADC_Stop must be used. | |
369 * @note In case of auto-injection mode, HAL_ADC_Stop must be used. | |
370 * @param hadc ADC handle | |
371 * @retval None | |
372 */ | |
373 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) | |
374 { | |
375 HAL_StatusTypeDef tmp_hal_status = HAL_OK; | |
376 | |
377 /* Check the parameters */ | |
378 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); | |
379 | |
380 /* Process locked */ | |
381 __HAL_LOCK(hadc); | |
382 | |
383 /* Stop potential conversion and disable ADC peripheral */ | |
384 /* Conditioned to: */ | |
385 /* - No conversion on the other group (regular group) is intended to */ | |
386 /* continue (injected and regular groups stop conversion and ADC disable */ | |
387 /* are common) */ | |
388 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ | |
389 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && | |
390 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) | |
391 { | |
392 /* Stop potential conversion on going, on regular and injected groups */ | |
393 /* Disable ADC peripheral */ | |
394 __HAL_ADC_DISABLE(hadc); | |
395 | |
396 /* Check if ADC is effectively disabled */ | |
397 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) | |
398 { | |
399 /* Set ADC state */ | |
400 ADC_STATE_CLR_SET(hadc->State, | |
401 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, | |
402 HAL_ADC_STATE_READY); | |
403 } | |
404 } | |
405 else | |
406 { | |
407 /* Update ADC state machine to error */ | |
408 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); | |
409 | |
410 tmp_hal_status = HAL_ERROR; | |
411 } | |
412 | |
413 /* Process unlocked */ | |
414 __HAL_UNLOCK(hadc); | |
415 | |
416 /* Return function status */ | |
417 return tmp_hal_status; | |
418 } | |
419 | |
420 /** | |
421 * @brief Poll for injected conversion complete | |
422 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
423 * the configuration information for the specified ADC. | |
424 * @param Timeout Timeout value in millisecond. | |
425 * @retval HAL status | |
426 */ | |
427 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) | |
428 { | |
429 uint32_t tickstart = 0U; | |
430 | |
431 /* Get tick */ | |
432 tickstart = HAL_GetTick(); | |
433 | |
434 /* Check End of conversion flag */ | |
435 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) | |
436 { | |
437 /* Check for the Timeout */ | |
438 if(Timeout != HAL_MAX_DELAY) | |
439 { | |
440 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) | |
441 { | |
442 hadc->State= HAL_ADC_STATE_TIMEOUT; | |
443 /* Process unlocked */ | |
444 __HAL_UNLOCK(hadc); | |
445 return HAL_TIMEOUT; | |
446 } | |
447 } | |
448 } | |
449 | |
450 /* Clear injected group conversion flag */ | |
451 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); | |
452 | |
453 /* Update ADC state machine */ | |
454 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); | |
455 | |
456 /* Determine whether any further conversion upcoming on group injected */ | |
457 /* by external trigger, continuous mode or scan sequence on going. */ | |
458 /* Note: On STM32F4, there is no independent flag of end of sequence. */ | |
459 /* The test of scan sequence on going is done either with scan */ | |
460 /* sequence disabled or with end of conversion flag set to */ | |
461 /* of end of sequence. */ | |
462 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && | |
463 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || | |
464 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && | |
465 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && | |
466 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && | |
467 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) | |
468 { | |
469 /* Set ADC state */ | |
470 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); | |
471 | |
472 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) | |
473 { | |
474 SET_BIT(hadc->State, HAL_ADC_STATE_READY); | |
475 } | |
476 } | |
477 | |
478 /* Return ADC state */ | |
479 return HAL_OK; | |
480 } | |
481 | |
482 /** | |
483 * @brief Stop conversion of injected channels, disable interruption of | |
484 * end-of-conversion. Disable ADC peripheral if no regular conversion | |
485 * is on going. | |
486 * @note If ADC must be disabled and if conversion is on going on | |
487 * regular group, function HAL_ADC_Stop must be used to stop both | |
488 * injected and regular groups, and disable the ADC. | |
489 * @note If injected group mode auto-injection is enabled, | |
490 * function HAL_ADC_Stop must be used. | |
491 * @param hadc ADC handle | |
492 * @retval None | |
493 */ | |
494 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) | |
495 { | |
496 HAL_StatusTypeDef tmp_hal_status = HAL_OK; | |
497 | |
498 /* Check the parameters */ | |
499 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); | |
500 | |
501 /* Process locked */ | |
502 __HAL_LOCK(hadc); | |
503 | |
504 /* Stop potential conversion and disable ADC peripheral */ | |
505 /* Conditioned to: */ | |
506 /* - No conversion on the other group (regular group) is intended to */ | |
507 /* continue (injected and regular groups stop conversion and ADC disable */ | |
508 /* are common) */ | |
509 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ | |
510 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && | |
511 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) | |
512 { | |
513 /* Stop potential conversion on going, on regular and injected groups */ | |
514 /* Disable ADC peripheral */ | |
515 __HAL_ADC_DISABLE(hadc); | |
516 | |
517 /* Check if ADC is effectively disabled */ | |
518 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) | |
519 { | |
520 /* Disable ADC end of conversion interrupt for injected channels */ | |
521 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); | |
522 | |
523 /* Set ADC state */ | |
524 ADC_STATE_CLR_SET(hadc->State, | |
525 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, | |
526 HAL_ADC_STATE_READY); | |
527 } | |
528 } | |
529 else | |
530 { | |
531 /* Update ADC state machine to error */ | |
532 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); | |
533 | |
534 tmp_hal_status = HAL_ERROR; | |
535 } | |
536 | |
537 /* Process unlocked */ | |
538 __HAL_UNLOCK(hadc); | |
539 | |
540 /* Return function status */ | |
541 return tmp_hal_status; | |
542 } | |
543 | |
544 /** | |
545 * @brief Gets the converted value from data register of injected channel. | |
546 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
547 * the configuration information for the specified ADC. | |
548 * @param InjectedRank the ADC injected rank. | |
549 * This parameter can be one of the following values: | |
550 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected | |
551 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected | |
552 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected | |
553 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected | |
554 * @retval None | |
555 */ | |
556 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) | |
557 { | |
558 __IO uint32_t tmp = 0U; | |
559 | |
560 /* Check the parameters */ | |
561 assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); | |
562 | |
563 /* Clear injected group conversion flag to have similar behaviour as */ | |
564 /* regular group: reading data register also clears end of conversion flag. */ | |
565 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); | |
566 | |
567 /* Return the selected ADC converted value */ | |
568 switch(InjectedRank) | |
569 { | |
570 case ADC_INJECTED_RANK_4: | |
571 { | |
572 tmp = hadc->Instance->JDR4; | |
573 } | |
574 break; | |
575 case ADC_INJECTED_RANK_3: | |
576 { | |
577 tmp = hadc->Instance->JDR3; | |
578 } | |
579 break; | |
580 case ADC_INJECTED_RANK_2: | |
581 { | |
582 tmp = hadc->Instance->JDR2; | |
583 } | |
584 break; | |
585 case ADC_INJECTED_RANK_1: | |
586 { | |
587 tmp = hadc->Instance->JDR1; | |
588 } | |
589 break; | |
590 default: | |
591 break; | |
592 } | |
593 return tmp; | |
594 } | |
595 | |
596 /** | |
597 * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral | |
598 * | |
599 * @note Caution: This function must be used only with the ADC master. | |
600 * | |
601 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
602 * the configuration information for the specified ADC. | |
603 * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. | |
604 * @param Length The length of data to be transferred from ADC peripheral to memory. | |
605 * @retval HAL status | |
606 */ | |
607 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) | |
608 { | |
609 __IO uint32_t counter = 0U; | |
610 ADC_Common_TypeDef *tmpADC_Common; | |
611 | |
612 /* Check the parameters */ | |
613 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); | |
614 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); | |
615 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); | |
616 | |
617 /* Process locked */ | |
618 __HAL_LOCK(hadc); | |
619 | |
620 /* Check if ADC peripheral is disabled in order to enable it and wait during | |
621 Tstab time the ADC's stabilization */ | |
622 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) | |
623 { | |
624 /* Enable the Peripheral */ | |
625 __HAL_ADC_ENABLE(hadc); | |
626 | |
627 /* Delay for temperature sensor stabilization time */ | |
628 /* Compute number of CPU cycles to wait for */ | |
629 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); | |
630 while(counter != 0U) | |
631 { | |
632 counter--; | |
633 } | |
634 } | |
635 | |
636 /* Start conversion if ADC is effectively enabled */ | |
637 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) | |
638 { | |
639 /* Set ADC state */ | |
640 /* - Clear state bitfield related to regular group conversion results */ | |
641 /* - Set state bitfield related to regular group operation */ | |
642 ADC_STATE_CLR_SET(hadc->State, | |
643 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, | |
644 HAL_ADC_STATE_REG_BUSY); | |
645 | |
646 /* If conversions on group regular are also triggering group injected, */ | |
647 /* update ADC state. */ | |
648 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) | |
649 { | |
650 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); | |
651 } | |
652 | |
653 /* State machine update: Check if an injected conversion is ongoing */ | |
654 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) | |
655 { | |
656 /* Reset ADC error code fields related to conversions on group regular */ | |
657 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); | |
658 } | |
659 else | |
660 { | |
661 /* Reset ADC all error code fields */ | |
662 ADC_CLEAR_ERRORCODE(hadc); | |
663 } | |
664 | |
665 /* Process unlocked */ | |
666 /* Unlock before starting ADC conversions: in case of potential */ | |
667 /* interruption, to let the process to ADC IRQ Handler. */ | |
668 __HAL_UNLOCK(hadc); | |
669 | |
670 /* Set the DMA transfer complete callback */ | |
671 hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; | |
672 | |
673 /* Set the DMA half transfer complete callback */ | |
674 hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; | |
675 | |
676 /* Set the DMA error callback */ | |
677 hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; | |
678 | |
679 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ | |
680 /* start (in case of SW start): */ | |
681 | |
682 /* Clear regular group conversion flag and overrun flag */ | |
683 /* (To ensure of no unknown state from potential previous ADC operations) */ | |
684 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); | |
685 | |
686 /* Enable ADC overrun interrupt */ | |
687 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); | |
688 | |
689 /* Pointer to the common control register to which is belonging hadc */ | |
690 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ | |
691 /* control register) */ | |
692 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
693 | |
694 if (hadc->Init.DMAContinuousRequests != DISABLE) | |
695 { | |
696 /* Enable the selected ADC DMA request after last transfer */ | |
697 tmpADC_Common->CCR |= ADC_CCR_DDS; | |
698 } | |
699 else | |
700 { | |
701 /* Disable the selected ADC EOC rising on each regular channel conversion */ | |
702 tmpADC_Common->CCR &= ~ADC_CCR_DDS; | |
703 } | |
704 | |
705 /* Enable the DMA Stream */ | |
706 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); | |
707 | |
708 /* if no external trigger present enable software conversion of regular channels */ | |
709 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) | |
710 { | |
711 /* Enable the selected ADC software conversion for regular group */ | |
712 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; | |
713 } | |
714 } | |
715 | |
716 /* Return function status */ | |
717 return HAL_OK; | |
718 } | |
719 | |
720 /** | |
721 * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral | |
722 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
723 * the configuration information for the specified ADC. | |
724 * @retval HAL status | |
725 */ | |
726 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) | |
727 { | |
728 HAL_StatusTypeDef tmp_hal_status = HAL_OK; | |
729 ADC_Common_TypeDef *tmpADC_Common; | |
730 | |
731 /* Check the parameters */ | |
732 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); | |
733 | |
734 /* Process locked */ | |
735 __HAL_LOCK(hadc); | |
736 | |
737 /* Stop potential conversion on going, on regular and injected groups */ | |
738 /* Disable ADC peripheral */ | |
739 __HAL_ADC_DISABLE(hadc); | |
740 | |
741 /* Pointer to the common control register to which is belonging hadc */ | |
742 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ | |
743 /* control register) */ | |
744 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
745 | |
746 /* Check if ADC is effectively disabled */ | |
747 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) | |
748 { | |
749 /* Disable the selected ADC DMA mode for multimode */ | |
750 tmpADC_Common->CCR &= ~ADC_CCR_DDS; | |
751 | |
752 /* Disable the DMA channel (in case of DMA in circular mode or stop while */ | |
753 /* DMA transfer is on going) */ | |
754 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); | |
755 | |
756 /* Disable ADC overrun interrupt */ | |
757 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); | |
758 | |
759 /* Set ADC state */ | |
760 ADC_STATE_CLR_SET(hadc->State, | |
761 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, | |
762 HAL_ADC_STATE_READY); | |
763 } | |
764 | |
765 /* Process unlocked */ | |
766 __HAL_UNLOCK(hadc); | |
767 | |
768 /* Return function status */ | |
769 return tmp_hal_status; | |
770 } | |
771 | |
772 /** | |
773 * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results | |
774 * data in the selected multi mode. | |
775 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
776 * the configuration information for the specified ADC. | |
777 * @retval The converted data value. | |
778 */ | |
779 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) | |
780 { | |
781 ADC_Common_TypeDef *tmpADC_Common; | |
782 | |
783 /* Pointer to the common control register to which is belonging hadc */ | |
784 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ | |
785 /* control register) */ | |
786 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
787 | |
788 /* Return the multi mode conversion value */ | |
789 return tmpADC_Common->CDR; | |
790 } | |
791 | |
792 /** | |
793 * @brief Injected conversion complete callback in non blocking mode | |
794 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
795 * the configuration information for the specified ADC. | |
796 * @retval None | |
797 */ | |
798 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) | |
799 { | |
800 /* Prevent unused argument(s) compilation warning */ | |
801 UNUSED(hadc); | |
802 /* NOTE : This function Should not be modified, when the callback is needed, | |
803 the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file | |
804 */ | |
805 } | |
806 | |
807 /** | |
808 * @brief Configures for the selected ADC injected channel its corresponding | |
809 * rank in the sequencer and its sample time. | |
810 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
811 * the configuration information for the specified ADC. | |
812 * @param sConfigInjected ADC configuration structure for injected channel. | |
813 * @retval None | |
814 */ | |
815 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) | |
816 { | |
817 | |
818 #ifdef USE_FULL_ASSERT | |
819 uint32_t tmp = 0U; | |
820 | |
821 #endif /* USE_FULL_ASSERT */ | |
822 | |
823 ADC_Common_TypeDef *tmpADC_Common; | |
824 | |
825 /* Check the parameters */ | |
826 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); | |
827 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); | |
828 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); | |
829 assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); | |
830 assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); | |
831 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); | |
832 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); | |
833 | |
834 #ifdef USE_FULL_ASSERT | |
835 tmp = ADC_GET_RESOLUTION(hadc); | |
836 assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); | |
837 #endif /* USE_FULL_ASSERT */ | |
838 | |
839 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) | |
840 { | |
841 assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); | |
842 } | |
843 | |
844 /* Process locked */ | |
845 __HAL_LOCK(hadc); | |
846 | |
847 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ | |
848 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) | |
849 { | |
850 /* Clear the old sample time */ | |
851 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); | |
852 | |
853 /* Set the new sample time */ | |
854 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); | |
855 } | |
856 else /* ADC_Channel include in ADC_Channel_[0..9] */ | |
857 { | |
858 /* Clear the old sample time */ | |
859 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); | |
860 | |
861 /* Set the new sample time */ | |
862 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); | |
863 } | |
864 | |
865 /*---------------------------- ADCx JSQR Configuration -----------------*/ | |
866 hadc->Instance->JSQR &= ~(ADC_JSQR_JL); | |
867 hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); | |
868 | |
869 /* Rank configuration */ | |
870 | |
871 /* Clear the old SQx bits for the selected rank */ | |
872 hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); | |
873 | |
874 /* Set the SQx bits for the selected rank */ | |
875 hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); | |
876 | |
877 /* Enable external trigger if trigger selection is different of software */ | |
878 /* start. */ | |
879 /* Note: This configuration keeps the hardware feature of parameter */ | |
880 /* ExternalTrigConvEdge "trigger edge none" equivalent to */ | |
881 /* software start. */ | |
882 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) | |
883 { | |
884 /* Select external trigger to start conversion */ | |
885 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); | |
886 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; | |
887 | |
888 /* Select external trigger polarity */ | |
889 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); | |
890 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; | |
891 } | |
892 else | |
893 { | |
894 /* Reset the external trigger */ | |
895 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); | |
896 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); | |
897 } | |
898 | |
899 if (sConfigInjected->AutoInjectedConv != DISABLE) | |
900 { | |
901 /* Enable the selected ADC automatic injected group conversion */ | |
902 hadc->Instance->CR1 |= ADC_CR1_JAUTO; | |
903 } | |
904 else | |
905 { | |
906 /* Disable the selected ADC automatic injected group conversion */ | |
907 hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); | |
908 } | |
909 | |
910 if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) | |
911 { | |
912 /* Enable the selected ADC injected discontinuous mode */ | |
913 hadc->Instance->CR1 |= ADC_CR1_JDISCEN; | |
914 } | |
915 else | |
916 { | |
917 /* Disable the selected ADC injected discontinuous mode */ | |
918 hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); | |
919 } | |
920 | |
921 switch(sConfigInjected->InjectedRank) | |
922 { | |
923 case 1U: | |
924 /* Set injected channel 1 offset */ | |
925 hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); | |
926 hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; | |
927 break; | |
928 case 2U: | |
929 /* Set injected channel 2 offset */ | |
930 hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); | |
931 hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; | |
932 break; | |
933 case 3U: | |
934 /* Set injected channel 3 offset */ | |
935 hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); | |
936 hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; | |
937 break; | |
938 default: | |
939 /* Set injected channel 4 offset */ | |
940 hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); | |
941 hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; | |
942 break; | |
943 } | |
944 | |
945 /* Pointer to the common control register to which is belonging hadc */ | |
946 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ | |
947 /* control register) */ | |
948 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
949 | |
950 /* if ADC1 Channel_18 is selected enable VBAT Channel */ | |
951 if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) | |
952 { | |
953 /* Enable the VBAT channel*/ | |
954 tmpADC_Common->CCR |= ADC_CCR_VBATE; | |
955 } | |
956 | |
957 /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ | |
958 if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) | |
959 { | |
960 /* Enable the TSVREFE channel*/ | |
961 tmpADC_Common->CCR |= ADC_CCR_TSVREFE; | |
962 } | |
963 | |
964 /* Process unlocked */ | |
965 __HAL_UNLOCK(hadc); | |
966 | |
967 /* Return function status */ | |
968 return HAL_OK; | |
969 } | |
970 | |
971 /** | |
972 * @brief Configures the ADC multi-mode | |
973 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
974 * the configuration information for the specified ADC. | |
975 * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains | |
976 * the configuration information for multimode. | |
977 * @retval HAL status | |
978 */ | |
979 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) | |
980 { | |
981 | |
982 ADC_Common_TypeDef *tmpADC_Common; | |
983 | |
984 /* Check the parameters */ | |
985 assert_param(IS_ADC_MODE(multimode->Mode)); | |
986 assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); | |
987 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); | |
988 | |
989 /* Process locked */ | |
990 __HAL_LOCK(hadc); | |
991 | |
992 /* Pointer to the common control register to which is belonging hadc */ | |
993 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ | |
994 /* control register) */ | |
995 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
996 | |
997 /* Set ADC mode */ | |
998 tmpADC_Common->CCR &= ~(ADC_CCR_MULTI); | |
999 tmpADC_Common->CCR |= multimode->Mode; | |
1000 | |
1001 /* Set the ADC DMA access mode */ | |
1002 tmpADC_Common->CCR &= ~(ADC_CCR_DMA); | |
1003 tmpADC_Common->CCR |= multimode->DMAAccessMode; | |
1004 | |
1005 /* Set delay between two sampling phases */ | |
1006 tmpADC_Common->CCR &= ~(ADC_CCR_DELAY); | |
1007 tmpADC_Common->CCR |= multimode->TwoSamplingDelay; | |
1008 | |
1009 /* Process unlocked */ | |
1010 __HAL_UNLOCK(hadc); | |
1011 | |
1012 /* Return function status */ | |
1013 return HAL_OK; | |
1014 } | |
1015 | |
1016 /** | |
1017 * @} | |
1018 */ | |
1019 | |
1020 /** | |
1021 * @brief DMA transfer complete callback. | |
1022 * @param hdma pointer to a DMA_HandleTypeDef structure that contains | |
1023 * the configuration information for the specified DMA module. | |
1024 * @retval None | |
1025 */ | |
1026 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) | |
1027 { | |
1028 /* Retrieve ADC handle corresponding to current DMA handle */ | |
1029 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
1030 | |
1031 /* Update state machine on conversion status if not in error state */ | |
1032 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) | |
1033 { | |
1034 /* Update ADC state machine */ | |
1035 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); | |
1036 | |
1037 /* Determine whether any further conversion upcoming on group regular */ | |
1038 /* by external trigger, continuous mode or scan sequence on going. */ | |
1039 /* Note: On STM32F4, there is no independent flag of end of sequence. */ | |
1040 /* The test of scan sequence on going is done either with scan */ | |
1041 /* sequence disabled or with end of conversion flag set to */ | |
1042 /* of end of sequence. */ | |
1043 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && | |
1044 (hadc->Init.ContinuousConvMode == DISABLE) && | |
1045 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || | |
1046 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) | |
1047 { | |
1048 /* Disable ADC end of single conversion interrupt on group regular */ | |
1049 /* Note: Overrun interrupt was enabled with EOC interrupt in */ | |
1050 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ | |
1051 /* by overrun IRQ process below. */ | |
1052 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); | |
1053 | |
1054 /* Set ADC state */ | |
1055 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); | |
1056 | |
1057 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) | |
1058 { | |
1059 SET_BIT(hadc->State, HAL_ADC_STATE_READY); | |
1060 } | |
1061 } | |
1062 | |
1063 /* Conversion complete callback */ | |
1064 HAL_ADC_ConvCpltCallback(hadc); | |
1065 } | |
1066 else | |
1067 { | |
1068 /* Call DMA error callback */ | |
1069 hadc->DMA_Handle->XferErrorCallback(hdma); | |
1070 } | |
1071 } | |
1072 | |
1073 /** | |
1074 * @brief DMA half transfer complete callback. | |
1075 * @param hdma pointer to a DMA_HandleTypeDef structure that contains | |
1076 * the configuration information for the specified DMA module. | |
1077 * @retval None | |
1078 */ | |
1079 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) | |
1080 { | |
1081 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
1082 /* Conversion complete callback */ | |
1083 HAL_ADC_ConvHalfCpltCallback(hadc); | |
1084 } | |
1085 | |
1086 /** | |
1087 * @brief DMA error callback | |
1088 * @param hdma pointer to a DMA_HandleTypeDef structure that contains | |
1089 * the configuration information for the specified DMA module. | |
1090 * @retval None | |
1091 */ | |
1092 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) | |
1093 { | |
1094 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
1095 hadc->State= HAL_ADC_STATE_ERROR_DMA; | |
1096 /* Set ADC error code to DMA error */ | |
1097 hadc->ErrorCode |= HAL_ADC_ERROR_DMA; | |
1098 HAL_ADC_ErrorCallback(hadc); | |
1099 } | |
1100 | |
1101 /** | |
1102 * @} | |
1103 */ | |
1104 | |
1105 #endif /* HAL_ADC_MODULE_ENABLED */ | |
1106 /** | |
1107 * @} | |
1108 */ | |
1109 | |
1110 /** | |
1111 * @} | |
1112 */ | |
1113 | |
1114 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |