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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_wwdg.h
4 * @author MCD Application Team
5 * @brief Header file of WWDG LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_LL_WWDG_H
38 #define __STM32F4xx_LL_WWDG_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx.h"
46
47 /** @addtogroup STM32F4xx_LL_Driver
48 * @{
49 */
50
51 #if defined (WWDG)
52
53 /** @defgroup WWDG_LL WWDG
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61
62 /* Private macros ------------------------------------------------------------*/
63
64 /* Exported types ------------------------------------------------------------*/
65 /* Exported constants --------------------------------------------------------*/
66 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
67 * @{
68 */
69
70
71 /** @defgroup WWDG_LL_EC_IT IT Defines
72 * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
73 * @{
74 */
75 #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
76 /**
77 * @}
78 */
79
80 /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
81 * @{
82 */
83 #define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
84 #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
85 #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
86 #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
87 /**
88 * @}
89 */
90
91 /**
92 * @}
93 */
94
95 /* Exported macro ------------------------------------------------------------*/
96 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
97 * @{
98 */
99 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
100 * @{
101 */
102 /**
103 * @brief Write a value in WWDG register
104 * @param __INSTANCE__ WWDG Instance
105 * @param __REG__ Register to be written
106 * @param __VALUE__ Value to be written in the register
107 * @retval None
108 */
109 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
110
111 /**
112 * @brief Read a value in WWDG register
113 * @param __INSTANCE__ WWDG Instance
114 * @param __REG__ Register to be read
115 * @retval Register value
116 */
117 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
118 /**
119 * @}
120 */
121
122
123 /**
124 * @}
125 */
126
127 /* Exported functions --------------------------------------------------------*/
128 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
129 * @{
130 */
131
132 /** @defgroup WWDG_LL_EF_Configuration Configuration
133 * @{
134 */
135 /**
136 * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
137 * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
138 * then it cannot be disabled again except by a reset.
139 * This bit is set by software and only cleared by hardware after a reset.
140 * When WDGA = 1, the watchdog can generate a reset.
141 * @rmtoll CR WDGA LL_WWDG_Enable
142 * @param WWDGx WWDG Instance
143 * @retval None
144 */
145 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
146 {
147 SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
148 }
149
150 /**
151 * @brief Checks if Window Watchdog is enabled
152 * @rmtoll CR WDGA LL_WWDG_IsEnabled
153 * @param WWDGx WWDG Instance
154 * @retval State of bit (1 or 0).
155 */
156 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
157 {
158 return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
159 }
160
161 /**
162 * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
163 * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
164 * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
165 * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
166 * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
167 * @rmtoll CR T LL_WWDG_SetCounter
168 * @param WWDGx WWDG Instance
169 * @param Counter 0..0x7F (7 bit counter value)
170 * @retval None
171 */
172 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
173 {
174 MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
175 }
176
177 /**
178 * @brief Return current Watchdog Counter Value (7 bits counter value)
179 * @rmtoll CR T LL_WWDG_GetCounter
180 * @param WWDGx WWDG Instance
181 * @retval 7 bit Watchdog Counter value
182 */
183 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
184 {
185 return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
186 }
187
188 /**
189 * @brief Set the time base of the prescaler (WDGTB).
190 * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
191 * is decremented every (4096 x 2expWDGTB) PCLK cycles
192 * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
193 * @param WWDGx WWDG Instance
194 * @param Prescaler This parameter can be one of the following values:
195 * @arg @ref LL_WWDG_PRESCALER_1
196 * @arg @ref LL_WWDG_PRESCALER_2
197 * @arg @ref LL_WWDG_PRESCALER_4
198 * @arg @ref LL_WWDG_PRESCALER_8
199 * @retval None
200 */
201 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
202 {
203 MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
204 }
205
206 /**
207 * @brief Return current Watchdog Prescaler Value
208 * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
209 * @param WWDGx WWDG Instance
210 * @retval Returned value can be one of the following values:
211 * @arg @ref LL_WWDG_PRESCALER_1
212 * @arg @ref LL_WWDG_PRESCALER_2
213 * @arg @ref LL_WWDG_PRESCALER_4
214 * @arg @ref LL_WWDG_PRESCALER_8
215 */
216 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
217 {
218 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
219 }
220
221 /**
222 * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
223 * @note This window value defines when write in the WWDG_CR register
224 * to program Watchdog counter is allowed.
225 * Watchdog counter value update must occur only when the counter value
226 * is lower than the Watchdog window register value.
227 * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
228 * (in the control register) is refreshed before the downcounter has reached
229 * the watchdog window register value.
230 * Physically is possible to set the Window lower then 0x40 but it is not recommended.
231 * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
232 * @rmtoll CFR W LL_WWDG_SetWindow
233 * @param WWDGx WWDG Instance
234 * @param Window 0x00..0x7F (7 bit Window value)
235 * @retval None
236 */
237 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
238 {
239 MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
240 }
241
242 /**
243 * @brief Return current Watchdog Window Value (7 bits value)
244 * @rmtoll CFR W LL_WWDG_GetWindow
245 * @param WWDGx WWDG Instance
246 * @retval 7 bit Watchdog Window value
247 */
248 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
249 {
250 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
251 }
252
253 /**
254 * @}
255 */
256
257 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
258 * @{
259 */
260 /**
261 * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
262 * @note This bit is set by hardware when the counter has reached the value 0x40.
263 * It must be cleared by software by writing 0.
264 * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
265 * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
266 * @param WWDGx WWDG Instance
267 * @retval State of bit (1 or 0).
268 */
269 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
270 {
271 return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
272 }
273
274 /**
275 * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
276 * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
277 * @param WWDGx WWDG Instance
278 * @retval None
279 */
280 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
281 {
282 WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
283 }
284
285 /**
286 * @}
287 */
288
289 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
290 * @{
291 */
292 /**
293 * @brief Enable the Early Wakeup Interrupt.
294 * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
295 * This interrupt is only cleared by hardware after a reset
296 * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
297 * @param WWDGx WWDG Instance
298 * @retval None
299 */
300 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
301 {
302 SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
303 }
304
305 /**
306 * @brief Check if Early Wakeup Interrupt is enabled
307 * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
308 * @param WWDGx WWDG Instance
309 * @retval State of bit (1 or 0).
310 */
311 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
312 {
313 return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
314 }
315
316 /**
317 * @}
318 */
319
320 /**
321 * @}
322 */
323
324 /**
325 * @}
326 */
327
328 #endif /* WWDG */
329
330 /**
331 * @}
332 */
333
334 #ifdef __cplusplus
335 }
336 #endif
337
338 #endif /* __STM32F4xx_LL_WWDG_H */
339
340 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/