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Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_tim.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of TIM LL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_LL_TIM_H | |
38 #define __STM32F4xx_LL_TIM_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 /* Includes ------------------------------------------------------------------*/ | |
45 #include "stm32f4xx.h" | |
46 | |
47 /** @addtogroup STM32F4xx_LL_Driver | |
48 * @{ | |
49 */ | |
50 | |
51 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) | |
52 | |
53 /** @defgroup TIM_LL TIM | |
54 * @{ | |
55 */ | |
56 | |
57 /* Private types -------------------------------------------------------------*/ | |
58 /* Private variables ---------------------------------------------------------*/ | |
59 /** @defgroup TIM_LL_Private_Variables TIM Private Variables | |
60 * @{ | |
61 */ | |
62 static const uint8_t OFFSET_TAB_CCMRx[] = | |
63 { | |
64 0x00U, /* 0: TIMx_CH1 */ | |
65 0x00U, /* 1: TIMx_CH1N */ | |
66 0x00U, /* 2: TIMx_CH2 */ | |
67 0x00U, /* 3: TIMx_CH2N */ | |
68 0x04U, /* 4: TIMx_CH3 */ | |
69 0x04U, /* 5: TIMx_CH3N */ | |
70 0x04U /* 6: TIMx_CH4 */ | |
71 }; | |
72 | |
73 static const uint8_t SHIFT_TAB_OCxx[] = | |
74 { | |
75 0U, /* 0: OC1M, OC1FE, OC1PE */ | |
76 0U, /* 1: - NA */ | |
77 8U, /* 2: OC2M, OC2FE, OC2PE */ | |
78 0U, /* 3: - NA */ | |
79 0U, /* 4: OC3M, OC3FE, OC3PE */ | |
80 0U, /* 5: - NA */ | |
81 8U /* 6: OC4M, OC4FE, OC4PE */ | |
82 }; | |
83 | |
84 static const uint8_t SHIFT_TAB_ICxx[] = | |
85 { | |
86 0U, /* 0: CC1S, IC1PSC, IC1F */ | |
87 0U, /* 1: - NA */ | |
88 8U, /* 2: CC2S, IC2PSC, IC2F */ | |
89 0U, /* 3: - NA */ | |
90 0U, /* 4: CC3S, IC3PSC, IC3F */ | |
91 0U, /* 5: - NA */ | |
92 8U /* 6: CC4S, IC4PSC, IC4F */ | |
93 }; | |
94 | |
95 static const uint8_t SHIFT_TAB_CCxP[] = | |
96 { | |
97 0U, /* 0: CC1P */ | |
98 2U, /* 1: CC1NP */ | |
99 4U, /* 2: CC2P */ | |
100 6U, /* 3: CC2NP */ | |
101 8U, /* 4: CC3P */ | |
102 10U, /* 5: CC3NP */ | |
103 12U /* 6: CC4P */ | |
104 }; | |
105 | |
106 static const uint8_t SHIFT_TAB_OISx[] = | |
107 { | |
108 0U, /* 0: OIS1 */ | |
109 1U, /* 1: OIS1N */ | |
110 2U, /* 2: OIS2 */ | |
111 3U, /* 3: OIS2N */ | |
112 4U, /* 4: OIS3 */ | |
113 5U, /* 5: OIS3N */ | |
114 6U /* 6: OIS4 */ | |
115 }; | |
116 /** | |
117 * @} | |
118 */ | |
119 | |
120 | |
121 /* Private constants ---------------------------------------------------------*/ | |
122 /** @defgroup TIM_LL_Private_Constants TIM Private Constants | |
123 * @{ | |
124 */ | |
125 | |
126 | |
127 /* Remap mask definitions */ | |
128 #define TIMx_OR_RMP_SHIFT 16U | |
129 #define TIMx_OR_RMP_MASK 0x0000FFFFU | |
130 #define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) | |
131 #define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) | |
132 #define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) | |
133 | |
134 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ | |
135 #define DT_DELAY_1 ((uint8_t)0x7FU) | |
136 #define DT_DELAY_2 ((uint8_t)0x3FU) | |
137 #define DT_DELAY_3 ((uint8_t)0x1FU) | |
138 #define DT_DELAY_4 ((uint8_t)0x1FU) | |
139 | |
140 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ | |
141 #define DT_RANGE_1 ((uint8_t)0x00U) | |
142 #define DT_RANGE_2 ((uint8_t)0x80U) | |
143 #define DT_RANGE_3 ((uint8_t)0xC0U) | |
144 #define DT_RANGE_4 ((uint8_t)0xE0U) | |
145 | |
146 | |
147 /** | |
148 * @} | |
149 */ | |
150 | |
151 /* Private macros ------------------------------------------------------------*/ | |
152 /** @defgroup TIM_LL_Private_Macros TIM Private Macros | |
153 * @{ | |
154 */ | |
155 /** @brief Convert channel id into channel index. | |
156 * @param __CHANNEL__ This parameter can be one of the following values: | |
157 * @arg @ref LL_TIM_CHANNEL_CH1 | |
158 * @arg @ref LL_TIM_CHANNEL_CH1N | |
159 * @arg @ref LL_TIM_CHANNEL_CH2 | |
160 * @arg @ref LL_TIM_CHANNEL_CH2N | |
161 * @arg @ref LL_TIM_CHANNEL_CH3 | |
162 * @arg @ref LL_TIM_CHANNEL_CH3N | |
163 * @arg @ref LL_TIM_CHANNEL_CH4 | |
164 * @retval none | |
165 */ | |
166 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ | |
167 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ | |
168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ | |
169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ | |
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ | |
171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ | |
172 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) | |
173 | |
174 /** @brief Calculate the deadtime sampling period(in ps). | |
175 * @param __TIMCLK__ timer input clock frequency (in Hz). | |
176 * @param __CKD__ This parameter can be one of the following values: | |
177 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 | |
178 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 | |
179 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 | |
180 * @retval none | |
181 */ | |
182 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ | |
183 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ | |
184 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ | |
185 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) | |
186 /** | |
187 * @} | |
188 */ | |
189 | |
190 | |
191 /* Exported types ------------------------------------------------------------*/ | |
192 #if defined(USE_FULL_LL_DRIVER) | |
193 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure | |
194 * @{ | |
195 */ | |
196 | |
197 /** | |
198 * @brief TIM Time Base configuration structure definition. | |
199 */ | |
200 typedef struct | |
201 { | |
202 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. | |
203 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. | |
204 | |
205 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ | |
206 | |
207 uint32_t CounterMode; /*!< Specifies the counter mode. | |
208 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. | |
209 | |
210 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ | |
211 | |
212 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active | |
213 Auto-Reload Register at the next update event. | |
214 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. | |
215 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. | |
216 | |
217 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ | |
218 | |
219 uint32_t ClockDivision; /*!< Specifies the clock division. | |
220 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. | |
221 | |
222 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ | |
223 | |
224 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter | |
225 reaches zero, an update event is generated and counting restarts | |
226 from the RCR value (N). | |
227 This means in PWM mode that (N+1) corresponds to: | |
228 - the number of PWM periods in edge-aligned mode | |
229 - the number of half PWM period in center-aligned mode | |
230 This parameter must be a number between 0x00 and 0xFF. | |
231 | |
232 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ | |
233 } LL_TIM_InitTypeDef; | |
234 | |
235 /** | |
236 * @brief TIM Output Compare configuration structure definition. | |
237 */ | |
238 typedef struct | |
239 { | |
240 uint32_t OCMode; /*!< Specifies the output mode. | |
241 This parameter can be a value of @ref TIM_LL_EC_OCMODE. | |
242 | |
243 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ | |
244 | |
245 uint32_t OCState; /*!< Specifies the TIM Output Compare state. | |
246 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. | |
247 | |
248 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ | |
249 | |
250 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. | |
251 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. | |
252 | |
253 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ | |
254 | |
255 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. | |
256 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. | |
257 | |
258 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ | |
259 | |
260 uint32_t OCPolarity; /*!< Specifies the output polarity. | |
261 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. | |
262 | |
263 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ | |
264 | |
265 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. | |
266 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. | |
267 | |
268 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ | |
269 | |
270 | |
271 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. | |
272 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. | |
273 | |
274 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ | |
275 | |
276 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. | |
277 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. | |
278 | |
279 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ | |
280 } LL_TIM_OC_InitTypeDef; | |
281 | |
282 /** | |
283 * @brief TIM Input Capture configuration structure definition. | |
284 */ | |
285 | |
286 typedef struct | |
287 { | |
288 | |
289 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. | |
290 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. | |
291 | |
292 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ | |
293 | |
294 uint32_t ICActiveInput; /*!< Specifies the input. | |
295 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. | |
296 | |
297 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ | |
298 | |
299 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. | |
300 This parameter can be a value of @ref TIM_LL_EC_ICPSC. | |
301 | |
302 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ | |
303 | |
304 uint32_t ICFilter; /*!< Specifies the input capture filter. | |
305 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. | |
306 | |
307 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ | |
308 } LL_TIM_IC_InitTypeDef; | |
309 | |
310 | |
311 /** | |
312 * @brief TIM Encoder interface configuration structure definition. | |
313 */ | |
314 typedef struct | |
315 { | |
316 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). | |
317 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. | |
318 | |
319 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ | |
320 | |
321 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. | |
322 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. | |
323 | |
324 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ | |
325 | |
326 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source | |
327 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. | |
328 | |
329 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ | |
330 | |
331 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. | |
332 This parameter can be a value of @ref TIM_LL_EC_ICPSC. | |
333 | |
334 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ | |
335 | |
336 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. | |
337 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. | |
338 | |
339 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ | |
340 | |
341 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. | |
342 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. | |
343 | |
344 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ | |
345 | |
346 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source | |
347 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. | |
348 | |
349 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ | |
350 | |
351 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. | |
352 This parameter can be a value of @ref TIM_LL_EC_ICPSC. | |
353 | |
354 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ | |
355 | |
356 uint32_t IC2Filter; /*!< Specifies the TI2 input filter. | |
357 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. | |
358 | |
359 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ | |
360 | |
361 } LL_TIM_ENCODER_InitTypeDef; | |
362 | |
363 /** | |
364 * @brief TIM Hall sensor interface configuration structure definition. | |
365 */ | |
366 typedef struct | |
367 { | |
368 | |
369 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. | |
370 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. | |
371 | |
372 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ | |
373 | |
374 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. | |
375 Prescaler must be set to get a maximum counter period longer than the | |
376 time interval between 2 consecutive changes on the Hall inputs. | |
377 This parameter can be a value of @ref TIM_LL_EC_ICPSC. | |
378 | |
379 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ | |
380 | |
381 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. | |
382 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. | |
383 | |
384 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ | |
385 | |
386 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. | |
387 A positive pulse (TRGO event) is generated with a programmable delay every time | |
388 a change occurs on the Hall inputs. | |
389 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. | |
390 | |
391 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ | |
392 } LL_TIM_HALLSENSOR_InitTypeDef; | |
393 | |
394 /** | |
395 * @brief BDTR (Break and Dead Time) structure definition | |
396 */ | |
397 typedef struct | |
398 { | |
399 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. | |
400 This parameter can be a value of @ref TIM_LL_EC_OSSR | |
401 | |
402 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() | |
403 | |
404 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ | |
405 | |
406 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. | |
407 This parameter can be a value of @ref TIM_LL_EC_OSSI | |
408 | |
409 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() | |
410 | |
411 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ | |
412 | |
413 uint32_t LockLevel; /*!< Specifies the LOCK level parameters. | |
414 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL | |
415 | |
416 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register | |
417 has been written, their content is frozen until the next reset.*/ | |
418 | |
419 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the | |
420 switching-on of the outputs. | |
421 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. | |
422 | |
423 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() | |
424 | |
425 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ | |
426 | |
427 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. | |
428 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE | |
429 | |
430 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() | |
431 | |
432 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ | |
433 | |
434 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. | |
435 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY | |
436 | |
437 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() | |
438 | |
439 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ | |
440 | |
441 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. | |
442 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE | |
443 | |
444 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() | |
445 | |
446 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ | |
447 } LL_TIM_BDTR_InitTypeDef; | |
448 | |
449 /** | |
450 * @} | |
451 */ | |
452 #endif /* USE_FULL_LL_DRIVER */ | |
453 | |
454 /* Exported constants --------------------------------------------------------*/ | |
455 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants | |
456 * @{ | |
457 */ | |
458 | |
459 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines | |
460 * @brief Flags defines which can be used with LL_TIM_ReadReg function. | |
461 * @{ | |
462 */ | |
463 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ | |
464 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ | |
465 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ | |
466 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ | |
467 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ | |
468 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ | |
469 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ | |
470 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ | |
471 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ | |
472 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ | |
473 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ | |
474 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ | |
475 /** | |
476 * @} | |
477 */ | |
478 | |
479 #if defined(USE_FULL_LL_DRIVER) | |
480 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable | |
481 * @{ | |
482 */ | |
483 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ | |
484 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ | |
485 /** | |
486 * @} | |
487 */ | |
488 | |
489 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable | |
490 * @{ | |
491 */ | |
492 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ | |
493 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ | |
494 /** | |
495 * @} | |
496 */ | |
497 #endif /* USE_FULL_LL_DRIVER */ | |
498 | |
499 /** @defgroup TIM_LL_EC_IT IT Defines | |
500 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. | |
501 * @{ | |
502 */ | |
503 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ | |
504 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ | |
505 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ | |
506 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ | |
507 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ | |
508 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ | |
509 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ | |
510 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ | |
511 /** | |
512 * @} | |
513 */ | |
514 | |
515 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source | |
516 * @{ | |
517 */ | |
518 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ | |
519 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ | |
520 /** | |
521 * @} | |
522 */ | |
523 | |
524 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode | |
525 * @{ | |
526 */ | |
527 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ | |
528 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ | |
529 /** | |
530 * @} | |
531 */ | |
532 | |
533 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode | |
534 * @{ | |
535 */ | |
536 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ | |
537 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ | |
538 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ | |
539 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ | |
540 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ | |
541 /** | |
542 * @} | |
543 */ | |
544 | |
545 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division | |
546 * @{ | |
547 */ | |
548 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ | |
549 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ | |
550 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ | |
551 /** | |
552 * @} | |
553 */ | |
554 | |
555 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction | |
556 * @{ | |
557 */ | |
558 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ | |
559 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ | |
560 /** | |
561 * @} | |
562 */ | |
563 | |
564 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source | |
565 * @{ | |
566 */ | |
567 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ | |
568 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ | |
569 /** | |
570 * @} | |
571 */ | |
572 | |
573 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request | |
574 * @{ | |
575 */ | |
576 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ | |
577 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ | |
578 /** | |
579 * @} | |
580 */ | |
581 | |
582 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level | |
583 * @{ | |
584 */ | |
585 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ | |
586 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ | |
587 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ | |
588 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ | |
589 /** | |
590 * @} | |
591 */ | |
592 | |
593 /** @defgroup TIM_LL_EC_CHANNEL Channel | |
594 * @{ | |
595 */ | |
596 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ | |
597 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ | |
598 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ | |
599 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ | |
600 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ | |
601 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ | |
602 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ | |
603 /** | |
604 * @} | |
605 */ | |
606 | |
607 #if defined(USE_FULL_LL_DRIVER) | |
608 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State | |
609 * @{ | |
610 */ | |
611 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ | |
612 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ | |
613 /** | |
614 * @} | |
615 */ | |
616 #endif /* USE_FULL_LL_DRIVER */ | |
617 | |
618 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode | |
619 * @{ | |
620 */ | |
621 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ | |
622 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ | |
623 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ | |
624 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ | |
625 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ | |
626 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ | |
627 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ | |
628 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ | |
629 /** | |
630 * @} | |
631 */ | |
632 | |
633 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity | |
634 * @{ | |
635 */ | |
636 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ | |
637 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ | |
638 /** | |
639 * @} | |
640 */ | |
641 | |
642 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State | |
643 * @{ | |
644 */ | |
645 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ | |
646 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ | |
647 /** | |
648 * @} | |
649 */ | |
650 | |
651 | |
652 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection | |
653 * @{ | |
654 */ | |
655 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ | |
656 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ | |
657 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ | |
658 /** | |
659 * @} | |
660 */ | |
661 | |
662 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler | |
663 * @{ | |
664 */ | |
665 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ | |
666 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ | |
667 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ | |
668 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ | |
669 /** | |
670 * @} | |
671 */ | |
672 | |
673 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter | |
674 * @{ | |
675 */ | |
676 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ | |
677 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ | |
678 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ | |
679 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ | |
680 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ | |
681 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ | |
682 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ | |
683 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ | |
684 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ | |
685 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ | |
686 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ | |
687 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ | |
688 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ | |
689 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ | |
690 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ | |
691 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ | |
692 /** | |
693 * @} | |
694 */ | |
695 | |
696 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity | |
697 * @{ | |
698 */ | |
699 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ | |
700 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ | |
701 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ | |
702 /** | |
703 * @} | |
704 */ | |
705 | |
706 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source | |
707 * @{ | |
708 */ | |
709 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ | |
710 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/ | |
711 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ | |
712 /** | |
713 * @} | |
714 */ | |
715 | |
716 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode | |
717 * @{ | |
718 */ | |
719 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ | |
720 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ | |
721 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ | |
722 /** | |
723 * @} | |
724 */ | |
725 | |
726 /** @defgroup TIM_LL_EC_TRGO Trigger Output | |
727 * @{ | |
728 */ | |
729 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ | |
730 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ | |
731 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ | |
732 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ | |
733 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ | |
734 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ | |
735 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ | |
736 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ | |
737 /** | |
738 * @} | |
739 */ | |
740 | |
741 | |
742 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode | |
743 * @{ | |
744 */ | |
745 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ | |
746 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ | |
747 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ | |
748 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ | |
749 /** | |
750 * @} | |
751 */ | |
752 | |
753 /** @defgroup TIM_LL_EC_TS Trigger Selection | |
754 * @{ | |
755 */ | |
756 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ | |
757 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ | |
758 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ | |
759 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ | |
760 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ | |
761 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ | |
762 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ | |
763 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ | |
764 /** | |
765 * @} | |
766 */ | |
767 | |
768 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity | |
769 * @{ | |
770 */ | |
771 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ | |
772 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ | |
773 /** | |
774 * @} | |
775 */ | |
776 | |
777 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler | |
778 * @{ | |
779 */ | |
780 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ | |
781 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ | |
782 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ | |
783 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ | |
784 /** | |
785 * @} | |
786 */ | |
787 | |
788 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter | |
789 * @{ | |
790 */ | |
791 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ | |
792 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ | |
793 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ | |
794 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ | |
795 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ | |
796 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ | |
797 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ | |
798 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ | |
799 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ | |
800 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ | |
801 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ | |
802 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ | |
803 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ | |
804 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ | |
805 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ | |
806 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ | |
807 /** | |
808 * @} | |
809 */ | |
810 | |
811 | |
812 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity | |
813 * @{ | |
814 */ | |
815 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ | |
816 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ | |
817 /** | |
818 * @} | |
819 */ | |
820 | |
821 | |
822 | |
823 | |
824 /** @defgroup TIM_LL_EC_OSSI OSSI | |
825 * @{ | |
826 */ | |
827 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ | |
828 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ | |
829 /** | |
830 * @} | |
831 */ | |
832 | |
833 /** @defgroup TIM_LL_EC_OSSR OSSR | |
834 * @{ | |
835 */ | |
836 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ | |
837 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ | |
838 /** | |
839 * @} | |
840 */ | |
841 | |
842 | |
843 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address | |
844 * @{ | |
845 */ | |
846 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ | |
847 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ | |
848 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ | |
849 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ | |
850 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ | |
851 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ | |
852 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ | |
853 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ | |
854 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ | |
855 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ | |
856 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ | |
857 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ | |
858 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ | |
859 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ | |
860 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ | |
861 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ | |
862 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ | |
863 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ | |
864 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) | |
865 /** | |
866 * @} | |
867 */ | |
868 | |
869 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length | |
870 * @{ | |
871 */ | |
872 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ | |
873 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ | |
874 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ | |
875 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ | |
876 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ | |
877 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ | |
878 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ | |
879 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ | |
880 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ | |
881 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ | |
882 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ | |
883 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ | |
884 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ | |
885 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ | |
886 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ | |
887 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ | |
888 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ | |
889 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ | |
890 /** | |
891 * @} | |
892 */ | |
893 | |
894 | |
895 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8 | |
896 * @{ | |
897 */ | |
898 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */ | |
899 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */ | |
900 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */ | |
901 /** | |
902 * @} | |
903 */ | |
904 | |
905 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap | |
906 * @{ | |
907 */ | |
908 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */ | |
909 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */ | |
910 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */ | |
911 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */ | |
912 /** | |
913 * @} | |
914 */ | |
915 | |
916 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap | |
917 * @{ | |
918 */ | |
919 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */ | |
920 #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */ | |
921 #define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */ | |
922 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */ | |
923 /** | |
924 * @} | |
925 */ | |
926 | |
927 | |
928 /** | |
929 * @} | |
930 */ | |
931 | |
932 /* Exported macro ------------------------------------------------------------*/ | |
933 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros | |
934 * @{ | |
935 */ | |
936 | |
937 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros | |
938 * @{ | |
939 */ | |
940 /** | |
941 * @brief Write a value in TIM register. | |
942 * @param __INSTANCE__ TIM Instance | |
943 * @param __REG__ Register to be written | |
944 * @param __VALUE__ Value to be written in the register | |
945 * @retval None | |
946 */ | |
947 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) | |
948 | |
949 /** | |
950 * @brief Read a value in TIM register. | |
951 * @param __INSTANCE__ TIM Instance | |
952 * @param __REG__ Register to be read | |
953 * @retval Register value | |
954 */ | |
955 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) | |
956 /** | |
957 * @} | |
958 */ | |
959 | |
960 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros | |
961 * @{ | |
962 */ | |
963 | |
964 /** | |
965 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. | |
966 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); | |
967 * @param __TIMCLK__ timer input clock frequency (in Hz) | |
968 * @param __CKD__ This parameter can be one of the following values: | |
969 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 | |
970 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 | |
971 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 | |
972 * @param __DT__ deadtime duration (in ns) | |
973 * @retval DTG[0:7] | |
974 */ | |
975 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ | |
976 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ | |
977 (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ | |
978 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ | |
979 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ | |
980 0U) | |
981 | |
982 /** | |
983 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. | |
984 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); | |
985 * @param __TIMCLK__ timer input clock frequency (in Hz) | |
986 * @param __CNTCLK__ counter clock frequency (in Hz) | |
987 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) | |
988 */ | |
989 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ | |
990 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U | |
991 | |
992 /** | |
993 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. | |
994 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); | |
995 * @param __TIMCLK__ timer input clock frequency (in Hz) | |
996 * @param __PSC__ prescaler | |
997 * @param __FREQ__ output signal frequency (in Hz) | |
998 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) | |
999 */ | |
1000 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ | |
1001 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U | |
1002 | |
1003 /** | |
1004 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. | |
1005 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); | |
1006 * @param __TIMCLK__ timer input clock frequency (in Hz) | |
1007 * @param __PSC__ prescaler | |
1008 * @param __DELAY__ timer output compare active/inactive delay (in us) | |
1009 * @retval Compare value (between Min_Data=0 and Max_Data=65535) | |
1010 */ | |
1011 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ | |
1012 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ | |
1013 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) | |
1014 | |
1015 /** | |
1016 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). | |
1017 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); | |
1018 * @param __TIMCLK__ timer input clock frequency (in Hz) | |
1019 * @param __PSC__ prescaler | |
1020 * @param __DELAY__ timer output compare active/inactive delay (in us) | |
1021 * @param __PULSE__ pulse duration (in us) | |
1022 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) | |
1023 */ | |
1024 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ | |
1025 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ | |
1026 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) | |
1027 | |
1028 /** | |
1029 * @brief HELPER macro retrieving the ratio of the input capture prescaler | |
1030 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); | |
1031 * @param __ICPSC__ This parameter can be one of the following values: | |
1032 * @arg @ref LL_TIM_ICPSC_DIV1 | |
1033 * @arg @ref LL_TIM_ICPSC_DIV2 | |
1034 * @arg @ref LL_TIM_ICPSC_DIV4 | |
1035 * @arg @ref LL_TIM_ICPSC_DIV8 | |
1036 * @retval Input capture prescaler ratio (1, 2, 4 or 8) | |
1037 */ | |
1038 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ | |
1039 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) | |
1040 | |
1041 | |
1042 /** | |
1043 * @} | |
1044 */ | |
1045 | |
1046 | |
1047 /** | |
1048 * @} | |
1049 */ | |
1050 | |
1051 /* Exported functions --------------------------------------------------------*/ | |
1052 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions | |
1053 * @{ | |
1054 */ | |
1055 | |
1056 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration | |
1057 * @{ | |
1058 */ | |
1059 /** | |
1060 * @brief Enable timer counter. | |
1061 * @rmtoll CR1 CEN LL_TIM_EnableCounter | |
1062 * @param TIMx Timer instance | |
1063 * @retval None | |
1064 */ | |
1065 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) | |
1066 { | |
1067 SET_BIT(TIMx->CR1, TIM_CR1_CEN); | |
1068 } | |
1069 | |
1070 /** | |
1071 * @brief Disable timer counter. | |
1072 * @rmtoll CR1 CEN LL_TIM_DisableCounter | |
1073 * @param TIMx Timer instance | |
1074 * @retval None | |
1075 */ | |
1076 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) | |
1077 { | |
1078 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); | |
1079 } | |
1080 | |
1081 /** | |
1082 * @brief Indicates whether the timer counter is enabled. | |
1083 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter | |
1084 * @param TIMx Timer instance | |
1085 * @retval State of bit (1 or 0). | |
1086 */ | |
1087 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) | |
1088 { | |
1089 return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); | |
1090 } | |
1091 | |
1092 /** | |
1093 * @brief Enable update event generation. | |
1094 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent | |
1095 * @param TIMx Timer instance | |
1096 * @retval None | |
1097 */ | |
1098 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) | |
1099 { | |
1100 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); | |
1101 } | |
1102 | |
1103 /** | |
1104 * @brief Disable update event generation. | |
1105 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent | |
1106 * @param TIMx Timer instance | |
1107 * @retval None | |
1108 */ | |
1109 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) | |
1110 { | |
1111 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); | |
1112 } | |
1113 | |
1114 /** | |
1115 * @brief Indicates whether update event generation is enabled. | |
1116 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent | |
1117 * @param TIMx Timer instance | |
1118 * @retval Inverted state of bit (0 or 1). | |
1119 */ | |
1120 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) | |
1121 { | |
1122 return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); | |
1123 } | |
1124 | |
1125 /** | |
1126 * @brief Set update event source | |
1127 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events | |
1128 * generate an update interrupt or DMA request if enabled: | |
1129 * - Counter overflow/underflow | |
1130 * - Setting the UG bit | |
1131 * - Update generation through the slave mode controller | |
1132 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter | |
1133 * overflow/underflow generates an update interrupt or DMA request if enabled. | |
1134 * @rmtoll CR1 URS LL_TIM_SetUpdateSource | |
1135 * @param TIMx Timer instance | |
1136 * @param UpdateSource This parameter can be one of the following values: | |
1137 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR | |
1138 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER | |
1139 * @retval None | |
1140 */ | |
1141 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) | |
1142 { | |
1143 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); | |
1144 } | |
1145 | |
1146 /** | |
1147 * @brief Get actual event update source | |
1148 * @rmtoll CR1 URS LL_TIM_GetUpdateSource | |
1149 * @param TIMx Timer instance | |
1150 * @retval Returned value can be one of the following values: | |
1151 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR | |
1152 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER | |
1153 */ | |
1154 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) | |
1155 { | |
1156 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); | |
1157 } | |
1158 | |
1159 /** | |
1160 * @brief Set one pulse mode (one shot v.s. repetitive). | |
1161 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode | |
1162 * @param TIMx Timer instance | |
1163 * @param OnePulseMode This parameter can be one of the following values: | |
1164 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE | |
1165 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE | |
1166 * @retval None | |
1167 */ | |
1168 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) | |
1169 { | |
1170 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); | |
1171 } | |
1172 | |
1173 /** | |
1174 * @brief Get actual one pulse mode. | |
1175 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode | |
1176 * @param TIMx Timer instance | |
1177 * @retval Returned value can be one of the following values: | |
1178 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE | |
1179 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE | |
1180 */ | |
1181 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) | |
1182 { | |
1183 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); | |
1184 } | |
1185 | |
1186 /** | |
1187 * @brief Set the timer counter counting mode. | |
1188 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to | |
1189 * check whether or not the counter mode selection feature is supported | |
1190 * by a timer instance. | |
1191 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n | |
1192 * CR1 CMS LL_TIM_SetCounterMode | |
1193 * @param TIMx Timer instance | |
1194 * @param CounterMode This parameter can be one of the following values: | |
1195 * @arg @ref LL_TIM_COUNTERMODE_UP | |
1196 * @arg @ref LL_TIM_COUNTERMODE_DOWN | |
1197 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP | |
1198 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN | |
1199 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN | |
1200 * @retval None | |
1201 */ | |
1202 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) | |
1203 { | |
1204 MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); | |
1205 } | |
1206 | |
1207 /** | |
1208 * @brief Get actual counter mode. | |
1209 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to | |
1210 * check whether or not the counter mode selection feature is supported | |
1211 * by a timer instance. | |
1212 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n | |
1213 * CR1 CMS LL_TIM_GetCounterMode | |
1214 * @param TIMx Timer instance | |
1215 * @retval Returned value can be one of the following values: | |
1216 * @arg @ref LL_TIM_COUNTERMODE_UP | |
1217 * @arg @ref LL_TIM_COUNTERMODE_DOWN | |
1218 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP | |
1219 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN | |
1220 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN | |
1221 */ | |
1222 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) | |
1223 { | |
1224 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); | |
1225 } | |
1226 | |
1227 /** | |
1228 * @brief Enable auto-reload (ARR) preload. | |
1229 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload | |
1230 * @param TIMx Timer instance | |
1231 * @retval None | |
1232 */ | |
1233 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) | |
1234 { | |
1235 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); | |
1236 } | |
1237 | |
1238 /** | |
1239 * @brief Disable auto-reload (ARR) preload. | |
1240 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload | |
1241 * @param TIMx Timer instance | |
1242 * @retval None | |
1243 */ | |
1244 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) | |
1245 { | |
1246 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); | |
1247 } | |
1248 | |
1249 /** | |
1250 * @brief Indicates whether auto-reload (ARR) preload is enabled. | |
1251 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload | |
1252 * @param TIMx Timer instance | |
1253 * @retval State of bit (1 or 0). | |
1254 */ | |
1255 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) | |
1256 { | |
1257 return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); | |
1258 } | |
1259 | |
1260 /** | |
1261 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. | |
1262 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check | |
1263 * whether or not the clock division feature is supported by the timer | |
1264 * instance. | |
1265 * @rmtoll CR1 CKD LL_TIM_SetClockDivision | |
1266 * @param TIMx Timer instance | |
1267 * @param ClockDivision This parameter can be one of the following values: | |
1268 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 | |
1269 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 | |
1270 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 | |
1271 * @retval None | |
1272 */ | |
1273 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) | |
1274 { | |
1275 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); | |
1276 } | |
1277 | |
1278 /** | |
1279 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. | |
1280 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check | |
1281 * whether or not the clock division feature is supported by the timer | |
1282 * instance. | |
1283 * @rmtoll CR1 CKD LL_TIM_GetClockDivision | |
1284 * @param TIMx Timer instance | |
1285 * @retval Returned value can be one of the following values: | |
1286 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 | |
1287 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 | |
1288 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 | |
1289 */ | |
1290 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) | |
1291 { | |
1292 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); | |
1293 } | |
1294 | |
1295 /** | |
1296 * @brief Set the counter value. | |
1297 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
1298 * whether or not a timer instance supports a 32 bits counter. | |
1299 * @rmtoll CNT CNT LL_TIM_SetCounter | |
1300 * @param TIMx Timer instance | |
1301 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) | |
1302 * @retval None | |
1303 */ | |
1304 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) | |
1305 { | |
1306 WRITE_REG(TIMx->CNT, Counter); | |
1307 } | |
1308 | |
1309 /** | |
1310 * @brief Get the counter value. | |
1311 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
1312 * whether or not a timer instance supports a 32 bits counter. | |
1313 * @rmtoll CNT CNT LL_TIM_GetCounter | |
1314 * @param TIMx Timer instance | |
1315 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) | |
1316 */ | |
1317 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) | |
1318 { | |
1319 return (uint32_t)(READ_REG(TIMx->CNT)); | |
1320 } | |
1321 | |
1322 /** | |
1323 * @brief Get the current direction of the counter | |
1324 * @rmtoll CR1 DIR LL_TIM_GetDirection | |
1325 * @param TIMx Timer instance | |
1326 * @retval Returned value can be one of the following values: | |
1327 * @arg @ref LL_TIM_COUNTERDIRECTION_UP | |
1328 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN | |
1329 */ | |
1330 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) | |
1331 { | |
1332 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); | |
1333 } | |
1334 | |
1335 /** | |
1336 * @brief Set the prescaler value. | |
1337 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). | |
1338 * @note The prescaler can be changed on the fly as this control register is buffered. The new | |
1339 * prescaler ratio is taken into account at the next update event. | |
1340 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter | |
1341 * @rmtoll PSC PSC LL_TIM_SetPrescaler | |
1342 * @param TIMx Timer instance | |
1343 * @param Prescaler between Min_Data=0 and Max_Data=65535 | |
1344 * @retval None | |
1345 */ | |
1346 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) | |
1347 { | |
1348 WRITE_REG(TIMx->PSC, Prescaler); | |
1349 } | |
1350 | |
1351 /** | |
1352 * @brief Get the prescaler value. | |
1353 * @rmtoll PSC PSC LL_TIM_GetPrescaler | |
1354 * @param TIMx Timer instance | |
1355 * @retval Prescaler value between Min_Data=0 and Max_Data=65535 | |
1356 */ | |
1357 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) | |
1358 { | |
1359 return (uint32_t)(READ_REG(TIMx->PSC)); | |
1360 } | |
1361 | |
1362 /** | |
1363 * @brief Set the auto-reload value. | |
1364 * @note The counter is blocked while the auto-reload value is null. | |
1365 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
1366 * whether or not a timer instance supports a 32 bits counter. | |
1367 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter | |
1368 * @rmtoll ARR ARR LL_TIM_SetAutoReload | |
1369 * @param TIMx Timer instance | |
1370 * @param AutoReload between Min_Data=0 and Max_Data=65535 | |
1371 * @retval None | |
1372 */ | |
1373 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) | |
1374 { | |
1375 WRITE_REG(TIMx->ARR, AutoReload); | |
1376 } | |
1377 | |
1378 /** | |
1379 * @brief Get the auto-reload value. | |
1380 * @rmtoll ARR ARR LL_TIM_GetAutoReload | |
1381 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
1382 * whether or not a timer instance supports a 32 bits counter. | |
1383 * @param TIMx Timer instance | |
1384 * @retval Auto-reload value | |
1385 */ | |
1386 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) | |
1387 { | |
1388 return (uint32_t)(READ_REG(TIMx->ARR)); | |
1389 } | |
1390 | |
1391 /** | |
1392 * @brief Set the repetition counter value. | |
1393 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check | |
1394 * whether or not a timer instance supports a repetition counter. | |
1395 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter | |
1396 * @param TIMx Timer instance | |
1397 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 | |
1398 * @retval None | |
1399 */ | |
1400 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) | |
1401 { | |
1402 WRITE_REG(TIMx->RCR, RepetitionCounter); | |
1403 } | |
1404 | |
1405 /** | |
1406 * @brief Get the repetition counter value. | |
1407 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check | |
1408 * whether or not a timer instance supports a repetition counter. | |
1409 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter | |
1410 * @param TIMx Timer instance | |
1411 * @retval Repetition counter value | |
1412 */ | |
1413 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) | |
1414 { | |
1415 return (uint32_t)(READ_REG(TIMx->RCR)); | |
1416 } | |
1417 | |
1418 /** | |
1419 * @} | |
1420 */ | |
1421 | |
1422 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration | |
1423 * @{ | |
1424 */ | |
1425 /** | |
1426 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. | |
1427 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, | |
1428 * they are updated only when a commutation event (COM) occurs. | |
1429 * @note Only on channels that have a complementary output. | |
1430 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check | |
1431 * whether or not a timer instance is able to generate a commutation event. | |
1432 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload | |
1433 * @param TIMx Timer instance | |
1434 * @retval None | |
1435 */ | |
1436 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) | |
1437 { | |
1438 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); | |
1439 } | |
1440 | |
1441 /** | |
1442 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. | |
1443 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check | |
1444 * whether or not a timer instance is able to generate a commutation event. | |
1445 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload | |
1446 * @param TIMx Timer instance | |
1447 * @retval None | |
1448 */ | |
1449 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) | |
1450 { | |
1451 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); | |
1452 } | |
1453 | |
1454 /** | |
1455 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). | |
1456 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check | |
1457 * whether or not a timer instance is able to generate a commutation event. | |
1458 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate | |
1459 * @param TIMx Timer instance | |
1460 * @param CCUpdateSource This parameter can be one of the following values: | |
1461 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY | |
1462 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI | |
1463 * @retval None | |
1464 */ | |
1465 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) | |
1466 { | |
1467 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); | |
1468 } | |
1469 | |
1470 /** | |
1471 * @brief Set the trigger of the capture/compare DMA request. | |
1472 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger | |
1473 * @param TIMx Timer instance | |
1474 * @param DMAReqTrigger This parameter can be one of the following values: | |
1475 * @arg @ref LL_TIM_CCDMAREQUEST_CC | |
1476 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE | |
1477 * @retval None | |
1478 */ | |
1479 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) | |
1480 { | |
1481 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); | |
1482 } | |
1483 | |
1484 /** | |
1485 * @brief Get actual trigger of the capture/compare DMA request. | |
1486 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger | |
1487 * @param TIMx Timer instance | |
1488 * @retval Returned value can be one of the following values: | |
1489 * @arg @ref LL_TIM_CCDMAREQUEST_CC | |
1490 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE | |
1491 */ | |
1492 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) | |
1493 { | |
1494 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); | |
1495 } | |
1496 | |
1497 /** | |
1498 * @brief Set the lock level to freeze the | |
1499 * configuration of several capture/compare parameters. | |
1500 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
1501 * the lock mechanism is supported by a timer instance. | |
1502 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel | |
1503 * @param TIMx Timer instance | |
1504 * @param LockLevel This parameter can be one of the following values: | |
1505 * @arg @ref LL_TIM_LOCKLEVEL_OFF | |
1506 * @arg @ref LL_TIM_LOCKLEVEL_1 | |
1507 * @arg @ref LL_TIM_LOCKLEVEL_2 | |
1508 * @arg @ref LL_TIM_LOCKLEVEL_3 | |
1509 * @retval None | |
1510 */ | |
1511 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) | |
1512 { | |
1513 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); | |
1514 } | |
1515 | |
1516 /** | |
1517 * @brief Enable capture/compare channels. | |
1518 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n | |
1519 * CCER CC1NE LL_TIM_CC_EnableChannel\n | |
1520 * CCER CC2E LL_TIM_CC_EnableChannel\n | |
1521 * CCER CC2NE LL_TIM_CC_EnableChannel\n | |
1522 * CCER CC3E LL_TIM_CC_EnableChannel\n | |
1523 * CCER CC3NE LL_TIM_CC_EnableChannel\n | |
1524 * CCER CC4E LL_TIM_CC_EnableChannel | |
1525 * @param TIMx Timer instance | |
1526 * @param Channels This parameter can be a combination of the following values: | |
1527 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1528 * @arg @ref LL_TIM_CHANNEL_CH1N | |
1529 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1530 * @arg @ref LL_TIM_CHANNEL_CH2N | |
1531 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1532 * @arg @ref LL_TIM_CHANNEL_CH3N | |
1533 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1534 * @retval None | |
1535 */ | |
1536 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) | |
1537 { | |
1538 SET_BIT(TIMx->CCER, Channels); | |
1539 } | |
1540 | |
1541 /** | |
1542 * @brief Disable capture/compare channels. | |
1543 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n | |
1544 * CCER CC1NE LL_TIM_CC_DisableChannel\n | |
1545 * CCER CC2E LL_TIM_CC_DisableChannel\n | |
1546 * CCER CC2NE LL_TIM_CC_DisableChannel\n | |
1547 * CCER CC3E LL_TIM_CC_DisableChannel\n | |
1548 * CCER CC3NE LL_TIM_CC_DisableChannel\n | |
1549 * CCER CC4E LL_TIM_CC_DisableChannel | |
1550 * @param TIMx Timer instance | |
1551 * @param Channels This parameter can be a combination of the following values: | |
1552 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1553 * @arg @ref LL_TIM_CHANNEL_CH1N | |
1554 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1555 * @arg @ref LL_TIM_CHANNEL_CH2N | |
1556 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1557 * @arg @ref LL_TIM_CHANNEL_CH3N | |
1558 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1559 * @retval None | |
1560 */ | |
1561 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) | |
1562 { | |
1563 CLEAR_BIT(TIMx->CCER, Channels); | |
1564 } | |
1565 | |
1566 /** | |
1567 * @brief Indicate whether channel(s) is(are) enabled. | |
1568 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n | |
1569 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n | |
1570 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n | |
1571 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n | |
1572 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n | |
1573 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n | |
1574 * CCER CC4E LL_TIM_CC_IsEnabledChannel | |
1575 * @param TIMx Timer instance | |
1576 * @param Channels This parameter can be a combination of the following values: | |
1577 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1578 * @arg @ref LL_TIM_CHANNEL_CH1N | |
1579 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1580 * @arg @ref LL_TIM_CHANNEL_CH2N | |
1581 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1582 * @arg @ref LL_TIM_CHANNEL_CH3N | |
1583 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1584 * @retval State of bit (1 or 0). | |
1585 */ | |
1586 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) | |
1587 { | |
1588 return (READ_BIT(TIMx->CCER, Channels) == (Channels)); | |
1589 } | |
1590 | |
1591 /** | |
1592 * @} | |
1593 */ | |
1594 | |
1595 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration | |
1596 * @{ | |
1597 */ | |
1598 /** | |
1599 * @brief Configure an output channel. | |
1600 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n | |
1601 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n | |
1602 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n | |
1603 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n | |
1604 * CCER CC1P LL_TIM_OC_ConfigOutput\n | |
1605 * CCER CC2P LL_TIM_OC_ConfigOutput\n | |
1606 * CCER CC3P LL_TIM_OC_ConfigOutput\n | |
1607 * CCER CC4P LL_TIM_OC_ConfigOutput\n | |
1608 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n | |
1609 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n | |
1610 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n | |
1611 * CR2 OIS4 LL_TIM_OC_ConfigOutput | |
1612 * @param TIMx Timer instance | |
1613 * @param Channel This parameter can be one of the following values: | |
1614 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1615 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1616 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1617 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1618 * @param Configuration This parameter must be a combination of all the following values: | |
1619 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW | |
1620 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH | |
1621 * @retval None | |
1622 */ | |
1623 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) | |
1624 { | |
1625 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1626 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1627 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); | |
1628 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), | |
1629 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); | |
1630 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), | |
1631 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); | |
1632 } | |
1633 | |
1634 /** | |
1635 * @brief Define the behavior of the output reference signal OCxREF from which | |
1636 * OCx and OCxN (when relevant) are derived. | |
1637 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n | |
1638 * CCMR1 OC2M LL_TIM_OC_SetMode\n | |
1639 * CCMR2 OC3M LL_TIM_OC_SetMode\n | |
1640 * CCMR2 OC4M LL_TIM_OC_SetMode | |
1641 * @param TIMx Timer instance | |
1642 * @param Channel This parameter can be one of the following values: | |
1643 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1644 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1645 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1646 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1647 * @param Mode This parameter can be one of the following values: | |
1648 * @arg @ref LL_TIM_OCMODE_FROZEN | |
1649 * @arg @ref LL_TIM_OCMODE_ACTIVE | |
1650 * @arg @ref LL_TIM_OCMODE_INACTIVE | |
1651 * @arg @ref LL_TIM_OCMODE_TOGGLE | |
1652 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE | |
1653 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE | |
1654 * @arg @ref LL_TIM_OCMODE_PWM1 | |
1655 * @arg @ref LL_TIM_OCMODE_PWM2 | |
1656 * @retval None | |
1657 */ | |
1658 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) | |
1659 { | |
1660 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1661 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1662 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); | |
1663 } | |
1664 | |
1665 /** | |
1666 * @brief Get the output compare mode of an output channel. | |
1667 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n | |
1668 * CCMR1 OC2M LL_TIM_OC_GetMode\n | |
1669 * CCMR2 OC3M LL_TIM_OC_GetMode\n | |
1670 * CCMR2 OC4M LL_TIM_OC_GetMode | |
1671 * @param TIMx Timer instance | |
1672 * @param Channel This parameter can be one of the following values: | |
1673 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1674 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1675 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1676 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1677 * @retval Returned value can be one of the following values: | |
1678 * @arg @ref LL_TIM_OCMODE_FROZEN | |
1679 * @arg @ref LL_TIM_OCMODE_ACTIVE | |
1680 * @arg @ref LL_TIM_OCMODE_INACTIVE | |
1681 * @arg @ref LL_TIM_OCMODE_TOGGLE | |
1682 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE | |
1683 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE | |
1684 * @arg @ref LL_TIM_OCMODE_PWM1 | |
1685 * @arg @ref LL_TIM_OCMODE_PWM2 | |
1686 */ | |
1687 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) | |
1688 { | |
1689 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1690 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1691 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); | |
1692 } | |
1693 | |
1694 /** | |
1695 * @brief Set the polarity of an output channel. | |
1696 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n | |
1697 * CCER CC1NP LL_TIM_OC_SetPolarity\n | |
1698 * CCER CC2P LL_TIM_OC_SetPolarity\n | |
1699 * CCER CC2NP LL_TIM_OC_SetPolarity\n | |
1700 * CCER CC3P LL_TIM_OC_SetPolarity\n | |
1701 * CCER CC3NP LL_TIM_OC_SetPolarity\n | |
1702 * CCER CC4P LL_TIM_OC_SetPolarity | |
1703 * @param TIMx Timer instance | |
1704 * @param Channel This parameter can be one of the following values: | |
1705 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1706 * @arg @ref LL_TIM_CHANNEL_CH1N | |
1707 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1708 * @arg @ref LL_TIM_CHANNEL_CH2N | |
1709 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1710 * @arg @ref LL_TIM_CHANNEL_CH3N | |
1711 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1712 * @param Polarity This parameter can be one of the following values: | |
1713 * @arg @ref LL_TIM_OCPOLARITY_HIGH | |
1714 * @arg @ref LL_TIM_OCPOLARITY_LOW | |
1715 * @retval None | |
1716 */ | |
1717 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) | |
1718 { | |
1719 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1720 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); | |
1721 } | |
1722 | |
1723 /** | |
1724 * @brief Get the polarity of an output channel. | |
1725 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n | |
1726 * CCER CC1NP LL_TIM_OC_GetPolarity\n | |
1727 * CCER CC2P LL_TIM_OC_GetPolarity\n | |
1728 * CCER CC2NP LL_TIM_OC_GetPolarity\n | |
1729 * CCER CC3P LL_TIM_OC_GetPolarity\n | |
1730 * CCER CC3NP LL_TIM_OC_GetPolarity\n | |
1731 * CCER CC4P LL_TIM_OC_GetPolarity | |
1732 * @param TIMx Timer instance | |
1733 * @param Channel This parameter can be one of the following values: | |
1734 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1735 * @arg @ref LL_TIM_CHANNEL_CH1N | |
1736 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1737 * @arg @ref LL_TIM_CHANNEL_CH2N | |
1738 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1739 * @arg @ref LL_TIM_CHANNEL_CH3N | |
1740 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1741 * @retval Returned value can be one of the following values: | |
1742 * @arg @ref LL_TIM_OCPOLARITY_HIGH | |
1743 * @arg @ref LL_TIM_OCPOLARITY_LOW | |
1744 */ | |
1745 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) | |
1746 { | |
1747 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1748 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); | |
1749 } | |
1750 | |
1751 /** | |
1752 * @brief Set the IDLE state of an output channel | |
1753 * @note This function is significant only for the timer instances | |
1754 * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) | |
1755 * can be used to check whether or not a timer instance provides | |
1756 * a break input. | |
1757 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n | |
1758 * CR2 OIS1N LL_TIM_OC_SetIdleState\n | |
1759 * CR2 OIS2 LL_TIM_OC_SetIdleState\n | |
1760 * CR2 OIS2N LL_TIM_OC_SetIdleState\n | |
1761 * CR2 OIS3 LL_TIM_OC_SetIdleState\n | |
1762 * CR2 OIS3N LL_TIM_OC_SetIdleState\n | |
1763 * CR2 OIS4 LL_TIM_OC_SetIdleState | |
1764 * @param TIMx Timer instance | |
1765 * @param Channel This parameter can be one of the following values: | |
1766 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1767 * @arg @ref LL_TIM_CHANNEL_CH1N | |
1768 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1769 * @arg @ref LL_TIM_CHANNEL_CH2N | |
1770 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1771 * @arg @ref LL_TIM_CHANNEL_CH3N | |
1772 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1773 * @param IdleState This parameter can be one of the following values: | |
1774 * @arg @ref LL_TIM_OCIDLESTATE_LOW | |
1775 * @arg @ref LL_TIM_OCIDLESTATE_HIGH | |
1776 * @retval None | |
1777 */ | |
1778 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) | |
1779 { | |
1780 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1781 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); | |
1782 } | |
1783 | |
1784 /** | |
1785 * @brief Get the IDLE state of an output channel | |
1786 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n | |
1787 * CR2 OIS1N LL_TIM_OC_GetIdleState\n | |
1788 * CR2 OIS2 LL_TIM_OC_GetIdleState\n | |
1789 * CR2 OIS2N LL_TIM_OC_GetIdleState\n | |
1790 * CR2 OIS3 LL_TIM_OC_GetIdleState\n | |
1791 * CR2 OIS3N LL_TIM_OC_GetIdleState\n | |
1792 * CR2 OIS4 LL_TIM_OC_GetIdleState | |
1793 * @param TIMx Timer instance | |
1794 * @param Channel This parameter can be one of the following values: | |
1795 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1796 * @arg @ref LL_TIM_CHANNEL_CH1N | |
1797 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1798 * @arg @ref LL_TIM_CHANNEL_CH2N | |
1799 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1800 * @arg @ref LL_TIM_CHANNEL_CH3N | |
1801 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1802 * @retval Returned value can be one of the following values: | |
1803 * @arg @ref LL_TIM_OCIDLESTATE_LOW | |
1804 * @arg @ref LL_TIM_OCIDLESTATE_HIGH | |
1805 */ | |
1806 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) | |
1807 { | |
1808 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1809 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); | |
1810 } | |
1811 | |
1812 /** | |
1813 * @brief Enable fast mode for the output channel. | |
1814 * @note Acts only if the channel is configured in PWM1 or PWM2 mode. | |
1815 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n | |
1816 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n | |
1817 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n | |
1818 * CCMR2 OC4FE LL_TIM_OC_EnableFast | |
1819 * @param TIMx Timer instance | |
1820 * @param Channel This parameter can be one of the following values: | |
1821 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1822 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1823 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1824 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1825 * @retval None | |
1826 */ | |
1827 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) | |
1828 { | |
1829 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1830 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1831 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); | |
1832 | |
1833 } | |
1834 | |
1835 /** | |
1836 * @brief Disable fast mode for the output channel. | |
1837 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n | |
1838 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n | |
1839 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n | |
1840 * CCMR2 OC4FE LL_TIM_OC_DisableFast | |
1841 * @param TIMx Timer instance | |
1842 * @param Channel This parameter can be one of the following values: | |
1843 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1844 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1845 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1846 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1847 * @retval None | |
1848 */ | |
1849 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) | |
1850 { | |
1851 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1852 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1853 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); | |
1854 | |
1855 } | |
1856 | |
1857 /** | |
1858 * @brief Indicates whether fast mode is enabled for the output channel. | |
1859 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n | |
1860 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n | |
1861 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n | |
1862 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n | |
1863 * @param TIMx Timer instance | |
1864 * @param Channel This parameter can be one of the following values: | |
1865 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1866 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1867 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1868 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1869 * @retval State of bit (1 or 0). | |
1870 */ | |
1871 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) | |
1872 { | |
1873 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1874 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1875 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; | |
1876 return (READ_BIT(*pReg, bitfield) == bitfield); | |
1877 } | |
1878 | |
1879 /** | |
1880 * @brief Enable compare register (TIMx_CCRx) preload for the output channel. | |
1881 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n | |
1882 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n | |
1883 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n | |
1884 * CCMR2 OC4PE LL_TIM_OC_EnablePreload | |
1885 * @param TIMx Timer instance | |
1886 * @param Channel This parameter can be one of the following values: | |
1887 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1888 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1889 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1890 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1891 * @retval None | |
1892 */ | |
1893 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) | |
1894 { | |
1895 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1896 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1897 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); | |
1898 } | |
1899 | |
1900 /** | |
1901 * @brief Disable compare register (TIMx_CCRx) preload for the output channel. | |
1902 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n | |
1903 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n | |
1904 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n | |
1905 * CCMR2 OC4PE LL_TIM_OC_DisablePreload | |
1906 * @param TIMx Timer instance | |
1907 * @param Channel This parameter can be one of the following values: | |
1908 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1909 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1910 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1911 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1912 * @retval None | |
1913 */ | |
1914 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) | |
1915 { | |
1916 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1917 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1918 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); | |
1919 } | |
1920 | |
1921 /** | |
1922 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. | |
1923 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n | |
1924 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n | |
1925 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n | |
1926 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n | |
1927 * @param TIMx Timer instance | |
1928 * @param Channel This parameter can be one of the following values: | |
1929 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1930 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1931 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1932 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1933 * @retval State of bit (1 or 0). | |
1934 */ | |
1935 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) | |
1936 { | |
1937 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1938 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1939 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; | |
1940 return (READ_BIT(*pReg, bitfield) == bitfield); | |
1941 } | |
1942 | |
1943 /** | |
1944 * @brief Enable clearing the output channel on an external event. | |
1945 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. | |
1946 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether | |
1947 * or not a timer instance can clear the OCxREF signal on an external event. | |
1948 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n | |
1949 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n | |
1950 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n | |
1951 * CCMR2 OC4CE LL_TIM_OC_EnableClear | |
1952 * @param TIMx Timer instance | |
1953 * @param Channel This parameter can be one of the following values: | |
1954 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1955 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1956 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1957 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1958 * @retval None | |
1959 */ | |
1960 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) | |
1961 { | |
1962 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1963 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1964 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); | |
1965 } | |
1966 | |
1967 /** | |
1968 * @brief Disable clearing the output channel on an external event. | |
1969 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether | |
1970 * or not a timer instance can clear the OCxREF signal on an external event. | |
1971 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n | |
1972 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n | |
1973 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n | |
1974 * CCMR2 OC4CE LL_TIM_OC_DisableClear | |
1975 * @param TIMx Timer instance | |
1976 * @param Channel This parameter can be one of the following values: | |
1977 * @arg @ref LL_TIM_CHANNEL_CH1 | |
1978 * @arg @ref LL_TIM_CHANNEL_CH2 | |
1979 * @arg @ref LL_TIM_CHANNEL_CH3 | |
1980 * @arg @ref LL_TIM_CHANNEL_CH4 | |
1981 * @retval None | |
1982 */ | |
1983 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) | |
1984 { | |
1985 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
1986 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
1987 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); | |
1988 } | |
1989 | |
1990 /** | |
1991 * @brief Indicates clearing the output channel on an external event is enabled for the output channel. | |
1992 * @note This function enables clearing the output channel on an external event. | |
1993 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. | |
1994 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether | |
1995 * or not a timer instance can clear the OCxREF signal on an external event. | |
1996 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n | |
1997 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n | |
1998 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n | |
1999 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n | |
2000 * @param TIMx Timer instance | |
2001 * @param Channel This parameter can be one of the following values: | |
2002 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2003 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2004 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2005 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2006 * @retval State of bit (1 or 0). | |
2007 */ | |
2008 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) | |
2009 { | |
2010 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2011 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
2012 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; | |
2013 return (READ_BIT(*pReg, bitfield) == bitfield); | |
2014 } | |
2015 | |
2016 /** | |
2017 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). | |
2018 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2019 * dead-time insertion feature is supported by a timer instance. | |
2020 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter | |
2021 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime | |
2022 * @param TIMx Timer instance | |
2023 * @param DeadTime between Min_Data=0 and Max_Data=255 | |
2024 * @retval None | |
2025 */ | |
2026 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) | |
2027 { | |
2028 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); | |
2029 } | |
2030 | |
2031 /** | |
2032 * @brief Set compare value for output channel 1 (TIMx_CCR1). | |
2033 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. | |
2034 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2035 * whether or not a timer instance supports a 32 bits counter. | |
2036 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not | |
2037 * output channel 1 is supported by a timer instance. | |
2038 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 | |
2039 * @param TIMx Timer instance | |
2040 * @param CompareValue between Min_Data=0 and Max_Data=65535 | |
2041 * @retval None | |
2042 */ | |
2043 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) | |
2044 { | |
2045 WRITE_REG(TIMx->CCR1, CompareValue); | |
2046 } | |
2047 | |
2048 /** | |
2049 * @brief Set compare value for output channel 2 (TIMx_CCR2). | |
2050 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. | |
2051 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2052 * whether or not a timer instance supports a 32 bits counter. | |
2053 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not | |
2054 * output channel 2 is supported by a timer instance. | |
2055 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 | |
2056 * @param TIMx Timer instance | |
2057 * @param CompareValue between Min_Data=0 and Max_Data=65535 | |
2058 * @retval None | |
2059 */ | |
2060 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) | |
2061 { | |
2062 WRITE_REG(TIMx->CCR2, CompareValue); | |
2063 } | |
2064 | |
2065 /** | |
2066 * @brief Set compare value for output channel 3 (TIMx_CCR3). | |
2067 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. | |
2068 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2069 * whether or not a timer instance supports a 32 bits counter. | |
2070 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not | |
2071 * output channel is supported by a timer instance. | |
2072 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 | |
2073 * @param TIMx Timer instance | |
2074 * @param CompareValue between Min_Data=0 and Max_Data=65535 | |
2075 * @retval None | |
2076 */ | |
2077 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) | |
2078 { | |
2079 WRITE_REG(TIMx->CCR3, CompareValue); | |
2080 } | |
2081 | |
2082 /** | |
2083 * @brief Set compare value for output channel 4 (TIMx_CCR4). | |
2084 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. | |
2085 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2086 * whether or not a timer instance supports a 32 bits counter. | |
2087 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not | |
2088 * output channel 4 is supported by a timer instance. | |
2089 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 | |
2090 * @param TIMx Timer instance | |
2091 * @param CompareValue between Min_Data=0 and Max_Data=65535 | |
2092 * @retval None | |
2093 */ | |
2094 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) | |
2095 { | |
2096 WRITE_REG(TIMx->CCR4, CompareValue); | |
2097 } | |
2098 | |
2099 /** | |
2100 * @brief Get compare value (TIMx_CCR1) set for output channel 1. | |
2101 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. | |
2102 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2103 * whether or not a timer instance supports a 32 bits counter. | |
2104 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not | |
2105 * output channel 1 is supported by a timer instance. | |
2106 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 | |
2107 * @param TIMx Timer instance | |
2108 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) | |
2109 */ | |
2110 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) | |
2111 { | |
2112 return (uint32_t)(READ_REG(TIMx->CCR1)); | |
2113 } | |
2114 | |
2115 /** | |
2116 * @brief Get compare value (TIMx_CCR2) set for output channel 2. | |
2117 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. | |
2118 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2119 * whether or not a timer instance supports a 32 bits counter. | |
2120 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not | |
2121 * output channel 2 is supported by a timer instance. | |
2122 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 | |
2123 * @param TIMx Timer instance | |
2124 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) | |
2125 */ | |
2126 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) | |
2127 { | |
2128 return (uint32_t)(READ_REG(TIMx->CCR2)); | |
2129 } | |
2130 | |
2131 /** | |
2132 * @brief Get compare value (TIMx_CCR3) set for output channel 3. | |
2133 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. | |
2134 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2135 * whether or not a timer instance supports a 32 bits counter. | |
2136 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not | |
2137 * output channel 3 is supported by a timer instance. | |
2138 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 | |
2139 * @param TIMx Timer instance | |
2140 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) | |
2141 */ | |
2142 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) | |
2143 { | |
2144 return (uint32_t)(READ_REG(TIMx->CCR3)); | |
2145 } | |
2146 | |
2147 /** | |
2148 * @brief Get compare value (TIMx_CCR4) set for output channel 4. | |
2149 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. | |
2150 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2151 * whether or not a timer instance supports a 32 bits counter. | |
2152 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not | |
2153 * output channel 4 is supported by a timer instance. | |
2154 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 | |
2155 * @param TIMx Timer instance | |
2156 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) | |
2157 */ | |
2158 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) | |
2159 { | |
2160 return (uint32_t)(READ_REG(TIMx->CCR4)); | |
2161 } | |
2162 | |
2163 /** | |
2164 * @} | |
2165 */ | |
2166 | |
2167 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration | |
2168 * @{ | |
2169 */ | |
2170 /** | |
2171 * @brief Configure input channel. | |
2172 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n | |
2173 * CCMR1 IC1PSC LL_TIM_IC_Config\n | |
2174 * CCMR1 IC1F LL_TIM_IC_Config\n | |
2175 * CCMR1 CC2S LL_TIM_IC_Config\n | |
2176 * CCMR1 IC2PSC LL_TIM_IC_Config\n | |
2177 * CCMR1 IC2F LL_TIM_IC_Config\n | |
2178 * CCMR2 CC3S LL_TIM_IC_Config\n | |
2179 * CCMR2 IC3PSC LL_TIM_IC_Config\n | |
2180 * CCMR2 IC3F LL_TIM_IC_Config\n | |
2181 * CCMR2 CC4S LL_TIM_IC_Config\n | |
2182 * CCMR2 IC4PSC LL_TIM_IC_Config\n | |
2183 * CCMR2 IC4F LL_TIM_IC_Config\n | |
2184 * CCER CC1P LL_TIM_IC_Config\n | |
2185 * CCER CC1NP LL_TIM_IC_Config\n | |
2186 * CCER CC2P LL_TIM_IC_Config\n | |
2187 * CCER CC2NP LL_TIM_IC_Config\n | |
2188 * CCER CC3P LL_TIM_IC_Config\n | |
2189 * CCER CC3NP LL_TIM_IC_Config\n | |
2190 * CCER CC4P LL_TIM_IC_Config\n | |
2191 * CCER CC4NP LL_TIM_IC_Config | |
2192 * @param TIMx Timer instance | |
2193 * @param Channel This parameter can be one of the following values: | |
2194 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2195 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2196 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2197 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2198 * @param Configuration This parameter must be a combination of all the following values: | |
2199 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC | |
2200 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 | |
2201 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 | |
2202 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE | |
2203 * @retval None | |
2204 */ | |
2205 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) | |
2206 { | |
2207 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2208 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
2209 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), | |
2210 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); | |
2211 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), | |
2212 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); | |
2213 } | |
2214 | |
2215 /** | |
2216 * @brief Set the active input. | |
2217 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n | |
2218 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n | |
2219 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n | |
2220 * CCMR2 CC4S LL_TIM_IC_SetActiveInput | |
2221 * @param TIMx Timer instance | |
2222 * @param Channel This parameter can be one of the following values: | |
2223 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2224 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2225 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2226 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2227 * @param ICActiveInput This parameter can be one of the following values: | |
2228 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI | |
2229 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI | |
2230 * @arg @ref LL_TIM_ACTIVEINPUT_TRC | |
2231 * @retval None | |
2232 */ | |
2233 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) | |
2234 { | |
2235 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2236 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
2237 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); | |
2238 } | |
2239 | |
2240 /** | |
2241 * @brief Get the current active input. | |
2242 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n | |
2243 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n | |
2244 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n | |
2245 * CCMR2 CC4S LL_TIM_IC_GetActiveInput | |
2246 * @param TIMx Timer instance | |
2247 * @param Channel This parameter can be one of the following values: | |
2248 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2249 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2250 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2251 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2252 * @retval Returned value can be one of the following values: | |
2253 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI | |
2254 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI | |
2255 * @arg @ref LL_TIM_ACTIVEINPUT_TRC | |
2256 */ | |
2257 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) | |
2258 { | |
2259 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2260 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
2261 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); | |
2262 } | |
2263 | |
2264 /** | |
2265 * @brief Set the prescaler of input channel. | |
2266 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n | |
2267 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n | |
2268 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n | |
2269 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler | |
2270 * @param TIMx Timer instance | |
2271 * @param Channel This parameter can be one of the following values: | |
2272 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2273 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2274 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2275 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2276 * @param ICPrescaler This parameter can be one of the following values: | |
2277 * @arg @ref LL_TIM_ICPSC_DIV1 | |
2278 * @arg @ref LL_TIM_ICPSC_DIV2 | |
2279 * @arg @ref LL_TIM_ICPSC_DIV4 | |
2280 * @arg @ref LL_TIM_ICPSC_DIV8 | |
2281 * @retval None | |
2282 */ | |
2283 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) | |
2284 { | |
2285 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2286 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
2287 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); | |
2288 } | |
2289 | |
2290 /** | |
2291 * @brief Get the current prescaler value acting on an input channel. | |
2292 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n | |
2293 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n | |
2294 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n | |
2295 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler | |
2296 * @param TIMx Timer instance | |
2297 * @param Channel This parameter can be one of the following values: | |
2298 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2299 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2300 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2301 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2302 * @retval Returned value can be one of the following values: | |
2303 * @arg @ref LL_TIM_ICPSC_DIV1 | |
2304 * @arg @ref LL_TIM_ICPSC_DIV2 | |
2305 * @arg @ref LL_TIM_ICPSC_DIV4 | |
2306 * @arg @ref LL_TIM_ICPSC_DIV8 | |
2307 */ | |
2308 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) | |
2309 { | |
2310 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2311 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
2312 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); | |
2313 } | |
2314 | |
2315 /** | |
2316 * @brief Set the input filter duration. | |
2317 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n | |
2318 * CCMR1 IC2F LL_TIM_IC_SetFilter\n | |
2319 * CCMR2 IC3F LL_TIM_IC_SetFilter\n | |
2320 * CCMR2 IC4F LL_TIM_IC_SetFilter | |
2321 * @param TIMx Timer instance | |
2322 * @param Channel This parameter can be one of the following values: | |
2323 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2324 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2325 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2326 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2327 * @param ICFilter This parameter can be one of the following values: | |
2328 * @arg @ref LL_TIM_IC_FILTER_FDIV1 | |
2329 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 | |
2330 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 | |
2331 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 | |
2332 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 | |
2333 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 | |
2334 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 | |
2335 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 | |
2336 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 | |
2337 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 | |
2338 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 | |
2339 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 | |
2340 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 | |
2341 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 | |
2342 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 | |
2343 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 | |
2344 * @retval None | |
2345 */ | |
2346 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) | |
2347 { | |
2348 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2349 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
2350 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); | |
2351 } | |
2352 | |
2353 /** | |
2354 * @brief Get the input filter duration. | |
2355 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n | |
2356 * CCMR1 IC2F LL_TIM_IC_GetFilter\n | |
2357 * CCMR2 IC3F LL_TIM_IC_GetFilter\n | |
2358 * CCMR2 IC4F LL_TIM_IC_GetFilter | |
2359 * @param TIMx Timer instance | |
2360 * @param Channel This parameter can be one of the following values: | |
2361 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2362 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2363 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2364 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2365 * @retval Returned value can be one of the following values: | |
2366 * @arg @ref LL_TIM_IC_FILTER_FDIV1 | |
2367 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 | |
2368 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 | |
2369 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 | |
2370 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 | |
2371 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 | |
2372 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 | |
2373 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 | |
2374 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 | |
2375 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 | |
2376 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 | |
2377 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 | |
2378 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 | |
2379 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 | |
2380 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 | |
2381 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 | |
2382 */ | |
2383 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) | |
2384 { | |
2385 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2386 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); | |
2387 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); | |
2388 } | |
2389 | |
2390 /** | |
2391 * @brief Set the input channel polarity. | |
2392 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n | |
2393 * CCER CC1NP LL_TIM_IC_SetPolarity\n | |
2394 * CCER CC2P LL_TIM_IC_SetPolarity\n | |
2395 * CCER CC2NP LL_TIM_IC_SetPolarity\n | |
2396 * CCER CC3P LL_TIM_IC_SetPolarity\n | |
2397 * CCER CC3NP LL_TIM_IC_SetPolarity\n | |
2398 * CCER CC4P LL_TIM_IC_SetPolarity\n | |
2399 * CCER CC4NP LL_TIM_IC_SetPolarity | |
2400 * @param TIMx Timer instance | |
2401 * @param Channel This parameter can be one of the following values: | |
2402 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2403 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2404 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2405 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2406 * @param ICPolarity This parameter can be one of the following values: | |
2407 * @arg @ref LL_TIM_IC_POLARITY_RISING | |
2408 * @arg @ref LL_TIM_IC_POLARITY_FALLING | |
2409 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE | |
2410 * @retval None | |
2411 */ | |
2412 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) | |
2413 { | |
2414 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2415 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), | |
2416 ICPolarity << SHIFT_TAB_CCxP[iChannel]); | |
2417 } | |
2418 | |
2419 /** | |
2420 * @brief Get the current input channel polarity. | |
2421 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n | |
2422 * CCER CC1NP LL_TIM_IC_GetPolarity\n | |
2423 * CCER CC2P LL_TIM_IC_GetPolarity\n | |
2424 * CCER CC2NP LL_TIM_IC_GetPolarity\n | |
2425 * CCER CC3P LL_TIM_IC_GetPolarity\n | |
2426 * CCER CC3NP LL_TIM_IC_GetPolarity\n | |
2427 * CCER CC4P LL_TIM_IC_GetPolarity\n | |
2428 * CCER CC4NP LL_TIM_IC_GetPolarity | |
2429 * @param TIMx Timer instance | |
2430 * @param Channel This parameter can be one of the following values: | |
2431 * @arg @ref LL_TIM_CHANNEL_CH1 | |
2432 * @arg @ref LL_TIM_CHANNEL_CH2 | |
2433 * @arg @ref LL_TIM_CHANNEL_CH3 | |
2434 * @arg @ref LL_TIM_CHANNEL_CH4 | |
2435 * @retval Returned value can be one of the following values: | |
2436 * @arg @ref LL_TIM_IC_POLARITY_RISING | |
2437 * @arg @ref LL_TIM_IC_POLARITY_FALLING | |
2438 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE | |
2439 */ | |
2440 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) | |
2441 { | |
2442 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); | |
2443 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> | |
2444 SHIFT_TAB_CCxP[iChannel]); | |
2445 } | |
2446 | |
2447 /** | |
2448 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). | |
2449 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not | |
2450 * a timer instance provides an XOR input. | |
2451 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination | |
2452 * @param TIMx Timer instance | |
2453 * @retval None | |
2454 */ | |
2455 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) | |
2456 { | |
2457 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); | |
2458 } | |
2459 | |
2460 /** | |
2461 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. | |
2462 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not | |
2463 * a timer instance provides an XOR input. | |
2464 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination | |
2465 * @param TIMx Timer instance | |
2466 * @retval None | |
2467 */ | |
2468 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) | |
2469 { | |
2470 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); | |
2471 } | |
2472 | |
2473 /** | |
2474 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. | |
2475 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not | |
2476 * a timer instance provides an XOR input. | |
2477 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination | |
2478 * @param TIMx Timer instance | |
2479 * @retval State of bit (1 or 0). | |
2480 */ | |
2481 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) | |
2482 { | |
2483 return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); | |
2484 } | |
2485 | |
2486 /** | |
2487 * @brief Get captured value for input channel 1. | |
2488 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. | |
2489 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2490 * whether or not a timer instance supports a 32 bits counter. | |
2491 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not | |
2492 * input channel 1 is supported by a timer instance. | |
2493 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 | |
2494 * @param TIMx Timer instance | |
2495 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) | |
2496 */ | |
2497 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) | |
2498 { | |
2499 return (uint32_t)(READ_REG(TIMx->CCR1)); | |
2500 } | |
2501 | |
2502 /** | |
2503 * @brief Get captured value for input channel 2. | |
2504 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. | |
2505 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2506 * whether or not a timer instance supports a 32 bits counter. | |
2507 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not | |
2508 * input channel 2 is supported by a timer instance. | |
2509 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 | |
2510 * @param TIMx Timer instance | |
2511 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) | |
2512 */ | |
2513 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) | |
2514 { | |
2515 return (uint32_t)(READ_REG(TIMx->CCR2)); | |
2516 } | |
2517 | |
2518 /** | |
2519 * @brief Get captured value for input channel 3. | |
2520 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. | |
2521 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2522 * whether or not a timer instance supports a 32 bits counter. | |
2523 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not | |
2524 * input channel 3 is supported by a timer instance. | |
2525 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 | |
2526 * @param TIMx Timer instance | |
2527 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) | |
2528 */ | |
2529 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) | |
2530 { | |
2531 return (uint32_t)(READ_REG(TIMx->CCR3)); | |
2532 } | |
2533 | |
2534 /** | |
2535 * @brief Get captured value for input channel 4. | |
2536 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. | |
2537 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check | |
2538 * whether or not a timer instance supports a 32 bits counter. | |
2539 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not | |
2540 * input channel 4 is supported by a timer instance. | |
2541 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 | |
2542 * @param TIMx Timer instance | |
2543 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) | |
2544 */ | |
2545 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) | |
2546 { | |
2547 return (uint32_t)(READ_REG(TIMx->CCR4)); | |
2548 } | |
2549 | |
2550 /** | |
2551 * @} | |
2552 */ | |
2553 | |
2554 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection | |
2555 * @{ | |
2556 */ | |
2557 /** | |
2558 * @brief Enable external clock mode 2. | |
2559 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. | |
2560 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check | |
2561 * whether or not a timer instance supports external clock mode2. | |
2562 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock | |
2563 * @param TIMx Timer instance | |
2564 * @retval None | |
2565 */ | |
2566 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) | |
2567 { | |
2568 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); | |
2569 } | |
2570 | |
2571 /** | |
2572 * @brief Disable external clock mode 2. | |
2573 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check | |
2574 * whether or not a timer instance supports external clock mode2. | |
2575 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock | |
2576 * @param TIMx Timer instance | |
2577 * @retval None | |
2578 */ | |
2579 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) | |
2580 { | |
2581 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); | |
2582 } | |
2583 | |
2584 /** | |
2585 * @brief Indicate whether external clock mode 2 is enabled. | |
2586 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check | |
2587 * whether or not a timer instance supports external clock mode2. | |
2588 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock | |
2589 * @param TIMx Timer instance | |
2590 * @retval State of bit (1 or 0). | |
2591 */ | |
2592 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) | |
2593 { | |
2594 return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); | |
2595 } | |
2596 | |
2597 /** | |
2598 * @brief Set the clock source of the counter clock. | |
2599 * @note when selected clock source is external clock mode 1, the timer input | |
2600 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() | |
2601 * function. This timer input must be configured by calling | |
2602 * the @ref LL_TIM_IC_Config() function. | |
2603 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check | |
2604 * whether or not a timer instance supports external clock mode1. | |
2605 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check | |
2606 * whether or not a timer instance supports external clock mode2. | |
2607 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n | |
2608 * SMCR ECE LL_TIM_SetClockSource | |
2609 * @param TIMx Timer instance | |
2610 * @param ClockSource This parameter can be one of the following values: | |
2611 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL | |
2612 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 | |
2613 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 | |
2614 * @retval None | |
2615 */ | |
2616 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) | |
2617 { | |
2618 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); | |
2619 } | |
2620 | |
2621 /** | |
2622 * @brief Set the encoder interface mode. | |
2623 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check | |
2624 * whether or not a timer instance supports the encoder mode. | |
2625 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode | |
2626 * @param TIMx Timer instance | |
2627 * @param EncoderMode This parameter can be one of the following values: | |
2628 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 | |
2629 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 | |
2630 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 | |
2631 * @retval None | |
2632 */ | |
2633 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) | |
2634 { | |
2635 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); | |
2636 } | |
2637 | |
2638 /** | |
2639 * @} | |
2640 */ | |
2641 | |
2642 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration | |
2643 * @{ | |
2644 */ | |
2645 /** | |
2646 * @brief Set the trigger output (TRGO) used for timer synchronization . | |
2647 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check | |
2648 * whether or not a timer instance can operate as a master timer. | |
2649 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput | |
2650 * @param TIMx Timer instance | |
2651 * @param TimerSynchronization This parameter can be one of the following values: | |
2652 * @arg @ref LL_TIM_TRGO_RESET | |
2653 * @arg @ref LL_TIM_TRGO_ENABLE | |
2654 * @arg @ref LL_TIM_TRGO_UPDATE | |
2655 * @arg @ref LL_TIM_TRGO_CC1IF | |
2656 * @arg @ref LL_TIM_TRGO_OC1REF | |
2657 * @arg @ref LL_TIM_TRGO_OC2REF | |
2658 * @arg @ref LL_TIM_TRGO_OC3REF | |
2659 * @arg @ref LL_TIM_TRGO_OC4REF | |
2660 * @retval None | |
2661 */ | |
2662 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) | |
2663 { | |
2664 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); | |
2665 } | |
2666 | |
2667 /** | |
2668 * @brief Set the synchronization mode of a slave timer. | |
2669 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not | |
2670 * a timer instance can operate as a slave timer. | |
2671 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode | |
2672 * @param TIMx Timer instance | |
2673 * @param SlaveMode This parameter can be one of the following values: | |
2674 * @arg @ref LL_TIM_SLAVEMODE_DISABLED | |
2675 * @arg @ref LL_TIM_SLAVEMODE_RESET | |
2676 * @arg @ref LL_TIM_SLAVEMODE_GATED | |
2677 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER | |
2678 * @retval None | |
2679 */ | |
2680 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) | |
2681 { | |
2682 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); | |
2683 } | |
2684 | |
2685 /** | |
2686 * @brief Set the selects the trigger input to be used to synchronize the counter. | |
2687 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not | |
2688 * a timer instance can operate as a slave timer. | |
2689 * @rmtoll SMCR TS LL_TIM_SetTriggerInput | |
2690 * @param TIMx Timer instance | |
2691 * @param TriggerInput This parameter can be one of the following values: | |
2692 * @arg @ref LL_TIM_TS_ITR0 | |
2693 * @arg @ref LL_TIM_TS_ITR1 | |
2694 * @arg @ref LL_TIM_TS_ITR2 | |
2695 * @arg @ref LL_TIM_TS_ITR3 | |
2696 * @arg @ref LL_TIM_TS_TI1F_ED | |
2697 * @arg @ref LL_TIM_TS_TI1FP1 | |
2698 * @arg @ref LL_TIM_TS_TI2FP2 | |
2699 * @arg @ref LL_TIM_TS_ETRF | |
2700 * @retval None | |
2701 */ | |
2702 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) | |
2703 { | |
2704 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); | |
2705 } | |
2706 | |
2707 /** | |
2708 * @brief Enable the Master/Slave mode. | |
2709 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not | |
2710 * a timer instance can operate as a slave timer. | |
2711 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode | |
2712 * @param TIMx Timer instance | |
2713 * @retval None | |
2714 */ | |
2715 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) | |
2716 { | |
2717 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); | |
2718 } | |
2719 | |
2720 /** | |
2721 * @brief Disable the Master/Slave mode. | |
2722 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not | |
2723 * a timer instance can operate as a slave timer. | |
2724 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode | |
2725 * @param TIMx Timer instance | |
2726 * @retval None | |
2727 */ | |
2728 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) | |
2729 { | |
2730 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); | |
2731 } | |
2732 | |
2733 /** | |
2734 * @brief Indicates whether the Master/Slave mode is enabled. | |
2735 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not | |
2736 * a timer instance can operate as a slave timer. | |
2737 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode | |
2738 * @param TIMx Timer instance | |
2739 * @retval State of bit (1 or 0). | |
2740 */ | |
2741 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) | |
2742 { | |
2743 return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); | |
2744 } | |
2745 | |
2746 /** | |
2747 * @brief Configure the external trigger (ETR) input. | |
2748 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not | |
2749 * a timer instance provides an external trigger input. | |
2750 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n | |
2751 * SMCR ETPS LL_TIM_ConfigETR\n | |
2752 * SMCR ETF LL_TIM_ConfigETR | |
2753 * @param TIMx Timer instance | |
2754 * @param ETRPolarity This parameter can be one of the following values: | |
2755 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED | |
2756 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED | |
2757 * @param ETRPrescaler This parameter can be one of the following values: | |
2758 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 | |
2759 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 | |
2760 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 | |
2761 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 | |
2762 * @param ETRFilter This parameter can be one of the following values: | |
2763 * @arg @ref LL_TIM_ETR_FILTER_FDIV1 | |
2764 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 | |
2765 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 | |
2766 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 | |
2767 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 | |
2768 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 | |
2769 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 | |
2770 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 | |
2771 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 | |
2772 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 | |
2773 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 | |
2774 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 | |
2775 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 | |
2776 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 | |
2777 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 | |
2778 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 | |
2779 * @retval None | |
2780 */ | |
2781 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, | |
2782 uint32_t ETRFilter) | |
2783 { | |
2784 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); | |
2785 } | |
2786 | |
2787 /** | |
2788 * @} | |
2789 */ | |
2790 | |
2791 /** @defgroup TIM_LL_EF_Break_Function Break function configuration | |
2792 * @{ | |
2793 */ | |
2794 /** | |
2795 * @brief Enable the break function. | |
2796 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2797 * a timer instance provides a break input. | |
2798 * @rmtoll BDTR BKE LL_TIM_EnableBRK | |
2799 * @param TIMx Timer instance | |
2800 * @retval None | |
2801 */ | |
2802 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) | |
2803 { | |
2804 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); | |
2805 } | |
2806 | |
2807 /** | |
2808 * @brief Disable the break function. | |
2809 * @rmtoll BDTR BKE LL_TIM_DisableBRK | |
2810 * @param TIMx Timer instance | |
2811 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2812 * a timer instance provides a break input. | |
2813 * @retval None | |
2814 */ | |
2815 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) | |
2816 { | |
2817 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); | |
2818 } | |
2819 | |
2820 /** | |
2821 * @brief Configure the break input. | |
2822 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2823 * a timer instance provides a break input. | |
2824 * @rmtoll BDTR BKP LL_TIM_ConfigBRK | |
2825 * @param TIMx Timer instance | |
2826 * @param BreakPolarity This parameter can be one of the following values: | |
2827 * @arg @ref LL_TIM_BREAK_POLARITY_LOW | |
2828 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH | |
2829 * @retval None | |
2830 */ | |
2831 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) | |
2832 { | |
2833 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); | |
2834 } | |
2835 | |
2836 /** | |
2837 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. | |
2838 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2839 * a timer instance provides a break input. | |
2840 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n | |
2841 * BDTR OSSR LL_TIM_SetOffStates | |
2842 * @param TIMx Timer instance | |
2843 * @param OffStateIdle This parameter can be one of the following values: | |
2844 * @arg @ref LL_TIM_OSSI_DISABLE | |
2845 * @arg @ref LL_TIM_OSSI_ENABLE | |
2846 * @param OffStateRun This parameter can be one of the following values: | |
2847 * @arg @ref LL_TIM_OSSR_DISABLE | |
2848 * @arg @ref LL_TIM_OSSR_ENABLE | |
2849 * @retval None | |
2850 */ | |
2851 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) | |
2852 { | |
2853 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); | |
2854 } | |
2855 | |
2856 /** | |
2857 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). | |
2858 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2859 * a timer instance provides a break input. | |
2860 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput | |
2861 * @param TIMx Timer instance | |
2862 * @retval None | |
2863 */ | |
2864 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) | |
2865 { | |
2866 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); | |
2867 } | |
2868 | |
2869 /** | |
2870 * @brief Disable automatic output (MOE can be set only by software). | |
2871 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2872 * a timer instance provides a break input. | |
2873 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput | |
2874 * @param TIMx Timer instance | |
2875 * @retval None | |
2876 */ | |
2877 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) | |
2878 { | |
2879 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); | |
2880 } | |
2881 | |
2882 /** | |
2883 * @brief Indicate whether automatic output is enabled. | |
2884 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2885 * a timer instance provides a break input. | |
2886 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput | |
2887 * @param TIMx Timer instance | |
2888 * @retval State of bit (1 or 0). | |
2889 */ | |
2890 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) | |
2891 { | |
2892 return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); | |
2893 } | |
2894 | |
2895 /** | |
2896 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). | |
2897 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by | |
2898 * software and is reset in case of break or break2 event | |
2899 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2900 * a timer instance provides a break input. | |
2901 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs | |
2902 * @param TIMx Timer instance | |
2903 * @retval None | |
2904 */ | |
2905 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) | |
2906 { | |
2907 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); | |
2908 } | |
2909 | |
2910 /** | |
2911 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). | |
2912 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by | |
2913 * software and is reset in case of break or break2 event. | |
2914 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2915 * a timer instance provides a break input. | |
2916 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs | |
2917 * @param TIMx Timer instance | |
2918 * @retval None | |
2919 */ | |
2920 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) | |
2921 { | |
2922 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); | |
2923 } | |
2924 | |
2925 /** | |
2926 * @brief Indicates whether outputs are enabled. | |
2927 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not | |
2928 * a timer instance provides a break input. | |
2929 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs | |
2930 * @param TIMx Timer instance | |
2931 * @retval State of bit (1 or 0). | |
2932 */ | |
2933 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) | |
2934 { | |
2935 return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); | |
2936 } | |
2937 | |
2938 /** | |
2939 * @} | |
2940 */ | |
2941 | |
2942 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration | |
2943 * @{ | |
2944 */ | |
2945 /** | |
2946 * @brief Configures the timer DMA burst feature. | |
2947 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or | |
2948 * not a timer instance supports the DMA burst mode. | |
2949 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n | |
2950 * DCR DBA LL_TIM_ConfigDMABurst | |
2951 * @param TIMx Timer instance | |
2952 * @param DMABurstBaseAddress This parameter can be one of the following values: | |
2953 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 | |
2954 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 | |
2955 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR | |
2956 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER | |
2957 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR | |
2958 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR | |
2959 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 | |
2960 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 | |
2961 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER | |
2962 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT | |
2963 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC | |
2964 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR | |
2965 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR | |
2966 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 | |
2967 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 | |
2968 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 | |
2969 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 | |
2970 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR | |
2971 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR | |
2972 * @param DMABurstLength This parameter can be one of the following values: | |
2973 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER | |
2974 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS | |
2975 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS | |
2976 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS | |
2977 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS | |
2978 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS | |
2979 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS | |
2980 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS | |
2981 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS | |
2982 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS | |
2983 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS | |
2984 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS | |
2985 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS | |
2986 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS | |
2987 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS | |
2988 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS | |
2989 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS | |
2990 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS | |
2991 * @retval None | |
2992 */ | |
2993 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) | |
2994 { | |
2995 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); | |
2996 } | |
2997 | |
2998 /** | |
2999 * @} | |
3000 */ | |
3001 | |
3002 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping | |
3003 * @{ | |
3004 */ | |
3005 /** | |
3006 * @brief Remap TIM inputs (input channel, internal/external triggers). | |
3007 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not | |
3008 * a some timer inputs can be remapped. | |
3009 * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n | |
3010 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n | |
3011 * TIM11_OR TI1_RMP LL_TIM_SetRemap | |
3012 * @param TIMx Timer instance | |
3013 * @param Remap Remap param depends on the TIMx. Description available only | |
3014 * in CHM version of the User Manual (not in .pdf). | |
3015 * Otherwise see Reference Manual description of OR registers. | |
3016 * | |
3017 * Below description summarizes "Timer Instance" and "Remap" param combinations: | |
3018 * | |
3019 * TIM2: one of the following values | |
3020 * | |
3021 * ITR1_RMP can be one of the following values | |
3022 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO | |
3023 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF | |
3024 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF | |
3025 * | |
3026 * TIM5: one of the following values | |
3027 * | |
3028 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO | |
3029 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI | |
3030 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE | |
3031 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC | |
3032 * | |
3033 * TIM11: one of the following values | |
3034 * | |
3035 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO | |
3036 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 | |
3037 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC | |
3038 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2 | |
3039 * | |
3040 * @retval None | |
3041 */ | |
3042 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) | |
3043 { | |
3044 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); | |
3045 } | |
3046 | |
3047 /** | |
3048 * @} | |
3049 */ | |
3050 | |
3051 | |
3052 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management | |
3053 * @{ | |
3054 */ | |
3055 /** | |
3056 * @brief Clear the update interrupt flag (UIF). | |
3057 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE | |
3058 * @param TIMx Timer instance | |
3059 * @retval None | |
3060 */ | |
3061 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) | |
3062 { | |
3063 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); | |
3064 } | |
3065 | |
3066 /** | |
3067 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). | |
3068 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE | |
3069 * @param TIMx Timer instance | |
3070 * @retval State of bit (1 or 0). | |
3071 */ | |
3072 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) | |
3073 { | |
3074 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); | |
3075 } | |
3076 | |
3077 /** | |
3078 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). | |
3079 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 | |
3080 * @param TIMx Timer instance | |
3081 * @retval None | |
3082 */ | |
3083 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) | |
3084 { | |
3085 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); | |
3086 } | |
3087 | |
3088 /** | |
3089 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). | |
3090 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 | |
3091 * @param TIMx Timer instance | |
3092 * @retval State of bit (1 or 0). | |
3093 */ | |
3094 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) | |
3095 { | |
3096 return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); | |
3097 } | |
3098 | |
3099 /** | |
3100 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). | |
3101 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 | |
3102 * @param TIMx Timer instance | |
3103 * @retval None | |
3104 */ | |
3105 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) | |
3106 { | |
3107 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); | |
3108 } | |
3109 | |
3110 /** | |
3111 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). | |
3112 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 | |
3113 * @param TIMx Timer instance | |
3114 * @retval State of bit (1 or 0). | |
3115 */ | |
3116 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) | |
3117 { | |
3118 return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); | |
3119 } | |
3120 | |
3121 /** | |
3122 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). | |
3123 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 | |
3124 * @param TIMx Timer instance | |
3125 * @retval None | |
3126 */ | |
3127 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) | |
3128 { | |
3129 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); | |
3130 } | |
3131 | |
3132 /** | |
3133 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). | |
3134 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 | |
3135 * @param TIMx Timer instance | |
3136 * @retval State of bit (1 or 0). | |
3137 */ | |
3138 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) | |
3139 { | |
3140 return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); | |
3141 } | |
3142 | |
3143 /** | |
3144 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). | |
3145 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 | |
3146 * @param TIMx Timer instance | |
3147 * @retval None | |
3148 */ | |
3149 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) | |
3150 { | |
3151 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); | |
3152 } | |
3153 | |
3154 /** | |
3155 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). | |
3156 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 | |
3157 * @param TIMx Timer instance | |
3158 * @retval State of bit (1 or 0). | |
3159 */ | |
3160 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) | |
3161 { | |
3162 return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); | |
3163 } | |
3164 | |
3165 /** | |
3166 * @brief Clear the commutation interrupt flag (COMIF). | |
3167 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM | |
3168 * @param TIMx Timer instance | |
3169 * @retval None | |
3170 */ | |
3171 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) | |
3172 { | |
3173 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); | |
3174 } | |
3175 | |
3176 /** | |
3177 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). | |
3178 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM | |
3179 * @param TIMx Timer instance | |
3180 * @retval State of bit (1 or 0). | |
3181 */ | |
3182 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) | |
3183 { | |
3184 return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); | |
3185 } | |
3186 | |
3187 /** | |
3188 * @brief Clear the trigger interrupt flag (TIF). | |
3189 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG | |
3190 * @param TIMx Timer instance | |
3191 * @retval None | |
3192 */ | |
3193 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) | |
3194 { | |
3195 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); | |
3196 } | |
3197 | |
3198 /** | |
3199 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). | |
3200 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG | |
3201 * @param TIMx Timer instance | |
3202 * @retval State of bit (1 or 0). | |
3203 */ | |
3204 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) | |
3205 { | |
3206 return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); | |
3207 } | |
3208 | |
3209 /** | |
3210 * @brief Clear the break interrupt flag (BIF). | |
3211 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK | |
3212 * @param TIMx Timer instance | |
3213 * @retval None | |
3214 */ | |
3215 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) | |
3216 { | |
3217 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); | |
3218 } | |
3219 | |
3220 /** | |
3221 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). | |
3222 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK | |
3223 * @param TIMx Timer instance | |
3224 * @retval State of bit (1 or 0). | |
3225 */ | |
3226 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) | |
3227 { | |
3228 return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); | |
3229 } | |
3230 | |
3231 /** | |
3232 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). | |
3233 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR | |
3234 * @param TIMx Timer instance | |
3235 * @retval None | |
3236 */ | |
3237 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) | |
3238 { | |
3239 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); | |
3240 } | |
3241 | |
3242 /** | |
3243 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). | |
3244 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR | |
3245 * @param TIMx Timer instance | |
3246 * @retval State of bit (1 or 0). | |
3247 */ | |
3248 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) | |
3249 { | |
3250 return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); | |
3251 } | |
3252 | |
3253 /** | |
3254 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). | |
3255 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR | |
3256 * @param TIMx Timer instance | |
3257 * @retval None | |
3258 */ | |
3259 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) | |
3260 { | |
3261 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); | |
3262 } | |
3263 | |
3264 /** | |
3265 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). | |
3266 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR | |
3267 * @param TIMx Timer instance | |
3268 * @retval State of bit (1 or 0). | |
3269 */ | |
3270 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) | |
3271 { | |
3272 return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); | |
3273 } | |
3274 | |
3275 /** | |
3276 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). | |
3277 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR | |
3278 * @param TIMx Timer instance | |
3279 * @retval None | |
3280 */ | |
3281 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) | |
3282 { | |
3283 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); | |
3284 } | |
3285 | |
3286 /** | |
3287 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). | |
3288 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR | |
3289 * @param TIMx Timer instance | |
3290 * @retval State of bit (1 or 0). | |
3291 */ | |
3292 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) | |
3293 { | |
3294 return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); | |
3295 } | |
3296 | |
3297 /** | |
3298 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). | |
3299 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR | |
3300 * @param TIMx Timer instance | |
3301 * @retval None | |
3302 */ | |
3303 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) | |
3304 { | |
3305 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); | |
3306 } | |
3307 | |
3308 /** | |
3309 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). | |
3310 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR | |
3311 * @param TIMx Timer instance | |
3312 * @retval State of bit (1 or 0). | |
3313 */ | |
3314 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) | |
3315 { | |
3316 return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); | |
3317 } | |
3318 | |
3319 /** | |
3320 * @} | |
3321 */ | |
3322 | |
3323 /** @defgroup TIM_LL_EF_IT_Management IT-Management | |
3324 * @{ | |
3325 */ | |
3326 /** | |
3327 * @brief Enable update interrupt (UIE). | |
3328 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE | |
3329 * @param TIMx Timer instance | |
3330 * @retval None | |
3331 */ | |
3332 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) | |
3333 { | |
3334 SET_BIT(TIMx->DIER, TIM_DIER_UIE); | |
3335 } | |
3336 | |
3337 /** | |
3338 * @brief Disable update interrupt (UIE). | |
3339 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE | |
3340 * @param TIMx Timer instance | |
3341 * @retval None | |
3342 */ | |
3343 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) | |
3344 { | |
3345 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); | |
3346 } | |
3347 | |
3348 /** | |
3349 * @brief Indicates whether the update interrupt (UIE) is enabled. | |
3350 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE | |
3351 * @param TIMx Timer instance | |
3352 * @retval State of bit (1 or 0). | |
3353 */ | |
3354 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) | |
3355 { | |
3356 return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); | |
3357 } | |
3358 | |
3359 /** | |
3360 * @brief Enable capture/compare 1 interrupt (CC1IE). | |
3361 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 | |
3362 * @param TIMx Timer instance | |
3363 * @retval None | |
3364 */ | |
3365 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) | |
3366 { | |
3367 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); | |
3368 } | |
3369 | |
3370 /** | |
3371 * @brief Disable capture/compare 1 interrupt (CC1IE). | |
3372 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 | |
3373 * @param TIMx Timer instance | |
3374 * @retval None | |
3375 */ | |
3376 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) | |
3377 { | |
3378 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); | |
3379 } | |
3380 | |
3381 /** | |
3382 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. | |
3383 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 | |
3384 * @param TIMx Timer instance | |
3385 * @retval State of bit (1 or 0). | |
3386 */ | |
3387 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) | |
3388 { | |
3389 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); | |
3390 } | |
3391 | |
3392 /** | |
3393 * @brief Enable capture/compare 2 interrupt (CC2IE). | |
3394 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 | |
3395 * @param TIMx Timer instance | |
3396 * @retval None | |
3397 */ | |
3398 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) | |
3399 { | |
3400 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); | |
3401 } | |
3402 | |
3403 /** | |
3404 * @brief Disable capture/compare 2 interrupt (CC2IE). | |
3405 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 | |
3406 * @param TIMx Timer instance | |
3407 * @retval None | |
3408 */ | |
3409 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) | |
3410 { | |
3411 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); | |
3412 } | |
3413 | |
3414 /** | |
3415 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. | |
3416 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 | |
3417 * @param TIMx Timer instance | |
3418 * @retval State of bit (1 or 0). | |
3419 */ | |
3420 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) | |
3421 { | |
3422 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); | |
3423 } | |
3424 | |
3425 /** | |
3426 * @brief Enable capture/compare 3 interrupt (CC3IE). | |
3427 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 | |
3428 * @param TIMx Timer instance | |
3429 * @retval None | |
3430 */ | |
3431 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) | |
3432 { | |
3433 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); | |
3434 } | |
3435 | |
3436 /** | |
3437 * @brief Disable capture/compare 3 interrupt (CC3IE). | |
3438 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 | |
3439 * @param TIMx Timer instance | |
3440 * @retval None | |
3441 */ | |
3442 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) | |
3443 { | |
3444 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); | |
3445 } | |
3446 | |
3447 /** | |
3448 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. | |
3449 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 | |
3450 * @param TIMx Timer instance | |
3451 * @retval State of bit (1 or 0). | |
3452 */ | |
3453 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) | |
3454 { | |
3455 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); | |
3456 } | |
3457 | |
3458 /** | |
3459 * @brief Enable capture/compare 4 interrupt (CC4IE). | |
3460 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 | |
3461 * @param TIMx Timer instance | |
3462 * @retval None | |
3463 */ | |
3464 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) | |
3465 { | |
3466 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); | |
3467 } | |
3468 | |
3469 /** | |
3470 * @brief Disable capture/compare 4 interrupt (CC4IE). | |
3471 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 | |
3472 * @param TIMx Timer instance | |
3473 * @retval None | |
3474 */ | |
3475 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) | |
3476 { | |
3477 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); | |
3478 } | |
3479 | |
3480 /** | |
3481 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. | |
3482 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 | |
3483 * @param TIMx Timer instance | |
3484 * @retval State of bit (1 or 0). | |
3485 */ | |
3486 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) | |
3487 { | |
3488 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); | |
3489 } | |
3490 | |
3491 /** | |
3492 * @brief Enable commutation interrupt (COMIE). | |
3493 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM | |
3494 * @param TIMx Timer instance | |
3495 * @retval None | |
3496 */ | |
3497 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) | |
3498 { | |
3499 SET_BIT(TIMx->DIER, TIM_DIER_COMIE); | |
3500 } | |
3501 | |
3502 /** | |
3503 * @brief Disable commutation interrupt (COMIE). | |
3504 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM | |
3505 * @param TIMx Timer instance | |
3506 * @retval None | |
3507 */ | |
3508 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) | |
3509 { | |
3510 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); | |
3511 } | |
3512 | |
3513 /** | |
3514 * @brief Indicates whether the commutation interrupt (COMIE) is enabled. | |
3515 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM | |
3516 * @param TIMx Timer instance | |
3517 * @retval State of bit (1 or 0). | |
3518 */ | |
3519 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) | |
3520 { | |
3521 return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); | |
3522 } | |
3523 | |
3524 /** | |
3525 * @brief Enable trigger interrupt (TIE). | |
3526 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG | |
3527 * @param TIMx Timer instance | |
3528 * @retval None | |
3529 */ | |
3530 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) | |
3531 { | |
3532 SET_BIT(TIMx->DIER, TIM_DIER_TIE); | |
3533 } | |
3534 | |
3535 /** | |
3536 * @brief Disable trigger interrupt (TIE). | |
3537 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG | |
3538 * @param TIMx Timer instance | |
3539 * @retval None | |
3540 */ | |
3541 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) | |
3542 { | |
3543 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); | |
3544 } | |
3545 | |
3546 /** | |
3547 * @brief Indicates whether the trigger interrupt (TIE) is enabled. | |
3548 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG | |
3549 * @param TIMx Timer instance | |
3550 * @retval State of bit (1 or 0). | |
3551 */ | |
3552 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) | |
3553 { | |
3554 return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); | |
3555 } | |
3556 | |
3557 /** | |
3558 * @brief Enable break interrupt (BIE). | |
3559 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK | |
3560 * @param TIMx Timer instance | |
3561 * @retval None | |
3562 */ | |
3563 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) | |
3564 { | |
3565 SET_BIT(TIMx->DIER, TIM_DIER_BIE); | |
3566 } | |
3567 | |
3568 /** | |
3569 * @brief Disable break interrupt (BIE). | |
3570 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK | |
3571 * @param TIMx Timer instance | |
3572 * @retval None | |
3573 */ | |
3574 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) | |
3575 { | |
3576 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); | |
3577 } | |
3578 | |
3579 /** | |
3580 * @brief Indicates whether the break interrupt (BIE) is enabled. | |
3581 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK | |
3582 * @param TIMx Timer instance | |
3583 * @retval State of bit (1 or 0). | |
3584 */ | |
3585 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) | |
3586 { | |
3587 return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); | |
3588 } | |
3589 | |
3590 /** | |
3591 * @} | |
3592 */ | |
3593 | |
3594 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management | |
3595 * @{ | |
3596 */ | |
3597 /** | |
3598 * @brief Enable update DMA request (UDE). | |
3599 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE | |
3600 * @param TIMx Timer instance | |
3601 * @retval None | |
3602 */ | |
3603 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) | |
3604 { | |
3605 SET_BIT(TIMx->DIER, TIM_DIER_UDE); | |
3606 } | |
3607 | |
3608 /** | |
3609 * @brief Disable update DMA request (UDE). | |
3610 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE | |
3611 * @param TIMx Timer instance | |
3612 * @retval None | |
3613 */ | |
3614 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) | |
3615 { | |
3616 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); | |
3617 } | |
3618 | |
3619 /** | |
3620 * @brief Indicates whether the update DMA request (UDE) is enabled. | |
3621 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE | |
3622 * @param TIMx Timer instance | |
3623 * @retval State of bit (1 or 0). | |
3624 */ | |
3625 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) | |
3626 { | |
3627 return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); | |
3628 } | |
3629 | |
3630 /** | |
3631 * @brief Enable capture/compare 1 DMA request (CC1DE). | |
3632 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 | |
3633 * @param TIMx Timer instance | |
3634 * @retval None | |
3635 */ | |
3636 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) | |
3637 { | |
3638 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); | |
3639 } | |
3640 | |
3641 /** | |
3642 * @brief Disable capture/compare 1 DMA request (CC1DE). | |
3643 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 | |
3644 * @param TIMx Timer instance | |
3645 * @retval None | |
3646 */ | |
3647 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) | |
3648 { | |
3649 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); | |
3650 } | |
3651 | |
3652 /** | |
3653 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. | |
3654 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 | |
3655 * @param TIMx Timer instance | |
3656 * @retval State of bit (1 or 0). | |
3657 */ | |
3658 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) | |
3659 { | |
3660 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); | |
3661 } | |
3662 | |
3663 /** | |
3664 * @brief Enable capture/compare 2 DMA request (CC2DE). | |
3665 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 | |
3666 * @param TIMx Timer instance | |
3667 * @retval None | |
3668 */ | |
3669 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) | |
3670 { | |
3671 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); | |
3672 } | |
3673 | |
3674 /** | |
3675 * @brief Disable capture/compare 2 DMA request (CC2DE). | |
3676 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 | |
3677 * @param TIMx Timer instance | |
3678 * @retval None | |
3679 */ | |
3680 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) | |
3681 { | |
3682 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); | |
3683 } | |
3684 | |
3685 /** | |
3686 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. | |
3687 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 | |
3688 * @param TIMx Timer instance | |
3689 * @retval State of bit (1 or 0). | |
3690 */ | |
3691 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) | |
3692 { | |
3693 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); | |
3694 } | |
3695 | |
3696 /** | |
3697 * @brief Enable capture/compare 3 DMA request (CC3DE). | |
3698 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 | |
3699 * @param TIMx Timer instance | |
3700 * @retval None | |
3701 */ | |
3702 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) | |
3703 { | |
3704 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); | |
3705 } | |
3706 | |
3707 /** | |
3708 * @brief Disable capture/compare 3 DMA request (CC3DE). | |
3709 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 | |
3710 * @param TIMx Timer instance | |
3711 * @retval None | |
3712 */ | |
3713 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) | |
3714 { | |
3715 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); | |
3716 } | |
3717 | |
3718 /** | |
3719 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. | |
3720 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 | |
3721 * @param TIMx Timer instance | |
3722 * @retval State of bit (1 or 0). | |
3723 */ | |
3724 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) | |
3725 { | |
3726 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); | |
3727 } | |
3728 | |
3729 /** | |
3730 * @brief Enable capture/compare 4 DMA request (CC4DE). | |
3731 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 | |
3732 * @param TIMx Timer instance | |
3733 * @retval None | |
3734 */ | |
3735 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) | |
3736 { | |
3737 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); | |
3738 } | |
3739 | |
3740 /** | |
3741 * @brief Disable capture/compare 4 DMA request (CC4DE). | |
3742 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 | |
3743 * @param TIMx Timer instance | |
3744 * @retval None | |
3745 */ | |
3746 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) | |
3747 { | |
3748 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); | |
3749 } | |
3750 | |
3751 /** | |
3752 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. | |
3753 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 | |
3754 * @param TIMx Timer instance | |
3755 * @retval State of bit (1 or 0). | |
3756 */ | |
3757 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) | |
3758 { | |
3759 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); | |
3760 } | |
3761 | |
3762 /** | |
3763 * @brief Enable commutation DMA request (COMDE). | |
3764 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM | |
3765 * @param TIMx Timer instance | |
3766 * @retval None | |
3767 */ | |
3768 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) | |
3769 { | |
3770 SET_BIT(TIMx->DIER, TIM_DIER_COMDE); | |
3771 } | |
3772 | |
3773 /** | |
3774 * @brief Disable commutation DMA request (COMDE). | |
3775 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM | |
3776 * @param TIMx Timer instance | |
3777 * @retval None | |
3778 */ | |
3779 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) | |
3780 { | |
3781 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); | |
3782 } | |
3783 | |
3784 /** | |
3785 * @brief Indicates whether the commutation DMA request (COMDE) is enabled. | |
3786 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM | |
3787 * @param TIMx Timer instance | |
3788 * @retval State of bit (1 or 0). | |
3789 */ | |
3790 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) | |
3791 { | |
3792 return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); | |
3793 } | |
3794 | |
3795 /** | |
3796 * @brief Enable trigger interrupt (TDE). | |
3797 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG | |
3798 * @param TIMx Timer instance | |
3799 * @retval None | |
3800 */ | |
3801 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) | |
3802 { | |
3803 SET_BIT(TIMx->DIER, TIM_DIER_TDE); | |
3804 } | |
3805 | |
3806 /** | |
3807 * @brief Disable trigger interrupt (TDE). | |
3808 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG | |
3809 * @param TIMx Timer instance | |
3810 * @retval None | |
3811 */ | |
3812 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) | |
3813 { | |
3814 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); | |
3815 } | |
3816 | |
3817 /** | |
3818 * @brief Indicates whether the trigger interrupt (TDE) is enabled. | |
3819 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG | |
3820 * @param TIMx Timer instance | |
3821 * @retval State of bit (1 or 0). | |
3822 */ | |
3823 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) | |
3824 { | |
3825 return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); | |
3826 } | |
3827 | |
3828 /** | |
3829 * @} | |
3830 */ | |
3831 | |
3832 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management | |
3833 * @{ | |
3834 */ | |
3835 /** | |
3836 * @brief Generate an update event. | |
3837 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE | |
3838 * @param TIMx Timer instance | |
3839 * @retval None | |
3840 */ | |
3841 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) | |
3842 { | |
3843 SET_BIT(TIMx->EGR, TIM_EGR_UG); | |
3844 } | |
3845 | |
3846 /** | |
3847 * @brief Generate Capture/Compare 1 event. | |
3848 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 | |
3849 * @param TIMx Timer instance | |
3850 * @retval None | |
3851 */ | |
3852 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) | |
3853 { | |
3854 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); | |
3855 } | |
3856 | |
3857 /** | |
3858 * @brief Generate Capture/Compare 2 event. | |
3859 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 | |
3860 * @param TIMx Timer instance | |
3861 * @retval None | |
3862 */ | |
3863 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) | |
3864 { | |
3865 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); | |
3866 } | |
3867 | |
3868 /** | |
3869 * @brief Generate Capture/Compare 3 event. | |
3870 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 | |
3871 * @param TIMx Timer instance | |
3872 * @retval None | |
3873 */ | |
3874 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) | |
3875 { | |
3876 SET_BIT(TIMx->EGR, TIM_EGR_CC3G); | |
3877 } | |
3878 | |
3879 /** | |
3880 * @brief Generate Capture/Compare 4 event. | |
3881 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 | |
3882 * @param TIMx Timer instance | |
3883 * @retval None | |
3884 */ | |
3885 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) | |
3886 { | |
3887 SET_BIT(TIMx->EGR, TIM_EGR_CC4G); | |
3888 } | |
3889 | |
3890 /** | |
3891 * @brief Generate commutation event. | |
3892 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM | |
3893 * @param TIMx Timer instance | |
3894 * @retval None | |
3895 */ | |
3896 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) | |
3897 { | |
3898 SET_BIT(TIMx->EGR, TIM_EGR_COMG); | |
3899 } | |
3900 | |
3901 /** | |
3902 * @brief Generate trigger event. | |
3903 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG | |
3904 * @param TIMx Timer instance | |
3905 * @retval None | |
3906 */ | |
3907 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) | |
3908 { | |
3909 SET_BIT(TIMx->EGR, TIM_EGR_TG); | |
3910 } | |
3911 | |
3912 /** | |
3913 * @brief Generate break event. | |
3914 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK | |
3915 * @param TIMx Timer instance | |
3916 * @retval None | |
3917 */ | |
3918 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) | |
3919 { | |
3920 SET_BIT(TIMx->EGR, TIM_EGR_BG); | |
3921 } | |
3922 | |
3923 /** | |
3924 * @} | |
3925 */ | |
3926 | |
3927 #if defined(USE_FULL_LL_DRIVER) | |
3928 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions | |
3929 * @{ | |
3930 */ | |
3931 | |
3932 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); | |
3933 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); | |
3934 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); | |
3935 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); | |
3936 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); | |
3937 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); | |
3938 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); | |
3939 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); | |
3940 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); | |
3941 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); | |
3942 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); | |
3943 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); | |
3944 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); | |
3945 /** | |
3946 * @} | |
3947 */ | |
3948 #endif /* USE_FULL_LL_DRIVER */ | |
3949 | |
3950 /** | |
3951 * @} | |
3952 */ | |
3953 | |
3954 /** | |
3955 * @} | |
3956 */ | |
3957 | |
3958 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */ | |
3959 | |
3960 /** | |
3961 * @} | |
3962 */ | |
3963 | |
3964 #ifdef __cplusplus | |
3965 } | |
3966 #endif | |
3967 | |
3968 #endif /* __STM32F4xx_LL_TIM_H */ | |
3969 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |