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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_LL_SPI_H
38 #define __STM32F4xx_LL_SPI_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx.h"
46
47 /** @addtogroup STM32F4xx_LL_Driver
48 * @{
49 */
50
51 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
52
53 /** @defgroup SPI_LL SPI
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private macros ------------------------------------------------------------*/
60
61 /* Exported types ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
64 * @{
65 */
66
67 /**
68 * @brief SPI Init structures definition
69 */
70 typedef struct
71 {
72 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
73 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
74
75 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
76
77 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
78 This parameter can be a value of @ref SPI_LL_EC_MODE.
79
80 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
81
82 uint32_t DataWidth; /*!< Specifies the SPI data width.
83 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
84
85 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
86
87 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
88 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
89
90 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
91
92 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
93 This parameter can be a value of @ref SPI_LL_EC_PHASE.
94
95 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
96
97 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
98 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
99
100 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
101
102 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
103 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
104 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
105
106 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
107
108 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
109 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
110
111 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
112
113 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
114 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
115
116 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
117
118 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
120
121 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
122
123 } LL_SPI_InitTypeDef;
124
125 /**
126 * @}
127 */
128 #endif /* USE_FULL_LL_DRIVER */
129
130 /* Exported constants --------------------------------------------------------*/
131 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
132 * @{
133 */
134
135 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
136 * @brief Flags defines which can be used with LL_SPI_ReadReg function
137 * @{
138 */
139 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
140 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
141 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
142 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
143 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
144 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
145 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
146 /**
147 * @}
148 */
149
150 /** @defgroup SPI_LL_EC_IT IT Defines
151 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
152 * @{
153 */
154 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
155 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
156 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
157 /**
158 * @}
159 */
160
161 /** @defgroup SPI_LL_EC_MODE Operation Mode
162 * @{
163 */
164 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
165 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
166 /**
167 * @}
168 */
169
170 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
171 * @{
172 */
173 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
174 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
175 /**
176 * @}
177 */
178
179 /** @defgroup SPI_LL_EC_PHASE Clock Phase
180 * @{
181 */
182 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
183 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
184 /**
185 * @}
186 */
187
188 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
189 * @{
190 */
191 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
192 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
193 /**
194 * @}
195 */
196
197 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
198 * @{
199 */
200 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
201 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
202 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
203 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
204 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
205 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
206 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
207 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
208 /**
209 * @}
210 */
211
212 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
213 * @{
214 */
215 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
216 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
217 /**
218 * @}
219 */
220
221 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
222 * @{
223 */
224 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
225 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
226 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
227 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
228 /**
229 * @}
230 */
231
232 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
233 * @{
234 */
235 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
236 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
237 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
238 /**
239 * @}
240 */
241
242 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
243 * @{
244 */
245 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
246 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
247 /**
248 * @}
249 */
250 #if defined(USE_FULL_LL_DRIVER)
251
252 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
253 * @{
254 */
255 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
256 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
257 /**
258 * @}
259 */
260 #endif /* USE_FULL_LL_DRIVER */
261
262 /**
263 * @}
264 */
265
266 /* Exported macro ------------------------------------------------------------*/
267 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
268 * @{
269 */
270
271 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
272 * @{
273 */
274
275 /**
276 * @brief Write a value in SPI register
277 * @param __INSTANCE__ SPI Instance
278 * @param __REG__ Register to be written
279 * @param __VALUE__ Value to be written in the register
280 * @retval None
281 */
282 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
283
284 /**
285 * @brief Read a value in SPI register
286 * @param __INSTANCE__ SPI Instance
287 * @param __REG__ Register to be read
288 * @retval Register value
289 */
290 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
291 /**
292 * @}
293 */
294
295 /**
296 * @}
297 */
298
299 /* Exported functions --------------------------------------------------------*/
300 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
301 * @{
302 */
303
304 /** @defgroup SPI_LL_EF_Configuration Configuration
305 * @{
306 */
307
308 /**
309 * @brief Enable SPI peripheral
310 * @rmtoll CR1 SPE LL_SPI_Enable
311 * @param SPIx SPI Instance
312 * @retval None
313 */
314 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
315 {
316 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
317 }
318
319 /**
320 * @brief Disable SPI peripheral
321 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
322 * @rmtoll CR1 SPE LL_SPI_Disable
323 * @param SPIx SPI Instance
324 * @retval None
325 */
326 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
327 {
328 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
329 }
330
331 /**
332 * @brief Check if SPI peripheral is enabled
333 * @rmtoll CR1 SPE LL_SPI_IsEnabled
334 * @param SPIx SPI Instance
335 * @retval State of bit (1 or 0).
336 */
337 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
338 {
339 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
340 }
341
342 /**
343 * @brief Set SPI operation mode to Master or Slave
344 * @note This bit should not be changed when communication is ongoing.
345 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
346 * CR1 SSI LL_SPI_SetMode
347 * @param SPIx SPI Instance
348 * @param Mode This parameter can be one of the following values:
349 * @arg @ref LL_SPI_MODE_MASTER
350 * @arg @ref LL_SPI_MODE_SLAVE
351 * @retval None
352 */
353 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
354 {
355 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
356 }
357
358 /**
359 * @brief Get SPI operation mode (Master or Slave)
360 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
361 * CR1 SSI LL_SPI_GetMode
362 * @param SPIx SPI Instance
363 * @retval Returned value can be one of the following values:
364 * @arg @ref LL_SPI_MODE_MASTER
365 * @arg @ref LL_SPI_MODE_SLAVE
366 */
367 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
368 {
369 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
370 }
371
372 /**
373 * @brief Set serial protocol used
374 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
375 * @rmtoll CR2 FRF LL_SPI_SetStandard
376 * @param SPIx SPI Instance
377 * @param Standard This parameter can be one of the following values:
378 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
379 * @arg @ref LL_SPI_PROTOCOL_TI
380 * @retval None
381 */
382 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
383 {
384 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
385 }
386
387 /**
388 * @brief Get serial protocol used
389 * @rmtoll CR2 FRF LL_SPI_GetStandard
390 * @param SPIx SPI Instance
391 * @retval Returned value can be one of the following values:
392 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
393 * @arg @ref LL_SPI_PROTOCOL_TI
394 */
395 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
396 {
397 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
398 }
399
400 /**
401 * @brief Set clock phase
402 * @note This bit should not be changed when communication is ongoing.
403 * This bit is not used in SPI TI mode.
404 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
405 * @param SPIx SPI Instance
406 * @param ClockPhase This parameter can be one of the following values:
407 * @arg @ref LL_SPI_PHASE_1EDGE
408 * @arg @ref LL_SPI_PHASE_2EDGE
409 * @retval None
410 */
411 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
412 {
413 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
414 }
415
416 /**
417 * @brief Get clock phase
418 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
419 * @param SPIx SPI Instance
420 * @retval Returned value can be one of the following values:
421 * @arg @ref LL_SPI_PHASE_1EDGE
422 * @arg @ref LL_SPI_PHASE_2EDGE
423 */
424 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
425 {
426 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
427 }
428
429 /**
430 * @brief Set clock polarity
431 * @note This bit should not be changed when communication is ongoing.
432 * This bit is not used in SPI TI mode.
433 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
434 * @param SPIx SPI Instance
435 * @param ClockPolarity This parameter can be one of the following values:
436 * @arg @ref LL_SPI_POLARITY_LOW
437 * @arg @ref LL_SPI_POLARITY_HIGH
438 * @retval None
439 */
440 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
441 {
442 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
443 }
444
445 /**
446 * @brief Get clock polarity
447 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
448 * @param SPIx SPI Instance
449 * @retval Returned value can be one of the following values:
450 * @arg @ref LL_SPI_POLARITY_LOW
451 * @arg @ref LL_SPI_POLARITY_HIGH
452 */
453 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
454 {
455 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
456 }
457
458 /**
459 * @brief Set baud rate prescaler
460 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
461 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
462 * @param SPIx SPI Instance
463 * @param BaudRate This parameter can be one of the following values:
464 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
465 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
466 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
467 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
468 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
469 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
470 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
471 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
472 * @retval None
473 */
474 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
475 {
476 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
477 }
478
479 /**
480 * @brief Get baud rate prescaler
481 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
482 * @param SPIx SPI Instance
483 * @retval Returned value can be one of the following values:
484 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
485 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
486 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
487 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
488 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
489 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
490 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
491 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
492 */
493 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
494 {
495 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
496 }
497
498 /**
499 * @brief Set transfer bit order
500 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
501 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
502 * @param SPIx SPI Instance
503 * @param BitOrder This parameter can be one of the following values:
504 * @arg @ref LL_SPI_LSB_FIRST
505 * @arg @ref LL_SPI_MSB_FIRST
506 * @retval None
507 */
508 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
509 {
510 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
511 }
512
513 /**
514 * @brief Get transfer bit order
515 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
516 * @param SPIx SPI Instance
517 * @retval Returned value can be one of the following values:
518 * @arg @ref LL_SPI_LSB_FIRST
519 * @arg @ref LL_SPI_MSB_FIRST
520 */
521 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
522 {
523 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
524 }
525
526 /**
527 * @brief Set transfer direction mode
528 * @note For Half-Duplex mode, Rx Direction is set by default.
529 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
530 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
531 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
532 * CR1 BIDIOE LL_SPI_SetTransferDirection
533 * @param SPIx SPI Instance
534 * @param TransferDirection This parameter can be one of the following values:
535 * @arg @ref LL_SPI_FULL_DUPLEX
536 * @arg @ref LL_SPI_SIMPLEX_RX
537 * @arg @ref LL_SPI_HALF_DUPLEX_RX
538 * @arg @ref LL_SPI_HALF_DUPLEX_TX
539 * @retval None
540 */
541 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
542 {
543 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
544 }
545
546 /**
547 * @brief Get transfer direction mode
548 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
549 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
550 * CR1 BIDIOE LL_SPI_GetTransferDirection
551 * @param SPIx SPI Instance
552 * @retval Returned value can be one of the following values:
553 * @arg @ref LL_SPI_FULL_DUPLEX
554 * @arg @ref LL_SPI_SIMPLEX_RX
555 * @arg @ref LL_SPI_HALF_DUPLEX_RX
556 * @arg @ref LL_SPI_HALF_DUPLEX_TX
557 */
558 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
559 {
560 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
561 }
562
563 /**
564 * @brief Set frame data width
565 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
566 * @param SPIx SPI Instance
567 * @param DataWidth This parameter can be one of the following values:
568 * @arg @ref LL_SPI_DATAWIDTH_8BIT
569 * @arg @ref LL_SPI_DATAWIDTH_16BIT
570 * @retval None
571 */
572 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
573 {
574 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
575 }
576
577 /**
578 * @brief Get frame data width
579 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
580 * @param SPIx SPI Instance
581 * @retval Returned value can be one of the following values:
582 * @arg @ref LL_SPI_DATAWIDTH_8BIT
583 * @arg @ref LL_SPI_DATAWIDTH_16BIT
584 */
585 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
586 {
587 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
588 }
589
590 /**
591 * @}
592 */
593
594 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
595 * @{
596 */
597
598 /**
599 * @brief Enable CRC
600 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
601 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
602 * @param SPIx SPI Instance
603 * @retval None
604 */
605 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
606 {
607 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
608 }
609
610 /**
611 * @brief Disable CRC
612 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
613 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
614 * @param SPIx SPI Instance
615 * @retval None
616 */
617 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
618 {
619 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
620 }
621
622 /**
623 * @brief Check if CRC is enabled
624 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
625 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
626 * @param SPIx SPI Instance
627 * @retval State of bit (1 or 0).
628 */
629 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
630 {
631 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
632 }
633
634 /**
635 * @brief Set CRCNext to transfer CRC on the line
636 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
637 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
638 * @param SPIx SPI Instance
639 * @retval None
640 */
641 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
642 {
643 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
644 }
645
646 /**
647 * @brief Set polynomial for CRC calculation
648 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
649 * @param SPIx SPI Instance
650 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
651 * @retval None
652 */
653 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
654 {
655 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
656 }
657
658 /**
659 * @brief Get polynomial for CRC calculation
660 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
661 * @param SPIx SPI Instance
662 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
663 */
664 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
665 {
666 return (uint32_t)(READ_REG(SPIx->CRCPR));
667 }
668
669 /**
670 * @brief Get Rx CRC
671 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
672 * @param SPIx SPI Instance
673 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
674 */
675 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
676 {
677 return (uint32_t)(READ_REG(SPIx->RXCRCR));
678 }
679
680 /**
681 * @brief Get Tx CRC
682 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
683 * @param SPIx SPI Instance
684 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
685 */
686 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
687 {
688 return (uint32_t)(READ_REG(SPIx->TXCRCR));
689 }
690
691 /**
692 * @}
693 */
694
695 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
696 * @{
697 */
698
699 /**
700 * @brief Set NSS mode
701 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
702 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
703 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
704 * @param SPIx SPI Instance
705 * @param NSS This parameter can be one of the following values:
706 * @arg @ref LL_SPI_NSS_SOFT
707 * @arg @ref LL_SPI_NSS_HARD_INPUT
708 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
709 * @retval None
710 */
711 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
712 {
713 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
714 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
715 }
716
717 /**
718 * @brief Get NSS mode
719 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
720 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
721 * @param SPIx SPI Instance
722 * @retval Returned value can be one of the following values:
723 * @arg @ref LL_SPI_NSS_SOFT
724 * @arg @ref LL_SPI_NSS_HARD_INPUT
725 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
726 */
727 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
728 {
729 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
730 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
731 return (Ssm | Ssoe);
732 }
733
734 /**
735 * @}
736 */
737
738 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
739 * @{
740 */
741
742 /**
743 * @brief Check if Rx buffer is not empty
744 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
745 * @param SPIx SPI Instance
746 * @retval State of bit (1 or 0).
747 */
748 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
749 {
750 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
751 }
752
753 /**
754 * @brief Check if Tx buffer is empty
755 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
756 * @param SPIx SPI Instance
757 * @retval State of bit (1 or 0).
758 */
759 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
760 {
761 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
762 }
763
764 /**
765 * @brief Get CRC error flag
766 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
767 * @param SPIx SPI Instance
768 * @retval State of bit (1 or 0).
769 */
770 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
771 {
772 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
773 }
774
775 /**
776 * @brief Get mode fault error flag
777 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
778 * @param SPIx SPI Instance
779 * @retval State of bit (1 or 0).
780 */
781 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
782 {
783 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
784 }
785
786 /**
787 * @brief Get overrun error flag
788 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
789 * @param SPIx SPI Instance
790 * @retval State of bit (1 or 0).
791 */
792 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
793 {
794 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
795 }
796
797 /**
798 * @brief Get busy flag
799 * @note The BSY flag is cleared under any one of the following conditions:
800 * -When the SPI is correctly disabled
801 * -When a fault is detected in Master mode (MODF bit set to 1)
802 * -In Master mode, when it finishes a data transmission and no new data is ready to be
803 * sent
804 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
805 * each data transfer.
806 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
807 * @param SPIx SPI Instance
808 * @retval State of bit (1 or 0).
809 */
810 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
811 {
812 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
813 }
814
815 /**
816 * @brief Get frame format error flag
817 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
818 * @param SPIx SPI Instance
819 * @retval State of bit (1 or 0).
820 */
821 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
822 {
823 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
824 }
825
826 /**
827 * @brief Clear CRC error flag
828 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
829 * @param SPIx SPI Instance
830 * @retval None
831 */
832 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
833 {
834 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
835 }
836
837 /**
838 * @brief Clear mode fault error flag
839 * @note Clearing this flag is done by a read access to the SPIx_SR
840 * register followed by a write access to the SPIx_CR1 register
841 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
842 * @param SPIx SPI Instance
843 * @retval None
844 */
845 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
846 {
847 __IO uint32_t tmpreg;
848 tmpreg = SPIx->SR;
849 (void) tmpreg;
850 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
851 (void) tmpreg;
852 }
853
854 /**
855 * @brief Clear overrun error flag
856 * @note Clearing this flag is done by a read access to the SPIx_DR
857 * register followed by a read access to the SPIx_SR register
858 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
859 * @param SPIx SPI Instance
860 * @retval None
861 */
862 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
863 {
864 __IO uint32_t tmpreg;
865 tmpreg = SPIx->DR;
866 (void) tmpreg;
867 tmpreg = SPIx->SR;
868 (void) tmpreg;
869 }
870
871 /**
872 * @brief Clear frame format error flag
873 * @note Clearing this flag is done by reading SPIx_SR register
874 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
875 * @param SPIx SPI Instance
876 * @retval None
877 */
878 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
879 {
880 __IO uint32_t tmpreg;
881 tmpreg = SPIx->SR;
882 (void) tmpreg;
883 }
884
885 /**
886 * @}
887 */
888
889 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
890 * @{
891 */
892
893 /**
894 * @brief Enable error interrupt
895 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
896 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
897 * @param SPIx SPI Instance
898 * @retval None
899 */
900 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
901 {
902 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
903 }
904
905 /**
906 * @brief Enable Rx buffer not empty interrupt
907 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
908 * @param SPIx SPI Instance
909 * @retval None
910 */
911 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
912 {
913 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
914 }
915
916 /**
917 * @brief Enable Tx buffer empty interrupt
918 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
919 * @param SPIx SPI Instance
920 * @retval None
921 */
922 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
923 {
924 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
925 }
926
927 /**
928 * @brief Disable error interrupt
929 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
930 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
931 * @param SPIx SPI Instance
932 * @retval None
933 */
934 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
935 {
936 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
937 }
938
939 /**
940 * @brief Disable Rx buffer not empty interrupt
941 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
942 * @param SPIx SPI Instance
943 * @retval None
944 */
945 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
946 {
947 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
948 }
949
950 /**
951 * @brief Disable Tx buffer empty interrupt
952 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
953 * @param SPIx SPI Instance
954 * @retval None
955 */
956 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
957 {
958 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
959 }
960
961 /**
962 * @brief Check if error interrupt is enabled
963 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
964 * @param SPIx SPI Instance
965 * @retval State of bit (1 or 0).
966 */
967 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
968 {
969 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
970 }
971
972 /**
973 * @brief Check if Rx buffer not empty interrupt is enabled
974 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
975 * @param SPIx SPI Instance
976 * @retval State of bit (1 or 0).
977 */
978 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
979 {
980 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
981 }
982
983 /**
984 * @brief Check if Tx buffer empty interrupt
985 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
986 * @param SPIx SPI Instance
987 * @retval State of bit (1 or 0).
988 */
989 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
990 {
991 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
992 }
993
994 /**
995 * @}
996 */
997
998 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
999 * @{
1000 */
1001
1002 /**
1003 * @brief Enable DMA Rx
1004 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
1005 * @param SPIx SPI Instance
1006 * @retval None
1007 */
1008 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1009 {
1010 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1011 }
1012
1013 /**
1014 * @brief Disable DMA Rx
1015 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
1016 * @param SPIx SPI Instance
1017 * @retval None
1018 */
1019 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1020 {
1021 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1022 }
1023
1024 /**
1025 * @brief Check if DMA Rx is enabled
1026 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
1027 * @param SPIx SPI Instance
1028 * @retval State of bit (1 or 0).
1029 */
1030 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1031 {
1032 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
1033 }
1034
1035 /**
1036 * @brief Enable DMA Tx
1037 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
1038 * @param SPIx SPI Instance
1039 * @retval None
1040 */
1041 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1042 {
1043 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1044 }
1045
1046 /**
1047 * @brief Disable DMA Tx
1048 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1049 * @param SPIx SPI Instance
1050 * @retval None
1051 */
1052 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1053 {
1054 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1055 }
1056
1057 /**
1058 * @brief Check if DMA Tx is enabled
1059 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1060 * @param SPIx SPI Instance
1061 * @retval State of bit (1 or 0).
1062 */
1063 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1064 {
1065 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
1066 }
1067
1068 /**
1069 * @brief Get the data register address used for DMA transfer
1070 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1071 * @param SPIx SPI Instance
1072 * @retval Address of data register
1073 */
1074 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
1075 {
1076 return (uint32_t) & (SPIx->DR);
1077 }
1078
1079 /**
1080 * @}
1081 */
1082
1083 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1084 * @{
1085 */
1086
1087 /**
1088 * @brief Read 8-Bits in the data register
1089 * @rmtoll DR DR LL_SPI_ReceiveData8
1090 * @param SPIx SPI Instance
1091 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1092 */
1093 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1094 {
1095 return (uint8_t)(READ_REG(SPIx->DR));
1096 }
1097
1098 /**
1099 * @brief Read 16-Bits in the data register
1100 * @rmtoll DR DR LL_SPI_ReceiveData16
1101 * @param SPIx SPI Instance
1102 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1103 */
1104 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1105 {
1106 return (uint16_t)(READ_REG(SPIx->DR));
1107 }
1108
1109 /**
1110 * @brief Write 8-Bits in the data register
1111 * @rmtoll DR DR LL_SPI_TransmitData8
1112 * @param SPIx SPI Instance
1113 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1114 * @retval None
1115 */
1116 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1117 {
1118 SPIx->DR = TxData;
1119 }
1120
1121 /**
1122 * @brief Write 16-Bits in the data register
1123 * @rmtoll DR DR LL_SPI_TransmitData16
1124 * @param SPIx SPI Instance
1125 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1126 * @retval None
1127 */
1128 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1129 {
1130 SPIx->DR = TxData;
1131 }
1132
1133 /**
1134 * @}
1135 */
1136 #if defined(USE_FULL_LL_DRIVER)
1137 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1138 * @{
1139 */
1140
1141 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
1142 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1143 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1144
1145 /**
1146 * @}
1147 */
1148 #endif /* USE_FULL_LL_DRIVER */
1149 /**
1150 * @}
1151 */
1152
1153 /**
1154 * @}
1155 */
1156
1157 /** @defgroup I2S_LL I2S
1158 * @{
1159 */
1160
1161 /* Private variables ---------------------------------------------------------*/
1162 /* Private constants ---------------------------------------------------------*/
1163 /* Private macros ------------------------------------------------------------*/
1164
1165 /* Exported types ------------------------------------------------------------*/
1166 #if defined(USE_FULL_LL_DRIVER)
1167 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1168 * @{
1169 */
1170
1171 /**
1172 * @brief I2S Init structure definition
1173 */
1174
1175 typedef struct
1176 {
1177 uint32_t Mode; /*!< Specifies the I2S operating mode.
1178 This parameter can be a value of @ref I2S_LL_EC_MODE
1179
1180 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1181
1182 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1183 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1184
1185 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1186
1187
1188 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1189 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1190
1191 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1192
1193
1194 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1195 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1196
1197 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1198
1199
1200 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1201 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1202
1203 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1204 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1205
1206
1207 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1208 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1209
1210 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1211
1212 } LL_I2S_InitTypeDef;
1213
1214 /**
1215 * @}
1216 */
1217 #endif /*USE_FULL_LL_DRIVER*/
1218
1219 /* Exported constants --------------------------------------------------------*/
1220 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1221 * @{
1222 */
1223
1224 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1225 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1226 * @{
1227 */
1228 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1229 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1230 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1231 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1232 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1233 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1234 /**
1235 * @}
1236 */
1237
1238 /** @defgroup SPI_LL_EC_IT IT Defines
1239 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1240 * @{
1241 */
1242 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1243 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1244 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1245 /**
1246 * @}
1247 */
1248
1249 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1250 * @{
1251 */
1252 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
1253 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
1254 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
1255 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
1256 /**
1257 * @}
1258 */
1259
1260 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1261 * @{
1262 */
1263 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1264 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1265 /**
1266 * @}
1267 */
1268
1269 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1270 * @{
1271 */
1272 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1273 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1274 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1275 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1276 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1277 /**
1278 * @}
1279 */
1280
1281 /** @defgroup I2S_LL_EC_MODE Operation Mode
1282 * @{
1283 */
1284 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1285 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1286 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1287 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1288 /**
1289 * @}
1290 */
1291
1292 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1293 * @{
1294 */
1295 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1296 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1297 /**
1298 * @}
1299 */
1300
1301 #if defined(USE_FULL_LL_DRIVER)
1302
1303 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1304 * @{
1305 */
1306 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1307 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1308 /**
1309 * @}
1310 */
1311
1312 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1313 * @{
1314 */
1315
1316 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1317 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1318 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1319 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1320 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1321 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1322 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1323 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1324 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1325 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1326 /**
1327 * @}
1328 */
1329 #endif /* USE_FULL_LL_DRIVER */
1330
1331 /**
1332 * @}
1333 */
1334
1335 /* Exported macro ------------------------------------------------------------*/
1336 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1337 * @{
1338 */
1339
1340 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1341 * @{
1342 */
1343
1344 /**
1345 * @brief Write a value in I2S register
1346 * @param __INSTANCE__ I2S Instance
1347 * @param __REG__ Register to be written
1348 * @param __VALUE__ Value to be written in the register
1349 * @retval None
1350 */
1351 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1352
1353 /**
1354 * @brief Read a value in I2S register
1355 * @param __INSTANCE__ I2S Instance
1356 * @param __REG__ Register to be read
1357 * @retval Register value
1358 */
1359 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1360 /**
1361 * @}
1362 */
1363
1364 /**
1365 * @}
1366 */
1367
1368
1369 /* Exported functions --------------------------------------------------------*/
1370
1371 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1372 * @{
1373 */
1374
1375 /** @defgroup I2S_LL_EF_Configuration Configuration
1376 * @{
1377 */
1378
1379 /**
1380 * @brief Select I2S mode and Enable I2S peripheral
1381 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1382 * I2SCFGR I2SE LL_I2S_Enable
1383 * @param SPIx SPI Instance
1384 * @retval None
1385 */
1386 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1387 {
1388 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1389 }
1390
1391 /**
1392 * @brief Disable I2S peripheral
1393 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1394 * @param SPIx SPI Instance
1395 * @retval None
1396 */
1397 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1398 {
1399 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1400 }
1401
1402 /**
1403 * @brief Check if I2S peripheral is enabled
1404 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1405 * @param SPIx SPI Instance
1406 * @retval State of bit (1 or 0).
1407 */
1408 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
1409 {
1410 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
1411 }
1412
1413 /**
1414 * @brief Set I2S data frame length
1415 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1416 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1417 * @param SPIx SPI Instance
1418 * @param DataFormat This parameter can be one of the following values:
1419 * @arg @ref LL_I2S_DATAFORMAT_16B
1420 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1421 * @arg @ref LL_I2S_DATAFORMAT_24B
1422 * @arg @ref LL_I2S_DATAFORMAT_32B
1423 * @retval None
1424 */
1425 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1426 {
1427 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1428 }
1429
1430 /**
1431 * @brief Get I2S data frame length
1432 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1433 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1434 * @param SPIx SPI Instance
1435 * @retval Returned value can be one of the following values:
1436 * @arg @ref LL_I2S_DATAFORMAT_16B
1437 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1438 * @arg @ref LL_I2S_DATAFORMAT_24B
1439 * @arg @ref LL_I2S_DATAFORMAT_32B
1440 */
1441 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
1442 {
1443 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1444 }
1445
1446 /**
1447 * @brief Set I2S clock polarity
1448 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1449 * @param SPIx SPI Instance
1450 * @param ClockPolarity This parameter can be one of the following values:
1451 * @arg @ref LL_I2S_POLARITY_LOW
1452 * @arg @ref LL_I2S_POLARITY_HIGH
1453 * @retval None
1454 */
1455 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1456 {
1457 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1458 }
1459
1460 /**
1461 * @brief Get I2S clock polarity
1462 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1463 * @param SPIx SPI Instance
1464 * @retval Returned value can be one of the following values:
1465 * @arg @ref LL_I2S_POLARITY_LOW
1466 * @arg @ref LL_I2S_POLARITY_HIGH
1467 */
1468 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
1469 {
1470 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1471 }
1472
1473 /**
1474 * @brief Set I2S standard protocol
1475 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1476 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1477 * @param SPIx SPI Instance
1478 * @param Standard This parameter can be one of the following values:
1479 * @arg @ref LL_I2S_STANDARD_PHILIPS
1480 * @arg @ref LL_I2S_STANDARD_MSB
1481 * @arg @ref LL_I2S_STANDARD_LSB
1482 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1483 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1484 * @retval None
1485 */
1486 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1487 {
1488 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1489 }
1490
1491 /**
1492 * @brief Get I2S standard protocol
1493 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1494 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1495 * @param SPIx SPI Instance
1496 * @retval Returned value can be one of the following values:
1497 * @arg @ref LL_I2S_STANDARD_PHILIPS
1498 * @arg @ref LL_I2S_STANDARD_MSB
1499 * @arg @ref LL_I2S_STANDARD_LSB
1500 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1501 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1502 */
1503 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
1504 {
1505 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1506 }
1507
1508 /**
1509 * @brief Set I2S transfer mode
1510 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1511 * @param SPIx SPI Instance
1512 * @param Mode This parameter can be one of the following values:
1513 * @arg @ref LL_I2S_MODE_SLAVE_TX
1514 * @arg @ref LL_I2S_MODE_SLAVE_RX
1515 * @arg @ref LL_I2S_MODE_MASTER_TX
1516 * @arg @ref LL_I2S_MODE_MASTER_RX
1517 * @retval None
1518 */
1519 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1520 {
1521 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1522 }
1523
1524 /**
1525 * @brief Get I2S transfer mode
1526 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1527 * @param SPIx SPI Instance
1528 * @retval Returned value can be one of the following values:
1529 * @arg @ref LL_I2S_MODE_SLAVE_TX
1530 * @arg @ref LL_I2S_MODE_SLAVE_RX
1531 * @arg @ref LL_I2S_MODE_MASTER_TX
1532 * @arg @ref LL_I2S_MODE_MASTER_RX
1533 */
1534 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
1535 {
1536 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1537 }
1538
1539 /**
1540 * @brief Set I2S linear prescaler
1541 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1542 * @param SPIx SPI Instance
1543 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1544 * @retval None
1545 */
1546 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1547 {
1548 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1549 }
1550
1551 /**
1552 * @brief Get I2S linear prescaler
1553 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1554 * @param SPIx SPI Instance
1555 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1556 */
1557 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
1558 {
1559 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1560 }
1561
1562 /**
1563 * @brief Set I2S parity prescaler
1564 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1565 * @param SPIx SPI Instance
1566 * @param PrescalerParity This parameter can be one of the following values:
1567 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1568 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1569 * @retval None
1570 */
1571 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1572 {
1573 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1574 }
1575
1576 /**
1577 * @brief Get I2S parity prescaler
1578 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1579 * @param SPIx SPI Instance
1580 * @retval Returned value can be one of the following values:
1581 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1582 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1583 */
1584 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
1585 {
1586 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1587 }
1588
1589 /**
1590 * @brief Enable the master clock ouput (Pin MCK)
1591 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1592 * @param SPIx SPI Instance
1593 * @retval None
1594 */
1595 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1596 {
1597 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1598 }
1599
1600 /**
1601 * @brief Disable the master clock ouput (Pin MCK)
1602 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1603 * @param SPIx SPI Instance
1604 * @retval None
1605 */
1606 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1607 {
1608 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1609 }
1610
1611 /**
1612 * @brief Check if the master clock ouput (Pin MCK) is enabled
1613 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1614 * @param SPIx SPI Instance
1615 * @retval State of bit (1 or 0).
1616 */
1617 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
1618 {
1619 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
1620 }
1621
1622 #if defined(SPI_I2SCFGR_ASTRTEN)
1623 /**
1624 * @brief Enable asynchronous start
1625 * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
1626 * @param SPIx SPI Instance
1627 * @retval None
1628 */
1629 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
1630 {
1631 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1632 }
1633
1634 /**
1635 * @brief Disable asynchronous start
1636 * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
1637 * @param SPIx SPI Instance
1638 * @retval None
1639 */
1640 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
1641 {
1642 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1643 }
1644
1645 /**
1646 * @brief Check if asynchronous start is enabled
1647 * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
1648 * @param SPIx SPI Instance
1649 * @retval State of bit (1 or 0).
1650 */
1651 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
1652 {
1653 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
1654 }
1655 #endif /* SPI_I2SCFGR_ASTRTEN */
1656
1657 /**
1658 * @}
1659 */
1660
1661 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1662 * @{
1663 */
1664
1665 /**
1666 * @brief Check if Rx buffer is not empty
1667 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1668 * @param SPIx SPI Instance
1669 * @retval State of bit (1 or 0).
1670 */
1671 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
1672 {
1673 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1674 }
1675
1676 /**
1677 * @brief Check if Tx buffer is empty
1678 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1679 * @param SPIx SPI Instance
1680 * @retval State of bit (1 or 0).
1681 */
1682 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
1683 {
1684 return LL_SPI_IsActiveFlag_TXE(SPIx);
1685 }
1686
1687 /**
1688 * @brief Get busy flag
1689 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1690 * @param SPIx SPI Instance
1691 * @retval State of bit (1 or 0).
1692 */
1693 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
1694 {
1695 return LL_SPI_IsActiveFlag_BSY(SPIx);
1696 }
1697
1698 /**
1699 * @brief Get overrun error flag
1700 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1701 * @param SPIx SPI Instance
1702 * @retval State of bit (1 or 0).
1703 */
1704 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1705 {
1706 return LL_SPI_IsActiveFlag_OVR(SPIx);
1707 }
1708
1709 /**
1710 * @brief Get underrun error flag
1711 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1712 * @param SPIx SPI Instance
1713 * @retval State of bit (1 or 0).
1714 */
1715 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1716 {
1717 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
1718 }
1719
1720 /**
1721 * @brief Get frame format error flag
1722 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
1723 * @param SPIx SPI Instance
1724 * @retval State of bit (1 or 0).
1725 */
1726 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1727 {
1728 return LL_SPI_IsActiveFlag_FRE(SPIx);
1729 }
1730
1731 /**
1732 * @brief Get channel side flag.
1733 * @note 0: Channel Left has to be transmitted or has been received\n
1734 * 1: Channel Right has to be transmitted or has been received\n
1735 * It has no significance in PCM mode.
1736 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1737 * @param SPIx SPI Instance
1738 * @retval State of bit (1 or 0).
1739 */
1740 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
1741 {
1742 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
1743 }
1744
1745 /**
1746 * @brief Clear overrun error flag
1747 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1748 * @param SPIx SPI Instance
1749 * @retval None
1750 */
1751 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1752 {
1753 LL_SPI_ClearFlag_OVR(SPIx);
1754 }
1755
1756 /**
1757 * @brief Clear underrun error flag
1758 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
1759 * @param SPIx SPI Instance
1760 * @retval None
1761 */
1762 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
1763 {
1764 __IO uint32_t tmpreg;
1765 tmpreg = SPIx->SR;
1766 (void)tmpreg;
1767 }
1768
1769 /**
1770 * @brief Clear frame format error flag
1771 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
1772 * @param SPIx SPI Instance
1773 * @retval None
1774 */
1775 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
1776 {
1777 LL_SPI_ClearFlag_FRE(SPIx);
1778 }
1779
1780 /**
1781 * @}
1782 */
1783
1784 /** @defgroup I2S_LL_EF_IT Interrupt Management
1785 * @{
1786 */
1787
1788 /**
1789 * @brief Enable error IT
1790 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1791 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
1792 * @param SPIx SPI Instance
1793 * @retval None
1794 */
1795 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1796 {
1797 LL_SPI_EnableIT_ERR(SPIx);
1798 }
1799
1800 /**
1801 * @brief Enable Rx buffer not empty IT
1802 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
1803 * @param SPIx SPI Instance
1804 * @retval None
1805 */
1806 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1807 {
1808 LL_SPI_EnableIT_RXNE(SPIx);
1809 }
1810
1811 /**
1812 * @brief Enable Tx buffer empty IT
1813 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
1814 * @param SPIx SPI Instance
1815 * @retval None
1816 */
1817 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1818 {
1819 LL_SPI_EnableIT_TXE(SPIx);
1820 }
1821
1822 /**
1823 * @brief Disable error IT
1824 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1825 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
1826 * @param SPIx SPI Instance
1827 * @retval None
1828 */
1829 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1830 {
1831 LL_SPI_DisableIT_ERR(SPIx);
1832 }
1833
1834 /**
1835 * @brief Disable Rx buffer not empty IT
1836 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
1837 * @param SPIx SPI Instance
1838 * @retval None
1839 */
1840 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1841 {
1842 LL_SPI_DisableIT_RXNE(SPIx);
1843 }
1844
1845 /**
1846 * @brief Disable Tx buffer empty IT
1847 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
1848 * @param SPIx SPI Instance
1849 * @retval None
1850 */
1851 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1852 {
1853 LL_SPI_DisableIT_TXE(SPIx);
1854 }
1855
1856 /**
1857 * @brief Check if ERR IT is enabled
1858 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
1859 * @param SPIx SPI Instance
1860 * @retval State of bit (1 or 0).
1861 */
1862 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
1863 {
1864 return LL_SPI_IsEnabledIT_ERR(SPIx);
1865 }
1866
1867 /**
1868 * @brief Check if RXNE IT is enabled
1869 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
1870 * @param SPIx SPI Instance
1871 * @retval State of bit (1 or 0).
1872 */
1873 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
1874 {
1875 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1876 }
1877
1878 /**
1879 * @brief Check if TXE IT is enabled
1880 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
1881 * @param SPIx SPI Instance
1882 * @retval State of bit (1 or 0).
1883 */
1884 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
1885 {
1886 return LL_SPI_IsEnabledIT_TXE(SPIx);
1887 }
1888
1889 /**
1890 * @}
1891 */
1892
1893 /** @defgroup I2S_LL_EF_DMA DMA Management
1894 * @{
1895 */
1896
1897 /**
1898 * @brief Enable DMA Rx
1899 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
1900 * @param SPIx SPI Instance
1901 * @retval None
1902 */
1903 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1904 {
1905 LL_SPI_EnableDMAReq_RX(SPIx);
1906 }
1907
1908 /**
1909 * @brief Disable DMA Rx
1910 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
1911 * @param SPIx SPI Instance
1912 * @retval None
1913 */
1914 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1915 {
1916 LL_SPI_DisableDMAReq_RX(SPIx);
1917 }
1918
1919 /**
1920 * @brief Check if DMA Rx is enabled
1921 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
1922 * @param SPIx SPI Instance
1923 * @retval State of bit (1 or 0).
1924 */
1925 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1926 {
1927 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1928 }
1929
1930 /**
1931 * @brief Enable DMA Tx
1932 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
1933 * @param SPIx SPI Instance
1934 * @retval None
1935 */
1936 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1937 {
1938 LL_SPI_EnableDMAReq_TX(SPIx);
1939 }
1940
1941 /**
1942 * @brief Disable DMA Tx
1943 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
1944 * @param SPIx SPI Instance
1945 * @retval None
1946 */
1947 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1948 {
1949 LL_SPI_DisableDMAReq_TX(SPIx);
1950 }
1951
1952 /**
1953 * @brief Check if DMA Tx is enabled
1954 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
1955 * @param SPIx SPI Instance
1956 * @retval State of bit (1 or 0).
1957 */
1958 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1959 {
1960 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1961 }
1962
1963 /**
1964 * @}
1965 */
1966
1967 /** @defgroup I2S_LL_EF_DATA DATA Management
1968 * @{
1969 */
1970
1971 /**
1972 * @brief Read 16-Bits in data register
1973 * @rmtoll DR DR LL_I2S_ReceiveData16
1974 * @param SPIx SPI Instance
1975 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1976 */
1977 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1978 {
1979 return LL_SPI_ReceiveData16(SPIx);
1980 }
1981
1982 /**
1983 * @brief Write 16-Bits in data register
1984 * @rmtoll DR DR LL_I2S_TransmitData16
1985 * @param SPIx SPI Instance
1986 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1987 * @retval None
1988 */
1989 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1990 {
1991 LL_SPI_TransmitData16(SPIx, TxData);
1992 }
1993
1994 /**
1995 * @}
1996 */
1997
1998 #if defined(USE_FULL_LL_DRIVER)
1999 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
2000 * @{
2001 */
2002
2003 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
2004 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
2005 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
2006 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
2007 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
2008 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
2009 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
2010
2011 /**
2012 * @}
2013 */
2014 #endif /* USE_FULL_LL_DRIVER */
2015
2016 /**
2017 * @}
2018 */
2019
2020 /**
2021 * @}
2022 */
2023
2024 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
2025
2026 /**
2027 * @}
2028 */
2029
2030 #ifdef __cplusplus
2031 }
2032 #endif
2033
2034 #endif /* __STM32F4xx_LL_SPI_H */
2035
2036 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/