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comparison Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_sdmmc.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of SDMMC HAL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_LL_SDMMC_H | |
38 #define __STM32F4xx_LL_SDMMC_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ | |
45 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ | |
46 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ | |
47 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ | |
48 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) | |
49 | |
50 /* Includes ------------------------------------------------------------------*/ | |
51 #include "stm32f4xx_hal_def.h" | |
52 | |
53 /** @addtogroup STM32F4xx_Driver | |
54 * @{ | |
55 */ | |
56 | |
57 /** @addtogroup SDMMC_LL | |
58 * @{ | |
59 */ | |
60 | |
61 /* Exported types ------------------------------------------------------------*/ | |
62 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types | |
63 * @{ | |
64 */ | |
65 | |
66 /** | |
67 * @brief SDMMC Configuration Structure definition | |
68 */ | |
69 typedef struct | |
70 { | |
71 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. | |
72 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ | |
73 | |
74 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is | |
75 enabled or disabled. | |
76 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ | |
77 | |
78 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or | |
79 disabled when the bus is idle. | |
80 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ | |
81 | |
82 uint32_t BusWide; /*!< Specifies the SDMMC bus width. | |
83 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ | |
84 | |
85 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. | |
86 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ | |
87 | |
88 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. | |
89 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ | |
90 | |
91 }SDIO_InitTypeDef; | |
92 | |
93 | |
94 /** | |
95 * @brief SDMMC Command Control structure | |
96 */ | |
97 typedef struct | |
98 { | |
99 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent | |
100 to a card as part of a command message. If a command | |
101 contains an argument, it must be loaded into this register | |
102 before writing the command to the command register. */ | |
103 | |
104 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and | |
105 Max_Data = 64 */ | |
106 | |
107 uint32_t Response; /*!< Specifies the SDMMC response type. | |
108 This parameter can be a value of @ref SDMMC_LL_Response_Type */ | |
109 | |
110 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is | |
111 enabled or disabled. | |
112 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ | |
113 | |
114 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) | |
115 is enabled or disabled. | |
116 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ | |
117 }SDIO_CmdInitTypeDef; | |
118 | |
119 | |
120 /** | |
121 * @brief SDMMC Data Control structure | |
122 */ | |
123 typedef struct | |
124 { | |
125 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ | |
126 | |
127 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ | |
128 | |
129 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. | |
130 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ | |
131 | |
132 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer | |
133 is a read or write. | |
134 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ | |
135 | |
136 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. | |
137 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ | |
138 | |
139 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) | |
140 is enabled or disabled. | |
141 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ | |
142 }SDIO_DataInitTypeDef; | |
143 | |
144 /** | |
145 * @} | |
146 */ | |
147 | |
148 /* Exported constants --------------------------------------------------------*/ | |
149 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants | |
150 * @{ | |
151 */ | |
152 #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ | |
153 #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ | |
154 #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ | |
155 #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ | |
156 #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ | |
157 #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ | |
158 #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ | |
159 #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ | |
160 #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the | |
161 number of transferred bytes does not match the block length */ | |
162 #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ | |
163 #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ | |
164 #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ | |
165 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock | |
166 command or if there was an attempt to access a locked card */ | |
167 #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ | |
168 #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ | |
169 #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ | |
170 #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ | |
171 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ | |
172 #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ | |
173 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ | |
174 #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ | |
175 #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ | |
176 #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ | |
177 #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out | |
178 of erase sequence command was received */ | |
179 #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ | |
180 #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ | |
181 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ | |
182 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ | |
183 #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ | |
184 #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ | |
185 #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ | |
186 #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ | |
187 #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ | |
188 | |
189 /** | |
190 * @brief SDMMC Commands Index | |
191 */ | |
192 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ | |
193 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ | |
194 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ | |
195 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ | |
196 #define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ | |
197 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its | |
198 operating condition register (OCR) content in the response on the CMD line. */ | |
199 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ | |
200 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ | |
201 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information | |
202 and asks the card whether card supports voltage. */ | |
203 #define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ | |
204 #define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ | |
205 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ | |
206 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ | |
207 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ | |
208 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */ | |
209 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ | |
210 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands | |
211 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective | |
212 for SDHS and SDXC. */ | |
213 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of | |
214 fixed 512 bytes in case of SDHC and SDXC. */ | |
215 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by | |
216 STOP_TRANSMISSION command. */ | |
217 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ | |
218 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ | |
219 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ | |
220 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of | |
221 fixed 512 bytes in case of SDHC and SDXC. */ | |
222 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ | |
223 #define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ | |
224 #define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ | |
225 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ | |
226 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ | |
227 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ | |
228 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ | |
229 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ | |
230 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command | |
231 system set by switch function command (CMD6). */ | |
232 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. | |
233 Reserved for each command system set by switch function command (CMD6). */ | |
234 #define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ | |
235 #define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ | |
236 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ | |
237 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by | |
238 the SET_BLOCK_LEN command. */ | |
239 #define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather | |
240 than a standard command. */ | |
241 #define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card | |
242 for general purpose/application specific commands. */ | |
243 #define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */ | |
244 | |
245 /** | |
246 * @brief Following commands are SD Card Specific commands. | |
247 * SDMMC_APP_CMD should be sent before sending these commands. | |
248 */ | |
249 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus | |
250 widths are given in SCR register. */ | |
251 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ | |
252 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with | |
253 32bit+CRC data block. */ | |
254 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to | |
255 send its operating condition register (OCR) content in the response on the CMD line. */ | |
256 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ | |
257 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ | |
258 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ | |
259 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ | |
260 | |
261 /** | |
262 * @brief Following commands are SD Card Specific security commands. | |
263 * SDMMC_CMD_APP_CMD should be sent before sending these commands. | |
264 */ | |
265 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43) | |
266 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44) | |
267 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) | |
268 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) | |
269 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) | |
270 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) | |
271 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) | |
272 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) | |
273 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) | |
274 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) | |
275 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) | |
276 | |
277 /** | |
278 * @brief Masks for errors Card Status R1 (OCR Register) | |
279 */ | |
280 #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U | |
281 #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U | |
282 #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U | |
283 #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U | |
284 #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U | |
285 #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U | |
286 #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U | |
287 #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U | |
288 #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U | |
289 #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U | |
290 #define SDMMC_OCR_CC_ERROR 0x00100000U | |
291 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U | |
292 #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U | |
293 #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U | |
294 #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U | |
295 #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U | |
296 #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U | |
297 #define SDMMC_OCR_ERASE_RESET 0x00002000U | |
298 #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U | |
299 #define SDMMC_OCR_ERRORBITS 0xFDFFE008U | |
300 | |
301 /** | |
302 * @brief Masks for R6 Response | |
303 */ | |
304 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U | |
305 #define SDMMC_R6_ILLEGAL_CMD 0x00004000U | |
306 #define SDMMC_R6_COM_CRC_FAILED 0x00008000U | |
307 | |
308 #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U | |
309 #define SDMMC_HIGH_CAPACITY 0x40000000U | |
310 #define SDMMC_STD_CAPACITY 0x00000000U | |
311 #define SDMMC_CHECK_PATTERN 0x000001AAU | |
312 | |
313 #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU | |
314 | |
315 #define SDMMC_MAX_TRIAL 0x0000FFFFU | |
316 | |
317 #define SDMMC_ALLZERO 0x00000000U | |
318 | |
319 #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U | |
320 #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U | |
321 #define SDMMC_CARD_LOCKED 0x02000000U | |
322 | |
323 #define SDMMC_DATATIMEOUT 0xFFFFFFFFU | |
324 | |
325 #define SDMMC_0TO7BITS 0x000000FFU | |
326 #define SDMMC_8TO15BITS 0x0000FF00U | |
327 #define SDMMC_16TO23BITS 0x00FF0000U | |
328 #define SDMMC_24TO31BITS 0xFF000000U | |
329 #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU | |
330 | |
331 #define SDMMC_HALFFIFO 0x00000008U | |
332 #define SDMMC_HALFFIFOBYTES 0x00000020U | |
333 | |
334 /** | |
335 * @brief Command Class supported | |
336 */ | |
337 #define SDIO_CCCC_ERASE 0x00000020U | |
338 | |
339 #define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */ | |
340 #define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ | |
341 | |
342 | |
343 /** @defgroup SDIO_LL_Clock_Edge Clock Edge | |
344 * @{ | |
345 */ | |
346 #define SDIO_CLOCK_EDGE_RISING 0x00000000U | |
347 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE | |
348 | |
349 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ | |
350 ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) | |
351 /** | |
352 * @} | |
353 */ | |
354 | |
355 /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass | |
356 * @{ | |
357 */ | |
358 #define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U | |
359 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS | |
360 | |
361 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ | |
362 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) | |
363 /** | |
364 * @} | |
365 */ | |
366 | |
367 /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving | |
368 * @{ | |
369 */ | |
370 #define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U | |
371 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV | |
372 | |
373 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ | |
374 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) | |
375 /** | |
376 * @} | |
377 */ | |
378 | |
379 /** @defgroup SDIO_LL_Bus_Wide Bus Width | |
380 * @{ | |
381 */ | |
382 #define SDIO_BUS_WIDE_1B 0x00000000U | |
383 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 | |
384 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 | |
385 | |
386 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ | |
387 ((WIDE) == SDIO_BUS_WIDE_4B) || \ | |
388 ((WIDE) == SDIO_BUS_WIDE_8B)) | |
389 /** | |
390 * @} | |
391 */ | |
392 | |
393 /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control | |
394 * @{ | |
395 */ | |
396 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U | |
397 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN | |
398 | |
399 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ | |
400 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) | |
401 /** | |
402 * @} | |
403 */ | |
404 | |
405 /** @defgroup SDIO_LL_Clock_Division Clock Division | |
406 * @{ | |
407 */ | |
408 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU) | |
409 /** | |
410 * @} | |
411 */ | |
412 | |
413 /** @defgroup SDIO_LL_Command_Index Command Index | |
414 * @{ | |
415 */ | |
416 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U) | |
417 /** | |
418 * @} | |
419 */ | |
420 | |
421 /** @defgroup SDIO_LL_Response_Type Response Type | |
422 * @{ | |
423 */ | |
424 #define SDIO_RESPONSE_NO 0x00000000U | |
425 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 | |
426 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP | |
427 | |
428 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ | |
429 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ | |
430 ((RESPONSE) == SDIO_RESPONSE_LONG)) | |
431 /** | |
432 * @} | |
433 */ | |
434 | |
435 /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt | |
436 * @{ | |
437 */ | |
438 #define SDIO_WAIT_NO 0x00000000U | |
439 #define SDIO_WAIT_IT SDIO_CMD_WAITINT | |
440 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND | |
441 | |
442 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ | |
443 ((WAIT) == SDIO_WAIT_IT) || \ | |
444 ((WAIT) == SDIO_WAIT_PEND)) | |
445 /** | |
446 * @} | |
447 */ | |
448 | |
449 /** @defgroup SDIO_LL_CPSM_State CPSM State | |
450 * @{ | |
451 */ | |
452 #define SDIO_CPSM_DISABLE 0x00000000U | |
453 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN | |
454 | |
455 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ | |
456 ((CPSM) == SDIO_CPSM_ENABLE)) | |
457 /** | |
458 * @} | |
459 */ | |
460 | |
461 /** @defgroup SDIO_LL_Response_Registers Response Register | |
462 * @{ | |
463 */ | |
464 #define SDIO_RESP1 0x00000000U | |
465 #define SDIO_RESP2 0x00000004U | |
466 #define SDIO_RESP3 0x00000008U | |
467 #define SDIO_RESP4 0x0000000CU | |
468 | |
469 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ | |
470 ((RESP) == SDIO_RESP2) || \ | |
471 ((RESP) == SDIO_RESP3) || \ | |
472 ((RESP) == SDIO_RESP4)) | |
473 /** | |
474 * @} | |
475 */ | |
476 | |
477 /** @defgroup SDIO_LL_Data_Length Data Lenght | |
478 * @{ | |
479 */ | |
480 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) | |
481 /** | |
482 * @} | |
483 */ | |
484 | |
485 /** @defgroup SDIO_LL_Data_Block_Size Data Block Size | |
486 * @{ | |
487 */ | |
488 #define SDIO_DATABLOCK_SIZE_1B 0x00000000U | |
489 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 | |
490 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 | |
491 #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) | |
492 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 | |
493 #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) | |
494 #define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) | |
495 #define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) | |
496 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 | |
497 #define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3) | |
498 #define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) | |
499 #define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) | |
500 #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) | |
501 #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) | |
502 #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) | |
503 | |
504 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ | |
505 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ | |
506 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ | |
507 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ | |
508 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ | |
509 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ | |
510 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ | |
511 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ | |
512 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ | |
513 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ | |
514 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ | |
515 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ | |
516 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ | |
517 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ | |
518 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) | |
519 /** | |
520 * @} | |
521 */ | |
522 | |
523 /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction | |
524 * @{ | |
525 */ | |
526 #define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U | |
527 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR | |
528 | |
529 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ | |
530 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) | |
531 /** | |
532 * @} | |
533 */ | |
534 | |
535 /** @defgroup SDIO_LL_Transfer_Type Transfer Type | |
536 * @{ | |
537 */ | |
538 #define SDIO_TRANSFER_MODE_BLOCK 0x00000000U | |
539 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE | |
540 | |
541 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ | |
542 ((MODE) == SDIO_TRANSFER_MODE_STREAM)) | |
543 /** | |
544 * @} | |
545 */ | |
546 | |
547 /** @defgroup SDIO_LL_DPSM_State DPSM State | |
548 * @{ | |
549 */ | |
550 #define SDIO_DPSM_DISABLE 0x00000000U | |
551 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN | |
552 | |
553 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ | |
554 ((DPSM) == SDIO_DPSM_ENABLE)) | |
555 /** | |
556 * @} | |
557 */ | |
558 | |
559 /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode | |
560 * @{ | |
561 */ | |
562 #define SDIO_READ_WAIT_MODE_DATA2 0x00000000U | |
563 #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) | |
564 | |
565 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ | |
566 ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) | |
567 /** | |
568 * @} | |
569 */ | |
570 | |
571 /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources | |
572 * @{ | |
573 */ | |
574 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL | |
575 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL | |
576 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT | |
577 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT | |
578 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR | |
579 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR | |
580 #define SDIO_IT_CMDREND SDIO_STA_CMDREND | |
581 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT | |
582 #define SDIO_IT_DATAEND SDIO_STA_DATAEND | |
583 #define SDIO_IT_STBITERR SDIO_STA_STBITERR | |
584 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND | |
585 #define SDIO_IT_CMDACT SDIO_STA_CMDACT | |
586 #define SDIO_IT_TXACT SDIO_STA_TXACT | |
587 #define SDIO_IT_RXACT SDIO_STA_RXACT | |
588 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE | |
589 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF | |
590 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF | |
591 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF | |
592 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE | |
593 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE | |
594 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL | |
595 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL | |
596 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT | |
597 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND | |
598 /** | |
599 * @} | |
600 */ | |
601 | |
602 /** @defgroup SDIO_LL_Flags Flags | |
603 * @{ | |
604 */ | |
605 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL | |
606 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL | |
607 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT | |
608 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT | |
609 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR | |
610 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR | |
611 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND | |
612 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT | |
613 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND | |
614 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR | |
615 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND | |
616 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT | |
617 #define SDIO_FLAG_TXACT SDIO_STA_TXACT | |
618 #define SDIO_FLAG_RXACT SDIO_STA_RXACT | |
619 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE | |
620 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF | |
621 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF | |
622 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF | |
623 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE | |
624 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE | |
625 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL | |
626 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL | |
627 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT | |
628 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND | |
629 #define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ | |
630 SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ | |
631 SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ | |
632 SDIO_FLAG_DBCKEND)) | |
633 /** | |
634 * @} | |
635 */ | |
636 | |
637 /** | |
638 * @} | |
639 */ | |
640 | |
641 /* Exported macro ------------------------------------------------------------*/ | |
642 /** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros | |
643 * @{ | |
644 */ | |
645 | |
646 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region | |
647 * @{ | |
648 */ | |
649 /* ------------ SDIO registers bit address in the alias region -------------- */ | |
650 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) | |
651 | |
652 /* --- CLKCR Register ---*/ | |
653 /* Alias word address of CLKEN bit */ | |
654 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04U) | |
655 #define CLKEN_BITNUMBER 0x08U | |
656 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U)) | |
657 | |
658 /* --- CMD Register ---*/ | |
659 /* Alias word address of SDIOSUSPEND bit */ | |
660 #define CMD_OFFSET (SDIO_OFFSET + 0x0CU) | |
661 #define SDIOSUSPEND_BITNUMBER 0x0BU | |
662 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U)) | |
663 | |
664 /* Alias word address of ENCMDCOMPL bit */ | |
665 #define ENCMDCOMPL_BITNUMBER 0x0CU | |
666 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U)) | |
667 | |
668 /* Alias word address of NIEN bit */ | |
669 #define NIEN_BITNUMBER 0x0DU | |
670 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U)) | |
671 | |
672 /* Alias word address of ATACMD bit */ | |
673 #define ATACMD_BITNUMBER 0x0EU | |
674 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U)) | |
675 | |
676 /* --- DCTRL Register ---*/ | |
677 /* Alias word address of DMAEN bit */ | |
678 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU) | |
679 #define DMAEN_BITNUMBER 0x03U | |
680 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U)) | |
681 | |
682 /* Alias word address of RWSTART bit */ | |
683 #define RWSTART_BITNUMBER 0x08U | |
684 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U)) | |
685 | |
686 /* Alias word address of RWSTOP bit */ | |
687 #define RWSTOP_BITNUMBER 0x09U | |
688 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U)) | |
689 | |
690 /* Alias word address of RWMOD bit */ | |
691 #define RWMOD_BITNUMBER 0x0AU | |
692 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U)) | |
693 | |
694 /* Alias word address of SDIOEN bit */ | |
695 #define SDIOEN_BITNUMBER 0x0BU | |
696 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U)) | |
697 /** | |
698 * @} | |
699 */ | |
700 | |
701 /** @defgroup SDIO_LL_Register Bits And Addresses Definitions | |
702 * @brief SDIO_LL registers bit address in the alias region | |
703 * @{ | |
704 */ | |
705 /* ---------------------- SDIO registers bit mask --------------------------- */ | |
706 /* --- CLKCR Register ---*/ | |
707 /* CLKCR register clear mask */ | |
708 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ | |
709 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ | |
710 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) | |
711 | |
712 /* --- DCTRL Register ---*/ | |
713 /* SDIO DCTRL Clear Mask */ | |
714 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ | |
715 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) | |
716 | |
717 /* --- CMD Register ---*/ | |
718 /* CMD Register clear mask */ | |
719 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ | |
720 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ | |
721 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) | |
722 | |
723 /* SDIO Initialization Frequency (400KHz max) */ | |
724 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) | |
725 | |
726 /* SDIO Data Transfer Frequency (25MHz max) */ | |
727 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) | |
728 | |
729 /** | |
730 * @} | |
731 */ | |
732 | |
733 /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration | |
734 * @brief macros to handle interrupts and specific clock configurations | |
735 * @{ | |
736 */ | |
737 | |
738 /** | |
739 * @brief Enable the SDIO device. | |
740 * @param __INSTANCE__ SDIO Instance | |
741 * @retval None | |
742 */ | |
743 #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) | |
744 | |
745 /** | |
746 * @brief Disable the SDIO device. | |
747 * @param __INSTANCE__ SDIO Instance | |
748 * @retval None | |
749 */ | |
750 #define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) | |
751 | |
752 /** | |
753 * @brief Enable the SDIO DMA transfer. | |
754 * @param __INSTANCE__ SDIO Instance | |
755 * @retval None | |
756 */ | |
757 #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) | |
758 /** | |
759 * @brief Disable the SDIO DMA transfer. | |
760 * @param __INSTANCE__ SDIO Instance | |
761 * @retval None | |
762 */ | |
763 #define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) | |
764 | |
765 /** | |
766 * @brief Enable the SDIO device interrupt. | |
767 * @param __INSTANCE__ Pointer to SDIO register base | |
768 * @param __INTERRUPT__ specifies the SDIO interrupt sources to be enabled. | |
769 * This parameter can be one or a combination of the following values: | |
770 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt | |
771 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt | |
772 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt | |
773 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt | |
774 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt | |
775 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt | |
776 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt | |
777 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt | |
778 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt | |
779 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt | |
780 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt | |
781 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt | |
782 * @arg SDIO_IT_RXACT: Data receive in progress interrupt | |
783 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt | |
784 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt | |
785 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt | |
786 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt | |
787 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt | |
788 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt | |
789 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt | |
790 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt | |
791 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt | |
792 * @retval None | |
793 */ | |
794 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) | |
795 | |
796 /** | |
797 * @brief Disable the SDIO device interrupt. | |
798 * @param __INSTANCE__ Pointer to SDIO register base | |
799 * @param __INTERRUPT__ specifies the SDIO interrupt sources to be disabled. | |
800 * This parameter can be one or a combination of the following values: | |
801 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt | |
802 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt | |
803 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt | |
804 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt | |
805 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt | |
806 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt | |
807 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt | |
808 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt | |
809 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt | |
810 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt | |
811 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt | |
812 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt | |
813 * @arg SDIO_IT_RXACT: Data receive in progress interrupt | |
814 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt | |
815 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt | |
816 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt | |
817 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt | |
818 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt | |
819 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt | |
820 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt | |
821 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt | |
822 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt | |
823 * @retval None | |
824 */ | |
825 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) | |
826 | |
827 /** | |
828 * @brief Checks whether the specified SDIO flag is set or not. | |
829 * @param __INSTANCE__ Pointer to SDIO register base | |
830 * @param __FLAG__ specifies the flag to check. | |
831 * This parameter can be one of the following values: | |
832 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) | |
833 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) | |
834 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout | |
835 * @arg SDIO_FLAG_DTIMEOUT: Data timeout | |
836 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error | |
837 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error | |
838 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) | |
839 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) | |
840 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) | |
841 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) | |
842 * @arg SDIO_FLAG_CMDACT: Command transfer in progress | |
843 * @arg SDIO_FLAG_TXACT: Data transmit in progress | |
844 * @arg SDIO_FLAG_RXACT: Data receive in progress | |
845 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty | |
846 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full | |
847 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full | |
848 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full | |
849 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty | |
850 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty | |
851 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO | |
852 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO | |
853 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received | |
854 * @retval The new state of SDIO_FLAG (SET or RESET). | |
855 */ | |
856 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) | |
857 | |
858 | |
859 /** | |
860 * @brief Clears the SDIO pending flags. | |
861 * @param __INSTANCE__ Pointer to SDIO register base | |
862 * @param __FLAG__ specifies the flag to clear. | |
863 * This parameter can be one or a combination of the following values: | |
864 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) | |
865 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) | |
866 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout | |
867 * @arg SDIO_FLAG_DTIMEOUT: Data timeout | |
868 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error | |
869 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error | |
870 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) | |
871 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) | |
872 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) | |
873 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) | |
874 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received | |
875 * @retval None | |
876 */ | |
877 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) | |
878 | |
879 /** | |
880 * @brief Checks whether the specified SDIO interrupt has occurred or not. | |
881 * @param __INSTANCE__ Pointer to SDIO register base | |
882 * @param __INTERRUPT__ specifies the SDIO interrupt source to check. | |
883 * This parameter can be one of the following values: | |
884 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt | |
885 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt | |
886 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt | |
887 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt | |
888 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt | |
889 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt | |
890 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt | |
891 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt | |
892 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt | |
893 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt | |
894 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt | |
895 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt | |
896 * @arg SDIO_IT_RXACT: Data receive in progress interrupt | |
897 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt | |
898 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt | |
899 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt | |
900 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt | |
901 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt | |
902 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt | |
903 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt | |
904 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt | |
905 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt | |
906 * @retval The new state of SDIO_IT (SET or RESET). | |
907 */ | |
908 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) | |
909 | |
910 /** | |
911 * @brief Clears the SDIO's interrupt pending bits. | |
912 * @param __INSTANCE__ Pointer to SDIO register base | |
913 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. | |
914 * This parameter can be one or a combination of the following values: | |
915 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt | |
916 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt | |
917 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt | |
918 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt | |
919 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt | |
920 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt | |
921 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt | |
922 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt | |
923 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt | |
924 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt | |
925 * @retval None | |
926 */ | |
927 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) | |
928 | |
929 /** | |
930 * @brief Enable Start the SD I/O Read Wait operation. | |
931 * @param __INSTANCE__ Pointer to SDIO register base | |
932 * @retval None | |
933 */ | |
934 #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) | |
935 | |
936 /** | |
937 * @brief Disable Start the SD I/O Read Wait operations. | |
938 * @param __INSTANCE__ Pointer to SDIO register base | |
939 * @retval None | |
940 */ | |
941 #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) | |
942 | |
943 /** | |
944 * @brief Enable Start the SD I/O Read Wait operation. | |
945 * @param __INSTANCE__ Pointer to SDIO register base | |
946 * @retval None | |
947 */ | |
948 #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) | |
949 | |
950 /** | |
951 * @brief Disable Stop the SD I/O Read Wait operations. | |
952 * @param __INSTANCE__ Pointer to SDIO register base | |
953 * @retval None | |
954 */ | |
955 #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) | |
956 | |
957 /** | |
958 * @brief Enable the SD I/O Mode Operation. | |
959 * @param __INSTANCE__ Pointer to SDIO register base | |
960 * @retval None | |
961 */ | |
962 #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) | |
963 | |
964 /** | |
965 * @brief Disable the SD I/O Mode Operation. | |
966 * @param __INSTANCE__ Pointer to SDIO register base | |
967 * @retval None | |
968 */ | |
969 #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) | |
970 | |
971 /** | |
972 * @brief Enable the SD I/O Suspend command sending. | |
973 * @param __INSTANCE__ Pointer to SDIO register base | |
974 * @retval None | |
975 */ | |
976 #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) | |
977 | |
978 /** | |
979 * @brief Disable the SD I/O Suspend command sending. | |
980 * @param __INSTANCE__ Pointer to SDIO register base | |
981 * @retval None | |
982 */ | |
983 #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) | |
984 | |
985 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ | |
986 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ | |
987 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) | |
988 /** | |
989 * @brief Enable the command completion signal. | |
990 * @retval None | |
991 */ | |
992 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) | |
993 | |
994 /** | |
995 * @brief Disable the command completion signal. | |
996 * @retval None | |
997 */ | |
998 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) | |
999 | |
1000 /** | |
1001 * @brief Enable the CE-ATA interrupt. | |
1002 * @retval None | |
1003 */ | |
1004 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U) | |
1005 | |
1006 /** | |
1007 * @brief Disable the CE-ATA interrupt. | |
1008 * @retval None | |
1009 */ | |
1010 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U) | |
1011 | |
1012 /** | |
1013 * @brief Enable send CE-ATA command (CMD61). | |
1014 * @retval None | |
1015 */ | |
1016 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) | |
1017 | |
1018 /** | |
1019 * @brief Disable send CE-ATA command (CMD61). | |
1020 * @retval None | |
1021 */ | |
1022 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) | |
1023 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\ | |
1024 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ | |
1025 | |
1026 /** | |
1027 * @} | |
1028 */ | |
1029 | |
1030 /** | |
1031 * @} | |
1032 */ | |
1033 | |
1034 /* Exported functions --------------------------------------------------------*/ | |
1035 /** @addtogroup SDMMC_LL_Exported_Functions | |
1036 * @{ | |
1037 */ | |
1038 | |
1039 /* Initialization/de-initialization functions **********************************/ | |
1040 /** @addtogroup HAL_SDMMC_LL_Group1 | |
1041 * @{ | |
1042 */ | |
1043 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); | |
1044 /** | |
1045 * @} | |
1046 */ | |
1047 | |
1048 /* I/O operation functions *****************************************************/ | |
1049 /** @addtogroup HAL_SDMMC_LL_Group2 | |
1050 * @{ | |
1051 */ | |
1052 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); | |
1053 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); | |
1054 /** | |
1055 * @} | |
1056 */ | |
1057 | |
1058 /* Peripheral Control functions ************************************************/ | |
1059 /** @addtogroup HAL_SDMMC_LL_Group3 | |
1060 * @{ | |
1061 */ | |
1062 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); | |
1063 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); | |
1064 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); | |
1065 | |
1066 /* Command path state machine (CPSM) management functions */ | |
1067 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command); | |
1068 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); | |
1069 uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response); | |
1070 | |
1071 /* Data path state machine (DPSM) management functions */ | |
1072 HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); | |
1073 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); | |
1074 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); | |
1075 | |
1076 /* SDMMC Cards mode management functions */ | |
1077 HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); | |
1078 | |
1079 /* SDMMC Commands management functions */ | |
1080 uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); | |
1081 uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); | |
1082 uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); | |
1083 uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); | |
1084 uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); | |
1085 uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); | |
1086 uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); | |
1087 uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx); | |
1088 uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx); | |
1089 uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr); | |
1090 uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx); | |
1091 uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx); | |
1092 uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); | |
1093 uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType); | |
1094 uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); | |
1095 uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); | |
1096 uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); | |
1097 uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); | |
1098 uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); | |
1099 uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); | |
1100 uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); | |
1101 | |
1102 uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); | |
1103 uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); | |
1104 uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); | |
1105 uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); | |
1106 | |
1107 /** | |
1108 * @} | |
1109 */ | |
1110 | |
1111 /** | |
1112 * @} | |
1113 */ | |
1114 | |
1115 /** | |
1116 * @} | |
1117 */ | |
1118 | |
1119 /** | |
1120 * @} | |
1121 */ | |
1122 | |
1123 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || | |
1124 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || | |
1125 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ | |
1126 | |
1127 #ifdef __cplusplus | |
1128 } | |
1129 #endif | |
1130 | |
1131 #endif /* __STM32F4xx_LL_SDMMC_H */ | |
1132 | |
1133 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |