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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_LL_PWR_H
38 #define __STM32F4xx_LL_PWR_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx.h"
46
47 /** @addtogroup STM32F4xx_LL_Driver
48 * @{
49 */
50
51 #if defined(PWR)
52
53 /** @defgroup PWR_LL PWR
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /* Private macros ------------------------------------------------------------*/
61 /* Exported types ------------------------------------------------------------*/
62 /* Exported constants --------------------------------------------------------*/
63 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
64 * @{
65 */
66
67 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
68 * @brief Flags defines which can be used with LL_PWR_WriteReg function
69 * @{
70 */
71 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
72 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
73 /**
74 * @}
75 */
76
77 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
78 * @brief Flags defines which can be used with LL_PWR_ReadReg function
79 * @{
80 */
81 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
82 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
83 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
84 #define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */
85 #if defined(PWR_CSR_EWUP)
86 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */
87 #elif defined(PWR_CSR_EWUP1)
88 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
89 #endif /* PWR_CSR_EWUP */
90 #if defined(PWR_CSR_EWUP2)
91 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
92 #endif /* PWR_CSR_EWUP2 */
93 #if defined(PWR_CSR_EWUP3)
94 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
95 #endif /* PWR_CSR_EWUP3 */
96 /**
97 * @}
98 */
99
100 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
101 * @{
102 */
103 #if defined(PWR_CR_VOS_0)
104 #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0)
105 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1)
106 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
107 #else
108 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS)
109 #define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U
110 #endif /* PWR_CR_VOS_0 */
111 /**
112 * @}
113 */
114
115 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
116 * @{
117 */
118 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
119 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
120 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
121 #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
122 #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
123 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
124 #if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
125 #define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
126 #define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
127 #endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
128 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
129 /**
130 * @}
131 */
132
133 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
134 * @{
135 */
136 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
137 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
138 /**
139 * @}
140 */
141
142 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
143 * @{
144 */
145 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
146 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
147 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
148 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
149 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
150 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
151 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
152 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
153 /**
154 * @}
155 */
156 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
157 * @{
158 */
159 #if defined(PWR_CSR_EWUP)
160 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */
161 #endif /* PWR_CSR_EWUP */
162 #if defined(PWR_CSR_EWUP1)
163 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
164 #endif /* PWR_CSR_EWUP1 */
165 #if defined(PWR_CSR_EWUP2)
166 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */
167 #endif /* PWR_CSR_EWUP2 */
168 #if defined(PWR_CSR_EWUP3)
169 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */
170 #endif /* PWR_CSR_EWUP3 */
171 /**
172 * @}
173 */
174
175 /**
176 * @}
177 */
178
179
180 /* Exported macro ------------------------------------------------------------*/
181 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
182 * @{
183 */
184
185 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
186 * @{
187 */
188
189 /**
190 * @brief Write a value in PWR register
191 * @param __REG__ Register to be written
192 * @param __VALUE__ Value to be written in the register
193 * @retval None
194 */
195 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
196
197 /**
198 * @brief Read a value in PWR register
199 * @param __REG__ Register to be read
200 * @retval Register value
201 */
202 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
203 /**
204 * @}
205 */
206
207 /**
208 * @}
209 */
210
211 /* Exported functions --------------------------------------------------------*/
212 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
213 * @{
214 */
215
216 /** @defgroup PWR_LL_EF_Configuration Configuration
217 * @{
218 */
219 #if defined(PWR_CR_FISSR)
220 /**
221 * @brief Enable FLASH interface STOP while system Run is ON
222 * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP
223 * @note This mode is enabled only with STOP low power mode.
224 * @retval None
225 */
226 __STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
227 {
228 SET_BIT(PWR->CR, PWR_CR_FISSR);
229 }
230
231 /**
232 * @brief Disable FLASH Interface STOP while system Run is ON
233 * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP
234 * @retval None
235 */
236 __STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
237 {
238 CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
239 }
240
241 /**
242 * @brief Check if FLASH Interface STOP while system Run feature is enabled
243 * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP
244 * @retval State of bit (1 or 0).
245 */
246 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
247 {
248 return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
249 }
250 #endif /* PWR_CR_FISSR */
251
252 #if defined(PWR_CR_FMSSR)
253 /**
254 * @brief Enable FLASH Memory STOP while system Run is ON
255 * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP
256 * @note This mode is enabled only with STOP low power mode.
257 * @retval None
258 */
259 __STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
260 {
261 SET_BIT(PWR->CR, PWR_CR_FMSSR);
262 }
263
264 /**
265 * @brief Disable FLASH Memory STOP while system Run is ON
266 * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP
267 * @retval None
268 */
269 __STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
270 {
271 CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
272 }
273
274 /**
275 * @brief Check if FLASH Memory STOP while system Run feature is enabled
276 * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP
277 * @retval State of bit (1 or 0).
278 */
279 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
280 {
281 return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
282 }
283 #endif /* PWR_CR_FMSSR */
284 #if defined(PWR_CR_UDEN)
285 /**
286 * @brief Enable Under Drive Mode
287 * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode
288 * @note This mode is enabled only with STOP low power mode.
289 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
290 * mode is only available when the main Regulator or the low power Regulator
291 * is in low voltage mode.
292 * @note If the Under-drive mode was enabled, it is automatically disabled after
293 * exiting Stop mode.
294 * When the voltage Regulator operates in Under-drive mode, an additional
295 * startup delay is induced when waking up from Stop mode.
296 * @retval None
297 */
298 __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
299 {
300 SET_BIT(PWR->CR, PWR_CR_UDEN);
301 }
302
303 /**
304 * @brief Disable Under Drive Mode
305 * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode
306 * @retval None
307 */
308 __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
309 {
310 CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
311 }
312
313 /**
314 * @brief Check if Under Drive Mode is enabled
315 * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode
316 * @retval State of bit (1 or 0).
317 */
318 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
319 {
320 return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
321 }
322 #endif /* PWR_CR_UDEN */
323
324 #if defined(PWR_CR_ODSWEN)
325 /**
326 * @brief Enable Over drive switching
327 * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching
328 * @retval None
329 */
330 __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
331 {
332 SET_BIT(PWR->CR, PWR_CR_ODSWEN);
333 }
334
335 /**
336 * @brief Disable Over drive switching
337 * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching
338 * @retval None
339 */
340 __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
341 {
342 CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
343 }
344
345 /**
346 * @brief Check if Over drive switching is enabled
347 * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching
348 * @retval State of bit (1 or 0).
349 */
350 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
351 {
352 return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
353 }
354 #endif /* PWR_CR_ODSWEN */
355 #if defined(PWR_CR_ODEN)
356 /**
357 * @brief Enable Over drive Mode
358 * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode
359 * @retval None
360 */
361 __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
362 {
363 SET_BIT(PWR->CR, PWR_CR_ODEN);
364 }
365
366 /**
367 * @brief Disable Over drive Mode
368 * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode
369 * @retval None
370 */
371 __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
372 {
373 CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
374 }
375
376 /**
377 * @brief Check if Over drive switching is enabled
378 * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode
379 * @retval State of bit (1 or 0).
380 */
381 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
382 {
383 return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
384 }
385 #endif /* PWR_CR_ODEN */
386 #if defined(PWR_CR_MRUDS)
387 /**
388 * @brief Enable Main Regulator in deepsleep under-drive Mode
389 * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode
390 * @retval None
391 */
392 __STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
393 {
394 SET_BIT(PWR->CR, PWR_CR_MRUDS);
395 }
396
397 /**
398 * @brief Disable Main Regulator in deepsleep under-drive Mode
399 * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode
400 * @retval None
401 */
402 __STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
403 {
404 CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
405 }
406
407 /**
408 * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled
409 * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
410 * @retval State of bit (1 or 0).
411 */
412 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
413 {
414 return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
415 }
416 #endif /* PWR_CR_MRUDS */
417
418 #if defined(PWR_CR_LPUDS)
419 /**
420 * @brief Enable Low Power Regulator in deepsleep under-drive Mode
421 * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
422 * @retval None
423 */
424 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
425 {
426 SET_BIT(PWR->CR, PWR_CR_LPUDS);
427 }
428
429 /**
430 * @brief Disable Low Power Regulator in deepsleep under-drive Mode
431 * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
432 * @retval None
433 */
434 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
435 {
436 CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
437 }
438
439 /**
440 * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled
441 * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
442 * @retval State of bit (1 or 0).
443 */
444 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
445 {
446 return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
447 }
448 #endif /* PWR_CR_LPUDS */
449
450 #if defined(PWR_CR_MRLVDS)
451 /**
452 * @brief Enable Main Regulator low voltage Mode
453 * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode
454 * @retval None
455 */
456 __STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
457 {
458 SET_BIT(PWR->CR, PWR_CR_MRLVDS);
459 }
460
461 /**
462 * @brief Disable Main Regulator low voltage Mode
463 * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode
464 * @retval None
465 */
466 __STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
467 {
468 CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
469 }
470
471 /**
472 * @brief Check if Main Regulator low voltage Mode is enabled
473 * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode
474 * @retval State of bit (1 or 0).
475 */
476 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
477 {
478 return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
479 }
480 #endif /* PWR_CR_MRLVDS */
481
482 #if defined(PWR_CR_LPLVDS)
483 /**
484 * @brief Enable Low Power Regulator low voltage Mode
485 * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode
486 * @retval None
487 */
488 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
489 {
490 SET_BIT(PWR->CR, PWR_CR_LPLVDS);
491 }
492
493 /**
494 * @brief Disable Low Power Regulator low voltage Mode
495 * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode
496 * @retval None
497 */
498 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
499 {
500 CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
501 }
502
503 /**
504 * @brief Check if Low Power Regulator low voltage Mode is enabled
505 * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
506 * @retval State of bit (1 or 0).
507 */
508 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
509 {
510 return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
511 }
512 #endif /* PWR_CR_LPLVDS */
513 /**
514 * @brief Set the main internal Regulator output voltage
515 * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
516 * @param VoltageScaling This parameter can be one of the following values:
517 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
518 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
519 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
520 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
521 * @retval None
522 */
523 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
524 {
525 MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
526 }
527
528 /**
529 * @brief Get the main internal Regulator output voltage
530 * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
531 * @retval Returned value can be one of the following values:
532 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
533 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
534 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
535 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
536 */
537 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
538 {
539 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
540 }
541 /**
542 * @brief Enable the Flash Power Down in Stop Mode
543 * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
544 * @retval None
545 */
546 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
547 {
548 SET_BIT(PWR->CR, PWR_CR_FPDS);
549 }
550
551 /**
552 * @brief Disable the Flash Power Down in Stop Mode
553 * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
554 * @retval None
555 */
556 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
557 {
558 CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
559 }
560
561 /**
562 * @brief Check if the Flash Power Down in Stop Mode is enabled
563 * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
564 * @retval State of bit (1 or 0).
565 */
566 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
567 {
568 return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
569 }
570
571 /**
572 * @brief Enable access to the backup domain
573 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
574 * @retval None
575 */
576 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
577 {
578 SET_BIT(PWR->CR, PWR_CR_DBP);
579 }
580
581 /**
582 * @brief Disable access to the backup domain
583 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
584 * @retval None
585 */
586 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
587 {
588 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
589 }
590
591 /**
592 * @brief Check if the backup domain is enabled
593 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
594 * @retval State of bit (1 or 0).
595 */
596 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
597 {
598 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
599 }
600 /**
601 * @brief Enable the backup Regulator
602 * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
603 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
604 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
605 * @retval None
606 */
607 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
608 {
609 SET_BIT(PWR->CSR, PWR_CSR_BRE);
610 }
611
612 /**
613 * @brief Disable the backup Regulator
614 * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
615 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
616 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
617 * @retval None
618 */
619 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
620 {
621 CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
622 }
623
624 /**
625 * @brief Check if the backup Regulator is enabled
626 * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
627 * @retval State of bit (1 or 0).
628 */
629 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
630 {
631 return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
632 }
633
634 /**
635 * @brief Set voltage Regulator mode during deep sleep mode
636 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
637 * @param RegulMode This parameter can be one of the following values:
638 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
639 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
640 * @retval None
641 */
642 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
643 {
644 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
645 }
646
647 /**
648 * @brief Get voltage Regulator mode during deep sleep mode
649 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
650 * @retval Returned value can be one of the following values:
651 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
652 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
653 */
654 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
655 {
656 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
657 }
658
659 /**
660 * @brief Set Power Down mode when CPU enters deepsleep
661 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
662 * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n
663 * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n
664 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
665 * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n
666 * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n
667 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
668 * @rmtoll CR LPDS LL_PWR_SetPowerMode
669 * @param PDMode This parameter can be one of the following values:
670 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
671 * @arg @ref LL_PWR_MODE_STOP_LPREGU
672 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
673 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
674 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
675 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
676 *
677 * (*) not available on all devices
678 * @arg @ref LL_PWR_MODE_STANDBY
679 * @retval None
680 */
681 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
682 {
683 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
684 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
685 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
686 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
687 #else
688 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
689 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
690 }
691
692 /**
693 * @brief Get Power Down mode when CPU enters deepsleep
694 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
695 * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n
696 * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n
697 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
698 * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n
699 * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n
700 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
701 * @rmtoll CR LPDS LL_PWR_GetPowerMode
702 * @retval Returned value can be one of the following values:
703 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
704 * @arg @ref LL_PWR_MODE_STOP_LPREGU
705 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
706 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
707 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
708 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
709 *
710 * (*) not available on all devices
711 * @arg @ref LL_PWR_MODE_STANDBY
712 */
713 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
714 {
715 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
716 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
717 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
718 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
719 #else
720 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
721 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
722 }
723
724 /**
725 * @brief Configure the voltage threshold detected by the Power Voltage Detector
726 * @rmtoll CR PLS LL_PWR_SetPVDLevel
727 * @param PVDLevel This parameter can be one of the following values:
728 * @arg @ref LL_PWR_PVDLEVEL_0
729 * @arg @ref LL_PWR_PVDLEVEL_1
730 * @arg @ref LL_PWR_PVDLEVEL_2
731 * @arg @ref LL_PWR_PVDLEVEL_3
732 * @arg @ref LL_PWR_PVDLEVEL_4
733 * @arg @ref LL_PWR_PVDLEVEL_5
734 * @arg @ref LL_PWR_PVDLEVEL_6
735 * @arg @ref LL_PWR_PVDLEVEL_7
736 * @retval None
737 */
738 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
739 {
740 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
741 }
742
743 /**
744 * @brief Get the voltage threshold detection
745 * @rmtoll CR PLS LL_PWR_GetPVDLevel
746 * @retval Returned value can be one of the following values:
747 * @arg @ref LL_PWR_PVDLEVEL_0
748 * @arg @ref LL_PWR_PVDLEVEL_1
749 * @arg @ref LL_PWR_PVDLEVEL_2
750 * @arg @ref LL_PWR_PVDLEVEL_3
751 * @arg @ref LL_PWR_PVDLEVEL_4
752 * @arg @ref LL_PWR_PVDLEVEL_5
753 * @arg @ref LL_PWR_PVDLEVEL_6
754 * @arg @ref LL_PWR_PVDLEVEL_7
755 */
756 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
757 {
758 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
759 }
760
761 /**
762 * @brief Enable Power Voltage Detector
763 * @rmtoll CR PVDE LL_PWR_EnablePVD
764 * @retval None
765 */
766 __STATIC_INLINE void LL_PWR_EnablePVD(void)
767 {
768 SET_BIT(PWR->CR, PWR_CR_PVDE);
769 }
770
771 /**
772 * @brief Disable Power Voltage Detector
773 * @rmtoll CR PVDE LL_PWR_DisablePVD
774 * @retval None
775 */
776 __STATIC_INLINE void LL_PWR_DisablePVD(void)
777 {
778 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
779 }
780
781 /**
782 * @brief Check if Power Voltage Detector is enabled
783 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
784 * @retval State of bit (1 or 0).
785 */
786 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
787 {
788 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
789 }
790
791 /**
792 * @brief Enable the WakeUp PINx functionality
793 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n
794 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
795 * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
796 * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
797 * @param WakeUpPin This parameter can be one of the following values:
798 * @arg @ref LL_PWR_WAKEUP_PIN1
799 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
800 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
801 *
802 * (*) not available on all devices
803 * @retval None
804 */
805 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
806 {
807 SET_BIT(PWR->CSR, WakeUpPin);
808 }
809
810 /**
811 * @brief Disable the WakeUp PINx functionality
812 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n
813 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
814 * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
815 * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
816 * @param WakeUpPin This parameter can be one of the following values:
817 * @arg @ref LL_PWR_WAKEUP_PIN1
818 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
819 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
820 *
821 * (*) not available on all devices
822 * @retval None
823 */
824 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
825 {
826 CLEAR_BIT(PWR->CSR, WakeUpPin);
827 }
828
829 /**
830 * @brief Check if the WakeUp PINx functionality is enabled
831 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n
832 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
833 * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
834 * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
835 * @param WakeUpPin This parameter can be one of the following values:
836 * @arg @ref LL_PWR_WAKEUP_PIN1
837 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
838 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
839 *
840 * (*) not available on all devices
841 * @retval State of bit (1 or 0).
842 */
843 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
844 {
845 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
846 }
847
848
849 /**
850 * @}
851 */
852
853 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
854 * @{
855 */
856
857 /**
858 * @brief Get Wake-up Flag
859 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
860 * @retval State of bit (1 or 0).
861 */
862 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
863 {
864 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
865 }
866
867 /**
868 * @brief Get Standby Flag
869 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
870 * @retval State of bit (1 or 0).
871 */
872 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
873 {
874 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
875 }
876
877 /**
878 * @brief Get Backup Regulator ready Flag
879 * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
880 * @retval State of bit (1 or 0).
881 */
882 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
883 {
884 return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
885 }
886 /**
887 * @brief Indicate whether VDD voltage is below the selected PVD threshold
888 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
889 * @retval State of bit (1 or 0).
890 */
891 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
892 {
893 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
894 }
895
896 /**
897 * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
898 * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS
899 * @retval State of bit (1 or 0).
900 */
901 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
902 {
903 return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
904 }
905 #if defined(PWR_CR_ODEN)
906 /**
907 * @brief Indicate whether the Over-Drive mode is ready or not
908 * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD
909 * @retval State of bit (1 or 0).
910 */
911 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
912 {
913 return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
914 }
915 #endif /* PWR_CR_ODEN */
916
917 #if defined(PWR_CR_ODSWEN)
918 /**
919 * @brief Indicate whether the Over-Drive mode switching is ready or not
920 * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW
921 * @retval State of bit (1 or 0).
922 */
923 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
924 {
925 return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
926 }
927 #endif /* PWR_CR_ODSWEN */
928
929 #if defined(PWR_CR_UDEN)
930 /**
931 * @brief Indicate whether the Under-Drive mode is ready or not
932 * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD
933 * @retval State of bit (1 or 0).
934 */
935 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
936 {
937 return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
938 }
939 #endif /* PWR_CR_UDEN */
940 /**
941 * @brief Clear Standby Flag
942 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
943 * @retval None
944 */
945 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
946 {
947 SET_BIT(PWR->CR, PWR_CR_CSBF);
948 }
949
950 /**
951 * @brief Clear Wake-up Flags
952 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
953 * @retval None
954 */
955 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
956 {
957 SET_BIT(PWR->CR, PWR_CR_CWUF);
958 }
959 #if defined(PWR_CSR_UDRDY)
960 /**
961 * @brief Clear Under-Drive ready Flag
962 * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD
963 * @retval None
964 */
965 __STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
966 {
967 WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
968 }
969 #endif /* PWR_CSR_UDRDY */
970
971 /**
972 * @}
973 */
974
975 #if defined(USE_FULL_LL_DRIVER)
976 /** @defgroup PWR_LL_EF_Init De-initialization function
977 * @{
978 */
979 ErrorStatus LL_PWR_DeInit(void);
980 /**
981 * @}
982 */
983 #endif /* USE_FULL_LL_DRIVER */
984
985 /**
986 * @}
987 */
988
989 /**
990 * @}
991 */
992
993 #endif /* defined(PWR) */
994
995 /**
996 * @}
997 */
998
999 #ifdef __cplusplus
1000 }
1001 #endif
1002
1003 #endif /* __STM32F4xx_LL_PWR_H */
1004
1005 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/