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Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_i2c.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of I2C LL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_LL_I2C_H | |
38 #define __STM32F4xx_LL_I2C_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 /* Includes ------------------------------------------------------------------*/ | |
45 #include "stm32f4xx.h" | |
46 | |
47 /** @addtogroup STM32F4xx_LL_Driver | |
48 * @{ | |
49 */ | |
50 | |
51 #if defined (I2C1) || defined (I2C2) || defined (I2C3) | |
52 | |
53 /** @defgroup I2C_LL I2C | |
54 * @{ | |
55 */ | |
56 | |
57 /* Private types -------------------------------------------------------------*/ | |
58 /* Private variables ---------------------------------------------------------*/ | |
59 | |
60 /* Private constants ---------------------------------------------------------*/ | |
61 /** @defgroup I2C_LL_Private_Constants I2C Private Constants | |
62 * @{ | |
63 */ | |
64 | |
65 /* Defines used to perform compute and check in the macros */ | |
66 #define LL_I2C_MAX_SPEED_STANDARD 100000U | |
67 #define LL_I2C_MAX_SPEED_FAST 400000U | |
68 /** | |
69 * @} | |
70 */ | |
71 | |
72 /* Private macros ------------------------------------------------------------*/ | |
73 #if defined(USE_FULL_LL_DRIVER) | |
74 /** @defgroup I2C_LL_Private_Macros I2C Private Macros | |
75 * @{ | |
76 */ | |
77 /** | |
78 * @} | |
79 */ | |
80 #endif /*USE_FULL_LL_DRIVER*/ | |
81 | |
82 /* Exported types ------------------------------------------------------------*/ | |
83 #if defined(USE_FULL_LL_DRIVER) | |
84 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure | |
85 * @{ | |
86 */ | |
87 typedef struct | |
88 { | |
89 uint32_t PeripheralMode; /*!< Specifies the peripheral mode. | |
90 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE | |
91 | |
92 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ | |
93 | |
94 uint32_t ClockSpeed; /*!< Specifies the clock frequency. | |
95 This parameter must be set to a value lower than 400kHz (in Hz) | |
96 | |
97 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod() | |
98 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */ | |
99 | |
100 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. | |
101 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE | |
102 | |
103 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */ | |
104 | |
105 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) | |
106 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. | |
107 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION | |
108 | |
109 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ | |
110 | |
111 uint32_t DigitalFilter; /*!< Configures the digital noise filter. | |
112 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F | |
113 | |
114 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ | |
115 | |
116 #endif | |
117 uint32_t OwnAddress1; /*!< Specifies the device own address 1. | |
118 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF | |
119 | |
120 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ | |
121 | |
122 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. | |
123 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE | |
124 | |
125 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ | |
126 | |
127 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). | |
128 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 | |
129 | |
130 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ | |
131 } LL_I2C_InitTypeDef; | |
132 /** | |
133 * @} | |
134 */ | |
135 #endif /*USE_FULL_LL_DRIVER*/ | |
136 | |
137 /* Exported constants --------------------------------------------------------*/ | |
138 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants | |
139 * @{ | |
140 */ | |
141 | |
142 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines | |
143 * @brief Flags defines which can be used with LL_I2C_ReadReg function | |
144 * @{ | |
145 */ | |
146 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */ | |
147 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or | |
148 Address matched flag (slave mode) */ | |
149 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */ | |
150 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */ | |
151 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */ | |
152 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */ | |
153 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */ | |
154 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */ | |
155 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */ | |
156 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */ | |
157 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */ | |
158 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ | |
159 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ | |
160 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */ | |
161 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */ | |
162 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */ | |
163 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */ | |
164 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */ | |
165 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */ | |
166 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */ | |
167 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */ | |
168 /** | |
169 * @} | |
170 */ | |
171 | |
172 /** @defgroup I2C_LL_EC_IT IT Defines | |
173 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions | |
174 * @{ | |
175 */ | |
176 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */ | |
177 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */ | |
178 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */ | |
179 /** | |
180 * @} | |
181 */ | |
182 | |
183 #if defined(I2C_FLTR_ANOFF) | |
184 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection | |
185 * @{ | |
186 */ | |
187 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ | |
188 #define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/ | |
189 /** | |
190 * @} | |
191 */ | |
192 | |
193 #endif | |
194 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length | |
195 * @{ | |
196 */ | |
197 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */ | |
198 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */ | |
199 /** | |
200 * @} | |
201 */ | |
202 | |
203 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle | |
204 * @{ | |
205 */ | |
206 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */ | |
207 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */ | |
208 /** | |
209 * @} | |
210 */ | |
211 | |
212 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode | |
213 * @{ | |
214 */ | |
215 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */ | |
216 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */ | |
217 /** | |
218 * @} | |
219 */ | |
220 | |
221 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode | |
222 * @{ | |
223 */ | |
224 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ | |
225 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */ | |
226 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */ | |
227 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */ | |
228 /** | |
229 * @} | |
230 */ | |
231 | |
232 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation | |
233 * @{ | |
234 */ | |
235 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */ | |
236 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/ | |
237 /** | |
238 * @} | |
239 */ | |
240 | |
241 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction | |
242 * @{ | |
243 */ | |
244 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */ | |
245 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */ | |
246 /** | |
247 * @} | |
248 */ | |
249 | |
250 /** | |
251 * @} | |
252 */ | |
253 | |
254 /* Exported macro ------------------------------------------------------------*/ | |
255 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros | |
256 * @{ | |
257 */ | |
258 | |
259 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros | |
260 * @{ | |
261 */ | |
262 | |
263 /** | |
264 * @brief Write a value in I2C register | |
265 * @param __INSTANCE__ I2C Instance | |
266 * @param __REG__ Register to be written | |
267 * @param __VALUE__ Value to be written in the register | |
268 * @retval None | |
269 */ | |
270 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) | |
271 | |
272 /** | |
273 * @brief Read a value in I2C register | |
274 * @param __INSTANCE__ I2C Instance | |
275 * @param __REG__ Register to be read | |
276 * @retval Register value | |
277 */ | |
278 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) | |
279 /** | |
280 * @} | |
281 */ | |
282 | |
283 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper | |
284 * @{ | |
285 */ | |
286 | |
287 /** | |
288 * @brief Convert Peripheral Clock Frequency in Mhz. | |
289 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). | |
290 * @retval Value of peripheral clock (in Mhz) | |
291 */ | |
292 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U) | |
293 | |
294 /** | |
295 * @brief Convert Peripheral Clock Frequency in Hz. | |
296 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz). | |
297 * @retval Value of peripheral clock (in Hz) | |
298 */ | |
299 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U) | |
300 | |
301 /** | |
302 * @brief Compute I2C Clock rising time. | |
303 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz). | |
304 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). | |
305 * @retval Value between Min_Data=0x02 and Max_Data=0x3F | |
306 */ | |
307 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) | |
308 | |
309 /** | |
310 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value. | |
311 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). | |
312 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). | |
313 * @param __DUTYCYCLE__ This parameter can be one of the following values: | |
314 * @arg @ref LL_I2C_DUTYCYCLE_2 | |
315 * @arg @ref LL_I2C_DUTYCYCLE_16_9 | |
316 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. | |
317 */ | |
318 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \ | |
319 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \ | |
320 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__)))) | |
321 | |
322 /** | |
323 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value. | |
324 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). | |
325 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz). | |
326 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF. | |
327 */ | |
328 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) | |
329 | |
330 /** | |
331 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value. | |
332 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). | |
333 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz). | |
334 * @param __DUTYCYCLE__ This parameter can be one of the following values: | |
335 * @arg @ref LL_I2C_DUTYCYCLE_2 | |
336 * @arg @ref LL_I2C_DUTYCYCLE_16_9 | |
337 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF | |
338 */ | |
339 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \ | |
340 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \ | |
341 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U)))) | |
342 | |
343 /** | |
344 * @brief Get the Least significant bits of a 10-Bits address. | |
345 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. | |
346 * @retval Value between Min_Data=0x00 and Max_Data=0xFF | |
347 */ | |
348 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) | |
349 | |
350 /** | |
351 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction. | |
352 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. | |
353 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6 | |
354 */ | |
355 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) | |
356 | |
357 /** | |
358 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction. | |
359 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. | |
360 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7 | |
361 */ | |
362 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) | |
363 | |
364 /** | |
365 * @} | |
366 */ | |
367 | |
368 /** | |
369 * @} | |
370 */ | |
371 | |
372 /* Exported functions --------------------------------------------------------*/ | |
373 | |
374 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions | |
375 * @{ | |
376 */ | |
377 | |
378 /** @defgroup I2C_LL_EF_Configuration Configuration | |
379 * @{ | |
380 */ | |
381 | |
382 /** | |
383 * @brief Enable I2C peripheral (PE = 1). | |
384 * @rmtoll CR1 PE LL_I2C_Enable | |
385 * @param I2Cx I2C Instance. | |
386 * @retval None | |
387 */ | |
388 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) | |
389 { | |
390 SET_BIT(I2Cx->CR1, I2C_CR1_PE); | |
391 } | |
392 | |
393 /** | |
394 * @brief Disable I2C peripheral (PE = 0). | |
395 * @rmtoll CR1 PE LL_I2C_Disable | |
396 * @param I2Cx I2C Instance. | |
397 * @retval None | |
398 */ | |
399 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) | |
400 { | |
401 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); | |
402 } | |
403 | |
404 /** | |
405 * @brief Check if the I2C peripheral is enabled or disabled. | |
406 * @rmtoll CR1 PE LL_I2C_IsEnabled | |
407 * @param I2Cx I2C Instance. | |
408 * @retval State of bit (1 or 0). | |
409 */ | |
410 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) | |
411 { | |
412 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); | |
413 } | |
414 | |
415 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) | |
416 /** | |
417 * @brief Configure Noise Filters (Analog and Digital). | |
418 * @note If the analog filter is also enabled, the digital filter is added to analog filter. | |
419 * The filters can only be programmed when the I2C is disabled (PE = 0). | |
420 * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n | |
421 * FLTR DNF LL_I2C_ConfigFilters | |
422 * @param I2Cx I2C Instance. | |
423 * @param AnalogFilter This parameter can be one of the following values: | |
424 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE | |
425 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE | |
426 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1) | |
427 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1. | |
428 * @retval None | |
429 */ | |
430 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) | |
431 { | |
432 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter); | |
433 } | |
434 #endif | |
435 #if defined(I2C_FLTR_DNF) | |
436 | |
437 /** | |
438 * @brief Configure Digital Noise Filter. | |
439 * @note If the analog filter is also enabled, the digital filter is added to analog filter. | |
440 * This filter can only be programmed when the I2C is disabled (PE = 0). | |
441 * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter | |
442 * @param I2Cx I2C Instance. | |
443 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1) | |
444 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1. | |
445 * @retval None | |
446 */ | |
447 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) | |
448 { | |
449 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter); | |
450 } | |
451 | |
452 /** | |
453 * @brief Get the current Digital Noise Filter configuration. | |
454 * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter | |
455 * @param I2Cx I2C Instance. | |
456 * @retval Value between Min_Data=0x0 and Max_Data=0xF | |
457 */ | |
458 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) | |
459 { | |
460 return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF)); | |
461 } | |
462 #endif | |
463 #if defined(I2C_FLTR_ANOFF) | |
464 | |
465 /** | |
466 * @brief Enable Analog Noise Filter. | |
467 * @note This filter can only be programmed when the I2C is disabled (PE = 0). | |
468 * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter | |
469 * @param I2Cx I2C Instance. | |
470 * @retval None | |
471 */ | |
472 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) | |
473 { | |
474 CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF); | |
475 } | |
476 | |
477 /** | |
478 * @brief Disable Analog Noise Filter. | |
479 * @note This filter can only be programmed when the I2C is disabled (PE = 0). | |
480 * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter | |
481 * @param I2Cx I2C Instance. | |
482 * @retval None | |
483 */ | |
484 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) | |
485 { | |
486 SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF); | |
487 } | |
488 | |
489 /** | |
490 * @brief Check if Analog Noise Filter is enabled or disabled. | |
491 * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter | |
492 * @param I2Cx I2C Instance. | |
493 * @retval State of bit (1 or 0). | |
494 */ | |
495 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) | |
496 { | |
497 return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF)); | |
498 } | |
499 #endif | |
500 | |
501 /** | |
502 * @brief Enable DMA transmission requests. | |
503 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX | |
504 * @param I2Cx I2C Instance. | |
505 * @retval None | |
506 */ | |
507 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) | |
508 { | |
509 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); | |
510 } | |
511 | |
512 /** | |
513 * @brief Disable DMA transmission requests. | |
514 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX | |
515 * @param I2Cx I2C Instance. | |
516 * @retval None | |
517 */ | |
518 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) | |
519 { | |
520 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); | |
521 } | |
522 | |
523 /** | |
524 * @brief Check if DMA transmission requests are enabled or disabled. | |
525 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX | |
526 * @param I2Cx I2C Instance. | |
527 * @retval State of bit (1 or 0). | |
528 */ | |
529 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) | |
530 { | |
531 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); | |
532 } | |
533 | |
534 /** | |
535 * @brief Enable DMA reception requests. | |
536 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX | |
537 * @param I2Cx I2C Instance. | |
538 * @retval None | |
539 */ | |
540 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) | |
541 { | |
542 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); | |
543 } | |
544 | |
545 /** | |
546 * @brief Disable DMA reception requests. | |
547 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX | |
548 * @param I2Cx I2C Instance. | |
549 * @retval None | |
550 */ | |
551 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) | |
552 { | |
553 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); | |
554 } | |
555 | |
556 /** | |
557 * @brief Check if DMA reception requests are enabled or disabled. | |
558 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX | |
559 * @param I2Cx I2C Instance. | |
560 * @retval State of bit (1 or 0). | |
561 */ | |
562 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) | |
563 { | |
564 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); | |
565 } | |
566 | |
567 /** | |
568 * @brief Get the data register address used for DMA transfer. | |
569 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr | |
570 * @param I2Cx I2C Instance. | |
571 * @retval Address of data register | |
572 */ | |
573 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx) | |
574 { | |
575 return (uint32_t) & (I2Cx->DR); | |
576 } | |
577 | |
578 /** | |
579 * @brief Enable Clock stretching. | |
580 * @note This bit can only be programmed when the I2C is disabled (PE = 0). | |
581 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching | |
582 * @param I2Cx I2C Instance. | |
583 * @retval None | |
584 */ | |
585 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) | |
586 { | |
587 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); | |
588 } | |
589 | |
590 /** | |
591 * @brief Disable Clock stretching. | |
592 * @note This bit can only be programmed when the I2C is disabled (PE = 0). | |
593 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching | |
594 * @param I2Cx I2C Instance. | |
595 * @retval None | |
596 */ | |
597 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) | |
598 { | |
599 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); | |
600 } | |
601 | |
602 /** | |
603 * @brief Check if Clock stretching is enabled or disabled. | |
604 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching | |
605 * @param I2Cx I2C Instance. | |
606 * @retval State of bit (1 or 0). | |
607 */ | |
608 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) | |
609 { | |
610 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); | |
611 } | |
612 | |
613 /** | |
614 * @brief Enable General Call. | |
615 * @note When enabled the Address 0x00 is ACKed. | |
616 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall | |
617 * @param I2Cx I2C Instance. | |
618 * @retval None | |
619 */ | |
620 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) | |
621 { | |
622 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC); | |
623 } | |
624 | |
625 /** | |
626 * @brief Disable General Call. | |
627 * @note When disabled the Address 0x00 is NACKed. | |
628 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall | |
629 * @param I2Cx I2C Instance. | |
630 * @retval None | |
631 */ | |
632 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) | |
633 { | |
634 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC); | |
635 } | |
636 | |
637 /** | |
638 * @brief Check if General Call is enabled or disabled. | |
639 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall | |
640 * @param I2Cx I2C Instance. | |
641 * @retval State of bit (1 or 0). | |
642 */ | |
643 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) | |
644 { | |
645 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC)); | |
646 } | |
647 | |
648 /** | |
649 * @brief Set the Own Address1. | |
650 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n | |
651 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n | |
652 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n | |
653 * OAR1 ADDMODE LL_I2C_SetOwnAddress1 | |
654 * @param I2Cx I2C Instance. | |
655 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. | |
656 * @param OwnAddrSize This parameter can be one of the following values: | |
657 * @arg @ref LL_I2C_OWNADDRESS1_7BIT | |
658 * @arg @ref LL_I2C_OWNADDRESS1_10BIT | |
659 * @retval None | |
660 */ | |
661 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) | |
662 { | |
663 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize); | |
664 } | |
665 | |
666 /** | |
667 * @brief Set the 7bits Own Address2. | |
668 * @note This action has no effect if own address2 is enabled. | |
669 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2 | |
670 * @param I2Cx I2C Instance. | |
671 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F. | |
672 * @retval None | |
673 */ | |
674 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2) | |
675 { | |
676 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2); | |
677 } | |
678 | |
679 /** | |
680 * @brief Enable acknowledge on Own Address2 match address. | |
681 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2 | |
682 * @param I2Cx I2C Instance. | |
683 * @retval None | |
684 */ | |
685 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) | |
686 { | |
687 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); | |
688 } | |
689 | |
690 /** | |
691 * @brief Disable acknowledge on Own Address2 match address. | |
692 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2 | |
693 * @param I2Cx I2C Instance. | |
694 * @retval None | |
695 */ | |
696 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) | |
697 { | |
698 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); | |
699 } | |
700 | |
701 /** | |
702 * @brief Check if Own Address1 acknowledge is enabled or disabled. | |
703 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2 | |
704 * @param I2Cx I2C Instance. | |
705 * @retval State of bit (1 or 0). | |
706 */ | |
707 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) | |
708 { | |
709 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL)); | |
710 } | |
711 | |
712 /** | |
713 * @brief Configure the Peripheral clock frequency. | |
714 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock | |
715 * @param I2Cx I2C Instance. | |
716 * @param PeriphClock Peripheral Clock (in Hz) | |
717 * @retval None | |
718 */ | |
719 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock) | |
720 { | |
721 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock)); | |
722 } | |
723 | |
724 /** | |
725 * @brief Get the Peripheral clock frequency. | |
726 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock | |
727 * @param I2Cx I2C Instance. | |
728 * @retval Value of Peripheral Clock (in Hz) | |
729 */ | |
730 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx) | |
731 { | |
732 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ))); | |
733 } | |
734 | |
735 /** | |
736 * @brief Configure the Duty cycle (Fast mode only). | |
737 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle | |
738 * @param I2Cx I2C Instance. | |
739 * @param DutyCycle This parameter can be one of the following values: | |
740 * @arg @ref LL_I2C_DUTYCYCLE_2 | |
741 * @arg @ref LL_I2C_DUTYCYCLE_16_9 | |
742 * @retval None | |
743 */ | |
744 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle) | |
745 { | |
746 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle); | |
747 } | |
748 | |
749 /** | |
750 * @brief Get the Duty cycle (Fast mode only). | |
751 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle | |
752 * @param I2Cx I2C Instance. | |
753 * @retval Returned value can be one of the following values: | |
754 * @arg @ref LL_I2C_DUTYCYCLE_2 | |
755 * @arg @ref LL_I2C_DUTYCYCLE_16_9 | |
756 */ | |
757 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx) | |
758 { | |
759 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY)); | |
760 } | |
761 | |
762 /** | |
763 * @brief Configure the I2C master clock speed mode. | |
764 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode | |
765 * @param I2Cx I2C Instance. | |
766 * @param ClockSpeedMode This parameter can be one of the following values: | |
767 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE | |
768 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE | |
769 * @retval None | |
770 */ | |
771 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode) | |
772 { | |
773 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode); | |
774 } | |
775 | |
776 /** | |
777 * @brief Get the the I2C master speed mode. | |
778 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode | |
779 * @param I2Cx I2C Instance. | |
780 * @retval Returned value can be one of the following values: | |
781 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE | |
782 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE | |
783 */ | |
784 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx) | |
785 { | |
786 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS)); | |
787 } | |
788 | |
789 /** | |
790 * @brief Configure the SCL, SDA rising time. | |
791 * @note This bit can only be programmed when the I2C is disabled (PE = 0). | |
792 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime | |
793 * @param I2Cx I2C Instance. | |
794 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F. | |
795 * @retval None | |
796 */ | |
797 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime) | |
798 { | |
799 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime); | |
800 } | |
801 | |
802 /** | |
803 * @brief Get the SCL, SDA rising time. | |
804 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime | |
805 * @param I2Cx I2C Instance. | |
806 * @retval Value between Min_Data=0x02 and Max_Data=0x3F | |
807 */ | |
808 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx) | |
809 { | |
810 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE)); | |
811 } | |
812 | |
813 /** | |
814 * @brief Configure the SCL high and low period. | |
815 * @note This bit can only be programmed when the I2C is disabled (PE = 0). | |
816 * @rmtoll CCR CCR LL_I2C_SetClockPeriod | |
817 * @param I2Cx I2C Instance. | |
818 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. | |
819 * @retval None | |
820 */ | |
821 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod) | |
822 { | |
823 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod); | |
824 } | |
825 | |
826 /** | |
827 * @brief Get the SCL high and low period. | |
828 * @rmtoll CCR CCR LL_I2C_GetClockPeriod | |
829 * @param I2Cx I2C Instance. | |
830 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. | |
831 */ | |
832 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx) | |
833 { | |
834 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR)); | |
835 } | |
836 | |
837 /** | |
838 * @brief Configure the SCL speed. | |
839 * @note This bit can only be programmed when the I2C is disabled (PE = 0). | |
840 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n | |
841 * TRISE TRISE LL_I2C_ConfigSpeed\n | |
842 * CCR FS LL_I2C_ConfigSpeed\n | |
843 * CCR DUTY LL_I2C_ConfigSpeed\n | |
844 * CCR CCR LL_I2C_ConfigSpeed | |
845 * @param I2Cx I2C Instance. | |
846 * @param PeriphClock Peripheral Clock (in Hz) | |
847 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz). | |
848 * @param DutyCycle This parameter can be one of the following values: | |
849 * @arg @ref LL_I2C_DUTYCYCLE_2 | |
850 * @arg @ref LL_I2C_DUTYCYCLE_16_9 | |
851 * @retval None | |
852 */ | |
853 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, | |
854 uint32_t DutyCycle) | |
855 { | |
856 register uint32_t freqrange = 0x0U; | |
857 register uint32_t clockconfig = 0x0U; | |
858 | |
859 /* Compute frequency range */ | |
860 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock); | |
861 | |
862 /* Configure I2Cx: Frequency range register */ | |
863 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange); | |
864 | |
865 /* Configure I2Cx: Rise Time register */ | |
866 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed)); | |
867 | |
868 /* Configure Speed mode, Duty Cycle and Clock control register value */ | |
869 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD) | |
870 { | |
871 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */ | |
872 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \ | |
873 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \ | |
874 DutyCycle; | |
875 } | |
876 else | |
877 { | |
878 /* Set Speed mode at standard for Clock Speed request in standard clock range */ | |
879 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \ | |
880 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed); | |
881 } | |
882 | |
883 /* Configure I2Cx: Clock control register */ | |
884 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig); | |
885 } | |
886 | |
887 /** | |
888 * @brief Configure peripheral mode. | |
889 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
890 * SMBus feature is supported by the I2Cx Instance. | |
891 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n | |
892 * CR1 SMBTYPE LL_I2C_SetMode\n | |
893 * CR1 ENARP LL_I2C_SetMode | |
894 * @param I2Cx I2C Instance. | |
895 * @param PeripheralMode This parameter can be one of the following values: | |
896 * @arg @ref LL_I2C_MODE_I2C | |
897 * @arg @ref LL_I2C_MODE_SMBUS_HOST | |
898 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE | |
899 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP | |
900 * @retval None | |
901 */ | |
902 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) | |
903 { | |
904 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode); | |
905 } | |
906 | |
907 /** | |
908 * @brief Get peripheral mode. | |
909 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
910 * SMBus feature is supported by the I2Cx Instance. | |
911 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n | |
912 * CR1 SMBTYPE LL_I2C_GetMode\n | |
913 * CR1 ENARP LL_I2C_GetMode | |
914 * @param I2Cx I2C Instance. | |
915 * @retval Returned value can be one of the following values: | |
916 * @arg @ref LL_I2C_MODE_I2C | |
917 * @arg @ref LL_I2C_MODE_SMBUS_HOST | |
918 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE | |
919 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP | |
920 */ | |
921 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) | |
922 { | |
923 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)); | |
924 } | |
925 | |
926 /** | |
927 * @brief Enable SMBus alert (Host or Device mode) | |
928 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
929 * SMBus feature is supported by the I2Cx Instance. | |
930 * @note SMBus Device mode: | |
931 * - SMBus Alert pin is drived low and | |
932 * Alert Response Address Header acknowledge is enabled. | |
933 * SMBus Host mode: | |
934 * - SMBus Alert pin management is supported. | |
935 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert | |
936 * @param I2Cx I2C Instance. | |
937 * @retval None | |
938 */ | |
939 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) | |
940 { | |
941 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT); | |
942 } | |
943 | |
944 /** | |
945 * @brief Disable SMBus alert (Host or Device mode) | |
946 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
947 * SMBus feature is supported by the I2Cx Instance. | |
948 * @note SMBus Device mode: | |
949 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and | |
950 * Alert Response Address Header acknowledge is disabled. | |
951 * SMBus Host mode: | |
952 * - SMBus Alert pin management is not supported. | |
953 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert | |
954 * @param I2Cx I2C Instance. | |
955 * @retval None | |
956 */ | |
957 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) | |
958 { | |
959 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT); | |
960 } | |
961 | |
962 /** | |
963 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. | |
964 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
965 * SMBus feature is supported by the I2Cx Instance. | |
966 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert | |
967 * @param I2Cx I2C Instance. | |
968 * @retval State of bit (1 or 0). | |
969 */ | |
970 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) | |
971 { | |
972 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT)); | |
973 } | |
974 | |
975 /** | |
976 * @brief Enable SMBus Packet Error Calculation (PEC). | |
977 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
978 * SMBus feature is supported by the I2Cx Instance. | |
979 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC | |
980 * @param I2Cx I2C Instance. | |
981 * @retval None | |
982 */ | |
983 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) | |
984 { | |
985 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC); | |
986 } | |
987 | |
988 /** | |
989 * @brief Disable SMBus Packet Error Calculation (PEC). | |
990 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
991 * SMBus feature is supported by the I2Cx Instance. | |
992 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC | |
993 * @param I2Cx I2C Instance. | |
994 * @retval None | |
995 */ | |
996 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) | |
997 { | |
998 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC); | |
999 } | |
1000 | |
1001 /** | |
1002 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. | |
1003 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1004 * SMBus feature is supported by the I2Cx Instance. | |
1005 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC | |
1006 * @param I2Cx I2C Instance. | |
1007 * @retval State of bit (1 or 0). | |
1008 */ | |
1009 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) | |
1010 { | |
1011 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC)); | |
1012 } | |
1013 | |
1014 /** | |
1015 * @} | |
1016 */ | |
1017 | |
1018 /** @defgroup I2C_LL_EF_IT_Management IT_Management | |
1019 * @{ | |
1020 */ | |
1021 | |
1022 /** | |
1023 * @brief Enable TXE interrupt. | |
1024 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n | |
1025 * CR2 ITBUFEN LL_I2C_EnableIT_TX | |
1026 * @param I2Cx I2C Instance. | |
1027 * @retval None | |
1028 */ | |
1029 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) | |
1030 { | |
1031 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); | |
1032 } | |
1033 | |
1034 /** | |
1035 * @brief Disable TXE interrupt. | |
1036 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n | |
1037 * CR2 ITBUFEN LL_I2C_DisableIT_TX | |
1038 * @param I2Cx I2C Instance. | |
1039 * @retval None | |
1040 */ | |
1041 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) | |
1042 { | |
1043 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); | |
1044 } | |
1045 | |
1046 /** | |
1047 * @brief Check if the TXE Interrupt is enabled or disabled. | |
1048 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n | |
1049 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX | |
1050 * @param I2Cx I2C Instance. | |
1051 * @retval State of bit (1 or 0). | |
1052 */ | |
1053 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) | |
1054 { | |
1055 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); | |
1056 } | |
1057 | |
1058 /** | |
1059 * @brief Enable RXNE interrupt. | |
1060 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n | |
1061 * CR2 ITBUFEN LL_I2C_EnableIT_RX | |
1062 * @param I2Cx I2C Instance. | |
1063 * @retval None | |
1064 */ | |
1065 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) | |
1066 { | |
1067 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); | |
1068 } | |
1069 | |
1070 /** | |
1071 * @brief Disable RXNE interrupt. | |
1072 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n | |
1073 * CR2 ITBUFEN LL_I2C_DisableIT_RX | |
1074 * @param I2Cx I2C Instance. | |
1075 * @retval None | |
1076 */ | |
1077 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) | |
1078 { | |
1079 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); | |
1080 } | |
1081 | |
1082 /** | |
1083 * @brief Check if the RXNE Interrupt is enabled or disabled. | |
1084 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n | |
1085 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX | |
1086 * @param I2Cx I2C Instance. | |
1087 * @retval State of bit (1 or 0). | |
1088 */ | |
1089 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) | |
1090 { | |
1091 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); | |
1092 } | |
1093 | |
1094 /** | |
1095 * @brief Enable Events interrupts. | |
1096 * @note Any of these events will generate interrupt : | |
1097 * Start Bit (SB) | |
1098 * Address sent, Address matched (ADDR) | |
1099 * 10-bit header sent (ADD10) | |
1100 * Stop detection (STOPF) | |
1101 * Byte transfer finished (BTF) | |
1102 * | |
1103 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) : | |
1104 * Receive buffer not empty (RXNE) | |
1105 * Transmit buffer empty (TXE) | |
1106 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT | |
1107 * @param I2Cx I2C Instance. | |
1108 * @retval None | |
1109 */ | |
1110 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx) | |
1111 { | |
1112 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); | |
1113 } | |
1114 | |
1115 /** | |
1116 * @brief Disable Events interrupts. | |
1117 * @note Any of these events will generate interrupt : | |
1118 * Start Bit (SB) | |
1119 * Address sent, Address matched (ADDR) | |
1120 * 10-bit header sent (ADD10) | |
1121 * Stop detection (STOPF) | |
1122 * Byte transfer finished (BTF) | |
1123 * Receive buffer not empty (RXNE) | |
1124 * Transmit buffer empty (TXE) | |
1125 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT | |
1126 * @param I2Cx I2C Instance. | |
1127 * @retval None | |
1128 */ | |
1129 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx) | |
1130 { | |
1131 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); | |
1132 } | |
1133 | |
1134 /** | |
1135 * @brief Check if Events interrupts are enabled or disabled. | |
1136 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT | |
1137 * @param I2Cx I2C Instance. | |
1138 * @retval State of bit (1 or 0). | |
1139 */ | |
1140 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx) | |
1141 { | |
1142 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN)); | |
1143 } | |
1144 | |
1145 /** | |
1146 * @brief Enable Buffer interrupts. | |
1147 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) : | |
1148 * Receive buffer not empty (RXNE) | |
1149 * Transmit buffer empty (TXE) | |
1150 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF | |
1151 * @param I2Cx I2C Instance. | |
1152 * @retval None | |
1153 */ | |
1154 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx) | |
1155 { | |
1156 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); | |
1157 } | |
1158 | |
1159 /** | |
1160 * @brief Disable Buffer interrupts. | |
1161 * @note Any of these Buffer events will generate interrupt : | |
1162 * Receive buffer not empty (RXNE) | |
1163 * Transmit buffer empty (TXE) | |
1164 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF | |
1165 * @param I2Cx I2C Instance. | |
1166 * @retval None | |
1167 */ | |
1168 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx) | |
1169 { | |
1170 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); | |
1171 } | |
1172 | |
1173 /** | |
1174 * @brief Check if Buffer interrupts are enabled or disabled. | |
1175 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF | |
1176 * @param I2Cx I2C Instance. | |
1177 * @retval State of bit (1 or 0). | |
1178 */ | |
1179 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx) | |
1180 { | |
1181 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN)); | |
1182 } | |
1183 | |
1184 /** | |
1185 * @brief Enable Error interrupts. | |
1186 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1187 * SMBus feature is supported by the I2Cx Instance. | |
1188 * @note Any of these errors will generate interrupt : | |
1189 * Bus Error detection (BERR) | |
1190 * Arbitration Loss (ARLO) | |
1191 * Acknowledge Failure(AF) | |
1192 * Overrun/Underrun (OVR) | |
1193 * SMBus Timeout detection (TIMEOUT) | |
1194 * SMBus PEC error detection (PECERR) | |
1195 * SMBus Alert pin event detection (SMBALERT) | |
1196 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR | |
1197 * @param I2Cx I2C Instance. | |
1198 * @retval None | |
1199 */ | |
1200 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) | |
1201 { | |
1202 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN); | |
1203 } | |
1204 | |
1205 /** | |
1206 * @brief Disable Error interrupts. | |
1207 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1208 * SMBus feature is supported by the I2Cx Instance. | |
1209 * @note Any of these errors will generate interrupt : | |
1210 * Bus Error detection (BERR) | |
1211 * Arbitration Loss (ARLO) | |
1212 * Acknowledge Failure(AF) | |
1213 * Overrun/Underrun (OVR) | |
1214 * SMBus Timeout detection (TIMEOUT) | |
1215 * SMBus PEC error detection (PECERR) | |
1216 * SMBus Alert pin event detection (SMBALERT) | |
1217 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR | |
1218 * @param I2Cx I2C Instance. | |
1219 * @retval None | |
1220 */ | |
1221 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) | |
1222 { | |
1223 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN); | |
1224 } | |
1225 | |
1226 /** | |
1227 * @brief Check if Error interrupts are enabled or disabled. | |
1228 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR | |
1229 * @param I2Cx I2C Instance. | |
1230 * @retval State of bit (1 or 0). | |
1231 */ | |
1232 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) | |
1233 { | |
1234 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN)); | |
1235 } | |
1236 | |
1237 /** | |
1238 * @} | |
1239 */ | |
1240 | |
1241 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management | |
1242 * @{ | |
1243 */ | |
1244 | |
1245 /** | |
1246 * @brief Indicate the status of Transmit data register empty flag. | |
1247 * @note RESET: When next data is written in Transmit data register. | |
1248 * SET: When Transmit data register is empty. | |
1249 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE | |
1250 * @param I2Cx I2C Instance. | |
1251 * @retval State of bit (1 or 0). | |
1252 */ | |
1253 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) | |
1254 { | |
1255 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE)); | |
1256 } | |
1257 | |
1258 /** | |
1259 * @brief Indicate the status of Byte Transfer Finished flag. | |
1260 * RESET: When Data byte transfer not done. | |
1261 * SET: When Data byte transfer succeeded. | |
1262 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF | |
1263 * @param I2Cx I2C Instance. | |
1264 * @retval State of bit (1 or 0). | |
1265 */ | |
1266 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx) | |
1267 { | |
1268 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF)); | |
1269 } | |
1270 | |
1271 /** | |
1272 * @brief Indicate the status of Receive data register not empty flag. | |
1273 * @note RESET: When Receive data register is read. | |
1274 * SET: When the received data is copied in Receive data register. | |
1275 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE | |
1276 * @param I2Cx I2C Instance. | |
1277 * @retval State of bit (1 or 0). | |
1278 */ | |
1279 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) | |
1280 { | |
1281 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE)); | |
1282 } | |
1283 | |
1284 /** | |
1285 * @brief Indicate the status of Start Bit (master mode). | |
1286 * @note RESET: When No Start condition. | |
1287 * SET: When Start condition is generated. | |
1288 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB | |
1289 * @param I2Cx I2C Instance. | |
1290 * @retval State of bit (1 or 0). | |
1291 */ | |
1292 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx) | |
1293 { | |
1294 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB)); | |
1295 } | |
1296 | |
1297 /** | |
1298 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode). | |
1299 * @note RESET: Clear default value. | |
1300 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode). | |
1301 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR | |
1302 * @param I2Cx I2C Instance. | |
1303 * @retval State of bit (1 or 0). | |
1304 */ | |
1305 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) | |
1306 { | |
1307 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR)); | |
1308 } | |
1309 | |
1310 /** | |
1311 * @brief Indicate the status of 10-bit header sent (master mode). | |
1312 * @note RESET: When no ADD10 event occured. | |
1313 * SET: When the master has sent the first address byte (header). | |
1314 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 | |
1315 * @param I2Cx I2C Instance. | |
1316 * @retval State of bit (1 or 0). | |
1317 */ | |
1318 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx) | |
1319 { | |
1320 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10)); | |
1321 } | |
1322 | |
1323 /** | |
1324 * @brief Indicate the status of Acknowledge failure flag. | |
1325 * @note RESET: No acknowledge failure. | |
1326 * SET: When an acknowledge failure is received after a byte transmission. | |
1327 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF | |
1328 * @param I2Cx I2C Instance. | |
1329 * @retval State of bit (1 or 0). | |
1330 */ | |
1331 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx) | |
1332 { | |
1333 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF)); | |
1334 } | |
1335 | |
1336 /** | |
1337 * @brief Indicate the status of Stop detection flag (slave mode). | |
1338 * @note RESET: Clear default value. | |
1339 * SET: When a Stop condition is detected. | |
1340 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP | |
1341 * @param I2Cx I2C Instance. | |
1342 * @retval State of bit (1 or 0). | |
1343 */ | |
1344 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) | |
1345 { | |
1346 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF)); | |
1347 } | |
1348 | |
1349 /** | |
1350 * @brief Indicate the status of Bus error flag. | |
1351 * @note RESET: Clear default value. | |
1352 * SET: When a misplaced Start or Stop condition is detected. | |
1353 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR | |
1354 * @param I2Cx I2C Instance. | |
1355 * @retval State of bit (1 or 0). | |
1356 */ | |
1357 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) | |
1358 { | |
1359 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR)); | |
1360 } | |
1361 | |
1362 /** | |
1363 * @brief Indicate the status of Arbitration lost flag. | |
1364 * @note RESET: Clear default value. | |
1365 * SET: When arbitration lost. | |
1366 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO | |
1367 * @param I2Cx I2C Instance. | |
1368 * @retval State of bit (1 or 0). | |
1369 */ | |
1370 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) | |
1371 { | |
1372 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO)); | |
1373 } | |
1374 | |
1375 /** | |
1376 * @brief Indicate the status of Overrun/Underrun flag. | |
1377 * @note RESET: Clear default value. | |
1378 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). | |
1379 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR | |
1380 * @param I2Cx I2C Instance. | |
1381 * @retval State of bit (1 or 0). | |
1382 */ | |
1383 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) | |
1384 { | |
1385 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR)); | |
1386 } | |
1387 | |
1388 /** | |
1389 * @brief Indicate the status of SMBus PEC error flag in reception. | |
1390 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1391 * SMBus feature is supported by the I2Cx Instance. | |
1392 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR | |
1393 * @param I2Cx I2C Instance. | |
1394 * @retval State of bit (1 or 0). | |
1395 */ | |
1396 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) | |
1397 { | |
1398 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR)); | |
1399 } | |
1400 | |
1401 /** | |
1402 * @brief Indicate the status of SMBus Timeout detection flag. | |
1403 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1404 * SMBus feature is supported by the I2Cx Instance. | |
1405 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT | |
1406 * @param I2Cx I2C Instance. | |
1407 * @retval State of bit (1 or 0). | |
1408 */ | |
1409 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) | |
1410 { | |
1411 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT)); | |
1412 } | |
1413 | |
1414 /** | |
1415 * @brief Indicate the status of SMBus alert flag. | |
1416 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1417 * SMBus feature is supported by the I2Cx Instance. | |
1418 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT | |
1419 * @param I2Cx I2C Instance. | |
1420 * @retval State of bit (1 or 0). | |
1421 */ | |
1422 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) | |
1423 { | |
1424 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT)); | |
1425 } | |
1426 | |
1427 /** | |
1428 * @brief Indicate the status of Bus Busy flag. | |
1429 * @note RESET: Clear default value. | |
1430 * SET: When a Start condition is detected. | |
1431 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY | |
1432 * @param I2Cx I2C Instance. | |
1433 * @retval State of bit (1 or 0). | |
1434 */ | |
1435 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) | |
1436 { | |
1437 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY)); | |
1438 } | |
1439 | |
1440 /** | |
1441 * @brief Indicate the status of Dual flag. | |
1442 * @note RESET: Received address matched with OAR1. | |
1443 * SET: Received address matched with OAR2. | |
1444 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL | |
1445 * @param I2Cx I2C Instance. | |
1446 * @retval State of bit (1 or 0). | |
1447 */ | |
1448 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx) | |
1449 { | |
1450 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF)); | |
1451 } | |
1452 | |
1453 /** | |
1454 * @brief Indicate the status of SMBus Host address reception (Slave mode). | |
1455 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1456 * SMBus feature is supported by the I2Cx Instance. | |
1457 * @note RESET: No SMBus Host address | |
1458 * SET: SMBus Host address received. | |
1459 * @note This status is cleared by hardware after a STOP condition or repeated START condition. | |
1460 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST | |
1461 * @param I2Cx I2C Instance. | |
1462 * @retval State of bit (1 or 0). | |
1463 */ | |
1464 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx) | |
1465 { | |
1466 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST)); | |
1467 } | |
1468 | |
1469 /** | |
1470 * @brief Indicate the status of SMBus Device default address reception (Slave mode). | |
1471 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1472 * SMBus feature is supported by the I2Cx Instance. | |
1473 * @note RESET: No SMBus Device default address | |
1474 * SET: SMBus Device default address received. | |
1475 * @note This status is cleared by hardware after a STOP condition or repeated START condition. | |
1476 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT | |
1477 * @param I2Cx I2C Instance. | |
1478 * @retval State of bit (1 or 0). | |
1479 */ | |
1480 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx) | |
1481 { | |
1482 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT)); | |
1483 } | |
1484 | |
1485 /** | |
1486 * @brief Indicate the status of General call address reception (Slave mode). | |
1487 * @note RESET: No Generall call address | |
1488 * SET: General call address received. | |
1489 * @note This status is cleared by hardware after a STOP condition or repeated START condition. | |
1490 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL | |
1491 * @param I2Cx I2C Instance. | |
1492 * @retval State of bit (1 or 0). | |
1493 */ | |
1494 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx) | |
1495 { | |
1496 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL)); | |
1497 } | |
1498 | |
1499 /** | |
1500 * @brief Indicate the status of Master/Slave flag. | |
1501 * @note RESET: Slave Mode. | |
1502 * SET: Master Mode. | |
1503 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL | |
1504 * @param I2Cx I2C Instance. | |
1505 * @retval State of bit (1 or 0). | |
1506 */ | |
1507 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx) | |
1508 { | |
1509 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL)); | |
1510 } | |
1511 | |
1512 /** | |
1513 * @brief Clear Address Matched flag. | |
1514 * @note Clearing this flag is done by a read access to the I2Cx_SR1 | |
1515 * register followed by a read access to the I2Cx_SR2 register. | |
1516 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR | |
1517 * @param I2Cx I2C Instance. | |
1518 * @retval None | |
1519 */ | |
1520 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) | |
1521 { | |
1522 __IO uint32_t tmpreg; | |
1523 tmpreg = I2Cx->SR1; | |
1524 (void) tmpreg; | |
1525 tmpreg = I2Cx->SR2; | |
1526 (void) tmpreg; | |
1527 } | |
1528 | |
1529 /** | |
1530 * @brief Clear Acknowledge failure flag. | |
1531 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF | |
1532 * @param I2Cx I2C Instance. | |
1533 * @retval None | |
1534 */ | |
1535 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx) | |
1536 { | |
1537 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF); | |
1538 } | |
1539 | |
1540 /** | |
1541 * @brief Clear Stop detection flag. | |
1542 * @note Clearing this flag is done by a read access to the I2Cx_SR1 | |
1543 * register followed by a write access to I2Cx_CR1 register. | |
1544 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n | |
1545 * CR1 PE LL_I2C_ClearFlag_STOP | |
1546 * @param I2Cx I2C Instance. | |
1547 * @retval None | |
1548 */ | |
1549 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) | |
1550 { | |
1551 __IO uint32_t tmpreg; | |
1552 tmpreg = I2Cx->SR1; | |
1553 (void) tmpreg; | |
1554 SET_BIT(I2Cx->CR1, I2C_CR1_PE); | |
1555 } | |
1556 | |
1557 /** | |
1558 * @brief Clear Bus error flag. | |
1559 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR | |
1560 * @param I2Cx I2C Instance. | |
1561 * @retval None | |
1562 */ | |
1563 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) | |
1564 { | |
1565 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR); | |
1566 } | |
1567 | |
1568 /** | |
1569 * @brief Clear Arbitration lost flag. | |
1570 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO | |
1571 * @param I2Cx I2C Instance. | |
1572 * @retval None | |
1573 */ | |
1574 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) | |
1575 { | |
1576 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO); | |
1577 } | |
1578 | |
1579 /** | |
1580 * @brief Clear Overrun/Underrun flag. | |
1581 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR | |
1582 * @param I2Cx I2C Instance. | |
1583 * @retval None | |
1584 */ | |
1585 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) | |
1586 { | |
1587 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR); | |
1588 } | |
1589 | |
1590 /** | |
1591 * @brief Clear SMBus PEC error flag. | |
1592 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR | |
1593 * @param I2Cx I2C Instance. | |
1594 * @retval None | |
1595 */ | |
1596 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) | |
1597 { | |
1598 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR); | |
1599 } | |
1600 | |
1601 /** | |
1602 * @brief Clear SMBus Timeout detection flag. | |
1603 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1604 * SMBus feature is supported by the I2Cx Instance. | |
1605 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT | |
1606 * @param I2Cx I2C Instance. | |
1607 * @retval None | |
1608 */ | |
1609 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) | |
1610 { | |
1611 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT); | |
1612 } | |
1613 | |
1614 /** | |
1615 * @brief Clear SMBus Alert flag. | |
1616 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1617 * SMBus feature is supported by the I2Cx Instance. | |
1618 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT | |
1619 * @param I2Cx I2C Instance. | |
1620 * @retval None | |
1621 */ | |
1622 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) | |
1623 { | |
1624 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT); | |
1625 } | |
1626 | |
1627 /** | |
1628 * @} | |
1629 */ | |
1630 | |
1631 /** @defgroup I2C_LL_EF_Data_Management Data_Management | |
1632 * @{ | |
1633 */ | |
1634 | |
1635 /** | |
1636 * @brief Enable Reset of I2C peripheral. | |
1637 * @rmtoll CR1 SWRST LL_I2C_EnableReset | |
1638 * @param I2Cx I2C Instance. | |
1639 * @retval None | |
1640 */ | |
1641 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx) | |
1642 { | |
1643 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST); | |
1644 } | |
1645 | |
1646 /** | |
1647 * @brief Disable Reset of I2C peripheral. | |
1648 * @rmtoll CR1 SWRST LL_I2C_DisableReset | |
1649 * @param I2Cx I2C Instance. | |
1650 * @retval None | |
1651 */ | |
1652 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx) | |
1653 { | |
1654 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST); | |
1655 } | |
1656 | |
1657 /** | |
1658 * @brief Check if the I2C peripheral is under reset state or not. | |
1659 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled | |
1660 * @param I2Cx I2C Instance. | |
1661 * @retval State of bit (1 or 0). | |
1662 */ | |
1663 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx) | |
1664 { | |
1665 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST)); | |
1666 } | |
1667 | |
1668 /** | |
1669 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. | |
1670 * @note Usage in Slave or Master mode. | |
1671 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData | |
1672 * @param I2Cx I2C Instance. | |
1673 * @param TypeAcknowledge This parameter can be one of the following values: | |
1674 * @arg @ref LL_I2C_ACK | |
1675 * @arg @ref LL_I2C_NACK | |
1676 * @retval None | |
1677 */ | |
1678 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) | |
1679 { | |
1680 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge); | |
1681 } | |
1682 | |
1683 /** | |
1684 * @brief Generate a START or RESTART condition | |
1685 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. | |
1686 * This action has no effect when RELOAD is set. | |
1687 * @rmtoll CR1 START LL_I2C_GenerateStartCondition | |
1688 * @param I2Cx I2C Instance. | |
1689 * @retval None | |
1690 */ | |
1691 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) | |
1692 { | |
1693 SET_BIT(I2Cx->CR1, I2C_CR1_START); | |
1694 } | |
1695 | |
1696 /** | |
1697 * @brief Generate a STOP condition after the current byte transfer (master mode). | |
1698 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition | |
1699 * @param I2Cx I2C Instance. | |
1700 * @retval None | |
1701 */ | |
1702 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) | |
1703 { | |
1704 SET_BIT(I2Cx->CR1, I2C_CR1_STOP); | |
1705 } | |
1706 | |
1707 /** | |
1708 * @brief Enable bit POS (master/host mode). | |
1709 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC. | |
1710 * @rmtoll CR1 POS LL_I2C_EnableBitPOS | |
1711 * @param I2Cx I2C Instance. | |
1712 * @retval None | |
1713 */ | |
1714 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx) | |
1715 { | |
1716 SET_BIT(I2Cx->CR1, I2C_CR1_POS); | |
1717 } | |
1718 | |
1719 /** | |
1720 * @brief Disable bit POS (master/host mode). | |
1721 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC. | |
1722 * @rmtoll CR1 POS LL_I2C_DisableBitPOS | |
1723 * @param I2Cx I2C Instance. | |
1724 * @retval None | |
1725 */ | |
1726 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx) | |
1727 { | |
1728 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS); | |
1729 } | |
1730 | |
1731 /** | |
1732 * @brief Check if bit POS is enabled or disabled. | |
1733 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS | |
1734 * @param I2Cx I2C Instance. | |
1735 * @retval State of bit (1 or 0). | |
1736 */ | |
1737 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx) | |
1738 { | |
1739 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS)); | |
1740 } | |
1741 | |
1742 /** | |
1743 * @brief Indicate the value of transfer direction. | |
1744 * @note RESET: Bus is in read transfer (peripheral point of view). | |
1745 * SET: Bus is in write transfer (peripheral point of view). | |
1746 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection | |
1747 * @param I2Cx I2C Instance. | |
1748 * @retval Returned value can be one of the following values: | |
1749 * @arg @ref LL_I2C_DIRECTION_WRITE | |
1750 * @arg @ref LL_I2C_DIRECTION_READ | |
1751 */ | |
1752 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) | |
1753 { | |
1754 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA)); | |
1755 } | |
1756 | |
1757 /** | |
1758 * @brief Enable DMA last transfer. | |
1759 * @note This action mean that next DMA EOT is the last transfer. | |
1760 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA | |
1761 * @param I2Cx I2C Instance. | |
1762 * @retval None | |
1763 */ | |
1764 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx) | |
1765 { | |
1766 SET_BIT(I2Cx->CR2, I2C_CR2_LAST); | |
1767 } | |
1768 | |
1769 /** | |
1770 * @brief Disable DMA last transfer. | |
1771 * @note This action mean that next DMA EOT is not the last transfer. | |
1772 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA | |
1773 * @param I2Cx I2C Instance. | |
1774 * @retval None | |
1775 */ | |
1776 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx) | |
1777 { | |
1778 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST); | |
1779 } | |
1780 | |
1781 /** | |
1782 * @brief Check if DMA last transfer is enabled or disabled. | |
1783 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA | |
1784 * @param I2Cx I2C Instance. | |
1785 * @retval State of bit (1 or 0). | |
1786 */ | |
1787 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx) | |
1788 { | |
1789 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST)); | |
1790 } | |
1791 | |
1792 /** | |
1793 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). | |
1794 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1795 * SMBus feature is supported by the I2Cx Instance. | |
1796 * @note This feature is cleared by hardware when the PEC byte is transferred or compared, | |
1797 * or by a START or STOP condition, it is also cleared by software. | |
1798 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare | |
1799 * @param I2Cx I2C Instance. | |
1800 * @retval None | |
1801 */ | |
1802 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) | |
1803 { | |
1804 SET_BIT(I2Cx->CR1, I2C_CR1_PEC); | |
1805 } | |
1806 | |
1807 /** | |
1808 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). | |
1809 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1810 * SMBus feature is supported by the I2Cx Instance. | |
1811 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare | |
1812 * @param I2Cx I2C Instance. | |
1813 * @retval None | |
1814 */ | |
1815 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx) | |
1816 { | |
1817 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC); | |
1818 } | |
1819 | |
1820 /** | |
1821 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not. | |
1822 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1823 * SMBus feature is supported by the I2Cx Instance. | |
1824 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare | |
1825 * @param I2Cx I2C Instance. | |
1826 * @retval State of bit (1 or 0). | |
1827 */ | |
1828 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) | |
1829 { | |
1830 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC)); | |
1831 } | |
1832 | |
1833 /** | |
1834 * @brief Get the SMBus Packet Error byte calculated. | |
1835 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not | |
1836 * SMBus feature is supported by the I2Cx Instance. | |
1837 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC | |
1838 * @param I2Cx I2C Instance. | |
1839 * @retval Value between Min_Data=0x00 and Max_Data=0xFF | |
1840 */ | |
1841 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) | |
1842 { | |
1843 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos); | |
1844 } | |
1845 | |
1846 /** | |
1847 * @brief Read Receive Data register. | |
1848 * @rmtoll DR DR LL_I2C_ReceiveData8 | |
1849 * @param I2Cx I2C Instance. | |
1850 * @retval Value between Min_Data=0x0 and Max_Data=0xFF | |
1851 */ | |
1852 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) | |
1853 { | |
1854 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR)); | |
1855 } | |
1856 | |
1857 /** | |
1858 * @brief Write in Transmit Data Register . | |
1859 * @rmtoll DR DR LL_I2C_TransmitData8 | |
1860 * @param I2Cx I2C Instance. | |
1861 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF | |
1862 * @retval None | |
1863 */ | |
1864 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) | |
1865 { | |
1866 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data); | |
1867 } | |
1868 | |
1869 /** | |
1870 * @} | |
1871 */ | |
1872 | |
1873 #if defined(USE_FULL_LL_DRIVER) | |
1874 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions | |
1875 * @{ | |
1876 */ | |
1877 | |
1878 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); | |
1879 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); | |
1880 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); | |
1881 | |
1882 | |
1883 /** | |
1884 * @} | |
1885 */ | |
1886 #endif /* USE_FULL_LL_DRIVER */ | |
1887 | |
1888 /** | |
1889 * @} | |
1890 */ | |
1891 | |
1892 /** | |
1893 * @} | |
1894 */ | |
1895 | |
1896 #endif /* I2C1 || I2C2 || I2C3 */ | |
1897 | |
1898 /** | |
1899 * @} | |
1900 */ | |
1901 | |
1902 #ifdef __cplusplus | |
1903 } | |
1904 #endif | |
1905 | |
1906 #endif /* __STM32F4xx_LL_I2C_H */ | |
1907 | |
1908 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |