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Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_fsmc.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of FSMC HAL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_LL_FSMC_H | |
38 #define __STM32F4xx_LL_FSMC_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 /* Includes ------------------------------------------------------------------*/ | |
45 #include "stm32f4xx_hal_def.h" | |
46 | |
47 /** @addtogroup STM32F4xx_HAL_Driver | |
48 * @{ | |
49 */ | |
50 | |
51 /** @addtogroup FSMC_LL | |
52 * @{ | |
53 */ | |
54 | |
55 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ | |
56 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) | |
57 /* Private types -------------------------------------------------------------*/ | |
58 /** @defgroup FSMC_LL_Private_Types FSMC Private Types | |
59 * @{ | |
60 */ | |
61 | |
62 /** | |
63 * @brief FSMC NORSRAM Configuration Structure definition | |
64 */ | |
65 typedef struct | |
66 { | |
67 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. | |
68 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ | |
69 | |
70 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are | |
71 multiplexed on the data bus or not. | |
72 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ | |
73 | |
74 uint32_t MemoryType; /*!< Specifies the type of external memory attached to | |
75 the corresponding memory device. | |
76 This parameter can be a value of @ref FSMC_Memory_Type */ | |
77 | |
78 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. | |
79 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ | |
80 | |
81 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, | |
82 valid only with synchronous burst Flash memories. | |
83 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ | |
84 | |
85 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing | |
86 the Flash memory in burst mode. | |
87 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ | |
88 | |
89 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash | |
90 memory, valid only when accessing Flash memories in burst mode. | |
91 This parameter can be a value of @ref FSMC_Wrap_Mode | |
92 This mode is available only for the STM32F405/407/4015/417xx devices */ | |
93 | |
94 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one | |
95 clock cycle before the wait state or during the wait state, | |
96 valid only when accessing memories in burst mode. | |
97 This parameter can be a value of @ref FSMC_Wait_Timing */ | |
98 | |
99 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. | |
100 This parameter can be a value of @ref FSMC_Write_Operation */ | |
101 | |
102 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait | |
103 signal, valid for Flash memory access in burst mode. | |
104 This parameter can be a value of @ref FSMC_Wait_Signal */ | |
105 | |
106 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. | |
107 This parameter can be a value of @ref FSMC_Extended_Mode */ | |
108 | |
109 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, | |
110 valid only with asynchronous Flash memories. | |
111 This parameter can be a value of @ref FSMC_AsynchronousWait */ | |
112 | |
113 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. | |
114 This parameter can be a value of @ref FSMC_Write_Burst */ | |
115 | |
116 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. | |
117 This parameter is only enabled through the FMC_BCR1 register, and don't care | |
118 through FMC_BCR2..4 registers. | |
119 This parameter can be a value of @ref FMC_Continous_Clock | |
120 This mode is available only for the STM32F412Vx/Zx/Rx devices */ | |
121 | |
122 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. | |
123 This parameter is only enabled through the FMC_BCR1 register, and don't care | |
124 through FMC_BCR2..4 registers. | |
125 This parameter can be a value of @ref FMC_Write_FIFO | |
126 This mode is available only for the STM32F412Vx/Vx devices */ | |
127 | |
128 uint32_t PageSize; /*!< Specifies the memory page size. | |
129 This parameter can be a value of @ref FMC_Page_Size */ | |
130 }FSMC_NORSRAM_InitTypeDef; | |
131 | |
132 /** | |
133 * @brief FSMC NORSRAM Timing parameters structure definition | |
134 */ | |
135 typedef struct | |
136 { | |
137 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure | |
138 the duration of the address setup time. | |
139 This parameter can be a value between Min_Data = 0 and Max_Data = 15. | |
140 @note This parameter is not used with synchronous NOR Flash memories. */ | |
141 | |
142 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure | |
143 the duration of the address hold time. | |
144 This parameter can be a value between Min_Data = 1 and Max_Data = 15. | |
145 @note This parameter is not used with synchronous NOR Flash memories. */ | |
146 | |
147 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure | |
148 the duration of the data setup time. | |
149 This parameter can be a value between Min_Data = 1 and Max_Data = 255. | |
150 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed | |
151 NOR Flash memories. */ | |
152 | |
153 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure | |
154 the duration of the bus turnaround. | |
155 This parameter can be a value between Min_Data = 0 and Max_Data = 15. | |
156 @note This parameter is only used for multiplexed NOR Flash memories. */ | |
157 | |
158 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of | |
159 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. | |
160 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM | |
161 accesses. */ | |
162 | |
163 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue | |
164 to the memory before getting the first data. | |
165 The parameter value depends on the memory type as shown below: | |
166 - It must be set to 0 in case of a CRAM | |
167 - It is don't care in asynchronous NOR, SRAM or ROM accesses | |
168 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories | |
169 with synchronous burst mode enable */ | |
170 | |
171 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. | |
172 This parameter can be a value of @ref FSMC_Access_Mode */ | |
173 | |
174 }FSMC_NORSRAM_TimingTypeDef; | |
175 | |
176 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
177 /** | |
178 * @brief FSMC NAND Configuration Structure definition | |
179 */ | |
180 typedef struct | |
181 { | |
182 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. | |
183 This parameter can be a value of @ref FSMC_NAND_Bank */ | |
184 | |
185 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. | |
186 This parameter can be any value of @ref FSMC_Wait_feature */ | |
187 | |
188 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. | |
189 This parameter can be any value of @ref FSMC_NAND_Data_Width */ | |
190 | |
191 uint32_t EccComputation; /*!< Enables or disables the ECC computation. | |
192 This parameter can be any value of @ref FSMC_ECC */ | |
193 | |
194 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. | |
195 This parameter can be any value of @ref FSMC_ECC_Page_Size */ | |
196 | |
197 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the | |
198 delay between CLE low and RE low. | |
199 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ | |
200 | |
201 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the | |
202 delay between ALE low and RE low. | |
203 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ | |
204 | |
205 }FSMC_NAND_InitTypeDef; | |
206 | |
207 /** | |
208 * @brief FSMC NAND/PCCARD Timing parameters structure definition | |
209 */ | |
210 typedef struct | |
211 { | |
212 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before | |
213 the command assertion for NAND-Flash read or write access | |
214 to common/Attribute or I/O memory space (depending on | |
215 the memory space timing to be configured). | |
216 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ | |
217 | |
218 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the | |
219 command for NAND-Flash read or write access to | |
220 common/Attribute or I/O memory space (depending on the | |
221 memory space timing to be configured). | |
222 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ | |
223 | |
224 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address | |
225 (and data for write access) after the command de-assertion | |
226 for NAND-Flash read or write access to common/Attribute | |
227 or I/O memory space (depending on the memory space timing | |
228 to be configured). | |
229 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ | |
230 | |
231 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the | |
232 data bus is kept in HiZ after the start of a NAND-Flash | |
233 write access to common/Attribute or I/O memory space (depending | |
234 on the memory space timing to be configured). | |
235 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ | |
236 | |
237 }FSMC_NAND_PCC_TimingTypeDef; | |
238 | |
239 /** | |
240 * @brief FSMC NAND Configuration Structure definition | |
241 */ | |
242 typedef struct | |
243 { | |
244 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. | |
245 This parameter can be any value of @ref FSMC_Wait_feature */ | |
246 | |
247 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the | |
248 delay between CLE low and RE low. | |
249 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ | |
250 | |
251 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the | |
252 delay between ALE low and RE low. | |
253 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ | |
254 | |
255 }FSMC_PCCARD_InitTypeDef; | |
256 /** | |
257 * @} | |
258 */ | |
259 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
260 | |
261 /* Private constants ---------------------------------------------------------*/ | |
262 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants | |
263 * @{ | |
264 */ | |
265 | |
266 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller | |
267 * @{ | |
268 */ | |
269 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank | |
270 * @{ | |
271 */ | |
272 #define FSMC_NORSRAM_BANK1 0x00000000U | |
273 #define FSMC_NORSRAM_BANK2 0x00000002U | |
274 #define FSMC_NORSRAM_BANK3 0x00000004U | |
275 #define FSMC_NORSRAM_BANK4 0x00000006U | |
276 /** | |
277 * @} | |
278 */ | |
279 | |
280 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing | |
281 * @{ | |
282 */ | |
283 #define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U | |
284 #define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U | |
285 /** | |
286 * @} | |
287 */ | |
288 | |
289 /** @defgroup FSMC_Memory_Type FSMC Memory Type | |
290 * @{ | |
291 */ | |
292 #define FSMC_MEMORY_TYPE_SRAM 0x00000000U | |
293 #define FSMC_MEMORY_TYPE_PSRAM 0x00000004U | |
294 #define FSMC_MEMORY_TYPE_NOR 0x00000008U | |
295 /** | |
296 * @} | |
297 */ | |
298 | |
299 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width | |
300 * @{ | |
301 */ | |
302 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U | |
303 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U | |
304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U | |
305 /** | |
306 * @} | |
307 */ | |
308 | |
309 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access | |
310 * @{ | |
311 */ | |
312 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U | |
313 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U | |
314 /** | |
315 * @} | |
316 */ | |
317 | |
318 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode | |
319 * @{ | |
320 */ | |
321 #define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U | |
322 #define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U | |
323 /** | |
324 * @} | |
325 */ | |
326 | |
327 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity | |
328 * @{ | |
329 */ | |
330 #define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U | |
331 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U | |
332 /** | |
333 * @} | |
334 */ | |
335 | |
336 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode | |
337 * @note These values are available only for the STM32F405/415/407/417xx devices. | |
338 * @{ | |
339 */ | |
340 #define FSMC_WRAP_MODE_DISABLE 0x00000000U | |
341 #define FSMC_WRAP_MODE_ENABLE 0x00000400U | |
342 /** | |
343 * @} | |
344 */ | |
345 | |
346 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing | |
347 * @{ | |
348 */ | |
349 #define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U | |
350 #define FSMC_WAIT_TIMING_DURING_WS 0x00000800U | |
351 /** | |
352 * @} | |
353 */ | |
354 | |
355 /** @defgroup FSMC_Write_Operation FSMC Write Operation | |
356 * @{ | |
357 */ | |
358 #define FSMC_WRITE_OPERATION_DISABLE 0x00000000U | |
359 #define FSMC_WRITE_OPERATION_ENABLE 0x00001000U | |
360 /** | |
361 * @} | |
362 */ | |
363 | |
364 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal | |
365 * @{ | |
366 */ | |
367 #define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U | |
368 #define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U | |
369 /** | |
370 * @} | |
371 */ | |
372 | |
373 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode | |
374 * @{ | |
375 */ | |
376 #define FSMC_EXTENDED_MODE_DISABLE 0x00000000U | |
377 #define FSMC_EXTENDED_MODE_ENABLE 0x00004000U | |
378 /** | |
379 * @} | |
380 */ | |
381 | |
382 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait | |
383 * @{ | |
384 */ | |
385 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U | |
386 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U | |
387 /** | |
388 * @} | |
389 */ | |
390 | |
391 /** @defgroup FSMC_Page_Size FSMC Page Size | |
392 * @{ | |
393 */ | |
394 #define FSMC_PAGE_SIZE_NONE 0x00000000U | |
395 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0) | |
396 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1) | |
397 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1)) | |
398 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2) | |
399 /** | |
400 * @} | |
401 */ | |
402 | |
403 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO | |
404 * @note These values are available only for the STM32F412Vx/Zx/Rx devices. | |
405 * @{ | |
406 */ | |
407 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS) | |
408 #define FSMC_WRITE_FIFO_ENABLE 0x00000000U | |
409 /** | |
410 * @} | |
411 */ | |
412 | |
413 /** @defgroup FSMC_Write_Burst FSMC Write Burst | |
414 * @{ | |
415 */ | |
416 #define FSMC_WRITE_BURST_DISABLE 0x00000000U | |
417 #define FSMC_WRITE_BURST_ENABLE 0x00080000U | |
418 /** | |
419 * @} | |
420 */ | |
421 | |
422 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock | |
423 * @note These values are available only for the STM32F412Vx/Zx/Rx devices. | |
424 * @{ | |
425 */ | |
426 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U | |
427 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U | |
428 /** | |
429 * @} | |
430 */ | |
431 | |
432 /** @defgroup FSMC_Access_Mode FSMC Access Mode | |
433 * @{ | |
434 */ | |
435 #define FSMC_ACCESS_MODE_A 0x00000000U | |
436 #define FSMC_ACCESS_MODE_B 0x10000000U | |
437 #define FSMC_ACCESS_MODE_C 0x20000000U | |
438 #define FSMC_ACCESS_MODE_D 0x30000000U | |
439 /** | |
440 * @} | |
441 */ | |
442 /** | |
443 * @} | |
444 */ | |
445 | |
446 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
447 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller | |
448 * @{ | |
449 */ | |
450 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank | |
451 * @{ | |
452 */ | |
453 #define FSMC_NAND_BANK2 0x00000010U | |
454 #define FSMC_NAND_BANK3 0x00000100U | |
455 /** | |
456 * @} | |
457 */ | |
458 | |
459 /** @defgroup FSMC_Wait_feature FSMC Wait feature | |
460 * @{ | |
461 */ | |
462 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U | |
463 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U | |
464 /** | |
465 * @} | |
466 */ | |
467 | |
468 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type | |
469 * @{ | |
470 */ | |
471 #define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U | |
472 #define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U | |
473 /** | |
474 * @} | |
475 */ | |
476 | |
477 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width | |
478 * @{ | |
479 */ | |
480 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U | |
481 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U | |
482 /** | |
483 * @} | |
484 */ | |
485 | |
486 /** @defgroup FSMC_ECC FSMC ECC | |
487 * @{ | |
488 */ | |
489 #define FSMC_NAND_ECC_DISABLE 0x00000000U | |
490 #define FSMC_NAND_ECC_ENABLE 0x00000040U | |
491 /** | |
492 * @} | |
493 */ | |
494 | |
495 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size | |
496 * @{ | |
497 */ | |
498 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U | |
499 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U | |
500 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U | |
501 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U | |
502 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U | |
503 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U | |
504 /** | |
505 * @} | |
506 */ | |
507 /** | |
508 * @} | |
509 */ | |
510 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
511 | |
512 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition | |
513 * @{ | |
514 */ | |
515 #define FSMC_IT_RISING_EDGE 0x00000008U | |
516 #define FSMC_IT_LEVEL 0x00000010U | |
517 #define FSMC_IT_FALLING_EDGE 0x00000020U | |
518 #define FSMC_IT_REFRESH_ERROR 0x00004000U | |
519 /** | |
520 * @} | |
521 */ | |
522 | |
523 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition | |
524 * @{ | |
525 */ | |
526 #define FSMC_FLAG_RISING_EDGE 0x00000001U | |
527 #define FSMC_FLAG_LEVEL 0x00000002U | |
528 #define FSMC_FLAG_FALLING_EDGE 0x00000004U | |
529 #define FSMC_FLAG_FEMPT 0x00000040U | |
530 /** | |
531 * @} | |
532 */ | |
533 | |
534 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition | |
535 * @{ | |
536 */ | |
537 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef | |
538 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef | |
539 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
540 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef | |
541 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef | |
542 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
543 | |
544 #define FSMC_NORSRAM_DEVICE FSMC_Bank1 | |
545 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E | |
546 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
547 #define FSMC_NAND_DEVICE FSMC_Bank2_3 | |
548 #define FSMC_PCCARD_DEVICE FSMC_Bank4 | |
549 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
550 | |
551 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8 | |
552 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16 | |
553 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32 | |
554 | |
555 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef | |
556 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef | |
557 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef | |
558 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef | |
559 | |
560 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init | |
561 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init | |
562 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init | |
563 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit | |
564 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable | |
565 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable | |
566 | |
567 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE | |
568 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE | |
569 | |
570 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
571 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef | |
572 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef | |
573 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef | |
574 | |
575 #define FMC_NAND_Init FSMC_NAND_Init | |
576 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init | |
577 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init | |
578 #define FMC_NAND_DeInit FSMC_NAND_DeInit | |
579 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable | |
580 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable | |
581 #define FMC_NAND_GetECC FSMC_NAND_GetECC | |
582 #define FMC_PCCARD_Init FSMC_PCCARD_Init | |
583 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init | |
584 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init | |
585 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init | |
586 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit | |
587 | |
588 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE | |
589 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE | |
590 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE | |
591 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE | |
592 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT | |
593 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT | |
594 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG | |
595 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG | |
596 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT | |
597 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT | |
598 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG | |
599 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG | |
600 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
601 | |
602 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef | |
603 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef | |
604 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
605 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef | |
606 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef | |
607 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
608 | |
609 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE | |
610 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE | |
611 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
612 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE | |
613 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE | |
614 | |
615 #define FMC_NAND_BANK2 FSMC_NAND_BANK2 | |
616 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
617 | |
618 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 | |
619 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 | |
620 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3 | |
621 | |
622 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE | |
623 #define FMC_IT_LEVEL FSMC_IT_LEVEL | |
624 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE | |
625 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR | |
626 | |
627 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE | |
628 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL | |
629 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE | |
630 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT | |
631 /** | |
632 * @} | |
633 */ | |
634 | |
635 /** | |
636 * @} | |
637 */ | |
638 | |
639 /* Private macro -------------------------------------------------------------*/ | |
640 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros | |
641 * @{ | |
642 */ | |
643 | |
644 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros | |
645 * @brief macros to handle NOR device enable/disable and read/write operations | |
646 * @{ | |
647 */ | |
648 /** | |
649 * @brief Enable the NORSRAM device access. | |
650 * @param __INSTANCE__ FSMC_NORSRAM Instance | |
651 * @param __BANK__ FSMC_NORSRAM Bank | |
652 * @retval none | |
653 */ | |
654 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) | |
655 | |
656 /** | |
657 * @brief Disable the NORSRAM device access. | |
658 * @param __INSTANCE__ FSMC_NORSRAM Instance | |
659 * @param __BANK__ FSMC_NORSRAM Bank | |
660 * @retval none | |
661 */ | |
662 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) | |
663 /** | |
664 * @} | |
665 */ | |
666 | |
667 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros | |
668 * @brief macros to handle NAND device enable/disable | |
669 * @{ | |
670 */ | |
671 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
672 /** | |
673 * @brief Enable the NAND device access. | |
674 * @param __INSTANCE__ FSMC_NAND Instance | |
675 * @param __BANK__ FSMC_NAND Bank | |
676 * @retval none | |
677 */ | |
678 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ | |
679 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) | |
680 | |
681 /** | |
682 * @brief Disable the NAND device access. | |
683 * @param __INSTANCE__ FSMC_NAND Instance | |
684 * @param __BANK__ FSMC_NAND Bank | |
685 * @retval none | |
686 */ | |
687 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ | |
688 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN)) | |
689 /** | |
690 * @} | |
691 */ | |
692 | |
693 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros | |
694 * @brief macros to handle SRAM read/write operations | |
695 * @{ | |
696 */ | |
697 /** | |
698 * @brief Enable the PCCARD device access. | |
699 * @param __INSTANCE__ FSMC_PCCARD Instance | |
700 * @retval none | |
701 */ | |
702 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) | |
703 | |
704 /** | |
705 * @brief Disable the PCCARD device access. | |
706 * @param __INSTANCE__ FSMC_PCCARD Instance | |
707 * @retval none | |
708 */ | |
709 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) | |
710 /** | |
711 * @} | |
712 */ | |
713 | |
714 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros | |
715 * @brief macros to handle FSMC flags and interrupts | |
716 * @{ | |
717 */ | |
718 /** | |
719 * @brief Enable the NAND device interrupt. | |
720 * @param __INSTANCE__ FSMC_NAND Instance | |
721 * @param __BANK__ FSMC_NAND Bank | |
722 * @param __INTERRUPT__ FSMC_NAND interrupt | |
723 * This parameter can be any combination of the following values: | |
724 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. | |
725 * @arg FSMC_IT_LEVEL: Interrupt level. | |
726 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. | |
727 * @retval None | |
728 */ | |
729 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ | |
730 ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) | |
731 | |
732 /** | |
733 * @brief Disable the NAND device interrupt. | |
734 * @param __INSTANCE__ FSMC_NAND Instance | |
735 * @param __BANK__ FSMC_NAND Bank | |
736 * @param __INTERRUPT__ FSMC_NAND interrupt | |
737 * This parameter can be any combination of the following values: | |
738 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. | |
739 * @arg FSMC_IT_LEVEL: Interrupt level. | |
740 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. | |
741 * @retval None | |
742 */ | |
743 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ | |
744 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) | |
745 | |
746 /** | |
747 * @brief Get flag status of the NAND device. | |
748 * @param __INSTANCE__ FSMC_NAND Instance | |
749 * @param __BANK__ FSMC_NAND Bank | |
750 * @param __FLAG__ FSMC_NAND flag | |
751 * This parameter can be any combination of the following values: | |
752 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. | |
753 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. | |
754 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. | |
755 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. | |
756 * @retval The state of FLAG (SET or RESET). | |
757 */ | |
758 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ | |
759 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) | |
760 | |
761 /** | |
762 * @brief Clear flag status of the NAND device. | |
763 * @param __INSTANCE__ FSMC_NAND Instance | |
764 * @param __BANK__ FSMC_NAND Bank | |
765 * @param __FLAG__ FSMC_NAND flag | |
766 * This parameter can be any combination of the following values: | |
767 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. | |
768 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. | |
769 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. | |
770 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. | |
771 * @retval None | |
772 */ | |
773 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ | |
774 ((__INSTANCE__)->SR3 &= ~(__FLAG__))) | |
775 | |
776 /** | |
777 * @brief Enable the PCCARD device interrupt. | |
778 * @param __INSTANCE__ FSMC_PCCARD Instance | |
779 * @param __INTERRUPT__ FSMC_PCCARD interrupt | |
780 * This parameter can be any combination of the following values: | |
781 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. | |
782 * @arg FSMC_IT_LEVEL: Interrupt level. | |
783 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. | |
784 * @retval None | |
785 */ | |
786 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) | |
787 | |
788 /** | |
789 * @brief Disable the PCCARD device interrupt. | |
790 * @param __INSTANCE__ FSMC_PCCARD Instance | |
791 * @param __INTERRUPT__ FSMC_PCCARD interrupt | |
792 * This parameter can be any combination of the following values: | |
793 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. | |
794 * @arg FSMC_IT_LEVEL: Interrupt level. | |
795 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. | |
796 * @retval None | |
797 */ | |
798 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) | |
799 | |
800 /** | |
801 * @brief Get flag status of the PCCARD device. | |
802 * @param __INSTANCE__ FSMC_PCCARD Instance | |
803 * @param __FLAG__ FSMC_PCCARD flag | |
804 * This parameter can be any combination of the following values: | |
805 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. | |
806 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. | |
807 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. | |
808 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. | |
809 * @retval The state of FLAG (SET or RESET). | |
810 */ | |
811 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) | |
812 | |
813 /** | |
814 * @brief Clear flag status of the PCCARD device. | |
815 * @param __INSTANCE__ FSMC_PCCARD Instance | |
816 * @param __FLAG__ FSMC_PCCARD flag | |
817 * This parameter can be any combination of the following values: | |
818 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. | |
819 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. | |
820 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. | |
821 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. | |
822 * @retval None | |
823 */ | |
824 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) | |
825 /** | |
826 * @} | |
827 */ | |
828 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
829 | |
830 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros | |
831 * @{ | |
832 */ | |
833 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ | |
834 ((__BANK__) == FSMC_NORSRAM_BANK2) || \ | |
835 ((__BANK__) == FSMC_NORSRAM_BANK3) || \ | |
836 ((__BANK__) == FSMC_NORSRAM_BANK4)) | |
837 | |
838 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ | |
839 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) | |
840 | |
841 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ | |
842 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ | |
843 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) | |
844 | |
845 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ | |
846 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ | |
847 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) | |
848 | |
849 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ | |
850 ((__MODE__) == FSMC_ACCESS_MODE_B) || \ | |
851 ((__MODE__) == FSMC_ACCESS_MODE_C) || \ | |
852 ((__MODE__) == FSMC_ACCESS_MODE_D)) | |
853 | |
854 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ | |
855 ((BANK) == FSMC_NAND_BANK3)) | |
856 | |
857 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ | |
858 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) | |
859 | |
860 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ | |
861 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) | |
862 | |
863 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ | |
864 ((STATE) == FSMC_NAND_ECC_ENABLE)) | |
865 | |
866 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ | |
867 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ | |
868 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ | |
869 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ | |
870 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ | |
871 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) | |
872 | |
873 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U) | |
874 | |
875 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U) | |
876 | |
877 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U) | |
878 | |
879 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U) | |
880 | |
881 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U) | |
882 | |
883 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U) | |
884 | |
885 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) | |
886 | |
887 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) | |
888 | |
889 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) | |
890 | |
891 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) | |
892 | |
893 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ | |
894 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) | |
895 | |
896 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ | |
897 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) | |
898 | |
899 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ | |
900 ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) | |
901 | |
902 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ | |
903 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) | |
904 | |
905 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ | |
906 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) | |
907 | |
908 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ | |
909 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) | |
910 | |
911 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ | |
912 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) | |
913 | |
914 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ | |
915 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) | |
916 | |
917 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) | |
918 | |
919 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ | |
920 ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) | |
921 | |
922 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) | |
923 | |
924 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) | |
925 | |
926 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) | |
927 | |
928 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) | |
929 | |
930 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ | |
931 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) | |
932 | |
933 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) | |
934 | |
935 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \ | |
936 ((SIZE) == FSMC_PAGE_SIZE_128) || \ | |
937 ((SIZE) == FSMC_PAGE_SIZE_256) || \ | |
938 ((SIZE) == FSMC_PAGE_SIZE_512) || \ | |
939 ((SIZE) == FSMC_PAGE_SIZE_1024)) | |
940 | |
941 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \ | |
942 ((FIFO) == FSMC_WRITE_FIFO_ENABLE)) | |
943 | |
944 /** | |
945 * @} | |
946 */ | |
947 /** | |
948 * @} | |
949 */ | |
950 | |
951 /* Private functions ---------------------------------------------------------*/ | |
952 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions | |
953 * @{ | |
954 */ | |
955 | |
956 /** @defgroup FSMC_LL_NORSRAM NOR SRAM | |
957 * @{ | |
958 */ | |
959 | |
960 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions | |
961 * @{ | |
962 */ | |
963 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); | |
964 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); | |
965 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); | |
966 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); | |
967 /** | |
968 * @} | |
969 */ | |
970 | |
971 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions | |
972 * @{ | |
973 */ | |
974 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); | |
975 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); | |
976 /** | |
977 * @} | |
978 */ | |
979 /** | |
980 * @} | |
981 */ | |
982 | |
983 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
984 /** @defgroup FSMC_LL_NAND NAND | |
985 * @{ | |
986 */ | |
987 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions | |
988 * @{ | |
989 */ | |
990 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); | |
991 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); | |
992 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); | |
993 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); | |
994 /** | |
995 * @} | |
996 */ | |
997 | |
998 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions | |
999 * @{ | |
1000 */ | |
1001 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); | |
1002 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); | |
1003 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); | |
1004 /** | |
1005 * @} | |
1006 */ | |
1007 /** | |
1008 * @} | |
1009 */ | |
1010 | |
1011 /** @defgroup FSMC_LL_PCCARD PCCARD | |
1012 * @{ | |
1013 */ | |
1014 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions | |
1015 * @{ | |
1016 */ | |
1017 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); | |
1018 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); | |
1019 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); | |
1020 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); | |
1021 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); | |
1022 /** | |
1023 * @} | |
1024 */ | |
1025 /** | |
1026 * @} | |
1027 */ | |
1028 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
1029 | |
1030 /** | |
1031 * @} | |
1032 */ | |
1033 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ | |
1034 | |
1035 /** | |
1036 * @} | |
1037 */ | |
1038 | |
1039 /** | |
1040 * @} | |
1041 */ | |
1042 | |
1043 #ifdef __cplusplus | |
1044 } | |
1045 #endif | |
1046 | |
1047 #endif /* __STM32F4xx_LL_FSMC_H */ | |
1048 | |
1049 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |