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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fmc.h
4 * @author MCD Application Team
5 * @brief Header file of FMC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_LL_FMC_H
38 #define __STM32F4xx_LL_FMC_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx_hal_def.h"
46
47 /** @addtogroup STM32F4xx_HAL_Driver
48 * @{
49 */
50
51 /** @addtogroup FMC_LL
52 * @{
53 */
54 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
55 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
56 /* Private types -------------------------------------------------------------*/
57 /** @defgroup FMC_LL_Private_Types FMC Private Types
58 * @{
59 */
60
61 /**
62 * @brief FMC NORSRAM Configuration Structure definition
63 */
64 typedef struct
65 {
66 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
67 This parameter can be a value of @ref FMC_NORSRAM_Bank */
68
69 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
70 multiplexed on the data bus or not.
71 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
72
73 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
74 the corresponding memory device.
75 This parameter can be a value of @ref FMC_Memory_Type */
76
77 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
78 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
79
80 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
81 valid only with synchronous burst Flash memories.
82 This parameter can be a value of @ref FMC_Burst_Access_Mode */
83
84 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
85 the Flash memory in burst mode.
86 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
87
88 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
89 memory, valid only when accessing Flash memories in burst mode.
90 This parameter can be a value of @ref FMC_Wrap_Mode
91 This mode is not available for the STM32F446/467/479xx devices */
92
93 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
94 clock cycle before the wait state or during the wait state,
95 valid only when accessing memories in burst mode.
96 This parameter can be a value of @ref FMC_Wait_Timing */
97
98 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
99 This parameter can be a value of @ref FMC_Write_Operation */
100
101 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
102 signal, valid for Flash memory access in burst mode.
103 This parameter can be a value of @ref FMC_Wait_Signal */
104
105 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
106 This parameter can be a value of @ref FMC_Extended_Mode */
107
108 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
109 valid only with asynchronous Flash memories.
110 This parameter can be a value of @ref FMC_AsynchronousWait */
111
112 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
113 This parameter can be a value of @ref FMC_Write_Burst */
114
115 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
116 This parameter is only enabled through the FMC_BCR1 register, and don't care
117 through FMC_BCR2..4 registers.
118 This parameter can be a value of @ref FMC_Continous_Clock */
119
120 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
121 This parameter is only enabled through the FMC_BCR1 register, and don't care
122 through FMC_BCR2..4 registers.
123 This parameter can be a value of @ref FMC_Write_FIFO
124 This mode is available only for the STM32F446/469/479xx devices */
125
126 uint32_t PageSize; /*!< Specifies the memory page size.
127 This parameter can be a value of @ref FMC_Page_Size */
128 }FMC_NORSRAM_InitTypeDef;
129
130 /**
131 * @brief FMC NORSRAM Timing parameters structure definition
132 */
133 typedef struct
134 {
135 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
136 the duration of the address setup time.
137 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
138 @note This parameter is not used with synchronous NOR Flash memories. */
139
140 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
141 the duration of the address hold time.
142 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
143 @note This parameter is not used with synchronous NOR Flash memories. */
144
145 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
146 the duration of the data setup time.
147 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
148 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
149 NOR Flash memories. */
150
151 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
152 the duration of the bus turnaround.
153 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
154 @note This parameter is only used for multiplexed NOR Flash memories. */
155
156 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
157 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
158 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
159 accesses. */
160
161 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
162 to the memory before getting the first data.
163 The parameter value depends on the memory type as shown below:
164 - It must be set to 0 in case of a CRAM
165 - It is don't care in asynchronous NOR, SRAM or ROM accesses
166 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
167 with synchronous burst mode enable */
168
169 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
170 This parameter can be a value of @ref FMC_Access_Mode */
171 }FMC_NORSRAM_TimingTypeDef;
172
173 /**
174 * @brief FMC NAND Configuration Structure definition
175 */
176 typedef struct
177 {
178 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
179 This parameter can be a value of @ref FMC_NAND_Bank */
180
181 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
182 This parameter can be any value of @ref FMC_Wait_feature */
183
184 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
185 This parameter can be any value of @ref FMC_NAND_Data_Width */
186
187 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
188 This parameter can be any value of @ref FMC_ECC */
189
190 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
191 This parameter can be any value of @ref FMC_ECC_Page_Size */
192
193 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
194 delay between CLE low and RE low.
195 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
196
197 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
198 delay between ALE low and RE low.
199 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
200 }FMC_NAND_InitTypeDef;
201
202 /**
203 * @brief FMC NAND/PCCARD Timing parameters structure definition
204 */
205 typedef struct
206 {
207 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
208 the command assertion for NAND-Flash read or write access
209 to common/Attribute or I/O memory space (depending on
210 the memory space timing to be configured).
211 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
212
213 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
214 command for NAND-Flash read or write access to
215 common/Attribute or I/O memory space (depending on the
216 memory space timing to be configured).
217 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
218
219 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
220 (and data for write access) after the command de-assertion
221 for NAND-Flash read or write access to common/Attribute
222 or I/O memory space (depending on the memory space timing
223 to be configured).
224 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
225
226 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
227 data bus is kept in HiZ after the start of a NAND-Flash
228 write access to common/Attribute or I/O memory space (depending
229 on the memory space timing to be configured).
230 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
231 }FMC_NAND_PCC_TimingTypeDef;
232
233 /**
234 * @brief FMC NAND Configuration Structure definition
235 */
236 typedef struct
237 {
238 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
239 This parameter can be any value of @ref FMC_Wait_feature */
240
241 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
242 delay between CLE low and RE low.
243 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
244
245 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
246 delay between ALE low and RE low.
247 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
248 }FMC_PCCARD_InitTypeDef;
249
250 /**
251 * @brief FMC SDRAM Configuration Structure definition
252 */
253 typedef struct
254 {
255 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
256 This parameter can be a value of @ref FMC_SDRAM_Bank */
257
258 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
259 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
260
261 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
262 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
263
264 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
265 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
266
267 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
268 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
269
270 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
271 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
272
273 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
274 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
275
276 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
277 to disable the clock before changing frequency.
278 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
279
280 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
281 commands during the CAS latency and stores data in the Read FIFO.
282 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
283
284 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
285 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
286 }FMC_SDRAM_InitTypeDef;
287
288 /**
289 * @brief FMC SDRAM Timing parameters structure definition
290 */
291 typedef struct
292 {
293 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
294 an active or Refresh command in number of memory clock cycles.
295 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
296
297 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
298 issuing the Activate command in number of memory clock cycles.
299 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
300
301 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
302 cycles.
303 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
304
305 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
306 and the delay between two consecutive Refresh commands in number of
307 memory clock cycles.
308 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
309
310 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
311 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
312
313 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
314 in number of memory clock cycles.
315 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
316
317 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
318 command in number of memory clock cycles.
319 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
320 }FMC_SDRAM_TimingTypeDef;
321
322 /**
323 * @brief SDRAM command parameters structure definition
324 */
325 typedef struct
326 {
327 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
328 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
329
330 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
331 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
332
333 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
334 in auto refresh mode.
335 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
336 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
337 }FMC_SDRAM_CommandTypeDef;
338 /**
339 * @}
340 */
341
342 /* Private constants ---------------------------------------------------------*/
343 /** @defgroup FMC_LL_Private_Constants FMC Private Constants
344 * @{
345 */
346
347 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
348 * @{
349 */
350 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
351 * @{
352 */
353 #define FMC_NORSRAM_BANK1 0x00000000U
354 #define FMC_NORSRAM_BANK2 0x00000002U
355 #define FMC_NORSRAM_BANK3 0x00000004U
356 #define FMC_NORSRAM_BANK4 0x00000006U
357 /**
358 * @}
359 */
360
361 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
362 * @{
363 */
364 #define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
365 #define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
366 /**
367 * @}
368 */
369
370 /** @defgroup FMC_Memory_Type FMC Memory Type
371 * @{
372 */
373 #define FMC_MEMORY_TYPE_SRAM 0x00000000U
374 #define FMC_MEMORY_TYPE_PSRAM 0x00000004U
375 #define FMC_MEMORY_TYPE_NOR 0x00000008U
376 /**
377 * @}
378 */
379
380 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
381 * @{
382 */
383 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
384 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
385 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
386 /**
387 * @}
388 */
389
390 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
391 * @{
392 */
393 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
394 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
395 /**
396 * @}
397 */
398
399 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
400 * @{
401 */
402 #define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
403 #define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
404 /**
405 * @}
406 */
407
408 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
409 * @{
410 */
411 #define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
412 #define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
413 /**
414 * @}
415 */
416
417 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
418 * @{
419 */
420 /** @note This mode is not available for the STM32F446/469/479xx devices
421 */
422 #define FMC_WRAP_MODE_DISABLE 0x00000000U
423 #define FMC_WRAP_MODE_ENABLE 0x00000400U
424 /**
425 * @}
426 */
427
428 /** @defgroup FMC_Wait_Timing FMC Wait Timing
429 * @{
430 */
431 #define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
432 #define FMC_WAIT_TIMING_DURING_WS 0x00000800U
433 /**
434 * @}
435 */
436
437 /** @defgroup FMC_Write_Operation FMC Write Operation
438 * @{
439 */
440 #define FMC_WRITE_OPERATION_DISABLE 0x00000000U
441 #define FMC_WRITE_OPERATION_ENABLE 0x00001000U
442 /**
443 * @}
444 */
445
446 /** @defgroup FMC_Wait_Signal FMC Wait Signal
447 * @{
448 */
449 #define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
450 #define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
451 /**
452 * @}
453 */
454
455 /** @defgroup FMC_Extended_Mode FMC Extended Mode
456 * @{
457 */
458 #define FMC_EXTENDED_MODE_DISABLE 0x00000000U
459 #define FMC_EXTENDED_MODE_ENABLE 0x00004000U
460 /**
461 * @}
462 */
463
464 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
465 * @{
466 */
467 #define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
468 #define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
469 /**
470 * @}
471 */
472
473 /** @defgroup FMC_Page_Size FMC Page Size
474 * @{
475 */
476 #define FMC_PAGE_SIZE_NONE 0x00000000U
477 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
478 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
479 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
480 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
481 /**
482 * @}
483 */
484
485 /** @defgroup FMC_Write_FIFO FMC Write FIFO
486 * @note These values are available only for the STM32F446/469/479xx devices.
487 * @{
488 */
489 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
490 #define FMC_WRITE_FIFO_ENABLE 0x00000000U
491 /**
492 * @}
493 */
494
495 /** @defgroup FMC_Write_Burst FMC Write Burst
496 * @{
497 */
498 #define FMC_WRITE_BURST_DISABLE 0x00000000U
499 #define FMC_WRITE_BURST_ENABLE 0x00080000U
500 /**
501 * @}
502 */
503
504 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
505 * @{
506 */
507 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
508 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
509 /**
510 * @}
511 */
512
513 /** @defgroup FMC_Access_Mode FMC Access Mode
514 * @{
515 */
516 #define FMC_ACCESS_MODE_A 0x00000000U
517 #define FMC_ACCESS_MODE_B 0x10000000U
518 #define FMC_ACCESS_MODE_C 0x20000000U
519 #define FMC_ACCESS_MODE_D 0x30000000U
520 /**
521 * @}
522 */
523
524 /**
525 * @}
526 */
527
528 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
529 * @{
530 */
531 /** @defgroup FMC_NAND_Bank FMC NAND Bank
532 * @{
533 */
534 #define FMC_NAND_BANK2 0x00000010U
535 #define FMC_NAND_BANK3 0x00000100U
536 /**
537 * @}
538 */
539
540 /** @defgroup FMC_Wait_feature FMC Wait feature
541 * @{
542 */
543 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
544 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
545 /**
546 * @}
547 */
548
549 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
550 * @{
551 */
552 #define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
553 #define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
554 /**
555 * @}
556 */
557
558 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
559 * @{
560 */
561 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
562 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
563 /**
564 * @}
565 */
566
567 /** @defgroup FMC_ECC FMC ECC
568 * @{
569 */
570 #define FMC_NAND_ECC_DISABLE 0x00000000U
571 #define FMC_NAND_ECC_ENABLE 0x00000040U
572 /**
573 * @}
574 */
575
576 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
577 * @{
578 */
579 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
580 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
581 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
582 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
583 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
584 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
585 /**
586 * @}
587 */
588
589 /**
590 * @}
591 */
592
593 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
594 * @{
595 */
596 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
597 * @{
598 */
599 #define FMC_SDRAM_BANK1 0x00000000U
600 #define FMC_SDRAM_BANK2 0x00000001U
601 /**
602 * @}
603 */
604
605 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
606 * @{
607 */
608 #define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
609 #define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
610 #define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
611 #define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
612 /**
613 * @}
614 */
615
616 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
617 * @{
618 */
619 #define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
620 #define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
621 #define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
622 /**
623 * @}
624 */
625
626 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
627 * @{
628 */
629 #define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
630 #define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
631 #define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
632 /**
633 * @}
634 */
635
636 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
637 * @{
638 */
639 #define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
640 #define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
641 /**
642 * @}
643 */
644
645 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
646 * @{
647 */
648 #define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
649 #define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
650 #define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
651 /**
652 * @}
653 */
654
655 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
656 * @{
657 */
658 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
659 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
660
661 /**
662 * @}
663 */
664
665 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
666 * @{
667 */
668 #define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
669 #define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
670 #define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
671 /**
672 * @}
673 */
674
675 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
676 * @{
677 */
678 #define FMC_SDRAM_RBURST_DISABLE 0x00000000U
679 #define FMC_SDRAM_RBURST_ENABLE 0x00001000U
680 /**
681 * @}
682 */
683
684 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
685 * @{
686 */
687 #define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
688 #define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
689 #define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
690 /**
691 * @}
692 */
693
694 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
695 * @{
696 */
697 #define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
698 #define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
699 #define FMC_SDRAM_CMD_PALL 0x00000002U
700 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
701 #define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
702 #define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
703 #define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
704 /**
705 * @}
706 */
707
708 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
709 * @{
710 */
711 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
712 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
713 #define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
714 /**
715 * @}
716 */
717
718 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
719 * @{
720 */
721 #define FMC_SDRAM_NORMAL_MODE 0x00000000U
722 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
723 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
724 /**
725 * @}
726 */
727
728 /**
729 * @}
730 */
731
732 /** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
733 * @{
734 */
735 #define FMC_IT_RISING_EDGE 0x00000008U
736 #define FMC_IT_LEVEL 0x00000010U
737 #define FMC_IT_FALLING_EDGE 0x00000020U
738 #define FMC_IT_REFRESH_ERROR 0x00004000U
739 /**
740 * @}
741 */
742
743 /** @defgroup FMC_LL_Flag_definition FMC Flag definition
744 * @{
745 */
746 #define FMC_FLAG_RISING_EDGE 0x00000001U
747 #define FMC_FLAG_LEVEL 0x00000002U
748 #define FMC_FLAG_FALLING_EDGE 0x00000004U
749 #define FMC_FLAG_FEMPT 0x00000040U
750 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
751 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
752 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
753 /**
754 * @}
755 */
756
757 /** @defgroup FMC_LL_Alias_definition FMC Alias definition
758 * @{
759 */
760 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
761 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
762 #else
763 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
764 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
765 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
766 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
767 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
768 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
769
770
771 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
772 #define FMC_NAND_DEVICE FMC_Bank3
773 #else
774 #define FMC_NAND_DEVICE FMC_Bank2_3
775 #define FMC_PCCARD_DEVICE FMC_Bank4
776 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
777 #define FMC_NORSRAM_DEVICE FMC_Bank1
778 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
779 #define FMC_SDRAM_DEVICE FMC_Bank5_6
780 /**
781 * @}
782 */
783
784 /**
785 * @}
786 */
787
788 /* Private macro -------------------------------------------------------------*/
789 /** @defgroup FMC_LL_Private_Macros FMC Private Macros
790 * @{
791 */
792
793 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
794 * @brief macros to handle NOR device enable/disable and read/write operations
795 * @{
796 */
797 /**
798 * @brief Enable the NORSRAM device access.
799 * @param __INSTANCE__ FMC_NORSRAM Instance
800 * @param __BANK__ FMC_NORSRAM Bank
801 * @retval None
802 */
803 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
804
805 /**
806 * @brief Disable the NORSRAM device access.
807 * @param __INSTANCE__ FMC_NORSRAM Instance
808 * @param __BANK__ FMC_NORSRAM Bank
809 * @retval None
810 */
811 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
812 /**
813 * @}
814 */
815
816 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
817 * @brief macros to handle NAND device enable/disable
818 * @{
819 */
820 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
821 /**
822 * @brief Enable the NAND device access.
823 * @param __INSTANCE__ FMC_NAND Instance
824 * @param __BANK__ FMC_NAND Bank
825 * @retval None
826 */
827 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
828
829 /**
830 * @brief Disable the NAND device access.
831 * @param __INSTANCE__ FMC_NAND Instance
832 * @param __BANK__ FMC_NAND Bank
833 * @retval None
834 */
835 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
836 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
837 /**
838 * @brief Enable the NAND device access.
839 * @param __INSTANCE__ FMC_NAND Instance
840 * @param __BANK__ FMC_NAND Bank
841 * @retval None
842 */
843 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
844 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
845
846 /**
847 * @brief Disable the NAND device access.
848 * @param __INSTANCE__ FMC_NAND Instance
849 * @param __BANK__ FMC_NAND Bank
850 * @retval None
851 */
852 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
853 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
854
855 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
856 /**
857 * @}
858 */
859 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
860 /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
861 * @brief macros to handle SRAM read/write operations
862 * @{
863 */
864 /**
865 * @brief Enable the PCCARD device access.
866 * @param __INSTANCE__ FMC_PCCARD Instance
867 * @retval None
868 */
869 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
870
871 /**
872 * @brief Disable the PCCARD device access.
873 * @param __INSTANCE__ FMC_PCCARD Instance
874 * @retval None
875 */
876 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
877 /**
878 * @}
879 */
880 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
881
882 /** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
883 * @brief macros to handle FMC flags and interrupts
884 * @{
885 */
886 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
887 /**
888 * @brief Enable the NAND device interrupt.
889 * @param __INSTANCE__ FMC_NAND instance
890 * @param __BANK__ FMC_NAND Bank
891 * @param __INTERRUPT__ FMC_NAND interrupt
892 * This parameter can be any combination of the following values:
893 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
894 * @arg FMC_IT_LEVEL: Interrupt level.
895 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
896 * @retval None
897 */
898 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
899
900 /**
901 * @brief Disable the NAND device interrupt.
902 * @param __INSTANCE__ FMC_NAND Instance
903 * @param __BANK__ FMC_NAND Bank
904 * @param __INTERRUPT__ FMC_NAND interrupt
905 * This parameter can be any combination of the following values:
906 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
907 * @arg FMC_IT_LEVEL: Interrupt level.
908 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
909 * @retval None
910 */
911 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
912
913 /**
914 * @brief Get flag status of the NAND device.
915 * @param __INSTANCE__ FMC_NAND Instance
916 * @param __BANK__ FMC_NAND Bank
917 * @param __FLAG__ FMC_NAND flag
918 * This parameter can be any combination of the following values:
919 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
920 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
921 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
922 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
923 * @retval The state of FLAG (SET or RESET).
924 */
925 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
926 /**
927 * @brief Clear flag status of the NAND device.
928 * @param __INSTANCE__ FMC_NAND Instance
929 * @param __BANK__ FMC_NAND Bank
930 * @param __FLAG__ FMC_NAND flag
931 * This parameter can be any combination of the following values:
932 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
933 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
934 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
935 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
936 * @retval None
937 */
938 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
939 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
940 /**
941 * @brief Enable the NAND device interrupt.
942 * @param __INSTANCE__ FMC_NAND instance
943 * @param __BANK__ FMC_NAND Bank
944 * @param __INTERRUPT__ FMC_NAND interrupt
945 * This parameter can be any combination of the following values:
946 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
947 * @arg FMC_IT_LEVEL: Interrupt level.
948 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
949 * @retval None
950 */
951 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
952 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
953
954 /**
955 * @brief Disable the NAND device interrupt.
956 * @param __INSTANCE__ FMC_NAND Instance
957 * @param __BANK__ FMC_NAND Bank
958 * @param __INTERRUPT__ FMC_NAND interrupt
959 * This parameter can be any combination of the following values:
960 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
961 * @arg FMC_IT_LEVEL: Interrupt level.
962 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
963 * @retval None
964 */
965 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
966 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
967
968 /**
969 * @brief Get flag status of the NAND device.
970 * @param __INSTANCE__ FMC_NAND Instance
971 * @param __BANK__ FMC_NAND Bank
972 * @param __FLAG__ FMC_NAND flag
973 * This parameter can be any combination of the following values:
974 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
975 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
976 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
977 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
978 * @retval The state of FLAG (SET or RESET).
979 */
980 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
981 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
982 /**
983 * @brief Clear flag status of the NAND device.
984 * @param __INSTANCE__ FMC_NAND Instance
985 * @param __BANK__ FMC_NAND Bank
986 * @param __FLAG__ FMC_NAND flag
987 * This parameter can be any combination of the following values:
988 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
989 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
990 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
991 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
992 * @retval None
993 */
994 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
995 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
996 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
997
998 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
999 /**
1000 * @brief Enable the PCCARD device interrupt.
1001 * @param __INSTANCE__ FMC_PCCARD instance
1002 * @param __INTERRUPT__ FMC_PCCARD interrupt
1003 * This parameter can be any combination of the following values:
1004 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1005 * @arg FMC_IT_LEVEL: Interrupt level.
1006 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1007 * @retval None
1008 */
1009 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
1010
1011 /**
1012 * @brief Disable the PCCARD device interrupt.
1013 * @param __INSTANCE__ FMC_PCCARD instance
1014 * @param __INTERRUPT__ FMC_PCCARD interrupt
1015 * This parameter can be any combination of the following values:
1016 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1017 * @arg FMC_IT_LEVEL: Interrupt level.
1018 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1019 * @retval None
1020 */
1021 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
1022
1023 /**
1024 * @brief Get flag status of the PCCARD device.
1025 * @param __INSTANCE__ FMC_PCCARD instance
1026 * @param __FLAG__ FMC_PCCARD flag
1027 * This parameter can be any combination of the following values:
1028 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1029 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1030 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1031 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1032 * @retval The state of FLAG (SET or RESET).
1033 */
1034 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
1035
1036 /**
1037 * @brief Clear flag status of the PCCARD device.
1038 * @param __INSTANCE__ FMC_PCCARD instance
1039 * @param __FLAG__ FMC_PCCARD flag
1040 * This parameter can be any combination of the following values:
1041 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1042 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1043 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1044 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1045 * @retval None
1046 */
1047 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
1048 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
1049
1050 /**
1051 * @brief Enable the SDRAM device interrupt.
1052 * @param __INSTANCE__ FMC_SDRAM instance
1053 * @param __INTERRUPT__ FMC_SDRAM interrupt
1054 * This parameter can be any combination of the following values:
1055 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1056 * @retval None
1057 */
1058 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1059
1060 /**
1061 * @brief Disable the SDRAM device interrupt.
1062 * @param __INSTANCE__ FMC_SDRAM instance
1063 * @param __INTERRUPT__ FMC_SDRAM interrupt
1064 * This parameter can be any combination of the following values:
1065 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1066 * @retval None
1067 */
1068 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1069
1070 /**
1071 * @brief Get flag status of the SDRAM device.
1072 * @param __INSTANCE__ FMC_SDRAM instance
1073 * @param __FLAG__ FMC_SDRAM flag
1074 * This parameter can be any combination of the following values:
1075 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
1076 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
1077 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
1078 * @retval The state of FLAG (SET or RESET).
1079 */
1080 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1081
1082 /**
1083 * @brief Clear flag status of the SDRAM device.
1084 * @param __INSTANCE__ FMC_SDRAM instance
1085 * @param __FLAG__ FMC_SDRAM flag
1086 * This parameter can be any combination of the following values:
1087 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
1088 * @retval None
1089 */
1090 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1091 /**
1092 * @}
1093 */
1094
1095 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
1096 * @{
1097 */
1098 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
1099 ((BANK) == FMC_NORSRAM_BANK2) || \
1100 ((BANK) == FMC_NORSRAM_BANK3) || \
1101 ((BANK) == FMC_NORSRAM_BANK4))
1102
1103 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
1104 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
1105
1106 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
1107 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
1108 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
1109
1110 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
1111 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
1112 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
1113
1114 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
1115 ((__MODE__) == FMC_ACCESS_MODE_B) || \
1116 ((__MODE__) == FMC_ACCESS_MODE_C) || \
1117 ((__MODE__) == FMC_ACCESS_MODE_D))
1118
1119 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
1120 ((BANK) == FMC_NAND_BANK3))
1121
1122 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
1123 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
1124
1125 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
1126 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
1127
1128 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
1129 ((STATE) == FMC_NAND_ECC_ENABLE))
1130
1131 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
1132 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
1133 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
1134 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
1135 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
1136 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
1137
1138 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
1139
1140 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
1141
1142 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
1143
1144 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
1145
1146 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
1147
1148 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
1149
1150 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
1151
1152 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
1153
1154 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
1155
1156 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
1157
1158 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
1159 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
1160
1161 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
1162 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
1163
1164 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1165 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
1166 ((__MODE__) == FMC_WRAP_MODE_ENABLE))
1167 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1168
1169 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
1170 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
1171
1172 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
1173 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
1174
1175 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
1176 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
1177
1178 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
1179 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
1180
1181 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
1182 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
1183
1184 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
1185 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
1186
1187 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
1188 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
1189
1190 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
1191
1192 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
1193
1194 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
1195
1196 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
1197
1198 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
1199
1200 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
1201
1202 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
1203 ((BANK) == FMC_SDRAM_BANK2))
1204
1205 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
1206 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
1207 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
1208 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
1209
1210 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
1211 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
1212 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
1213
1214 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
1215 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
1216 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
1217
1218 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
1219 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
1220
1221
1222 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
1223 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
1224 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
1225
1226 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
1227 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
1228 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
1229
1230 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
1231 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
1232
1233
1234 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
1235 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
1236 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
1237
1238 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1239
1240 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1241
1242 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
1243
1244 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1245
1246 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
1247
1248 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1249
1250 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1251
1252 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
1253 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
1254 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
1255 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
1256 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
1257 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
1258 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
1259
1260 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
1261 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
1262 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
1263
1264 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
1265
1266 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
1267
1268 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
1269
1270 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
1271
1272 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
1273 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
1274
1275 #define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
1276 ((SIZE) == FMC_PAGE_SIZE_128) || \
1277 ((SIZE) == FMC_PAGE_SIZE_256) || \
1278 ((SIZE) == FMC_PAGE_SIZE_512) || \
1279 ((SIZE) == FMC_PAGE_SIZE_1024))
1280
1281 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
1282 #define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
1283 ((FIFO) == FMC_WRITE_FIFO_ENABLE))
1284 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
1285
1286 /**
1287 * @}
1288 */
1289
1290 /**
1291 * @}
1292 */
1293
1294 /* Private functions ---------------------------------------------------------*/
1295 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
1296 * @{
1297 */
1298
1299 /** @defgroup FMC_LL_NORSRAM NOR SRAM
1300 * @{
1301 */
1302 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
1303 * @{
1304 */
1305 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
1306 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1307 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
1308 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1309 /**
1310 * @}
1311 */
1312
1313 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
1314 * @{
1315 */
1316 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1317 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1318 /**
1319 * @}
1320 */
1321 /**
1322 * @}
1323 */
1324
1325 /** @defgroup FMC_LL_NAND NAND
1326 * @{
1327 */
1328 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
1329 * @{
1330 */
1331 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1332 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1333 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1334 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1335 /**
1336 * @}
1337 */
1338
1339 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
1340 * @{
1341 */
1342 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1343 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1344 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1345
1346 /**
1347 * @}
1348 */
1349 /**
1350 * @}
1351 */
1352 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1353 /** @defgroup FMC_LL_PCCARD PCCARD
1354 * @{
1355 */
1356 /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
1357 * @{
1358 */
1359 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
1360 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1361 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1362 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1363 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1364 /**
1365 * @}
1366 */
1367 /**
1368 * @}
1369 */
1370 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1371
1372 /** @defgroup FMC_LL_SDRAM SDRAM
1373 * @{
1374 */
1375 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
1376 * @{
1377 */
1378 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1379 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1380 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1381 /**
1382 * @}
1383 */
1384
1385 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
1386 * @{
1387 */
1388 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1389 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1390 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1391 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1392 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1393 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1394 /**
1395 * @}
1396 */
1397 /**
1398 * @}
1399 */
1400
1401 /**
1402 * @}
1403 */
1404
1405 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
1406 /**
1407 * @}
1408 */
1409
1410 /**
1411 * @}
1412 */
1413 #ifdef __cplusplus
1414 }
1415 #endif
1416
1417 #endif /* __STM32F4xx_LL_FMC_H */
1418
1419 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/