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Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_dma2d.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of DMA2D LL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_LL_DMA2D_H | |
38 #define __STM32F4xx_LL_DMA2D_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 /* Includes ------------------------------------------------------------------*/ | |
45 #include "stm32f4xx.h" | |
46 | |
47 /** @addtogroup STM32F4xx_LL_Driver | |
48 * @{ | |
49 */ | |
50 | |
51 #if defined (DMA2D) | |
52 | |
53 /** @defgroup DMA2D_LL DMA2D | |
54 * @{ | |
55 */ | |
56 | |
57 /* Private types -------------------------------------------------------------*/ | |
58 /* Private variables ---------------------------------------------------------*/ | |
59 /* Private constants ---------------------------------------------------------*/ | |
60 /* Private macros ------------------------------------------------------------*/ | |
61 #if defined(USE_FULL_LL_DRIVER) | |
62 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros | |
63 * @{ | |
64 */ | |
65 | |
66 /** | |
67 * @} | |
68 */ | |
69 #endif /*USE_FULL_LL_DRIVER*/ | |
70 | |
71 /* Exported types ------------------------------------------------------------*/ | |
72 #if defined(USE_FULL_LL_DRIVER) | |
73 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures | |
74 * @{ | |
75 */ | |
76 | |
77 /** | |
78 * @brief LL DMA2D Init Structure Definition | |
79 */ | |
80 typedef struct | |
81 { | |
82 uint32_t Mode; /*!< Specifies the DMA2D transfer mode. | |
83 - This parameter can be one value of @ref DMA2D_LL_EC_MODE. | |
84 | |
85 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/ | |
86 | |
87 uint32_t ColorMode; /*!< Specifies the color format of the output image. | |
88 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. | |
89 | |
90 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */ | |
91 | |
92 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. | |
93 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. | |
94 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. | |
95 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. | |
96 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. | |
97 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. | |
98 | |
99 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration | |
100 function @ref LL_DMA2D_ConfigOutputColor(). */ | |
101 | |
102 uint32_t OutputGreen; /*!< Specifies the Green value of the output image. | |
103 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. | |
104 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. | |
105 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. | |
106 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. | |
107 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. | |
108 | |
109 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration | |
110 function @ref LL_DMA2D_ConfigOutputColor(). */ | |
111 | |
112 uint32_t OutputRed; /*!< Specifies the Red value of the output image. | |
113 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. | |
114 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. | |
115 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. | |
116 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. | |
117 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. | |
118 | |
119 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration | |
120 function @ref LL_DMA2D_ConfigOutputColor(). */ | |
121 | |
122 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. | |
123 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. | |
124 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. | |
125 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. | |
126 - This parameter is not considered if RGB888 or RGB565 color mode is selected. | |
127 | |
128 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration | |
129 function @ref LL_DMA2D_ConfigOutputColor(). */ | |
130 | |
131 uint32_t OutputMemoryAddress; /*!< Specifies the memory address. | |
132 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. | |
133 | |
134 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ | |
135 | |
136 uint32_t LineOffset; /*!< Specifies the output line offset value. | |
137 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. | |
138 | |
139 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */ | |
140 | |
141 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred. | |
142 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. | |
143 | |
144 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ | |
145 | |
146 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered. | |
147 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. | |
148 | |
149 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ | |
150 | |
151 } LL_DMA2D_InitTypeDef; | |
152 | |
153 /** | |
154 * @brief LL DMA2D Layer Configuration Structure Definition | |
155 */ | |
156 typedef struct | |
157 { | |
158 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address. | |
159 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. | |
160 | |
161 This parameter can be modified afterwards using unitary functions | |
162 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer, | |
163 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */ | |
164 | |
165 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value. | |
166 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. | |
167 | |
168 This parameter can be modified afterwards using unitary functions | |
169 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer, | |
170 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */ | |
171 | |
172 uint32_t ColorMode; /*!< Specifies the foreground or background color mode. | |
173 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE. | |
174 | |
175 This parameter can be modified afterwards using unitary functions | |
176 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer, | |
177 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */ | |
178 | |
179 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode. | |
180 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE. | |
181 | |
182 This parameter can be modified afterwards using unitary functions | |
183 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer, | |
184 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */ | |
185 | |
186 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size. | |
187 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. | |
188 | |
189 This parameter can be modified afterwards using unitary functions | |
190 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer, | |
191 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */ | |
192 | |
193 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode. | |
194 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE. | |
195 | |
196 This parameter can be modified afterwards using unitary functions | |
197 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer, | |
198 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */ | |
199 | |
200 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value. | |
201 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. | |
202 | |
203 This parameter can be modified afterwards using unitary functions | |
204 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer, | |
205 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */ | |
206 | |
207 uint32_t Blue; /*!< Specifies the foreground or background Blue color value. | |
208 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. | |
209 | |
210 This parameter can be modified afterwards using unitary functions | |
211 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer, | |
212 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */ | |
213 | |
214 uint32_t Green; /*!< Specifies the foreground or background Green color value. | |
215 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. | |
216 | |
217 This parameter can be modified afterwards using unitary functions | |
218 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer, | |
219 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */ | |
220 | |
221 uint32_t Red; /*!< Specifies the foreground or background Red color value. | |
222 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. | |
223 | |
224 This parameter can be modified afterwards using unitary functions | |
225 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer, | |
226 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */ | |
227 | |
228 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address. | |
229 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. | |
230 | |
231 This parameter can be modified afterwards using unitary functions | |
232 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer, | |
233 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */ | |
234 | |
235 } LL_DMA2D_LayerCfgTypeDef; | |
236 | |
237 /** | |
238 * @brief LL DMA2D Output Color Structure Definition | |
239 */ | |
240 typedef struct | |
241 { | |
242 uint32_t ColorMode; /*!< Specifies the color format of the output image. | |
243 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. | |
244 | |
245 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */ | |
246 | |
247 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. | |
248 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. | |
249 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. | |
250 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. | |
251 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. | |
252 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. | |
253 | |
254 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration | |
255 function @ref LL_DMA2D_ConfigOutputColor(). */ | |
256 | |
257 uint32_t OutputGreen; /*!< Specifies the Green value of the output image. | |
258 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. | |
259 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. | |
260 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. | |
261 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. | |
262 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. | |
263 | |
264 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration | |
265 function @ref LL_DMA2D_ConfigOutputColor(). */ | |
266 | |
267 uint32_t OutputRed; /*!< Specifies the Red value of the output image. | |
268 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. | |
269 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. | |
270 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. | |
271 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. | |
272 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. | |
273 | |
274 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration | |
275 function @ref LL_DMA2D_ConfigOutputColor(). */ | |
276 | |
277 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. | |
278 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. | |
279 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. | |
280 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. | |
281 - This parameter is not considered if RGB888 or RGB565 color mode is selected. | |
282 | |
283 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration | |
284 function @ref LL_DMA2D_ConfigOutputColor(). */ | |
285 | |
286 } LL_DMA2D_ColorTypeDef; | |
287 | |
288 /** | |
289 * @} | |
290 */ | |
291 #endif /* USE_FULL_LL_DRIVER */ | |
292 | |
293 /* Exported constants --------------------------------------------------------*/ | |
294 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants | |
295 * @{ | |
296 */ | |
297 | |
298 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines | |
299 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function | |
300 * @{ | |
301 */ | |
302 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ | |
303 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ | |
304 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ | |
305 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ | |
306 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ | |
307 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ | |
308 /** | |
309 * @} | |
310 */ | |
311 | |
312 /** @defgroup DMA2D_LL_EC_IT IT Defines | |
313 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions | |
314 * @{ | |
315 */ | |
316 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ | |
317 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ | |
318 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ | |
319 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ | |
320 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ | |
321 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ | |
322 /** | |
323 * @} | |
324 */ | |
325 | |
326 /** @defgroup DMA2D_LL_EC_MODE Mode | |
327 * @{ | |
328 */ | |
329 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ | |
330 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ | |
331 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ | |
332 #define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ | |
333 /** | |
334 * @} | |
335 */ | |
336 | |
337 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode | |
338 * @{ | |
339 */ | |
340 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ | |
341 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */ | |
342 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */ | |
343 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */ | |
344 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */ | |
345 /** | |
346 * @} | |
347 */ | |
348 | |
349 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode | |
350 * @{ | |
351 */ | |
352 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ | |
353 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */ | |
354 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */ | |
355 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */ | |
356 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */ | |
357 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */ | |
358 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */ | |
359 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */ | |
360 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */ | |
361 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */ | |
362 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */ | |
363 /** | |
364 * @} | |
365 */ | |
366 | |
367 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode | |
368 * @{ | |
369 */ | |
370 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */ | |
371 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */ | |
372 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value | |
373 with original alpha channel value */ | |
374 /** | |
375 * @} | |
376 */ | |
377 | |
378 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode | |
379 * @{ | |
380 */ | |
381 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ | |
382 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */ | |
383 /** | |
384 * @} | |
385 */ | |
386 | |
387 /** | |
388 * @} | |
389 */ | |
390 | |
391 /* Exported macro ------------------------------------------------------------*/ | |
392 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros | |
393 * @{ | |
394 */ | |
395 | |
396 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros | |
397 * @{ | |
398 */ | |
399 | |
400 /** | |
401 * @brief Write a value in DMA2D register. | |
402 * @param __INSTANCE__ DMA2D Instance | |
403 * @param __REG__ Register to be written | |
404 * @param __VALUE__ Value to be written in the register | |
405 * @retval None | |
406 */ | |
407 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) | |
408 | |
409 /** | |
410 * @brief Read a value in DMA2D register. | |
411 * @param __INSTANCE__ DMA2D Instance | |
412 * @param __REG__ Register to be read | |
413 * @retval Register value | |
414 */ | |
415 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) | |
416 /** | |
417 * @} | |
418 */ | |
419 | |
420 /** | |
421 * @} | |
422 */ | |
423 | |
424 /* Exported functions --------------------------------------------------------*/ | |
425 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions | |
426 * @{ | |
427 */ | |
428 | |
429 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions | |
430 * @{ | |
431 */ | |
432 | |
433 /** | |
434 * @brief Start a DMA2D transfer. | |
435 * @rmtoll CR START LL_DMA2D_Start | |
436 * @param DMA2Dx DMA2D Instance | |
437 * @retval None | |
438 */ | |
439 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) | |
440 { | |
441 SET_BIT(DMA2Dx->CR, DMA2D_CR_START); | |
442 } | |
443 | |
444 /** | |
445 * @brief Indicate if a DMA2D transfer is ongoing. | |
446 * @rmtoll CR START LL_DMA2D_IsTransferOngoing | |
447 * @param DMA2Dx DMA2D Instance | |
448 * @retval State of bit (1 or 0). | |
449 */ | |
450 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) | |
451 { | |
452 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)); | |
453 } | |
454 | |
455 /** | |
456 * @brief Suspend DMA2D transfer. | |
457 * @note This API can be used to suspend automatic foreground or background CLUT loading. | |
458 * @rmtoll CR SUSP LL_DMA2D_Suspend | |
459 * @param DMA2Dx DMA2D Instance | |
460 * @retval None | |
461 */ | |
462 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx) | |
463 { | |
464 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); | |
465 } | |
466 | |
467 /** | |
468 * @brief Resume DMA2D transfer. | |
469 * @note This API can be used to resume automatic foreground or background CLUT loading. | |
470 * @rmtoll CR SUSP LL_DMA2D_Resume | |
471 * @param DMA2Dx DMA2D Instance | |
472 * @retval None | |
473 */ | |
474 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) | |
475 { | |
476 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START); | |
477 } | |
478 | |
479 /** | |
480 * @brief Indicate if DMA2D transfer is suspended. | |
481 * @note This API can be used to indicate whether or not automatic foreground or | |
482 * background CLUT loading is suspended. | |
483 * @rmtoll CR SUSP LL_DMA2D_IsSuspended | |
484 * @param DMA2Dx DMA2D Instance | |
485 * @retval State of bit (1 or 0). | |
486 */ | |
487 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) | |
488 { | |
489 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)); | |
490 } | |
491 | |
492 /** | |
493 * @brief Abort DMA2D transfer. | |
494 * @note This API can be used to abort automatic foreground or background CLUT loading. | |
495 * @rmtoll CR ABORT LL_DMA2D_Abort | |
496 * @param DMA2Dx DMA2D Instance | |
497 * @retval None | |
498 */ | |
499 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) | |
500 { | |
501 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); | |
502 } | |
503 | |
504 /** | |
505 * @brief Indicate if DMA2D transfer is aborted. | |
506 * @note This API can be used to indicate whether or not automatic foreground or | |
507 * background CLUT loading is aborted. | |
508 * @rmtoll CR ABORT LL_DMA2D_IsAborted | |
509 * @param DMA2Dx DMA2D Instance | |
510 * @retval State of bit (1 or 0). | |
511 */ | |
512 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) | |
513 { | |
514 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)); | |
515 } | |
516 | |
517 /** | |
518 * @brief Set DMA2D mode. | |
519 * @rmtoll CR MODE LL_DMA2D_SetMode | |
520 * @param DMA2Dx DMA2D Instance | |
521 * @param Mode This parameter can be one of the following values: | |
522 * @arg @ref LL_DMA2D_MODE_M2M | |
523 * @arg @ref LL_DMA2D_MODE_M2M_PFC | |
524 * @arg @ref LL_DMA2D_MODE_M2M_BLEND | |
525 * @arg @ref LL_DMA2D_MODE_R2M | |
526 * @retval None | |
527 */ | |
528 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) | |
529 { | |
530 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode); | |
531 } | |
532 | |
533 /** | |
534 * @brief Return DMA2D mode | |
535 * @rmtoll CR MODE LL_DMA2D_GetMode | |
536 * @param DMA2Dx DMA2D Instance | |
537 * @retval Returned value can be one of the following values: | |
538 * @arg @ref LL_DMA2D_MODE_M2M | |
539 * @arg @ref LL_DMA2D_MODE_M2M_PFC | |
540 * @arg @ref LL_DMA2D_MODE_M2M_BLEND | |
541 * @arg @ref LL_DMA2D_MODE_R2M | |
542 */ | |
543 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) | |
544 { | |
545 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); | |
546 } | |
547 | |
548 /** | |
549 * @brief Set DMA2D output color mode. | |
550 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode | |
551 * @param DMA2Dx DMA2D Instance | |
552 * @param ColorMode This parameter can be one of the following values: | |
553 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 | |
554 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 | |
555 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 | |
556 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 | |
557 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 | |
558 * @retval None | |
559 */ | |
560 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) | |
561 { | |
562 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode); | |
563 } | |
564 | |
565 /** | |
566 * @brief Return DMA2D output color mode. | |
567 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode | |
568 * @param DMA2Dx DMA2D Instance | |
569 * @retval Returned value can be one of the following values: | |
570 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 | |
571 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 | |
572 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 | |
573 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 | |
574 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 | |
575 */ | |
576 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) | |
577 { | |
578 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); | |
579 } | |
580 | |
581 /** | |
582 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits). | |
583 * @rmtoll OOR LO LL_DMA2D_SetLineOffset | |
584 * @param DMA2Dx DMA2D Instance | |
585 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF | |
586 * @retval None | |
587 */ | |
588 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) | |
589 { | |
590 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset); | |
591 } | |
592 | |
593 /** | |
594 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits). | |
595 * @rmtoll OOR LO LL_DMA2D_GetLineOffset | |
596 * @param DMA2Dx DMA2D Instance | |
597 * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF | |
598 */ | |
599 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) | |
600 { | |
601 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); | |
602 } | |
603 | |
604 /** | |
605 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits). | |
606 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines | |
607 * @param DMA2Dx DMA2D Instance | |
608 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF | |
609 * @retval None | |
610 */ | |
611 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines) | |
612 { | |
613 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos)); | |
614 } | |
615 | |
616 /** | |
617 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits) | |
618 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines | |
619 * @param DMA2Dx DMA2D Instance | |
620 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF | |
621 */ | |
622 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) | |
623 { | |
624 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); | |
625 } | |
626 | |
627 /** | |
628 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits). | |
629 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines | |
630 * @param DMA2Dx DMA2D Instance | |
631 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF | |
632 * @retval None | |
633 */ | |
634 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines) | |
635 { | |
636 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines); | |
637 } | |
638 | |
639 /** | |
640 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits). | |
641 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines | |
642 * @param DMA2Dx DMA2D Instance | |
643 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF | |
644 */ | |
645 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) | |
646 { | |
647 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); | |
648 } | |
649 | |
650 /** | |
651 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits). | |
652 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr | |
653 * @param DMA2Dx DMA2D Instance | |
654 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
655 * @retval None | |
656 */ | |
657 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress) | |
658 { | |
659 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress); | |
660 } | |
661 | |
662 /** | |
663 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits). | |
664 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr | |
665 * @param DMA2Dx DMA2D Instance | |
666 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
667 */ | |
668 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) | |
669 { | |
670 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); | |
671 } | |
672 | |
673 /** | |
674 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits). | |
675 * @note Output color format depends on output color mode, ARGB8888, RGB888, | |
676 * RGB565, ARGB1555 or ARGB4444. | |
677 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting | |
678 * with respect to color mode is not done by the user code. | |
679 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n | |
680 * OCOLR GREEN LL_DMA2D_SetOutputColor\n | |
681 * OCOLR RED LL_DMA2D_SetOutputColor\n | |
682 * OCOLR ALPHA LL_DMA2D_SetOutputColor | |
683 * @param DMA2Dx DMA2D Instance | |
684 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
685 * @retval None | |
686 */ | |
687 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) | |
688 { | |
689 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ | |
690 OutputColor); | |
691 } | |
692 | |
693 /** | |
694 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits). | |
695 * @note Alpha channel and red, green, blue color values must be retrieved from the returned | |
696 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444) | |
697 * as set by @ref LL_DMA2D_SetOutputColorMode. | |
698 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n | |
699 * OCOLR GREEN LL_DMA2D_GetOutputColor\n | |
700 * OCOLR RED LL_DMA2D_GetOutputColor\n | |
701 * OCOLR ALPHA LL_DMA2D_GetOutputColor | |
702 * @param DMA2Dx DMA2D Instance | |
703 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
704 */ | |
705 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) | |
706 { | |
707 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ | |
708 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); | |
709 } | |
710 | |
711 /** | |
712 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits). | |
713 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark | |
714 * @param DMA2Dx DMA2D Instance | |
715 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF | |
716 * @retval None | |
717 */ | |
718 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark) | |
719 { | |
720 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark); | |
721 } | |
722 | |
723 /** | |
724 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits). | |
725 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark | |
726 * @param DMA2Dx DMA2D Instance | |
727 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF | |
728 */ | |
729 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) | |
730 { | |
731 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); | |
732 } | |
733 | |
734 /** | |
735 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits). | |
736 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime | |
737 * @param DMA2Dx DMA2D Instance | |
738 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF | |
739 * @retval None | |
740 */ | |
741 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime) | |
742 { | |
743 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos)); | |
744 } | |
745 | |
746 /** | |
747 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits). | |
748 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime | |
749 * @param DMA2Dx DMA2D Instance | |
750 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF | |
751 */ | |
752 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) | |
753 { | |
754 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); | |
755 } | |
756 | |
757 /** | |
758 * @brief Enable DMA2D dead time functionality. | |
759 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime | |
760 * @param DMA2Dx DMA2D Instance | |
761 * @retval None | |
762 */ | |
763 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx) | |
764 { | |
765 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); | |
766 } | |
767 | |
768 /** | |
769 * @brief Disable DMA2D dead time functionality. | |
770 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime | |
771 * @param DMA2Dx DMA2D Instance | |
772 * @retval None | |
773 */ | |
774 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) | |
775 { | |
776 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); | |
777 } | |
778 | |
779 /** | |
780 * @brief Indicate if DMA2D dead time functionality is enabled. | |
781 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime | |
782 * @param DMA2Dx DMA2D Instance | |
783 * @retval State of bit (1 or 0). | |
784 */ | |
785 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) | |
786 { | |
787 return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)); | |
788 } | |
789 | |
790 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions | |
791 * @{ | |
792 */ | |
793 | |
794 /** | |
795 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). | |
796 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr | |
797 * @param DMA2Dx DMA2D Instance | |
798 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
799 * @retval None | |
800 */ | |
801 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) | |
802 { | |
803 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress); | |
804 } | |
805 | |
806 /** | |
807 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). | |
808 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr | |
809 * @param DMA2Dx DMA2D Instance | |
810 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
811 */ | |
812 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) | |
813 { | |
814 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); | |
815 } | |
816 | |
817 /** | |
818 * @brief Enable DMA2D foreground CLUT loading. | |
819 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad | |
820 * @param DMA2Dx DMA2D Instance | |
821 * @retval None | |
822 */ | |
823 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) | |
824 { | |
825 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START); | |
826 } | |
827 | |
828 /** | |
829 * @brief Indicate if DMA2D foreground CLUT loading is enabled. | |
830 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad | |
831 * @param DMA2Dx DMA2D Instance | |
832 * @retval State of bit (1 or 0). | |
833 */ | |
834 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) | |
835 { | |
836 return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)); | |
837 } | |
838 | |
839 /** | |
840 * @brief Set DMA2D foreground color mode. | |
841 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode | |
842 * @param DMA2Dx DMA2D Instance | |
843 * @param ColorMode This parameter can be one of the following values: | |
844 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 | |
845 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 | |
846 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 | |
847 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 | |
848 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 | |
849 * @arg @ref LL_DMA2D_INPUT_MODE_L8 | |
850 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 | |
851 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 | |
852 * @arg @ref LL_DMA2D_INPUT_MODE_L4 | |
853 * @arg @ref LL_DMA2D_INPUT_MODE_A8 | |
854 * @arg @ref LL_DMA2D_INPUT_MODE_A4 | |
855 * @retval None | |
856 */ | |
857 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) | |
858 { | |
859 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode); | |
860 } | |
861 | |
862 /** | |
863 * @brief Return DMA2D foreground color mode. | |
864 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode | |
865 * @param DMA2Dx DMA2D Instance | |
866 * @retval Returned value can be one of the following values: | |
867 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 | |
868 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 | |
869 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 | |
870 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 | |
871 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 | |
872 * @arg @ref LL_DMA2D_INPUT_MODE_L8 | |
873 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 | |
874 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 | |
875 * @arg @ref LL_DMA2D_INPUT_MODE_L4 | |
876 * @arg @ref LL_DMA2D_INPUT_MODE_A8 | |
877 * @arg @ref LL_DMA2D_INPUT_MODE_A4 | |
878 */ | |
879 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) | |
880 { | |
881 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); | |
882 } | |
883 | |
884 /** | |
885 * @brief Set DMA2D foreground alpha mode. | |
886 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode | |
887 * @param DMA2Dx DMA2D Instance | |
888 * @param AphaMode This parameter can be one of the following values: | |
889 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF | |
890 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE | |
891 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE | |
892 * @retval None | |
893 */ | |
894 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) | |
895 { | |
896 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode); | |
897 } | |
898 | |
899 /** | |
900 * @brief Return DMA2D foreground alpha mode. | |
901 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode | |
902 * @param DMA2Dx DMA2D Instance | |
903 * @retval Returned value can be one of the following values: | |
904 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF | |
905 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE | |
906 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE | |
907 */ | |
908 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) | |
909 { | |
910 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); | |
911 } | |
912 | |
913 /** | |
914 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). | |
915 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha | |
916 * @param DMA2Dx DMA2D Instance | |
917 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF | |
918 * @retval None | |
919 */ | |
920 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) | |
921 { | |
922 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos)); | |
923 } | |
924 | |
925 /** | |
926 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). | |
927 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha | |
928 * @param DMA2Dx DMA2D Instance | |
929 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF | |
930 */ | |
931 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) | |
932 { | |
933 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); | |
934 } | |
935 | |
936 /** | |
937 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). | |
938 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset | |
939 * @param DMA2Dx DMA2D Instance | |
940 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF | |
941 * @retval None | |
942 */ | |
943 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) | |
944 { | |
945 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset); | |
946 } | |
947 | |
948 /** | |
949 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). | |
950 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset | |
951 * @param DMA2Dx DMA2D Instance | |
952 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF | |
953 */ | |
954 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) | |
955 { | |
956 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); | |
957 } | |
958 | |
959 /** | |
960 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits). | |
961 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor | |
962 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor | |
963 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor | |
964 * @param DMA2Dx DMA2D Instance | |
965 * @param Red Value between Min_Data=0 and Max_Data=0xFF | |
966 * @param Green Value between Min_Data=0 and Max_Data=0xFF | |
967 * @param Blue Value between Min_Data=0 and Max_Data=0xFF | |
968 * @retval None | |
969 */ | |
970 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) | |
971 { | |
972 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \ | |
973 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue)); | |
974 } | |
975 | |
976 /** | |
977 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). | |
978 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor | |
979 * @param DMA2Dx DMA2D Instance | |
980 * @param Red Value between Min_Data=0 and Max_Data=0xFF | |
981 * @retval None | |
982 */ | |
983 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) | |
984 { | |
985 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos)); | |
986 } | |
987 | |
988 /** | |
989 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). | |
990 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor | |
991 * @param DMA2Dx DMA2D Instance | |
992 * @retval Red color value between Min_Data=0 and Max_Data=0xFF | |
993 */ | |
994 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) | |
995 { | |
996 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); | |
997 } | |
998 | |
999 /** | |
1000 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). | |
1001 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor | |
1002 * @param DMA2Dx DMA2D Instance | |
1003 * @param Green Value between Min_Data=0 and Max_Data=0xFF | |
1004 * @retval None | |
1005 */ | |
1006 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) | |
1007 { | |
1008 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos)); | |
1009 } | |
1010 | |
1011 /** | |
1012 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). | |
1013 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor | |
1014 * @param DMA2Dx DMA2D Instance | |
1015 * @retval Green color value between Min_Data=0 and Max_Data=0xFF | |
1016 */ | |
1017 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) | |
1018 { | |
1019 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); | |
1020 } | |
1021 | |
1022 /** | |
1023 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). | |
1024 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor | |
1025 * @param DMA2Dx DMA2D Instance | |
1026 * @param Blue Value between Min_Data=0 and Max_Data=0xFF | |
1027 * @retval None | |
1028 */ | |
1029 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) | |
1030 { | |
1031 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue); | |
1032 } | |
1033 | |
1034 /** | |
1035 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). | |
1036 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor | |
1037 * @param DMA2Dx DMA2D Instance | |
1038 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF | |
1039 */ | |
1040 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) | |
1041 { | |
1042 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); | |
1043 } | |
1044 | |
1045 /** | |
1046 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). | |
1047 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr | |
1048 * @param DMA2Dx DMA2D Instance | |
1049 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
1050 * @retval None | |
1051 */ | |
1052 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) | |
1053 { | |
1054 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress); | |
1055 } | |
1056 | |
1057 /** | |
1058 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). | |
1059 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr | |
1060 * @param DMA2Dx DMA2D Instance | |
1061 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
1062 */ | |
1063 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) | |
1064 { | |
1065 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); | |
1066 } | |
1067 | |
1068 /** | |
1069 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). | |
1070 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize | |
1071 * @param DMA2Dx DMA2D Instance | |
1072 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF | |
1073 * @retval None | |
1074 */ | |
1075 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) | |
1076 { | |
1077 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos)); | |
1078 } | |
1079 | |
1080 /** | |
1081 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). | |
1082 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize | |
1083 * @param DMA2Dx DMA2D Instance | |
1084 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF | |
1085 */ | |
1086 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) | |
1087 { | |
1088 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); | |
1089 } | |
1090 | |
1091 /** | |
1092 * @brief Set DMA2D foreground CLUT color mode. | |
1093 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode | |
1094 * @param DMA2Dx DMA2D Instance | |
1095 * @param CLUTColorMode This parameter can be one of the following values: | |
1096 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 | |
1097 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 | |
1098 * @retval None | |
1099 */ | |
1100 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) | |
1101 { | |
1102 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode); | |
1103 } | |
1104 | |
1105 /** | |
1106 * @brief Return DMA2D foreground CLUT color mode. | |
1107 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode | |
1108 * @param DMA2Dx DMA2D Instance | |
1109 * @retval Returned value can be one of the following values: | |
1110 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 | |
1111 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 | |
1112 */ | |
1113 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) | |
1114 { | |
1115 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); | |
1116 } | |
1117 | |
1118 /** | |
1119 * @} | |
1120 */ | |
1121 | |
1122 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions | |
1123 * @{ | |
1124 */ | |
1125 | |
1126 /** | |
1127 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits). | |
1128 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr | |
1129 * @param DMA2Dx DMA2D Instance | |
1130 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
1131 * @retval None | |
1132 */ | |
1133 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) | |
1134 { | |
1135 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress); | |
1136 } | |
1137 | |
1138 /** | |
1139 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits). | |
1140 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr | |
1141 * @param DMA2Dx DMA2D Instance | |
1142 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
1143 */ | |
1144 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) | |
1145 { | |
1146 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); | |
1147 } | |
1148 | |
1149 /** | |
1150 * @brief Enable DMA2D background CLUT loading. | |
1151 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad | |
1152 * @param DMA2Dx DMA2D Instance | |
1153 * @retval None | |
1154 */ | |
1155 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) | |
1156 { | |
1157 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START); | |
1158 } | |
1159 | |
1160 /** | |
1161 * @brief Indicate if DMA2D background CLUT loading is enabled. | |
1162 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad | |
1163 * @param DMA2Dx DMA2D Instance | |
1164 * @retval State of bit (1 or 0). | |
1165 */ | |
1166 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) | |
1167 { | |
1168 return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)); | |
1169 } | |
1170 | |
1171 /** | |
1172 * @brief Set DMA2D background color mode. | |
1173 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode | |
1174 * @param DMA2Dx DMA2D Instance | |
1175 * @param ColorMode This parameter can be one of the following values: | |
1176 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 | |
1177 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 | |
1178 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 | |
1179 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 | |
1180 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 | |
1181 * @arg @ref LL_DMA2D_INPUT_MODE_L8 | |
1182 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 | |
1183 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 | |
1184 * @arg @ref LL_DMA2D_INPUT_MODE_L4 | |
1185 * @arg @ref LL_DMA2D_INPUT_MODE_A8 | |
1186 * @arg @ref LL_DMA2D_INPUT_MODE_A4 | |
1187 * @retval None | |
1188 */ | |
1189 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) | |
1190 { | |
1191 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode); | |
1192 } | |
1193 | |
1194 /** | |
1195 * @brief Return DMA2D background color mode. | |
1196 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode | |
1197 * @param DMA2Dx DMA2D Instance | |
1198 * @retval Returned value can be one of the following values: | |
1199 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 | |
1200 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 | |
1201 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 | |
1202 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 | |
1203 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 | |
1204 * @arg @ref LL_DMA2D_INPUT_MODE_L8 | |
1205 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 | |
1206 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 | |
1207 * @arg @ref LL_DMA2D_INPUT_MODE_L4 | |
1208 * @arg @ref LL_DMA2D_INPUT_MODE_A8 | |
1209 * @arg @ref LL_DMA2D_INPUT_MODE_A4 | |
1210 */ | |
1211 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) | |
1212 { | |
1213 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); | |
1214 } | |
1215 | |
1216 /** | |
1217 * @brief Set DMA2D background alpha mode. | |
1218 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode | |
1219 * @param DMA2Dx DMA2D Instance | |
1220 * @param AphaMode This parameter can be one of the following values: | |
1221 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF | |
1222 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE | |
1223 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE | |
1224 * @retval None | |
1225 */ | |
1226 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) | |
1227 { | |
1228 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode); | |
1229 } | |
1230 | |
1231 /** | |
1232 * @brief Return DMA2D background alpha mode. | |
1233 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode | |
1234 * @param DMA2Dx DMA2D Instance | |
1235 * @retval Returned value can be one of the following values: | |
1236 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF | |
1237 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE | |
1238 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE | |
1239 */ | |
1240 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) | |
1241 { | |
1242 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); | |
1243 } | |
1244 | |
1245 /** | |
1246 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits). | |
1247 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha | |
1248 * @param DMA2Dx DMA2D Instance | |
1249 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF | |
1250 * @retval None | |
1251 */ | |
1252 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) | |
1253 { | |
1254 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos)); | |
1255 } | |
1256 | |
1257 /** | |
1258 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits). | |
1259 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha | |
1260 * @param DMA2Dx DMA2D Instance | |
1261 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF | |
1262 */ | |
1263 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) | |
1264 { | |
1265 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); | |
1266 } | |
1267 | |
1268 /** | |
1269 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits). | |
1270 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset | |
1271 * @param DMA2Dx DMA2D Instance | |
1272 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF | |
1273 * @retval None | |
1274 */ | |
1275 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) | |
1276 { | |
1277 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset); | |
1278 } | |
1279 | |
1280 /** | |
1281 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits). | |
1282 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset | |
1283 * @param DMA2Dx DMA2D Instance | |
1284 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF | |
1285 */ | |
1286 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) | |
1287 { | |
1288 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); | |
1289 } | |
1290 | |
1291 /** | |
1292 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits). | |
1293 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor | |
1294 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor | |
1295 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor | |
1296 * @param DMA2Dx DMA2D Instance | |
1297 * @param Red Value between Min_Data=0 and Max_Data=0xFF | |
1298 * @param Green Value between Min_Data=0 and Max_Data=0xFF | |
1299 * @param Blue Value between Min_Data=0 and Max_Data=0xFF | |
1300 * @retval None | |
1301 */ | |
1302 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) | |
1303 { | |
1304 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \ | |
1305 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue)); | |
1306 } | |
1307 | |
1308 /** | |
1309 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits). | |
1310 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor | |
1311 * @param DMA2Dx DMA2D Instance | |
1312 * @param Red Value between Min_Data=0 and Max_Data=0xFF | |
1313 * @retval None | |
1314 */ | |
1315 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) | |
1316 { | |
1317 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos)); | |
1318 } | |
1319 | |
1320 /** | |
1321 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits). | |
1322 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor | |
1323 * @param DMA2Dx DMA2D Instance | |
1324 * @retval Red color value between Min_Data=0 and Max_Data=0xFF | |
1325 */ | |
1326 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) | |
1327 { | |
1328 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); | |
1329 } | |
1330 | |
1331 /** | |
1332 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits). | |
1333 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor | |
1334 * @param DMA2Dx DMA2D Instance | |
1335 * @param Green Value between Min_Data=0 and Max_Data=0xFF | |
1336 * @retval None | |
1337 */ | |
1338 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) | |
1339 { | |
1340 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos)); | |
1341 } | |
1342 | |
1343 /** | |
1344 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits). | |
1345 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor | |
1346 * @param DMA2Dx DMA2D Instance | |
1347 * @retval Green color value between Min_Data=0 and Max_Data=0xFF | |
1348 */ | |
1349 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) | |
1350 { | |
1351 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); | |
1352 } | |
1353 | |
1354 /** | |
1355 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits). | |
1356 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor | |
1357 * @param DMA2Dx DMA2D Instance | |
1358 * @param Blue Value between Min_Data=0 and Max_Data=0xFF | |
1359 * @retval None | |
1360 */ | |
1361 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) | |
1362 { | |
1363 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue); | |
1364 } | |
1365 | |
1366 /** | |
1367 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits). | |
1368 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor | |
1369 * @param DMA2Dx DMA2D Instance | |
1370 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF | |
1371 */ | |
1372 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) | |
1373 { | |
1374 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); | |
1375 } | |
1376 | |
1377 /** | |
1378 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). | |
1379 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr | |
1380 * @param DMA2Dx DMA2D Instance | |
1381 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
1382 * @retval None | |
1383 */ | |
1384 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) | |
1385 { | |
1386 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress); | |
1387 } | |
1388 | |
1389 /** | |
1390 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). | |
1391 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr | |
1392 * @param DMA2Dx DMA2D Instance | |
1393 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF | |
1394 */ | |
1395 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) | |
1396 { | |
1397 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); | |
1398 } | |
1399 | |
1400 /** | |
1401 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). | |
1402 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize | |
1403 * @param DMA2Dx DMA2D Instance | |
1404 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF | |
1405 * @retval None | |
1406 */ | |
1407 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) | |
1408 { | |
1409 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos)); | |
1410 } | |
1411 | |
1412 /** | |
1413 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). | |
1414 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize | |
1415 * @param DMA2Dx DMA2D Instance | |
1416 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF | |
1417 */ | |
1418 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) | |
1419 { | |
1420 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); | |
1421 } | |
1422 | |
1423 /** | |
1424 * @brief Set DMA2D background CLUT color mode. | |
1425 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode | |
1426 * @param DMA2Dx DMA2D Instance | |
1427 * @param CLUTColorMode This parameter can be one of the following values: | |
1428 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 | |
1429 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 | |
1430 * @retval None | |
1431 */ | |
1432 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) | |
1433 { | |
1434 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode); | |
1435 } | |
1436 | |
1437 /** | |
1438 * @brief Return DMA2D background CLUT color mode. | |
1439 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode | |
1440 * @param DMA2Dx DMA2D Instance | |
1441 * @retval Returned value can be one of the following values: | |
1442 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 | |
1443 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 | |
1444 */ | |
1445 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) | |
1446 { | |
1447 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); | |
1448 } | |
1449 | |
1450 /** | |
1451 * @} | |
1452 */ | |
1453 | |
1454 /** | |
1455 * @} | |
1456 */ | |
1457 | |
1458 | |
1459 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management | |
1460 * @{ | |
1461 */ | |
1462 | |
1463 /** | |
1464 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not | |
1465 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE | |
1466 * @param DMA2Dx DMA2D Instance | |
1467 * @retval State of bit (1 or 0). | |
1468 */ | |
1469 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) | |
1470 { | |
1471 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)); | |
1472 } | |
1473 | |
1474 /** | |
1475 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not | |
1476 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC | |
1477 * @param DMA2Dx DMA2D Instance | |
1478 * @retval State of bit (1 or 0). | |
1479 */ | |
1480 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) | |
1481 { | |
1482 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)); | |
1483 } | |
1484 | |
1485 /** | |
1486 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not | |
1487 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE | |
1488 * @param DMA2Dx DMA2D Instance | |
1489 * @retval State of bit (1 or 0). | |
1490 */ | |
1491 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) | |
1492 { | |
1493 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)); | |
1494 } | |
1495 | |
1496 /** | |
1497 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not | |
1498 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW | |
1499 * @param DMA2Dx DMA2D Instance | |
1500 * @retval State of bit (1 or 0). | |
1501 */ | |
1502 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) | |
1503 { | |
1504 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)); | |
1505 } | |
1506 | |
1507 /** | |
1508 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not | |
1509 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC | |
1510 * @param DMA2Dx DMA2D Instance | |
1511 * @retval State of bit (1 or 0). | |
1512 */ | |
1513 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) | |
1514 { | |
1515 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)); | |
1516 } | |
1517 | |
1518 /** | |
1519 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not | |
1520 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE | |
1521 * @param DMA2Dx DMA2D Instance | |
1522 * @retval State of bit (1 or 0). | |
1523 */ | |
1524 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) | |
1525 { | |
1526 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)); | |
1527 } | |
1528 | |
1529 /** | |
1530 * @brief Clear DMA2D Configuration Error Interrupt Flag | |
1531 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE | |
1532 * @param DMA2Dx DMA2D Instance | |
1533 * @retval None | |
1534 */ | |
1535 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx) | |
1536 { | |
1537 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF); | |
1538 } | |
1539 | |
1540 /** | |
1541 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag | |
1542 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC | |
1543 * @param DMA2Dx DMA2D Instance | |
1544 * @retval None | |
1545 */ | |
1546 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx) | |
1547 { | |
1548 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF); | |
1549 } | |
1550 | |
1551 /** | |
1552 * @brief Clear DMA2D CLUT Access Error Interrupt Flag | |
1553 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE | |
1554 * @param DMA2Dx DMA2D Instance | |
1555 * @retval None | |
1556 */ | |
1557 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx) | |
1558 { | |
1559 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF); | |
1560 } | |
1561 | |
1562 /** | |
1563 * @brief Clear DMA2D Transfer Watermark Interrupt Flag | |
1564 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW | |
1565 * @param DMA2Dx DMA2D Instance | |
1566 * @retval None | |
1567 */ | |
1568 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx) | |
1569 { | |
1570 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF); | |
1571 } | |
1572 | |
1573 /** | |
1574 * @brief Clear DMA2D Transfer Complete Interrupt Flag | |
1575 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC | |
1576 * @param DMA2Dx DMA2D Instance | |
1577 * @retval None | |
1578 */ | |
1579 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx) | |
1580 { | |
1581 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF); | |
1582 } | |
1583 | |
1584 /** | |
1585 * @brief Clear DMA2D Transfer Error Interrupt Flag | |
1586 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE | |
1587 * @param DMA2Dx DMA2D Instance | |
1588 * @retval None | |
1589 */ | |
1590 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx) | |
1591 { | |
1592 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF); | |
1593 } | |
1594 | |
1595 /** | |
1596 * @} | |
1597 */ | |
1598 | |
1599 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management | |
1600 * @{ | |
1601 */ | |
1602 | |
1603 /** | |
1604 * @brief Enable Configuration Error Interrupt | |
1605 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE | |
1606 * @param DMA2Dx DMA2D Instance | |
1607 * @retval None | |
1608 */ | |
1609 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx) | |
1610 { | |
1611 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); | |
1612 } | |
1613 | |
1614 /** | |
1615 * @brief Enable CLUT Transfer Complete Interrupt | |
1616 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC | |
1617 * @param DMA2Dx DMA2D Instance | |
1618 * @retval None | |
1619 */ | |
1620 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx) | |
1621 { | |
1622 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); | |
1623 } | |
1624 | |
1625 /** | |
1626 * @brief Enable CLUT Access Error Interrupt | |
1627 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE | |
1628 * @param DMA2Dx DMA2D Instance | |
1629 * @retval None | |
1630 */ | |
1631 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx) | |
1632 { | |
1633 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); | |
1634 } | |
1635 | |
1636 /** | |
1637 * @brief Enable Transfer Watermark Interrupt | |
1638 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW | |
1639 * @param DMA2Dx DMA2D Instance | |
1640 * @retval None | |
1641 */ | |
1642 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx) | |
1643 { | |
1644 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); | |
1645 } | |
1646 | |
1647 /** | |
1648 * @brief Enable Transfer Complete Interrupt | |
1649 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC | |
1650 * @param DMA2Dx DMA2D Instance | |
1651 * @retval None | |
1652 */ | |
1653 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx) | |
1654 { | |
1655 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); | |
1656 } | |
1657 | |
1658 /** | |
1659 * @brief Enable Transfer Error Interrupt | |
1660 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE | |
1661 * @param DMA2Dx DMA2D Instance | |
1662 * @retval None | |
1663 */ | |
1664 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx) | |
1665 { | |
1666 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); | |
1667 } | |
1668 | |
1669 /** | |
1670 * @brief Disable Configuration Error Interrupt | |
1671 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE | |
1672 * @param DMA2Dx DMA2D Instance | |
1673 * @retval None | |
1674 */ | |
1675 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx) | |
1676 { | |
1677 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); | |
1678 } | |
1679 | |
1680 /** | |
1681 * @brief Disable CLUT Transfer Complete Interrupt | |
1682 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC | |
1683 * @param DMA2Dx DMA2D Instance | |
1684 * @retval None | |
1685 */ | |
1686 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx) | |
1687 { | |
1688 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); | |
1689 } | |
1690 | |
1691 /** | |
1692 * @brief Disable CLUT Access Error Interrupt | |
1693 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE | |
1694 * @param DMA2Dx DMA2D Instance | |
1695 * @retval None | |
1696 */ | |
1697 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx) | |
1698 { | |
1699 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); | |
1700 } | |
1701 | |
1702 /** | |
1703 * @brief Disable Transfer Watermark Interrupt | |
1704 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW | |
1705 * @param DMA2Dx DMA2D Instance | |
1706 * @retval None | |
1707 */ | |
1708 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx) | |
1709 { | |
1710 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); | |
1711 } | |
1712 | |
1713 /** | |
1714 * @brief Disable Transfer Complete Interrupt | |
1715 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC | |
1716 * @param DMA2Dx DMA2D Instance | |
1717 * @retval None | |
1718 */ | |
1719 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx) | |
1720 { | |
1721 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); | |
1722 } | |
1723 | |
1724 /** | |
1725 * @brief Disable Transfer Error Interrupt | |
1726 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE | |
1727 * @param DMA2Dx DMA2D Instance | |
1728 * @retval None | |
1729 */ | |
1730 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) | |
1731 { | |
1732 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); | |
1733 } | |
1734 | |
1735 /** | |
1736 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled. | |
1737 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE | |
1738 * @param DMA2Dx DMA2D Instance | |
1739 * @retval State of bit (1 or 0). | |
1740 */ | |
1741 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) | |
1742 { | |
1743 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)); | |
1744 } | |
1745 | |
1746 /** | |
1747 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled. | |
1748 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC | |
1749 * @param DMA2Dx DMA2D Instance | |
1750 * @retval State of bit (1 or 0). | |
1751 */ | |
1752 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) | |
1753 { | |
1754 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)); | |
1755 } | |
1756 | |
1757 /** | |
1758 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled. | |
1759 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE | |
1760 * @param DMA2Dx DMA2D Instance | |
1761 * @retval State of bit (1 or 0). | |
1762 */ | |
1763 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) | |
1764 { | |
1765 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)); | |
1766 } | |
1767 | |
1768 /** | |
1769 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled. | |
1770 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW | |
1771 * @param DMA2Dx DMA2D Instance | |
1772 * @retval State of bit (1 or 0). | |
1773 */ | |
1774 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) | |
1775 { | |
1776 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)); | |
1777 } | |
1778 | |
1779 /** | |
1780 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled. | |
1781 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC | |
1782 * @param DMA2Dx DMA2D Instance | |
1783 * @retval State of bit (1 or 0). | |
1784 */ | |
1785 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) | |
1786 { | |
1787 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)); | |
1788 } | |
1789 | |
1790 /** | |
1791 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled. | |
1792 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE | |
1793 * @param DMA2Dx DMA2D Instance | |
1794 * @retval State of bit (1 or 0). | |
1795 */ | |
1796 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) | |
1797 { | |
1798 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)); | |
1799 } | |
1800 | |
1801 | |
1802 | |
1803 /** | |
1804 * @} | |
1805 */ | |
1806 | |
1807 #if defined(USE_FULL_LL_DRIVER) | |
1808 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions | |
1809 * @{ | |
1810 */ | |
1811 | |
1812 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); | |
1813 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); | |
1814 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); | |
1815 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); | |
1816 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); | |
1817 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); | |
1818 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); | |
1819 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); | |
1820 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); | |
1821 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); | |
1822 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); | |
1823 | |
1824 /** | |
1825 * @} | |
1826 */ | |
1827 #endif /* USE_FULL_LL_DRIVER */ | |
1828 | |
1829 /** | |
1830 * @} | |
1831 */ | |
1832 | |
1833 /** | |
1834 * @} | |
1835 */ | |
1836 | |
1837 #endif /* defined (DMA2D) */ | |
1838 | |
1839 /** | |
1840 * @} | |
1841 */ | |
1842 | |
1843 #ifdef __cplusplus | |
1844 } | |
1845 #endif | |
1846 | |
1847 #endif /* __STM32F4xx_LL_DMA2D_H */ | |
1848 | |
1849 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |