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comparison Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_dma.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of DMA LL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_LL_DMA_H | |
38 #define __STM32F4xx_LL_DMA_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 /* Includes ------------------------------------------------------------------*/ | |
45 #include "stm32f4xx.h" | |
46 | |
47 /** @addtogroup STM32F4xx_LL_Driver | |
48 * @{ | |
49 */ | |
50 | |
51 #if defined (DMA1) || defined (DMA2) | |
52 | |
53 /** @defgroup DMA_LL DMA | |
54 * @{ | |
55 */ | |
56 | |
57 /* Private types -------------------------------------------------------------*/ | |
58 /* Private variables ---------------------------------------------------------*/ | |
59 /** @defgroup DMA_LL_Private_Variables DMA Private Variables | |
60 * @{ | |
61 */ | |
62 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ | |
63 static const uint8_t STREAM_OFFSET_TAB[] = | |
64 { | |
65 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), | |
66 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), | |
67 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), | |
68 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), | |
69 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), | |
70 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), | |
71 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), | |
72 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) | |
73 }; | |
74 | |
75 /** | |
76 * @} | |
77 */ | |
78 | |
79 /* Private constants ---------------------------------------------------------*/ | |
80 /** @defgroup DMA_LL_Private_Constants DMA Private Constants | |
81 * @{ | |
82 */ | |
83 /** | |
84 * @} | |
85 */ | |
86 | |
87 | |
88 /* Private macros ------------------------------------------------------------*/ | |
89 /* Exported types ------------------------------------------------------------*/ | |
90 #if defined(USE_FULL_LL_DRIVER) | |
91 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure | |
92 * @{ | |
93 */ | |
94 typedef struct | |
95 { | |
96 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer | |
97 or as Source base address in case of memory to memory transfer direction. | |
98 | |
99 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ | |
100 | |
101 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer | |
102 or as Destination base address in case of memory to memory transfer direction. | |
103 | |
104 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ | |
105 | |
106 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, | |
107 from memory to memory or from peripheral to memory. | |
108 This parameter can be a value of @ref DMA_LL_EC_DIRECTION | |
109 | |
110 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ | |
111 | |
112 uint32_t Mode; /*!< Specifies the normal or circular operation mode. | |
113 This parameter can be a value of @ref DMA_LL_EC_MODE | |
114 @note The circular buffer mode cannot be used if the memory to memory | |
115 data transfer direction is configured on the selected Stream | |
116 | |
117 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ | |
118 | |
119 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction | |
120 is incremented or not. | |
121 This parameter can be a value of @ref DMA_LL_EC_PERIPH | |
122 | |
123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ | |
124 | |
125 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction | |
126 is incremented or not. | |
127 This parameter can be a value of @ref DMA_LL_EC_MEMORY | |
128 | |
129 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ | |
130 | |
131 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) | |
132 in case of memory to memory transfer direction. | |
133 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN | |
134 | |
135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ | |
136 | |
137 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) | |
138 in case of memory to memory transfer direction. | |
139 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN | |
140 | |
141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ | |
142 | |
143 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. | |
144 The data unit is equal to the source buffer configuration set in PeripheralSize | |
145 or MemorySize parameters depending in the transfer direction. | |
146 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF | |
147 | |
148 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ | |
149 | |
150 uint32_t Channel; /*!< Specifies the peripheral channel. | |
151 This parameter can be a value of @ref DMA_LL_EC_CHANNEL | |
152 | |
153 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ | |
154 | |
155 uint32_t Priority; /*!< Specifies the channel priority level. | |
156 This parameter can be a value of @ref DMA_LL_EC_PRIORITY | |
157 | |
158 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ | |
159 | |
160 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. | |
161 This parameter can be a value of @ref DMA_LL_FIFOMODE | |
162 @note The Direct mode (FIFO mode disabled) cannot be used if the | |
163 memory-to-memory data transfer is configured on the selected stream | |
164 | |
165 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ | |
166 | |
167 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. | |
168 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD | |
169 | |
170 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ | |
171 | |
172 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. | |
173 It specifies the amount of data to be transferred in a single non interruptible | |
174 transaction. | |
175 This parameter can be a value of @ref DMA_LL_EC_MBURST | |
176 @note The burst mode is possible only if the address Increment mode is enabled. | |
177 | |
178 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ | |
179 | |
180 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. | |
181 It specifies the amount of data to be transferred in a single non interruptible | |
182 transaction. | |
183 This parameter can be a value of @ref DMA_LL_EC_PBURST | |
184 @note The burst mode is possible only if the address Increment mode is enabled. | |
185 | |
186 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ | |
187 | |
188 } LL_DMA_InitTypeDef; | |
189 /** | |
190 * @} | |
191 */ | |
192 #endif /*USE_FULL_LL_DRIVER*/ | |
193 /* Exported constants --------------------------------------------------------*/ | |
194 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants | |
195 * @{ | |
196 */ | |
197 | |
198 /** @defgroup DMA_LL_EC_STREAM STREAM | |
199 * @{ | |
200 */ | |
201 #define LL_DMA_STREAM_0 0x00000000U | |
202 #define LL_DMA_STREAM_1 0x00000001U | |
203 #define LL_DMA_STREAM_2 0x00000002U | |
204 #define LL_DMA_STREAM_3 0x00000003U | |
205 #define LL_DMA_STREAM_4 0x00000004U | |
206 #define LL_DMA_STREAM_5 0x00000005U | |
207 #define LL_DMA_STREAM_6 0x00000006U | |
208 #define LL_DMA_STREAM_7 0x00000007U | |
209 #define LL_DMA_STREAM_ALL 0xFFFF0000U | |
210 /** | |
211 * @} | |
212 */ | |
213 | |
214 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION | |
215 * @{ | |
216 */ | |
217 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ | |
218 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ | |
219 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ | |
220 /** | |
221 * @} | |
222 */ | |
223 | |
224 /** @defgroup DMA_LL_EC_MODE MODE | |
225 * @{ | |
226 */ | |
227 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ | |
228 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ | |
229 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ | |
230 /** | |
231 * @} | |
232 */ | |
233 | |
234 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE | |
235 * @{ | |
236 */ | |
237 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ | |
238 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ | |
239 /** | |
240 * @} | |
241 */ | |
242 | |
243 /** @defgroup DMA_LL_EC_PERIPH PERIPH | |
244 * @{ | |
245 */ | |
246 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ | |
247 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ | |
248 /** | |
249 * @} | |
250 */ | |
251 | |
252 /** @defgroup DMA_LL_EC_MEMORY MEMORY | |
253 * @{ | |
254 */ | |
255 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ | |
256 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ | |
257 /** | |
258 * @} | |
259 */ | |
260 | |
261 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN | |
262 * @{ | |
263 */ | |
264 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ | |
265 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ | |
266 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ | |
267 /** | |
268 * @} | |
269 */ | |
270 | |
271 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN | |
272 * @{ | |
273 */ | |
274 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ | |
275 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ | |
276 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ | |
277 /** | |
278 * @} | |
279 */ | |
280 | |
281 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE | |
282 * @{ | |
283 */ | |
284 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ | |
285 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ | |
286 /** | |
287 * @} | |
288 */ | |
289 | |
290 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY | |
291 * @{ | |
292 */ | |
293 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ | |
294 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ | |
295 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ | |
296 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ | |
297 /** | |
298 * @} | |
299 */ | |
300 | |
301 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL | |
302 * @{ | |
303 */ | |
304 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ | |
305 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ | |
306 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ | |
307 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ | |
308 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ | |
309 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ | |
310 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ | |
311 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ | |
312 /** | |
313 * @} | |
314 */ | |
315 | |
316 /** @defgroup DMA_LL_EC_MBURST MBURST | |
317 * @{ | |
318 */ | |
319 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ | |
320 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ | |
321 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ | |
322 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ | |
323 /** | |
324 * @} | |
325 */ | |
326 | |
327 /** @defgroup DMA_LL_EC_PBURST PBURST | |
328 * @{ | |
329 */ | |
330 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ | |
331 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ | |
332 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ | |
333 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ | |
334 /** | |
335 * @} | |
336 */ | |
337 | |
338 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE | |
339 * @{ | |
340 */ | |
341 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ | |
342 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ | |
343 /** | |
344 * @} | |
345 */ | |
346 | |
347 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 | |
348 * @{ | |
349 */ | |
350 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ | |
351 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ | |
352 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ | |
353 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ | |
354 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ | |
355 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ | |
356 /** | |
357 * @} | |
358 */ | |
359 | |
360 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD | |
361 * @{ | |
362 */ | |
363 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ | |
364 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ | |
365 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ | |
366 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ | |
367 /** | |
368 * @} | |
369 */ | |
370 | |
371 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM | |
372 * @{ | |
373 */ | |
374 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ | |
375 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ | |
376 /** | |
377 * @} | |
378 */ | |
379 | |
380 /** | |
381 * @} | |
382 */ | |
383 | |
384 /* Exported macro ------------------------------------------------------------*/ | |
385 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros | |
386 * @{ | |
387 */ | |
388 | |
389 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros | |
390 * @{ | |
391 */ | |
392 /** | |
393 * @brief Write a value in DMA register | |
394 * @param __INSTANCE__ DMA Instance | |
395 * @param __REG__ Register to be written | |
396 * @param __VALUE__ Value to be written in the register | |
397 * @retval None | |
398 */ | |
399 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) | |
400 | |
401 /** | |
402 * @brief Read a value in DMA register | |
403 * @param __INSTANCE__ DMA Instance | |
404 * @param __REG__ Register to be read | |
405 * @retval Register value | |
406 */ | |
407 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) | |
408 /** | |
409 * @} | |
410 */ | |
411 | |
412 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy | |
413 * @{ | |
414 */ | |
415 /** | |
416 * @brief Convert DMAx_Streamy into DMAx | |
417 * @param __STREAM_INSTANCE__ DMAx_Streamy | |
418 * @retval DMAx | |
419 */ | |
420 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ | |
421 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) | |
422 | |
423 /** | |
424 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y | |
425 * @param __STREAM_INSTANCE__ DMAx_Streamy | |
426 * @retval LL_DMA_CHANNEL_y | |
427 */ | |
428 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ | |
429 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ | |
430 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ | |
431 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ | |
432 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ | |
433 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ | |
434 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ | |
435 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ | |
436 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ | |
437 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ | |
438 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ | |
439 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ | |
440 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ | |
441 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ | |
442 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ | |
443 LL_DMA_STREAM_7) | |
444 | |
445 /** | |
446 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy | |
447 * @param __DMA_INSTANCE__ DMAx | |
448 * @param __STREAM__ LL_DMA_STREAM_y | |
449 * @retval DMAx_Streamy | |
450 */ | |
451 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ | |
452 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ | |
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ | |
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ | |
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ | |
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ | |
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ | |
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ | |
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ | |
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ | |
461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ | |
462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ | |
463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ | |
464 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ | |
465 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ | |
466 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ | |
467 DMA2_Stream7) | |
468 | |
469 /** | |
470 * @} | |
471 */ | |
472 | |
473 /** | |
474 * @} | |
475 */ | |
476 | |
477 | |
478 /* Exported functions --------------------------------------------------------*/ | |
479 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions | |
480 * @{ | |
481 */ | |
482 | |
483 /** @defgroup DMA_LL_EF_Configuration Configuration | |
484 * @{ | |
485 */ | |
486 /** | |
487 * @brief Enable DMA stream. | |
488 * @rmtoll CR EN LL_DMA_EnableStream | |
489 * @param DMAx DMAx Instance | |
490 * @param Stream This parameter can be one of the following values: | |
491 * @arg @ref LL_DMA_STREAM_0 | |
492 * @arg @ref LL_DMA_STREAM_1 | |
493 * @arg @ref LL_DMA_STREAM_2 | |
494 * @arg @ref LL_DMA_STREAM_3 | |
495 * @arg @ref LL_DMA_STREAM_4 | |
496 * @arg @ref LL_DMA_STREAM_5 | |
497 * @arg @ref LL_DMA_STREAM_6 | |
498 * @arg @ref LL_DMA_STREAM_7 | |
499 * @retval None | |
500 */ | |
501 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) | |
502 { | |
503 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); | |
504 } | |
505 | |
506 /** | |
507 * @brief Disable DMA stream. | |
508 * @rmtoll CR EN LL_DMA_DisableStream | |
509 * @param DMAx DMAx Instance | |
510 * @param Stream This parameter can be one of the following values: | |
511 * @arg @ref LL_DMA_STREAM_0 | |
512 * @arg @ref LL_DMA_STREAM_1 | |
513 * @arg @ref LL_DMA_STREAM_2 | |
514 * @arg @ref LL_DMA_STREAM_3 | |
515 * @arg @ref LL_DMA_STREAM_4 | |
516 * @arg @ref LL_DMA_STREAM_5 | |
517 * @arg @ref LL_DMA_STREAM_6 | |
518 * @arg @ref LL_DMA_STREAM_7 | |
519 * @retval None | |
520 */ | |
521 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) | |
522 { | |
523 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); | |
524 } | |
525 | |
526 /** | |
527 * @brief Check if DMA stream is enabled or disabled. | |
528 * @rmtoll CR EN LL_DMA_IsEnabledStream | |
529 * @param DMAx DMAx Instance | |
530 * @param Stream This parameter can be one of the following values: | |
531 * @arg @ref LL_DMA_STREAM_0 | |
532 * @arg @ref LL_DMA_STREAM_1 | |
533 * @arg @ref LL_DMA_STREAM_2 | |
534 * @arg @ref LL_DMA_STREAM_3 | |
535 * @arg @ref LL_DMA_STREAM_4 | |
536 * @arg @ref LL_DMA_STREAM_5 | |
537 * @arg @ref LL_DMA_STREAM_6 | |
538 * @arg @ref LL_DMA_STREAM_7 | |
539 * @retval State of bit (1 or 0). | |
540 */ | |
541 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) | |
542 { | |
543 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); | |
544 } | |
545 | |
546 /** | |
547 * @brief Configure all parameters linked to DMA transfer. | |
548 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n | |
549 * CR CIRC LL_DMA_ConfigTransfer\n | |
550 * CR PINC LL_DMA_ConfigTransfer\n | |
551 * CR MINC LL_DMA_ConfigTransfer\n | |
552 * CR PSIZE LL_DMA_ConfigTransfer\n | |
553 * CR MSIZE LL_DMA_ConfigTransfer\n | |
554 * CR PL LL_DMA_ConfigTransfer\n | |
555 * CR PFCTRL LL_DMA_ConfigTransfer | |
556 * @param DMAx DMAx Instance | |
557 * @param Stream This parameter can be one of the following values: | |
558 * @arg @ref LL_DMA_STREAM_0 | |
559 * @arg @ref LL_DMA_STREAM_1 | |
560 * @arg @ref LL_DMA_STREAM_2 | |
561 * @arg @ref LL_DMA_STREAM_3 | |
562 * @arg @ref LL_DMA_STREAM_4 | |
563 * @arg @ref LL_DMA_STREAM_5 | |
564 * @arg @ref LL_DMA_STREAM_6 | |
565 * @arg @ref LL_DMA_STREAM_7 | |
566 * @param Configuration This parameter must be a combination of all the following values: | |
567 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY | |
568 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL | |
569 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT | |
570 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT | |
571 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD | |
572 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD | |
573 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH | |
574 *@retval None | |
575 */ | |
576 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) | |
577 { | |
578 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, | |
579 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, | |
580 Configuration); | |
581 } | |
582 | |
583 /** | |
584 * @brief Set Data transfer direction (read from peripheral or from memory). | |
585 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection | |
586 * @param DMAx DMAx Instance | |
587 * @param Stream This parameter can be one of the following values: | |
588 * @arg @ref LL_DMA_STREAM_0 | |
589 * @arg @ref LL_DMA_STREAM_1 | |
590 * @arg @ref LL_DMA_STREAM_2 | |
591 * @arg @ref LL_DMA_STREAM_3 | |
592 * @arg @ref LL_DMA_STREAM_4 | |
593 * @arg @ref LL_DMA_STREAM_5 | |
594 * @arg @ref LL_DMA_STREAM_6 | |
595 * @arg @ref LL_DMA_STREAM_7 | |
596 * @param Direction This parameter can be one of the following values: | |
597 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY | |
598 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH | |
599 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY | |
600 * @retval None | |
601 */ | |
602 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) | |
603 { | |
604 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); | |
605 } | |
606 | |
607 /** | |
608 * @brief Get Data transfer direction (read from peripheral or from memory). | |
609 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection | |
610 * @param DMAx DMAx Instance | |
611 * @param Stream This parameter can be one of the following values: | |
612 * @arg @ref LL_DMA_STREAM_0 | |
613 * @arg @ref LL_DMA_STREAM_1 | |
614 * @arg @ref LL_DMA_STREAM_2 | |
615 * @arg @ref LL_DMA_STREAM_3 | |
616 * @arg @ref LL_DMA_STREAM_4 | |
617 * @arg @ref LL_DMA_STREAM_5 | |
618 * @arg @ref LL_DMA_STREAM_6 | |
619 * @arg @ref LL_DMA_STREAM_7 | |
620 * @retval Returned value can be one of the following values: | |
621 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY | |
622 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH | |
623 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY | |
624 */ | |
625 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) | |
626 { | |
627 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); | |
628 } | |
629 | |
630 /** | |
631 * @brief Set DMA mode normal, circular or peripheral flow control. | |
632 * @rmtoll CR CIRC LL_DMA_SetMode\n | |
633 * CR PFCTRL LL_DMA_SetMode | |
634 * @param DMAx DMAx Instance | |
635 * @param Stream This parameter can be one of the following values: | |
636 * @arg @ref LL_DMA_STREAM_0 | |
637 * @arg @ref LL_DMA_STREAM_1 | |
638 * @arg @ref LL_DMA_STREAM_2 | |
639 * @arg @ref LL_DMA_STREAM_3 | |
640 * @arg @ref LL_DMA_STREAM_4 | |
641 * @arg @ref LL_DMA_STREAM_5 | |
642 * @arg @ref LL_DMA_STREAM_6 | |
643 * @arg @ref LL_DMA_STREAM_7 | |
644 * @param Mode This parameter can be one of the following values: | |
645 * @arg @ref LL_DMA_MODE_NORMAL | |
646 * @arg @ref LL_DMA_MODE_CIRCULAR | |
647 * @arg @ref LL_DMA_MODE_PFCTRL | |
648 * @retval None | |
649 */ | |
650 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) | |
651 { | |
652 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); | |
653 } | |
654 | |
655 /** | |
656 * @brief Get DMA mode normal, circular or peripheral flow control. | |
657 * @rmtoll CR CIRC LL_DMA_GetMode\n | |
658 * CR PFCTRL LL_DMA_GetMode | |
659 * @param DMAx DMAx Instance | |
660 * @param Stream This parameter can be one of the following values: | |
661 * @arg @ref LL_DMA_STREAM_0 | |
662 * @arg @ref LL_DMA_STREAM_1 | |
663 * @arg @ref LL_DMA_STREAM_2 | |
664 * @arg @ref LL_DMA_STREAM_3 | |
665 * @arg @ref LL_DMA_STREAM_4 | |
666 * @arg @ref LL_DMA_STREAM_5 | |
667 * @arg @ref LL_DMA_STREAM_6 | |
668 * @arg @ref LL_DMA_STREAM_7 | |
669 * @retval Returned value can be one of the following values: | |
670 * @arg @ref LL_DMA_MODE_NORMAL | |
671 * @arg @ref LL_DMA_MODE_CIRCULAR | |
672 * @arg @ref LL_DMA_MODE_PFCTRL | |
673 */ | |
674 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) | |
675 { | |
676 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); | |
677 } | |
678 | |
679 /** | |
680 * @brief Set Peripheral increment mode. | |
681 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode | |
682 * @param DMAx DMAx Instance | |
683 * @param Stream This parameter can be one of the following values: | |
684 * @arg @ref LL_DMA_STREAM_0 | |
685 * @arg @ref LL_DMA_STREAM_1 | |
686 * @arg @ref LL_DMA_STREAM_2 | |
687 * @arg @ref LL_DMA_STREAM_3 | |
688 * @arg @ref LL_DMA_STREAM_4 | |
689 * @arg @ref LL_DMA_STREAM_5 | |
690 * @arg @ref LL_DMA_STREAM_6 | |
691 * @arg @ref LL_DMA_STREAM_7 | |
692 * @param IncrementMode This parameter can be one of the following values: | |
693 * @arg @ref LL_DMA_PERIPH_NOINCREMENT | |
694 * @arg @ref LL_DMA_PERIPH_INCREMENT | |
695 * @retval None | |
696 */ | |
697 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) | |
698 { | |
699 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); | |
700 } | |
701 | |
702 /** | |
703 * @brief Get Peripheral increment mode. | |
704 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode | |
705 * @param DMAx DMAx Instance | |
706 * @param Stream This parameter can be one of the following values: | |
707 * @arg @ref LL_DMA_STREAM_0 | |
708 * @arg @ref LL_DMA_STREAM_1 | |
709 * @arg @ref LL_DMA_STREAM_2 | |
710 * @arg @ref LL_DMA_STREAM_3 | |
711 * @arg @ref LL_DMA_STREAM_4 | |
712 * @arg @ref LL_DMA_STREAM_5 | |
713 * @arg @ref LL_DMA_STREAM_6 | |
714 * @arg @ref LL_DMA_STREAM_7 | |
715 * @retval Returned value can be one of the following values: | |
716 * @arg @ref LL_DMA_PERIPH_NOINCREMENT | |
717 * @arg @ref LL_DMA_PERIPH_INCREMENT | |
718 */ | |
719 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) | |
720 { | |
721 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); | |
722 } | |
723 | |
724 /** | |
725 * @brief Set Memory increment mode. | |
726 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode | |
727 * @param DMAx DMAx Instance | |
728 * @param Stream This parameter can be one of the following values: | |
729 * @arg @ref LL_DMA_STREAM_0 | |
730 * @arg @ref LL_DMA_STREAM_1 | |
731 * @arg @ref LL_DMA_STREAM_2 | |
732 * @arg @ref LL_DMA_STREAM_3 | |
733 * @arg @ref LL_DMA_STREAM_4 | |
734 * @arg @ref LL_DMA_STREAM_5 | |
735 * @arg @ref LL_DMA_STREAM_6 | |
736 * @arg @ref LL_DMA_STREAM_7 | |
737 * @param IncrementMode This parameter can be one of the following values: | |
738 * @arg @ref LL_DMA_MEMORY_NOINCREMENT | |
739 * @arg @ref LL_DMA_MEMORY_INCREMENT | |
740 * @retval None | |
741 */ | |
742 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) | |
743 { | |
744 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); | |
745 } | |
746 | |
747 /** | |
748 * @brief Get Memory increment mode. | |
749 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode | |
750 * @param DMAx DMAx Instance | |
751 * @param Stream This parameter can be one of the following values: | |
752 * @arg @ref LL_DMA_STREAM_0 | |
753 * @arg @ref LL_DMA_STREAM_1 | |
754 * @arg @ref LL_DMA_STREAM_2 | |
755 * @arg @ref LL_DMA_STREAM_3 | |
756 * @arg @ref LL_DMA_STREAM_4 | |
757 * @arg @ref LL_DMA_STREAM_5 | |
758 * @arg @ref LL_DMA_STREAM_6 | |
759 * @arg @ref LL_DMA_STREAM_7 | |
760 * @retval Returned value can be one of the following values: | |
761 * @arg @ref LL_DMA_MEMORY_NOINCREMENT | |
762 * @arg @ref LL_DMA_MEMORY_INCREMENT | |
763 */ | |
764 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) | |
765 { | |
766 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); | |
767 } | |
768 | |
769 /** | |
770 * @brief Set Peripheral size. | |
771 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize | |
772 * @param DMAx DMAx Instance | |
773 * @param Stream This parameter can be one of the following values: | |
774 * @arg @ref LL_DMA_STREAM_0 | |
775 * @arg @ref LL_DMA_STREAM_1 | |
776 * @arg @ref LL_DMA_STREAM_2 | |
777 * @arg @ref LL_DMA_STREAM_3 | |
778 * @arg @ref LL_DMA_STREAM_4 | |
779 * @arg @ref LL_DMA_STREAM_5 | |
780 * @arg @ref LL_DMA_STREAM_6 | |
781 * @arg @ref LL_DMA_STREAM_7 | |
782 * @param Size This parameter can be one of the following values: | |
783 * @arg @ref LL_DMA_PDATAALIGN_BYTE | |
784 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD | |
785 * @arg @ref LL_DMA_PDATAALIGN_WORD | |
786 * @retval None | |
787 */ | |
788 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) | |
789 { | |
790 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); | |
791 } | |
792 | |
793 /** | |
794 * @brief Get Peripheral size. | |
795 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize | |
796 * @param DMAx DMAx Instance | |
797 * @param Stream This parameter can be one of the following values: | |
798 * @arg @ref LL_DMA_STREAM_0 | |
799 * @arg @ref LL_DMA_STREAM_1 | |
800 * @arg @ref LL_DMA_STREAM_2 | |
801 * @arg @ref LL_DMA_STREAM_3 | |
802 * @arg @ref LL_DMA_STREAM_4 | |
803 * @arg @ref LL_DMA_STREAM_5 | |
804 * @arg @ref LL_DMA_STREAM_6 | |
805 * @arg @ref LL_DMA_STREAM_7 | |
806 * @retval Returned value can be one of the following values: | |
807 * @arg @ref LL_DMA_PDATAALIGN_BYTE | |
808 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD | |
809 * @arg @ref LL_DMA_PDATAALIGN_WORD | |
810 */ | |
811 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) | |
812 { | |
813 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); | |
814 } | |
815 | |
816 /** | |
817 * @brief Set Memory size. | |
818 * @rmtoll CR MSIZE LL_DMA_SetMemorySize | |
819 * @param DMAx DMAx Instance | |
820 * @param Stream This parameter can be one of the following values: | |
821 * @arg @ref LL_DMA_STREAM_0 | |
822 * @arg @ref LL_DMA_STREAM_1 | |
823 * @arg @ref LL_DMA_STREAM_2 | |
824 * @arg @ref LL_DMA_STREAM_3 | |
825 * @arg @ref LL_DMA_STREAM_4 | |
826 * @arg @ref LL_DMA_STREAM_5 | |
827 * @arg @ref LL_DMA_STREAM_6 | |
828 * @arg @ref LL_DMA_STREAM_7 | |
829 * @param Size This parameter can be one of the following values: | |
830 * @arg @ref LL_DMA_MDATAALIGN_BYTE | |
831 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD | |
832 * @arg @ref LL_DMA_MDATAALIGN_WORD | |
833 * @retval None | |
834 */ | |
835 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) | |
836 { | |
837 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); | |
838 } | |
839 | |
840 /** | |
841 * @brief Get Memory size. | |
842 * @rmtoll CR MSIZE LL_DMA_GetMemorySize | |
843 * @param DMAx DMAx Instance | |
844 * @param Stream This parameter can be one of the following values: | |
845 * @arg @ref LL_DMA_STREAM_0 | |
846 * @arg @ref LL_DMA_STREAM_1 | |
847 * @arg @ref LL_DMA_STREAM_2 | |
848 * @arg @ref LL_DMA_STREAM_3 | |
849 * @arg @ref LL_DMA_STREAM_4 | |
850 * @arg @ref LL_DMA_STREAM_5 | |
851 * @arg @ref LL_DMA_STREAM_6 | |
852 * @arg @ref LL_DMA_STREAM_7 | |
853 * @retval Returned value can be one of the following values: | |
854 * @arg @ref LL_DMA_MDATAALIGN_BYTE | |
855 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD | |
856 * @arg @ref LL_DMA_MDATAALIGN_WORD | |
857 */ | |
858 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) | |
859 { | |
860 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); | |
861 } | |
862 | |
863 /** | |
864 * @brief Set Peripheral increment offset size. | |
865 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize | |
866 * @param DMAx DMAx Instance | |
867 * @param Stream This parameter can be one of the following values: | |
868 * @arg @ref LL_DMA_STREAM_0 | |
869 * @arg @ref LL_DMA_STREAM_1 | |
870 * @arg @ref LL_DMA_STREAM_2 | |
871 * @arg @ref LL_DMA_STREAM_3 | |
872 * @arg @ref LL_DMA_STREAM_4 | |
873 * @arg @ref LL_DMA_STREAM_5 | |
874 * @arg @ref LL_DMA_STREAM_6 | |
875 * @arg @ref LL_DMA_STREAM_7 | |
876 * @param OffsetSize This parameter can be one of the following values: | |
877 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE | |
878 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 | |
879 * @retval None | |
880 */ | |
881 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) | |
882 { | |
883 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); | |
884 } | |
885 | |
886 /** | |
887 * @brief Get Peripheral increment offset size. | |
888 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize | |
889 * @param DMAx DMAx Instance | |
890 * @param Stream This parameter can be one of the following values: | |
891 * @arg @ref LL_DMA_STREAM_0 | |
892 * @arg @ref LL_DMA_STREAM_1 | |
893 * @arg @ref LL_DMA_STREAM_2 | |
894 * @arg @ref LL_DMA_STREAM_3 | |
895 * @arg @ref LL_DMA_STREAM_4 | |
896 * @arg @ref LL_DMA_STREAM_5 | |
897 * @arg @ref LL_DMA_STREAM_6 | |
898 * @arg @ref LL_DMA_STREAM_7 | |
899 * @retval Returned value can be one of the following values: | |
900 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE | |
901 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 | |
902 */ | |
903 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) | |
904 { | |
905 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); | |
906 } | |
907 | |
908 /** | |
909 * @brief Set Stream priority level. | |
910 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel | |
911 * @param DMAx DMAx Instance | |
912 * @param Stream This parameter can be one of the following values: | |
913 * @arg @ref LL_DMA_STREAM_0 | |
914 * @arg @ref LL_DMA_STREAM_1 | |
915 * @arg @ref LL_DMA_STREAM_2 | |
916 * @arg @ref LL_DMA_STREAM_3 | |
917 * @arg @ref LL_DMA_STREAM_4 | |
918 * @arg @ref LL_DMA_STREAM_5 | |
919 * @arg @ref LL_DMA_STREAM_6 | |
920 * @arg @ref LL_DMA_STREAM_7 | |
921 * @param Priority This parameter can be one of the following values: | |
922 * @arg @ref LL_DMA_PRIORITY_LOW | |
923 * @arg @ref LL_DMA_PRIORITY_MEDIUM | |
924 * @arg @ref LL_DMA_PRIORITY_HIGH | |
925 * @arg @ref LL_DMA_PRIORITY_VERYHIGH | |
926 * @retval None | |
927 */ | |
928 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) | |
929 { | |
930 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); | |
931 } | |
932 | |
933 /** | |
934 * @brief Get Stream priority level. | |
935 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel | |
936 * @param DMAx DMAx Instance | |
937 * @param Stream This parameter can be one of the following values: | |
938 * @arg @ref LL_DMA_STREAM_0 | |
939 * @arg @ref LL_DMA_STREAM_1 | |
940 * @arg @ref LL_DMA_STREAM_2 | |
941 * @arg @ref LL_DMA_STREAM_3 | |
942 * @arg @ref LL_DMA_STREAM_4 | |
943 * @arg @ref LL_DMA_STREAM_5 | |
944 * @arg @ref LL_DMA_STREAM_6 | |
945 * @arg @ref LL_DMA_STREAM_7 | |
946 * @retval Returned value can be one of the following values: | |
947 * @arg @ref LL_DMA_PRIORITY_LOW | |
948 * @arg @ref LL_DMA_PRIORITY_MEDIUM | |
949 * @arg @ref LL_DMA_PRIORITY_HIGH | |
950 * @arg @ref LL_DMA_PRIORITY_VERYHIGH | |
951 */ | |
952 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) | |
953 { | |
954 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); | |
955 } | |
956 | |
957 /** | |
958 * @brief Set Number of data to transfer. | |
959 * @rmtoll NDTR NDT LL_DMA_SetDataLength | |
960 * @note This action has no effect if | |
961 * stream is enabled. | |
962 * @param DMAx DMAx Instance | |
963 * @param Stream This parameter can be one of the following values: | |
964 * @arg @ref LL_DMA_STREAM_0 | |
965 * @arg @ref LL_DMA_STREAM_1 | |
966 * @arg @ref LL_DMA_STREAM_2 | |
967 * @arg @ref LL_DMA_STREAM_3 | |
968 * @arg @ref LL_DMA_STREAM_4 | |
969 * @arg @ref LL_DMA_STREAM_5 | |
970 * @arg @ref LL_DMA_STREAM_6 | |
971 * @arg @ref LL_DMA_STREAM_7 | |
972 * @param NbData Between 0 to 0xFFFFFFFF | |
973 * @retval None | |
974 */ | |
975 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) | |
976 { | |
977 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); | |
978 } | |
979 | |
980 /** | |
981 * @brief Get Number of data to transfer. | |
982 * @rmtoll NDTR NDT LL_DMA_GetDataLength | |
983 * @note Once the stream is enabled, the return value indicate the | |
984 * remaining bytes to be transmitted. | |
985 * @param DMAx DMAx Instance | |
986 * @param Stream This parameter can be one of the following values: | |
987 * @arg @ref LL_DMA_STREAM_0 | |
988 * @arg @ref LL_DMA_STREAM_1 | |
989 * @arg @ref LL_DMA_STREAM_2 | |
990 * @arg @ref LL_DMA_STREAM_3 | |
991 * @arg @ref LL_DMA_STREAM_4 | |
992 * @arg @ref LL_DMA_STREAM_5 | |
993 * @arg @ref LL_DMA_STREAM_6 | |
994 * @arg @ref LL_DMA_STREAM_7 | |
995 * @retval Between 0 to 0xFFFFFFFF | |
996 */ | |
997 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) | |
998 { | |
999 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); | |
1000 } | |
1001 | |
1002 /** | |
1003 * @brief Select Channel number associated to the Stream. | |
1004 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection | |
1005 * @param DMAx DMAx Instance | |
1006 * @param Stream This parameter can be one of the following values: | |
1007 * @arg @ref LL_DMA_STREAM_0 | |
1008 * @arg @ref LL_DMA_STREAM_1 | |
1009 * @arg @ref LL_DMA_STREAM_2 | |
1010 * @arg @ref LL_DMA_STREAM_3 | |
1011 * @arg @ref LL_DMA_STREAM_4 | |
1012 * @arg @ref LL_DMA_STREAM_5 | |
1013 * @arg @ref LL_DMA_STREAM_6 | |
1014 * @arg @ref LL_DMA_STREAM_7 | |
1015 * @param Channel This parameter can be one of the following values: | |
1016 * @arg @ref LL_DMA_CHANNEL_0 | |
1017 * @arg @ref LL_DMA_CHANNEL_1 | |
1018 * @arg @ref LL_DMA_CHANNEL_2 | |
1019 * @arg @ref LL_DMA_CHANNEL_3 | |
1020 * @arg @ref LL_DMA_CHANNEL_4 | |
1021 * @arg @ref LL_DMA_CHANNEL_5 | |
1022 * @arg @ref LL_DMA_CHANNEL_6 | |
1023 * @arg @ref LL_DMA_CHANNEL_7 | |
1024 * @retval None | |
1025 */ | |
1026 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) | |
1027 { | |
1028 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); | |
1029 } | |
1030 | |
1031 /** | |
1032 * @brief Get the Channel number associated to the Stream. | |
1033 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection | |
1034 * @param DMAx DMAx Instance | |
1035 * @param Stream This parameter can be one of the following values: | |
1036 * @arg @ref LL_DMA_STREAM_0 | |
1037 * @arg @ref LL_DMA_STREAM_1 | |
1038 * @arg @ref LL_DMA_STREAM_2 | |
1039 * @arg @ref LL_DMA_STREAM_3 | |
1040 * @arg @ref LL_DMA_STREAM_4 | |
1041 * @arg @ref LL_DMA_STREAM_5 | |
1042 * @arg @ref LL_DMA_STREAM_6 | |
1043 * @arg @ref LL_DMA_STREAM_7 | |
1044 * @retval Returned value can be one of the following values: | |
1045 * @arg @ref LL_DMA_CHANNEL_0 | |
1046 * @arg @ref LL_DMA_CHANNEL_1 | |
1047 * @arg @ref LL_DMA_CHANNEL_2 | |
1048 * @arg @ref LL_DMA_CHANNEL_3 | |
1049 * @arg @ref LL_DMA_CHANNEL_4 | |
1050 * @arg @ref LL_DMA_CHANNEL_5 | |
1051 * @arg @ref LL_DMA_CHANNEL_6 | |
1052 * @arg @ref LL_DMA_CHANNEL_7 | |
1053 */ | |
1054 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) | |
1055 { | |
1056 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); | |
1057 } | |
1058 | |
1059 /** | |
1060 * @brief Set Memory burst transfer configuration. | |
1061 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer | |
1062 * @param DMAx DMAx Instance | |
1063 * @param Stream This parameter can be one of the following values: | |
1064 * @arg @ref LL_DMA_STREAM_0 | |
1065 * @arg @ref LL_DMA_STREAM_1 | |
1066 * @arg @ref LL_DMA_STREAM_2 | |
1067 * @arg @ref LL_DMA_STREAM_3 | |
1068 * @arg @ref LL_DMA_STREAM_4 | |
1069 * @arg @ref LL_DMA_STREAM_5 | |
1070 * @arg @ref LL_DMA_STREAM_6 | |
1071 * @arg @ref LL_DMA_STREAM_7 | |
1072 * @param Mburst This parameter can be one of the following values: | |
1073 * @arg @ref LL_DMA_MBURST_SINGLE | |
1074 * @arg @ref LL_DMA_MBURST_INC4 | |
1075 * @arg @ref LL_DMA_MBURST_INC8 | |
1076 * @arg @ref LL_DMA_MBURST_INC16 | |
1077 * @retval None | |
1078 */ | |
1079 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) | |
1080 { | |
1081 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); | |
1082 } | |
1083 | |
1084 /** | |
1085 * @brief Get Memory burst transfer configuration. | |
1086 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer | |
1087 * @param DMAx DMAx Instance | |
1088 * @param Stream This parameter can be one of the following values: | |
1089 * @arg @ref LL_DMA_STREAM_0 | |
1090 * @arg @ref LL_DMA_STREAM_1 | |
1091 * @arg @ref LL_DMA_STREAM_2 | |
1092 * @arg @ref LL_DMA_STREAM_3 | |
1093 * @arg @ref LL_DMA_STREAM_4 | |
1094 * @arg @ref LL_DMA_STREAM_5 | |
1095 * @arg @ref LL_DMA_STREAM_6 | |
1096 * @arg @ref LL_DMA_STREAM_7 | |
1097 * @retval Returned value can be one of the following values: | |
1098 * @arg @ref LL_DMA_MBURST_SINGLE | |
1099 * @arg @ref LL_DMA_MBURST_INC4 | |
1100 * @arg @ref LL_DMA_MBURST_INC8 | |
1101 * @arg @ref LL_DMA_MBURST_INC16 | |
1102 */ | |
1103 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) | |
1104 { | |
1105 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); | |
1106 } | |
1107 | |
1108 /** | |
1109 * @brief Set Peripheral burst transfer configuration. | |
1110 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer | |
1111 * @param DMAx DMAx Instance | |
1112 * @param Stream This parameter can be one of the following values: | |
1113 * @arg @ref LL_DMA_STREAM_0 | |
1114 * @arg @ref LL_DMA_STREAM_1 | |
1115 * @arg @ref LL_DMA_STREAM_2 | |
1116 * @arg @ref LL_DMA_STREAM_3 | |
1117 * @arg @ref LL_DMA_STREAM_4 | |
1118 * @arg @ref LL_DMA_STREAM_5 | |
1119 * @arg @ref LL_DMA_STREAM_6 | |
1120 * @arg @ref LL_DMA_STREAM_7 | |
1121 * @param Pburst This parameter can be one of the following values: | |
1122 * @arg @ref LL_DMA_PBURST_SINGLE | |
1123 * @arg @ref LL_DMA_PBURST_INC4 | |
1124 * @arg @ref LL_DMA_PBURST_INC8 | |
1125 * @arg @ref LL_DMA_PBURST_INC16 | |
1126 * @retval None | |
1127 */ | |
1128 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) | |
1129 { | |
1130 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); | |
1131 } | |
1132 | |
1133 /** | |
1134 * @brief Get Peripheral burst transfer configuration. | |
1135 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer | |
1136 * @param DMAx DMAx Instance | |
1137 * @param Stream This parameter can be one of the following values: | |
1138 * @arg @ref LL_DMA_STREAM_0 | |
1139 * @arg @ref LL_DMA_STREAM_1 | |
1140 * @arg @ref LL_DMA_STREAM_2 | |
1141 * @arg @ref LL_DMA_STREAM_3 | |
1142 * @arg @ref LL_DMA_STREAM_4 | |
1143 * @arg @ref LL_DMA_STREAM_5 | |
1144 * @arg @ref LL_DMA_STREAM_6 | |
1145 * @arg @ref LL_DMA_STREAM_7 | |
1146 * @retval Returned value can be one of the following values: | |
1147 * @arg @ref LL_DMA_PBURST_SINGLE | |
1148 * @arg @ref LL_DMA_PBURST_INC4 | |
1149 * @arg @ref LL_DMA_PBURST_INC8 | |
1150 * @arg @ref LL_DMA_PBURST_INC16 | |
1151 */ | |
1152 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) | |
1153 { | |
1154 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); | |
1155 } | |
1156 | |
1157 /** | |
1158 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. | |
1159 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem | |
1160 * @param DMAx DMAx Instance | |
1161 * @param Stream This parameter can be one of the following values: | |
1162 * @arg @ref LL_DMA_STREAM_0 | |
1163 * @arg @ref LL_DMA_STREAM_1 | |
1164 * @arg @ref LL_DMA_STREAM_2 | |
1165 * @arg @ref LL_DMA_STREAM_3 | |
1166 * @arg @ref LL_DMA_STREAM_4 | |
1167 * @arg @ref LL_DMA_STREAM_5 | |
1168 * @arg @ref LL_DMA_STREAM_6 | |
1169 * @arg @ref LL_DMA_STREAM_7 | |
1170 * @param CurrentMemory This parameter can be one of the following values: | |
1171 * @arg @ref LL_DMA_CURRENTTARGETMEM0 | |
1172 * @arg @ref LL_DMA_CURRENTTARGETMEM1 | |
1173 * @retval None | |
1174 */ | |
1175 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) | |
1176 { | |
1177 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); | |
1178 } | |
1179 | |
1180 /** | |
1181 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. | |
1182 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem | |
1183 * @param DMAx DMAx Instance | |
1184 * @param Stream This parameter can be one of the following values: | |
1185 * @arg @ref LL_DMA_STREAM_0 | |
1186 * @arg @ref LL_DMA_STREAM_1 | |
1187 * @arg @ref LL_DMA_STREAM_2 | |
1188 * @arg @ref LL_DMA_STREAM_3 | |
1189 * @arg @ref LL_DMA_STREAM_4 | |
1190 * @arg @ref LL_DMA_STREAM_5 | |
1191 * @arg @ref LL_DMA_STREAM_6 | |
1192 * @arg @ref LL_DMA_STREAM_7 | |
1193 * @retval Returned value can be one of the following values: | |
1194 * @arg @ref LL_DMA_CURRENTTARGETMEM0 | |
1195 * @arg @ref LL_DMA_CURRENTTARGETMEM1 | |
1196 */ | |
1197 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) | |
1198 { | |
1199 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); | |
1200 } | |
1201 | |
1202 /** | |
1203 * @brief Enable the double buffer mode. | |
1204 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode | |
1205 * @param DMAx DMAx Instance | |
1206 * @param Stream This parameter can be one of the following values: | |
1207 * @arg @ref LL_DMA_STREAM_0 | |
1208 * @arg @ref LL_DMA_STREAM_1 | |
1209 * @arg @ref LL_DMA_STREAM_2 | |
1210 * @arg @ref LL_DMA_STREAM_3 | |
1211 * @arg @ref LL_DMA_STREAM_4 | |
1212 * @arg @ref LL_DMA_STREAM_5 | |
1213 * @arg @ref LL_DMA_STREAM_6 | |
1214 * @arg @ref LL_DMA_STREAM_7 | |
1215 * @retval None | |
1216 */ | |
1217 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) | |
1218 { | |
1219 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); | |
1220 } | |
1221 | |
1222 /** | |
1223 * @brief Disable the double buffer mode. | |
1224 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode | |
1225 * @param DMAx DMAx Instance | |
1226 * @param Stream This parameter can be one of the following values: | |
1227 * @arg @ref LL_DMA_STREAM_0 | |
1228 * @arg @ref LL_DMA_STREAM_1 | |
1229 * @arg @ref LL_DMA_STREAM_2 | |
1230 * @arg @ref LL_DMA_STREAM_3 | |
1231 * @arg @ref LL_DMA_STREAM_4 | |
1232 * @arg @ref LL_DMA_STREAM_5 | |
1233 * @arg @ref LL_DMA_STREAM_6 | |
1234 * @arg @ref LL_DMA_STREAM_7 | |
1235 * @retval None | |
1236 */ | |
1237 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) | |
1238 { | |
1239 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); | |
1240 } | |
1241 | |
1242 /** | |
1243 * @brief Get FIFO status. | |
1244 * @rmtoll FCR FS LL_DMA_GetFIFOStatus | |
1245 * @param DMAx DMAx Instance | |
1246 * @param Stream This parameter can be one of the following values: | |
1247 * @arg @ref LL_DMA_STREAM_0 | |
1248 * @arg @ref LL_DMA_STREAM_1 | |
1249 * @arg @ref LL_DMA_STREAM_2 | |
1250 * @arg @ref LL_DMA_STREAM_3 | |
1251 * @arg @ref LL_DMA_STREAM_4 | |
1252 * @arg @ref LL_DMA_STREAM_5 | |
1253 * @arg @ref LL_DMA_STREAM_6 | |
1254 * @arg @ref LL_DMA_STREAM_7 | |
1255 * @retval Returned value can be one of the following values: | |
1256 * @arg @ref LL_DMA_FIFOSTATUS_0_25 | |
1257 * @arg @ref LL_DMA_FIFOSTATUS_25_50 | |
1258 * @arg @ref LL_DMA_FIFOSTATUS_50_75 | |
1259 * @arg @ref LL_DMA_FIFOSTATUS_75_100 | |
1260 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY | |
1261 * @arg @ref LL_DMA_FIFOSTATUS_FULL | |
1262 */ | |
1263 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) | |
1264 { | |
1265 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); | |
1266 } | |
1267 | |
1268 /** | |
1269 * @brief Disable Fifo mode. | |
1270 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode | |
1271 * @param DMAx DMAx Instance | |
1272 * @param Stream This parameter can be one of the following values: | |
1273 * @arg @ref LL_DMA_STREAM_0 | |
1274 * @arg @ref LL_DMA_STREAM_1 | |
1275 * @arg @ref LL_DMA_STREAM_2 | |
1276 * @arg @ref LL_DMA_STREAM_3 | |
1277 * @arg @ref LL_DMA_STREAM_4 | |
1278 * @arg @ref LL_DMA_STREAM_5 | |
1279 * @arg @ref LL_DMA_STREAM_6 | |
1280 * @arg @ref LL_DMA_STREAM_7 | |
1281 * @retval None | |
1282 */ | |
1283 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) | |
1284 { | |
1285 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); | |
1286 } | |
1287 | |
1288 /** | |
1289 * @brief Enable Fifo mode. | |
1290 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode | |
1291 * @param DMAx DMAx Instance | |
1292 * @param Stream This parameter can be one of the following values: | |
1293 * @arg @ref LL_DMA_STREAM_0 | |
1294 * @arg @ref LL_DMA_STREAM_1 | |
1295 * @arg @ref LL_DMA_STREAM_2 | |
1296 * @arg @ref LL_DMA_STREAM_3 | |
1297 * @arg @ref LL_DMA_STREAM_4 | |
1298 * @arg @ref LL_DMA_STREAM_5 | |
1299 * @arg @ref LL_DMA_STREAM_6 | |
1300 * @arg @ref LL_DMA_STREAM_7 | |
1301 * @retval None | |
1302 */ | |
1303 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) | |
1304 { | |
1305 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); | |
1306 } | |
1307 | |
1308 /** | |
1309 * @brief Select FIFO threshold. | |
1310 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold | |
1311 * @param DMAx DMAx Instance | |
1312 * @param Stream This parameter can be one of the following values: | |
1313 * @arg @ref LL_DMA_STREAM_0 | |
1314 * @arg @ref LL_DMA_STREAM_1 | |
1315 * @arg @ref LL_DMA_STREAM_2 | |
1316 * @arg @ref LL_DMA_STREAM_3 | |
1317 * @arg @ref LL_DMA_STREAM_4 | |
1318 * @arg @ref LL_DMA_STREAM_5 | |
1319 * @arg @ref LL_DMA_STREAM_6 | |
1320 * @arg @ref LL_DMA_STREAM_7 | |
1321 * @param Threshold This parameter can be one of the following values: | |
1322 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 | |
1323 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 | |
1324 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 | |
1325 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL | |
1326 * @retval None | |
1327 */ | |
1328 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) | |
1329 { | |
1330 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); | |
1331 } | |
1332 | |
1333 /** | |
1334 * @brief Get FIFO threshold. | |
1335 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold | |
1336 * @param DMAx DMAx Instance | |
1337 * @param Stream This parameter can be one of the following values: | |
1338 * @arg @ref LL_DMA_STREAM_0 | |
1339 * @arg @ref LL_DMA_STREAM_1 | |
1340 * @arg @ref LL_DMA_STREAM_2 | |
1341 * @arg @ref LL_DMA_STREAM_3 | |
1342 * @arg @ref LL_DMA_STREAM_4 | |
1343 * @arg @ref LL_DMA_STREAM_5 | |
1344 * @arg @ref LL_DMA_STREAM_6 | |
1345 * @arg @ref LL_DMA_STREAM_7 | |
1346 * @retval Returned value can be one of the following values: | |
1347 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 | |
1348 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 | |
1349 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 | |
1350 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL | |
1351 */ | |
1352 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) | |
1353 { | |
1354 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); | |
1355 } | |
1356 | |
1357 /** | |
1358 * @brief Configure the FIFO . | |
1359 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n | |
1360 * FCR DMDIS LL_DMA_ConfigFifo | |
1361 * @param DMAx DMAx Instance | |
1362 * @param Stream This parameter can be one of the following values: | |
1363 * @arg @ref LL_DMA_STREAM_0 | |
1364 * @arg @ref LL_DMA_STREAM_1 | |
1365 * @arg @ref LL_DMA_STREAM_2 | |
1366 * @arg @ref LL_DMA_STREAM_3 | |
1367 * @arg @ref LL_DMA_STREAM_4 | |
1368 * @arg @ref LL_DMA_STREAM_5 | |
1369 * @arg @ref LL_DMA_STREAM_6 | |
1370 * @arg @ref LL_DMA_STREAM_7 | |
1371 * @param FifoMode This parameter can be one of the following values: | |
1372 * @arg @ref LL_DMA_FIFOMODE_ENABLE | |
1373 * @arg @ref LL_DMA_FIFOMODE_DISABLE | |
1374 * @param FifoThreshold This parameter can be one of the following values: | |
1375 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 | |
1376 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 | |
1377 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 | |
1378 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL | |
1379 * @retval None | |
1380 */ | |
1381 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) | |
1382 { | |
1383 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); | |
1384 } | |
1385 | |
1386 /** | |
1387 * @brief Configure the Source and Destination addresses. | |
1388 * @note This API must not be called when the DMA stream is enabled. | |
1389 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n | |
1390 * PAR PA LL_DMA_ConfigAddresses | |
1391 * @param DMAx DMAx Instance | |
1392 * @param Stream This parameter can be one of the following values: | |
1393 * @arg @ref LL_DMA_STREAM_0 | |
1394 * @arg @ref LL_DMA_STREAM_1 | |
1395 * @arg @ref LL_DMA_STREAM_2 | |
1396 * @arg @ref LL_DMA_STREAM_3 | |
1397 * @arg @ref LL_DMA_STREAM_4 | |
1398 * @arg @ref LL_DMA_STREAM_5 | |
1399 * @arg @ref LL_DMA_STREAM_6 | |
1400 * @arg @ref LL_DMA_STREAM_7 | |
1401 * @param SrcAddress Between 0 to 0xFFFFFFFF | |
1402 * @param DstAddress Between 0 to 0xFFFFFFFF | |
1403 * @param Direction This parameter can be one of the following values: | |
1404 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY | |
1405 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH | |
1406 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY | |
1407 * @retval None | |
1408 */ | |
1409 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) | |
1410 { | |
1411 /* Direction Memory to Periph */ | |
1412 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) | |
1413 { | |
1414 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); | |
1415 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); | |
1416 } | |
1417 /* Direction Periph to Memory and Memory to Memory */ | |
1418 else | |
1419 { | |
1420 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); | |
1421 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); | |
1422 } | |
1423 } | |
1424 | |
1425 /** | |
1426 * @brief Set the Memory address. | |
1427 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress | |
1428 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. | |
1429 * @note This API must not be called when the DMA channel is enabled. | |
1430 * @param DMAx DMAx Instance | |
1431 * @param Stream This parameter can be one of the following values: | |
1432 * @arg @ref LL_DMA_STREAM_0 | |
1433 * @arg @ref LL_DMA_STREAM_1 | |
1434 * @arg @ref LL_DMA_STREAM_2 | |
1435 * @arg @ref LL_DMA_STREAM_3 | |
1436 * @arg @ref LL_DMA_STREAM_4 | |
1437 * @arg @ref LL_DMA_STREAM_5 | |
1438 * @arg @ref LL_DMA_STREAM_6 | |
1439 * @arg @ref LL_DMA_STREAM_7 | |
1440 * @param MemoryAddress Between 0 to 0xFFFFFFFF | |
1441 * @retval None | |
1442 */ | |
1443 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) | |
1444 { | |
1445 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); | |
1446 } | |
1447 | |
1448 /** | |
1449 * @brief Set the Peripheral address. | |
1450 * @rmtoll PAR PA LL_DMA_SetPeriphAddress | |
1451 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. | |
1452 * @note This API must not be called when the DMA channel is enabled. | |
1453 * @param DMAx DMAx Instance | |
1454 * @param Stream This parameter can be one of the following values: | |
1455 * @arg @ref LL_DMA_STREAM_0 | |
1456 * @arg @ref LL_DMA_STREAM_1 | |
1457 * @arg @ref LL_DMA_STREAM_2 | |
1458 * @arg @ref LL_DMA_STREAM_3 | |
1459 * @arg @ref LL_DMA_STREAM_4 | |
1460 * @arg @ref LL_DMA_STREAM_5 | |
1461 * @arg @ref LL_DMA_STREAM_6 | |
1462 * @arg @ref LL_DMA_STREAM_7 | |
1463 * @param PeriphAddress Between 0 to 0xFFFFFFFF | |
1464 * @retval None | |
1465 */ | |
1466 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) | |
1467 { | |
1468 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); | |
1469 } | |
1470 | |
1471 /** | |
1472 * @brief Get the Memory address. | |
1473 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress | |
1474 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. | |
1475 * @param DMAx DMAx Instance | |
1476 * @param Stream This parameter can be one of the following values: | |
1477 * @arg @ref LL_DMA_STREAM_0 | |
1478 * @arg @ref LL_DMA_STREAM_1 | |
1479 * @arg @ref LL_DMA_STREAM_2 | |
1480 * @arg @ref LL_DMA_STREAM_3 | |
1481 * @arg @ref LL_DMA_STREAM_4 | |
1482 * @arg @ref LL_DMA_STREAM_5 | |
1483 * @arg @ref LL_DMA_STREAM_6 | |
1484 * @arg @ref LL_DMA_STREAM_7 | |
1485 * @retval Between 0 to 0xFFFFFFFF | |
1486 */ | |
1487 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) | |
1488 { | |
1489 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); | |
1490 } | |
1491 | |
1492 /** | |
1493 * @brief Get the Peripheral address. | |
1494 * @rmtoll PAR PA LL_DMA_GetPeriphAddress | |
1495 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. | |
1496 * @param DMAx DMAx Instance | |
1497 * @param Stream This parameter can be one of the following values: | |
1498 * @arg @ref LL_DMA_STREAM_0 | |
1499 * @arg @ref LL_DMA_STREAM_1 | |
1500 * @arg @ref LL_DMA_STREAM_2 | |
1501 * @arg @ref LL_DMA_STREAM_3 | |
1502 * @arg @ref LL_DMA_STREAM_4 | |
1503 * @arg @ref LL_DMA_STREAM_5 | |
1504 * @arg @ref LL_DMA_STREAM_6 | |
1505 * @arg @ref LL_DMA_STREAM_7 | |
1506 * @retval Between 0 to 0xFFFFFFFF | |
1507 */ | |
1508 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) | |
1509 { | |
1510 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); | |
1511 } | |
1512 | |
1513 /** | |
1514 * @brief Set the Memory to Memory Source address. | |
1515 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress | |
1516 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. | |
1517 * @note This API must not be called when the DMA channel is enabled. | |
1518 * @param DMAx DMAx Instance | |
1519 * @param Stream This parameter can be one of the following values: | |
1520 * @arg @ref LL_DMA_STREAM_0 | |
1521 * @arg @ref LL_DMA_STREAM_1 | |
1522 * @arg @ref LL_DMA_STREAM_2 | |
1523 * @arg @ref LL_DMA_STREAM_3 | |
1524 * @arg @ref LL_DMA_STREAM_4 | |
1525 * @arg @ref LL_DMA_STREAM_5 | |
1526 * @arg @ref LL_DMA_STREAM_6 | |
1527 * @arg @ref LL_DMA_STREAM_7 | |
1528 * @param MemoryAddress Between 0 to 0xFFFFFFFF | |
1529 * @retval None | |
1530 */ | |
1531 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) | |
1532 { | |
1533 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); | |
1534 } | |
1535 | |
1536 /** | |
1537 * @brief Set the Memory to Memory Destination address. | |
1538 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress | |
1539 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. | |
1540 * @note This API must not be called when the DMA channel is enabled. | |
1541 * @param DMAx DMAx Instance | |
1542 * @param Stream This parameter can be one of the following values: | |
1543 * @arg @ref LL_DMA_STREAM_0 | |
1544 * @arg @ref LL_DMA_STREAM_1 | |
1545 * @arg @ref LL_DMA_STREAM_2 | |
1546 * @arg @ref LL_DMA_STREAM_3 | |
1547 * @arg @ref LL_DMA_STREAM_4 | |
1548 * @arg @ref LL_DMA_STREAM_5 | |
1549 * @arg @ref LL_DMA_STREAM_6 | |
1550 * @arg @ref LL_DMA_STREAM_7 | |
1551 * @param MemoryAddress Between 0 to 0xFFFFFFFF | |
1552 * @retval None | |
1553 */ | |
1554 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) | |
1555 { | |
1556 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); | |
1557 } | |
1558 | |
1559 /** | |
1560 * @brief Get the Memory to Memory Source address. | |
1561 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress | |
1562 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. | |
1563 * @param DMAx DMAx Instance | |
1564 * @param Stream This parameter can be one of the following values: | |
1565 * @arg @ref LL_DMA_STREAM_0 | |
1566 * @arg @ref LL_DMA_STREAM_1 | |
1567 * @arg @ref LL_DMA_STREAM_2 | |
1568 * @arg @ref LL_DMA_STREAM_3 | |
1569 * @arg @ref LL_DMA_STREAM_4 | |
1570 * @arg @ref LL_DMA_STREAM_5 | |
1571 * @arg @ref LL_DMA_STREAM_6 | |
1572 * @arg @ref LL_DMA_STREAM_7 | |
1573 * @retval Between 0 to 0xFFFFFFFF | |
1574 */ | |
1575 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) | |
1576 { | |
1577 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); | |
1578 } | |
1579 | |
1580 /** | |
1581 * @brief Get the Memory to Memory Destination address. | |
1582 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress | |
1583 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. | |
1584 * @param DMAx DMAx Instance | |
1585 * @param Stream This parameter can be one of the following values: | |
1586 * @arg @ref LL_DMA_STREAM_0 | |
1587 * @arg @ref LL_DMA_STREAM_1 | |
1588 * @arg @ref LL_DMA_STREAM_2 | |
1589 * @arg @ref LL_DMA_STREAM_3 | |
1590 * @arg @ref LL_DMA_STREAM_4 | |
1591 * @arg @ref LL_DMA_STREAM_5 | |
1592 * @arg @ref LL_DMA_STREAM_6 | |
1593 * @arg @ref LL_DMA_STREAM_7 | |
1594 * @retval Between 0 to 0xFFFFFFFF | |
1595 */ | |
1596 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) | |
1597 { | |
1598 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); | |
1599 } | |
1600 | |
1601 /** | |
1602 * @brief Set Memory 1 address (used in case of Double buffer mode). | |
1603 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address | |
1604 * @param DMAx DMAx Instance | |
1605 * @param Stream This parameter can be one of the following values: | |
1606 * @arg @ref LL_DMA_STREAM_0 | |
1607 * @arg @ref LL_DMA_STREAM_1 | |
1608 * @arg @ref LL_DMA_STREAM_2 | |
1609 * @arg @ref LL_DMA_STREAM_3 | |
1610 * @arg @ref LL_DMA_STREAM_4 | |
1611 * @arg @ref LL_DMA_STREAM_5 | |
1612 * @arg @ref LL_DMA_STREAM_6 | |
1613 * @arg @ref LL_DMA_STREAM_7 | |
1614 * @param Address Between 0 to 0xFFFFFFFF | |
1615 * @retval None | |
1616 */ | |
1617 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) | |
1618 { | |
1619 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address); | |
1620 } | |
1621 | |
1622 /** | |
1623 * @brief Get Memory 1 address (used in case of Double buffer mode). | |
1624 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address | |
1625 * @param DMAx DMAx Instance | |
1626 * @param Stream This parameter can be one of the following values: | |
1627 * @arg @ref LL_DMA_STREAM_0 | |
1628 * @arg @ref LL_DMA_STREAM_1 | |
1629 * @arg @ref LL_DMA_STREAM_2 | |
1630 * @arg @ref LL_DMA_STREAM_3 | |
1631 * @arg @ref LL_DMA_STREAM_4 | |
1632 * @arg @ref LL_DMA_STREAM_5 | |
1633 * @arg @ref LL_DMA_STREAM_6 | |
1634 * @arg @ref LL_DMA_STREAM_7 | |
1635 * @retval Between 0 to 0xFFFFFFFF | |
1636 */ | |
1637 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) | |
1638 { | |
1639 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); | |
1640 } | |
1641 | |
1642 /** | |
1643 * @} | |
1644 */ | |
1645 | |
1646 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management | |
1647 * @{ | |
1648 */ | |
1649 | |
1650 /** | |
1651 * @brief Get Stream 0 half transfer flag. | |
1652 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 | |
1653 * @param DMAx DMAx Instance | |
1654 * @retval State of bit (1 or 0). | |
1655 */ | |
1656 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) | |
1657 { | |
1658 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); | |
1659 } | |
1660 | |
1661 /** | |
1662 * @brief Get Stream 1 half transfer flag. | |
1663 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 | |
1664 * @param DMAx DMAx Instance | |
1665 * @retval State of bit (1 or 0). | |
1666 */ | |
1667 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) | |
1668 { | |
1669 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); | |
1670 } | |
1671 | |
1672 /** | |
1673 * @brief Get Stream 2 half transfer flag. | |
1674 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 | |
1675 * @param DMAx DMAx Instance | |
1676 * @retval State of bit (1 or 0). | |
1677 */ | |
1678 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) | |
1679 { | |
1680 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); | |
1681 } | |
1682 | |
1683 /** | |
1684 * @brief Get Stream 3 half transfer flag. | |
1685 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 | |
1686 * @param DMAx DMAx Instance | |
1687 * @retval State of bit (1 or 0). | |
1688 */ | |
1689 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) | |
1690 { | |
1691 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); | |
1692 } | |
1693 | |
1694 /** | |
1695 * @brief Get Stream 4 half transfer flag. | |
1696 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 | |
1697 * @param DMAx DMAx Instance | |
1698 * @retval State of bit (1 or 0). | |
1699 */ | |
1700 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) | |
1701 { | |
1702 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); | |
1703 } | |
1704 | |
1705 /** | |
1706 * @brief Get Stream 5 half transfer flag. | |
1707 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 | |
1708 * @param DMAx DMAx Instance | |
1709 * @retval State of bit (1 or 0). | |
1710 */ | |
1711 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) | |
1712 { | |
1713 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); | |
1714 } | |
1715 | |
1716 /** | |
1717 * @brief Get Stream 6 half transfer flag. | |
1718 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 | |
1719 * @param DMAx DMAx Instance | |
1720 * @retval State of bit (1 or 0). | |
1721 */ | |
1722 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) | |
1723 { | |
1724 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); | |
1725 } | |
1726 | |
1727 /** | |
1728 * @brief Get Stream 7 half transfer flag. | |
1729 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 | |
1730 * @param DMAx DMAx Instance | |
1731 * @retval State of bit (1 or 0). | |
1732 */ | |
1733 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) | |
1734 { | |
1735 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); | |
1736 } | |
1737 | |
1738 /** | |
1739 * @brief Get Stream 0 transfer complete flag. | |
1740 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 | |
1741 * @param DMAx DMAx Instance | |
1742 * @retval State of bit (1 or 0). | |
1743 */ | |
1744 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) | |
1745 { | |
1746 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); | |
1747 } | |
1748 | |
1749 /** | |
1750 * @brief Get Stream 1 transfer complete flag. | |
1751 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 | |
1752 * @param DMAx DMAx Instance | |
1753 * @retval State of bit (1 or 0). | |
1754 */ | |
1755 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) | |
1756 { | |
1757 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); | |
1758 } | |
1759 | |
1760 /** | |
1761 * @brief Get Stream 2 transfer complete flag. | |
1762 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 | |
1763 * @param DMAx DMAx Instance | |
1764 * @retval State of bit (1 or 0). | |
1765 */ | |
1766 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) | |
1767 { | |
1768 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); | |
1769 } | |
1770 | |
1771 /** | |
1772 * @brief Get Stream 3 transfer complete flag. | |
1773 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 | |
1774 * @param DMAx DMAx Instance | |
1775 * @retval State of bit (1 or 0). | |
1776 */ | |
1777 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) | |
1778 { | |
1779 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); | |
1780 } | |
1781 | |
1782 /** | |
1783 * @brief Get Stream 4 transfer complete flag. | |
1784 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 | |
1785 * @param DMAx DMAx Instance | |
1786 * @retval State of bit (1 or 0). | |
1787 */ | |
1788 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) | |
1789 { | |
1790 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); | |
1791 } | |
1792 | |
1793 /** | |
1794 * @brief Get Stream 5 transfer complete flag. | |
1795 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 | |
1796 * @param DMAx DMAx Instance | |
1797 * @retval State of bit (1 or 0). | |
1798 */ | |
1799 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) | |
1800 { | |
1801 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); | |
1802 } | |
1803 | |
1804 /** | |
1805 * @brief Get Stream 6 transfer complete flag. | |
1806 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 | |
1807 * @param DMAx DMAx Instance | |
1808 * @retval State of bit (1 or 0). | |
1809 */ | |
1810 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) | |
1811 { | |
1812 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); | |
1813 } | |
1814 | |
1815 /** | |
1816 * @brief Get Stream 7 transfer complete flag. | |
1817 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 | |
1818 * @param DMAx DMAx Instance | |
1819 * @retval State of bit (1 or 0). | |
1820 */ | |
1821 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) | |
1822 { | |
1823 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); | |
1824 } | |
1825 | |
1826 /** | |
1827 * @brief Get Stream 0 transfer error flag. | |
1828 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 | |
1829 * @param DMAx DMAx Instance | |
1830 * @retval State of bit (1 or 0). | |
1831 */ | |
1832 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) | |
1833 { | |
1834 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); | |
1835 } | |
1836 | |
1837 /** | |
1838 * @brief Get Stream 1 transfer error flag. | |
1839 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 | |
1840 * @param DMAx DMAx Instance | |
1841 * @retval State of bit (1 or 0). | |
1842 */ | |
1843 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) | |
1844 { | |
1845 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); | |
1846 } | |
1847 | |
1848 /** | |
1849 * @brief Get Stream 2 transfer error flag. | |
1850 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 | |
1851 * @param DMAx DMAx Instance | |
1852 * @retval State of bit (1 or 0). | |
1853 */ | |
1854 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) | |
1855 { | |
1856 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); | |
1857 } | |
1858 | |
1859 /** | |
1860 * @brief Get Stream 3 transfer error flag. | |
1861 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 | |
1862 * @param DMAx DMAx Instance | |
1863 * @retval State of bit (1 or 0). | |
1864 */ | |
1865 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) | |
1866 { | |
1867 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); | |
1868 } | |
1869 | |
1870 /** | |
1871 * @brief Get Stream 4 transfer error flag. | |
1872 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 | |
1873 * @param DMAx DMAx Instance | |
1874 * @retval State of bit (1 or 0). | |
1875 */ | |
1876 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) | |
1877 { | |
1878 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); | |
1879 } | |
1880 | |
1881 /** | |
1882 * @brief Get Stream 5 transfer error flag. | |
1883 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 | |
1884 * @param DMAx DMAx Instance | |
1885 * @retval State of bit (1 or 0). | |
1886 */ | |
1887 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) | |
1888 { | |
1889 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); | |
1890 } | |
1891 | |
1892 /** | |
1893 * @brief Get Stream 6 transfer error flag. | |
1894 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 | |
1895 * @param DMAx DMAx Instance | |
1896 * @retval State of bit (1 or 0). | |
1897 */ | |
1898 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) | |
1899 { | |
1900 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); | |
1901 } | |
1902 | |
1903 /** | |
1904 * @brief Get Stream 7 transfer error flag. | |
1905 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 | |
1906 * @param DMAx DMAx Instance | |
1907 * @retval State of bit (1 or 0). | |
1908 */ | |
1909 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) | |
1910 { | |
1911 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); | |
1912 } | |
1913 | |
1914 /** | |
1915 * @brief Get Stream 0 direct mode error flag. | |
1916 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 | |
1917 * @param DMAx DMAx Instance | |
1918 * @retval State of bit (1 or 0). | |
1919 */ | |
1920 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) | |
1921 { | |
1922 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); | |
1923 } | |
1924 | |
1925 /** | |
1926 * @brief Get Stream 1 direct mode error flag. | |
1927 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 | |
1928 * @param DMAx DMAx Instance | |
1929 * @retval State of bit (1 or 0). | |
1930 */ | |
1931 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) | |
1932 { | |
1933 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); | |
1934 } | |
1935 | |
1936 /** | |
1937 * @brief Get Stream 2 direct mode error flag. | |
1938 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 | |
1939 * @param DMAx DMAx Instance | |
1940 * @retval State of bit (1 or 0). | |
1941 */ | |
1942 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) | |
1943 { | |
1944 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); | |
1945 } | |
1946 | |
1947 /** | |
1948 * @brief Get Stream 3 direct mode error flag. | |
1949 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 | |
1950 * @param DMAx DMAx Instance | |
1951 * @retval State of bit (1 or 0). | |
1952 */ | |
1953 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) | |
1954 { | |
1955 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); | |
1956 } | |
1957 | |
1958 /** | |
1959 * @brief Get Stream 4 direct mode error flag. | |
1960 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 | |
1961 * @param DMAx DMAx Instance | |
1962 * @retval State of bit (1 or 0). | |
1963 */ | |
1964 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) | |
1965 { | |
1966 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); | |
1967 } | |
1968 | |
1969 /** | |
1970 * @brief Get Stream 5 direct mode error flag. | |
1971 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 | |
1972 * @param DMAx DMAx Instance | |
1973 * @retval State of bit (1 or 0). | |
1974 */ | |
1975 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) | |
1976 { | |
1977 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); | |
1978 } | |
1979 | |
1980 /** | |
1981 * @brief Get Stream 6 direct mode error flag. | |
1982 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 | |
1983 * @param DMAx DMAx Instance | |
1984 * @retval State of bit (1 or 0). | |
1985 */ | |
1986 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) | |
1987 { | |
1988 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); | |
1989 } | |
1990 | |
1991 /** | |
1992 * @brief Get Stream 7 direct mode error flag. | |
1993 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 | |
1994 * @param DMAx DMAx Instance | |
1995 * @retval State of bit (1 or 0). | |
1996 */ | |
1997 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) | |
1998 { | |
1999 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); | |
2000 } | |
2001 | |
2002 /** | |
2003 * @brief Get Stream 0 FIFO error flag. | |
2004 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 | |
2005 * @param DMAx DMAx Instance | |
2006 * @retval State of bit (1 or 0). | |
2007 */ | |
2008 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) | |
2009 { | |
2010 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); | |
2011 } | |
2012 | |
2013 /** | |
2014 * @brief Get Stream 1 FIFO error flag. | |
2015 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 | |
2016 * @param DMAx DMAx Instance | |
2017 * @retval State of bit (1 or 0). | |
2018 */ | |
2019 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) | |
2020 { | |
2021 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); | |
2022 } | |
2023 | |
2024 /** | |
2025 * @brief Get Stream 2 FIFO error flag. | |
2026 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 | |
2027 * @param DMAx DMAx Instance | |
2028 * @retval State of bit (1 or 0). | |
2029 */ | |
2030 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) | |
2031 { | |
2032 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); | |
2033 } | |
2034 | |
2035 /** | |
2036 * @brief Get Stream 3 FIFO error flag. | |
2037 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 | |
2038 * @param DMAx DMAx Instance | |
2039 * @retval State of bit (1 or 0). | |
2040 */ | |
2041 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) | |
2042 { | |
2043 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); | |
2044 } | |
2045 | |
2046 /** | |
2047 * @brief Get Stream 4 FIFO error flag. | |
2048 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 | |
2049 * @param DMAx DMAx Instance | |
2050 * @retval State of bit (1 or 0). | |
2051 */ | |
2052 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) | |
2053 { | |
2054 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); | |
2055 } | |
2056 | |
2057 /** | |
2058 * @brief Get Stream 5 FIFO error flag. | |
2059 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 | |
2060 * @param DMAx DMAx Instance | |
2061 * @retval State of bit (1 or 0). | |
2062 */ | |
2063 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) | |
2064 { | |
2065 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); | |
2066 } | |
2067 | |
2068 /** | |
2069 * @brief Get Stream 6 FIFO error flag. | |
2070 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 | |
2071 * @param DMAx DMAx Instance | |
2072 * @retval State of bit (1 or 0). | |
2073 */ | |
2074 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) | |
2075 { | |
2076 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); | |
2077 } | |
2078 | |
2079 /** | |
2080 * @brief Get Stream 7 FIFO error flag. | |
2081 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 | |
2082 * @param DMAx DMAx Instance | |
2083 * @retval State of bit (1 or 0). | |
2084 */ | |
2085 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) | |
2086 { | |
2087 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); | |
2088 } | |
2089 | |
2090 /** | |
2091 * @brief Clear Stream 0 half transfer flag. | |
2092 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 | |
2093 * @param DMAx DMAx Instance | |
2094 * @retval None | |
2095 */ | |
2096 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) | |
2097 { | |
2098 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); | |
2099 } | |
2100 | |
2101 /** | |
2102 * @brief Clear Stream 1 half transfer flag. | |
2103 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 | |
2104 * @param DMAx DMAx Instance | |
2105 * @retval None | |
2106 */ | |
2107 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) | |
2108 { | |
2109 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); | |
2110 } | |
2111 | |
2112 /** | |
2113 * @brief Clear Stream 2 half transfer flag. | |
2114 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 | |
2115 * @param DMAx DMAx Instance | |
2116 * @retval None | |
2117 */ | |
2118 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) | |
2119 { | |
2120 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); | |
2121 } | |
2122 | |
2123 /** | |
2124 * @brief Clear Stream 3 half transfer flag. | |
2125 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 | |
2126 * @param DMAx DMAx Instance | |
2127 * @retval None | |
2128 */ | |
2129 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) | |
2130 { | |
2131 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); | |
2132 } | |
2133 | |
2134 /** | |
2135 * @brief Clear Stream 4 half transfer flag. | |
2136 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 | |
2137 * @param DMAx DMAx Instance | |
2138 * @retval None | |
2139 */ | |
2140 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) | |
2141 { | |
2142 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); | |
2143 } | |
2144 | |
2145 /** | |
2146 * @brief Clear Stream 5 half transfer flag. | |
2147 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 | |
2148 * @param DMAx DMAx Instance | |
2149 * @retval None | |
2150 */ | |
2151 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) | |
2152 { | |
2153 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); | |
2154 } | |
2155 | |
2156 /** | |
2157 * @brief Clear Stream 6 half transfer flag. | |
2158 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 | |
2159 * @param DMAx DMAx Instance | |
2160 * @retval None | |
2161 */ | |
2162 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) | |
2163 { | |
2164 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); | |
2165 } | |
2166 | |
2167 /** | |
2168 * @brief Clear Stream 7 half transfer flag. | |
2169 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 | |
2170 * @param DMAx DMAx Instance | |
2171 * @retval None | |
2172 */ | |
2173 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) | |
2174 { | |
2175 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); | |
2176 } | |
2177 | |
2178 /** | |
2179 * @brief Clear Stream 0 transfer complete flag. | |
2180 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 | |
2181 * @param DMAx DMAx Instance | |
2182 * @retval None | |
2183 */ | |
2184 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) | |
2185 { | |
2186 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); | |
2187 } | |
2188 | |
2189 /** | |
2190 * @brief Clear Stream 1 transfer complete flag. | |
2191 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 | |
2192 * @param DMAx DMAx Instance | |
2193 * @retval None | |
2194 */ | |
2195 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) | |
2196 { | |
2197 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); | |
2198 } | |
2199 | |
2200 /** | |
2201 * @brief Clear Stream 2 transfer complete flag. | |
2202 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 | |
2203 * @param DMAx DMAx Instance | |
2204 * @retval None | |
2205 */ | |
2206 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) | |
2207 { | |
2208 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); | |
2209 } | |
2210 | |
2211 /** | |
2212 * @brief Clear Stream 3 transfer complete flag. | |
2213 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 | |
2214 * @param DMAx DMAx Instance | |
2215 * @retval None | |
2216 */ | |
2217 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) | |
2218 { | |
2219 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); | |
2220 } | |
2221 | |
2222 /** | |
2223 * @brief Clear Stream 4 transfer complete flag. | |
2224 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 | |
2225 * @param DMAx DMAx Instance | |
2226 * @retval None | |
2227 */ | |
2228 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) | |
2229 { | |
2230 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); | |
2231 } | |
2232 | |
2233 /** | |
2234 * @brief Clear Stream 5 transfer complete flag. | |
2235 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 | |
2236 * @param DMAx DMAx Instance | |
2237 * @retval None | |
2238 */ | |
2239 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) | |
2240 { | |
2241 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); | |
2242 } | |
2243 | |
2244 /** | |
2245 * @brief Clear Stream 6 transfer complete flag. | |
2246 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 | |
2247 * @param DMAx DMAx Instance | |
2248 * @retval None | |
2249 */ | |
2250 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) | |
2251 { | |
2252 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); | |
2253 } | |
2254 | |
2255 /** | |
2256 * @brief Clear Stream 7 transfer complete flag. | |
2257 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 | |
2258 * @param DMAx DMAx Instance | |
2259 * @retval None | |
2260 */ | |
2261 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) | |
2262 { | |
2263 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); | |
2264 } | |
2265 | |
2266 /** | |
2267 * @brief Clear Stream 0 transfer error flag. | |
2268 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 | |
2269 * @param DMAx DMAx Instance | |
2270 * @retval None | |
2271 */ | |
2272 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) | |
2273 { | |
2274 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); | |
2275 } | |
2276 | |
2277 /** | |
2278 * @brief Clear Stream 1 transfer error flag. | |
2279 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 | |
2280 * @param DMAx DMAx Instance | |
2281 * @retval None | |
2282 */ | |
2283 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) | |
2284 { | |
2285 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); | |
2286 } | |
2287 | |
2288 /** | |
2289 * @brief Clear Stream 2 transfer error flag. | |
2290 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 | |
2291 * @param DMAx DMAx Instance | |
2292 * @retval None | |
2293 */ | |
2294 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) | |
2295 { | |
2296 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); | |
2297 } | |
2298 | |
2299 /** | |
2300 * @brief Clear Stream 3 transfer error flag. | |
2301 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 | |
2302 * @param DMAx DMAx Instance | |
2303 * @retval None | |
2304 */ | |
2305 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) | |
2306 { | |
2307 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); | |
2308 } | |
2309 | |
2310 /** | |
2311 * @brief Clear Stream 4 transfer error flag. | |
2312 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 | |
2313 * @param DMAx DMAx Instance | |
2314 * @retval None | |
2315 */ | |
2316 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) | |
2317 { | |
2318 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); | |
2319 } | |
2320 | |
2321 /** | |
2322 * @brief Clear Stream 5 transfer error flag. | |
2323 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 | |
2324 * @param DMAx DMAx Instance | |
2325 * @retval None | |
2326 */ | |
2327 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) | |
2328 { | |
2329 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); | |
2330 } | |
2331 | |
2332 /** | |
2333 * @brief Clear Stream 6 transfer error flag. | |
2334 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 | |
2335 * @param DMAx DMAx Instance | |
2336 * @retval None | |
2337 */ | |
2338 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) | |
2339 { | |
2340 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); | |
2341 } | |
2342 | |
2343 /** | |
2344 * @brief Clear Stream 7 transfer error flag. | |
2345 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 | |
2346 * @param DMAx DMAx Instance | |
2347 * @retval None | |
2348 */ | |
2349 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) | |
2350 { | |
2351 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); | |
2352 } | |
2353 | |
2354 /** | |
2355 * @brief Clear Stream 0 direct mode error flag. | |
2356 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 | |
2357 * @param DMAx DMAx Instance | |
2358 * @retval None | |
2359 */ | |
2360 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) | |
2361 { | |
2362 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); | |
2363 } | |
2364 | |
2365 /** | |
2366 * @brief Clear Stream 1 direct mode error flag. | |
2367 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 | |
2368 * @param DMAx DMAx Instance | |
2369 * @retval None | |
2370 */ | |
2371 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) | |
2372 { | |
2373 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); | |
2374 } | |
2375 | |
2376 /** | |
2377 * @brief Clear Stream 2 direct mode error flag. | |
2378 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 | |
2379 * @param DMAx DMAx Instance | |
2380 * @retval None | |
2381 */ | |
2382 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) | |
2383 { | |
2384 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); | |
2385 } | |
2386 | |
2387 /** | |
2388 * @brief Clear Stream 3 direct mode error flag. | |
2389 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 | |
2390 * @param DMAx DMAx Instance | |
2391 * @retval None | |
2392 */ | |
2393 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) | |
2394 { | |
2395 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); | |
2396 } | |
2397 | |
2398 /** | |
2399 * @brief Clear Stream 4 direct mode error flag. | |
2400 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 | |
2401 * @param DMAx DMAx Instance | |
2402 * @retval None | |
2403 */ | |
2404 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) | |
2405 { | |
2406 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); | |
2407 } | |
2408 | |
2409 /** | |
2410 * @brief Clear Stream 5 direct mode error flag. | |
2411 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 | |
2412 * @param DMAx DMAx Instance | |
2413 * @retval None | |
2414 */ | |
2415 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) | |
2416 { | |
2417 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); | |
2418 } | |
2419 | |
2420 /** | |
2421 * @brief Clear Stream 6 direct mode error flag. | |
2422 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 | |
2423 * @param DMAx DMAx Instance | |
2424 * @retval None | |
2425 */ | |
2426 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) | |
2427 { | |
2428 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); | |
2429 } | |
2430 | |
2431 /** | |
2432 * @brief Clear Stream 7 direct mode error flag. | |
2433 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 | |
2434 * @param DMAx DMAx Instance | |
2435 * @retval None | |
2436 */ | |
2437 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) | |
2438 { | |
2439 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); | |
2440 } | |
2441 | |
2442 /** | |
2443 * @brief Clear Stream 0 FIFO error flag. | |
2444 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 | |
2445 * @param DMAx DMAx Instance | |
2446 * @retval None | |
2447 */ | |
2448 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) | |
2449 { | |
2450 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); | |
2451 } | |
2452 | |
2453 /** | |
2454 * @brief Clear Stream 1 FIFO error flag. | |
2455 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 | |
2456 * @param DMAx DMAx Instance | |
2457 * @retval None | |
2458 */ | |
2459 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) | |
2460 { | |
2461 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); | |
2462 } | |
2463 | |
2464 /** | |
2465 * @brief Clear Stream 2 FIFO error flag. | |
2466 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 | |
2467 * @param DMAx DMAx Instance | |
2468 * @retval None | |
2469 */ | |
2470 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) | |
2471 { | |
2472 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); | |
2473 } | |
2474 | |
2475 /** | |
2476 * @brief Clear Stream 3 FIFO error flag. | |
2477 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 | |
2478 * @param DMAx DMAx Instance | |
2479 * @retval None | |
2480 */ | |
2481 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) | |
2482 { | |
2483 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); | |
2484 } | |
2485 | |
2486 /** | |
2487 * @brief Clear Stream 4 FIFO error flag. | |
2488 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 | |
2489 * @param DMAx DMAx Instance | |
2490 * @retval None | |
2491 */ | |
2492 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) | |
2493 { | |
2494 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); | |
2495 } | |
2496 | |
2497 /** | |
2498 * @brief Clear Stream 5 FIFO error flag. | |
2499 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 | |
2500 * @param DMAx DMAx Instance | |
2501 * @retval None | |
2502 */ | |
2503 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) | |
2504 { | |
2505 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); | |
2506 } | |
2507 | |
2508 /** | |
2509 * @brief Clear Stream 6 FIFO error flag. | |
2510 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 | |
2511 * @param DMAx DMAx Instance | |
2512 * @retval None | |
2513 */ | |
2514 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) | |
2515 { | |
2516 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); | |
2517 } | |
2518 | |
2519 /** | |
2520 * @brief Clear Stream 7 FIFO error flag. | |
2521 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 | |
2522 * @param DMAx DMAx Instance | |
2523 * @retval None | |
2524 */ | |
2525 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) | |
2526 { | |
2527 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); | |
2528 } | |
2529 | |
2530 /** | |
2531 * @} | |
2532 */ | |
2533 | |
2534 /** @defgroup DMA_LL_EF_IT_Management IT_Management | |
2535 * @{ | |
2536 */ | |
2537 | |
2538 /** | |
2539 * @brief Enable Half transfer interrupt. | |
2540 * @rmtoll CR HTIE LL_DMA_EnableIT_HT | |
2541 * @param DMAx DMAx Instance | |
2542 * @param Stream This parameter can be one of the following values: | |
2543 * @arg @ref LL_DMA_STREAM_0 | |
2544 * @arg @ref LL_DMA_STREAM_1 | |
2545 * @arg @ref LL_DMA_STREAM_2 | |
2546 * @arg @ref LL_DMA_STREAM_3 | |
2547 * @arg @ref LL_DMA_STREAM_4 | |
2548 * @arg @ref LL_DMA_STREAM_5 | |
2549 * @arg @ref LL_DMA_STREAM_6 | |
2550 * @arg @ref LL_DMA_STREAM_7 | |
2551 * @retval None | |
2552 */ | |
2553 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) | |
2554 { | |
2555 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); | |
2556 } | |
2557 | |
2558 /** | |
2559 * @brief Enable Transfer error interrupt. | |
2560 * @rmtoll CR TEIE LL_DMA_EnableIT_TE | |
2561 * @param DMAx DMAx Instance | |
2562 * @param Stream This parameter can be one of the following values: | |
2563 * @arg @ref LL_DMA_STREAM_0 | |
2564 * @arg @ref LL_DMA_STREAM_1 | |
2565 * @arg @ref LL_DMA_STREAM_2 | |
2566 * @arg @ref LL_DMA_STREAM_3 | |
2567 * @arg @ref LL_DMA_STREAM_4 | |
2568 * @arg @ref LL_DMA_STREAM_5 | |
2569 * @arg @ref LL_DMA_STREAM_6 | |
2570 * @arg @ref LL_DMA_STREAM_7 | |
2571 * @retval None | |
2572 */ | |
2573 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) | |
2574 { | |
2575 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); | |
2576 } | |
2577 | |
2578 /** | |
2579 * @brief Enable Transfer complete interrupt. | |
2580 * @rmtoll CR TCIE LL_DMA_EnableIT_TC | |
2581 * @param DMAx DMAx Instance | |
2582 * @param Stream This parameter can be one of the following values: | |
2583 * @arg @ref LL_DMA_STREAM_0 | |
2584 * @arg @ref LL_DMA_STREAM_1 | |
2585 * @arg @ref LL_DMA_STREAM_2 | |
2586 * @arg @ref LL_DMA_STREAM_3 | |
2587 * @arg @ref LL_DMA_STREAM_4 | |
2588 * @arg @ref LL_DMA_STREAM_5 | |
2589 * @arg @ref LL_DMA_STREAM_6 | |
2590 * @arg @ref LL_DMA_STREAM_7 | |
2591 * @retval None | |
2592 */ | |
2593 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) | |
2594 { | |
2595 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); | |
2596 } | |
2597 | |
2598 /** | |
2599 * @brief Enable Direct mode error interrupt. | |
2600 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME | |
2601 * @param DMAx DMAx Instance | |
2602 * @param Stream This parameter can be one of the following values: | |
2603 * @arg @ref LL_DMA_STREAM_0 | |
2604 * @arg @ref LL_DMA_STREAM_1 | |
2605 * @arg @ref LL_DMA_STREAM_2 | |
2606 * @arg @ref LL_DMA_STREAM_3 | |
2607 * @arg @ref LL_DMA_STREAM_4 | |
2608 * @arg @ref LL_DMA_STREAM_5 | |
2609 * @arg @ref LL_DMA_STREAM_6 | |
2610 * @arg @ref LL_DMA_STREAM_7 | |
2611 * @retval None | |
2612 */ | |
2613 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) | |
2614 { | |
2615 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); | |
2616 } | |
2617 | |
2618 /** | |
2619 * @brief Enable FIFO error interrupt. | |
2620 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE | |
2621 * @param DMAx DMAx Instance | |
2622 * @param Stream This parameter can be one of the following values: | |
2623 * @arg @ref LL_DMA_STREAM_0 | |
2624 * @arg @ref LL_DMA_STREAM_1 | |
2625 * @arg @ref LL_DMA_STREAM_2 | |
2626 * @arg @ref LL_DMA_STREAM_3 | |
2627 * @arg @ref LL_DMA_STREAM_4 | |
2628 * @arg @ref LL_DMA_STREAM_5 | |
2629 * @arg @ref LL_DMA_STREAM_6 | |
2630 * @arg @ref LL_DMA_STREAM_7 | |
2631 * @retval None | |
2632 */ | |
2633 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) | |
2634 { | |
2635 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); | |
2636 } | |
2637 | |
2638 /** | |
2639 * @brief Disable Half transfer interrupt. | |
2640 * @rmtoll CR HTIE LL_DMA_DisableIT_HT | |
2641 * @param DMAx DMAx Instance | |
2642 * @param Stream This parameter can be one of the following values: | |
2643 * @arg @ref LL_DMA_STREAM_0 | |
2644 * @arg @ref LL_DMA_STREAM_1 | |
2645 * @arg @ref LL_DMA_STREAM_2 | |
2646 * @arg @ref LL_DMA_STREAM_3 | |
2647 * @arg @ref LL_DMA_STREAM_4 | |
2648 * @arg @ref LL_DMA_STREAM_5 | |
2649 * @arg @ref LL_DMA_STREAM_6 | |
2650 * @arg @ref LL_DMA_STREAM_7 | |
2651 * @retval None | |
2652 */ | |
2653 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) | |
2654 { | |
2655 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); | |
2656 } | |
2657 | |
2658 /** | |
2659 * @brief Disable Transfer error interrupt. | |
2660 * @rmtoll CR TEIE LL_DMA_DisableIT_TE | |
2661 * @param DMAx DMAx Instance | |
2662 * @param Stream This parameter can be one of the following values: | |
2663 * @arg @ref LL_DMA_STREAM_0 | |
2664 * @arg @ref LL_DMA_STREAM_1 | |
2665 * @arg @ref LL_DMA_STREAM_2 | |
2666 * @arg @ref LL_DMA_STREAM_3 | |
2667 * @arg @ref LL_DMA_STREAM_4 | |
2668 * @arg @ref LL_DMA_STREAM_5 | |
2669 * @arg @ref LL_DMA_STREAM_6 | |
2670 * @arg @ref LL_DMA_STREAM_7 | |
2671 * @retval None | |
2672 */ | |
2673 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) | |
2674 { | |
2675 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); | |
2676 } | |
2677 | |
2678 /** | |
2679 * @brief Disable Transfer complete interrupt. | |
2680 * @rmtoll CR TCIE LL_DMA_DisableIT_TC | |
2681 * @param DMAx DMAx Instance | |
2682 * @param Stream This parameter can be one of the following values: | |
2683 * @arg @ref LL_DMA_STREAM_0 | |
2684 * @arg @ref LL_DMA_STREAM_1 | |
2685 * @arg @ref LL_DMA_STREAM_2 | |
2686 * @arg @ref LL_DMA_STREAM_3 | |
2687 * @arg @ref LL_DMA_STREAM_4 | |
2688 * @arg @ref LL_DMA_STREAM_5 | |
2689 * @arg @ref LL_DMA_STREAM_6 | |
2690 * @arg @ref LL_DMA_STREAM_7 | |
2691 * @retval None | |
2692 */ | |
2693 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) | |
2694 { | |
2695 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); | |
2696 } | |
2697 | |
2698 /** | |
2699 * @brief Disable Direct mode error interrupt. | |
2700 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME | |
2701 * @param DMAx DMAx Instance | |
2702 * @param Stream This parameter can be one of the following values: | |
2703 * @arg @ref LL_DMA_STREAM_0 | |
2704 * @arg @ref LL_DMA_STREAM_1 | |
2705 * @arg @ref LL_DMA_STREAM_2 | |
2706 * @arg @ref LL_DMA_STREAM_3 | |
2707 * @arg @ref LL_DMA_STREAM_4 | |
2708 * @arg @ref LL_DMA_STREAM_5 | |
2709 * @arg @ref LL_DMA_STREAM_6 | |
2710 * @arg @ref LL_DMA_STREAM_7 | |
2711 * @retval None | |
2712 */ | |
2713 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) | |
2714 { | |
2715 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); | |
2716 } | |
2717 | |
2718 /** | |
2719 * @brief Disable FIFO error interrupt. | |
2720 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE | |
2721 * @param DMAx DMAx Instance | |
2722 * @param Stream This parameter can be one of the following values: | |
2723 * @arg @ref LL_DMA_STREAM_0 | |
2724 * @arg @ref LL_DMA_STREAM_1 | |
2725 * @arg @ref LL_DMA_STREAM_2 | |
2726 * @arg @ref LL_DMA_STREAM_3 | |
2727 * @arg @ref LL_DMA_STREAM_4 | |
2728 * @arg @ref LL_DMA_STREAM_5 | |
2729 * @arg @ref LL_DMA_STREAM_6 | |
2730 * @arg @ref LL_DMA_STREAM_7 | |
2731 * @retval None | |
2732 */ | |
2733 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) | |
2734 { | |
2735 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); | |
2736 } | |
2737 | |
2738 /** | |
2739 * @brief Check if Half transfer interrup is enabled. | |
2740 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT | |
2741 * @param DMAx DMAx Instance | |
2742 * @param Stream This parameter can be one of the following values: | |
2743 * @arg @ref LL_DMA_STREAM_0 | |
2744 * @arg @ref LL_DMA_STREAM_1 | |
2745 * @arg @ref LL_DMA_STREAM_2 | |
2746 * @arg @ref LL_DMA_STREAM_3 | |
2747 * @arg @ref LL_DMA_STREAM_4 | |
2748 * @arg @ref LL_DMA_STREAM_5 | |
2749 * @arg @ref LL_DMA_STREAM_6 | |
2750 * @arg @ref LL_DMA_STREAM_7 | |
2751 * @retval State of bit (1 or 0). | |
2752 */ | |
2753 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) | |
2754 { | |
2755 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); | |
2756 } | |
2757 | |
2758 /** | |
2759 * @brief Check if Transfer error nterrup is enabled. | |
2760 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE | |
2761 * @param DMAx DMAx Instance | |
2762 * @param Stream This parameter can be one of the following values: | |
2763 * @arg @ref LL_DMA_STREAM_0 | |
2764 * @arg @ref LL_DMA_STREAM_1 | |
2765 * @arg @ref LL_DMA_STREAM_2 | |
2766 * @arg @ref LL_DMA_STREAM_3 | |
2767 * @arg @ref LL_DMA_STREAM_4 | |
2768 * @arg @ref LL_DMA_STREAM_5 | |
2769 * @arg @ref LL_DMA_STREAM_6 | |
2770 * @arg @ref LL_DMA_STREAM_7 | |
2771 * @retval State of bit (1 or 0). | |
2772 */ | |
2773 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) | |
2774 { | |
2775 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); | |
2776 } | |
2777 | |
2778 /** | |
2779 * @brief Check if Transfer complete interrup is enabled. | |
2780 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC | |
2781 * @param DMAx DMAx Instance | |
2782 * @param Stream This parameter can be one of the following values: | |
2783 * @arg @ref LL_DMA_STREAM_0 | |
2784 * @arg @ref LL_DMA_STREAM_1 | |
2785 * @arg @ref LL_DMA_STREAM_2 | |
2786 * @arg @ref LL_DMA_STREAM_3 | |
2787 * @arg @ref LL_DMA_STREAM_4 | |
2788 * @arg @ref LL_DMA_STREAM_5 | |
2789 * @arg @ref LL_DMA_STREAM_6 | |
2790 * @arg @ref LL_DMA_STREAM_7 | |
2791 * @retval State of bit (1 or 0). | |
2792 */ | |
2793 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) | |
2794 { | |
2795 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); | |
2796 } | |
2797 | |
2798 /** | |
2799 * @brief Check if Direct mode error interrupt is enabled. | |
2800 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME | |
2801 * @param DMAx DMAx Instance | |
2802 * @param Stream This parameter can be one of the following values: | |
2803 * @arg @ref LL_DMA_STREAM_0 | |
2804 * @arg @ref LL_DMA_STREAM_1 | |
2805 * @arg @ref LL_DMA_STREAM_2 | |
2806 * @arg @ref LL_DMA_STREAM_3 | |
2807 * @arg @ref LL_DMA_STREAM_4 | |
2808 * @arg @ref LL_DMA_STREAM_5 | |
2809 * @arg @ref LL_DMA_STREAM_6 | |
2810 * @arg @ref LL_DMA_STREAM_7 | |
2811 * @retval State of bit (1 or 0). | |
2812 */ | |
2813 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) | |
2814 { | |
2815 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); | |
2816 } | |
2817 | |
2818 /** | |
2819 * @brief Check if FIFO error interrup is enabled. | |
2820 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE | |
2821 * @param DMAx DMAx Instance | |
2822 * @param Stream This parameter can be one of the following values: | |
2823 * @arg @ref LL_DMA_STREAM_0 | |
2824 * @arg @ref LL_DMA_STREAM_1 | |
2825 * @arg @ref LL_DMA_STREAM_2 | |
2826 * @arg @ref LL_DMA_STREAM_3 | |
2827 * @arg @ref LL_DMA_STREAM_4 | |
2828 * @arg @ref LL_DMA_STREAM_5 | |
2829 * @arg @ref LL_DMA_STREAM_6 | |
2830 * @arg @ref LL_DMA_STREAM_7 | |
2831 * @retval State of bit (1 or 0). | |
2832 */ | |
2833 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) | |
2834 { | |
2835 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); | |
2836 } | |
2837 | |
2838 /** | |
2839 * @} | |
2840 */ | |
2841 | |
2842 #if defined(USE_FULL_LL_DRIVER) | |
2843 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions | |
2844 * @{ | |
2845 */ | |
2846 | |
2847 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); | |
2848 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); | |
2849 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); | |
2850 | |
2851 /** | |
2852 * @} | |
2853 */ | |
2854 #endif /* USE_FULL_LL_DRIVER */ | |
2855 | |
2856 /** | |
2857 * @} | |
2858 */ | |
2859 | |
2860 /** | |
2861 * @} | |
2862 */ | |
2863 | |
2864 #endif /* DMA1 || DMA2 */ | |
2865 | |
2866 /** | |
2867 * @} | |
2868 */ | |
2869 | |
2870 #ifdef __cplusplus | |
2871 } | |
2872 #endif | |
2873 | |
2874 #endif /* __STM32F4xx_LL_DMA_H */ | |
2875 | |
2876 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |