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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_LL_DAC_H
38 #define __STM32F4xx_LL_DAC_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx.h"
46
47 /** @addtogroup STM32F4xx_LL_Driver
48 * @{
49 */
50
51 #if defined(DAC)
52
53 /** @defgroup DAC_LL DAC
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
62 * @{
63 */
64
65 /* Internal masks for DAC channels definition */
66 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
67 /* - channel bits position into register CR */
68 /* - channel bits position into register SWTRIG */
69 /* - channel register offset of data holding register DHRx */
70 /* - channel register offset of data output register DORx */
71 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
72 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
73 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
74
75 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
76 #if defined(DAC_CHANNEL2_SUPPORT)
77 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
78 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
79 #else
80 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
81 #endif /* DAC_CHANNEL2_SUPPORT */
82
83 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
84 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
85 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
86 #if defined(DAC_CHANNEL2_SUPPORT)
87 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
88 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
89 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
90 #endif /* DAC_CHANNEL2_SUPPORT */
91 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
92 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
93 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
94 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
95
96 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
97 #if defined(DAC_CHANNEL2_SUPPORT)
98 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
99 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
100 #else
101 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
102 #endif /* DAC_CHANNEL2_SUPPORT */
103
104 /* DAC registers bits positions */
105 #if defined(DAC_CHANNEL2_SUPPORT)
106 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
107 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
108 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
109 #endif /* DAC_CHANNEL2_SUPPORT */
110
111 /* Miscellaneous data */
112 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
113
114 /**
115 * @}
116 */
117
118
119 /* Private macros ------------------------------------------------------------*/
120 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
121 * @{
122 */
123
124 /**
125 * @brief Driver macro reserved for internal use: isolate bits with the
126 * selected mask and shift them to the register LSB
127 * (shift mask on register position bit 0).
128 * @param __BITS__ Bits in register 32 bits
129 * @param __MASK__ Mask in register 32 bits
130 * @retval Bits in register 32 bits
131 */
132 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
133 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
134
135 /**
136 * @brief Driver macro reserved for internal use: set a pointer to
137 * a register from a register basis from which an offset
138 * is applied.
139 * @param __REG__ Register basis from which the offset is applied.
140 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
141 * @retval Pointer to register address
142 */
143 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
144 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
145
146 /**
147 * @}
148 */
149
150
151 /* Exported types ------------------------------------------------------------*/
152 #if defined(USE_FULL_LL_DRIVER)
153 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
154 * @{
155 */
156
157 /**
158 * @brief Structure definition of some features of DAC instance.
159 */
160 typedef struct
161 {
162 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
163 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
164
165 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
166
167 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
168 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
169
170 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
171
172 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
173 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
174 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
175 @note If waveform automatic generation mode is disabled, this parameter is discarded.
176
177 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
178
179 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
180 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
181
182 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
183
184 } LL_DAC_InitTypeDef;
185
186 /**
187 * @}
188 */
189 #endif /* USE_FULL_LL_DRIVER */
190
191 /* Exported constants --------------------------------------------------------*/
192 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
193 * @{
194 */
195
196 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
197 * @brief Flags defines which can be used with LL_DAC_ReadReg function
198 * @{
199 */
200 /* DAC channel 1 flags */
201 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
202
203 #if defined(DAC_CHANNEL2_SUPPORT)
204 /* DAC channel 2 flags */
205 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
206 #endif /* DAC_CHANNEL2_SUPPORT */
207 /**
208 * @}
209 */
210
211 /** @defgroup DAC_LL_EC_IT DAC interruptions
212 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
213 * @{
214 */
215 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
216 #if defined(DAC_CHANNEL2_SUPPORT)
217 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
218 #endif /* DAC_CHANNEL2_SUPPORT */
219 /**
220 * @}
221 */
222
223 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
224 * @{
225 */
226 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
227 #if defined(DAC_CHANNEL2_SUPPORT)
228 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
229 #endif /* DAC_CHANNEL2_SUPPORT */
230 /**
231 * @}
232 */
233
234 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
235 * @{
236 */
237 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
238 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
239 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
240 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
241 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
242 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
243 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
244 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
245 /**
246 * @}
247 */
248
249 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
250 * @{
251 */
252 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
253 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
254 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
255 /**
256 * @}
257 */
258
259 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
260 * @{
261 */
262 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
263 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
264 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
265 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
266 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
267 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
268 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
269 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
270 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
271 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
272 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
274 /**
275 * @}
276 */
277
278 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
279 * @{
280 */
281 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
282 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
283 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
284 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
285 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
286 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
287 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
288 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
289 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
290 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
291 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
292 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
293 /**
294 * @}
295 */
296
297 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
298 * @{
299 */
300 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
301 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
302 /**
303 * @}
304 */
305
306
307 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
308 * @{
309 */
310 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
311 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
312 /**
313 * @}
314 */
315
316 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
317 * @{
318 */
319 /* List of DAC registers intended to be used (most commonly) with */
320 /* DMA transfer. */
321 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
322 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
323 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
324 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
325 /**
326 * @}
327 */
328
329 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
330 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
331 * not timeout values.
332 * For details on delays values, refer to descriptions in source code
333 * above each literal definition.
334 * @{
335 */
336
337 /* Delay for DAC channel voltage settling time from DAC channel startup */
338 /* (transition from disable to enable). */
339 /* Note: DAC channel startup time depends on board application environment: */
340 /* impedance connected to DAC channel output. */
341 /* The delay below is specified under conditions: */
342 /* - voltage maximum transition (lowest to highest value) */
343 /* - until voltage reaches final value +-1LSB */
344 /* - DAC channel output buffer enabled */
345 /* - load impedance of 5kOhm (min), 50pF (max) */
346 /* Literal set to maximum value (refer to device datasheet, */
347 /* parameter "tWAKEUP"). */
348 /* Unit: us */
349 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
350
351 /* Delay for DAC channel voltage settling time. */
352 /* Note: DAC channel startup time depends on board application environment: */
353 /* impedance connected to DAC channel output. */
354 /* The delay below is specified under conditions: */
355 /* - voltage maximum transition (lowest to highest value) */
356 /* - until voltage reaches final value +-1LSB */
357 /* - DAC channel output buffer enabled */
358 /* - load impedance of 5kOhm min, 50pF max */
359 /* Literal set to maximum value (refer to device datasheet, */
360 /* parameter "tSETTLING"). */
361 /* Unit: us */
362 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
363 /**
364 * @}
365 */
366
367 /**
368 * @}
369 */
370
371 /* Exported macro ------------------------------------------------------------*/
372 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
373 * @{
374 */
375
376 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
377 * @{
378 */
379
380 /**
381 * @brief Write a value in DAC register
382 * @param __INSTANCE__ DAC Instance
383 * @param __REG__ Register to be written
384 * @param __VALUE__ Value to be written in the register
385 * @retval None
386 */
387 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
388
389 /**
390 * @brief Read a value in DAC register
391 * @param __INSTANCE__ DAC Instance
392 * @param __REG__ Register to be read
393 * @retval Register value
394 */
395 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
396
397 /**
398 * @}
399 */
400
401 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
402 * @{
403 */
404
405 /**
406 * @brief Helper macro to get DAC channel number in decimal format
407 * from literals LL_DAC_CHANNEL_x.
408 * Example:
409 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
410 * will return decimal number "1".
411 * @note The input can be a value from functions where a channel
412 * number is returned.
413 * @param __CHANNEL__ This parameter can be one of the following values:
414 * @arg @ref LL_DAC_CHANNEL_1
415 * @arg @ref LL_DAC_CHANNEL_2 (1)
416 *
417 * (1) On this STM32 serie, parameter not available on all devices.
418 * Refer to device datasheet for channels availability.
419 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
420 */
421 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
422 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
423
424 /**
425 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
426 * from number in decimal format.
427 * Example:
428 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
429 * will return a data equivalent to "LL_DAC_CHANNEL_1".
430 * @note If the input parameter does not correspond to a DAC channel,
431 * this macro returns value '0'.
432 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
433 * @retval Returned value can be one of the following values:
434 * @arg @ref LL_DAC_CHANNEL_1
435 * @arg @ref LL_DAC_CHANNEL_2 (1)
436 *
437 * (1) On this STM32 serie, parameter not available on all devices.
438 * Refer to device datasheet for channels availability.
439 */
440 #if defined(DAC_CHANNEL2_SUPPORT)
441 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
442 (((__DECIMAL_NB__) == 1U) \
443 ? ( \
444 LL_DAC_CHANNEL_1 \
445 ) \
446 : \
447 (((__DECIMAL_NB__) == 2U) \
448 ? ( \
449 LL_DAC_CHANNEL_2 \
450 ) \
451 : \
452 ( \
453 0 \
454 ) \
455 ) \
456 )
457 #else
458 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
459 (((__DECIMAL_NB__) == 1U) \
460 ? ( \
461 LL_DAC_CHANNEL_1 \
462 ) \
463 : \
464 ( \
465 0 \
466 ) \
467 )
468 #endif /* DAC_CHANNEL2_SUPPORT */
469
470 /**
471 * @brief Helper macro to define the DAC conversion data full-scale digital
472 * value corresponding to the selected DAC resolution.
473 * @note DAC conversion data full-scale corresponds to voltage range
474 * determined by analog voltage references Vref+ and Vref-
475 * (refer to reference manual).
476 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
477 * @arg @ref LL_DAC_RESOLUTION_12B
478 * @arg @ref LL_DAC_RESOLUTION_8B
479 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
480 */
481 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
482 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
483
484 /**
485 * @brief Helper macro to calculate the DAC conversion data (unit: digital
486 * value) corresponding to a voltage (unit: mVolt).
487 * @note This helper macro is intended to provide input data in voltage
488 * rather than digital value,
489 * to be used with LL DAC functions such as
490 * @ref LL_DAC_ConvertData12RightAligned().
491 * @note Analog reference voltage (Vref+) must be either known from
492 * user board environment or can be calculated using ADC measurement
493 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
494 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
495 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
496 * (unit: mVolt).
497 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
498 * @arg @ref LL_DAC_RESOLUTION_12B
499 * @arg @ref LL_DAC_RESOLUTION_8B
500 * @retval DAC conversion data (unit: digital value)
501 */
502 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
503 __DAC_VOLTAGE__,\
504 __DAC_RESOLUTION__) \
505 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
506 / (__VREFANALOG_VOLTAGE__) \
507 )
508
509 /**
510 * @}
511 */
512
513 /**
514 * @}
515 */
516
517
518 /* Exported functions --------------------------------------------------------*/
519 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
520 * @{
521 */
522 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
523 * @{
524 */
525
526 /**
527 * @brief Set the conversion trigger source for the selected DAC channel.
528 * @note For conversion trigger source to be effective, DAC trigger
529 * must be enabled using function @ref LL_DAC_EnableTrigger().
530 * @note To set conversion trigger source, DAC channel must be disabled.
531 * Otherwise, the setting is discarded.
532 * @note Availability of parameters of trigger sources from timer
533 * depends on timers availability on the selected device.
534 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
535 * CR TSEL2 LL_DAC_SetTriggerSource
536 * @param DACx DAC instance
537 * @param DAC_Channel This parameter can be one of the following values:
538 * @arg @ref LL_DAC_CHANNEL_1
539 * @arg @ref LL_DAC_CHANNEL_2 (1)
540 *
541 * (1) On this STM32 serie, parameter not available on all devices.
542 * Refer to device datasheet for channels availability.
543 * @param TriggerSource This parameter can be one of the following values:
544 * @arg @ref LL_DAC_TRIG_SOFTWARE
545 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
546 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
547 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
548 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
549 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
550 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
551 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
552 * @retval None
553 */
554 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
555 {
556 MODIFY_REG(DACx->CR,
557 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
558 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
559 }
560
561 /**
562 * @brief Get the conversion trigger source for the selected DAC channel.
563 * @note For conversion trigger source to be effective, DAC trigger
564 * must be enabled using function @ref LL_DAC_EnableTrigger().
565 * @note Availability of parameters of trigger sources from timer
566 * depends on timers availability on the selected device.
567 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
568 * CR TSEL2 LL_DAC_GetTriggerSource
569 * @param DACx DAC instance
570 * @param DAC_Channel This parameter can be one of the following values:
571 * @arg @ref LL_DAC_CHANNEL_1
572 * @arg @ref LL_DAC_CHANNEL_2 (1)
573 *
574 * (1) On this STM32 serie, parameter not available on all devices.
575 * Refer to device datasheet for channels availability.
576 * @retval Returned value can be one of the following values:
577 * @arg @ref LL_DAC_TRIG_SOFTWARE
578 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
579 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
580 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
581 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
582 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
583 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
584 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
585 */
586 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
587 {
588 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
589 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
590 );
591 }
592
593 /**
594 * @brief Set the waveform automatic generation mode
595 * for the selected DAC channel.
596 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
597 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
598 * @param DACx DAC instance
599 * @param DAC_Channel This parameter can be one of the following values:
600 * @arg @ref LL_DAC_CHANNEL_1
601 * @arg @ref LL_DAC_CHANNEL_2 (1)
602 *
603 * (1) On this STM32 serie, parameter not available on all devices.
604 * Refer to device datasheet for channels availability.
605 * @param WaveAutoGeneration This parameter can be one of the following values:
606 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
607 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
608 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
609 * @retval None
610 */
611 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
612 {
613 MODIFY_REG(DACx->CR,
614 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
615 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
616 }
617
618 /**
619 * @brief Get the waveform automatic generation mode
620 * for the selected DAC channel.
621 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
622 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
623 * @param DACx DAC instance
624 * @param DAC_Channel This parameter can be one of the following values:
625 * @arg @ref LL_DAC_CHANNEL_1
626 * @arg @ref LL_DAC_CHANNEL_2 (1)
627 *
628 * (1) On this STM32 serie, parameter not available on all devices.
629 * Refer to device datasheet for channels availability.
630 * @retval Returned value can be one of the following values:
631 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
632 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
633 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
634 */
635 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
636 {
637 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
638 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
639 );
640 }
641
642 /**
643 * @brief Set the noise waveform generation for the selected DAC channel:
644 * Noise mode and parameters LFSR (linear feedback shift register).
645 * @note For wave generation to be effective, DAC channel
646 * wave generation mode must be enabled using
647 * function @ref LL_DAC_SetWaveAutoGeneration().
648 * @note This setting can be set when the selected DAC channel is disabled
649 * (otherwise, the setting operation is ignored).
650 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
651 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
652 * @param DACx DAC instance
653 * @param DAC_Channel This parameter can be one of the following values:
654 * @arg @ref LL_DAC_CHANNEL_1
655 * @arg @ref LL_DAC_CHANNEL_2 (1)
656 *
657 * (1) On this STM32 serie, parameter not available on all devices.
658 * Refer to device datasheet for channels availability.
659 * @param NoiseLFSRMask This parameter can be one of the following values:
660 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
661 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
662 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
663 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
664 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
665 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
666 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
667 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
668 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
669 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
670 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
671 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
672 * @retval None
673 */
674 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
675 {
676 MODIFY_REG(DACx->CR,
677 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
678 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
679 }
680
681 /**
682 * @brief Set the noise waveform generation for the selected DAC channel:
683 * Noise mode and parameters LFSR (linear feedback shift register).
684 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
685 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
686 * @param DACx DAC instance
687 * @param DAC_Channel This parameter can be one of the following values:
688 * @arg @ref LL_DAC_CHANNEL_1
689 * @arg @ref LL_DAC_CHANNEL_2 (1)
690 *
691 * (1) On this STM32 serie, parameter not available on all devices.
692 * Refer to device datasheet for channels availability.
693 * @retval Returned value can be one of the following values:
694 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
695 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
696 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
697 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
698 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
699 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
700 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
701 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
702 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
703 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
704 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
705 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
706 */
707 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
708 {
709 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
710 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
711 );
712 }
713
714 /**
715 * @brief Set the triangle waveform generation for the selected DAC channel:
716 * triangle mode and amplitude.
717 * @note For wave generation to be effective, DAC channel
718 * wave generation mode must be enabled using
719 * function @ref LL_DAC_SetWaveAutoGeneration().
720 * @note This setting can be set when the selected DAC channel is disabled
721 * (otherwise, the setting operation is ignored).
722 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
723 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
724 * @param DACx DAC instance
725 * @param DAC_Channel This parameter can be one of the following values:
726 * @arg @ref LL_DAC_CHANNEL_1
727 * @arg @ref LL_DAC_CHANNEL_2 (1)
728 *
729 * (1) On this STM32 serie, parameter not available on all devices.
730 * Refer to device datasheet for channels availability.
731 * @param TriangleAmplitude This parameter can be one of the following values:
732 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
733 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
734 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
735 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
736 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
737 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
738 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
739 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
740 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
741 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
742 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
743 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
744 * @retval None
745 */
746 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
747 {
748 MODIFY_REG(DACx->CR,
749 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
750 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
751 }
752
753 /**
754 * @brief Set the triangle waveform generation for the selected DAC channel:
755 * triangle mode and amplitude.
756 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
757 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
758 * @param DACx DAC instance
759 * @param DAC_Channel This parameter can be one of the following values:
760 * @arg @ref LL_DAC_CHANNEL_1
761 * @arg @ref LL_DAC_CHANNEL_2 (1)
762 *
763 * (1) On this STM32 serie, parameter not available on all devices.
764 * Refer to device datasheet for channels availability.
765 * @retval Returned value can be one of the following values:
766 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
767 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
768 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
769 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
770 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
771 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
772 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
773 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
774 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
775 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
776 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
777 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
778 */
779 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
780 {
781 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
782 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
783 );
784 }
785
786 /**
787 * @brief Set the output buffer for the selected DAC channel.
788 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
789 * CR BOFF2 LL_DAC_SetOutputBuffer
790 * @param DACx DAC instance
791 * @param DAC_Channel This parameter can be one of the following values:
792 * @arg @ref LL_DAC_CHANNEL_1
793 * @arg @ref LL_DAC_CHANNEL_2 (1)
794 *
795 * (1) On this STM32 serie, parameter not available on all devices.
796 * Refer to device datasheet for channels availability.
797 * @param OutputBuffer This parameter can be one of the following values:
798 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
799 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
800 * @retval None
801 */
802 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
803 {
804 MODIFY_REG(DACx->CR,
805 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
806 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
807 }
808
809 /**
810 * @brief Get the output buffer state for the selected DAC channel.
811 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
812 * CR BOFF2 LL_DAC_GetOutputBuffer
813 * @param DACx DAC instance
814 * @param DAC_Channel This parameter can be one of the following values:
815 * @arg @ref LL_DAC_CHANNEL_1
816 * @arg @ref LL_DAC_CHANNEL_2 (1)
817 *
818 * (1) On this STM32 serie, parameter not available on all devices.
819 * Refer to device datasheet for channels availability.
820 * @retval Returned value can be one of the following values:
821 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
822 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
823 */
824 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
825 {
826 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
827 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
828 );
829 }
830
831 /**
832 * @}
833 */
834
835 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
836 * @{
837 */
838
839 /**
840 * @brief Enable DAC DMA transfer request of the selected channel.
841 * @note To configure DMA source address (peripheral address),
842 * use function @ref LL_DAC_DMA_GetRegAddr().
843 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
844 * CR DMAEN2 LL_DAC_EnableDMAReq
845 * @param DACx DAC instance
846 * @param DAC_Channel This parameter can be one of the following values:
847 * @arg @ref LL_DAC_CHANNEL_1
848 * @arg @ref LL_DAC_CHANNEL_2 (1)
849 *
850 * (1) On this STM32 serie, parameter not available on all devices.
851 * Refer to device datasheet for channels availability.
852 * @retval None
853 */
854 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
855 {
856 SET_BIT(DACx->CR,
857 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
858 }
859
860 /**
861 * @brief Disable DAC DMA transfer request of the selected channel.
862 * @note To configure DMA source address (peripheral address),
863 * use function @ref LL_DAC_DMA_GetRegAddr().
864 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
865 * CR DMAEN2 LL_DAC_DisableDMAReq
866 * @param DACx DAC instance
867 * @param DAC_Channel This parameter can be one of the following values:
868 * @arg @ref LL_DAC_CHANNEL_1
869 * @arg @ref LL_DAC_CHANNEL_2 (1)
870 *
871 * (1) On this STM32 serie, parameter not available on all devices.
872 * Refer to device datasheet for channels availability.
873 * @retval None
874 */
875 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
876 {
877 CLEAR_BIT(DACx->CR,
878 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
879 }
880
881 /**
882 * @brief Get DAC DMA transfer request state of the selected channel.
883 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
884 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
885 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
886 * @param DACx DAC instance
887 * @param DAC_Channel This parameter can be one of the following values:
888 * @arg @ref LL_DAC_CHANNEL_1
889 * @arg @ref LL_DAC_CHANNEL_2 (1)
890 *
891 * (1) On this STM32 serie, parameter not available on all devices.
892 * Refer to device datasheet for channels availability.
893 * @retval State of bit (1 or 0).
894 */
895 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
896 {
897 return (READ_BIT(DACx->CR,
898 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
899 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
900 }
901
902 /**
903 * @brief Function to help to configure DMA transfer to DAC: retrieve the
904 * DAC register address from DAC instance and a list of DAC registers
905 * intended to be used (most commonly) with DMA transfer.
906 * @note These DAC registers are data holding registers:
907 * when DAC conversion is requested, DAC generates a DMA transfer
908 * request to have data available in DAC data holding registers.
909 * @note This macro is intended to be used with LL DMA driver, refer to
910 * function "LL_DMA_ConfigAddresses()".
911 * Example:
912 * LL_DMA_ConfigAddresses(DMA1,
913 * LL_DMA_CHANNEL_1,
914 * (uint32_t)&< array or variable >,
915 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
916 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
917 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
918 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
919 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
920 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
921 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
922 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
923 * @param DACx DAC instance
924 * @param DAC_Channel This parameter can be one of the following values:
925 * @arg @ref LL_DAC_CHANNEL_1
926 * @arg @ref LL_DAC_CHANNEL_2 (1)
927 *
928 * (1) On this STM32 serie, parameter not available on all devices.
929 * Refer to device datasheet for channels availability.
930 * @param Register This parameter can be one of the following values:
931 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
932 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
933 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
934 * @retval DAC register address
935 */
936 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
937 {
938 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
939 /* DAC channel selected. */
940 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
941 }
942 /**
943 * @}
944 */
945
946 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
947 * @{
948 */
949
950 /**
951 * @brief Enable DAC selected channel.
952 * @rmtoll CR EN1 LL_DAC_Enable\n
953 * CR EN2 LL_DAC_Enable
954 * @note After enable from off state, DAC channel requires a delay
955 * for output voltage to reach accuracy +/- 1 LSB.
956 * Refer to device datasheet, parameter "tWAKEUP".
957 * @param DACx DAC instance
958 * @param DAC_Channel This parameter can be one of the following values:
959 * @arg @ref LL_DAC_CHANNEL_1
960 * @arg @ref LL_DAC_CHANNEL_2 (1)
961 *
962 * (1) On this STM32 serie, parameter not available on all devices.
963 * Refer to device datasheet for channels availability.
964 * @retval None
965 */
966 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
967 {
968 SET_BIT(DACx->CR,
969 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
970 }
971
972 /**
973 * @brief Disable DAC selected channel.
974 * @rmtoll CR EN1 LL_DAC_Disable\n
975 * CR EN2 LL_DAC_Disable
976 * @param DACx DAC instance
977 * @param DAC_Channel This parameter can be one of the following values:
978 * @arg @ref LL_DAC_CHANNEL_1
979 * @arg @ref LL_DAC_CHANNEL_2 (1)
980 *
981 * (1) On this STM32 serie, parameter not available on all devices.
982 * Refer to device datasheet for channels availability.
983 * @retval None
984 */
985 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
986 {
987 CLEAR_BIT(DACx->CR,
988 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
989 }
990
991 /**
992 * @brief Get DAC enable state of the selected channel.
993 * (0: DAC channel is disabled, 1: DAC channel is enabled)
994 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
995 * CR EN2 LL_DAC_IsEnabled
996 * @param DACx DAC instance
997 * @param DAC_Channel This parameter can be one of the following values:
998 * @arg @ref LL_DAC_CHANNEL_1
999 * @arg @ref LL_DAC_CHANNEL_2 (1)
1000 *
1001 * (1) On this STM32 serie, parameter not available on all devices.
1002 * Refer to device datasheet for channels availability.
1003 * @retval State of bit (1 or 0).
1004 */
1005 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1006 {
1007 return (READ_BIT(DACx->CR,
1008 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1009 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1010 }
1011
1012 /**
1013 * @brief Enable DAC trigger of the selected channel.
1014 * @note - If DAC trigger is disabled, DAC conversion is performed
1015 * automatically once the data holding register is updated,
1016 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1017 * @ref LL_DAC_ConvertData12RightAligned(), ...
1018 * - If DAC trigger is enabled, DAC conversion is performed
1019 * only when a hardware of software trigger event is occurring.
1020 * Select trigger source using
1021 * function @ref LL_DAC_SetTriggerSource().
1022 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1023 * CR TEN2 LL_DAC_EnableTrigger
1024 * @param DACx DAC instance
1025 * @param DAC_Channel This parameter can be one of the following values:
1026 * @arg @ref LL_DAC_CHANNEL_1
1027 * @arg @ref LL_DAC_CHANNEL_2 (1)
1028 *
1029 * (1) On this STM32 serie, parameter not available on all devices.
1030 * Refer to device datasheet for channels availability.
1031 * @retval None
1032 */
1033 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1034 {
1035 SET_BIT(DACx->CR,
1036 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1037 }
1038
1039 /**
1040 * @brief Disable DAC trigger of the selected channel.
1041 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1042 * CR TEN2 LL_DAC_DisableTrigger
1043 * @param DACx DAC instance
1044 * @param DAC_Channel This parameter can be one of the following values:
1045 * @arg @ref LL_DAC_CHANNEL_1
1046 * @arg @ref LL_DAC_CHANNEL_2 (1)
1047 *
1048 * (1) On this STM32 serie, parameter not available on all devices.
1049 * Refer to device datasheet for channels availability.
1050 * @retval None
1051 */
1052 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1053 {
1054 CLEAR_BIT(DACx->CR,
1055 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1056 }
1057
1058 /**
1059 * @brief Get DAC trigger state of the selected channel.
1060 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1061 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1062 * CR TEN2 LL_DAC_IsTriggerEnabled
1063 * @param DACx DAC instance
1064 * @param DAC_Channel This parameter can be one of the following values:
1065 * @arg @ref LL_DAC_CHANNEL_1
1066 * @arg @ref LL_DAC_CHANNEL_2 (1)
1067 *
1068 * (1) On this STM32 serie, parameter not available on all devices.
1069 * Refer to device datasheet for channels availability.
1070 * @retval State of bit (1 or 0).
1071 */
1072 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1073 {
1074 return (READ_BIT(DACx->CR,
1075 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1076 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1077 }
1078
1079 /**
1080 * @brief Trig DAC conversion by software for the selected DAC channel.
1081 * @note Preliminarily, DAC trigger must be set to software trigger
1082 * using function @ref LL_DAC_SetTriggerSource()
1083 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1084 * and DAC trigger must be enabled using
1085 * function @ref LL_DAC_EnableTrigger().
1086 * @note For devices featuring DAC with 2 channels: this function
1087 * can perform a SW start of both DAC channels simultaneously.
1088 * Two channels can be selected as parameter.
1089 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1090 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1091 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1092 * @param DACx DAC instance
1093 * @param DAC_Channel This parameter can a combination of the following values:
1094 * @arg @ref LL_DAC_CHANNEL_1
1095 * @arg @ref LL_DAC_CHANNEL_2 (1)
1096 *
1097 * (1) On this STM32 serie, parameter not available on all devices.
1098 * Refer to device datasheet for channels availability.
1099 * @retval None
1100 */
1101 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1102 {
1103 SET_BIT(DACx->SWTRIGR,
1104 (DAC_Channel & DAC_SWTR_CHX_MASK));
1105 }
1106
1107 /**
1108 * @brief Set the data to be loaded in the data holding register
1109 * in format 12 bits left alignment (LSB aligned on bit 0),
1110 * for the selected DAC channel.
1111 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1112 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1113 * @param DACx DAC instance
1114 * @param DAC_Channel This parameter can be one of the following values:
1115 * @arg @ref LL_DAC_CHANNEL_1
1116 * @arg @ref LL_DAC_CHANNEL_2 (1)
1117 *
1118 * (1) On this STM32 serie, parameter not available on all devices.
1119 * Refer to device datasheet for channels availability.
1120 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1121 * @retval None
1122 */
1123 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1124 {
1125 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
1126
1127 MODIFY_REG(*preg,
1128 DAC_DHR12R1_DACC1DHR,
1129 Data);
1130 }
1131
1132 /**
1133 * @brief Set the data to be loaded in the data holding register
1134 * in format 12 bits left alignment (MSB aligned on bit 15),
1135 * for the selected DAC channel.
1136 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1137 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1138 * @param DACx DAC instance
1139 * @param DAC_Channel This parameter can be one of the following values:
1140 * @arg @ref LL_DAC_CHANNEL_1
1141 * @arg @ref LL_DAC_CHANNEL_2 (1)
1142 *
1143 * (1) On this STM32 serie, parameter not available on all devices.
1144 * Refer to device datasheet for channels availability.
1145 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1146 * @retval None
1147 */
1148 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1149 {
1150 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
1151
1152 MODIFY_REG(*preg,
1153 DAC_DHR12L1_DACC1DHR,
1154 Data);
1155 }
1156
1157 /**
1158 * @brief Set the data to be loaded in the data holding register
1159 * in format 8 bits left alignment (LSB aligned on bit 0),
1160 * for the selected DAC channel.
1161 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1162 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1163 * @param DACx DAC instance
1164 * @param DAC_Channel This parameter can be one of the following values:
1165 * @arg @ref LL_DAC_CHANNEL_1
1166 * @arg @ref LL_DAC_CHANNEL_2 (1)
1167 *
1168 * (1) On this STM32 serie, parameter not available on all devices.
1169 * Refer to device datasheet for channels availability.
1170 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1171 * @retval None
1172 */
1173 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1174 {
1175 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
1176
1177 MODIFY_REG(*preg,
1178 DAC_DHR8R1_DACC1DHR,
1179 Data);
1180 }
1181
1182 #if defined(DAC_CHANNEL2_SUPPORT)
1183 /**
1184 * @brief Set the data to be loaded in the data holding register
1185 * in format 12 bits left alignment (LSB aligned on bit 0),
1186 * for both DAC channels.
1187 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1188 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1189 * @param DACx DAC instance
1190 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1191 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1192 * @retval None
1193 */
1194 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1195 {
1196 MODIFY_REG(DACx->DHR12RD,
1197 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1198 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1199 }
1200
1201 /**
1202 * @brief Set the data to be loaded in the data holding register
1203 * in format 12 bits left alignment (MSB aligned on bit 15),
1204 * for both DAC channels.
1205 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1206 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1207 * @param DACx DAC instance
1208 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1209 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1210 * @retval None
1211 */
1212 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1213 {
1214 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1215 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1216 /* the 4 LSB must be taken into account for the shift value. */
1217 MODIFY_REG(DACx->DHR12LD,
1218 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1219 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1220 }
1221
1222 /**
1223 * @brief Set the data to be loaded in the data holding register
1224 * in format 8 bits left alignment (LSB aligned on bit 0),
1225 * for both DAC channels.
1226 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1227 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1228 * @param DACx DAC instance
1229 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1230 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1231 * @retval None
1232 */
1233 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1234 {
1235 MODIFY_REG(DACx->DHR8RD,
1236 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1237 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1238 }
1239
1240 #endif /* DAC_CHANNEL2_SUPPORT */
1241 /**
1242 * @brief Retrieve output data currently generated for the selected DAC channel.
1243 * @note Whatever alignment and resolution settings
1244 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1245 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1246 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1247 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1248 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1249 * @param DACx DAC instance
1250 * @param DAC_Channel This parameter can be one of the following values:
1251 * @arg @ref LL_DAC_CHANNEL_1
1252 * @arg @ref LL_DAC_CHANNEL_2 (1)
1253 *
1254 * (1) On this STM32 serie, parameter not available on all devices.
1255 * Refer to device datasheet for channels availability.
1256 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1257 */
1258 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1259 {
1260 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
1261
1262 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1263 }
1264
1265 /**
1266 * @}
1267 */
1268
1269 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1270 * @{
1271 */
1272 /**
1273 * @brief Get DAC underrun flag for DAC channel 1
1274 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1275 * @param DACx DAC instance
1276 * @retval State of bit (1 or 0).
1277 */
1278 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1279 {
1280 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1281 }
1282
1283 #if defined(DAC_CHANNEL2_SUPPORT)
1284 /**
1285 * @brief Get DAC underrun flag for DAC channel 2
1286 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1287 * @param DACx DAC instance
1288 * @retval State of bit (1 or 0).
1289 */
1290 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1291 {
1292 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1293 }
1294 #endif /* DAC_CHANNEL2_SUPPORT */
1295
1296 /**
1297 * @brief Clear DAC underrun flag for DAC channel 1
1298 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1299 * @param DACx DAC instance
1300 * @retval None
1301 */
1302 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1303 {
1304 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1305 }
1306
1307 #if defined(DAC_CHANNEL2_SUPPORT)
1308 /**
1309 * @brief Clear DAC underrun flag for DAC channel 2
1310 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1311 * @param DACx DAC instance
1312 * @retval None
1313 */
1314 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1315 {
1316 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1317 }
1318 #endif /* DAC_CHANNEL2_SUPPORT */
1319
1320 /**
1321 * @}
1322 */
1323
1324 /** @defgroup DAC_LL_EF_IT_Management IT management
1325 * @{
1326 */
1327
1328 /**
1329 * @brief Enable DMA underrun interrupt for DAC channel 1
1330 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1331 * @param DACx DAC instance
1332 * @retval None
1333 */
1334 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1335 {
1336 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1337 }
1338
1339 #if defined(DAC_CHANNEL2_SUPPORT)
1340 /**
1341 * @brief Enable DMA underrun interrupt for DAC channel 2
1342 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1343 * @param DACx DAC instance
1344 * @retval None
1345 */
1346 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1347 {
1348 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1349 }
1350 #endif /* DAC_CHANNEL2_SUPPORT */
1351
1352 /**
1353 * @brief Disable DMA underrun interrupt for DAC channel 1
1354 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1355 * @param DACx DAC instance
1356 * @retval None
1357 */
1358 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1359 {
1360 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1361 }
1362
1363 #if defined(DAC_CHANNEL2_SUPPORT)
1364 /**
1365 * @brief Disable DMA underrun interrupt for DAC channel 2
1366 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1367 * @param DACx DAC instance
1368 * @retval None
1369 */
1370 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1371 {
1372 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1373 }
1374 #endif /* DAC_CHANNEL2_SUPPORT */
1375
1376 /**
1377 * @brief Get DMA underrun interrupt for DAC channel 1
1378 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1379 * @param DACx DAC instance
1380 * @retval State of bit (1 or 0).
1381 */
1382 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1383 {
1384 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1385 }
1386
1387 #if defined(DAC_CHANNEL2_SUPPORT)
1388 /**
1389 * @brief Get DMA underrun interrupt for DAC channel 2
1390 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1391 * @param DACx DAC instance
1392 * @retval State of bit (1 or 0).
1393 */
1394 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1395 {
1396 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1397 }
1398 #endif /* DAC_CHANNEL2_SUPPORT */
1399
1400 /**
1401 * @}
1402 */
1403
1404 #if defined(USE_FULL_LL_DRIVER)
1405 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1406 * @{
1407 */
1408
1409 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1410 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1411 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1412
1413 /**
1414 * @}
1415 */
1416 #endif /* USE_FULL_LL_DRIVER */
1417
1418 /**
1419 * @}
1420 */
1421
1422 /**
1423 * @}
1424 */
1425
1426 #endif /* DAC */
1427
1428 /**
1429 * @}
1430 */
1431
1432 #ifdef __cplusplus
1433 }
1434 #endif
1435
1436 #endif /* __STM32F4xx_LL_DAC_H */
1437
1438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/