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Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_cortex.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of CORTEX LL module. | |
6 @verbatim | |
7 ============================================================================== | |
8 ##### How to use this driver ##### | |
9 ============================================================================== | |
10 [..] | |
11 The LL CORTEX driver contains a set of generic APIs that can be | |
12 used by user: | |
13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick | |
14 functions | |
15 (+) Low power mode configuration (SCB register of Cortex-MCU) | |
16 (+) MPU API to configure and enable regions | |
17 (MPU services provided only on some devices) | |
18 (+) API to access to MCU info (CPUID register) | |
19 (+) API to enable fault handler (SHCSR accesses) | |
20 | |
21 @endverbatim | |
22 ****************************************************************************** | |
23 * @attention | |
24 * | |
25 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
26 * | |
27 * Redistribution and use in source and binary forms, with or without modification, | |
28 * are permitted provided that the following conditions are met: | |
29 * 1. Redistributions of source code must retain the above copyright notice, | |
30 * this list of conditions and the following disclaimer. | |
31 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
32 * this list of conditions and the following disclaimer in the documentation | |
33 * and/or other materials provided with the distribution. | |
34 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
35 * may be used to endorse or promote products derived from this software | |
36 * without specific prior written permission. | |
37 * | |
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
39 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
41 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
44 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
45 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
46 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
48 * | |
49 ****************************************************************************** | |
50 */ | |
51 | |
52 /* Define to prevent recursive inclusion -------------------------------------*/ | |
53 #ifndef __STM32F4xx_LL_CORTEX_H | |
54 #define __STM32F4xx_LL_CORTEX_H | |
55 | |
56 #ifdef __cplusplus | |
57 extern "C" { | |
58 #endif | |
59 | |
60 /* Includes ------------------------------------------------------------------*/ | |
61 #include "stm32f4xx.h" | |
62 | |
63 /** @addtogroup STM32F4xx_LL_Driver | |
64 * @{ | |
65 */ | |
66 | |
67 /** @defgroup CORTEX_LL CORTEX | |
68 * @{ | |
69 */ | |
70 | |
71 /* Private types -------------------------------------------------------------*/ | |
72 /* Private variables ---------------------------------------------------------*/ | |
73 | |
74 /* Private constants ---------------------------------------------------------*/ | |
75 | |
76 /* Private macros ------------------------------------------------------------*/ | |
77 | |
78 /* Exported types ------------------------------------------------------------*/ | |
79 /* Exported constants --------------------------------------------------------*/ | |
80 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants | |
81 * @{ | |
82 */ | |
83 | |
84 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source | |
85 * @{ | |
86 */ | |
87 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ | |
88 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ | |
89 /** | |
90 * @} | |
91 */ | |
92 | |
93 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type | |
94 * @{ | |
95 */ | |
96 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ | |
97 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ | |
98 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ | |
99 /** | |
100 * @} | |
101 */ | |
102 | |
103 #if __MPU_PRESENT | |
104 | |
105 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control | |
106 * @{ | |
107 */ | |
108 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ | |
109 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ | |
110 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ | |
111 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ | |
112 /** | |
113 * @} | |
114 */ | |
115 | |
116 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number | |
117 * @{ | |
118 */ | |
119 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ | |
120 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ | |
121 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ | |
122 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ | |
123 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ | |
124 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ | |
125 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ | |
126 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ | |
127 /** | |
128 * @} | |
129 */ | |
130 | |
131 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size | |
132 * @{ | |
133 */ | |
134 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ | |
135 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ | |
136 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ | |
137 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ | |
138 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ | |
139 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ | |
140 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ | |
141 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ | |
142 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ | |
143 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ | |
144 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ | |
145 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ | |
146 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ | |
147 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ | |
148 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ | |
149 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ | |
150 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ | |
151 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ | |
152 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ | |
153 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ | |
154 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ | |
155 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ | |
156 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ | |
157 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ | |
158 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ | |
159 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ | |
160 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ | |
161 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ | |
162 /** | |
163 * @} | |
164 */ | |
165 | |
166 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges | |
167 * @{ | |
168 */ | |
169 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ | |
170 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ | |
171 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ | |
172 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ | |
173 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ | |
174 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ | |
175 /** | |
176 * @} | |
177 */ | |
178 | |
179 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level | |
180 * @{ | |
181 */ | |
182 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ | |
183 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ | |
184 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ | |
185 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ | |
186 /** | |
187 * @} | |
188 */ | |
189 | |
190 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access | |
191 * @{ | |
192 */ | |
193 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ | |
194 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ | |
195 /** | |
196 * @} | |
197 */ | |
198 | |
199 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access | |
200 * @{ | |
201 */ | |
202 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ | |
203 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ | |
204 /** | |
205 * @} | |
206 */ | |
207 | |
208 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access | |
209 * @{ | |
210 */ | |
211 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ | |
212 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ | |
213 /** | |
214 * @} | |
215 */ | |
216 | |
217 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access | |
218 * @{ | |
219 */ | |
220 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ | |
221 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ | |
222 /** | |
223 * @} | |
224 */ | |
225 #endif /* __MPU_PRESENT */ | |
226 /** | |
227 * @} | |
228 */ | |
229 | |
230 /* Exported macro ------------------------------------------------------------*/ | |
231 | |
232 /* Exported functions --------------------------------------------------------*/ | |
233 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions | |
234 * @{ | |
235 */ | |
236 | |
237 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK | |
238 * @{ | |
239 */ | |
240 | |
241 /** | |
242 * @brief This function checks if the Systick counter flag is active or not. | |
243 * @note It can be used in timeout function on application side. | |
244 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag | |
245 * @retval State of bit (1 or 0). | |
246 */ | |
247 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) | |
248 { | |
249 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); | |
250 } | |
251 | |
252 /** | |
253 * @brief Configures the SysTick clock source | |
254 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource | |
255 * @param Source This parameter can be one of the following values: | |
256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 | |
257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK | |
258 * @retval None | |
259 */ | |
260 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) | |
261 { | |
262 if (Source == LL_SYSTICK_CLKSOURCE_HCLK) | |
263 { | |
264 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); | |
265 } | |
266 else | |
267 { | |
268 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); | |
269 } | |
270 } | |
271 | |
272 /** | |
273 * @brief Get the SysTick clock source | |
274 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource | |
275 * @retval Returned value can be one of the following values: | |
276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 | |
277 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK | |
278 */ | |
279 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) | |
280 { | |
281 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); | |
282 } | |
283 | |
284 /** | |
285 * @brief Enable SysTick exception request | |
286 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT | |
287 * @retval None | |
288 */ | |
289 __STATIC_INLINE void LL_SYSTICK_EnableIT(void) | |
290 { | |
291 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); | |
292 } | |
293 | |
294 /** | |
295 * @brief Disable SysTick exception request | |
296 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT | |
297 * @retval None | |
298 */ | |
299 __STATIC_INLINE void LL_SYSTICK_DisableIT(void) | |
300 { | |
301 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); | |
302 } | |
303 | |
304 /** | |
305 * @brief Checks if the SYSTICK interrupt is enabled or disabled. | |
306 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT | |
307 * @retval State of bit (1 or 0). | |
308 */ | |
309 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) | |
310 { | |
311 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); | |
312 } | |
313 | |
314 /** | |
315 * @} | |
316 */ | |
317 | |
318 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE | |
319 * @{ | |
320 */ | |
321 | |
322 /** | |
323 * @brief Processor uses sleep as its low power mode | |
324 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep | |
325 * @retval None | |
326 */ | |
327 __STATIC_INLINE void LL_LPM_EnableSleep(void) | |
328 { | |
329 /* Clear SLEEPDEEP bit of Cortex System Control Register */ | |
330 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); | |
331 } | |
332 | |
333 /** | |
334 * @brief Processor uses deep sleep as its low power mode | |
335 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep | |
336 * @retval None | |
337 */ | |
338 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) | |
339 { | |
340 /* Set SLEEPDEEP bit of Cortex System Control Register */ | |
341 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); | |
342 } | |
343 | |
344 /** | |
345 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. | |
346 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an | |
347 * empty main application. | |
348 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit | |
349 * @retval None | |
350 */ | |
351 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) | |
352 { | |
353 /* Set SLEEPONEXIT bit of Cortex System Control Register */ | |
354 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); | |
355 } | |
356 | |
357 /** | |
358 * @brief Do not sleep when returning to Thread mode. | |
359 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit | |
360 * @retval None | |
361 */ | |
362 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) | |
363 { | |
364 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ | |
365 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); | |
366 } | |
367 | |
368 /** | |
369 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the | |
370 * processor. | |
371 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend | |
372 * @retval None | |
373 */ | |
374 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) | |
375 { | |
376 /* Set SEVEONPEND bit of Cortex System Control Register */ | |
377 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); | |
378 } | |
379 | |
380 /** | |
381 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are | |
382 * excluded | |
383 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend | |
384 * @retval None | |
385 */ | |
386 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) | |
387 { | |
388 /* Clear SEVEONPEND bit of Cortex System Control Register */ | |
389 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); | |
390 } | |
391 | |
392 /** | |
393 * @} | |
394 */ | |
395 | |
396 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER | |
397 * @{ | |
398 */ | |
399 | |
400 /** | |
401 * @brief Enable a fault in System handler control register (SHCSR) | |
402 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault | |
403 * @param Fault This parameter can be a combination of the following values: | |
404 * @arg @ref LL_HANDLER_FAULT_USG | |
405 * @arg @ref LL_HANDLER_FAULT_BUS | |
406 * @arg @ref LL_HANDLER_FAULT_MEM | |
407 * @retval None | |
408 */ | |
409 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) | |
410 { | |
411 /* Enable the system handler fault */ | |
412 SET_BIT(SCB->SHCSR, Fault); | |
413 } | |
414 | |
415 /** | |
416 * @brief Disable a fault in System handler control register (SHCSR) | |
417 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault | |
418 * @param Fault This parameter can be a combination of the following values: | |
419 * @arg @ref LL_HANDLER_FAULT_USG | |
420 * @arg @ref LL_HANDLER_FAULT_BUS | |
421 * @arg @ref LL_HANDLER_FAULT_MEM | |
422 * @retval None | |
423 */ | |
424 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) | |
425 { | |
426 /* Disable the system handler fault */ | |
427 CLEAR_BIT(SCB->SHCSR, Fault); | |
428 } | |
429 | |
430 /** | |
431 * @} | |
432 */ | |
433 | |
434 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO | |
435 * @{ | |
436 */ | |
437 | |
438 /** | |
439 * @brief Get Implementer code | |
440 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer | |
441 * @retval Value should be equal to 0x41 for ARM | |
442 */ | |
443 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) | |
444 { | |
445 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); | |
446 } | |
447 | |
448 /** | |
449 * @brief Get Variant number (The r value in the rnpn product revision identifier) | |
450 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant | |
451 * @retval Value between 0 and 255 (0x0: revision 0) | |
452 */ | |
453 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) | |
454 { | |
455 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); | |
456 } | |
457 | |
458 /** | |
459 * @brief Get Constant number | |
460 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant | |
461 * @retval Value should be equal to 0xF for Cortex-M4 devices | |
462 */ | |
463 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) | |
464 { | |
465 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); | |
466 } | |
467 | |
468 /** | |
469 * @brief Get Part number | |
470 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo | |
471 * @retval Value should be equal to 0xC24 for Cortex-M4 | |
472 */ | |
473 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) | |
474 { | |
475 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); | |
476 } | |
477 | |
478 /** | |
479 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) | |
480 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision | |
481 * @retval Value between 0 and 255 (0x1: patch 1) | |
482 */ | |
483 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) | |
484 { | |
485 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); | |
486 } | |
487 | |
488 /** | |
489 * @} | |
490 */ | |
491 | |
492 #if __MPU_PRESENT | |
493 /** @defgroup CORTEX_LL_EF_MPU MPU | |
494 * @{ | |
495 */ | |
496 | |
497 /** | |
498 * @brief Enable MPU with input options | |
499 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable | |
500 * @param Options This parameter can be one of the following values: | |
501 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE | |
502 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI | |
503 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT | |
504 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF | |
505 * @retval None | |
506 */ | |
507 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) | |
508 { | |
509 /* Enable the MPU*/ | |
510 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); | |
511 /* Ensure MPU settings take effects */ | |
512 __DSB(); | |
513 /* Sequence instruction fetches using update settings */ | |
514 __ISB(); | |
515 } | |
516 | |
517 /** | |
518 * @brief Disable MPU | |
519 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable | |
520 * @retval None | |
521 */ | |
522 __STATIC_INLINE void LL_MPU_Disable(void) | |
523 { | |
524 /* Make sure outstanding transfers are done */ | |
525 __DMB(); | |
526 /* Disable MPU*/ | |
527 WRITE_REG(MPU->CTRL, 0U); | |
528 } | |
529 | |
530 /** | |
531 * @brief Check if MPU is enabled or not | |
532 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled | |
533 * @retval State of bit (1 or 0). | |
534 */ | |
535 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) | |
536 { | |
537 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); | |
538 } | |
539 | |
540 /** | |
541 * @brief Enable a MPU region | |
542 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion | |
543 * @param Region This parameter can be one of the following values: | |
544 * @arg @ref LL_MPU_REGION_NUMBER0 | |
545 * @arg @ref LL_MPU_REGION_NUMBER1 | |
546 * @arg @ref LL_MPU_REGION_NUMBER2 | |
547 * @arg @ref LL_MPU_REGION_NUMBER3 | |
548 * @arg @ref LL_MPU_REGION_NUMBER4 | |
549 * @arg @ref LL_MPU_REGION_NUMBER5 | |
550 * @arg @ref LL_MPU_REGION_NUMBER6 | |
551 * @arg @ref LL_MPU_REGION_NUMBER7 | |
552 * @retval None | |
553 */ | |
554 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) | |
555 { | |
556 /* Set Region number */ | |
557 WRITE_REG(MPU->RNR, Region); | |
558 /* Enable the MPU region */ | |
559 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); | |
560 } | |
561 | |
562 /** | |
563 * @brief Configure and enable a region | |
564 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n | |
565 * MPU_RBAR REGION LL_MPU_ConfigRegion\n | |
566 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n | |
567 * MPU_RASR XN LL_MPU_ConfigRegion\n | |
568 * MPU_RASR AP LL_MPU_ConfigRegion\n | |
569 * MPU_RASR S LL_MPU_ConfigRegion\n | |
570 * MPU_RASR C LL_MPU_ConfigRegion\n | |
571 * MPU_RASR B LL_MPU_ConfigRegion\n | |
572 * MPU_RASR SIZE LL_MPU_ConfigRegion | |
573 * @param Region This parameter can be one of the following values: | |
574 * @arg @ref LL_MPU_REGION_NUMBER0 | |
575 * @arg @ref LL_MPU_REGION_NUMBER1 | |
576 * @arg @ref LL_MPU_REGION_NUMBER2 | |
577 * @arg @ref LL_MPU_REGION_NUMBER3 | |
578 * @arg @ref LL_MPU_REGION_NUMBER4 | |
579 * @arg @ref LL_MPU_REGION_NUMBER5 | |
580 * @arg @ref LL_MPU_REGION_NUMBER6 | |
581 * @arg @ref LL_MPU_REGION_NUMBER7 | |
582 * @param Address Value of region base address | |
583 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF | |
584 * @param Attributes This parameter can be a combination of the following values: | |
585 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B | |
586 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB | |
587 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB | |
588 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB | |
589 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB | |
590 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB | |
591 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS | |
592 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO | |
593 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 | |
594 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE | |
595 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE | |
596 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE | |
597 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE | |
598 * @retval None | |
599 */ | |
600 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) | |
601 { | |
602 /* Set Region number */ | |
603 WRITE_REG(MPU->RNR, Region); | |
604 /* Set base address */ | |
605 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); | |
606 /* Configure MPU */ | |
607 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); | |
608 } | |
609 | |
610 /** | |
611 * @brief Disable a region | |
612 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n | |
613 * MPU_RASR ENABLE LL_MPU_DisableRegion | |
614 * @param Region This parameter can be one of the following values: | |
615 * @arg @ref LL_MPU_REGION_NUMBER0 | |
616 * @arg @ref LL_MPU_REGION_NUMBER1 | |
617 * @arg @ref LL_MPU_REGION_NUMBER2 | |
618 * @arg @ref LL_MPU_REGION_NUMBER3 | |
619 * @arg @ref LL_MPU_REGION_NUMBER4 | |
620 * @arg @ref LL_MPU_REGION_NUMBER5 | |
621 * @arg @ref LL_MPU_REGION_NUMBER6 | |
622 * @arg @ref LL_MPU_REGION_NUMBER7 | |
623 * @retval None | |
624 */ | |
625 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) | |
626 { | |
627 /* Set Region number */ | |
628 WRITE_REG(MPU->RNR, Region); | |
629 /* Disable the MPU region */ | |
630 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); | |
631 } | |
632 | |
633 /** | |
634 * @} | |
635 */ | |
636 | |
637 #endif /* __MPU_PRESENT */ | |
638 /** | |
639 * @} | |
640 */ | |
641 | |
642 /** | |
643 * @} | |
644 */ | |
645 | |
646 /** | |
647 * @} | |
648 */ | |
649 | |
650 #ifdef __cplusplus | |
651 } | |
652 #endif | |
653 | |
654 #endif /* __STM32F4xx_LL_CORTEX_H */ | |
655 | |
656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |