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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_LL_ADC_H
38 #define __STM32F4xx_LL_ADC_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx.h"
46
47 /** @addtogroup STM32F4xx_LL_Driver
48 * @{
49 */
50
51 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
52
53 /** @defgroup ADC_LL ADC
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
62 * @{
63 */
64
65 /* Internal mask for ADC group regular sequencer: */
66 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
67 /* - sequencer register offset */
68 /* - sequencer rank bits position into the selected register */
69
70 /* Internal register offset for ADC group regular sequencer configuration */
71 /* (offset placed into a spare area of literal definition) */
72 #define ADC_SQR1_REGOFFSET 0x00000000U
73 #define ADC_SQR2_REGOFFSET 0x00000100U
74 #define ADC_SQR3_REGOFFSET 0x00000200U
75 #define ADC_SQR4_REGOFFSET 0x00000300U
76
77 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
78 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
79
80 /* Definition of ADC group regular sequencer bits information to be inserted */
81 /* into ADC group regular sequencer ranks literals definition. */
82 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
83 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
84 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
85 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
86 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
87 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
88 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
89 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
90 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
91 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
92 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
93 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
94 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
95 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
96 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
97 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
98
99 /* Internal mask for ADC group injected sequencer: */
100 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
101 /* - data register offset */
102 /* - offset register offset */
103 /* - sequencer rank bits position into the selected register */
104
105 /* Internal register offset for ADC group injected data register */
106 /* (offset placed into a spare area of literal definition) */
107 #define ADC_JDR1_REGOFFSET 0x00000000U
108 #define ADC_JDR2_REGOFFSET 0x00000100U
109 #define ADC_JDR3_REGOFFSET 0x00000200U
110 #define ADC_JDR4_REGOFFSET 0x00000300U
111
112 /* Internal register offset for ADC group injected offset configuration */
113 /* (offset placed into a spare area of literal definition) */
114 #define ADC_JOFR1_REGOFFSET 0x00000000U
115 #define ADC_JOFR2_REGOFFSET 0x00001000U
116 #define ADC_JOFR3_REGOFFSET 0x00002000U
117 #define ADC_JOFR4_REGOFFSET 0x00003000U
118
119 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
120 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
121 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
122
123 /* Internal mask for ADC group regular trigger: */
124 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
125 /* - regular trigger source */
126 /* - regular trigger edge */
127 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
128
129 /* Mask containing trigger source masks for each of possible */
130 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
131 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
132 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
133 ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \
134 ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \
135 ((ADC_CR2_EXTSEL) >> (4U * 3U)))
136
137 /* Mask containing trigger edge masks for each of possible */
138 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
139 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
140 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
141 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
142 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
143 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
144
145 /* Definition of ADC group regular trigger bits information. */
146 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
147 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
148
149
150
151 /* Internal mask for ADC group injected trigger: */
152 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
153 /* - injected trigger source */
154 /* - injected trigger edge */
155 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
156
157 /* Mask containing trigger source masks for each of possible */
158 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
159 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
160 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
161 ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \
162 ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \
163 ((ADC_CR2_JEXTSEL) >> (4U * 3U)))
164
165 /* Mask containing trigger edge masks for each of possible */
166 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
167 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
168 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
169 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
170 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
171 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
172
173 /* Definition of ADC group injected trigger bits information. */
174 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
175 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
176
177 /* Internal mask for ADC channel: */
178 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
179 /* - channel identifier defined by number */
180 /* - channel differentiation between external channels (connected to */
181 /* GPIO pins) and internal channels (connected to internal paths) */
182 /* - channel sampling time defined by SMPRx register offset */
183 /* and SMPx bits positions into SMPRx register */
184 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
185 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
186 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
187 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
188 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
189
190 /* Channel differentiation between external and internal channels */
191 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
192 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
193 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
194 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
195
196 /* Internal register offset for ADC channel sampling time configuration */
197 /* (offset placed into a spare area of literal definition) */
198 #define ADC_SMPR1_REGOFFSET 0x00000000U
199 #define ADC_SMPR2_REGOFFSET 0x02000000U
200 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
201
202 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
203 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
204
205 /* Definition of channels ID number information to be inserted into */
206 /* channels literals definition. */
207 #define ADC_CHANNEL_0_NUMBER 0x00000000U
208 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
209 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
210 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
211 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
212 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
213 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
214 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
215 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
216 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
217 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
218 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
219 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
220 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
221 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
222 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
223 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
224 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
225 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
226
227 /* Definition of channels sampling time information to be inserted into */
228 /* channels literals definition. */
229 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
230 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
231 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
232 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
233 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
234 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
235 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
236 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
237 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
238 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
239 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
240 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
241 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
242 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
243 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
244 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
245 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
246 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
247 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
248
249 /* Internal mask for ADC analog watchdog: */
250 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
251 /* (concatenation of multiple bits used in different analog watchdogs, */
252 /* (feature of several watchdogs not available on all STM32 families)). */
253 /* - analog watchdog 1: monitored channel defined by number, */
254 /* selection of ADC group (ADC groups regular and-or injected). */
255
256 /* Internal register offset for ADC analog watchdog channel configuration */
257 #define ADC_AWD_CR1_REGOFFSET 0x00000000U
258
259 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
260
261 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
262 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
263
264 /* Internal register offset for ADC analog watchdog threshold configuration */
265 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
266 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
267 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
268
269 /* ADC registers bits positions */
270 #define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
271 #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
272 /**
273 * @}
274 */
275
276
277 /* Private macros ------------------------------------------------------------*/
278 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
279 * @{
280 */
281
282 /**
283 * @brief Driver macro reserved for internal use: isolate bits with the
284 * selected mask and shift them to the register LSB
285 * (shift mask on register position bit 0).
286 * @param __BITS__ Bits in register 32 bits
287 * @param __MASK__ Mask in register 32 bits
288 * @retval Bits in register 32 bits
289 */
290 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
291 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
292
293 /**
294 * @brief Driver macro reserved for internal use: set a pointer to
295 * a register from a register basis from which an offset
296 * is applied.
297 * @param __REG__ Register basis from which the offset is applied.
298 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
299 * @retval Pointer to register address
300 */
301 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
302 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
303
304 /**
305 * @}
306 */
307
308
309 /* Exported types ------------------------------------------------------------*/
310 #if defined(USE_FULL_LL_DRIVER)
311 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
312 * @{
313 */
314
315 /**
316 * @brief Structure definition of some features of ADC common parameters
317 * and multimode
318 * (all ADC instances belonging to the same ADC common instance).
319 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
320 * is conditioned to ADC instances state (all ADC instances
321 * sharing the same ADC common instance):
322 * All ADC instances sharing the same ADC common instance must be
323 * disabled.
324 */
325 typedef struct
326 {
327 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
328 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
329
330 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
331
332 #if defined(ADC_MULTIMODE_SUPPORT)
333 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
334 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
335
336 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
337
338 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
339 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
340
341 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
342
343 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
344 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
345
346 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
347 #endif /* ADC_MULTIMODE_SUPPORT */
348
349 } LL_ADC_CommonInitTypeDef;
350
351 /**
352 * @brief Structure definition of some features of ADC instance.
353 * @note These parameters have an impact on ADC scope: ADC instance.
354 * Affects both group regular and group injected (availability
355 * of ADC group injected depends on STM32 families).
356 * Refer to corresponding unitary functions into
357 * @ref ADC_LL_EF_Configuration_ADC_Instance .
358 * @note The setting of these parameters by function @ref LL_ADC_Init()
359 * is conditioned to ADC state:
360 * ADC instance must be disabled.
361 * This condition is applied to all ADC features, for efficiency
362 * and compatibility over all STM32 families. However, the different
363 * features can be set under different ADC state conditions
364 * (setting possible with ADC enabled without conversion on going,
365 * ADC enabled with conversion on going, ...)
366 * Each feature can be updated afterwards with a unitary function
367 * and potentially with ADC in a different state than disabled,
368 * refer to description of each function for setting
369 * conditioned to ADC state.
370 */
371 typedef struct
372 {
373 uint32_t Resolution; /*!< Set ADC resolution.
374 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
375
376 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
377
378 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
379 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
380
381 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
382
383 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
384 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
385
386 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
387
388 } LL_ADC_InitTypeDef;
389
390 /**
391 * @brief Structure definition of some features of ADC group regular.
392 * @note These parameters have an impact on ADC scope: ADC group regular.
393 * Refer to corresponding unitary functions into
394 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
395 * (functions with prefix "REG").
396 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
397 * is conditioned to ADC state:
398 * ADC instance must be disabled.
399 * This condition is applied to all ADC features, for efficiency
400 * and compatibility over all STM32 families. However, the different
401 * features can be set under different ADC state conditions
402 * (setting possible with ADC enabled without conversion on going,
403 * ADC enabled with conversion on going, ...)
404 * Each feature can be updated afterwards with a unitary function
405 * and potentially with ADC in a different state than disabled,
406 * refer to description of each function for setting
407 * conditioned to ADC state.
408 */
409 typedef struct
410 {
411 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
412 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
413 @note On this STM32 serie, setting of external trigger edge is performed
414 using function @ref LL_ADC_REG_StartConversionExtTrig().
415
416 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
417
418 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
419 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
420 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
421
422 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
423
424 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
425 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
426 @note This parameter has an effect only if group regular sequencer is enabled
427 (scan length of 2 ranks or more).
428
429 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
430
431 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
432 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
433 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
434
435 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
436
437 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
438 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
439
440 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
441
442 } LL_ADC_REG_InitTypeDef;
443
444 /**
445 * @brief Structure definition of some features of ADC group injected.
446 * @note These parameters have an impact on ADC scope: ADC group injected.
447 * Refer to corresponding unitary functions into
448 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
449 * (functions with prefix "INJ").
450 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
451 * is conditioned to ADC state:
452 * ADC instance must be disabled.
453 * This condition is applied to all ADC features, for efficiency
454 * and compatibility over all STM32 families. However, the different
455 * features can be set under different ADC state conditions
456 * (setting possible with ADC enabled without conversion on going,
457 * ADC enabled with conversion on going, ...)
458 * Each feature can be updated afterwards with a unitary function
459 * and potentially with ADC in a different state than disabled,
460 * refer to description of each function for setting
461 * conditioned to ADC state.
462 */
463 typedef struct
464 {
465 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
466 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
467 @note On this STM32 serie, setting of external trigger edge is performed
468 using function @ref LL_ADC_INJ_StartConversionExtTrig().
469
470 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
471
472 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
473 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
474 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
475
476 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
477
478 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
479 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
480 @note This parameter has an effect only if group injected sequencer is enabled
481 (scan length of 2 ranks or more).
482
483 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
484
485 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
486 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
487 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
488
489 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
490
491 } LL_ADC_INJ_InitTypeDef;
492
493 /**
494 * @}
495 */
496 #endif /* USE_FULL_LL_DRIVER */
497
498 /* Exported constants --------------------------------------------------------*/
499 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
500 * @{
501 */
502
503 /** @defgroup ADC_LL_EC_FLAG ADC flags
504 * @brief Flags defines which can be used with LL_ADC_ReadReg function
505 * @{
506 */
507 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
508 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
509 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
510 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
511 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
512 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
513 #if defined(ADC_MULTIMODE_SUPPORT)
514 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
515 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
516 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
517 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
518 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
519 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
520 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
521 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
522 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
523 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
524 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
525 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
526 #endif
527 /**
528 * @}
529 */
530
531 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
532 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
533 * @{
534 */
535 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
536 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
537 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
538 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
539 /**
540 * @}
541 */
542
543 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
544 * @{
545 */
546 /* List of ADC registers intended to be used (most commonly) with */
547 /* DMA transfer. */
548 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
549 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
550 #if defined(ADC_MULTIMODE_SUPPORT)
551 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
552 #endif
553 /**
554 * @}
555 */
556
557 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
558 * @{
559 */
560 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
561 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
562 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
563 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
564 /**
565 * @}
566 */
567
568 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
569 * @{
570 */
571 /* Note: Other measurement paths to internal channels may be available */
572 /* (connections to other peripherals). */
573 /* If they are not listed below, they do not require any specific */
574 /* path enable. In this case, Access to measurement path is done */
575 /* only by selecting the corresponding ADC internal channel. */
576 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
577 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
578 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
579 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
580 /**
581 * @}
582 */
583
584 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
585 * @{
586 */
587 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
588 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
589 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
590 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
591 /**
592 * @}
593 */
594
595 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
596 * @{
597 */
598 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
599 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
600 /**
601 * @}
602 */
603
604 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
605 * @{
606 */
607 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
608 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
609 /**
610 * @}
611 */
612
613 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
614 * @{
615 */
616 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
617 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
618 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
619 /**
620 * @}
621 */
622
623 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
624 * @{
625 */
626 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
627 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
628 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
629 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
630 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
631 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
632 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
633 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
634 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
635 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
636 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
637 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
638 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
639 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
640 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
641 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
642 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
643 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
644 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
645 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */
646 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */
647 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
648 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */
649 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
650 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
651 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
652 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
653 /**
654 * @}
655 */
656
657 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
658 * @{
659 */
660 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */
661 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
662 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
663 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
664 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
665 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
666 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
667 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
668 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
669 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
670 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
671 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
672 #define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
673 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
674 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
675 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
676 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
677 /**
678 * @}
679 */
680
681 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
682 * @{
683 */
684 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
685 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
686 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
687 /**
688 * @}
689 */
690
691 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
692 * @{
693 */
694 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
695 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
696 /**
697 * @}
698 */
699
700 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
701 * @{
702 */
703 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
704 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
705 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
706 /**
707 * @}
708 */
709
710 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
711 * @{
712 */
713 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */
714 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
715 /**
716 * @}
717 */
718
719 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
720 * @{
721 */
722 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
723 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
724 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
725 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
726 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
727 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
728 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
729 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
730 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
731 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
732 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
733 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
734 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
735 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
736 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
737 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
738 /**
739 * @}
740 */
741
742 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
743 * @{
744 */
745 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
746 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
747 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
748 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
749 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
750 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
751 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
752 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
753 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
754 /**
755 * @}
756 */
757
758 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
759 * @{
760 */
761 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
762 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
763 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
764 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
765 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
766 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
767 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
768 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
769 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
770 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
771 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
772 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
773 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
774 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
775 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
776 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
777 /**
778 * @}
779 */
780
781 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
782 * @{
783 */
784 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */
785 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
786 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
787 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
788 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
789 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
790 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
791 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
792 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
793 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
794 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
795 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
796 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
797 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
798 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
799 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
800 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
801 /**
802 * @}
803 */
804
805 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
806 * @{
807 */
808 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
809 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
810 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
811 /**
812 * @}
813 */
814
815 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
816 * @{
817 */
818 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
819 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
820 /**
821 * @}
822 */
823
824
825 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
826 * @{
827 */
828 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
829 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
830 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
831 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
832 /**
833 * @}
834 */
835
836 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
837 * @{
838 */
839 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
840 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
841 /**
842 * @}
843 */
844
845 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
846 * @{
847 */
848 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
849 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
850 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
851 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
852 /**
853 * @}
854 */
855
856 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
857 * @{
858 */
859 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */
860 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
861 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
862 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
863 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
864 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
865 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
866 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
867 /**
868 * @}
869 */
870
871 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
872 * @{
873 */
874 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
875 /**
876 * @}
877 */
878
879 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
880 * @{
881 */
882 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
883 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
884 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
885 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
886 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
887 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
888 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
889 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
890 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
891 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
892 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
893 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
894 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
895 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
896 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
897 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
898 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
899 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
900 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
901 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
902 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
903 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
904 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
905 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
906 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
907 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
908 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
909 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
910 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
911 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
912 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
913 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
914 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
915 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
916 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
917 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
918 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
919 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
920 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
921 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
922 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
923 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
924 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
925 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
926 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
927 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
928 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
929 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
930 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
931 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
932 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
933 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
934 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
935 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
936 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
937 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
938 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
939 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
940 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
941 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
942 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
943 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
944 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
945 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
946 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
947 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
948 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
949 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
950 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
951 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
952 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
953 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
954 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
955 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
956 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
957 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
958 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
959 /**
960 * @}
961 */
962
963 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
964 * @{
965 */
966 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
967 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
968 /**
969 * @}
970 */
971
972 #if defined(ADC_MULTIMODE_SUPPORT)
973 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
974 * @{
975 */
976 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
977 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
978 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
979 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
980 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
981 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
982 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
983 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
984 #if defined(ADC3)
985 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
986 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
987 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
988 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
989 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
990 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
991 #endif
992 /**
993 * @}
994 */
995
996 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
997 * @{
998 */
999 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1000 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
1001 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
1002 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
1003 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
1004 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
1005 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
1006 /**
1007 * @}
1008 */
1009
1010 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1011 * @{
1012 */
1013 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
1014 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1015 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1016 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1017 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1018 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1019 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1020 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1021 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
1022 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
1023 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
1024 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
1025 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
1026 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
1027 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
1028 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
1029 /**
1030 * @}
1031 */
1032
1033 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1034 * @{
1035 */
1036 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1037 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1038 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1039 /**
1040 * @}
1041 */
1042
1043 #endif /* ADC_MULTIMODE_SUPPORT */
1044
1045
1046 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1047 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1048 * not timeout values.
1049 * For details on delays values, refer to descriptions in source code
1050 * above each literal definition.
1051 * @{
1052 */
1053
1054 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1055 /* not timeout values. */
1056 /* Timeout values for ADC operations are dependent to device clock */
1057 /* configuration (system clock versus ADC clock), */
1058 /* and therefore must be defined in user application. */
1059 /* Indications for estimation of ADC timeout delays, for this */
1060 /* STM32 serie: */
1061 /* - ADC enable time: maximum delay is 2us */
1062 /* (refer to device datasheet, parameter "tSTAB") */
1063 /* - ADC conversion time: duration depending on ADC clock and ADC */
1064 /* configuration. */
1065 /* (refer to device reference manual, section "Timing") */
1066
1067 /* Delay for internal voltage reference stabilization time. */
1068 /* Delay set to maximum value (refer to device datasheet, */
1069 /* parameter "tSTART"). */
1070 /* Unit: us */
1071 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1072
1073 /* Delay for temperature sensor stabilization time. */
1074 /* Literal set to maximum value (refer to device datasheet, */
1075 /* parameter "tSTART"). */
1076 /* Unit: us */
1077 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1078
1079 /**
1080 * @}
1081 */
1082
1083 /**
1084 * @}
1085 */
1086
1087
1088 /* Exported macro ------------------------------------------------------------*/
1089 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1090 * @{
1091 */
1092
1093 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1094 * @{
1095 */
1096
1097 /**
1098 * @brief Write a value in ADC register
1099 * @param __INSTANCE__ ADC Instance
1100 * @param __REG__ Register to be written
1101 * @param __VALUE__ Value to be written in the register
1102 * @retval None
1103 */
1104 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1105
1106 /**
1107 * @brief Read a value in ADC register
1108 * @param __INSTANCE__ ADC Instance
1109 * @param __REG__ Register to be read
1110 * @retval Register value
1111 */
1112 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1113 /**
1114 * @}
1115 */
1116
1117 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1118 * @{
1119 */
1120
1121 /**
1122 * @brief Helper macro to get ADC channel number in decimal format
1123 * from literals LL_ADC_CHANNEL_x.
1124 * @note Example:
1125 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1126 * will return decimal number "4".
1127 * @note The input can be a value from functions where a channel
1128 * number is returned, either defined with number
1129 * or with bitfield (only one bit must be set).
1130 * @param __CHANNEL__ This parameter can be one of the following values:
1131 * @arg @ref LL_ADC_CHANNEL_0
1132 * @arg @ref LL_ADC_CHANNEL_1
1133 * @arg @ref LL_ADC_CHANNEL_2
1134 * @arg @ref LL_ADC_CHANNEL_3
1135 * @arg @ref LL_ADC_CHANNEL_4
1136 * @arg @ref LL_ADC_CHANNEL_5
1137 * @arg @ref LL_ADC_CHANNEL_6
1138 * @arg @ref LL_ADC_CHANNEL_7
1139 * @arg @ref LL_ADC_CHANNEL_8
1140 * @arg @ref LL_ADC_CHANNEL_9
1141 * @arg @ref LL_ADC_CHANNEL_10
1142 * @arg @ref LL_ADC_CHANNEL_11
1143 * @arg @ref LL_ADC_CHANNEL_12
1144 * @arg @ref LL_ADC_CHANNEL_13
1145 * @arg @ref LL_ADC_CHANNEL_14
1146 * @arg @ref LL_ADC_CHANNEL_15
1147 * @arg @ref LL_ADC_CHANNEL_16
1148 * @arg @ref LL_ADC_CHANNEL_17
1149 * @arg @ref LL_ADC_CHANNEL_18
1150 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1151 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1152 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1153 *
1154 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1155 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1156 * @retval Value between Min_Data=0 and Max_Data=18
1157 */
1158 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1159 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1160
1161 /**
1162 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1163 * from number in decimal format.
1164 * @note Example:
1165 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1166 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1167 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1168 * @retval Returned value can be one of the following values:
1169 * @arg @ref LL_ADC_CHANNEL_0
1170 * @arg @ref LL_ADC_CHANNEL_1
1171 * @arg @ref LL_ADC_CHANNEL_2
1172 * @arg @ref LL_ADC_CHANNEL_3
1173 * @arg @ref LL_ADC_CHANNEL_4
1174 * @arg @ref LL_ADC_CHANNEL_5
1175 * @arg @ref LL_ADC_CHANNEL_6
1176 * @arg @ref LL_ADC_CHANNEL_7
1177 * @arg @ref LL_ADC_CHANNEL_8
1178 * @arg @ref LL_ADC_CHANNEL_9
1179 * @arg @ref LL_ADC_CHANNEL_10
1180 * @arg @ref LL_ADC_CHANNEL_11
1181 * @arg @ref LL_ADC_CHANNEL_12
1182 * @arg @ref LL_ADC_CHANNEL_13
1183 * @arg @ref LL_ADC_CHANNEL_14
1184 * @arg @ref LL_ADC_CHANNEL_15
1185 * @arg @ref LL_ADC_CHANNEL_16
1186 * @arg @ref LL_ADC_CHANNEL_17
1187 * @arg @ref LL_ADC_CHANNEL_18
1188 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1189 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1190 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1191 *
1192 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1193 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1194 * (1) For ADC channel read back from ADC register,
1195 * comparison with internal channel parameter to be done
1196 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1197 */
1198 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1199 (((__DECIMAL_NB__) <= 9U) \
1200 ? ( \
1201 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1202 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1203 ) \
1204 : \
1205 ( \
1206 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1207 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1208 ) \
1209 )
1210
1211 /**
1212 * @brief Helper macro to determine whether the selected channel
1213 * corresponds to literal definitions of driver.
1214 * @note The different literal definitions of ADC channels are:
1215 * - ADC internal channel:
1216 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1217 * - ADC external channel (channel connected to a GPIO pin):
1218 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1219 * @note The channel parameter must be a value defined from literal
1220 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1221 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1222 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1223 * must not be a value from functions where a channel number is
1224 * returned from ADC registers,
1225 * because internal and external channels share the same channel
1226 * number in ADC registers. The differentiation is made only with
1227 * parameters definitions of driver.
1228 * @param __CHANNEL__ This parameter can be one of the following values:
1229 * @arg @ref LL_ADC_CHANNEL_0
1230 * @arg @ref LL_ADC_CHANNEL_1
1231 * @arg @ref LL_ADC_CHANNEL_2
1232 * @arg @ref LL_ADC_CHANNEL_3
1233 * @arg @ref LL_ADC_CHANNEL_4
1234 * @arg @ref LL_ADC_CHANNEL_5
1235 * @arg @ref LL_ADC_CHANNEL_6
1236 * @arg @ref LL_ADC_CHANNEL_7
1237 * @arg @ref LL_ADC_CHANNEL_8
1238 * @arg @ref LL_ADC_CHANNEL_9
1239 * @arg @ref LL_ADC_CHANNEL_10
1240 * @arg @ref LL_ADC_CHANNEL_11
1241 * @arg @ref LL_ADC_CHANNEL_12
1242 * @arg @ref LL_ADC_CHANNEL_13
1243 * @arg @ref LL_ADC_CHANNEL_14
1244 * @arg @ref LL_ADC_CHANNEL_15
1245 * @arg @ref LL_ADC_CHANNEL_16
1246 * @arg @ref LL_ADC_CHANNEL_17
1247 * @arg @ref LL_ADC_CHANNEL_18
1248 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1249 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1250 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1251 *
1252 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1253 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1254 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1255 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1256 */
1257 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1258 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1259
1260 /**
1261 * @brief Helper macro to convert a channel defined from parameter
1262 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1263 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1264 * to its equivalent parameter definition of a ADC external channel
1265 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1266 * @note The channel parameter can be, additionally to a value
1267 * defined from parameter definition of a ADC internal channel
1268 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1269 * a value defined from parameter definition of
1270 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1271 * or a value from functions where a channel number is returned
1272 * from ADC registers.
1273 * @param __CHANNEL__ This parameter can be one of the following values:
1274 * @arg @ref LL_ADC_CHANNEL_0
1275 * @arg @ref LL_ADC_CHANNEL_1
1276 * @arg @ref LL_ADC_CHANNEL_2
1277 * @arg @ref LL_ADC_CHANNEL_3
1278 * @arg @ref LL_ADC_CHANNEL_4
1279 * @arg @ref LL_ADC_CHANNEL_5
1280 * @arg @ref LL_ADC_CHANNEL_6
1281 * @arg @ref LL_ADC_CHANNEL_7
1282 * @arg @ref LL_ADC_CHANNEL_8
1283 * @arg @ref LL_ADC_CHANNEL_9
1284 * @arg @ref LL_ADC_CHANNEL_10
1285 * @arg @ref LL_ADC_CHANNEL_11
1286 * @arg @ref LL_ADC_CHANNEL_12
1287 * @arg @ref LL_ADC_CHANNEL_13
1288 * @arg @ref LL_ADC_CHANNEL_14
1289 * @arg @ref LL_ADC_CHANNEL_15
1290 * @arg @ref LL_ADC_CHANNEL_16
1291 * @arg @ref LL_ADC_CHANNEL_17
1292 * @arg @ref LL_ADC_CHANNEL_18
1293 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1294 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1295 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1296 *
1297 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1298 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1299 * @retval Returned value can be one of the following values:
1300 * @arg @ref LL_ADC_CHANNEL_0
1301 * @arg @ref LL_ADC_CHANNEL_1
1302 * @arg @ref LL_ADC_CHANNEL_2
1303 * @arg @ref LL_ADC_CHANNEL_3
1304 * @arg @ref LL_ADC_CHANNEL_4
1305 * @arg @ref LL_ADC_CHANNEL_5
1306 * @arg @ref LL_ADC_CHANNEL_6
1307 * @arg @ref LL_ADC_CHANNEL_7
1308 * @arg @ref LL_ADC_CHANNEL_8
1309 * @arg @ref LL_ADC_CHANNEL_9
1310 * @arg @ref LL_ADC_CHANNEL_10
1311 * @arg @ref LL_ADC_CHANNEL_11
1312 * @arg @ref LL_ADC_CHANNEL_12
1313 * @arg @ref LL_ADC_CHANNEL_13
1314 * @arg @ref LL_ADC_CHANNEL_14
1315 * @arg @ref LL_ADC_CHANNEL_15
1316 * @arg @ref LL_ADC_CHANNEL_16
1317 * @arg @ref LL_ADC_CHANNEL_17
1318 * @arg @ref LL_ADC_CHANNEL_18
1319 */
1320 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1321 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1322
1323 /**
1324 * @brief Helper macro to determine whether the internal channel
1325 * selected is available on the ADC instance selected.
1326 * @note The channel parameter must be a value defined from parameter
1327 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1328 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1329 * must not be a value defined from parameter definition of
1330 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1331 * or a value from functions where a channel number is
1332 * returned from ADC registers,
1333 * because internal and external channels share the same channel
1334 * number in ADC registers. The differentiation is made only with
1335 * parameters definitions of driver.
1336 * @param __ADC_INSTANCE__ ADC instance
1337 * @param __CHANNEL__ This parameter can be one of the following values:
1338 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1339 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1340 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1341 *
1342 * (1) On STM32F4, parameter available only on ADC instance: ADC1.
1343 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1344 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1345 * Value "1" if the internal channel selected is available on the ADC instance selected.
1346 */
1347 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1348 ( \
1349 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1350 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1351 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1352 )
1353 /**
1354 * @brief Helper macro to define ADC analog watchdog parameter:
1355 * define a single channel to monitor with analog watchdog
1356 * from sequencer channel and groups definition.
1357 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1358 * Example:
1359 * LL_ADC_SetAnalogWDMonitChannels(
1360 * ADC1, LL_ADC_AWD1,
1361 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1362 * @param __CHANNEL__ This parameter can be one of the following values:
1363 * @arg @ref LL_ADC_CHANNEL_0
1364 * @arg @ref LL_ADC_CHANNEL_1
1365 * @arg @ref LL_ADC_CHANNEL_2
1366 * @arg @ref LL_ADC_CHANNEL_3
1367 * @arg @ref LL_ADC_CHANNEL_4
1368 * @arg @ref LL_ADC_CHANNEL_5
1369 * @arg @ref LL_ADC_CHANNEL_6
1370 * @arg @ref LL_ADC_CHANNEL_7
1371 * @arg @ref LL_ADC_CHANNEL_8
1372 * @arg @ref LL_ADC_CHANNEL_9
1373 * @arg @ref LL_ADC_CHANNEL_10
1374 * @arg @ref LL_ADC_CHANNEL_11
1375 * @arg @ref LL_ADC_CHANNEL_12
1376 * @arg @ref LL_ADC_CHANNEL_13
1377 * @arg @ref LL_ADC_CHANNEL_14
1378 * @arg @ref LL_ADC_CHANNEL_15
1379 * @arg @ref LL_ADC_CHANNEL_16
1380 * @arg @ref LL_ADC_CHANNEL_17
1381 * @arg @ref LL_ADC_CHANNEL_18
1382 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1383 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1384 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1385 *
1386 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1387 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1388 * (1) For ADC channel read back from ADC register,
1389 * comparison with internal channel parameter to be done
1390 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1391 * @param __GROUP__ This parameter can be one of the following values:
1392 * @arg @ref LL_ADC_GROUP_REGULAR
1393 * @arg @ref LL_ADC_GROUP_INJECTED
1394 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1395 * @retval Returned value can be one of the following values:
1396 * @arg @ref LL_ADC_AWD_DISABLE
1397 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1398 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1399 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1400 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1401 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
1402 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1403 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1404 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
1405 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1406 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1407 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
1408 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1409 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1410 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
1411 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1412 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1413 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
1414 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1415 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1416 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
1417 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1418 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1419 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
1420 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1421 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1422 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
1423 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1424 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1425 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
1426 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1427 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1428 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
1429 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1430 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1431 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
1432 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1433 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1434 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
1435 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1436 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1437 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
1438 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1439 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1440 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
1441 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1442 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1443 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
1444 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1445 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1446 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
1447 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1448 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1449 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
1450 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1451 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1452 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
1453 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1454 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1455 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
1456 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1457 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
1458 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
1459 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1460 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
1461 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
1462 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
1463 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
1464 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
1465 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1466 *
1467 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1468 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1469 */
1470 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1471 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1472 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1473 : \
1474 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1475 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1476 : \
1477 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1478 )
1479
1480 /**
1481 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1482 * or low in function of ADC resolution, when ADC resolution is
1483 * different of 12 bits.
1484 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1485 * Example, with a ADC resolution of 8 bits, to set the value of
1486 * analog watchdog threshold high (on 8 bits):
1487 * LL_ADC_SetAnalogWDThresholds
1488 * (< ADCx param >,
1489 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1490 * );
1491 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1492 * @arg @ref LL_ADC_RESOLUTION_12B
1493 * @arg @ref LL_ADC_RESOLUTION_10B
1494 * @arg @ref LL_ADC_RESOLUTION_8B
1495 * @arg @ref LL_ADC_RESOLUTION_6B
1496 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1497 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1498 */
1499 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1500 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1501
1502 /**
1503 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1504 * or low in function of ADC resolution, when ADC resolution is
1505 * different of 12 bits.
1506 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1507 * Example, with a ADC resolution of 8 bits, to get the value of
1508 * analog watchdog threshold high (on 8 bits):
1509 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1510 * (LL_ADC_RESOLUTION_8B,
1511 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1512 * );
1513 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1514 * @arg @ref LL_ADC_RESOLUTION_12B
1515 * @arg @ref LL_ADC_RESOLUTION_10B
1516 * @arg @ref LL_ADC_RESOLUTION_8B
1517 * @arg @ref LL_ADC_RESOLUTION_6B
1518 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1519 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1520 */
1521 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1522 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1523
1524 #if defined(ADC_MULTIMODE_SUPPORT)
1525 /**
1526 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1527 * or ADC slave from raw value with both ADC conversion data concatenated.
1528 * @note This macro is intended to be used when multimode transfer by DMA
1529 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1530 * In this case the transferred data need to processed with this macro
1531 * to separate the conversion data of ADC master and ADC slave.
1532 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1533 * @arg @ref LL_ADC_MULTI_MASTER
1534 * @arg @ref LL_ADC_MULTI_SLAVE
1535 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1536 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1537 */
1538 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1539 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1540 #endif
1541
1542 /**
1543 * @brief Helper macro to select the ADC common instance
1544 * to which is belonging the selected ADC instance.
1545 * @note ADC common register instance can be used for:
1546 * - Set parameters common to several ADC instances
1547 * - Multimode (for devices with several ADC instances)
1548 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1549 * @param __ADCx__ ADC instance
1550 * @retval ADC common register instance
1551 */
1552 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1553 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1554 (ADC123_COMMON)
1555 #elif defined(ADC1) && defined(ADC2)
1556 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1557 (ADC12_COMMON)
1558 #else
1559 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1560 (ADC1_COMMON)
1561 #endif
1562
1563 /**
1564 * @brief Helper macro to check if all ADC instances sharing the same
1565 * ADC common instance are disabled.
1566 * @note This check is required by functions with setting conditioned to
1567 * ADC state:
1568 * All ADC instances of the ADC common group must be disabled.
1569 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1570 * @note On devices with only 1 ADC common instance, parameter of this macro
1571 * is useless and can be ignored (parameter kept for compatibility
1572 * with devices featuring several ADC common instances).
1573 * @param __ADCXY_COMMON__ ADC common instance
1574 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1575 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1576 * are disabled.
1577 * Value "1" if at least one ADC instance sharing the same ADC common instance
1578 * is enabled.
1579 */
1580 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1581 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1582 (LL_ADC_IsEnabled(ADC1) | \
1583 LL_ADC_IsEnabled(ADC2) | \
1584 LL_ADC_IsEnabled(ADC3) )
1585 #elif defined(ADC1) && defined(ADC2)
1586 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1587 (LL_ADC_IsEnabled(ADC1) | \
1588 LL_ADC_IsEnabled(ADC2) )
1589 #else
1590 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1591 (LL_ADC_IsEnabled(ADC1))
1592 #endif
1593
1594 /**
1595 * @brief Helper macro to define the ADC conversion data full-scale digital
1596 * value corresponding to the selected ADC resolution.
1597 * @note ADC conversion data full-scale corresponds to voltage range
1598 * determined by analog voltage references Vref+ and Vref-
1599 * (refer to reference manual).
1600 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1601 * @arg @ref LL_ADC_RESOLUTION_12B
1602 * @arg @ref LL_ADC_RESOLUTION_10B
1603 * @arg @ref LL_ADC_RESOLUTION_8B
1604 * @arg @ref LL_ADC_RESOLUTION_6B
1605 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1606 */
1607 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1608 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
1609
1610 /**
1611 * @brief Helper macro to convert the ADC conversion data from
1612 * a resolution to another resolution.
1613 * @param __DATA__ ADC conversion data to be converted
1614 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1615 * This parameter can be one of the following values:
1616 * @arg @ref LL_ADC_RESOLUTION_12B
1617 * @arg @ref LL_ADC_RESOLUTION_10B
1618 * @arg @ref LL_ADC_RESOLUTION_8B
1619 * @arg @ref LL_ADC_RESOLUTION_6B
1620 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1621 * This parameter can be one of the following values:
1622 * @arg @ref LL_ADC_RESOLUTION_12B
1623 * @arg @ref LL_ADC_RESOLUTION_10B
1624 * @arg @ref LL_ADC_RESOLUTION_8B
1625 * @arg @ref LL_ADC_RESOLUTION_6B
1626 * @retval ADC conversion data to the requested resolution
1627 */
1628 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1629 (((__DATA__) \
1630 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
1631 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
1632 )
1633
1634 /**
1635 * @brief Helper macro to calculate the voltage (unit: mVolt)
1636 * corresponding to a ADC conversion data (unit: digital value).
1637 * @note Analog reference voltage (Vref+) must be either known from
1638 * user board environment or can be calculated using ADC measurement
1639 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1640 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1641 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1642 * (unit: digital value).
1643 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1644 * @arg @ref LL_ADC_RESOLUTION_12B
1645 * @arg @ref LL_ADC_RESOLUTION_10B
1646 * @arg @ref LL_ADC_RESOLUTION_8B
1647 * @arg @ref LL_ADC_RESOLUTION_6B
1648 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1649 */
1650 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1651 __ADC_DATA__,\
1652 __ADC_RESOLUTION__) \
1653 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1654 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1655 )
1656
1657
1658 /**
1659 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1660 * from ADC conversion data of internal temperature sensor.
1661 * @note Computation is using temperature sensor typical values
1662 * (refer to device datasheet).
1663 * @note Calculation formula:
1664 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1665 * / Avg_Slope + CALx_TEMP
1666 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1667 * (unit: digital value)
1668 * Avg_Slope = temperature sensor slope
1669 * (unit: uV/Degree Celsius)
1670 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1671 * temperature CALx_TEMP (unit: mV)
1672 * Caution: Calculation relevancy under reserve the temperature sensor
1673 * of the current device has characteristics in line with
1674 * datasheet typical values.
1675 * If temperature sensor calibration values are available on
1676 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1677 * temperature calculation will be more accurate using
1678 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1679 * @note As calculation input, the analog reference voltage (Vref+) must be
1680 * defined as it impacts the ADC LSB equivalent voltage.
1681 * @note Analog reference voltage (Vref+) must be either known from
1682 * user board environment or can be calculated using ADC measurement
1683 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1684 * @note ADC measurement data must correspond to a resolution of 12bits
1685 * (full scale digital value 4095). If not the case, the data must be
1686 * preliminarily rescaled to an equivalent resolution of 12 bits.
1687 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).
1688 * On STM32F4, refer to device datasheet parameter "Avg_Slope".
1689 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).
1690 * On STM32F4, refer to device datasheet parameter "V25".
1691 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)
1692 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV)
1693 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value).
1694 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1695 * This parameter can be one of the following values:
1696 * @arg @ref LL_ADC_RESOLUTION_12B
1697 * @arg @ref LL_ADC_RESOLUTION_10B
1698 * @arg @ref LL_ADC_RESOLUTION_8B
1699 * @arg @ref LL_ADC_RESOLUTION_6B
1700 * @retval Temperature (unit: degree Celsius)
1701 */
1702 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1703 __TEMPSENSOR_TYP_CALX_V__,\
1704 __TEMPSENSOR_CALX_TEMP__,\
1705 __VREFANALOG_VOLTAGE__,\
1706 __TEMPSENSOR_ADC_DATA__,\
1707 __ADC_RESOLUTION__) \
1708 ((( ( \
1709 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1710 * 1000) \
1711 - \
1712 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1713 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1714 * 1000) \
1715 ) \
1716 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1717 ) + (__TEMPSENSOR_CALX_TEMP__) \
1718 )
1719
1720 /**
1721 * @}
1722 */
1723
1724 /**
1725 * @}
1726 */
1727
1728
1729 /* Exported functions --------------------------------------------------------*/
1730 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1731 * @{
1732 */
1733
1734 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1735 * @{
1736 */
1737 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1738 /* configuration of ADC instance, groups and multimode (if available): */
1739 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1740
1741 /**
1742 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1743 * ADC register address from ADC instance and a list of ADC registers
1744 * intended to be used (most commonly) with DMA transfer.
1745 * @note These ADC registers are data registers:
1746 * when ADC conversion data is available in ADC data registers,
1747 * ADC generates a DMA transfer request.
1748 * @note This macro is intended to be used with LL DMA driver, refer to
1749 * function "LL_DMA_ConfigAddresses()".
1750 * Example:
1751 * LL_DMA_ConfigAddresses(DMA1,
1752 * LL_DMA_CHANNEL_1,
1753 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1754 * (uint32_t)&< array or variable >,
1755 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1756 * @note For devices with several ADC: in multimode, some devices
1757 * use a different data register outside of ADC instance scope
1758 * (common data register). This macro manages this register difference,
1759 * only ADC instance has to be set as parameter.
1760 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
1761 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
1762 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
1763 * @param ADCx ADC instance
1764 * @param Register This parameter can be one of the following values:
1765 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1766 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
1767 *
1768 * (1) Available on devices with several ADC instances.
1769 * @retval ADC register address
1770 */
1771 #if defined(ADC_MULTIMODE_SUPPORT)
1772 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1773 {
1774 register uint32_t data_reg_addr = 0U;
1775
1776 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1777 {
1778 /* Retrieve address of register DR */
1779 data_reg_addr = (uint32_t)&(ADCx->DR);
1780 }
1781 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1782 {
1783 /* Retrieve address of register CDR */
1784 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
1785 }
1786
1787 return data_reg_addr;
1788 }
1789 #else
1790 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1791 {
1792 /* Retrieve address of register DR */
1793 return (uint32_t)&(ADCx->DR);
1794 }
1795 #endif
1796
1797 /**
1798 * @}
1799 */
1800
1801 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1802 * @{
1803 */
1804
1805 /**
1806 * @brief Set parameter common to several ADC: Clock source and prescaler.
1807 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
1808 * @param ADCxy_COMMON ADC common instance
1809 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1810 * @param CommonClock This parameter can be one of the following values:
1811 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1812 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1813 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1814 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1815 * @retval None
1816 */
1817 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1818 {
1819 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
1820 }
1821
1822 /**
1823 * @brief Get parameter common to several ADC: Clock source and prescaler.
1824 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
1825 * @param ADCxy_COMMON ADC common instance
1826 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1827 * @retval Returned value can be one of the following values:
1828 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1829 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1830 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1831 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1832 */
1833 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1834 {
1835 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
1836 }
1837
1838 /**
1839 * @brief Set parameter common to several ADC: measurement path to internal
1840 * channels (VrefInt, temperature sensor, ...).
1841 * @note One or several values can be selected.
1842 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1843 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1844 * @note Stabilization time of measurement path to internal channel:
1845 * After enabling internal paths, before starting ADC conversion,
1846 * a delay is required for internal voltage reference and
1847 * temperature sensor stabilization time.
1848 * Refer to device datasheet.
1849 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1850 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1851 * @note ADC internal channel sampling time constraint:
1852 * For ADC conversion of internal channels,
1853 * a sampling time minimum value is required.
1854 * Refer to device datasheet.
1855 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
1856 * CCR VBATE LL_ADC_SetCommonPathInternalCh
1857 * @param ADCxy_COMMON ADC common instance
1858 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1859 * @param PathInternal This parameter can be a combination of the following values:
1860 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1861 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1862 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1863 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1864 * @retval None
1865 */
1866 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1867 {
1868 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
1869 }
1870
1871 /**
1872 * @brief Get parameter common to several ADC: measurement path to internal
1873 * channels (VrefInt, temperature sensor, ...).
1874 * @note One or several values can be selected.
1875 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1876 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1877 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
1878 * CCR VBATE LL_ADC_GetCommonPathInternalCh
1879 * @param ADCxy_COMMON ADC common instance
1880 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1881 * @retval Returned value can be a combination of the following values:
1882 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1883 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1884 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1885 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1886 */
1887 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1888 {
1889 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
1890 }
1891
1892 /**
1893 * @}
1894 */
1895
1896 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1897 * @{
1898 */
1899
1900 /**
1901 * @brief Set ADC resolution.
1902 * Refer to reference manual for alignments formats
1903 * dependencies to ADC resolutions.
1904 * @rmtoll CR1 RES LL_ADC_SetResolution
1905 * @param ADCx ADC instance
1906 * @param Resolution This parameter can be one of the following values:
1907 * @arg @ref LL_ADC_RESOLUTION_12B
1908 * @arg @ref LL_ADC_RESOLUTION_10B
1909 * @arg @ref LL_ADC_RESOLUTION_8B
1910 * @arg @ref LL_ADC_RESOLUTION_6B
1911 * @retval None
1912 */
1913 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
1914 {
1915 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
1916 }
1917
1918 /**
1919 * @brief Get ADC resolution.
1920 * Refer to reference manual for alignments formats
1921 * dependencies to ADC resolutions.
1922 * @rmtoll CR1 RES LL_ADC_GetResolution
1923 * @param ADCx ADC instance
1924 * @retval Returned value can be one of the following values:
1925 * @arg @ref LL_ADC_RESOLUTION_12B
1926 * @arg @ref LL_ADC_RESOLUTION_10B
1927 * @arg @ref LL_ADC_RESOLUTION_8B
1928 * @arg @ref LL_ADC_RESOLUTION_6B
1929 */
1930 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
1931 {
1932 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
1933 }
1934
1935 /**
1936 * @brief Set ADC conversion data alignment.
1937 * @note Refer to reference manual for alignments formats
1938 * dependencies to ADC resolutions.
1939 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1940 * @param ADCx ADC instance
1941 * @param DataAlignment This parameter can be one of the following values:
1942 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1943 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1944 * @retval None
1945 */
1946 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
1947 {
1948 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
1949 }
1950
1951 /**
1952 * @brief Get ADC conversion data alignment.
1953 * @note Refer to reference manual for alignments formats
1954 * dependencies to ADC resolutions.
1955 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1956 * @param ADCx ADC instance
1957 * @retval Returned value can be one of the following values:
1958 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1959 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1960 */
1961 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
1962 {
1963 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
1964 }
1965
1966 /**
1967 * @brief Set ADC sequencers scan mode, for all ADC groups
1968 * (group regular, group injected).
1969 * @note According to sequencers scan mode :
1970 * - If disabled: ADC conversion is performed in unitary conversion
1971 * mode (one channel converted, that defined in rank 1).
1972 * Configuration of sequencers of all ADC groups
1973 * (sequencer scan length, ...) is discarded: equivalent to
1974 * scan length of 1 rank.
1975 * - If enabled: ADC conversions are performed in sequence conversions
1976 * mode, according to configuration of sequencers of
1977 * each ADC group (sequencer scan length, ...).
1978 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
1979 * and to function @ref LL_ADC_INJ_SetSequencerLength().
1980 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
1981 * @param ADCx ADC instance
1982 * @param ScanMode This parameter can be one of the following values:
1983 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
1984 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
1985 * @retval None
1986 */
1987 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
1988 {
1989 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
1990 }
1991
1992 /**
1993 * @brief Get ADC sequencers scan mode, for all ADC groups
1994 * (group regular, group injected).
1995 * @note According to sequencers scan mode :
1996 * - If disabled: ADC conversion is performed in unitary conversion
1997 * mode (one channel converted, that defined in rank 1).
1998 * Configuration of sequencers of all ADC groups
1999 * (sequencer scan length, ...) is discarded: equivalent to
2000 * scan length of 1 rank.
2001 * - If enabled: ADC conversions are performed in sequence conversions
2002 * mode, according to configuration of sequencers of
2003 * each ADC group (sequencer scan length, ...).
2004 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2005 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2006 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
2007 * @param ADCx ADC instance
2008 * @retval Returned value can be one of the following values:
2009 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2010 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2011 */
2012 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
2013 {
2014 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
2015 }
2016
2017 /**
2018 * @}
2019 */
2020
2021 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2022 * @{
2023 */
2024
2025 /**
2026 * @brief Set ADC group regular conversion trigger source:
2027 * internal (SW start) or from external IP (timer event,
2028 * external interrupt line).
2029 * @note On this STM32 serie, setting of external trigger edge is performed
2030 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2031 * @note Availability of parameters of trigger sources from timer
2032 * depends on timers availability on the selected device.
2033 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
2034 * CR2 EXTEN LL_ADC_REG_SetTriggerSource
2035 * @param ADCx ADC instance
2036 * @param TriggerSource This parameter can be one of the following values:
2037 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2038 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2039 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2040 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2041 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2042 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2043 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2044 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2045 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2046 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2047 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2048 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2049 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2050 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2051 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2052 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2053 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2054 * @retval None
2055 */
2056 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2057 {
2058 /* Note: On this STM32 serie, ADC group regular external trigger edge */
2059 /* is used to perform a ADC conversion start. */
2060 /* This function does not set external trigger edge. */
2061 /* This feature is set using function */
2062 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2063 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2064 }
2065
2066 /**
2067 * @brief Get ADC group regular conversion trigger source:
2068 * internal (SW start) or from external IP (timer event,
2069 * external interrupt line).
2070 * @note To determine whether group regular trigger source is
2071 * internal (SW start) or external, without detail
2072 * of which peripheral is selected as external trigger,
2073 * (equivalent to
2074 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2075 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2076 * @note Availability of parameters of trigger sources from timer
2077 * depends on timers availability on the selected device.
2078 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
2079 * CR2 EXTEN LL_ADC_REG_GetTriggerSource
2080 * @param ADCx ADC instance
2081 * @retval Returned value can be one of the following values:
2082 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2083 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2084 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2085 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2086 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2087 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2088 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2089 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2090 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2091 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2092 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2093 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2094 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2095 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2096 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2097 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2098 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2099 */
2100 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2101 {
2102 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2103
2104 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2105 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2106 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
2107
2108 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2109 /* to match with triggers literals definition. */
2110 return ((TriggerSource
2111 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2112 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2113 );
2114 }
2115
2116 /**
2117 * @brief Get ADC group regular conversion trigger source internal (SW start)
2118 or external.
2119 * @note In case of group regular trigger source set to external trigger,
2120 * to determine which peripheral is selected as external trigger,
2121 * use function @ref LL_ADC_REG_GetTriggerSource().
2122 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2123 * @param ADCx ADC instance
2124 * @retval Value "0" if trigger source external trigger
2125 * Value "1" if trigger source SW start.
2126 */
2127 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2128 {
2129 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2130 }
2131
2132 /**
2133 * @brief Get ADC group regular conversion trigger polarity.
2134 * @note Applicable only for trigger source set to external trigger.
2135 * @note On this STM32 serie, setting of external trigger edge is performed
2136 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2137 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
2138 * @param ADCx ADC instance
2139 * @retval Returned value can be one of the following values:
2140 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2141 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2142 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2143 */
2144 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2145 {
2146 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2147 }
2148
2149
2150 /**
2151 * @brief Set ADC group regular sequencer length and scan direction.
2152 * @note Description of ADC group regular sequencer features:
2153 * - For devices with sequencer fully configurable
2154 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2155 * sequencer length and each rank affectation to a channel
2156 * are configurable.
2157 * This function performs configuration of:
2158 * - Sequence length: Number of ranks in the scan sequence.
2159 * - Sequence direction: Unless specified in parameters, sequencer
2160 * scan direction is forward (from rank 1 to rank n).
2161 * Sequencer ranks are selected using
2162 * function "LL_ADC_REG_SetSequencerRanks()".
2163 * - For devices with sequencer not fully configurable
2164 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2165 * sequencer length and each rank affectation to a channel
2166 * are defined by channel number.
2167 * This function performs configuration of:
2168 * - Sequence length: Number of ranks in the scan sequence is
2169 * defined by number of channels set in the sequence,
2170 * rank of each channel is fixed by channel HW number.
2171 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2172 * - Sequence direction: Unless specified in parameters, sequencer
2173 * scan direction is forward (from lowest channel number to
2174 * highest channel number).
2175 * Sequencer ranks are selected using
2176 * function "LL_ADC_REG_SetSequencerChannels()".
2177 * @note On this STM32 serie, group regular sequencer configuration
2178 * is conditioned to ADC instance sequencer mode.
2179 * If ADC instance sequencer mode is disabled, sequencers of
2180 * all groups (group regular, group injected) can be configured
2181 * but their execution is disabled (limited to rank 1).
2182 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2183 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2184 * ADC conversion on only 1 channel.
2185 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2186 * @param ADCx ADC instance
2187 * @param SequencerNbRanks This parameter can be one of the following values:
2188 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2189 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2190 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2191 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2192 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2193 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2194 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2195 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2196 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2197 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2198 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2199 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2200 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2201 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2202 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2203 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2204 * @retval None
2205 */
2206 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2207 {
2208 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2209 }
2210
2211 /**
2212 * @brief Get ADC group regular sequencer length and scan direction.
2213 * @note Description of ADC group regular sequencer features:
2214 * - For devices with sequencer fully configurable
2215 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2216 * sequencer length and each rank affectation to a channel
2217 * are configurable.
2218 * This function retrieves:
2219 * - Sequence length: Number of ranks in the scan sequence.
2220 * - Sequence direction: Unless specified in parameters, sequencer
2221 * scan direction is forward (from rank 1 to rank n).
2222 * Sequencer ranks are selected using
2223 * function "LL_ADC_REG_SetSequencerRanks()".
2224 * - For devices with sequencer not fully configurable
2225 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2226 * sequencer length and each rank affectation to a channel
2227 * are defined by channel number.
2228 * This function retrieves:
2229 * - Sequence length: Number of ranks in the scan sequence is
2230 * defined by number of channels set in the sequence,
2231 * rank of each channel is fixed by channel HW number.
2232 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2233 * - Sequence direction: Unless specified in parameters, sequencer
2234 * scan direction is forward (from lowest channel number to
2235 * highest channel number).
2236 * Sequencer ranks are selected using
2237 * function "LL_ADC_REG_SetSequencerChannels()".
2238 * @note On this STM32 serie, group regular sequencer configuration
2239 * is conditioned to ADC instance sequencer mode.
2240 * If ADC instance sequencer mode is disabled, sequencers of
2241 * all groups (group regular, group injected) can be configured
2242 * but their execution is disabled (limited to rank 1).
2243 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2244 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2245 * ADC conversion on only 1 channel.
2246 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2247 * @param ADCx ADC instance
2248 * @retval Returned value can be one of the following values:
2249 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2250 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2251 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2252 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2253 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2254 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2255 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2256 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2257 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2258 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2259 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2260 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2261 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2262 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2263 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2264 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2265 */
2266 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2267 {
2268 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2269 }
2270
2271 /**
2272 * @brief Set ADC group regular sequencer discontinuous mode:
2273 * sequence subdivided and scan conversions interrupted every selected
2274 * number of ranks.
2275 * @note It is not possible to enable both ADC group regular
2276 * continuous mode and sequencer discontinuous mode.
2277 * @note It is not possible to enable both ADC auto-injected mode
2278 * and ADC group regular sequencer discontinuous mode.
2279 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2280 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2281 * @param ADCx ADC instance
2282 * @param SeqDiscont This parameter can be one of the following values:
2283 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2284 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2285 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2286 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2287 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2288 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2289 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2290 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2291 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2292 * @retval None
2293 */
2294 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2295 {
2296 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2297 }
2298
2299 /**
2300 * @brief Get ADC group regular sequencer discontinuous mode:
2301 * sequence subdivided and scan conversions interrupted every selected
2302 * number of ranks.
2303 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2304 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2305 * @param ADCx ADC instance
2306 * @retval Returned value can be one of the following values:
2307 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2308 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2309 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2310 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2311 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2312 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2313 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2314 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2315 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2316 */
2317 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2318 {
2319 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2320 }
2321
2322 /**
2323 * @brief Set ADC group regular sequence: channel on the selected
2324 * scan sequence rank.
2325 * @note This function performs configuration of:
2326 * - Channels ordering into each rank of scan sequence:
2327 * whatever channel can be placed into whatever rank.
2328 * @note On this STM32 serie, ADC group regular sequencer is
2329 * fully configurable: sequencer length and each rank
2330 * affectation to a channel are configurable.
2331 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2332 * @note Depending on devices and packages, some channels may not be available.
2333 * Refer to device datasheet for channels availability.
2334 * @note On this STM32 serie, to measure internal channels (VrefInt,
2335 * TempSensor, ...), measurement paths to internal channels must be
2336 * enabled separately.
2337 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2338 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
2339 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
2340 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
2341 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
2342 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
2343 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
2344 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
2345 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
2346 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
2347 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
2348 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
2349 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
2350 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
2351 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
2352 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
2353 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
2354 * @param ADCx ADC instance
2355 * @param Rank This parameter can be one of the following values:
2356 * @arg @ref LL_ADC_REG_RANK_1
2357 * @arg @ref LL_ADC_REG_RANK_2
2358 * @arg @ref LL_ADC_REG_RANK_3
2359 * @arg @ref LL_ADC_REG_RANK_4
2360 * @arg @ref LL_ADC_REG_RANK_5
2361 * @arg @ref LL_ADC_REG_RANK_6
2362 * @arg @ref LL_ADC_REG_RANK_7
2363 * @arg @ref LL_ADC_REG_RANK_8
2364 * @arg @ref LL_ADC_REG_RANK_9
2365 * @arg @ref LL_ADC_REG_RANK_10
2366 * @arg @ref LL_ADC_REG_RANK_11
2367 * @arg @ref LL_ADC_REG_RANK_12
2368 * @arg @ref LL_ADC_REG_RANK_13
2369 * @arg @ref LL_ADC_REG_RANK_14
2370 * @arg @ref LL_ADC_REG_RANK_15
2371 * @arg @ref LL_ADC_REG_RANK_16
2372 * @param Channel This parameter can be one of the following values:
2373 * @arg @ref LL_ADC_CHANNEL_0
2374 * @arg @ref LL_ADC_CHANNEL_1
2375 * @arg @ref LL_ADC_CHANNEL_2
2376 * @arg @ref LL_ADC_CHANNEL_3
2377 * @arg @ref LL_ADC_CHANNEL_4
2378 * @arg @ref LL_ADC_CHANNEL_5
2379 * @arg @ref LL_ADC_CHANNEL_6
2380 * @arg @ref LL_ADC_CHANNEL_7
2381 * @arg @ref LL_ADC_CHANNEL_8
2382 * @arg @ref LL_ADC_CHANNEL_9
2383 * @arg @ref LL_ADC_CHANNEL_10
2384 * @arg @ref LL_ADC_CHANNEL_11
2385 * @arg @ref LL_ADC_CHANNEL_12
2386 * @arg @ref LL_ADC_CHANNEL_13
2387 * @arg @ref LL_ADC_CHANNEL_14
2388 * @arg @ref LL_ADC_CHANNEL_15
2389 * @arg @ref LL_ADC_CHANNEL_16
2390 * @arg @ref LL_ADC_CHANNEL_17
2391 * @arg @ref LL_ADC_CHANNEL_18
2392 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2393 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2394 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2395 *
2396 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2397 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2398 * @retval None
2399 */
2400 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2401 {
2402 /* Set bits with content of parameter "Channel" with bits position */
2403 /* in register and register position depending on parameter "Rank". */
2404 /* Parameters "Rank" and "Channel" are used with masks because containing */
2405 /* other bits reserved for other purpose. */
2406 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2407
2408 MODIFY_REG(*preg,
2409 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2410 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2411 }
2412
2413 /**
2414 * @brief Get ADC group regular sequence: channel on the selected
2415 * scan sequence rank.
2416 * @note On this STM32 serie, ADC group regular sequencer is
2417 * fully configurable: sequencer length and each rank
2418 * affectation to a channel are configurable.
2419 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2420 * @note Depending on devices and packages, some channels may not be available.
2421 * Refer to device datasheet for channels availability.
2422 * @note Usage of the returned channel number:
2423 * - To reinject this channel into another function LL_ADC_xxx:
2424 * the returned channel number is only partly formatted on definition
2425 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2426 * with parts of literals LL_ADC_CHANNEL_x or using
2427 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2428 * Then the selected literal LL_ADC_CHANNEL_x can be used
2429 * as parameter for another function.
2430 * - To get the channel number in decimal format:
2431 * process the returned value with the helper macro
2432 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2433 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
2434 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
2435 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
2436 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
2437 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
2438 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
2439 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
2440 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
2441 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
2442 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
2443 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
2444 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
2445 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
2446 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
2447 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
2448 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
2449 * @param ADCx ADC instance
2450 * @param Rank This parameter can be one of the following values:
2451 * @arg @ref LL_ADC_REG_RANK_1
2452 * @arg @ref LL_ADC_REG_RANK_2
2453 * @arg @ref LL_ADC_REG_RANK_3
2454 * @arg @ref LL_ADC_REG_RANK_4
2455 * @arg @ref LL_ADC_REG_RANK_5
2456 * @arg @ref LL_ADC_REG_RANK_6
2457 * @arg @ref LL_ADC_REG_RANK_7
2458 * @arg @ref LL_ADC_REG_RANK_8
2459 * @arg @ref LL_ADC_REG_RANK_9
2460 * @arg @ref LL_ADC_REG_RANK_10
2461 * @arg @ref LL_ADC_REG_RANK_11
2462 * @arg @ref LL_ADC_REG_RANK_12
2463 * @arg @ref LL_ADC_REG_RANK_13
2464 * @arg @ref LL_ADC_REG_RANK_14
2465 * @arg @ref LL_ADC_REG_RANK_15
2466 * @arg @ref LL_ADC_REG_RANK_16
2467 * @retval Returned value can be one of the following values:
2468 * @arg @ref LL_ADC_CHANNEL_0
2469 * @arg @ref LL_ADC_CHANNEL_1
2470 * @arg @ref LL_ADC_CHANNEL_2
2471 * @arg @ref LL_ADC_CHANNEL_3
2472 * @arg @ref LL_ADC_CHANNEL_4
2473 * @arg @ref LL_ADC_CHANNEL_5
2474 * @arg @ref LL_ADC_CHANNEL_6
2475 * @arg @ref LL_ADC_CHANNEL_7
2476 * @arg @ref LL_ADC_CHANNEL_8
2477 * @arg @ref LL_ADC_CHANNEL_9
2478 * @arg @ref LL_ADC_CHANNEL_10
2479 * @arg @ref LL_ADC_CHANNEL_11
2480 * @arg @ref LL_ADC_CHANNEL_12
2481 * @arg @ref LL_ADC_CHANNEL_13
2482 * @arg @ref LL_ADC_CHANNEL_14
2483 * @arg @ref LL_ADC_CHANNEL_15
2484 * @arg @ref LL_ADC_CHANNEL_16
2485 * @arg @ref LL_ADC_CHANNEL_17
2486 * @arg @ref LL_ADC_CHANNEL_18
2487 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2488 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2489 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2490 *
2491 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2492 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
2493 * (1) For ADC channel read back from ADC register,
2494 * comparison with internal channel parameter to be done
2495 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2496 */
2497 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2498 {
2499 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2500
2501 return (uint32_t) (READ_BIT(*preg,
2502 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2503 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2504 );
2505 }
2506
2507 /**
2508 * @brief Set ADC continuous conversion mode on ADC group regular.
2509 * @note Description of ADC continuous conversion mode:
2510 * - single mode: one conversion per trigger
2511 * - continuous mode: after the first trigger, following
2512 * conversions launched successively automatically.
2513 * @note It is not possible to enable both ADC group regular
2514 * continuous mode and sequencer discontinuous mode.
2515 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
2516 * @param ADCx ADC instance
2517 * @param Continuous This parameter can be one of the following values:
2518 * @arg @ref LL_ADC_REG_CONV_SINGLE
2519 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2520 * @retval None
2521 */
2522 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2523 {
2524 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2525 }
2526
2527 /**
2528 * @brief Get ADC continuous conversion mode on ADC group regular.
2529 * @note Description of ADC continuous conversion mode:
2530 * - single mode: one conversion per trigger
2531 * - continuous mode: after the first trigger, following
2532 * conversions launched successively automatically.
2533 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
2534 * @param ADCx ADC instance
2535 * @retval Returned value can be one of the following values:
2536 * @arg @ref LL_ADC_REG_CONV_SINGLE
2537 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2538 */
2539 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2540 {
2541 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2542 }
2543
2544 /**
2545 * @brief Set ADC group regular conversion data transfer: no transfer or
2546 * transfer by DMA, and DMA requests mode.
2547 * @note If transfer by DMA selected, specifies the DMA requests
2548 * mode:
2549 * - Limited mode (One shot mode): DMA transfer requests are stopped
2550 * when number of DMA data transfers (number of
2551 * ADC conversions) is reached.
2552 * This ADC mode is intended to be used with DMA mode non-circular.
2553 * - Unlimited mode: DMA transfer requests are unlimited,
2554 * whatever number of DMA data transfers (number of
2555 * ADC conversions).
2556 * This ADC mode is intended to be used with DMA mode circular.
2557 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2558 * mode non-circular:
2559 * when DMA transfers size will be reached, DMA will stop transfers of
2560 * ADC conversions data ADC will raise an overrun error
2561 * (overrun flag and interruption if enabled).
2562 * @note For devices with several ADC instances: ADC multimode DMA
2563 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
2564 * @note To configure DMA source address (peripheral address),
2565 * use function @ref LL_ADC_DMA_GetRegAddr().
2566 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
2567 * CR2 DDS LL_ADC_REG_SetDMATransfer
2568 * @param ADCx ADC instance
2569 * @param DMATransfer This parameter can be one of the following values:
2570 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2571 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2572 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2573 * @retval None
2574 */
2575 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2576 {
2577 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
2578 }
2579
2580 /**
2581 * @brief Get ADC group regular conversion data transfer: no transfer or
2582 * transfer by DMA, and DMA requests mode.
2583 * @note If transfer by DMA selected, specifies the DMA requests
2584 * mode:
2585 * - Limited mode (One shot mode): DMA transfer requests are stopped
2586 * when number of DMA data transfers (number of
2587 * ADC conversions) is reached.
2588 * This ADC mode is intended to be used with DMA mode non-circular.
2589 * - Unlimited mode: DMA transfer requests are unlimited,
2590 * whatever number of DMA data transfers (number of
2591 * ADC conversions).
2592 * This ADC mode is intended to be used with DMA mode circular.
2593 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2594 * mode non-circular:
2595 * when DMA transfers size will be reached, DMA will stop transfers of
2596 * ADC conversions data ADC will raise an overrun error
2597 * (overrun flag and interruption if enabled).
2598 * @note For devices with several ADC instances: ADC multimode DMA
2599 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
2600 * @note To configure DMA source address (peripheral address),
2601 * use function @ref LL_ADC_DMA_GetRegAddr().
2602 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
2603 * CR2 DDS LL_ADC_REG_GetDMATransfer
2604 * @param ADCx ADC instance
2605 * @retval Returned value can be one of the following values:
2606 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2607 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2608 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2609 */
2610 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2611 {
2612 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
2613 }
2614
2615 /**
2616 * @brief Specify which ADC flag between EOC (end of unitary conversion)
2617 * or EOS (end of sequence conversions) is used to indicate
2618 * the end of conversion.
2619 * @note This feature is aimed to be set when using ADC with
2620 * programming model by polling or interruption
2621 * (programming model by DMA usually uses DMA interruptions
2622 * to indicate end of conversion and data transfer).
2623 * @note For ADC group injected, end of conversion (flag&IT) is raised
2624 * only at the end of the sequence.
2625 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
2626 * @param ADCx ADC instance
2627 * @param EocSelection This parameter can be one of the following values:
2628 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2629 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2630 * @retval None
2631 */
2632 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
2633 {
2634 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
2635 }
2636
2637 /**
2638 * @brief Get which ADC flag between EOC (end of unitary conversion)
2639 * or EOS (end of sequence conversions) is used to indicate
2640 * the end of conversion.
2641 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
2642 * @param ADCx ADC instance
2643 * @retval Returned value can be one of the following values:
2644 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2645 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2646 */
2647 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
2648 {
2649 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
2650 }
2651
2652 /**
2653 * @}
2654 */
2655
2656 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
2657 * @{
2658 */
2659
2660 /**
2661 * @brief Set ADC group injected conversion trigger source:
2662 * internal (SW start) or from external IP (timer event,
2663 * external interrupt line).
2664 * @note On this STM32 serie, setting of external trigger edge is performed
2665 * using function @ref LL_ADC_INJ_StartConversionExtTrig().
2666 * @note Availability of parameters of trigger sources from timer
2667 * depends on timers availability on the selected device.
2668 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
2669 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
2670 * @param ADCx ADC instance
2671 * @param TriggerSource This parameter can be one of the following values:
2672 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2673 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2674 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2675 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2676 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2677 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2678 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2679 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2680 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2681 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2682 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2683 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2684 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2685 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2686 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2687 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2688 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2689 * @retval None
2690 */
2691 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2692 {
2693 /* Note: On this STM32 serie, ADC group injected external trigger edge */
2694 /* is used to perform a ADC conversion start. */
2695 /* This function does not set external trigger edge. */
2696 /* This feature is set using function */
2697 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2698 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2699 }
2700
2701 /**
2702 * @brief Get ADC group injected conversion trigger source:
2703 * internal (SW start) or from external IP (timer event,
2704 * external interrupt line).
2705 * @note To determine whether group injected trigger source is
2706 * internal (SW start) or external, without detail
2707 * of which peripheral is selected as external trigger,
2708 * (equivalent to
2709 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
2710 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
2711 * @note Availability of parameters of trigger sources from timer
2712 * depends on timers availability on the selected device.
2713 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
2714 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
2715 * @param ADCx ADC instance
2716 * @retval Returned value can be one of the following values:
2717 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2718 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2719 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2720 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2721 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2722 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2723 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2724 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2725 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2726 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2727 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2728 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2729 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2730 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2731 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2732 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2733 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2734 */
2735 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
2736 {
2737 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
2738
2739 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2740 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
2741 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
2742
2743 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
2744 /* to match with triggers literals definition. */
2745 return ((TriggerSource
2746 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
2747 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
2748 );
2749 }
2750
2751 /**
2752 * @brief Get ADC group injected conversion trigger source internal (SW start)
2753 or external
2754 * @note In case of group injected trigger source set to external trigger,
2755 * to determine which peripheral is selected as external trigger,
2756 * use function @ref LL_ADC_INJ_GetTriggerSource.
2757 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
2758 * @param ADCx ADC instance
2759 * @retval Value "0" if trigger source external trigger
2760 * Value "1" if trigger source SW start.
2761 */
2762 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2763 {
2764 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
2765 }
2766
2767 /**
2768 * @brief Get ADC group injected conversion trigger polarity.
2769 * Applicable only for trigger source set to external trigger.
2770 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
2771 * @param ADCx ADC instance
2772 * @retval Returned value can be one of the following values:
2773 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
2774 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
2775 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
2776 */
2777 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
2778 {
2779 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
2780 }
2781
2782 /**
2783 * @brief Set ADC group injected sequencer length and scan direction.
2784 * @note This function performs configuration of:
2785 * - Sequence length: Number of ranks in the scan sequence.
2786 * - Sequence direction: Unless specified in parameters, sequencer
2787 * scan direction is forward (from rank 1 to rank n).
2788 * @note On this STM32 serie, group injected sequencer configuration
2789 * is conditioned to ADC instance sequencer mode.
2790 * If ADC instance sequencer mode is disabled, sequencers of
2791 * all groups (group regular, group injected) can be configured
2792 * but their execution is disabled (limited to rank 1).
2793 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2794 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2795 * ADC conversion on only 1 channel.
2796 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
2797 * @param ADCx ADC instance
2798 * @param SequencerNbRanks This parameter can be one of the following values:
2799 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2800 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2801 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2802 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2803 * @retval None
2804 */
2805 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2806 {
2807 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2808 }
2809
2810 /**
2811 * @brief Get ADC group injected sequencer length and scan direction.
2812 * @note This function retrieves:
2813 * - Sequence length: Number of ranks in the scan sequence.
2814 * - Sequence direction: Unless specified in parameters, sequencer
2815 * scan direction is forward (from rank 1 to rank n).
2816 * @note On this STM32 serie, group injected sequencer configuration
2817 * is conditioned to ADC instance sequencer mode.
2818 * If ADC instance sequencer mode is disabled, sequencers of
2819 * all groups (group regular, group injected) can be configured
2820 * but their execution is disabled (limited to rank 1).
2821 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2822 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2823 * ADC conversion on only 1 channel.
2824 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
2825 * @param ADCx ADC instance
2826 * @retval Returned value can be one of the following values:
2827 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2828 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2829 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2830 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2831 */
2832 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
2833 {
2834 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2835 }
2836
2837 /**
2838 * @brief Set ADC group injected sequencer discontinuous mode:
2839 * sequence subdivided and scan conversions interrupted every selected
2840 * number of ranks.
2841 * @note It is not possible to enable both ADC group injected
2842 * auto-injected mode and sequencer discontinuous mode.
2843 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
2844 * @param ADCx ADC instance
2845 * @param SeqDiscont This parameter can be one of the following values:
2846 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2847 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2848 * @retval None
2849 */
2850 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2851 {
2852 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2853 }
2854
2855 /**
2856 * @brief Get ADC group injected sequencer discontinuous mode:
2857 * sequence subdivided and scan conversions interrupted every selected
2858 * number of ranks.
2859 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
2860 * @param ADCx ADC instance
2861 * @retval Returned value can be one of the following values:
2862 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2863 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2864 */
2865 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
2866 {
2867 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2868 }
2869
2870 /**
2871 * @brief Set ADC group injected sequence: channel on the selected
2872 * sequence rank.
2873 * @note Depending on devices and packages, some channels may not be available.
2874 * Refer to device datasheet for channels availability.
2875 * @note On this STM32 serie, to measure internal channels (VrefInt,
2876 * TempSensor, ...), measurement paths to internal channels must be
2877 * enabled separately.
2878 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2879 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2880 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2881 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2882 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2883 * @param ADCx ADC instance
2884 * @param Rank This parameter can be one of the following values:
2885 * @arg @ref LL_ADC_INJ_RANK_1
2886 * @arg @ref LL_ADC_INJ_RANK_2
2887 * @arg @ref LL_ADC_INJ_RANK_3
2888 * @arg @ref LL_ADC_INJ_RANK_4
2889 * @param Channel This parameter can be one of the following values:
2890 * @arg @ref LL_ADC_CHANNEL_0
2891 * @arg @ref LL_ADC_CHANNEL_1
2892 * @arg @ref LL_ADC_CHANNEL_2
2893 * @arg @ref LL_ADC_CHANNEL_3
2894 * @arg @ref LL_ADC_CHANNEL_4
2895 * @arg @ref LL_ADC_CHANNEL_5
2896 * @arg @ref LL_ADC_CHANNEL_6
2897 * @arg @ref LL_ADC_CHANNEL_7
2898 * @arg @ref LL_ADC_CHANNEL_8
2899 * @arg @ref LL_ADC_CHANNEL_9
2900 * @arg @ref LL_ADC_CHANNEL_10
2901 * @arg @ref LL_ADC_CHANNEL_11
2902 * @arg @ref LL_ADC_CHANNEL_12
2903 * @arg @ref LL_ADC_CHANNEL_13
2904 * @arg @ref LL_ADC_CHANNEL_14
2905 * @arg @ref LL_ADC_CHANNEL_15
2906 * @arg @ref LL_ADC_CHANNEL_16
2907 * @arg @ref LL_ADC_CHANNEL_17
2908 * @arg @ref LL_ADC_CHANNEL_18
2909 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2910 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2911 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2912 *
2913 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2914 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2915 * @retval None
2916 */
2917 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2918 {
2919 /* Set bits with content of parameter "Channel" with bits position */
2920 /* in register depending on parameter "Rank". */
2921 /* Parameters "Rank" and "Channel" are used with masks because containing */
2922 /* other bits reserved for other purpose. */
2923 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2924
2925 MODIFY_REG(ADCx->JSQR,
2926 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
2927 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
2928 }
2929
2930 /**
2931 * @brief Get ADC group injected sequence: channel on the selected
2932 * sequence rank.
2933 * @note Depending on devices and packages, some channels may not be available.
2934 * Refer to device datasheet for channels availability.
2935 * @note Usage of the returned channel number:
2936 * - To reinject this channel into another function LL_ADC_xxx:
2937 * the returned channel number is only partly formatted on definition
2938 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2939 * with parts of literals LL_ADC_CHANNEL_x or using
2940 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2941 * Then the selected literal LL_ADC_CHANNEL_x can be used
2942 * as parameter for another function.
2943 * - To get the channel number in decimal format:
2944 * process the returned value with the helper macro
2945 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2946 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2947 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2948 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2949 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2950 * @param ADCx ADC instance
2951 * @param Rank This parameter can be one of the following values:
2952 * @arg @ref LL_ADC_INJ_RANK_1
2953 * @arg @ref LL_ADC_INJ_RANK_2
2954 * @arg @ref LL_ADC_INJ_RANK_3
2955 * @arg @ref LL_ADC_INJ_RANK_4
2956 * @retval Returned value can be one of the following values:
2957 * @arg @ref LL_ADC_CHANNEL_0
2958 * @arg @ref LL_ADC_CHANNEL_1
2959 * @arg @ref LL_ADC_CHANNEL_2
2960 * @arg @ref LL_ADC_CHANNEL_3
2961 * @arg @ref LL_ADC_CHANNEL_4
2962 * @arg @ref LL_ADC_CHANNEL_5
2963 * @arg @ref LL_ADC_CHANNEL_6
2964 * @arg @ref LL_ADC_CHANNEL_7
2965 * @arg @ref LL_ADC_CHANNEL_8
2966 * @arg @ref LL_ADC_CHANNEL_9
2967 * @arg @ref LL_ADC_CHANNEL_10
2968 * @arg @ref LL_ADC_CHANNEL_11
2969 * @arg @ref LL_ADC_CHANNEL_12
2970 * @arg @ref LL_ADC_CHANNEL_13
2971 * @arg @ref LL_ADC_CHANNEL_14
2972 * @arg @ref LL_ADC_CHANNEL_15
2973 * @arg @ref LL_ADC_CHANNEL_16
2974 * @arg @ref LL_ADC_CHANNEL_17
2975 * @arg @ref LL_ADC_CHANNEL_18
2976 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2977 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2978 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2979 *
2980 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2981 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
2982 * (1) For ADC channel read back from ADC register,
2983 * comparison with internal channel parameter to be done
2984 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2985 */
2986 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2987 {
2988 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2989
2990 return (uint32_t)(READ_BIT(ADCx->JSQR,
2991 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
2992 >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
2993 );
2994 }
2995
2996 /**
2997 * @brief Set ADC group injected conversion trigger:
2998 * independent or from ADC group regular.
2999 * @note This mode can be used to extend number of data registers
3000 * updated after one ADC conversion trigger and with data
3001 * permanently kept (not erased by successive conversions of scan of
3002 * ADC sequencer ranks), up to 5 data registers:
3003 * 1 data register on ADC group regular, 4 data registers
3004 * on ADC group injected.
3005 * @note If ADC group injected injected trigger source is set to an
3006 * external trigger, this feature must be must be set to
3007 * independent trigger.
3008 * ADC group injected automatic trigger is compliant only with
3009 * group injected trigger source set to SW start, without any
3010 * further action on ADC group injected conversion start or stop:
3011 * in this case, ADC group injected is controlled only
3012 * from ADC group regular.
3013 * @note It is not possible to enable both ADC group injected
3014 * auto-injected mode and sequencer discontinuous mode.
3015 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
3016 * @param ADCx ADC instance
3017 * @param TrigAuto This parameter can be one of the following values:
3018 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3019 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3020 * @retval None
3021 */
3022 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
3023 {
3024 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
3025 }
3026
3027 /**
3028 * @brief Get ADC group injected conversion trigger:
3029 * independent or from ADC group regular.
3030 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
3031 * @param ADCx ADC instance
3032 * @retval Returned value can be one of the following values:
3033 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3034 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3035 */
3036 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
3037 {
3038 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
3039 }
3040
3041 /**
3042 * @brief Set ADC group injected offset.
3043 * @note It sets:
3044 * - ADC group injected rank to which the offset programmed
3045 * will be applied
3046 * - Offset level (offset to be subtracted from the raw
3047 * converted data).
3048 * Caution: Offset format is dependent to ADC resolution:
3049 * offset has to be left-aligned on bit 11, the LSB (right bits)
3050 * are set to 0.
3051 * @note Offset cannot be enabled or disabled.
3052 * To emulate offset disabled, set an offset value equal to 0.
3053 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
3054 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
3055 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
3056 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
3057 * @param ADCx ADC instance
3058 * @param Rank This parameter can be one of the following values:
3059 * @arg @ref LL_ADC_INJ_RANK_1
3060 * @arg @ref LL_ADC_INJ_RANK_2
3061 * @arg @ref LL_ADC_INJ_RANK_3
3062 * @arg @ref LL_ADC_INJ_RANK_4
3063 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3064 * @retval None
3065 */
3066 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3067 {
3068 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3069
3070 MODIFY_REG(*preg,
3071 ADC_JOFR1_JOFFSET1,
3072 OffsetLevel);
3073 }
3074
3075 /**
3076 * @brief Get ADC group injected offset.
3077 * @note It gives offset level (offset to be subtracted from the raw converted data).
3078 * Caution: Offset format is dependent to ADC resolution:
3079 * offset has to be left-aligned on bit 11, the LSB (right bits)
3080 * are set to 0.
3081 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
3082 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
3083 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
3084 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
3085 * @param ADCx ADC instance
3086 * @param Rank This parameter can be one of the following values:
3087 * @arg @ref LL_ADC_INJ_RANK_1
3088 * @arg @ref LL_ADC_INJ_RANK_2
3089 * @arg @ref LL_ADC_INJ_RANK_3
3090 * @arg @ref LL_ADC_INJ_RANK_4
3091 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3092 */
3093 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
3094 {
3095 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3096
3097 return (uint32_t)(READ_BIT(*preg,
3098 ADC_JOFR1_JOFFSET1)
3099 );
3100 }
3101
3102 /**
3103 * @}
3104 */
3105
3106 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3107 * @{
3108 */
3109
3110 /**
3111 * @brief Set sampling time of the selected ADC channel
3112 * Unit: ADC clock cycles.
3113 * @note On this device, sampling time is on channel scope: independently
3114 * of channel mapped on ADC group regular or injected.
3115 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3116 * converted:
3117 * sampling time constraints must be respected (sampling time can be
3118 * adjusted in function of ADC clock frequency and sampling time
3119 * setting).
3120 * Refer to device datasheet for timings values (parameters TS_vrefint,
3121 * TS_temp, ...).
3122 * @note Conversion time is the addition of sampling time and processing time.
3123 * Refer to reference manual for ADC processing time of
3124 * this STM32 serie.
3125 * @note In case of ADC conversion of internal channel (VrefInt,
3126 * temperature sensor, ...), a sampling time minimum value
3127 * is required.
3128 * Refer to device datasheet.
3129 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
3130 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
3131 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
3132 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
3133 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
3134 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
3135 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
3136 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
3137 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
3138 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
3139 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
3140 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
3141 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
3142 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
3143 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
3144 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
3145 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
3146 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
3147 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
3148 * @param ADCx ADC instance
3149 * @param Channel This parameter can be one of the following values:
3150 * @arg @ref LL_ADC_CHANNEL_0
3151 * @arg @ref LL_ADC_CHANNEL_1
3152 * @arg @ref LL_ADC_CHANNEL_2
3153 * @arg @ref LL_ADC_CHANNEL_3
3154 * @arg @ref LL_ADC_CHANNEL_4
3155 * @arg @ref LL_ADC_CHANNEL_5
3156 * @arg @ref LL_ADC_CHANNEL_6
3157 * @arg @ref LL_ADC_CHANNEL_7
3158 * @arg @ref LL_ADC_CHANNEL_8
3159 * @arg @ref LL_ADC_CHANNEL_9
3160 * @arg @ref LL_ADC_CHANNEL_10
3161 * @arg @ref LL_ADC_CHANNEL_11
3162 * @arg @ref LL_ADC_CHANNEL_12
3163 * @arg @ref LL_ADC_CHANNEL_13
3164 * @arg @ref LL_ADC_CHANNEL_14
3165 * @arg @ref LL_ADC_CHANNEL_15
3166 * @arg @ref LL_ADC_CHANNEL_16
3167 * @arg @ref LL_ADC_CHANNEL_17
3168 * @arg @ref LL_ADC_CHANNEL_18
3169 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3170 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3171 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3172 *
3173 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3174 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3175 * @param SamplingTime This parameter can be one of the following values:
3176 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3177 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3178 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3179 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3180 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3181 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3182 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3183 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3184 * @retval None
3185 */
3186 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3187 {
3188 /* Set bits with content of parameter "SamplingTime" with bits position */
3189 /* in register and register position depending on parameter "Channel". */
3190 /* Parameter "Channel" is used with masks because containing */
3191 /* other bits reserved for other purpose. */
3192 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3193
3194 MODIFY_REG(*preg,
3195 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3196 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3197 }
3198
3199 /**
3200 * @brief Get sampling time of the selected ADC channel
3201 * Unit: ADC clock cycles.
3202 * @note On this device, sampling time is on channel scope: independently
3203 * of channel mapped on ADC group regular or injected.
3204 * @note Conversion time is the addition of sampling time and processing time.
3205 * Refer to reference manual for ADC processing time of
3206 * this STM32 serie.
3207 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
3208 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
3209 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
3210 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
3211 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
3212 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
3213 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
3214 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
3215 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
3216 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
3217 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
3218 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
3219 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
3220 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
3221 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
3222 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
3223 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
3224 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
3225 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
3226 * @param ADCx ADC instance
3227 * @param Channel This parameter can be one of the following values:
3228 * @arg @ref LL_ADC_CHANNEL_0
3229 * @arg @ref LL_ADC_CHANNEL_1
3230 * @arg @ref LL_ADC_CHANNEL_2
3231 * @arg @ref LL_ADC_CHANNEL_3
3232 * @arg @ref LL_ADC_CHANNEL_4
3233 * @arg @ref LL_ADC_CHANNEL_5
3234 * @arg @ref LL_ADC_CHANNEL_6
3235 * @arg @ref LL_ADC_CHANNEL_7
3236 * @arg @ref LL_ADC_CHANNEL_8
3237 * @arg @ref LL_ADC_CHANNEL_9
3238 * @arg @ref LL_ADC_CHANNEL_10
3239 * @arg @ref LL_ADC_CHANNEL_11
3240 * @arg @ref LL_ADC_CHANNEL_12
3241 * @arg @ref LL_ADC_CHANNEL_13
3242 * @arg @ref LL_ADC_CHANNEL_14
3243 * @arg @ref LL_ADC_CHANNEL_15
3244 * @arg @ref LL_ADC_CHANNEL_16
3245 * @arg @ref LL_ADC_CHANNEL_17
3246 * @arg @ref LL_ADC_CHANNEL_18
3247 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3248 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3249 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3250 *
3251 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3252 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3253 * @retval Returned value can be one of the following values:
3254 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3255 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3256 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3257 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3258 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3259 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3260 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3261 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3262 */
3263 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3264 {
3265 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3266
3267 return (uint32_t)(READ_BIT(*preg,
3268 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3269 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3270 );
3271 }
3272
3273 /**
3274 * @}
3275 */
3276
3277 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3278 * @{
3279 */
3280
3281 /**
3282 * @brief Set ADC analog watchdog monitored channels:
3283 * a single channel or all channels,
3284 * on ADC groups regular and-or injected.
3285 * @note Once monitored channels are selected, analog watchdog
3286 * is enabled.
3287 * @note In case of need to define a single channel to monitor
3288 * with analog watchdog from sequencer channel definition,
3289 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3290 * @note On this STM32 serie, there is only 1 kind of analog watchdog
3291 * instance:
3292 * - AWD standard (instance AWD1):
3293 * - channels monitored: can monitor 1 channel or all channels.
3294 * - groups monitored: ADC groups regular and-or injected.
3295 * - resolution: resolution is not limited (corresponds to
3296 * ADC resolution configured).
3297 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3298 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3299 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
3300 * @param ADCx ADC instance
3301 * @param AWDChannelGroup This parameter can be one of the following values:
3302 * @arg @ref LL_ADC_AWD_DISABLE
3303 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3304 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3305 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3306 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3307 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3308 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3309 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3310 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3311 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3312 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3313 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3314 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3315 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3316 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3317 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3318 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3319 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3320 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3321 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3322 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3323 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3324 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3325 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3326 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3327 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3328 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3329 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3330 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3331 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3332 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3333 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3334 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3335 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3336 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3337 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3338 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3339 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3340 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3341 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3342 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3343 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3344 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3345 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3346 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3347 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3348 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3349 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3350 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3351 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3352 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3353 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3354 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3355 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3356 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3357 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3358 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3359 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3360 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3361 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3362 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3363 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
3364 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
3365 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
3366 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
3367 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
3368 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
3369 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
3370 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
3371 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
3372 *
3373 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3374 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3375 * @retval None
3376 */
3377 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3378 {
3379 MODIFY_REG(ADCx->CR1,
3380 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3381 AWDChannelGroup);
3382 }
3383
3384 /**
3385 * @brief Get ADC analog watchdog monitored channel.
3386 * @note Usage of the returned channel number:
3387 * - To reinject this channel into another function LL_ADC_xxx:
3388 * the returned channel number is only partly formatted on definition
3389 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3390 * with parts of literals LL_ADC_CHANNEL_x or using
3391 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3392 * Then the selected literal LL_ADC_CHANNEL_x can be used
3393 * as parameter for another function.
3394 * - To get the channel number in decimal format:
3395 * process the returned value with the helper macro
3396 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3397 * Applicable only when the analog watchdog is set to monitor
3398 * one channel.
3399 * @note On this STM32 serie, there is only 1 kind of analog watchdog
3400 * instance:
3401 * - AWD standard (instance AWD1):
3402 * - channels monitored: can monitor 1 channel or all channels.
3403 * - groups monitored: ADC groups regular and-or injected.
3404 * - resolution: resolution is not limited (corresponds to
3405 * ADC resolution configured).
3406 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3407 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3408 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
3409 * @param ADCx ADC instance
3410 * @retval Returned value can be one of the following values:
3411 * @arg @ref LL_ADC_AWD_DISABLE
3412 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3413 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3414 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3415 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3416 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3417 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3418 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3419 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3420 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3421 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3422 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3423 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3424 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3425 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3426 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3427 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3428 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3429 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3430 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3431 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3432 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3433 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3434 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3435 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3436 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3437 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3438 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3439 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3440 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3441 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3442 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3443 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3444 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3445 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3446 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3447 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3448 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3449 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3450 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3451 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3452 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3453 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3454 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3455 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3456 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3457 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3458 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3459 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3460 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3461 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3462 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3463 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3464 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3465 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3466 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3467 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3468 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3469 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3470 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3471 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3472 */
3473 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
3474 {
3475 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3476 }
3477
3478 /**
3479 * @brief Set ADC analog watchdog threshold value of threshold
3480 * high or low.
3481 * @note In case of ADC resolution different of 12 bits,
3482 * analog watchdog thresholds data require a specific shift.
3483 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3484 * @note On this STM32 serie, there is only 1 kind of analog watchdog
3485 * instance:
3486 * - AWD standard (instance AWD1):
3487 * - channels monitored: can monitor 1 channel or all channels.
3488 * - groups monitored: ADC groups regular and-or injected.
3489 * - resolution: resolution is not limited (corresponds to
3490 * ADC resolution configured).
3491 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
3492 * LTR LT LL_ADC_SetAnalogWDThresholds
3493 * @param ADCx ADC instance
3494 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3495 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3496 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3497 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3498 * @retval None
3499 */
3500 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3501 {
3502 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3503
3504 MODIFY_REG(*preg,
3505 ADC_HTR_HT,
3506 AWDThresholdValue);
3507 }
3508
3509 /**
3510 * @brief Get ADC analog watchdog threshold value of threshold high or
3511 * threshold low.
3512 * @note In case of ADC resolution different of 12 bits,
3513 * analog watchdog thresholds data require a specific shift.
3514 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3515 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
3516 * LTR LT LL_ADC_GetAnalogWDThresholds
3517 * @param ADCx ADC instance
3518 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3519 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3520 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3521 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3522 */
3523 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3524 {
3525 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3526
3527 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3528 }
3529
3530 /**
3531 * @}
3532 */
3533
3534 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
3535 * @{
3536 */
3537
3538 #if defined(ADC_MULTIMODE_SUPPORT)
3539 /**
3540 * @brief Set ADC multimode configuration to operate in independent mode
3541 * or multimode (for devices with several ADC instances).
3542 * @note If multimode configuration: the selected ADC instance is
3543 * either master or slave depending on hardware.
3544 * Refer to reference manual.
3545 * @rmtoll CCR MULTI LL_ADC_SetMultimode
3546 * @param ADCxy_COMMON ADC common instance
3547 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3548 * @param Multimode This parameter can be one of the following values:
3549 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3550 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3551 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3552 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3553 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3554 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3555 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3556 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3557 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3558 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3559 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3560 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3561 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3562 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3563 * @retval None
3564 */
3565 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3566 {
3567 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
3568 }
3569
3570 /**
3571 * @brief Get ADC multimode configuration to operate in independent mode
3572 * or multimode (for devices with several ADC instances).
3573 * @note If multimode configuration: the selected ADC instance is
3574 * either master or slave depending on hardware.
3575 * Refer to reference manual.
3576 * @rmtoll CCR MULTI LL_ADC_GetMultimode
3577 * @param ADCxy_COMMON ADC common instance
3578 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3579 * @retval Returned value can be one of the following values:
3580 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3581 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3582 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3583 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3584 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3585 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3586 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3587 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3588 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3589 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3590 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3591 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3592 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3593 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3594 */
3595 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
3596 {
3597 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
3598 }
3599
3600 /**
3601 * @brief Set ADC multimode conversion data transfer: no transfer
3602 * or transfer by DMA.
3603 * @note If ADC multimode transfer by DMA is not selected:
3604 * each ADC uses its own DMA channel, with its individual
3605 * DMA transfer settings.
3606 * If ADC multimode transfer by DMA is selected:
3607 * One DMA channel is used for both ADC (DMA of ADC master)
3608 * Specifies the DMA requests mode:
3609 * - Limited mode (One shot mode): DMA transfer requests are stopped
3610 * when number of DMA data transfers (number of
3611 * ADC conversions) is reached.
3612 * This ADC mode is intended to be used with DMA mode non-circular.
3613 * - Unlimited mode: DMA transfer requests are unlimited,
3614 * whatever number of DMA data transfers (number of
3615 * ADC conversions).
3616 * This ADC mode is intended to be used with DMA mode circular.
3617 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3618 * mode non-circular:
3619 * when DMA transfers size will be reached, DMA will stop transfers of
3620 * ADC conversions data ADC will raise an overrun error
3621 * (overrun flag and interruption if enabled).
3622 * @note How to retrieve multimode conversion data:
3623 * Whatever multimode transfer by DMA setting: using function
3624 * @ref LL_ADC_REG_ReadMultiConversionData32().
3625 * If ADC multimode transfer by DMA is selected: conversion data
3626 * is a raw data with ADC master and slave concatenated.
3627 * A macro is available to get the conversion data of
3628 * ADC master or ADC slave: see helper macro
3629 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3630 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
3631 * CCR DDS LL_ADC_SetMultiDMATransfer
3632 * @param ADCxy_COMMON ADC common instance
3633 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3634 * @param MultiDMATransfer This parameter can be one of the following values:
3635 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3636 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3637 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3638 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3639 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3640 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3641 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3642 * @retval None
3643 */
3644 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
3645 {
3646 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
3647 }
3648
3649 /**
3650 * @brief Get ADC multimode conversion data transfer: no transfer
3651 * or transfer by DMA.
3652 * @note If ADC multimode transfer by DMA is not selected:
3653 * each ADC uses its own DMA channel, with its individual
3654 * DMA transfer settings.
3655 * If ADC multimode transfer by DMA is selected:
3656 * One DMA channel is used for both ADC (DMA of ADC master)
3657 * Specifies the DMA requests mode:
3658 * - Limited mode (One shot mode): DMA transfer requests are stopped
3659 * when number of DMA data transfers (number of
3660 * ADC conversions) is reached.
3661 * This ADC mode is intended to be used with DMA mode non-circular.
3662 * - Unlimited mode: DMA transfer requests are unlimited,
3663 * whatever number of DMA data transfers (number of
3664 * ADC conversions).
3665 * This ADC mode is intended to be used with DMA mode circular.
3666 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3667 * mode non-circular:
3668 * when DMA transfers size will be reached, DMA will stop transfers of
3669 * ADC conversions data ADC will raise an overrun error
3670 * (overrun flag and interruption if enabled).
3671 * @note How to retrieve multimode conversion data:
3672 * Whatever multimode transfer by DMA setting: using function
3673 * @ref LL_ADC_REG_ReadMultiConversionData32().
3674 * If ADC multimode transfer by DMA is selected: conversion data
3675 * is a raw data with ADC master and slave concatenated.
3676 * A macro is available to get the conversion data of
3677 * ADC master or ADC slave: see helper macro
3678 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3679 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
3680 * CCR DDS LL_ADC_GetMultiDMATransfer
3681 * @param ADCxy_COMMON ADC common instance
3682 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3683 * @retval Returned value can be one of the following values:
3684 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3685 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3686 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3687 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3688 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3689 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3690 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3691 */
3692 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
3693 {
3694 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
3695 }
3696
3697 /**
3698 * @brief Set ADC multimode delay between 2 sampling phases.
3699 * @note The sampling delay range depends on ADC resolution:
3700 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
3701 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
3702 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
3703 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
3704 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
3705 * @param ADCxy_COMMON ADC common instance
3706 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3707 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
3708 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3709 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3710 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3711 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3712 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3713 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3714 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3715 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3716 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3717 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3718 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3719 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3720 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3721 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3722 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3723 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3724 * @retval None
3725 */
3726 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
3727 {
3728 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
3729 }
3730
3731 /**
3732 * @brief Get ADC multimode delay between 2 sampling phases.
3733 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
3734 * @param ADCxy_COMMON ADC common instance
3735 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3736 * @retval Returned value can be one of the following values:
3737 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3738 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3739 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3740 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3741 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3742 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3743 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3744 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3745 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3746 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3747 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3748 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3749 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3750 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3751 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3752 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3753 */
3754 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
3755 {
3756 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
3757 }
3758 #endif /* ADC_MULTIMODE_SUPPORT */
3759
3760 /**
3761 * @}
3762 */
3763 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3764 * @{
3765 */
3766
3767 /**
3768 * @brief Enable the selected ADC instance.
3769 * @note On this STM32 serie, after ADC enable, a delay for
3770 * ADC internal analog stabilization is required before performing a
3771 * ADC conversion start.
3772 * Refer to device datasheet, parameter tSTAB.
3773 * @rmtoll CR2 ADON LL_ADC_Enable
3774 * @param ADCx ADC instance
3775 * @retval None
3776 */
3777 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3778 {
3779 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3780 }
3781
3782 /**
3783 * @brief Disable the selected ADC instance.
3784 * @rmtoll CR2 ADON LL_ADC_Disable
3785 * @param ADCx ADC instance
3786 * @retval None
3787 */
3788 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3789 {
3790 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3791 }
3792
3793 /**
3794 * @brief Get the selected ADC instance enable state.
3795 * @rmtoll CR2 ADON LL_ADC_IsEnabled
3796 * @param ADCx ADC instance
3797 * @retval 0: ADC is disabled, 1: ADC is enabled.
3798 */
3799 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
3800 {
3801 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3802 }
3803
3804 /**
3805 * @}
3806 */
3807
3808 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3809 * @{
3810 */
3811
3812 /**
3813 * @brief Start ADC group regular conversion.
3814 * @note On this STM32 serie, this function is relevant only for
3815 * internal trigger (SW start), not for external trigger:
3816 * - If ADC trigger has been set to software start, ADC conversion
3817 * starts immediately.
3818 * - If ADC trigger has been set to external trigger, ADC conversion
3819 * start must be performed using function
3820 * @ref LL_ADC_REG_StartConversionExtTrig().
3821 * (if external trigger edge would have been set during ADC other
3822 * settings, ADC conversion would start at trigger event
3823 * as soon as ADC is enabled).
3824 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
3825 * @param ADCx ADC instance
3826 * @retval None
3827 */
3828 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3829 {
3830 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
3831 }
3832
3833 /**
3834 * @brief Start ADC group regular conversion from external trigger.
3835 * @note ADC conversion will start at next trigger event (on the selected
3836 * trigger edge) following the ADC start conversion command.
3837 * @note On this STM32 serie, this function is relevant for
3838 * ADC conversion start from external trigger.
3839 * If internal trigger (SW start) is needed, perform ADC conversion
3840 * start using function @ref LL_ADC_REG_StartConversionSWStart().
3841 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
3842 * @param ExternalTriggerEdge This parameter can be one of the following values:
3843 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3844 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3845 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3846 * @param ADCx ADC instance
3847 * @retval None
3848 */
3849 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3850 {
3851 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3852 }
3853
3854 /**
3855 * @brief Stop ADC group regular conversion from external trigger.
3856 * @note No more ADC conversion will start at next trigger event
3857 * following the ADC stop conversion command.
3858 * If a conversion is on-going, it will be completed.
3859 * @note On this STM32 serie, there is no specific command
3860 * to stop a conversion on-going or to stop ADC converting
3861 * in continuous mode. These actions can be performed
3862 * using function @ref LL_ADC_Disable().
3863 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
3864 * @param ADCx ADC instance
3865 * @retval None
3866 */
3867 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3868 {
3869 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
3870 }
3871
3872 /**
3873 * @brief Get ADC group regular conversion data, range fit for
3874 * all ADC configurations: all ADC resolutions and
3875 * all oversampling increased data width (for devices
3876 * with feature oversampling).
3877 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
3878 * @param ADCx ADC instance
3879 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3880 */
3881 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
3882 {
3883 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3884 }
3885
3886 /**
3887 * @brief Get ADC group regular conversion data, range fit for
3888 * ADC resolution 12 bits.
3889 * @note For devices with feature oversampling: Oversampling
3890 * can increase data width, function for extended range
3891 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3892 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
3893 * @param ADCx ADC instance
3894 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3895 */
3896 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
3897 {
3898 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3899 }
3900
3901 /**
3902 * @brief Get ADC group regular conversion data, range fit for
3903 * ADC resolution 10 bits.
3904 * @note For devices with feature oversampling: Oversampling
3905 * can increase data width, function for extended range
3906 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3907 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
3908 * @param ADCx ADC instance
3909 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
3910 */
3911 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
3912 {
3913 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3914 }
3915
3916 /**
3917 * @brief Get ADC group regular conversion data, range fit for
3918 * ADC resolution 8 bits.
3919 * @note For devices with feature oversampling: Oversampling
3920 * can increase data width, function for extended range
3921 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3922 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
3923 * @param ADCx ADC instance
3924 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3925 */
3926 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
3927 {
3928 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3929 }
3930
3931 /**
3932 * @brief Get ADC group regular conversion data, range fit for
3933 * ADC resolution 6 bits.
3934 * @note For devices with feature oversampling: Oversampling
3935 * can increase data width, function for extended range
3936 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3937 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
3938 * @param ADCx ADC instance
3939 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
3940 */
3941 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
3942 {
3943 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3944 }
3945
3946 #if defined(ADC_MULTIMODE_SUPPORT)
3947 /**
3948 * @brief Get ADC multimode conversion data of ADC master, ADC slave
3949 * or raw data with ADC master and slave concatenated.
3950 * @note If raw data with ADC master and slave concatenated is retrieved,
3951 * a macro is available to get the conversion data of
3952 * ADC master or ADC slave: see helper macro
3953 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3954 * (however this macro is mainly intended for multimode
3955 * transfer by DMA, because this function can do the same
3956 * by getting multimode conversion data of ADC master or ADC slave
3957 * separately).
3958 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
3959 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
3960 * @param ADCxy_COMMON ADC common instance
3961 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3962 * @param ConversionData This parameter can be one of the following values:
3963 * @arg @ref LL_ADC_MULTI_MASTER
3964 * @arg @ref LL_ADC_MULTI_SLAVE
3965 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
3966 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3967 */
3968 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
3969 {
3970 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
3971 ADC_DR_ADC2DATA)
3972 >> POSITION_VAL(ConversionData)
3973 );
3974 }
3975 #endif /* ADC_MULTIMODE_SUPPORT */
3976
3977 /**
3978 * @}
3979 */
3980
3981 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
3982 * @{
3983 */
3984
3985 /**
3986 * @brief Start ADC group injected conversion.
3987 * @note On this STM32 serie, this function is relevant only for
3988 * internal trigger (SW start), not for external trigger:
3989 * - If ADC trigger has been set to software start, ADC conversion
3990 * starts immediately.
3991 * - If ADC trigger has been set to external trigger, ADC conversion
3992 * start must be performed using function
3993 * @ref LL_ADC_INJ_StartConversionExtTrig().
3994 * (if external trigger edge would have been set during ADC other
3995 * settings, ADC conversion would start at trigger event
3996 * as soon as ADC is enabled).
3997 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
3998 * @param ADCx ADC instance
3999 * @retval None
4000 */
4001 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
4002 {
4003 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
4004 }
4005
4006 /**
4007 * @brief Start ADC group injected conversion from external trigger.
4008 * @note ADC conversion will start at next trigger event (on the selected
4009 * trigger edge) following the ADC start conversion command.
4010 * @note On this STM32 serie, this function is relevant for
4011 * ADC conversion start from external trigger.
4012 * If internal trigger (SW start) is needed, perform ADC conversion
4013 * start using function @ref LL_ADC_INJ_StartConversionSWStart().
4014 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
4015 * @param ExternalTriggerEdge This parameter can be one of the following values:
4016 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4017 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4018 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4019 * @param ADCx ADC instance
4020 * @retval None
4021 */
4022 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4023 {
4024 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4025 }
4026
4027 /**
4028 * @brief Stop ADC group injected conversion from external trigger.
4029 * @note No more ADC conversion will start at next trigger event
4030 * following the ADC stop conversion command.
4031 * If a conversion is on-going, it will be completed.
4032 * @note On this STM32 serie, there is no specific command
4033 * to stop a conversion on-going or to stop ADC converting
4034 * in continuous mode. These actions can be performed
4035 * using function @ref LL_ADC_Disable().
4036 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
4037 * @param ADCx ADC instance
4038 * @retval None
4039 */
4040 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
4041 {
4042 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
4043 }
4044
4045 /**
4046 * @brief Get ADC group regular conversion data, range fit for
4047 * all ADC configurations: all ADC resolutions and
4048 * all oversampling increased data width (for devices
4049 * with feature oversampling).
4050 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
4051 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
4052 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
4053 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
4054 * @param ADCx ADC instance
4055 * @param Rank This parameter can be one of the following values:
4056 * @arg @ref LL_ADC_INJ_RANK_1
4057 * @arg @ref LL_ADC_INJ_RANK_2
4058 * @arg @ref LL_ADC_INJ_RANK_3
4059 * @arg @ref LL_ADC_INJ_RANK_4
4060 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4061 */
4062 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
4063 {
4064 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4065
4066 return (uint32_t)(READ_BIT(*preg,
4067 ADC_JDR1_JDATA)
4068 );
4069 }
4070
4071 /**
4072 * @brief Get ADC group injected conversion data, range fit for
4073 * ADC resolution 12 bits.
4074 * @note For devices with feature oversampling: Oversampling
4075 * can increase data width, function for extended range
4076 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4077 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
4078 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
4079 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
4080 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
4081 * @param ADCx ADC instance
4082 * @param Rank This parameter can be one of the following values:
4083 * @arg @ref LL_ADC_INJ_RANK_1
4084 * @arg @ref LL_ADC_INJ_RANK_2
4085 * @arg @ref LL_ADC_INJ_RANK_3
4086 * @arg @ref LL_ADC_INJ_RANK_4
4087 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4088 */
4089 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
4090 {
4091 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4092
4093 return (uint16_t)(READ_BIT(*preg,
4094 ADC_JDR1_JDATA)
4095 );
4096 }
4097
4098 /**
4099 * @brief Get ADC group injected conversion data, range fit for
4100 * ADC resolution 10 bits.
4101 * @note For devices with feature oversampling: Oversampling
4102 * can increase data width, function for extended range
4103 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4104 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
4105 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
4106 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
4107 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
4108 * @param ADCx ADC instance
4109 * @param Rank This parameter can be one of the following values:
4110 * @arg @ref LL_ADC_INJ_RANK_1
4111 * @arg @ref LL_ADC_INJ_RANK_2
4112 * @arg @ref LL_ADC_INJ_RANK_3
4113 * @arg @ref LL_ADC_INJ_RANK_4
4114 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4115 */
4116 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
4117 {
4118 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4119
4120 return (uint16_t)(READ_BIT(*preg,
4121 ADC_JDR1_JDATA)
4122 );
4123 }
4124
4125 /**
4126 * @brief Get ADC group injected conversion data, range fit for
4127 * ADC resolution 8 bits.
4128 * @note For devices with feature oversampling: Oversampling
4129 * can increase data width, function for extended range
4130 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4131 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
4132 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
4133 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
4134 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
4135 * @param ADCx ADC instance
4136 * @param Rank This parameter can be one of the following values:
4137 * @arg @ref LL_ADC_INJ_RANK_1
4138 * @arg @ref LL_ADC_INJ_RANK_2
4139 * @arg @ref LL_ADC_INJ_RANK_3
4140 * @arg @ref LL_ADC_INJ_RANK_4
4141 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4142 */
4143 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
4144 {
4145 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4146
4147 return (uint8_t)(READ_BIT(*preg,
4148 ADC_JDR1_JDATA)
4149 );
4150 }
4151
4152 /**
4153 * @brief Get ADC group injected conversion data, range fit for
4154 * ADC resolution 6 bits.
4155 * @note For devices with feature oversampling: Oversampling
4156 * can increase data width, function for extended range
4157 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4158 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
4159 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
4160 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
4161 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
4162 * @param ADCx ADC instance
4163 * @param Rank This parameter can be one of the following values:
4164 * @arg @ref LL_ADC_INJ_RANK_1
4165 * @arg @ref LL_ADC_INJ_RANK_2
4166 * @arg @ref LL_ADC_INJ_RANK_3
4167 * @arg @ref LL_ADC_INJ_RANK_4
4168 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4169 */
4170 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
4171 {
4172 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4173
4174 return (uint8_t)(READ_BIT(*preg,
4175 ADC_JDR1_JDATA)
4176 );
4177 }
4178
4179 /**
4180 * @}
4181 */
4182
4183 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4184 * @{
4185 */
4186
4187 /**
4188 * @brief Get flag ADC group regular end of unitary conversion
4189 * or end of sequence conversions, depending on
4190 * ADC configuration.
4191 * @note To configure flag of end of conversion,
4192 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4193 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
4194 * @param ADCx ADC instance
4195 * @retval State of bit (1 or 0).
4196 */
4197 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
4198 {
4199 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4200 }
4201
4202 /**
4203 * @brief Get flag ADC group regular overrun.
4204 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
4205 * @param ADCx ADC instance
4206 * @retval State of bit (1 or 0).
4207 */
4208 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4209 {
4210 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4211 }
4212
4213
4214 /**
4215 * @brief Get flag ADC group injected end of sequence conversions.
4216 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
4217 * @param ADCx ADC instance
4218 * @retval State of bit (1 or 0).
4219 */
4220 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
4221 {
4222 /* Note: on this STM32 serie, there is no flag ADC group injected */
4223 /* end of unitary conversion. */
4224 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4225 /* in other STM32 families). */
4226 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4227 }
4228
4229 /**
4230 * @brief Get flag ADC analog watchdog 1 flag
4231 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
4232 * @param ADCx ADC instance
4233 * @retval State of bit (1 or 0).
4234 */
4235 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4236 {
4237 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4238 }
4239
4240 /**
4241 * @brief Clear flag ADC group regular end of unitary conversion
4242 * or end of sequence conversions, depending on
4243 * ADC configuration.
4244 * @note To configure flag of end of conversion,
4245 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4246 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
4247 * @param ADCx ADC instance
4248 * @retval None
4249 */
4250 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4251 {
4252 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4253 }
4254
4255 /**
4256 * @brief Clear flag ADC group regular overrun.
4257 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
4258 * @param ADCx ADC instance
4259 * @retval None
4260 */
4261 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4262 {
4263 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4264 }
4265
4266
4267 /**
4268 * @brief Clear flag ADC group injected end of sequence conversions.
4269 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
4270 * @param ADCx ADC instance
4271 * @retval None
4272 */
4273 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4274 {
4275 /* Note: on this STM32 serie, there is no flag ADC group injected */
4276 /* end of unitary conversion. */
4277 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4278 /* in other STM32 families). */
4279 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4280 }
4281
4282 /**
4283 * @brief Clear flag ADC analog watchdog 1.
4284 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
4285 * @param ADCx ADC instance
4286 * @retval None
4287 */
4288 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4289 {
4290 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4291 }
4292
4293 #if defined(ADC_MULTIMODE_SUPPORT)
4294 /**
4295 * @brief Get flag multimode ADC group regular end of unitary conversion
4296 * or end of sequence conversions, depending on
4297 * ADC configuration, of the ADC master.
4298 * @note To configure flag of end of conversion,
4299 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4300 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
4301 * @param ADCxy_COMMON ADC common instance
4302 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4303 * @retval State of bit (1 or 0).
4304 */
4305 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4306 {
4307 return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4308 }
4309
4310 /**
4311 * @brief Get flag multimode ADC group regular end of unitary conversion
4312 * or end of sequence conversions, depending on
4313 * ADC configuration, of the ADC slave 1.
4314 * @note To configure flag of end of conversion,
4315 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4316 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
4317 * @param ADCxy_COMMON ADC common instance
4318 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4319 * @retval State of bit (1 or 0).
4320 */
4321 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4322 {
4323 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
4324 }
4325
4326 /**
4327 * @brief Get flag multimode ADC group regular end of unitary conversion
4328 * or end of sequence conversions, depending on
4329 * ADC configuration, of the ADC slave 2.
4330 * @note To configure flag of end of conversion,
4331 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4332 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
4333 * @param ADCxy_COMMON ADC common instance
4334 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4335 * @retval State of bit (1 or 0).
4336 */
4337 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4338 {
4339 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
4340 }
4341 /**
4342 * @brief Get flag multimode ADC group regular overrun of the ADC master.
4343 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
4344 * @param ADCxy_COMMON ADC common instance
4345 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4346 * @retval State of bit (1 or 0).
4347 */
4348 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4349 {
4350 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
4351 }
4352
4353 /**
4354 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
4355 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
4356 * @param ADCxy_COMMON ADC common instance
4357 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4358 * @retval State of bit (1 or 0).
4359 */
4360 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4361 {
4362 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
4363 }
4364
4365 /**
4366 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
4367 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
4368 * @param ADCxy_COMMON ADC common instance
4369 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4370 * @retval State of bit (1 or 0).
4371 */
4372 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4373 {
4374 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
4375 }
4376
4377
4378 /**
4379 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
4380 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS
4381 * @param ADCxy_COMMON ADC common instance
4382 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4383 * @retval State of bit (1 or 0).
4384 */
4385 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4386 {
4387 /* Note: on this STM32 serie, there is no flag ADC group injected */
4388 /* end of unitary conversion. */
4389 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4390 /* in other STM32 families). */
4391 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
4392 }
4393
4394 /**
4395 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
4396 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
4397 * @param ADCxy_COMMON ADC common instance
4398 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4399 * @retval State of bit (1 or 0).
4400 */
4401 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4402 {
4403 /* Note: on this STM32 serie, there is no flag ADC group injected */
4404 /* end of unitary conversion. */
4405 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4406 /* in other STM32 families). */
4407 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
4408 }
4409
4410 /**
4411 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
4412 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
4413 * @param ADCxy_COMMON ADC common instance
4414 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4415 * @retval State of bit (1 or 0).
4416 */
4417 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4418 {
4419 /* Note: on this STM32 serie, there is no flag ADC group injected */
4420 /* end of unitary conversion. */
4421 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4422 /* in other STM32 families). */
4423 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
4424 }
4425
4426 /**
4427 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
4428 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
4429 * @param ADCxy_COMMON ADC common instance
4430 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4431 * @retval State of bit (1 or 0).
4432 */
4433 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4434 {
4435 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
4436 }
4437
4438 /**
4439 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
4440 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
4441 * @param ADCxy_COMMON ADC common instance
4442 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4443 * @retval State of bit (1 or 0).
4444 */
4445 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4446 {
4447 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
4448 }
4449
4450 /**
4451 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
4452 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
4453 * @param ADCxy_COMMON ADC common instance
4454 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4455 * @retval State of bit (1 or 0).
4456 */
4457 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4458 {
4459 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
4460 }
4461
4462 #endif /* ADC_MULTIMODE_SUPPORT */
4463
4464 /**
4465 * @}
4466 */
4467
4468 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4469 * @{
4470 */
4471
4472 /**
4473 * @brief Enable interruption ADC group regular end of unitary conversion
4474 * or end of sequence conversions, depending on
4475 * ADC configuration.
4476 * @note To configure flag of end of conversion,
4477 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4478 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
4479 * @param ADCx ADC instance
4480 * @retval None
4481 */
4482 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4483 {
4484 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4485 }
4486
4487 /**
4488 * @brief Enable ADC group regular interruption overrun.
4489 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
4490 * @param ADCx ADC instance
4491 * @retval None
4492 */
4493 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4494 {
4495 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4496 }
4497
4498
4499 /**
4500 * @brief Enable interruption ADC group injected end of sequence conversions.
4501 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4502 * @param ADCx ADC instance
4503 * @retval None
4504 */
4505 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4506 {
4507 /* Note: on this STM32 serie, there is no flag ADC group injected */
4508 /* end of unitary conversion. */
4509 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4510 /* in other STM32 families). */
4511 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4512 }
4513
4514 /**
4515 * @brief Enable interruption ADC analog watchdog 1.
4516 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4517 * @param ADCx ADC instance
4518 * @retval None
4519 */
4520 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4521 {
4522 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4523 }
4524
4525 /**
4526 * @brief Disable interruption ADC group regular end of unitary conversion
4527 * or end of sequence conversions, depending on
4528 * ADC configuration.
4529 * @note To configure flag of end of conversion,
4530 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4531 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
4532 * @param ADCx ADC instance
4533 * @retval None
4534 */
4535 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
4536 {
4537 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4538 }
4539
4540 /**
4541 * @brief Disable interruption ADC group regular overrun.
4542 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
4543 * @param ADCx ADC instance
4544 * @retval None
4545 */
4546 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4547 {
4548 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4549 }
4550
4551
4552 /**
4553 * @brief Disable interruption ADC group injected end of sequence conversions.
4554 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4555 * @param ADCx ADC instance
4556 * @retval None
4557 */
4558 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
4559 {
4560 /* Note: on this STM32 serie, there is no flag ADC group injected */
4561 /* end of unitary conversion. */
4562 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4563 /* in other STM32 families). */
4564 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4565 }
4566
4567 /**
4568 * @brief Disable interruption ADC analog watchdog 1.
4569 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4570 * @param ADCx ADC instance
4571 * @retval None
4572 */
4573 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4574 {
4575 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4576 }
4577
4578 /**
4579 * @brief Get state of interruption ADC group regular end of unitary conversion
4580 * or end of sequence conversions, depending on
4581 * ADC configuration.
4582 * @note To configure flag of end of conversion,
4583 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4584 * (0: interrupt disabled, 1: interrupt enabled)
4585 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
4586 * @param ADCx ADC instance
4587 * @retval State of bit (1 or 0).
4588 */
4589 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
4590 {
4591 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
4592 }
4593
4594 /**
4595 * @brief Get state of interruption ADC group regular overrun
4596 * (0: interrupt disabled, 1: interrupt enabled).
4597 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
4598 * @param ADCx ADC instance
4599 * @retval State of bit (1 or 0).
4600 */
4601 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
4602 {
4603 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
4604 }
4605
4606
4607 /**
4608 * @brief Get state of interruption ADC group injected end of sequence conversions
4609 * (0: interrupt disabled, 1: interrupt enabled).
4610 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4611 * @param ADCx ADC instance
4612 * @retval State of bit (1 or 0).
4613 */
4614 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
4615 {
4616 /* Note: on this STM32 serie, there is no flag ADC group injected */
4617 /* end of unitary conversion. */
4618 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4619 /* in other STM32 families). */
4620 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
4621 }
4622
4623 /**
4624 * @brief Get state of interruption ADC analog watchdog 1
4625 * (0: interrupt disabled, 1: interrupt enabled).
4626 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4627 * @param ADCx ADC instance
4628 * @retval State of bit (1 or 0).
4629 */
4630 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
4631 {
4632 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4633 }
4634
4635 /**
4636 * @}
4637 */
4638
4639 #if defined(USE_FULL_LL_DRIVER)
4640 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
4641 * @{
4642 */
4643
4644 /* Initialization of some features of ADC common parameters and multimode */
4645 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4646 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4647 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4648
4649 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
4650 /* (availability of ADC group injected depends on STM32 families) */
4651 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4652
4653 /* Initialization of some features of ADC instance */
4654 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4655 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4656
4657 /* Initialization of some features of ADC instance and ADC group regular */
4658 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4659 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4660
4661 /* Initialization of some features of ADC instance and ADC group injected */
4662 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4663 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4664
4665 /**
4666 * @}
4667 */
4668 #endif /* USE_FULL_LL_DRIVER */
4669
4670 /**
4671 * @}
4672 */
4673
4674 /**
4675 * @}
4676 */
4677
4678 #endif /* ADC1 || ADC2 || ADC3 */
4679
4680 /**
4681 * @}
4682 */
4683
4684 #ifdef __cplusplus
4685 }
4686 #endif
4687
4688 #endif /* __STM32F4xx_LL_ADC_H */
4689
4690 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/