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Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_tim.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of TIM HAL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_HAL_TIM_H | |
38 #define __STM32F4xx_HAL_TIM_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 /* Includes ------------------------------------------------------------------*/ | |
45 #include "stm32f4xx_hal_def.h" | |
46 | |
47 /** @addtogroup STM32F4xx_HAL_Driver | |
48 * @{ | |
49 */ | |
50 | |
51 /** @addtogroup TIM | |
52 * @{ | |
53 */ | |
54 | |
55 /* Exported types ------------------------------------------------------------*/ | |
56 /** @defgroup TIM_Exported_Types TIM Exported Types | |
57 * @{ | |
58 */ | |
59 | |
60 /** | |
61 * @brief TIM Time base Configuration Structure definition | |
62 */ | |
63 typedef struct | |
64 { | |
65 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. | |
66 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */ | |
67 | |
68 uint32_t CounterMode; /*!< Specifies the counter mode. | |
69 This parameter can be a value of @ref TIM_Counter_Mode */ | |
70 | |
71 uint32_t Period; /*!< Specifies the period value to be loaded into the active | |
72 Auto-Reload Register at the next update event. | |
73 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */ | |
74 | |
75 uint32_t ClockDivision; /*!< Specifies the clock division. | |
76 This parameter can be a value of @ref TIM_ClockDivision */ | |
77 | |
78 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter | |
79 reaches zero, an update event is generated and counting restarts | |
80 from the RCR value (N). | |
81 This means in PWM mode that (N+1) corresponds to: | |
82 - the number of PWM periods in edge-aligned mode | |
83 - the number of half PWM period in center-aligned mode | |
84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. | |
85 @note This parameter is valid only for TIM1 and TIM8. */ | |
86 } TIM_Base_InitTypeDef; | |
87 | |
88 /** | |
89 * @brief TIM Output Compare Configuration Structure definition | |
90 */ | |
91 | |
92 typedef struct | |
93 { | |
94 uint32_t OCMode; /*!< Specifies the TIM mode. | |
95 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ | |
96 | |
97 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. | |
98 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */ | |
99 | |
100 uint32_t OCPolarity; /*!< Specifies the output polarity. | |
101 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ | |
102 | |
103 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. | |
104 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity | |
105 @note This parameter is valid only for TIM1 and TIM8. */ | |
106 | |
107 uint32_t OCFastMode; /*!< Specifies the Fast mode state. | |
108 This parameter can be a value of @ref TIM_Output_Fast_State | |
109 @note This parameter is valid only in PWM1 and PWM2 mode. */ | |
110 | |
111 | |
112 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. | |
113 This parameter can be a value of @ref TIM_Output_Compare_Idle_State | |
114 @note This parameter is valid only for TIM1 and TIM8. */ | |
115 | |
116 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. | |
117 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State | |
118 @note This parameter is valid only for TIM1 and TIM8. */ | |
119 } TIM_OC_InitTypeDef; | |
120 | |
121 /** | |
122 * @brief TIM One Pulse Mode Configuration Structure definition | |
123 */ | |
124 typedef struct | |
125 { | |
126 uint32_t OCMode; /*!< Specifies the TIM mode. | |
127 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ | |
128 | |
129 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. | |
130 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */ | |
131 | |
132 uint32_t OCPolarity; /*!< Specifies the output polarity. | |
133 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ | |
134 | |
135 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. | |
136 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity | |
137 @note This parameter is valid only for TIM1 and TIM8. */ | |
138 | |
139 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. | |
140 This parameter can be a value of @ref TIM_Output_Compare_Idle_State | |
141 @note This parameter is valid only for TIM1 and TIM8. */ | |
142 | |
143 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. | |
144 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State | |
145 @note This parameter is valid only for TIM1 and TIM8. */ | |
146 | |
147 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. | |
148 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ | |
149 | |
150 uint32_t ICSelection; /*!< Specifies the input. | |
151 This parameter can be a value of @ref TIM_Input_Capture_Selection */ | |
152 | |
153 uint32_t ICFilter; /*!< Specifies the input capture filter. | |
154 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ | |
155 } TIM_OnePulse_InitTypeDef; | |
156 | |
157 | |
158 /** | |
159 * @brief TIM Input Capture Configuration Structure definition | |
160 */ | |
161 | |
162 typedef struct | |
163 { | |
164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. | |
165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ | |
166 | |
167 uint32_t ICSelection; /*!< Specifies the input. | |
168 This parameter can be a value of @ref TIM_Input_Capture_Selection */ | |
169 | |
170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. | |
171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ | |
172 | |
173 uint32_t ICFilter; /*!< Specifies the input capture filter. | |
174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ | |
175 } TIM_IC_InitTypeDef; | |
176 | |
177 /** | |
178 * @brief TIM Encoder Configuration Structure definition | |
179 */ | |
180 | |
181 typedef struct | |
182 { | |
183 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. | |
184 This parameter can be a value of @ref TIM_Encoder_Mode */ | |
185 | |
186 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. | |
187 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ | |
188 | |
189 uint32_t IC1Selection; /*!< Specifies the input. | |
190 This parameter can be a value of @ref TIM_Input_Capture_Selection */ | |
191 | |
192 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. | |
193 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ | |
194 | |
195 uint32_t IC1Filter; /*!< Specifies the input capture filter. | |
196 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ | |
197 | |
198 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. | |
199 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ | |
200 | |
201 uint32_t IC2Selection; /*!< Specifies the input. | |
202 This parameter can be a value of @ref TIM_Input_Capture_Selection */ | |
203 | |
204 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. | |
205 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ | |
206 | |
207 uint32_t IC2Filter; /*!< Specifies the input capture filter. | |
208 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ | |
209 } TIM_Encoder_InitTypeDef; | |
210 | |
211 /** | |
212 * @brief Clock Configuration Handle Structure definition | |
213 */ | |
214 typedef struct | |
215 { | |
216 uint32_t ClockSource; /*!< TIM clock sources. | |
217 This parameter can be a value of @ref TIM_Clock_Source */ | |
218 uint32_t ClockPolarity; /*!< TIM clock polarity. | |
219 This parameter can be a value of @ref TIM_Clock_Polarity */ | |
220 uint32_t ClockPrescaler; /*!< TIM clock prescaler. | |
221 This parameter can be a value of @ref TIM_Clock_Prescaler */ | |
222 uint32_t ClockFilter; /*!< TIM clock filter. | |
223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ | |
224 }TIM_ClockConfigTypeDef; | |
225 | |
226 /** | |
227 * @brief Clear Input Configuration Handle Structure definition | |
228 */ | |
229 typedef struct | |
230 { | |
231 uint32_t ClearInputState; /*!< TIM clear Input state. | |
232 This parameter can be ENABLE or DISABLE */ | |
233 uint32_t ClearInputSource; /*!< TIM clear Input sources. | |
234 This parameter can be a value of @ref TIM_ClearInput_Source */ | |
235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. | |
236 This parameter can be a value of @ref TIM_ClearInput_Polarity */ | |
237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. | |
238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */ | |
239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter. | |
240 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ | |
241 }TIM_ClearInputConfigTypeDef; | |
242 | |
243 /** | |
244 * @brief TIM Slave configuration Structure definition | |
245 */ | |
246 typedef struct { | |
247 uint32_t SlaveMode; /*!< Slave mode selection | |
248 This parameter can be a value of @ref TIM_Slave_Mode */ | |
249 uint32_t InputTrigger; /*!< Input Trigger source | |
250 This parameter can be a value of @ref TIM_Trigger_Selection */ | |
251 uint32_t TriggerPolarity; /*!< Input Trigger polarity | |
252 This parameter can be a value of @ref TIM_Trigger_Polarity */ | |
253 uint32_t TriggerPrescaler; /*!< Input trigger prescaler | |
254 This parameter can be a value of @ref TIM_Trigger_Prescaler */ | |
255 uint32_t TriggerFilter; /*!< Input trigger filter | |
256 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ | |
257 | |
258 }TIM_SlaveConfigTypeDef; | |
259 | |
260 /** | |
261 * @brief HAL State structures definition | |
262 */ | |
263 typedef enum | |
264 { | |
265 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ | |
266 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ | |
267 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ | |
268 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ | |
269 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ | |
270 }HAL_TIM_StateTypeDef; | |
271 | |
272 /** | |
273 * @brief HAL Active channel structures definition | |
274 */ | |
275 typedef enum | |
276 { | |
277 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ | |
278 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ | |
279 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ | |
280 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ | |
281 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ | |
282 }HAL_TIM_ActiveChannel; | |
283 | |
284 /** | |
285 * @brief TIM Time Base Handle Structure definition | |
286 */ | |
287 typedef struct | |
288 { | |
289 TIM_TypeDef *Instance; /*!< Register base address */ | |
290 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ | |
291 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ | |
292 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array | |
293 This array is accessed by a @ref DMA_Handle_index */ | |
294 HAL_LockTypeDef Lock; /*!< Locking object */ | |
295 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ | |
296 }TIM_HandleTypeDef; | |
297 /** | |
298 * @} | |
299 */ | |
300 | |
301 /* Exported constants --------------------------------------------------------*/ | |
302 /** @defgroup TIM_Exported_Constants TIM Exported Constants | |
303 * @{ | |
304 */ | |
305 | |
306 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity | |
307 * @{ | |
308 */ | |
309 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ | |
310 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ | |
311 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ | |
312 /** | |
313 * @} | |
314 */ | |
315 | |
316 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity | |
317 * @{ | |
318 */ | |
319 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ | |
320 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ | |
321 /** | |
322 * @} | |
323 */ | |
324 | |
325 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler | |
326 * @{ | |
327 */ | |
328 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ | |
329 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ | |
330 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ | |
331 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ | |
332 /** | |
333 * @} | |
334 */ | |
335 | |
336 /** @defgroup TIM_Counter_Mode TIM Counter Mode | |
337 * @{ | |
338 */ | |
339 #define TIM_COUNTERMODE_UP 0x00000000U | |
340 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR | |
341 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 | |
342 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 | |
343 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS | |
344 /** | |
345 * @} | |
346 */ | |
347 | |
348 /** @defgroup TIM_ClockDivision TIM Clock Division | |
349 * @{ | |
350 */ | |
351 #define TIM_CLOCKDIVISION_DIV1 0x00000000U | |
352 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) | |
353 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) | |
354 /** | |
355 * @} | |
356 */ | |
357 | |
358 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes | |
359 * @{ | |
360 */ | |
361 #define TIM_OCMODE_TIMING 0x00000000U | |
362 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) | |
363 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) | |
364 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) | |
365 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) | |
366 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) | |
367 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) | |
368 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) | |
369 | |
370 /** | |
371 * @} | |
372 */ | |
373 | |
374 /** @defgroup TIM_Output_Fast_State TIM Output Fast State | |
375 * @{ | |
376 */ | |
377 #define TIM_OCFAST_DISABLE 0x00000000U | |
378 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) | |
379 /** | |
380 * @} | |
381 */ | |
382 | |
383 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity | |
384 * @{ | |
385 */ | |
386 #define TIM_OCPOLARITY_HIGH 0x00000000U | |
387 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) | |
388 /** | |
389 * @} | |
390 */ | |
391 | |
392 /** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity | |
393 * @{ | |
394 */ | |
395 #define TIM_OCNPOLARITY_HIGH 0x00000000U | |
396 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) | |
397 /** | |
398 * @} | |
399 */ | |
400 | |
401 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State | |
402 * @{ | |
403 */ | |
404 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) | |
405 #define TIM_OCIDLESTATE_RESET 0x00000000U | |
406 /** | |
407 * @} | |
408 */ | |
409 | |
410 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State | |
411 * @{ | |
412 */ | |
413 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) | |
414 #define TIM_OCNIDLESTATE_RESET 0x00000000U | |
415 /** | |
416 * @} | |
417 */ | |
418 | |
419 /** @defgroup TIM_Channel TIM Channel | |
420 * @{ | |
421 */ | |
422 #define TIM_CHANNEL_1 0x00000000U | |
423 #define TIM_CHANNEL_2 0x00000004U | |
424 #define TIM_CHANNEL_3 0x00000008U | |
425 #define TIM_CHANNEL_4 0x0000000CU | |
426 #define TIM_CHANNEL_ALL 0x00000018U | |
427 | |
428 /** | |
429 * @} | |
430 */ | |
431 | |
432 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity | |
433 * @{ | |
434 */ | |
435 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING | |
436 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING | |
437 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE | |
438 /** | |
439 * @} | |
440 */ | |
441 | |
442 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection | |
443 * @{ | |
444 */ | |
445 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be | |
446 connected to IC1, IC2, IC3 or IC4, respectively */ | |
447 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be | |
448 connected to IC2, IC1, IC4 or IC3, respectively */ | |
449 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ | |
450 | |
451 /** | |
452 * @} | |
453 */ | |
454 | |
455 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler | |
456 * @{ | |
457 */ | |
458 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ | |
459 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ | |
460 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ | |
461 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ | |
462 /** | |
463 * @} | |
464 */ | |
465 | |
466 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode | |
467 * @{ | |
468 */ | |
469 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) | |
470 #define TIM_OPMODE_REPETITIVE 0x00000000U | |
471 /** | |
472 * @} | |
473 */ | |
474 | |
475 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode | |
476 * @{ | |
477 */ | |
478 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) | |
479 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) | |
480 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) | |
481 | |
482 /** | |
483 * @} | |
484 */ | |
485 | |
486 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition | |
487 * @{ | |
488 */ | |
489 #define TIM_IT_UPDATE (TIM_DIER_UIE) | |
490 #define TIM_IT_CC1 (TIM_DIER_CC1IE) | |
491 #define TIM_IT_CC2 (TIM_DIER_CC2IE) | |
492 #define TIM_IT_CC3 (TIM_DIER_CC3IE) | |
493 #define TIM_IT_CC4 (TIM_DIER_CC4IE) | |
494 #define TIM_IT_COM (TIM_DIER_COMIE) | |
495 #define TIM_IT_TRIGGER (TIM_DIER_TIE) | |
496 #define TIM_IT_BREAK (TIM_DIER_BIE) | |
497 /** | |
498 * @} | |
499 */ | |
500 | |
501 /** @defgroup TIM_Commutation_Source TIM Commutation Source | |
502 * @{ | |
503 */ | |
504 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) | |
505 #define TIM_COMMUTATION_SOFTWARE 0x00000000U | |
506 /** | |
507 * @} | |
508 */ | |
509 | |
510 /** @defgroup TIM_DMA_sources TIM DMA sources | |
511 * @{ | |
512 */ | |
513 #define TIM_DMA_UPDATE (TIM_DIER_UDE) | |
514 #define TIM_DMA_CC1 (TIM_DIER_CC1DE) | |
515 #define TIM_DMA_CC2 (TIM_DIER_CC2DE) | |
516 #define TIM_DMA_CC3 (TIM_DIER_CC3DE) | |
517 #define TIM_DMA_CC4 (TIM_DIER_CC4DE) | |
518 #define TIM_DMA_COM (TIM_DIER_COMDE) | |
519 #define TIM_DMA_TRIGGER (TIM_DIER_TDE) | |
520 /** | |
521 * @} | |
522 */ | |
523 | |
524 /** @defgroup TIM_Event_Source TIM Event Source | |
525 * @{ | |
526 */ | |
527 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG | |
528 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G | |
529 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G | |
530 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G | |
531 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G | |
532 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG | |
533 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG | |
534 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG | |
535 | |
536 /** | |
537 * @} | |
538 */ | |
539 | |
540 /** @defgroup TIM_Flag_definition TIM Flag definition | |
541 * @{ | |
542 */ | |
543 #define TIM_FLAG_UPDATE (TIM_SR_UIF) | |
544 #define TIM_FLAG_CC1 (TIM_SR_CC1IF) | |
545 #define TIM_FLAG_CC2 (TIM_SR_CC2IF) | |
546 #define TIM_FLAG_CC3 (TIM_SR_CC3IF) | |
547 #define TIM_FLAG_CC4 (TIM_SR_CC4IF) | |
548 #define TIM_FLAG_COM (TIM_SR_COMIF) | |
549 #define TIM_FLAG_TRIGGER (TIM_SR_TIF) | |
550 #define TIM_FLAG_BREAK (TIM_SR_BIF) | |
551 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) | |
552 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) | |
553 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) | |
554 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) | |
555 /** | |
556 * @} | |
557 */ | |
558 | |
559 /** @defgroup TIM_Clock_Source TIM Clock Source | |
560 * @{ | |
561 */ | |
562 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) | |
563 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) | |
564 #define TIM_CLOCKSOURCE_ITR0 0x00000000U | |
565 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) | |
566 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) | |
567 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) | |
568 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) | |
569 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) | |
570 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) | |
571 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) | |
572 /** | |
573 * @} | |
574 */ | |
575 | |
576 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity | |
577 * @{ | |
578 */ | |
579 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ | |
580 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ | |
581 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ | |
582 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ | |
583 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ | |
584 /** | |
585 * @} | |
586 */ | |
587 | |
588 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler | |
589 * @{ | |
590 */ | |
591 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ | |
592 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ | |
593 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ | |
594 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ | |
595 /** | |
596 * @} | |
597 */ | |
598 | |
599 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source | |
600 * @{ | |
601 */ | |
602 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U | |
603 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U | |
604 /** | |
605 * @} | |
606 */ | |
607 | |
608 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity | |
609 * @{ | |
610 */ | |
611 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ | |
612 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ | |
613 /** | |
614 * @} | |
615 */ | |
616 | |
617 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler | |
618 * @{ | |
619 */ | |
620 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ | |
621 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ | |
622 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ | |
623 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ | |
624 /** | |
625 * @} | |
626 */ | |
627 | |
628 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state | |
629 * @{ | |
630 */ | |
631 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) | |
632 #define TIM_OSSR_DISABLE 0x00000000U | |
633 /** | |
634 * @} | |
635 */ | |
636 | |
637 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state | |
638 * @{ | |
639 */ | |
640 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) | |
641 #define TIM_OSSI_DISABLE 0x00000000U | |
642 /** | |
643 * @} | |
644 */ | |
645 | |
646 /** @defgroup TIM_Lock_level TIM Lock level | |
647 * @{ | |
648 */ | |
649 #define TIM_LOCKLEVEL_OFF 0x00000000U | |
650 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) | |
651 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) | |
652 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) | |
653 /** | |
654 * @} | |
655 */ | |
656 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State | |
657 * @{ | |
658 */ | |
659 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) | |
660 #define TIM_BREAK_DISABLE 0x00000000U | |
661 /** | |
662 * @} | |
663 */ | |
664 | |
665 /** @defgroup TIM_Break_Polarity TIM Break Polarity | |
666 * @{ | |
667 */ | |
668 #define TIM_BREAKPOLARITY_LOW 0x00000000U | |
669 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) | |
670 /** | |
671 * @} | |
672 */ | |
673 | |
674 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State | |
675 * @{ | |
676 */ | |
677 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) | |
678 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U | |
679 /** | |
680 * @} | |
681 */ | |
682 | |
683 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection | |
684 * @{ | |
685 */ | |
686 #define TIM_TRGO_RESET 0x00000000U | |
687 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) | |
688 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) | |
689 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) | |
690 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) | |
691 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) | |
692 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) | |
693 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) | |
694 /** | |
695 * @} | |
696 */ | |
697 | |
698 /** @defgroup TIM_Slave_Mode TIM Slave Mode | |
699 * @{ | |
700 */ | |
701 #define TIM_SLAVEMODE_DISABLE 0x00000000U | |
702 #define TIM_SLAVEMODE_RESET 0x00000004U | |
703 #define TIM_SLAVEMODE_GATED 0x00000005U | |
704 #define TIM_SLAVEMODE_TRIGGER 0x00000006U | |
705 #define TIM_SLAVEMODE_EXTERNAL1 0x00000007U | |
706 /** | |
707 * @} | |
708 */ | |
709 | |
710 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode | |
711 * @{ | |
712 */ | |
713 #define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U | |
714 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U | |
715 /** | |
716 * @} | |
717 */ | |
718 | |
719 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection | |
720 * @{ | |
721 */ | |
722 #define TIM_TS_ITR0 0x00000000U | |
723 #define TIM_TS_ITR1 0x00000010U | |
724 #define TIM_TS_ITR2 0x00000020U | |
725 #define TIM_TS_ITR3 0x00000030U | |
726 #define TIM_TS_TI1F_ED 0x00000040U | |
727 #define TIM_TS_TI1FP1 0x00000050U | |
728 #define TIM_TS_TI2FP2 0x00000060U | |
729 #define TIM_TS_ETRF 0x00000070U | |
730 #define TIM_TS_NONE 0x0000FFFFU | |
731 /** | |
732 * @} | |
733 */ | |
734 | |
735 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity | |
736 * @{ | |
737 */ | |
738 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ | |
739 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ | |
740 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ | |
741 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ | |
742 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ | |
743 /** | |
744 * @} | |
745 */ | |
746 | |
747 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler | |
748 * @{ | |
749 */ | |
750 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ | |
751 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ | |
752 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ | |
753 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ | |
754 /** | |
755 * @} | |
756 */ | |
757 | |
758 | |
759 /** @defgroup TIM_TI1_Selection TIM TI1 Selection | |
760 * @{ | |
761 */ | |
762 #define TIM_TI1SELECTION_CH1 0x00000000U | |
763 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) | |
764 /** | |
765 * @} | |
766 */ | |
767 | |
768 /** @defgroup TIM_DMA_Base_address TIM DMA Base address | |
769 * @{ | |
770 */ | |
771 #define TIM_DMABASE_CR1 0x00000000U | |
772 #define TIM_DMABASE_CR2 0x00000001U | |
773 #define TIM_DMABASE_SMCR 0x00000002U | |
774 #define TIM_DMABASE_DIER 0x00000003U | |
775 #define TIM_DMABASE_SR 0x00000004U | |
776 #define TIM_DMABASE_EGR 0x00000005U | |
777 #define TIM_DMABASE_CCMR1 0x00000006U | |
778 #define TIM_DMABASE_CCMR2 0x00000007U | |
779 #define TIM_DMABASE_CCER 0x00000008U | |
780 #define TIM_DMABASE_CNT 0x00000009U | |
781 #define TIM_DMABASE_PSC 0x0000000AU | |
782 #define TIM_DMABASE_ARR 0x0000000BU | |
783 #define TIM_DMABASE_RCR 0x0000000CU | |
784 #define TIM_DMABASE_CCR1 0x0000000DU | |
785 #define TIM_DMABASE_CCR2 0x0000000EU | |
786 #define TIM_DMABASE_CCR3 0x0000000FU | |
787 #define TIM_DMABASE_CCR4 0x00000010U | |
788 #define TIM_DMABASE_BDTR 0x00000011U | |
789 #define TIM_DMABASE_DCR 0x00000012U | |
790 #define TIM_DMABASE_OR 0x00000013U | |
791 /** | |
792 * @} | |
793 */ | |
794 | |
795 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length | |
796 * @{ | |
797 */ | |
798 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U | |
799 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U | |
800 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U | |
801 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U | |
802 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U | |
803 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U | |
804 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U | |
805 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U | |
806 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U | |
807 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U | |
808 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U | |
809 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U | |
810 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U | |
811 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U | |
812 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U | |
813 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U | |
814 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U | |
815 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U | |
816 /** | |
817 * @} | |
818 */ | |
819 | |
820 /** @defgroup DMA_Handle_index DMA Handle index | |
821 * @{ | |
822 */ | |
823 #define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */ | |
824 #define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ | |
825 #define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ | |
826 #define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ | |
827 #define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ | |
828 #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ | |
829 #define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ | |
830 /** | |
831 * @} | |
832 */ | |
833 | |
834 /** @defgroup Channel_CC_State Channel CC State | |
835 * @{ | |
836 */ | |
837 #define TIM_CCx_ENABLE 0x00000001U | |
838 #define TIM_CCx_DISABLE 0x00000000U | |
839 #define TIM_CCxN_ENABLE 0x00000004U | |
840 #define TIM_CCxN_DISABLE 0x00000000U | |
841 /** | |
842 * @} | |
843 */ | |
844 | |
845 /** | |
846 * @} | |
847 */ | |
848 | |
849 /* Exported macro ------------------------------------------------------------*/ | |
850 /** @defgroup TIM_Exported_Macros TIM Exported Macros | |
851 * @{ | |
852 */ | |
853 /** @brief Reset TIM handle state | |
854 * @param __HANDLE__ TIM handle | |
855 * @retval None | |
856 */ | |
857 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) | |
858 | |
859 /** | |
860 * @brief Enable the TIM peripheral. | |
861 * @param __HANDLE__ TIM handle | |
862 * @retval None | |
863 */ | |
864 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) | |
865 | |
866 /** | |
867 * @brief Enable the TIM main Output. | |
868 * @param __HANDLE__ TIM handle | |
869 * @retval None | |
870 */ | |
871 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) | |
872 | |
873 | |
874 /** | |
875 * @brief Disable the TIM peripheral. | |
876 * @param __HANDLE__ TIM handle | |
877 * @retval None | |
878 */ | |
879 #define __HAL_TIM_DISABLE(__HANDLE__) \ | |
880 do { \ | |
881 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ | |
882 { \ | |
883 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ | |
884 { \ | |
885 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ | |
886 } \ | |
887 } \ | |
888 } while(0U) | |
889 | |
890 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN | |
891 channels have been disabled */ | |
892 /** | |
893 * @brief Disable the TIM main Output. | |
894 * @param __HANDLE__ TIM handle | |
895 * @retval None | |
896 */ | |
897 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ | |
898 do { \ | |
899 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ | |
900 { \ | |
901 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ | |
902 { \ | |
903 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ | |
904 } \ | |
905 } \ | |
906 } while(0U) | |
907 | |
908 /** | |
909 * @brief Disable the TIM main Output. | |
910 * @param __HANDLE__ TIM handle | |
911 * @retval None | |
912 * @note The Main Output Enable of a timer instance is disabled unconditionally | |
913 */ | |
914 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) | |
915 | |
916 /** @brief Enable the specified TIM interrupt. | |
917 * @param __HANDLE__ specifies the TIM Handle. | |
918 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. | |
919 * This parameter can be one of the following values: | |
920 * @arg TIM_IT_UPDATE: Update interrupt | |
921 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt | |
922 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt | |
923 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt | |
924 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt | |
925 * @arg TIM_IT_COM: Commutation interrupt | |
926 * @arg TIM_IT_TRIGGER: Trigger interrupt | |
927 * @arg TIM_IT_BREAK: Break interrupt | |
928 * @retval None | |
929 */ | |
930 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) | |
931 | |
932 | |
933 /** @brief Disable the specified TIM interrupt. | |
934 * @param __HANDLE__ specifies the TIM Handle. | |
935 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. | |
936 * This parameter can be one of the following values: | |
937 * @arg TIM_IT_UPDATE: Update interrupt | |
938 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt | |
939 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt | |
940 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt | |
941 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt | |
942 * @arg TIM_IT_COM: Commutation interrupt | |
943 * @arg TIM_IT_TRIGGER: Trigger interrupt | |
944 * @arg TIM_IT_BREAK: Break interrupt | |
945 * @retval None | |
946 */ | |
947 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) | |
948 | |
949 /** @brief Enable the specified DMA request. | |
950 * @param __HANDLE__ specifies the TIM Handle. | |
951 * @param __DMA__ specifies the TIM DMA request to enable. | |
952 * This parameter can be one of the following values: | |
953 * @arg TIM_DMA_UPDATE: Update DMA request | |
954 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request | |
955 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request | |
956 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request | |
957 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request | |
958 * @arg TIM_DMA_COM: Commutation DMA request | |
959 * @arg TIM_DMA_TRIGGER: Trigger DMA request | |
960 * @retval None | |
961 */ | |
962 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) | |
963 | |
964 /** @brief Disable the specified DMA request. | |
965 * @param __HANDLE__ specifies the TIM Handle. | |
966 * @param __DMA__ specifies the TIM DMA request to disable. | |
967 * This parameter can be one of the following values: | |
968 * @arg TIM_DMA_UPDATE: Update DMA request | |
969 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request | |
970 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request | |
971 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request | |
972 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request | |
973 * @arg TIM_DMA_COM: Commutation DMA request | |
974 * @arg TIM_DMA_TRIGGER: Trigger DMA request | |
975 * @retval None | |
976 */ | |
977 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) | |
978 | |
979 /** @brief Check whether the specified TIM interrupt flag is set or not. | |
980 * @param __HANDLE__ specifies the TIM Handle. | |
981 * @param __FLAG__ specifies the TIM interrupt flag to check. | |
982 * This parameter can be one of the following values: | |
983 * @arg TIM_FLAG_UPDATE: Update interrupt flag | |
984 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag | |
985 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag | |
986 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag | |
987 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag | |
988 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag | |
989 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag | |
990 * @arg TIM_FLAG_COM: Commutation interrupt flag | |
991 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag | |
992 * @arg TIM_FLAG_BREAK: Break interrupt flag | |
993 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag | |
994 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag | |
995 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag | |
996 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag | |
997 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag | |
998 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag | |
999 * @retval The new state of __FLAG__ (TRUE or FALSE). | |
1000 */ | |
1001 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) | |
1002 | |
1003 /** @brief Clear the specified TIM interrupt flag. | |
1004 * @param __HANDLE__ specifies the TIM Handle. | |
1005 * @param __FLAG__ specifies the TIM interrupt flag to clear. | |
1006 * This parameter can be one of the following values: | |
1007 * @arg TIM_FLAG_UPDATE: Update interrupt flag | |
1008 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag | |
1009 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag | |
1010 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag | |
1011 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag | |
1012 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag | |
1013 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag | |
1014 * @arg TIM_FLAG_COM: Commutation interrupt flag | |
1015 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag | |
1016 * @arg TIM_FLAG_BREAK: Break interrupt flag | |
1017 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag | |
1018 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag | |
1019 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag | |
1020 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag | |
1021 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag | |
1022 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag | |
1023 * @retval The new state of __FLAG__ (TRUE or FALSE). | |
1024 */ | |
1025 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) | |
1026 | |
1027 /** | |
1028 * @brief Check whether the specified TIM interrupt source is enabled or not. | |
1029 * @param __HANDLE__ TIM handle | |
1030 * @param __INTERRUPT__ specifies the TIM interrupt source to check. | |
1031 * This parameter can be one of the following values: | |
1032 * @arg TIM_IT_UPDATE: Update interrupt | |
1033 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt | |
1034 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt | |
1035 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt | |
1036 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt | |
1037 * @arg TIM_IT_COM: Commutation interrupt | |
1038 * @arg TIM_IT_TRIGGER: Trigger interrupt | |
1039 * @arg TIM_IT_BREAK: Break interrupt | |
1040 * @retval The state of TIM_IT (SET or RESET). | |
1041 */ | |
1042 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) | |
1043 | |
1044 /** @brief Clear the TIM interrupt pending bits. | |
1045 * @param __HANDLE__ TIM handle | |
1046 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. | |
1047 * This parameter can be one of the following values: | |
1048 * @arg TIM_IT_UPDATE: Update interrupt | |
1049 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt | |
1050 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt | |
1051 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt | |
1052 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt | |
1053 * @arg TIM_IT_COM: Commutation interrupt | |
1054 * @arg TIM_IT_TRIGGER: Trigger interrupt | |
1055 * @arg TIM_IT_BREAK: Break interrupt | |
1056 * @retval None | |
1057 */ | |
1058 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) | |
1059 | |
1060 /** | |
1061 * @brief Indicates whether or not the TIM Counter is used as downcounter. | |
1062 * @param __HANDLE__ TIM handle. | |
1063 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) | |
1064 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder | |
1065 mode. | |
1066 */ | |
1067 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) | |
1068 | |
1069 /** | |
1070 * @brief Set the TIM Prescaler on runtime. | |
1071 * @param __HANDLE__ TIM handle. | |
1072 * @param __PRESC__ specifies the Prescaler new value. | |
1073 * @retval None | |
1074 */ | |
1075 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) | |
1076 | |
1077 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ | |
1078 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ | |
1079 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ | |
1080 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ | |
1081 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) | |
1082 | |
1083 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ | |
1084 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ | |
1085 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ | |
1086 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ | |
1087 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) | |
1088 | |
1089 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ | |
1090 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ | |
1091 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ | |
1092 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ | |
1093 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P))) | |
1094 | |
1095 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ | |
1096 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ | |
1097 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ | |
1098 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ | |
1099 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) | |
1100 | |
1101 /** | |
1102 * @brief Sets the TIM Capture Compare Register value on runtime without | |
1103 * calling another time ConfigChannel function. | |
1104 * @param __HANDLE__ TIM handle. | |
1105 * @param __CHANNEL__ TIM Channels to be configured. | |
1106 * This parameter can be one of the following values: | |
1107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1109 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1110 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1111 * @param __COMPARE__ specifies the Capture Compare register new value. | |
1112 * @retval None | |
1113 */ | |
1114 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ | |
1115 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) | |
1116 | |
1117 /** | |
1118 * @brief Gets the TIM Capture Compare Register value on runtime. | |
1119 * @param __HANDLE__ TIM handle. | |
1120 * @param __CHANNEL__ TIM Channel associated with the capture compare register | |
1121 * This parameter can be one of the following values: | |
1122 * @arg TIM_CHANNEL_1: get capture/compare 1 register value | |
1123 * @arg TIM_CHANNEL_2: get capture/compare 2 register value | |
1124 * @arg TIM_CHANNEL_3: get capture/compare 3 register value | |
1125 * @arg TIM_CHANNEL_4: get capture/compare 4 register value | |
1126 * @arg TIM_CHANNEL_5: get capture/compare 5 register value | |
1127 * @arg TIM_CHANNEL_6: get capture/compare 6 register value | |
1128 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) | |
1129 */ | |
1130 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ | |
1131 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) | |
1132 | |
1133 /** | |
1134 * @brief Sets the TIM Counter Register value on runtime. | |
1135 * @param __HANDLE__ TIM handle. | |
1136 * @param __COUNTER__ specifies the Counter register new value. | |
1137 * @retval None | |
1138 */ | |
1139 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) | |
1140 | |
1141 /** | |
1142 * @brief Gets the TIM Counter Register value on runtime. | |
1143 * @param __HANDLE__ TIM handle. | |
1144 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) | |
1145 */ | |
1146 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) | |
1147 | |
1148 /** | |
1149 * @brief Sets the TIM Autoreload Register value on runtime without calling | |
1150 * another time any Init function. | |
1151 * @param __HANDLE__ TIM handle. | |
1152 * @param __AUTORELOAD__ specifies the Counter register new value. | |
1153 * @retval None | |
1154 */ | |
1155 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ | |
1156 do{ \ | |
1157 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ | |
1158 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ | |
1159 } while(0U) | |
1160 /** | |
1161 * @brief Gets the TIM Autoreload Register value on runtime. | |
1162 * @param __HANDLE__ TIM handle. | |
1163 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) | |
1164 */ | |
1165 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) | |
1166 | |
1167 /** | |
1168 * @brief Sets the TIM Clock Division value on runtime without calling another time any Init function. | |
1169 * @param __HANDLE__ TIM handle. | |
1170 * @param __CKD__ specifies the clock division value. | |
1171 * This parameter can be one of the following value: | |
1172 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT | |
1173 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT | |
1174 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT | |
1175 * @retval None | |
1176 */ | |
1177 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ | |
1178 do{ \ | |
1179 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ | |
1180 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ | |
1181 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ | |
1182 } while(0U) | |
1183 /** | |
1184 * @brief Gets the TIM Clock Division value on runtime. | |
1185 * @param __HANDLE__ TIM handle. | |
1186 * @retval The clock division can be one of the following values: | |
1187 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT | |
1188 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT | |
1189 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT | |
1190 */ | |
1191 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) | |
1192 | |
1193 /** | |
1194 * @brief Sets the TIM Input Capture prescaler on runtime without calling | |
1195 * another time HAL_TIM_IC_ConfigChannel() function. | |
1196 * @param __HANDLE__ TIM handle. | |
1197 * @param __CHANNEL__ TIM Channels to be configured. | |
1198 * This parameter can be one of the following values: | |
1199 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1200 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1201 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1202 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1203 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. | |
1204 * This parameter can be one of the following values: | |
1205 * @arg TIM_ICPSC_DIV1: no prescaler | |
1206 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events | |
1207 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events | |
1208 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events | |
1209 * @retval None | |
1210 */ | |
1211 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ | |
1212 do{ \ | |
1213 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ | |
1214 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ | |
1215 } while(0U) | |
1216 | |
1217 /** | |
1218 * @brief Get the TIM Input Capture prescaler on runtime. | |
1219 * @param __HANDLE__ TIM handle. | |
1220 * @param __CHANNEL__ TIM Channels to be configured. | |
1221 * This parameter can be one of the following values: | |
1222 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value | |
1223 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value | |
1224 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value | |
1225 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value | |
1226 * @retval The input capture prescaler can be one of the following values: | |
1227 * @arg TIM_ICPSC_DIV1: no prescaler | |
1228 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events | |
1229 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events | |
1230 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events | |
1231 */ | |
1232 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ | |
1233 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ | |
1234 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ | |
1235 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ | |
1236 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) | |
1237 | |
1238 /** | |
1239 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register | |
1240 * @param __HANDLE__ TIM handle. | |
1241 * @note When the USR bit of the TIMx_CR1 register is set, only counter | |
1242 * overflow/underflow generates an update interrupt or DMA request (if | |
1243 * enabled) | |
1244 * @retval None | |
1245 */ | |
1246 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ | |
1247 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) | |
1248 | |
1249 /** | |
1250 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register | |
1251 * @param __HANDLE__ TIM handle. | |
1252 * @note When the USR bit of the TIMx_CR1 register is reset, any of the | |
1253 * following events generate an update interrupt or DMA request (if | |
1254 * enabled): | |
1255 * _ Counter overflow/underflow | |
1256 * _ Setting the UG bit | |
1257 * _ Update generation through the slave mode controller | |
1258 * @retval None | |
1259 */ | |
1260 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ | |
1261 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) | |
1262 | |
1263 /** | |
1264 * @brief Sets the TIM Capture x input polarity on runtime. | |
1265 * @param __HANDLE__ TIM handle. | |
1266 * @param __CHANNEL__ TIM Channels to be configured. | |
1267 * This parameter can be one of the following values: | |
1268 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1269 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1270 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1271 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1272 * @param __POLARITY__ Polarity for TIx source | |
1273 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge | |
1274 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge | |
1275 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge | |
1276 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. | |
1277 * @retval None | |
1278 */ | |
1279 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ | |
1280 do{ \ | |
1281 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ | |
1282 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ | |
1283 }while(0U) | |
1284 /** | |
1285 * @} | |
1286 */ | |
1287 | |
1288 /* Include TIM HAL Extension module */ | |
1289 #include "stm32f4xx_hal_tim_ex.h" | |
1290 | |
1291 /* Exported functions --------------------------------------------------------*/ | |
1292 /** @addtogroup TIM_Exported_Functions | |
1293 * @{ | |
1294 */ | |
1295 | |
1296 /** @addtogroup TIM_Exported_Functions_Group1 | |
1297 * @{ | |
1298 */ | |
1299 | |
1300 /* Time Base functions ********************************************************/ | |
1301 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); | |
1302 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); | |
1303 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); | |
1304 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); | |
1305 /* Blocking mode: Polling */ | |
1306 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); | |
1307 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); | |
1308 /* Non-Blocking mode: Interrupt */ | |
1309 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); | |
1310 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); | |
1311 /* Non-Blocking mode: DMA */ | |
1312 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); | |
1313 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); | |
1314 /** | |
1315 * @} | |
1316 */ | |
1317 | |
1318 /** @addtogroup TIM_Exported_Functions_Group2 | |
1319 * @{ | |
1320 */ | |
1321 /* Timer Output Compare functions **********************************************/ | |
1322 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); | |
1323 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); | |
1324 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); | |
1325 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); | |
1326 /* Blocking mode: Polling */ | |
1327 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1328 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1329 /* Non-Blocking mode: Interrupt */ | |
1330 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1331 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1332 /* Non-Blocking mode: DMA */ | |
1333 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); | |
1334 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1335 | |
1336 /** | |
1337 * @} | |
1338 */ | |
1339 | |
1340 /** @addtogroup TIM_Exported_Functions_Group3 | |
1341 * @{ | |
1342 */ | |
1343 /* Timer PWM functions *********************************************************/ | |
1344 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); | |
1345 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); | |
1346 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); | |
1347 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); | |
1348 /* Blocking mode: Polling */ | |
1349 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1350 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1351 /* Non-Blocking mode: Interrupt */ | |
1352 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1353 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1354 /* Non-Blocking mode: DMA */ | |
1355 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); | |
1356 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1357 | |
1358 /** | |
1359 * @} | |
1360 */ | |
1361 | |
1362 /** @addtogroup TIM_Exported_Functions_Group4 | |
1363 * @{ | |
1364 */ | |
1365 /* Timer Input Capture functions ***********************************************/ | |
1366 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); | |
1367 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); | |
1368 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); | |
1369 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); | |
1370 /* Blocking mode: Polling */ | |
1371 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1372 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1373 /* Non-Blocking mode: Interrupt */ | |
1374 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1375 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1376 /* Non-Blocking mode: DMA */ | |
1377 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); | |
1378 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1379 | |
1380 /** | |
1381 * @} | |
1382 */ | |
1383 | |
1384 /** @addtogroup TIM_Exported_Functions_Group5 | |
1385 * @{ | |
1386 */ | |
1387 /* Timer One Pulse functions ***************************************************/ | |
1388 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); | |
1389 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); | |
1390 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); | |
1391 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); | |
1392 /* Blocking mode: Polling */ | |
1393 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); | |
1394 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); | |
1395 | |
1396 /* Non-Blocking mode: Interrupt */ | |
1397 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); | |
1398 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); | |
1399 | |
1400 /** | |
1401 * @} | |
1402 */ | |
1403 | |
1404 /** @addtogroup TIM_Exported_Functions_Group6 | |
1405 * @{ | |
1406 */ | |
1407 /* Timer Encoder functions *****************************************************/ | |
1408 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); | |
1409 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); | |
1410 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); | |
1411 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); | |
1412 /* Blocking mode: Polling */ | |
1413 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1414 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1415 /* Non-Blocking mode: Interrupt */ | |
1416 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1417 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1418 /* Non-Blocking mode: DMA */ | |
1419 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); | |
1420 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1421 | |
1422 /** | |
1423 * @} | |
1424 */ | |
1425 | |
1426 /** @addtogroup TIM_Exported_Functions_Group7 | |
1427 * @{ | |
1428 */ | |
1429 /* Interrupt Handler functions **********************************************/ | |
1430 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); | |
1431 | |
1432 /** | |
1433 * @} | |
1434 */ | |
1435 | |
1436 /** @addtogroup TIM_Exported_Functions_Group8 | |
1437 * @{ | |
1438 */ | |
1439 /* Control functions *********************************************************/ | |
1440 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); | |
1441 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); | |
1442 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); | |
1443 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); | |
1444 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); | |
1445 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); | |
1446 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); | |
1447 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); | |
1448 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); | |
1449 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ | |
1450 uint32_t *BurstBuffer, uint32_t BurstLength); | |
1451 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); | |
1452 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ | |
1453 uint32_t *BurstBuffer, uint32_t BurstLength); | |
1454 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); | |
1455 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); | |
1456 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); | |
1457 | |
1458 /** | |
1459 * @} | |
1460 */ | |
1461 | |
1462 /** @addtogroup TIM_Exported_Functions_Group9 | |
1463 * @{ | |
1464 */ | |
1465 /* Callback in non blocking modes (Interrupt and DMA) *************************/ | |
1466 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); | |
1467 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); | |
1468 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); | |
1469 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); | |
1470 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); | |
1471 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); | |
1472 | |
1473 /** | |
1474 * @} | |
1475 */ | |
1476 | |
1477 /** @addtogroup TIM_Exported_Functions_Group10 | |
1478 * @{ | |
1479 */ | |
1480 /* Peripheral State functions **************************************************/ | |
1481 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); | |
1482 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); | |
1483 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); | |
1484 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); | |
1485 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); | |
1486 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); | |
1487 | |
1488 /** | |
1489 * @} | |
1490 */ | |
1491 | |
1492 /** | |
1493 * @} | |
1494 */ | |
1495 | |
1496 /* Private macros ------------------------------------------------------------*/ | |
1497 /** @defgroup TIM_Private_Macros TIM Private Macros | |
1498 * @{ | |
1499 */ | |
1500 | |
1501 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters | |
1502 * @{ | |
1503 */ | |
1504 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ | |
1505 ((MODE) == TIM_COUNTERMODE_DOWN) || \ | |
1506 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ | |
1507 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ | |
1508 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) | |
1509 | |
1510 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ | |
1511 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ | |
1512 ((DIV) == TIM_CLOCKDIVISION_DIV4)) | |
1513 | |
1514 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ | |
1515 ((MODE) == TIM_OCMODE_PWM2)) | |
1516 | |
1517 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ | |
1518 ((MODE) == TIM_OCMODE_ACTIVE) || \ | |
1519 ((MODE) == TIM_OCMODE_INACTIVE) || \ | |
1520 ((MODE) == TIM_OCMODE_TOGGLE) || \ | |
1521 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ | |
1522 ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) | |
1523 | |
1524 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ | |
1525 ((STATE) == TIM_OCFAST_ENABLE)) | |
1526 | |
1527 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ | |
1528 ((POLARITY) == TIM_OCPOLARITY_LOW)) | |
1529 | |
1530 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ | |
1531 ((POLARITY) == TIM_OCNPOLARITY_LOW)) | |
1532 | |
1533 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ | |
1534 ((STATE) == TIM_OCIDLESTATE_RESET)) | |
1535 | |
1536 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ | |
1537 ((STATE) == TIM_OCNIDLESTATE_RESET)) | |
1538 | |
1539 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ | |
1540 ((CHANNEL) == TIM_CHANNEL_2) || \ | |
1541 ((CHANNEL) == TIM_CHANNEL_3) || \ | |
1542 ((CHANNEL) == TIM_CHANNEL_4) || \ | |
1543 ((CHANNEL) == TIM_CHANNEL_ALL)) | |
1544 | |
1545 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ | |
1546 ((CHANNEL) == TIM_CHANNEL_2)) | |
1547 | |
1548 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ | |
1549 ((CHANNEL) == TIM_CHANNEL_2) || \ | |
1550 ((CHANNEL) == TIM_CHANNEL_3)) | |
1551 | |
1552 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ | |
1553 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ | |
1554 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) | |
1555 | |
1556 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ | |
1557 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ | |
1558 ((SELECTION) == TIM_ICSELECTION_TRC)) | |
1559 | |
1560 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ | |
1561 ((PRESCALER) == TIM_ICPSC_DIV2) || \ | |
1562 ((PRESCALER) == TIM_ICPSC_DIV4) || \ | |
1563 ((PRESCALER) == TIM_ICPSC_DIV8)) | |
1564 | |
1565 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ | |
1566 ((MODE) == TIM_OPMODE_REPETITIVE)) | |
1567 | |
1568 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) | |
1569 | |
1570 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ | |
1571 ((MODE) == TIM_ENCODERMODE_TI2) || \ | |
1572 ((MODE) == TIM_ENCODERMODE_TI12)) | |
1573 | |
1574 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) | |
1575 | |
1576 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ | |
1577 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ | |
1578 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ | |
1579 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ | |
1580 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ | |
1581 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ | |
1582 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ | |
1583 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ | |
1584 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ | |
1585 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) | |
1586 | |
1587 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ | |
1588 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ | |
1589 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ | |
1590 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ | |
1591 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) | |
1592 | |
1593 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ | |
1594 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ | |
1595 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ | |
1596 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) | |
1597 | |
1598 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) | |
1599 | |
1600 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ | |
1601 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) | |
1602 | |
1603 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ | |
1604 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) | |
1605 | |
1606 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ | |
1607 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ | |
1608 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ | |
1609 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) | |
1610 | |
1611 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) | |
1612 | |
1613 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ | |
1614 ((STATE) == TIM_OSSR_DISABLE)) | |
1615 | |
1616 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ | |
1617 ((STATE) == TIM_OSSI_DISABLE)) | |
1618 | |
1619 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ | |
1620 ((LEVEL) == TIM_LOCKLEVEL_1) || \ | |
1621 ((LEVEL) == TIM_LOCKLEVEL_2) || \ | |
1622 ((LEVEL) == TIM_LOCKLEVEL_3)) | |
1623 | |
1624 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ | |
1625 ((STATE) == TIM_BREAK_DISABLE)) | |
1626 | |
1627 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ | |
1628 ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) | |
1629 | |
1630 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ | |
1631 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) | |
1632 | |
1633 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ | |
1634 ((SOURCE) == TIM_TRGO_ENABLE) || \ | |
1635 ((SOURCE) == TIM_TRGO_UPDATE) || \ | |
1636 ((SOURCE) == TIM_TRGO_OC1) || \ | |
1637 ((SOURCE) == TIM_TRGO_OC1REF) || \ | |
1638 ((SOURCE) == TIM_TRGO_OC2REF) || \ | |
1639 ((SOURCE) == TIM_TRGO_OC3REF) || \ | |
1640 ((SOURCE) == TIM_TRGO_OC4REF)) | |
1641 | |
1642 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ | |
1643 ((MODE) == TIM_SLAVEMODE_GATED) || \ | |
1644 ((MODE) == TIM_SLAVEMODE_RESET) || \ | |
1645 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ | |
1646 ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) | |
1647 | |
1648 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ | |
1649 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) | |
1650 | |
1651 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ | |
1652 ((SELECTION) == TIM_TS_ITR1) || \ | |
1653 ((SELECTION) == TIM_TS_ITR2) || \ | |
1654 ((SELECTION) == TIM_TS_ITR3) || \ | |
1655 ((SELECTION) == TIM_TS_TI1F_ED) || \ | |
1656 ((SELECTION) == TIM_TS_TI1FP1) || \ | |
1657 ((SELECTION) == TIM_TS_TI2FP2) || \ | |
1658 ((SELECTION) == TIM_TS_ETRF)) | |
1659 | |
1660 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ | |
1661 ((SELECTION) == TIM_TS_ITR1) || \ | |
1662 ((SELECTION) == TIM_TS_ITR2) || \ | |
1663 ((SELECTION) == TIM_TS_ITR3) || \ | |
1664 ((SELECTION) == TIM_TS_NONE)) | |
1665 | |
1666 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ | |
1667 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ | |
1668 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ | |
1669 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ | |
1670 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) | |
1671 | |
1672 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ | |
1673 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ | |
1674 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ | |
1675 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) | |
1676 | |
1677 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) | |
1678 | |
1679 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ | |
1680 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) | |
1681 | |
1682 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ | |
1683 ((BASE) == TIM_DMABASE_CR2) || \ | |
1684 ((BASE) == TIM_DMABASE_SMCR) || \ | |
1685 ((BASE) == TIM_DMABASE_DIER) || \ | |
1686 ((BASE) == TIM_DMABASE_SR) || \ | |
1687 ((BASE) == TIM_DMABASE_EGR) || \ | |
1688 ((BASE) == TIM_DMABASE_CCMR1) || \ | |
1689 ((BASE) == TIM_DMABASE_CCMR2) || \ | |
1690 ((BASE) == TIM_DMABASE_CCER) || \ | |
1691 ((BASE) == TIM_DMABASE_CNT) || \ | |
1692 ((BASE) == TIM_DMABASE_PSC) || \ | |
1693 ((BASE) == TIM_DMABASE_ARR) || \ | |
1694 ((BASE) == TIM_DMABASE_RCR) || \ | |
1695 ((BASE) == TIM_DMABASE_CCR1) || \ | |
1696 ((BASE) == TIM_DMABASE_CCR2) || \ | |
1697 ((BASE) == TIM_DMABASE_CCR3) || \ | |
1698 ((BASE) == TIM_DMABASE_CCR4) || \ | |
1699 ((BASE) == TIM_DMABASE_BDTR) || \ | |
1700 ((BASE) == TIM_DMABASE_DCR) || \ | |
1701 ((BASE) == TIM_DMABASE_OR)) | |
1702 | |
1703 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ | |
1704 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ | |
1705 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ | |
1706 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ | |
1707 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ | |
1708 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ | |
1709 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ | |
1710 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ | |
1711 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ | |
1712 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ | |
1713 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ | |
1714 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ | |
1715 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ | |
1716 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ | |
1717 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ | |
1718 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ | |
1719 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ | |
1720 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) | |
1721 | |
1722 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) | |
1723 /** | |
1724 * @} | |
1725 */ | |
1726 | |
1727 /** @defgroup TIM_Mask_Definitions TIM Mask Definition | |
1728 * @{ | |
1729 */ | |
1730 /* The counter of a timer instance is disabled only if all the CCx and CCxN | |
1731 channels have been disabled */ | |
1732 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) | |
1733 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) | |
1734 /** | |
1735 * @} | |
1736 */ | |
1737 | |
1738 /** | |
1739 * @} | |
1740 */ | |
1741 | |
1742 /* Private functions ---------------------------------------------------------*/ | |
1743 /** @defgroup TIM_Private_Functions TIM Private Functions | |
1744 * @{ | |
1745 */ | |
1746 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); | |
1747 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); | |
1748 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); | |
1749 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); | |
1750 void TIM_DMAError(DMA_HandleTypeDef *hdma); | |
1751 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); | |
1752 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); | |
1753 /** | |
1754 * @} | |
1755 */ | |
1756 | |
1757 /** | |
1758 * @} | |
1759 */ | |
1760 | |
1761 /** | |
1762 * @} | |
1763 */ | |
1764 | |
1765 #ifdef __cplusplus | |
1766 } | |
1767 #endif | |
1768 | |
1769 #endif /* __STM32F4xx_HAL_TIM_H */ | |
1770 | |
1771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |