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Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_qspi.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of QSPI HAL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_HAL_QSPI_H | |
38 #define __STM32F4xx_HAL_QSPI_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ | |
45 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) | |
46 /* Includes ------------------------------------------------------------------*/ | |
47 #include "stm32f4xx_hal_def.h" | |
48 | |
49 /** @addtogroup STM32F4xx_HAL_Driver | |
50 * @{ | |
51 */ | |
52 | |
53 /** @addtogroup QSPI | |
54 * @{ | |
55 */ | |
56 | |
57 /* Exported types ------------------------------------------------------------*/ | |
58 /** @defgroup QSPI_Exported_Types QSPI Exported Types | |
59 * @{ | |
60 */ | |
61 | |
62 /** | |
63 * @brief QSPI Init structure definition | |
64 */ | |
65 | |
66 typedef struct | |
67 { | |
68 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. | |
69 This parameter can be a number between 0 and 255 */ | |
70 | |
71 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) | |
72 This parameter can be a value between 1 and 32 */ | |
73 | |
74 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to | |
75 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) | |
76 This parameter can be a value of @ref QSPI_SampleShifting */ | |
77 | |
78 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits | |
79 required to address the flash memory. The flash capacity can be up to 4GB | |
80 (addressed using 32 bits) in indirect mode, but the addressable space in | |
81 memory-mapped mode is limited to 256MB | |
82 This parameter can be a number between 0 and 31 */ | |
83 | |
84 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number | |
85 of clock cycles which the chip select must remain high between commands. | |
86 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ | |
87 | |
88 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. | |
89 This parameter can be a value of @ref QSPI_ClockMode */ | |
90 | |
91 uint32_t FlashID; /* Specifies the Flash which will be used, | |
92 This parameter can be a value of @ref QSPI_Flash_Select */ | |
93 | |
94 uint32_t DualFlash; /* Specifies the Dual Flash Mode State | |
95 This parameter can be a value of @ref QSPI_DualFlash_Mode */ | |
96 }QSPI_InitTypeDef; | |
97 | |
98 /** | |
99 * @brief HAL QSPI State structures definition | |
100 */ | |
101 typedef enum | |
102 { | |
103 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ | |
104 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ | |
105 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ | |
106 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ | |
107 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ | |
108 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ | |
109 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ | |
110 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ | |
111 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ | |
112 }HAL_QSPI_StateTypeDef; | |
113 | |
114 /** | |
115 * @brief QSPI Handle Structure definition | |
116 */ | |
117 typedef struct | |
118 { | |
119 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ | |
120 QSPI_InitTypeDef Init; /* QSPI communication parameters */ | |
121 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ | |
122 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ | |
123 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ | |
124 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ | |
125 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ | |
126 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ | |
127 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ | |
128 __IO HAL_LockTypeDef Lock; /* Locking object */ | |
129 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ | |
130 __IO uint32_t ErrorCode; /* QSPI Error code */ | |
131 uint32_t Timeout; /* Timeout for the QSPI memory access */ | |
132 }QSPI_HandleTypeDef; | |
133 | |
134 /** | |
135 * @brief QSPI Command structure definition | |
136 */ | |
137 typedef struct | |
138 { | |
139 uint32_t Instruction; /* Specifies the Instruction to be sent | |
140 This parameter can be a value (8-bit) between 0x00 and 0xFF */ | |
141 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) | |
142 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ | |
143 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) | |
144 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ | |
145 uint32_t AddressSize; /* Specifies the Address Size | |
146 This parameter can be a value of @ref QSPI_AddressSize */ | |
147 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size | |
148 This parameter can be a value of @ref QSPI_AlternateBytesSize */ | |
149 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. | |
150 This parameter can be a number between 0 and 31 */ | |
151 uint32_t InstructionMode; /* Specifies the Instruction Mode | |
152 This parameter can be a value of @ref QSPI_InstructionMode */ | |
153 uint32_t AddressMode; /* Specifies the Address Mode | |
154 This parameter can be a value of @ref QSPI_AddressMode */ | |
155 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode | |
156 This parameter can be a value of @ref QSPI_AlternateBytesMode */ | |
157 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) | |
158 This parameter can be a value of @ref QSPI_DataMode */ | |
159 uint32_t NbData; /* Specifies the number of data to transfer. | |
160 This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length | |
161 until end of memory)*/ | |
162 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase | |
163 This parameter can be a value of @ref QSPI_DdrMode */ | |
164 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of | |
165 system clock in DDR mode. | |
166 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ | |
167 uint32_t SIOOMode; /* Specifies the send instruction only once mode | |
168 This parameter can be a value of @ref QSPI_SIOOMode */ | |
169 }QSPI_CommandTypeDef; | |
170 | |
171 /** | |
172 * @brief QSPI Auto Polling mode configuration structure definition | |
173 */ | |
174 typedef struct | |
175 { | |
176 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. | |
177 This parameter can be any value between 0 and 0xFFFFFFFFU */ | |
178 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. | |
179 This parameter can be any value between 0 and 0xFFFFFFFFU */ | |
180 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. | |
181 This parameter can be any value between 0 and 0xFFFFU */ | |
182 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. | |
183 This parameter can be any value between 1 and 4 */ | |
184 uint32_t MatchMode; /* Specifies the method used for determining a match. | |
185 This parameter can be a value of @ref QSPI_MatchMode */ | |
186 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. | |
187 This parameter can be a value of @ref QSPI_AutomaticStop */ | |
188 }QSPI_AutoPollingTypeDef; | |
189 | |
190 /** | |
191 * @brief QSPI Memory Mapped mode configuration structure definition | |
192 */ | |
193 typedef struct | |
194 { | |
195 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. | |
196 This parameter can be any value between 0 and 0xFFFFU */ | |
197 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. | |
198 This parameter can be a value of @ref QSPI_TimeOutActivation */ | |
199 }QSPI_MemoryMappedTypeDef; | |
200 /** | |
201 * @} | |
202 */ | |
203 | |
204 /* Exported constants --------------------------------------------------------*/ | |
205 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants | |
206 * @{ | |
207 */ | |
208 /** @defgroup QSPI_ErrorCode QSPI Error Code | |
209 * @{ | |
210 */ | |
211 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ | |
212 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ | |
213 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ | |
214 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ | |
215 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ | |
216 /** | |
217 * @} | |
218 */ | |
219 | |
220 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting | |
221 * @{ | |
222 */ | |
223 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ | |
224 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ | |
225 /** | |
226 * @} | |
227 */ | |
228 | |
229 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time | |
230 * @{ | |
231 */ | |
232 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ | |
233 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ | |
234 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ | |
235 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ | |
236 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ | |
237 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ | |
238 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ | |
239 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ | |
240 /** | |
241 * @} | |
242 */ | |
243 | |
244 /** @defgroup QSPI_ClockMode QSPI Clock Mode | |
245 * @{ | |
246 */ | |
247 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ | |
248 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ | |
249 /** | |
250 * @} | |
251 */ | |
252 | |
253 /** @defgroup QSPI_Flash_Select QSPI Flash Select | |
254 * @{ | |
255 */ | |
256 #define QSPI_FLASH_ID_1 0x00000000U | |
257 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) | |
258 /** | |
259 * @} | |
260 */ | |
261 | |
262 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode | |
263 * @{ | |
264 */ | |
265 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) | |
266 #define QSPI_DUALFLASH_DISABLE 0x00000000U | |
267 /** | |
268 * @} | |
269 */ | |
270 | |
271 /** @defgroup QSPI_AddressSize QSPI Address Size | |
272 * @{ | |
273 */ | |
274 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ | |
275 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ | |
276 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ | |
277 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ | |
278 /** | |
279 * @} | |
280 */ | |
281 | |
282 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size | |
283 * @{ | |
284 */ | |
285 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ | |
286 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ | |
287 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ | |
288 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ | |
289 /** | |
290 * @} | |
291 */ | |
292 | |
293 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode | |
294 * @{ | |
295 */ | |
296 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ | |
297 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ | |
298 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ | |
299 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ | |
300 /** | |
301 * @} | |
302 */ | |
303 | |
304 /** @defgroup QSPI_AddressMode QSPI Address Mode | |
305 * @{ | |
306 */ | |
307 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ | |
308 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ | |
309 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ | |
310 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ | |
311 /** | |
312 * @} | |
313 */ | |
314 | |
315 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode | |
316 * @{ | |
317 */ | |
318 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ | |
319 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ | |
320 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ | |
321 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ | |
322 /** | |
323 * @} | |
324 */ | |
325 | |
326 /** @defgroup QSPI_DataMode QSPI Data Mode | |
327 * @{ | |
328 */ | |
329 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ | |
330 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ | |
331 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ | |
332 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ | |
333 /** | |
334 * @} | |
335 */ | |
336 | |
337 /** @defgroup QSPI_DdrMode QSPI Ddr Mode | |
338 * @{ | |
339 */ | |
340 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ | |
341 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ | |
342 /** | |
343 * @} | |
344 */ | |
345 | |
346 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle | |
347 * @{ | |
348 */ | |
349 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ | |
350 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/ | |
351 /** | |
352 * @} | |
353 */ | |
354 | |
355 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode | |
356 * @{ | |
357 */ | |
358 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ | |
359 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ | |
360 /** | |
361 * @} | |
362 */ | |
363 | |
364 /** @defgroup QSPI_MatchMode QSPI Match Mode | |
365 * @{ | |
366 */ | |
367 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ | |
368 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ | |
369 /** | |
370 * @} | |
371 */ | |
372 | |
373 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop | |
374 * @{ | |
375 */ | |
376 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ | |
377 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ | |
378 /** | |
379 * @} | |
380 */ | |
381 | |
382 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation | |
383 * @{ | |
384 */ | |
385 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ | |
386 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ | |
387 /** | |
388 * @} | |
389 */ | |
390 | |
391 /** @defgroup QSPI_Flags QSPI Flags | |
392 * @{ | |
393 */ | |
394 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ | |
395 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ | |
396 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ | |
397 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ | |
398 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ | |
399 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ | |
400 /** | |
401 * @} | |
402 */ | |
403 | |
404 /** @defgroup QSPI_Interrupts QSPI Interrupts | |
405 * @{ | |
406 */ | |
407 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ | |
408 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ | |
409 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ | |
410 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ | |
411 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ | |
412 /** | |
413 * @} | |
414 */ | |
415 | |
416 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition | |
417 * @{ | |
418 */ | |
419 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ | |
420 /** | |
421 * @} | |
422 */ | |
423 | |
424 /** | |
425 * @} | |
426 */ | |
427 | |
428 /* Exported macros -----------------------------------------------------------*/ | |
429 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros | |
430 * @{ | |
431 */ | |
432 | |
433 /** @brief Reset QSPI handle state | |
434 * @param __HANDLE__ QSPI handle. | |
435 * @retval None | |
436 */ | |
437 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) | |
438 | |
439 /** @brief Enable QSPI | |
440 * @param __HANDLE__ specifies the QSPI Handle. | |
441 * @retval None | |
442 */ | |
443 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) | |
444 | |
445 /** @brief Disable QSPI | |
446 * @param __HANDLE__ specifies the QSPI Handle. | |
447 * @retval None | |
448 */ | |
449 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) | |
450 | |
451 /** @brief Enables the specified QSPI interrupt. | |
452 * @param __HANDLE__ specifies the QSPI Handle. | |
453 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. | |
454 * This parameter can be one of the following values: | |
455 * @arg QSPI_IT_TO: QSPI Time out interrupt | |
456 * @arg QSPI_IT_SM: QSPI Status match interrupt | |
457 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt | |
458 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt | |
459 * @arg QSPI_IT_TE: QSPI Transfer error interrupt | |
460 * @retval None | |
461 */ | |
462 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) | |
463 | |
464 | |
465 /** @brief Disables the specified QSPI interrupt. | |
466 * @param __HANDLE__ specifies the QSPI Handle. | |
467 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. | |
468 * This parameter can be one of the following values: | |
469 * @arg QSPI_IT_TO: QSPI Timeout interrupt | |
470 * @arg QSPI_IT_SM: QSPI Status match interrupt | |
471 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt | |
472 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt | |
473 * @arg QSPI_IT_TE: QSPI Transfer error interrupt | |
474 * @retval None | |
475 */ | |
476 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) | |
477 | |
478 /** @brief Checks whether the specified QSPI interrupt source is enabled. | |
479 * @param __HANDLE__ specifies the QSPI Handle. | |
480 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. | |
481 * This parameter can be one of the following values: | |
482 * @arg QSPI_IT_TO: QSPI Time out interrupt | |
483 * @arg QSPI_IT_SM: QSPI Status match interrupt | |
484 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt | |
485 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt | |
486 * @arg QSPI_IT_TE: QSPI Transfer error interrupt | |
487 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). | |
488 */ | |
489 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) | |
490 | |
491 /** | |
492 * @brief Get the selected QSPI's flag status. | |
493 * @param __HANDLE__ specifies the QSPI Handle. | |
494 * @param __FLAG__ specifies the QSPI flag to check. | |
495 * This parameter can be one of the following values: | |
496 * @arg QSPI_FLAG_BUSY: QSPI Busy flag | |
497 * @arg QSPI_FLAG_TO: QSPI Time out flag | |
498 * @arg QSPI_FLAG_SM: QSPI Status match flag | |
499 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag | |
500 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag | |
501 * @arg QSPI_FLAG_TE: QSPI Transfer error flag | |
502 * @retval None | |
503 */ | |
504 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) | |
505 | |
506 /** @brief Clears the specified QSPI's flag status. | |
507 * @param __HANDLE__ specifies the QSPI Handle. | |
508 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set | |
509 * This parameter can be one of the following values: | |
510 * @arg QSPI_FLAG_TO: QSPI Time out flag | |
511 * @arg QSPI_FLAG_SM: QSPI Status match flag | |
512 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag | |
513 * @arg QSPI_FLAG_TE: QSPI Transfer error flag | |
514 * @retval None | |
515 */ | |
516 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) | |
517 /** | |
518 * @} | |
519 */ | |
520 | |
521 /* Exported functions --------------------------------------------------------*/ | |
522 /** @addtogroup QSPI_Exported_Functions | |
523 * @{ | |
524 */ | |
525 | |
526 /** @addtogroup QSPI_Exported_Functions_Group1 | |
527 * @{ | |
528 */ | |
529 /* Initialization/de-initialization functions ********************************/ | |
530 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); | |
531 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); | |
532 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); | |
533 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); | |
534 /** | |
535 * @} | |
536 */ | |
537 | |
538 /** @addtogroup QSPI_Exported_Functions_Group2 | |
539 * @{ | |
540 */ | |
541 /* IO operation functions *****************************************************/ | |
542 /* QSPI IRQ handler method */ | |
543 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); | |
544 | |
545 /* QSPI indirect mode */ | |
546 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); | |
547 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); | |
548 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); | |
549 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); | |
550 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); | |
551 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); | |
552 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); | |
553 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); | |
554 | |
555 /* QSPI status flag polling mode */ | |
556 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); | |
557 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); | |
558 | |
559 /* QSPI memory-mapped mode */ | |
560 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); | |
561 /** | |
562 * @} | |
563 */ | |
564 | |
565 /** @addtogroup QSPI_Exported_Functions_Group3 | |
566 * @{ | |
567 */ | |
568 /* Callback functions in non-blocking modes ***********************************/ | |
569 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); | |
570 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); | |
571 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); | |
572 | |
573 /* QSPI indirect mode */ | |
574 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); | |
575 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); | |
576 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); | |
577 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); | |
578 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); | |
579 | |
580 /* QSPI status flag polling mode */ | |
581 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); | |
582 | |
583 /* QSPI memory-mapped mode */ | |
584 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); | |
585 /** | |
586 * @} | |
587 */ | |
588 | |
589 /** @addtogroup QSPI_Exported_Functions_Group4 | |
590 * @{ | |
591 */ | |
592 /* Peripheral Control and State functions ************************************/ | |
593 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); | |
594 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); | |
595 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); | |
596 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); | |
597 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); | |
598 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); | |
599 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); | |
600 /** | |
601 * @} | |
602 */ | |
603 | |
604 /* Private macros ------------------------------------------------------------*/ | |
605 /** @defgroup QSPI_Private_Macros QSPI Private Macros | |
606 * @{ | |
607 */ | |
608 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler | |
609 * @{ | |
610 */ | |
611 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) | |
612 /** | |
613 * @} | |
614 */ | |
615 | |
616 /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold | |
617 * @{ | |
618 */ | |
619 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) | |
620 /** | |
621 * @} | |
622 */ | |
623 | |
624 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ | |
625 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) | |
626 | |
627 /** @defgroup QSPI_FlashSize QSPI Flash Size | |
628 * @{ | |
629 */ | |
630 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) | |
631 /** | |
632 * @} | |
633 */ | |
634 | |
635 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ | |
636 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ | |
637 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ | |
638 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ | |
639 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ | |
640 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ | |
641 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ | |
642 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) | |
643 | |
644 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ | |
645 ((CLKMODE) == QSPI_CLOCK_MODE_3)) | |
646 | |
647 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \ | |
648 ((FLA) == QSPI_FLASH_ID_2)) | |
649 | |
650 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ | |
651 ((MODE) == QSPI_DUALFLASH_DISABLE)) | |
652 | |
653 | |
654 /** @defgroup QSPI_Instruction QSPI Instruction | |
655 * @{ | |
656 */ | |
657 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) | |
658 /** | |
659 * @} | |
660 */ | |
661 | |
662 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ | |
663 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ | |
664 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ | |
665 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) | |
666 | |
667 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ | |
668 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ | |
669 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ | |
670 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) | |
671 | |
672 | |
673 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles | |
674 * @{ | |
675 */ | |
676 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) | |
677 /** | |
678 * @} | |
679 */ | |
680 | |
681 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ | |
682 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ | |
683 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ | |
684 ((MODE) == QSPI_INSTRUCTION_4_LINES)) | |
685 | |
686 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ | |
687 ((MODE) == QSPI_ADDRESS_1_LINE) || \ | |
688 ((MODE) == QSPI_ADDRESS_2_LINES) || \ | |
689 ((MODE) == QSPI_ADDRESS_4_LINES)) | |
690 | |
691 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ | |
692 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ | |
693 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ | |
694 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) | |
695 | |
696 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ | |
697 ((MODE) == QSPI_DATA_1_LINE) || \ | |
698 ((MODE) == QSPI_DATA_2_LINES) || \ | |
699 ((MODE) == QSPI_DATA_4_LINES)) | |
700 | |
701 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ | |
702 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) | |
703 | |
704 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ | |
705 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) | |
706 | |
707 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ | |
708 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) | |
709 | |
710 /** @defgroup QSPI_Interval QSPI Interval | |
711 * @{ | |
712 */ | |
713 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) | |
714 /** | |
715 * @} | |
716 */ | |
717 | |
718 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size | |
719 * @{ | |
720 */ | |
721 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) | |
722 /** | |
723 * @} | |
724 */ | |
725 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ | |
726 ((MODE) == QSPI_MATCH_MODE_OR)) | |
727 | |
728 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ | |
729 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) | |
730 | |
731 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ | |
732 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) | |
733 | |
734 /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period | |
735 * @{ | |
736 */ | |
737 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) | |
738 /** | |
739 * @} | |
740 */ | |
741 | |
742 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \ | |
743 ((FLAG) == QSPI_FLAG_TO) || \ | |
744 ((FLAG) == QSPI_FLAG_SM) || \ | |
745 ((FLAG) == QSPI_FLAG_FT) || \ | |
746 ((FLAG) == QSPI_FLAG_TC) || \ | |
747 ((FLAG) == QSPI_FLAG_TE)) | |
748 | |
749 #define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U)) | |
750 /** | |
751 * @} | |
752 */ | |
753 | |
754 /* Private functions ---------------------------------------------------------*/ | |
755 /** @defgroup QSPI_Private_Functions QSPI Private Functions | |
756 * @{ | |
757 */ | |
758 | |
759 /** | |
760 * @} | |
761 */ | |
762 | |
763 /** | |
764 * @} | |
765 */ | |
766 | |
767 /** | |
768 * @} | |
769 */ | |
770 | |
771 /** | |
772 * @} | |
773 */ | |
774 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || | |
775 STM32F413xx || STM32F423xx */ | |
776 | |
777 #ifdef __cplusplus | |
778 } | |
779 #endif | |
780 | |
781 #endif /* __STM32F4xx_HAL_QSPI_H */ | |
782 | |
783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |