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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_nor.h
4 * @author MCD Application Team
5 * @brief Header file of NOR HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_HAL_NOR_H
38 #define __STM32F4xx_HAL_NOR_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
46 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
47 #include "stm32f4xx_ll_fsmc.h"
48 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
49
50 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
51 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
52 #include "stm32f4xx_ll_fmc.h"
53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
54
55 /** @addtogroup STM32F4xx_HAL_Driver
56 * @{
57 */
58
59 /** @addtogroup NOR
60 * @{
61 */
62
63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
64 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
65 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
66 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
67
68 /* Exported typedef ----------------------------------------------------------*/
69 /** @defgroup NOR_Exported_Types NOR Exported Types
70 * @{
71 */
72
73 /**
74 * @brief HAL SRAM State structures definition
75 */
76 typedef enum
77 {
78 HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
79 HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
80 HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
81 HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
82 HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
83 }HAL_NOR_StateTypeDef;
84
85 /**
86 * @brief FMC NOR Status typedef
87 */
88 typedef enum
89 {
90 HAL_NOR_STATUS_SUCCESS = 0U,
91 HAL_NOR_STATUS_ONGOING,
92 HAL_NOR_STATUS_ERROR,
93 HAL_NOR_STATUS_TIMEOUT
94 }HAL_NOR_StatusTypeDef;
95
96 /**
97 * @brief FMC NOR ID typedef
98 */
99 typedef struct
100 {
101 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
102
103 uint16_t Device_Code1;
104
105 uint16_t Device_Code2;
106
107 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
108 These codes can be accessed by performing read operations with specific
109 control signals and addresses set.They can also be accessed by issuing
110 an Auto Select command */
111 }NOR_IDTypeDef;
112
113 /**
114 * @brief FMC NOR CFI typedef
115 */
116 typedef struct
117 {
118 /*!< Defines the information stored in the memory's Common flash interface
119 which contains a description of various electrical and timing parameters,
120 density information and functions supported by the memory */
121
122 uint16_t CFI_1;
123
124 uint16_t CFI_2;
125
126 uint16_t CFI_3;
127
128 uint16_t CFI_4;
129 }NOR_CFITypeDef;
130
131 /**
132 * @brief NOR handle Structure definition
133 */
134 typedef struct
135 {
136 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
137
138 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
139
140 FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
141
142 HAL_LockTypeDef Lock; /*!< NOR locking object */
143
144 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
145
146 }NOR_HandleTypeDef;
147 /**
148 * @}
149 */
150
151 /* Exported constants --------------------------------------------------------*/
152 /* Exported macros ------------------------------------------------------------*/
153 /** @defgroup NOR_Exported_Macros NOR Exported Macros
154 * @{
155 */
156 /** @brief Reset NOR handle state
157 * @param __HANDLE__ specifies the NOR handle.
158 * @retval None
159 */
160 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
161 /**
162 * @}
163 */
164
165 /* Exported functions --------------------------------------------------------*/
166 /** @addtogroup NOR_Exported_Functions
167 * @{
168 */
169
170 /** @addtogroup NOR_Exported_Functions_Group1
171 * @{
172 */
173 /* Initialization/de-initialization functions ********************************/
174 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
175 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
176 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
177 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
178 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
179 /**
180 * @}
181 */
182
183 /** @addtogroup NOR_Exported_Functions_Group2
184 * @{
185 */
186 /* I/O operation functions ***************************************************/
187 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
188 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
189 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
190 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
191
192 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
193 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
194
195 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
196 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
197 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
198 /**
199 * @}
200 */
201
202 /** @addtogroup NOR_Exported_Functions_Group3
203 * @{
204 */
205 /* NOR Control functions *****************************************************/
206 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
207 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
208 /**
209 * @}
210 */
211
212 /** @addtogroup NOR_Exported_Functions_Group4
213 * @{
214 */
215 /* NOR State functions ********************************************************/
216 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
217 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
218 /**
219 * @}
220 */
221
222 /**
223 * @}
224 */
225
226 /* Private types -------------------------------------------------------------*/
227 /* Private variables ---------------------------------------------------------*/
228 /* Private constants ---------------------------------------------------------*/
229 /** @defgroup NOR_Private_Constants NOR Private Constants
230 * @{
231 */
232 /* NOR device IDs addresses */
233 #define MC_ADDRESS ((uint16_t)0x0000)
234 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
235 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
236 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
237
238 /* NOR CFI IDs addresses */
239 #define CFI1_ADDRESS ((uint16_t)0x0061)
240 #define CFI2_ADDRESS ((uint16_t)0x0062)
241 #define CFI3_ADDRESS ((uint16_t)0x0063)
242 #define CFI4_ADDRESS ((uint16_t)0x0064)
243
244 /* NOR operation wait timeout */
245 #define NOR_TMEOUT ((uint16_t)0xFFFF)
246
247 /* NOR memory data width */
248 #define NOR_MEMORY_8B ((uint8_t)0x00)
249 #define NOR_MEMORY_16B ((uint8_t)0x01)
250
251 /* NOR memory device read/write start address */
252 #define NOR_MEMORY_ADRESS1 0x60000000U
253 #define NOR_MEMORY_ADRESS2 0x64000000U
254 #define NOR_MEMORY_ADRESS3 0x68000000U
255 #define NOR_MEMORY_ADRESS4 0x6C000000U
256 /**
257 * @}
258 */
259
260 /* Private macros ------------------------------------------------------------*/
261 /** @defgroup NOR_Private_Macros NOR Private Macros
262 * @{
263 */
264 /**
265 * @brief NOR memory address shifting.
266 * @param __NOR_ADDRESS__ NOR base address
267 * @param NOR_MEMORY_WIDTH NOR memory width
268 * @param ADDRESS NOR memory address
269 * @retval NOR shifted address value
270 */
271 #define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\
272 ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
273
274 /**
275 * @brief NOR memory write data to specified address.
276 * @param ADDRESS NOR memory address
277 * @param DATA Data to write
278 * @retval None
279 */
280 #define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
281
282 /**
283 * @}
284 */
285 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
286 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
287 STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
288 STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
289 /**
290 * @}
291 */
292
293 /**
294 * @}
295 */
296
297 #ifdef __cplusplus
298 }
299 #endif
300
301 #endif /* __STM32F4xx_HAL_NOR_H */
302
303 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/