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comparison Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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127:1369f8660eaa | 128:c78bcbd5deda |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_eth.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of ETH HAL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_HAL_ETH_H | |
38 #define __STM32F4xx_HAL_ETH_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ | |
45 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) | |
46 /* Includes ------------------------------------------------------------------*/ | |
47 #include "stm32f4xx_hal_def.h" | |
48 | |
49 /** @addtogroup STM32F4xx_HAL_Driver | |
50 * @{ | |
51 */ | |
52 | |
53 /** @addtogroup ETH | |
54 * @{ | |
55 */ | |
56 | |
57 /** @addtogroup ETH_Private_Macros | |
58 * @{ | |
59 */ | |
60 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) | |
61 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ | |
62 ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) | |
63 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ | |
64 ((SPEED) == ETH_SPEED_100M)) | |
65 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ | |
66 ((MODE) == ETH_MODE_HALFDUPLEX)) | |
67 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ | |
68 ((MODE) == ETH_RXINTERRUPT_MODE)) | |
69 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ | |
70 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) | |
71 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ | |
72 ((MODE) == ETH_MEDIA_INTERFACE_RMII)) | |
73 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ | |
74 ((CMD) == ETH_WATCHDOG_DISABLE)) | |
75 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ | |
76 ((CMD) == ETH_JABBER_DISABLE)) | |
77 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ | |
78 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ | |
79 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ | |
80 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ | |
81 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ | |
82 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ | |
83 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ | |
84 ((GAP) == ETH_INTERFRAMEGAP_40BIT)) | |
85 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ | |
86 ((CMD) == ETH_CARRIERSENCE_DISABLE)) | |
87 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ | |
88 ((CMD) == ETH_RECEIVEOWN_DISABLE)) | |
89 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ | |
90 ((CMD) == ETH_LOOPBACKMODE_DISABLE)) | |
91 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ | |
92 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) | |
93 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ | |
94 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) | |
95 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ | |
96 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) | |
97 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ | |
98 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ | |
99 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ | |
100 ((LIMIT) == ETH_BACKOFFLIMIT_1)) | |
101 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ | |
102 ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) | |
103 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ | |
104 ((CMD) == ETH_RECEIVEAll_DISABLE)) | |
105 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ | |
106 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ | |
107 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) | |
108 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ | |
109 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ | |
110 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) | |
111 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ | |
112 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) | |
113 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ | |
114 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) | |
115 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ | |
116 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) | |
117 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ | |
118 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ | |
119 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ | |
120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) | |
121 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ | |
122 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ | |
123 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) | |
124 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) | |
125 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ | |
126 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) | |
127 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ | |
128 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ | |
129 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ | |
130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) | |
131 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ | |
132 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) | |
133 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ | |
134 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) | |
135 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ | |
136 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) | |
137 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ | |
138 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) | |
139 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) | |
140 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ | |
141 ((ADDRESS) == ETH_MAC_ADDRESS1) || \ | |
142 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ | |
143 ((ADDRESS) == ETH_MAC_ADDRESS3)) | |
144 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ | |
145 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ | |
146 ((ADDRESS) == ETH_MAC_ADDRESS3)) | |
147 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ | |
148 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) | |
149 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ | |
150 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ | |
151 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ | |
152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ | |
153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ | |
154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) | |
155 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ | |
156 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) | |
157 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ | |
158 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) | |
159 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ | |
160 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) | |
161 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ | |
162 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) | |
163 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ | |
164 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ | |
165 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ | |
166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ | |
167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ | |
168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ | |
169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ | |
170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) | |
171 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ | |
172 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) | |
173 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ | |
174 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) | |
175 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ | |
176 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ | |
177 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ | |
178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) | |
179 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ | |
180 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) | |
181 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ | |
182 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) | |
183 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ | |
184 ((CMD) == ETH_FIXEDBURST_DISABLE)) | |
185 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ | |
186 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ | |
187 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ | |
188 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ | |
189 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ | |
190 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ | |
191 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ | |
192 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ | |
193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ | |
194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ | |
195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ | |
196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) | |
197 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ | |
198 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ | |
199 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ | |
200 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ | |
201 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ | |
202 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ | |
203 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ | |
204 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ | |
205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ | |
206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ | |
207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ | |
208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) | |
209 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) | |
210 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ | |
211 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ | |
212 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ | |
213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ | |
214 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) | |
215 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ | |
216 ((FLAG) == ETH_DMATXDESC_IC) || \ | |
217 ((FLAG) == ETH_DMATXDESC_LS) || \ | |
218 ((FLAG) == ETH_DMATXDESC_FS) || \ | |
219 ((FLAG) == ETH_DMATXDESC_DC) || \ | |
220 ((FLAG) == ETH_DMATXDESC_DP) || \ | |
221 ((FLAG) == ETH_DMATXDESC_TTSE) || \ | |
222 ((FLAG) == ETH_DMATXDESC_TER) || \ | |
223 ((FLAG) == ETH_DMATXDESC_TCH) || \ | |
224 ((FLAG) == ETH_DMATXDESC_TTSS) || \ | |
225 ((FLAG) == ETH_DMATXDESC_IHE) || \ | |
226 ((FLAG) == ETH_DMATXDESC_ES) || \ | |
227 ((FLAG) == ETH_DMATXDESC_JT) || \ | |
228 ((FLAG) == ETH_DMATXDESC_FF) || \ | |
229 ((FLAG) == ETH_DMATXDESC_PCE) || \ | |
230 ((FLAG) == ETH_DMATXDESC_LCA) || \ | |
231 ((FLAG) == ETH_DMATXDESC_NC) || \ | |
232 ((FLAG) == ETH_DMATXDESC_LCO) || \ | |
233 ((FLAG) == ETH_DMATXDESC_EC) || \ | |
234 ((FLAG) == ETH_DMATXDESC_VF) || \ | |
235 ((FLAG) == ETH_DMATXDESC_CC) || \ | |
236 ((FLAG) == ETH_DMATXDESC_ED) || \ | |
237 ((FLAG) == ETH_DMATXDESC_UF) || \ | |
238 ((FLAG) == ETH_DMATXDESC_DB)) | |
239 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ | |
240 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) | |
241 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ | |
242 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ | |
243 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ | |
244 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) | |
245 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) | |
246 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ | |
247 ((FLAG) == ETH_DMARXDESC_AFM) || \ | |
248 ((FLAG) == ETH_DMARXDESC_ES) || \ | |
249 ((FLAG) == ETH_DMARXDESC_DE) || \ | |
250 ((FLAG) == ETH_DMARXDESC_SAF) || \ | |
251 ((FLAG) == ETH_DMARXDESC_LE) || \ | |
252 ((FLAG) == ETH_DMARXDESC_OE) || \ | |
253 ((FLAG) == ETH_DMARXDESC_VLAN) || \ | |
254 ((FLAG) == ETH_DMARXDESC_FS) || \ | |
255 ((FLAG) == ETH_DMARXDESC_LS) || \ | |
256 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ | |
257 ((FLAG) == ETH_DMARXDESC_LC) || \ | |
258 ((FLAG) == ETH_DMARXDESC_FT) || \ | |
259 ((FLAG) == ETH_DMARXDESC_RWT) || \ | |
260 ((FLAG) == ETH_DMARXDESC_RE) || \ | |
261 ((FLAG) == ETH_DMARXDESC_DBE) || \ | |
262 ((FLAG) == ETH_DMARXDESC_CE) || \ | |
263 ((FLAG) == ETH_DMARXDESC_MAMPCE)) | |
264 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ | |
265 ((BUFFER) == ETH_DMARXDESC_BUFFER2)) | |
266 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ | |
267 ((FLAG) == ETH_PMT_FLAG_MPR)) | |
268 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) | |
269 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ | |
270 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ | |
271 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ | |
272 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ | |
273 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ | |
274 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ | |
275 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ | |
276 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ | |
277 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ | |
278 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ | |
279 ((FLAG) == ETH_DMA_FLAG_T)) | |
280 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) | |
281 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ | |
282 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ | |
283 ((IT) == ETH_MAC_IT_PMT)) | |
284 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ | |
285 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ | |
286 ((FLAG) == ETH_MAC_FLAG_PMT)) | |
287 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) | |
288 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ | |
289 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ | |
290 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ | |
291 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ | |
292 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ | |
293 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ | |
294 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ | |
295 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ | |
296 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) | |
297 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ | |
298 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) | |
299 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ | |
300 ((IT) != 0x00U)) | |
301 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ | |
302 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ | |
303 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) | |
304 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ | |
305 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) | |
306 | |
307 /** | |
308 * @} | |
309 */ | |
310 | |
311 /** @addtogroup ETH_Private_Defines | |
312 * @{ | |
313 */ | |
314 /* Delay to wait when writing to some Ethernet registers */ | |
315 #define ETH_REG_WRITE_DELAY 0x00000001U | |
316 | |
317 /* ETHERNET Errors */ | |
318 #define ETH_SUCCESS 0U | |
319 #define ETH_ERROR 1U | |
320 | |
321 /* ETHERNET DMA Tx descriptors Collision Count Shift */ | |
322 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U | |
323 | |
324 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ | |
325 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U | |
326 | |
327 /* ETHERNET DMA Rx descriptors Frame Length Shift */ | |
328 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U | |
329 | |
330 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ | |
331 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U | |
332 | |
333 /* ETHERNET DMA Rx descriptors Frame length Shift */ | |
334 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U | |
335 | |
336 /* ETHERNET MAC address offsets */ | |
337 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ | |
338 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ | |
339 | |
340 /* ETHERNET MACMIIAR register Mask */ | |
341 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U | |
342 | |
343 /* ETHERNET MACCR register Mask */ | |
344 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU | |
345 | |
346 /* ETHERNET MACFCR register Mask */ | |
347 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U | |
348 | |
349 /* ETHERNET DMAOMR register Mask */ | |
350 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U | |
351 | |
352 /* ETHERNET Remote Wake-up frame register length */ | |
353 #define ETH_WAKEUP_REGISTER_LENGTH 8U | |
354 | |
355 /* ETHERNET Missed frames counter Shift */ | |
356 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U | |
357 /** | |
358 * @} | |
359 */ | |
360 | |
361 /* Exported types ------------------------------------------------------------*/ | |
362 /** @defgroup ETH_Exported_Types ETH Exported Types | |
363 * @{ | |
364 */ | |
365 | |
366 /** | |
367 * @brief HAL State structures definition | |
368 */ | |
369 typedef enum | |
370 { | |
371 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ | |
372 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ | |
373 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ | |
374 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ | |
375 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ | |
376 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ | |
377 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ | |
378 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ | |
379 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ | |
380 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ | |
381 }HAL_ETH_StateTypeDef; | |
382 | |
383 /** | |
384 * @brief ETH Init Structure definition | |
385 */ | |
386 | |
387 typedef struct | |
388 { | |
389 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY | |
390 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) | |
391 and the mode (half/full-duplex). | |
392 This parameter can be a value of @ref ETH_AutoNegotiation */ | |
393 | |
394 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. | |
395 This parameter can be a value of @ref ETH_Speed */ | |
396 | |
397 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode | |
398 This parameter can be a value of @ref ETH_Duplex_Mode */ | |
399 | |
400 uint16_t PhyAddress; /*!< Ethernet PHY address. | |
401 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ | |
402 | |
403 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ | |
404 | |
405 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. | |
406 This parameter can be a value of @ref ETH_Rx_Mode */ | |
407 | |
408 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. | |
409 This parameter can be a value of @ref ETH_Checksum_Mode */ | |
410 | |
411 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. | |
412 This parameter can be a value of @ref ETH_Media_Interface */ | |
413 | |
414 } ETH_InitTypeDef; | |
415 | |
416 | |
417 /** | |
418 * @brief ETH MAC Configuration Structure definition | |
419 */ | |
420 | |
421 typedef struct | |
422 { | |
423 uint32_t Watchdog; /*!< Selects or not the Watchdog timer | |
424 When enabled, the MAC allows no more then 2048 bytes to be received. | |
425 When disabled, the MAC can receive up to 16384 bytes. | |
426 This parameter can be a value of @ref ETH_Watchdog */ | |
427 | |
428 uint32_t Jabber; /*!< Selects or not Jabber timer | |
429 When enabled, the MAC allows no more then 2048 bytes to be sent. | |
430 When disabled, the MAC can send up to 16384 bytes. | |
431 This parameter can be a value of @ref ETH_Jabber */ | |
432 | |
433 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. | |
434 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ | |
435 | |
436 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. | |
437 This parameter can be a value of @ref ETH_Carrier_Sense */ | |
438 | |
439 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, | |
440 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted | |
441 in Half-Duplex mode. | |
442 This parameter can be a value of @ref ETH_Receive_Own */ | |
443 | |
444 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. | |
445 This parameter can be a value of @ref ETH_Loop_Back_Mode */ | |
446 | |
447 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. | |
448 This parameter can be a value of @ref ETH_Checksum_Offload */ | |
449 | |
450 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, | |
451 when a collision occurs (Half-Duplex mode). | |
452 This parameter can be a value of @ref ETH_Retry_Transmission */ | |
453 | |
454 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. | |
455 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ | |
456 | |
457 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. | |
458 This parameter can be a value of @ref ETH_Back_Off_Limit */ | |
459 | |
460 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). | |
461 This parameter can be a value of @ref ETH_Deferral_Check */ | |
462 | |
463 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). | |
464 This parameter can be a value of @ref ETH_Receive_All */ | |
465 | |
466 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. | |
467 This parameter can be a value of @ref ETH_Source_Addr_Filter */ | |
468 | |
469 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) | |
470 This parameter can be a value of @ref ETH_Pass_Control_Frames */ | |
471 | |
472 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. | |
473 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ | |
474 | |
475 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. | |
476 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ | |
477 | |
478 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode | |
479 This parameter can be a value of @ref ETH_Promiscuous_Mode */ | |
480 | |
481 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. | |
482 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ | |
483 | |
484 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. | |
485 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ | |
486 | |
487 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. | |
488 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ | |
489 | |
490 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. | |
491 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ | |
492 | |
493 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. | |
494 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ | |
495 | |
496 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. | |
497 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ | |
498 | |
499 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for | |
500 automatic retransmission of PAUSE Frame. | |
501 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ | |
502 | |
503 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 | |
504 unicast address and unique multicast address). | |
505 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ | |
506 | |
507 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and | |
508 disable its transmitter for a specified time (Pause Time) | |
509 This parameter can be a value of @ref ETH_Receive_Flow_Control */ | |
510 | |
511 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) | |
512 or the MAC back-pressure operation (Half-Duplex mode) | |
513 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ | |
514 | |
515 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for | |
516 comparison and filtering. | |
517 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ | |
518 | |
519 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ | |
520 | |
521 } ETH_MACInitTypeDef; | |
522 | |
523 /** | |
524 * @brief ETH DMA Configuration Structure definition | |
525 */ | |
526 | |
527 typedef struct | |
528 { | |
529 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. | |
530 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ | |
531 | |
532 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. | |
533 This parameter can be a value of @ref ETH_Receive_Store_Forward */ | |
534 | |
535 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. | |
536 This parameter can be a value of @ref ETH_Flush_Received_Frame */ | |
537 | |
538 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. | |
539 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ | |
540 | |
541 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. | |
542 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ | |
543 | |
544 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. | |
545 This parameter can be a value of @ref ETH_Forward_Error_Frames */ | |
546 | |
547 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error | |
548 and length less than 64 bytes) including pad-bytes and CRC) | |
549 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ | |
550 | |
551 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. | |
552 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ | |
553 | |
554 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second | |
555 frame of Transmit data even before obtaining the status for the first frame. | |
556 This parameter can be a value of @ref ETH_Second_Frame_Operate */ | |
557 | |
558 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. | |
559 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ | |
560 | |
561 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. | |
562 This parameter can be a value of @ref ETH_Fixed_Burst */ | |
563 | |
564 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. | |
565 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ | |
566 | |
567 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. | |
568 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ | |
569 | |
570 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. | |
571 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ | |
572 | |
573 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) | |
574 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ | |
575 | |
576 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. | |
577 This parameter can be a value of @ref ETH_DMA_Arbitration */ | |
578 } ETH_DMAInitTypeDef; | |
579 | |
580 | |
581 /** | |
582 * @brief ETH DMA Descriptors data structure definition | |
583 */ | |
584 | |
585 typedef struct | |
586 { | |
587 __IO uint32_t Status; /*!< Status */ | |
588 | |
589 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ | |
590 | |
591 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ | |
592 | |
593 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ | |
594 | |
595 /*!< Enhanced ETHERNET DMA PTP Descriptors */ | |
596 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ | |
597 | |
598 uint32_t Reserved1; /*!< Reserved */ | |
599 | |
600 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ | |
601 | |
602 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ | |
603 | |
604 } ETH_DMADescTypeDef; | |
605 | |
606 /** | |
607 * @brief Received Frame Informations structure definition | |
608 */ | |
609 typedef struct | |
610 { | |
611 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ | |
612 | |
613 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ | |
614 | |
615 uint32_t SegCount; /*!< Segment count */ | |
616 | |
617 uint32_t length; /*!< Frame length */ | |
618 | |
619 uint32_t buffer; /*!< Frame buffer */ | |
620 | |
621 } ETH_DMARxFrameInfos; | |
622 | |
623 /** | |
624 * @brief ETH Handle Structure definition | |
625 */ | |
626 | |
627 typedef struct | |
628 { | |
629 ETH_TypeDef *Instance; /*!< Register base address */ | |
630 | |
631 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ | |
632 | |
633 uint32_t LinkStatus; /*!< Ethernet link status */ | |
634 | |
635 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ | |
636 | |
637 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ | |
638 | |
639 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ | |
640 | |
641 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ | |
642 | |
643 HAL_LockTypeDef Lock; /*!< ETH Lock */ | |
644 | |
645 } ETH_HandleTypeDef; | |
646 | |
647 /** | |
648 * @} | |
649 */ | |
650 | |
651 /* Exported constants --------------------------------------------------------*/ | |
652 /** @defgroup ETH_Exported_Constants ETH Exported Constants | |
653 * @{ | |
654 */ | |
655 | |
656 /** @defgroup ETH_Buffers_setting ETH Buffers setting | |
657 * @{ | |
658 */ | |
659 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ | |
660 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ | |
661 #define ETH_CRC 4U /*!< Ethernet CRC */ | |
662 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */ | |
663 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ | |
664 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ | |
665 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ | |
666 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ | |
667 | |
668 /* Ethernet driver receive buffers are organized in a chained linked-list, when | |
669 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO | |
670 to the driver receive buffers memory. | |
671 | |
672 Depending on the size of the received ethernet packet and the size of | |
673 each ethernet driver receive buffer, the received packet can take one or more | |
674 ethernet driver receive buffer. | |
675 | |
676 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE | |
677 and the total count of the driver receive buffers ETH_RXBUFNB. | |
678 | |
679 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as | |
680 example, they can be reconfigured in the application layer to fit the application | |
681 needs */ | |
682 | |
683 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet | |
684 packet */ | |
685 #ifndef ETH_RX_BUF_SIZE | |
686 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE | |
687 #endif | |
688 | |
689 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ | |
690 #ifndef ETH_RXBUFNB | |
691 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ | |
692 #endif | |
693 | |
694 | |
695 /* Ethernet driver transmit buffers are organized in a chained linked-list, when | |
696 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the | |
697 driver transmit buffers memory to the TxFIFO. | |
698 | |
699 Depending on the size of the Ethernet packet to be transmitted and the size of | |
700 each ethernet driver transmit buffer, the packet to be transmitted can take | |
701 one or more ethernet driver transmit buffer. | |
702 | |
703 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE | |
704 and the total count of the driver transmit buffers ETH_TXBUFNB. | |
705 | |
706 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as | |
707 example, they can be reconfigured in the application layer to fit the application | |
708 needs */ | |
709 | |
710 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet | |
711 packet */ | |
712 #ifndef ETH_TX_BUF_SIZE | |
713 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE | |
714 #endif | |
715 | |
716 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ | |
717 #ifndef ETH_TXBUFNB | |
718 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ | |
719 #endif | |
720 | |
721 /** | |
722 * @} | |
723 */ | |
724 | |
725 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor | |
726 * @{ | |
727 */ | |
728 | |
729 /* | |
730 DMA Tx Descriptor | |
731 ----------------------------------------------------------------------------------------------- | |
732 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | | |
733 ----------------------------------------------------------------------------------------------- | |
734 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | | |
735 ----------------------------------------------------------------------------------------------- | |
736 TDES2 | Buffer1 Address [31:0] | | |
737 ----------------------------------------------------------------------------------------------- | |
738 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | | |
739 ----------------------------------------------------------------------------------------------- | |
740 */ | |
741 | |
742 /** | |
743 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register | |
744 */ | |
745 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ | |
746 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ | |
747 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ | |
748 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ | |
749 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ | |
750 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ | |
751 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ | |
752 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ | |
753 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ | |
754 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ | |
755 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ | |
756 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ | |
757 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ | |
758 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ | |
759 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ | |
760 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ | |
761 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ | |
762 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ | |
763 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ | |
764 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ | |
765 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ | |
766 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ | |
767 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ | |
768 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ | |
769 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ | |
770 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ | |
771 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ | |
772 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ | |
773 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ | |
774 | |
775 /** | |
776 * @brief Bit definition of TDES1 register | |
777 */ | |
778 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ | |
779 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ | |
780 | |
781 /** | |
782 * @brief Bit definition of TDES2 register | |
783 */ | |
784 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ | |
785 | |
786 /** | |
787 * @brief Bit definition of TDES3 register | |
788 */ | |
789 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ | |
790 | |
791 /*--------------------------------------------------------------------------------------------- | |
792 TDES6 | Transmit Time Stamp Low [31:0] | | |
793 ----------------------------------------------------------------------------------------------- | |
794 TDES7 | Transmit Time Stamp High [31:0] | | |
795 ----------------------------------------------------------------------------------------------*/ | |
796 | |
797 /* Bit definition of TDES6 register */ | |
798 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ | |
799 | |
800 /* Bit definition of TDES7 register */ | |
801 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ | |
802 | |
803 /** | |
804 * @} | |
805 */ | |
806 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor | |
807 * @{ | |
808 */ | |
809 | |
810 /* | |
811 DMA Rx Descriptor | |
812 -------------------------------------------------------------------------------------------------------------------- | |
813 RDES0 | OWN(31) | Status [30:0] | | |
814 --------------------------------------------------------------------------------------------------------------------- | |
815 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | | |
816 --------------------------------------------------------------------------------------------------------------------- | |
817 RDES2 | Buffer1 Address [31:0] | | |
818 --------------------------------------------------------------------------------------------------------------------- | |
819 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | | |
820 --------------------------------------------------------------------------------------------------------------------- | |
821 */ | |
822 | |
823 /** | |
824 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register | |
825 */ | |
826 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ | |
827 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ | |
828 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ | |
829 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ | |
830 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ | |
831 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ | |
832 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ | |
833 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ | |
834 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ | |
835 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ | |
836 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ | |
837 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ | |
838 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ | |
839 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ | |
840 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ | |
841 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ | |
842 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ | |
843 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ | |
844 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ | |
845 | |
846 /** | |
847 * @brief Bit definition of RDES1 register | |
848 */ | |
849 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ | |
850 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ | |
851 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ | |
852 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ | |
853 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ | |
854 | |
855 /** | |
856 * @brief Bit definition of RDES2 register | |
857 */ | |
858 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ | |
859 | |
860 /** | |
861 * @brief Bit definition of RDES3 register | |
862 */ | |
863 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ | |
864 | |
865 /*--------------------------------------------------------------------------------------------------------------------- | |
866 RDES4 | Reserved[31:15] | Extended Status [14:0] | | |
867 --------------------------------------------------------------------------------------------------------------------- | |
868 RDES5 | Reserved[31:0] | | |
869 --------------------------------------------------------------------------------------------------------------------- | |
870 RDES6 | Receive Time Stamp Low [31:0] | | |
871 --------------------------------------------------------------------------------------------------------------------- | |
872 RDES7 | Receive Time Stamp High [31:0] | | |
873 --------------------------------------------------------------------------------------------------------------------*/ | |
874 | |
875 /* Bit definition of RDES4 register */ | |
876 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ | |
877 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ | |
878 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ | |
879 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ | |
880 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ | |
881 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ | |
882 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ | |
883 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ | |
884 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ | |
885 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ | |
886 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ | |
887 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ | |
888 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ | |
889 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ | |
890 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ | |
891 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ | |
892 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ | |
893 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ | |
894 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ | |
895 | |
896 /* Bit definition of RDES6 register */ | |
897 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ | |
898 | |
899 /* Bit definition of RDES7 register */ | |
900 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ | |
901 /** | |
902 * @} | |
903 */ | |
904 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation | |
905 * @{ | |
906 */ | |
907 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U | |
908 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U | |
909 | |
910 /** | |
911 * @} | |
912 */ | |
913 /** @defgroup ETH_Speed ETH Speed | |
914 * @{ | |
915 */ | |
916 #define ETH_SPEED_10M 0x00000000U | |
917 #define ETH_SPEED_100M 0x00004000U | |
918 | |
919 /** | |
920 * @} | |
921 */ | |
922 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode | |
923 * @{ | |
924 */ | |
925 #define ETH_MODE_FULLDUPLEX 0x00000800U | |
926 #define ETH_MODE_HALFDUPLEX 0x00000000U | |
927 /** | |
928 * @} | |
929 */ | |
930 /** @defgroup ETH_Rx_Mode ETH Rx Mode | |
931 * @{ | |
932 */ | |
933 #define ETH_RXPOLLING_MODE 0x00000000U | |
934 #define ETH_RXINTERRUPT_MODE 0x00000001U | |
935 /** | |
936 * @} | |
937 */ | |
938 | |
939 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode | |
940 * @{ | |
941 */ | |
942 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U | |
943 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U | |
944 /** | |
945 * @} | |
946 */ | |
947 | |
948 /** @defgroup ETH_Media_Interface ETH Media Interface | |
949 * @{ | |
950 */ | |
951 #define ETH_MEDIA_INTERFACE_MII 0x00000000U | |
952 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) | |
953 /** | |
954 * @} | |
955 */ | |
956 | |
957 /** @defgroup ETH_Watchdog ETH Watchdog | |
958 * @{ | |
959 */ | |
960 #define ETH_WATCHDOG_ENABLE 0x00000000U | |
961 #define ETH_WATCHDOG_DISABLE 0x00800000U | |
962 /** | |
963 * @} | |
964 */ | |
965 | |
966 /** @defgroup ETH_Jabber ETH Jabber | |
967 * @{ | |
968 */ | |
969 #define ETH_JABBER_ENABLE 0x00000000U | |
970 #define ETH_JABBER_DISABLE 0x00400000U | |
971 /** | |
972 * @} | |
973 */ | |
974 | |
975 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap | |
976 * @{ | |
977 */ | |
978 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ | |
979 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ | |
980 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ | |
981 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ | |
982 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ | |
983 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ | |
984 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ | |
985 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ | |
986 /** | |
987 * @} | |
988 */ | |
989 | |
990 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense | |
991 * @{ | |
992 */ | |
993 #define ETH_CARRIERSENCE_ENABLE 0x00000000U | |
994 #define ETH_CARRIERSENCE_DISABLE 0x00010000U | |
995 /** | |
996 * @} | |
997 */ | |
998 | |
999 /** @defgroup ETH_Receive_Own ETH Receive Own | |
1000 * @{ | |
1001 */ | |
1002 #define ETH_RECEIVEOWN_ENABLE 0x00000000U | |
1003 #define ETH_RECEIVEOWN_DISABLE 0x00002000U | |
1004 /** | |
1005 * @} | |
1006 */ | |
1007 | |
1008 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode | |
1009 * @{ | |
1010 */ | |
1011 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U | |
1012 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U | |
1013 /** | |
1014 * @} | |
1015 */ | |
1016 | |
1017 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload | |
1018 * @{ | |
1019 */ | |
1020 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U | |
1021 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U | |
1022 /** | |
1023 * @} | |
1024 */ | |
1025 | |
1026 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission | |
1027 * @{ | |
1028 */ | |
1029 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U | |
1030 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U | |
1031 /** | |
1032 * @} | |
1033 */ | |
1034 | |
1035 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip | |
1036 * @{ | |
1037 */ | |
1038 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U | |
1039 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U | |
1040 /** | |
1041 * @} | |
1042 */ | |
1043 | |
1044 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit | |
1045 * @{ | |
1046 */ | |
1047 #define ETH_BACKOFFLIMIT_10 0x00000000U | |
1048 #define ETH_BACKOFFLIMIT_8 0x00000020U | |
1049 #define ETH_BACKOFFLIMIT_4 0x00000040U | |
1050 #define ETH_BACKOFFLIMIT_1 0x00000060U | |
1051 /** | |
1052 * @} | |
1053 */ | |
1054 | |
1055 /** @defgroup ETH_Deferral_Check ETH Deferral Check | |
1056 * @{ | |
1057 */ | |
1058 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U | |
1059 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U | |
1060 /** | |
1061 * @} | |
1062 */ | |
1063 | |
1064 /** @defgroup ETH_Receive_All ETH Receive All | |
1065 * @{ | |
1066 */ | |
1067 #define ETH_RECEIVEALL_ENABLE 0x80000000U | |
1068 #define ETH_RECEIVEAll_DISABLE 0x00000000U | |
1069 /** | |
1070 * @} | |
1071 */ | |
1072 | |
1073 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter | |
1074 * @{ | |
1075 */ | |
1076 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U | |
1077 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U | |
1078 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U | |
1079 /** | |
1080 * @} | |
1081 */ | |
1082 | |
1083 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames | |
1084 * @{ | |
1085 */ | |
1086 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ | |
1087 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ | |
1088 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ | |
1089 /** | |
1090 * @} | |
1091 */ | |
1092 | |
1093 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception | |
1094 * @{ | |
1095 */ | |
1096 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U | |
1097 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U | |
1098 /** | |
1099 * @} | |
1100 */ | |
1101 | |
1102 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter | |
1103 * @{ | |
1104 */ | |
1105 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U | |
1106 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U | |
1107 /** | |
1108 * @} | |
1109 */ | |
1110 | |
1111 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode | |
1112 * @{ | |
1113 */ | |
1114 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U | |
1115 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U | |
1116 /** | |
1117 * @} | |
1118 */ | |
1119 | |
1120 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter | |
1121 * @{ | |
1122 */ | |
1123 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U | |
1124 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U | |
1125 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U | |
1126 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U | |
1127 /** | |
1128 * @} | |
1129 */ | |
1130 | |
1131 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter | |
1132 * @{ | |
1133 */ | |
1134 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U | |
1135 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U | |
1136 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U | |
1137 /** | |
1138 * @} | |
1139 */ | |
1140 | |
1141 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause | |
1142 * @{ | |
1143 */ | |
1144 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U | |
1145 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U | |
1146 /** | |
1147 * @} | |
1148 */ | |
1149 | |
1150 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold | |
1151 * @{ | |
1152 */ | |
1153 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ | |
1154 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ | |
1155 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ | |
1156 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ | |
1157 /** | |
1158 * @} | |
1159 */ | |
1160 | |
1161 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect | |
1162 * @{ | |
1163 */ | |
1164 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U | |
1165 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U | |
1166 /** | |
1167 * @} | |
1168 */ | |
1169 | |
1170 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control | |
1171 * @{ | |
1172 */ | |
1173 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U | |
1174 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U | |
1175 /** | |
1176 * @} | |
1177 */ | |
1178 | |
1179 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control | |
1180 * @{ | |
1181 */ | |
1182 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U | |
1183 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U | |
1184 /** | |
1185 * @} | |
1186 */ | |
1187 | |
1188 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison | |
1189 * @{ | |
1190 */ | |
1191 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U | |
1192 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U | |
1193 /** | |
1194 * @} | |
1195 */ | |
1196 | |
1197 /** @defgroup ETH_MAC_addresses ETH MAC addresses | |
1198 * @{ | |
1199 */ | |
1200 #define ETH_MAC_ADDRESS0 0x00000000U | |
1201 #define ETH_MAC_ADDRESS1 0x00000008U | |
1202 #define ETH_MAC_ADDRESS2 0x00000010U | |
1203 #define ETH_MAC_ADDRESS3 0x00000018U | |
1204 /** | |
1205 * @} | |
1206 */ | |
1207 | |
1208 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA | |
1209 * @{ | |
1210 */ | |
1211 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U | |
1212 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U | |
1213 /** | |
1214 * @} | |
1215 */ | |
1216 | |
1217 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes | |
1218 * @{ | |
1219 */ | |
1220 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ | |
1221 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ | |
1222 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ | |
1223 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ | |
1224 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ | |
1225 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ | |
1226 /** | |
1227 * @} | |
1228 */ | |
1229 | |
1230 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame | |
1231 * @{ | |
1232 */ | |
1233 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U | |
1234 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U | |
1235 /** | |
1236 * @} | |
1237 */ | |
1238 | |
1239 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward | |
1240 * @{ | |
1241 */ | |
1242 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U | |
1243 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U | |
1244 /** | |
1245 * @} | |
1246 */ | |
1247 | |
1248 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame | |
1249 * @{ | |
1250 */ | |
1251 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U | |
1252 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U | |
1253 /** | |
1254 * @} | |
1255 */ | |
1256 | |
1257 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward | |
1258 * @{ | |
1259 */ | |
1260 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U | |
1261 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U | |
1262 /** | |
1263 * @} | |
1264 */ | |
1265 | |
1266 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control | |
1267 * @{ | |
1268 */ | |
1269 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ | |
1270 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ | |
1271 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ | |
1272 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ | |
1273 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ | |
1274 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ | |
1275 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ | |
1276 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ | |
1277 /** | |
1278 * @} | |
1279 */ | |
1280 | |
1281 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames | |
1282 * @{ | |
1283 */ | |
1284 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U | |
1285 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U | |
1286 /** | |
1287 * @} | |
1288 */ | |
1289 | |
1290 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames | |
1291 * @{ | |
1292 */ | |
1293 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U | |
1294 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U | |
1295 /** | |
1296 * @} | |
1297 */ | |
1298 | |
1299 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control | |
1300 * @{ | |
1301 */ | |
1302 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ | |
1303 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ | |
1304 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ | |
1305 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ | |
1306 /** | |
1307 * @} | |
1308 */ | |
1309 | |
1310 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate | |
1311 * @{ | |
1312 */ | |
1313 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U | |
1314 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U | |
1315 /** | |
1316 * @} | |
1317 */ | |
1318 | |
1319 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats | |
1320 * @{ | |
1321 */ | |
1322 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U | |
1323 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U | |
1324 /** | |
1325 * @} | |
1326 */ | |
1327 | |
1328 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst | |
1329 * @{ | |
1330 */ | |
1331 #define ETH_FIXEDBURST_ENABLE 0x00010000U | |
1332 #define ETH_FIXEDBURST_DISABLE 0x00000000U | |
1333 /** | |
1334 * @} | |
1335 */ | |
1336 | |
1337 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length | |
1338 * @{ | |
1339 */ | |
1340 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ | |
1341 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ | |
1342 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ | |
1343 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ | |
1344 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ | |
1345 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ | |
1346 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ | |
1347 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ | |
1348 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ | |
1349 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ | |
1350 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ | |
1351 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ | |
1352 /** | |
1353 * @} | |
1354 */ | |
1355 | |
1356 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length | |
1357 * @{ | |
1358 */ | |
1359 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ | |
1360 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ | |
1361 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ | |
1362 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ | |
1363 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ | |
1364 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ | |
1365 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ | |
1366 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ | |
1367 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ | |
1368 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ | |
1369 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ | |
1370 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ | |
1371 /** | |
1372 * @} | |
1373 */ | |
1374 | |
1375 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format | |
1376 * @{ | |
1377 */ | |
1378 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U | |
1379 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U | |
1380 /** | |
1381 * @} | |
1382 */ | |
1383 | |
1384 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration | |
1385 * @{ | |
1386 */ | |
1387 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U | |
1388 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U | |
1389 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U | |
1390 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U | |
1391 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U | |
1392 /** | |
1393 * @} | |
1394 */ | |
1395 | |
1396 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment | |
1397 * @{ | |
1398 */ | |
1399 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ | |
1400 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ | |
1401 /** | |
1402 * @} | |
1403 */ | |
1404 | |
1405 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control | |
1406 * @{ | |
1407 */ | |
1408 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ | |
1409 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ | |
1410 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ | |
1411 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ | |
1412 /** | |
1413 * @} | |
1414 */ | |
1415 | |
1416 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers | |
1417 * @{ | |
1418 */ | |
1419 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ | |
1420 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ | |
1421 /** | |
1422 * @} | |
1423 */ | |
1424 | |
1425 /** @defgroup ETH_PMT_Flags ETH PMT Flags | |
1426 * @{ | |
1427 */ | |
1428 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ | |
1429 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ | |
1430 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ | |
1431 /** | |
1432 * @} | |
1433 */ | |
1434 | |
1435 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts | |
1436 * @{ | |
1437 */ | |
1438 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ | |
1439 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ | |
1440 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ | |
1441 /** | |
1442 * @} | |
1443 */ | |
1444 | |
1445 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts | |
1446 * @{ | |
1447 */ | |
1448 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ | |
1449 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ | |
1450 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ | |
1451 /** | |
1452 * @} | |
1453 */ | |
1454 | |
1455 /** @defgroup ETH_MAC_Flags ETH MAC Flags | |
1456 * @{ | |
1457 */ | |
1458 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ | |
1459 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ | |
1460 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ | |
1461 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ | |
1462 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ | |
1463 /** | |
1464 * @} | |
1465 */ | |
1466 | |
1467 /** @defgroup ETH_DMA_Flags ETH DMA Flags | |
1468 * @{ | |
1469 */ | |
1470 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ | |
1471 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ | |
1472 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ | |
1473 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ | |
1474 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ | |
1475 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ | |
1476 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ | |
1477 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ | |
1478 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ | |
1479 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ | |
1480 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ | |
1481 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ | |
1482 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ | |
1483 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ | |
1484 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ | |
1485 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ | |
1486 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ | |
1487 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ | |
1488 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ | |
1489 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ | |
1490 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ | |
1491 /** | |
1492 * @} | |
1493 */ | |
1494 | |
1495 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts | |
1496 * @{ | |
1497 */ | |
1498 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ | |
1499 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ | |
1500 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ | |
1501 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ | |
1502 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ | |
1503 /** | |
1504 * @} | |
1505 */ | |
1506 | |
1507 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts | |
1508 * @{ | |
1509 */ | |
1510 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ | |
1511 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ | |
1512 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ | |
1513 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ | |
1514 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ | |
1515 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ | |
1516 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ | |
1517 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ | |
1518 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ | |
1519 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ | |
1520 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ | |
1521 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ | |
1522 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ | |
1523 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ | |
1524 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ | |
1525 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ | |
1526 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ | |
1527 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ | |
1528 /** | |
1529 * @} | |
1530 */ | |
1531 | |
1532 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state | |
1533 * @{ | |
1534 */ | |
1535 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ | |
1536 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ | |
1537 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ | |
1538 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ | |
1539 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ | |
1540 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ | |
1541 | |
1542 /** | |
1543 * @} | |
1544 */ | |
1545 | |
1546 | |
1547 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state | |
1548 * @{ | |
1549 */ | |
1550 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ | |
1551 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ | |
1552 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ | |
1553 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ | |
1554 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ | |
1555 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ | |
1556 | |
1557 /** | |
1558 * @} | |
1559 */ | |
1560 | |
1561 /** @defgroup ETH_DMA_overflow ETH DMA overflow | |
1562 * @{ | |
1563 */ | |
1564 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ | |
1565 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ | |
1566 /** | |
1567 * @} | |
1568 */ | |
1569 | |
1570 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP | |
1571 * @{ | |
1572 */ | |
1573 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ | |
1574 | |
1575 /** | |
1576 * @} | |
1577 */ | |
1578 | |
1579 /** | |
1580 * @} | |
1581 */ | |
1582 | |
1583 /* Exported macro ------------------------------------------------------------*/ | |
1584 /** @defgroup ETH_Exported_Macros ETH Exported Macros | |
1585 * @brief macros to handle interrupts and specific clock configurations | |
1586 * @{ | |
1587 */ | |
1588 | |
1589 /** @brief Reset ETH handle state | |
1590 * @param __HANDLE__ specifies the ETH handle. | |
1591 * @retval None | |
1592 */ | |
1593 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) | |
1594 | |
1595 /** | |
1596 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. | |
1597 * @param __HANDLE__ ETH Handle | |
1598 * @param __FLAG__ specifies the flag of TDES0 to check. | |
1599 * @retval the ETH_DMATxDescFlag (SET or RESET). | |
1600 */ | |
1601 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) | |
1602 | |
1603 /** | |
1604 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. | |
1605 * @param __HANDLE__ ETH Handle | |
1606 * @param __FLAG__ specifies the flag of RDES0 to check. | |
1607 * @retval the ETH_DMATxDescFlag (SET or RESET). | |
1608 */ | |
1609 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) | |
1610 | |
1611 /** | |
1612 * @brief Enables the specified DMA Rx Desc receive interrupt. | |
1613 * @param __HANDLE__ ETH Handle | |
1614 * @retval None | |
1615 */ | |
1616 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) | |
1617 | |
1618 /** | |
1619 * @brief Disables the specified DMA Rx Desc receive interrupt. | |
1620 * @param __HANDLE__ ETH Handle | |
1621 * @retval None | |
1622 */ | |
1623 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) | |
1624 | |
1625 /** | |
1626 * @brief Set the specified DMA Rx Desc Own bit. | |
1627 * @param __HANDLE__ ETH Handle | |
1628 * @retval None | |
1629 */ | |
1630 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) | |
1631 | |
1632 /** | |
1633 * @brief Returns the specified ETHERNET DMA Tx Desc collision count. | |
1634 * @param __HANDLE__ ETH Handle | |
1635 * @retval The Transmit descriptor collision counter value. | |
1636 */ | |
1637 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) | |
1638 | |
1639 /** | |
1640 * @brief Set the specified DMA Tx Desc Own bit. | |
1641 * @param __HANDLE__ ETH Handle | |
1642 * @retval None | |
1643 */ | |
1644 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) | |
1645 | |
1646 /** | |
1647 * @brief Enables the specified DMA Tx Desc Transmit interrupt. | |
1648 * @param __HANDLE__ ETH Handle | |
1649 * @retval None | |
1650 */ | |
1651 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) | |
1652 | |
1653 /** | |
1654 * @brief Disables the specified DMA Tx Desc Transmit interrupt. | |
1655 * @param __HANDLE__ ETH Handle | |
1656 * @retval None | |
1657 */ | |
1658 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) | |
1659 | |
1660 /** | |
1661 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. | |
1662 * @param __HANDLE__ ETH Handle | |
1663 * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. | |
1664 * This parameter can be one of the following values: | |
1665 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass | |
1666 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum | |
1667 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present | |
1668 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header | |
1669 * @retval None | |
1670 */ | |
1671 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) | |
1672 | |
1673 /** | |
1674 * @brief Enables the DMA Tx Desc CRC. | |
1675 * @param __HANDLE__ ETH Handle | |
1676 * @retval None | |
1677 */ | |
1678 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) | |
1679 | |
1680 /** | |
1681 * @brief Disables the DMA Tx Desc CRC. | |
1682 * @param __HANDLE__ ETH Handle | |
1683 * @retval None | |
1684 */ | |
1685 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) | |
1686 | |
1687 /** | |
1688 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. | |
1689 * @param __HANDLE__ ETH Handle | |
1690 * @retval None | |
1691 */ | |
1692 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) | |
1693 | |
1694 /** | |
1695 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. | |
1696 * @param __HANDLE__ ETH Handle | |
1697 * @retval None | |
1698 */ | |
1699 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) | |
1700 | |
1701 /** | |
1702 * @brief Enables the specified ETHERNET MAC interrupts. | |
1703 * @param __HANDLE__ ETH Handle | |
1704 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be | |
1705 * enabled or disabled. | |
1706 * This parameter can be any combination of the following values: | |
1707 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt | |
1708 * @arg ETH_MAC_IT_PMT : PMT interrupt | |
1709 * @retval None | |
1710 */ | |
1711 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) | |
1712 | |
1713 /** | |
1714 * @brief Disables the specified ETHERNET MAC interrupts. | |
1715 * @param __HANDLE__ ETH Handle | |
1716 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be | |
1717 * enabled or disabled. | |
1718 * This parameter can be any combination of the following values: | |
1719 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt | |
1720 * @arg ETH_MAC_IT_PMT : PMT interrupt | |
1721 * @retval None | |
1722 */ | |
1723 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) | |
1724 | |
1725 /** | |
1726 * @brief Initiate a Pause Control Frame (Full-duplex only). | |
1727 * @param __HANDLE__ ETH Handle | |
1728 * @retval None | |
1729 */ | |
1730 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) | |
1731 | |
1732 /** | |
1733 * @brief Checks whether the ETHERNET flow control busy bit is set or not. | |
1734 * @param __HANDLE__ ETH Handle | |
1735 * @retval The new state of flow control busy status bit (SET or RESET). | |
1736 */ | |
1737 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) | |
1738 | |
1739 /** | |
1740 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). | |
1741 * @param __HANDLE__ ETH Handle | |
1742 * @retval None | |
1743 */ | |
1744 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) | |
1745 | |
1746 /** | |
1747 * @brief Disables the MAC BackPressure operation activation (Half-duplex only). | |
1748 * @param __HANDLE__ ETH Handle | |
1749 * @retval None | |
1750 */ | |
1751 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) | |
1752 | |
1753 /** | |
1754 * @brief Checks whether the specified ETHERNET MAC flag is set or not. | |
1755 * @param __HANDLE__ ETH Handle | |
1756 * @param __FLAG__ specifies the flag to check. | |
1757 * This parameter can be one of the following values: | |
1758 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag | |
1759 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag | |
1760 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag | |
1761 * @arg ETH_MAC_FLAG_MMC : MMC flag | |
1762 * @arg ETH_MAC_FLAG_PMT : PMT flag | |
1763 * @retval The state of ETHERNET MAC flag. | |
1764 */ | |
1765 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) | |
1766 | |
1767 /** | |
1768 * @brief Enables the specified ETHERNET DMA interrupts. | |
1769 * @param __HANDLE__ ETH Handle | |
1770 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be | |
1771 * enabled @ref ETH_DMA_Interrupts | |
1772 * @retval None | |
1773 */ | |
1774 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) | |
1775 | |
1776 /** | |
1777 * @brief Disables the specified ETHERNET DMA interrupts. | |
1778 * @param __HANDLE__ ETH Handle | |
1779 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be | |
1780 * disabled. @ref ETH_DMA_Interrupts | |
1781 * @retval None | |
1782 */ | |
1783 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) | |
1784 | |
1785 /** | |
1786 * @brief Clears the ETHERNET DMA IT pending bit. | |
1787 * @param __HANDLE__ ETH Handle | |
1788 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts | |
1789 * @retval None | |
1790 */ | |
1791 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) | |
1792 | |
1793 /** | |
1794 * @brief Checks whether the specified ETHERNET DMA flag is set or not. | |
1795 * @param __HANDLE__ ETH Handle | |
1796 * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags | |
1797 * @retval The new state of ETH_DMA_FLAG (SET or RESET). | |
1798 */ | |
1799 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) | |
1800 | |
1801 /** | |
1802 * @brief Checks whether the specified ETHERNET DMA flag is set or not. | |
1803 * @param __HANDLE__ ETH Handle | |
1804 * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags | |
1805 * @retval The new state of ETH_DMA_FLAG (SET or RESET). | |
1806 */ | |
1807 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) | |
1808 | |
1809 /** | |
1810 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. | |
1811 * @param __HANDLE__ ETH Handle | |
1812 * @param __OVERFLOW__ specifies the DMA overflow flag to check. | |
1813 * This parameter can be one of the following values: | |
1814 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter | |
1815 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter | |
1816 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). | |
1817 */ | |
1818 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) | |
1819 | |
1820 /** | |
1821 * @brief Set the DMA Receive status watchdog timer register value | |
1822 * @param __HANDLE__ ETH Handle | |
1823 * @param __VALUE__ DMA Receive status watchdog timer register value | |
1824 * @retval None | |
1825 */ | |
1826 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) | |
1827 | |
1828 /** | |
1829 * @brief Enables any unicast packet filtered by the MAC address | |
1830 * recognition to be a wake-up frame. | |
1831 * @param __HANDLE__ ETH Handle. | |
1832 * @retval None | |
1833 */ | |
1834 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) | |
1835 | |
1836 /** | |
1837 * @brief Disables any unicast packet filtered by the MAC address | |
1838 * recognition to be a wake-up frame. | |
1839 * @param __HANDLE__ ETH Handle. | |
1840 * @retval None | |
1841 */ | |
1842 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) | |
1843 | |
1844 /** | |
1845 * @brief Enables the MAC Wake-Up Frame Detection. | |
1846 * @param __HANDLE__ ETH Handle. | |
1847 * @retval None | |
1848 */ | |
1849 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) | |
1850 | |
1851 /** | |
1852 * @brief Disables the MAC Wake-Up Frame Detection. | |
1853 * @param __HANDLE__ ETH Handle. | |
1854 * @retval None | |
1855 */ | |
1856 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) | |
1857 | |
1858 /** | |
1859 * @brief Enables the MAC Magic Packet Detection. | |
1860 * @param __HANDLE__ ETH Handle. | |
1861 * @retval None | |
1862 */ | |
1863 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) | |
1864 | |
1865 /** | |
1866 * @brief Disables the MAC Magic Packet Detection. | |
1867 * @param __HANDLE__ ETH Handle. | |
1868 * @retval None | |
1869 */ | |
1870 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) | |
1871 | |
1872 /** | |
1873 * @brief Enables the MAC Power Down. | |
1874 * @param __HANDLE__ ETH Handle | |
1875 * @retval None | |
1876 */ | |
1877 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) | |
1878 | |
1879 /** | |
1880 * @brief Disables the MAC Power Down. | |
1881 * @param __HANDLE__ ETH Handle | |
1882 * @retval None | |
1883 */ | |
1884 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) | |
1885 | |
1886 /** | |
1887 * @brief Checks whether the specified ETHERNET PMT flag is set or not. | |
1888 * @param __HANDLE__ ETH Handle. | |
1889 * @param __FLAG__ specifies the flag to check. | |
1890 * This parameter can be one of the following values: | |
1891 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset | |
1892 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received | |
1893 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received | |
1894 * @retval The new state of ETHERNET PMT Flag (SET or RESET). | |
1895 */ | |
1896 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) | |
1897 | |
1898 /** | |
1899 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) | |
1900 * @param __HANDLE__ ETH Handle. | |
1901 * @retval None | |
1902 */ | |
1903 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) | |
1904 | |
1905 /** | |
1906 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) | |
1907 * @param __HANDLE__ ETH Handle. | |
1908 * @retval None | |
1909 */ | |
1910 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ | |
1911 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) | |
1912 | |
1913 /** | |
1914 * @brief Enables the MMC Counter Freeze. | |
1915 * @param __HANDLE__ ETH Handle. | |
1916 * @retval None | |
1917 */ | |
1918 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) | |
1919 | |
1920 /** | |
1921 * @brief Disables the MMC Counter Freeze. | |
1922 * @param __HANDLE__ ETH Handle. | |
1923 * @retval None | |
1924 */ | |
1925 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) | |
1926 | |
1927 /** | |
1928 * @brief Enables the MMC Reset On Read. | |
1929 * @param __HANDLE__ ETH Handle. | |
1930 * @retval None | |
1931 */ | |
1932 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) | |
1933 | |
1934 /** | |
1935 * @brief Disables the MMC Reset On Read. | |
1936 * @param __HANDLE__ ETH Handle. | |
1937 * @retval None | |
1938 */ | |
1939 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) | |
1940 | |
1941 /** | |
1942 * @brief Enables the MMC Counter Stop Rollover. | |
1943 * @param __HANDLE__ ETH Handle. | |
1944 * @retval None | |
1945 */ | |
1946 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) | |
1947 | |
1948 /** | |
1949 * @brief Disables the MMC Counter Stop Rollover. | |
1950 * @param __HANDLE__ ETH Handle. | |
1951 * @retval None | |
1952 */ | |
1953 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) | |
1954 | |
1955 /** | |
1956 * @brief Resets the MMC Counters. | |
1957 * @param __HANDLE__ ETH Handle. | |
1958 * @retval None | |
1959 */ | |
1960 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) | |
1961 | |
1962 /** | |
1963 * @brief Enables the specified ETHERNET MMC Rx interrupts. | |
1964 * @param __HANDLE__ ETH Handle. | |
1965 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. | |
1966 * This parameter can be one of the following values: | |
1967 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value | |
1968 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value | |
1969 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value | |
1970 * @retval None | |
1971 */ | |
1972 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) | |
1973 /** | |
1974 * @brief Disables the specified ETHERNET MMC Rx interrupts. | |
1975 * @param __HANDLE__ ETH Handle. | |
1976 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. | |
1977 * This parameter can be one of the following values: | |
1978 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value | |
1979 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value | |
1980 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value | |
1981 * @retval None | |
1982 */ | |
1983 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) | |
1984 /** | |
1985 * @brief Enables the specified ETHERNET MMC Tx interrupts. | |
1986 * @param __HANDLE__ ETH Handle. | |
1987 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. | |
1988 * This parameter can be one of the following values: | |
1989 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value | |
1990 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value | |
1991 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value | |
1992 * @retval None | |
1993 */ | |
1994 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) | |
1995 | |
1996 /** | |
1997 * @brief Disables the specified ETHERNET MMC Tx interrupts. | |
1998 * @param __HANDLE__ ETH Handle. | |
1999 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. | |
2000 * This parameter can be one of the following values: | |
2001 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value | |
2002 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value | |
2003 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value | |
2004 * @retval None | |
2005 */ | |
2006 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) | |
2007 | |
2008 /** | |
2009 * @brief Enables the ETH External interrupt line. | |
2010 * @retval None | |
2011 */ | |
2012 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) | |
2013 | |
2014 /** | |
2015 * @brief Disables the ETH External interrupt line. | |
2016 * @retval None | |
2017 */ | |
2018 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) | |
2019 | |
2020 /** | |
2021 * @brief Enable event on ETH External event line. | |
2022 * @retval None. | |
2023 */ | |
2024 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) | |
2025 | |
2026 /** | |
2027 * @brief Disable event on ETH External event line | |
2028 * @retval None. | |
2029 */ | |
2030 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) | |
2031 | |
2032 /** | |
2033 * @brief Get flag of the ETH External interrupt line. | |
2034 * @retval None | |
2035 */ | |
2036 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) | |
2037 | |
2038 /** | |
2039 * @brief Clear flag of the ETH External interrupt line. | |
2040 * @retval None | |
2041 */ | |
2042 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) | |
2043 | |
2044 /** | |
2045 * @brief Enables rising edge trigger to the ETH External interrupt line. | |
2046 * @retval None | |
2047 */ | |
2048 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP | |
2049 | |
2050 /** | |
2051 * @brief Disables the rising edge trigger to the ETH External interrupt line. | |
2052 * @retval None | |
2053 */ | |
2054 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) | |
2055 | |
2056 /** | |
2057 * @brief Enables falling edge trigger to the ETH External interrupt line. | |
2058 * @retval None | |
2059 */ | |
2060 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) | |
2061 | |
2062 /** | |
2063 * @brief Disables falling edge trigger to the ETH External interrupt line. | |
2064 * @retval None | |
2065 */ | |
2066 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) | |
2067 | |
2068 /** | |
2069 * @brief Enables rising/falling edge trigger to the ETH External interrupt line. | |
2070 * @retval None | |
2071 */ | |
2072 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ | |
2073 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ | |
2074 }while(0U) | |
2075 | |
2076 /** | |
2077 * @brief Disables rising/falling edge trigger to the ETH External interrupt line. | |
2078 * @retval None | |
2079 */ | |
2080 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ | |
2081 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ | |
2082 }while(0U) | |
2083 | |
2084 /** | |
2085 * @brief Generate a Software interrupt on selected EXTI line. | |
2086 * @retval None. | |
2087 */ | |
2088 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP | |
2089 | |
2090 /** | |
2091 * @} | |
2092 */ | |
2093 /* Exported functions --------------------------------------------------------*/ | |
2094 | |
2095 /** @addtogroup ETH_Exported_Functions | |
2096 * @{ | |
2097 */ | |
2098 | |
2099 /* Initialization and de-initialization functions ****************************/ | |
2100 | |
2101 /** @addtogroup ETH_Exported_Functions_Group1 | |
2102 * @{ | |
2103 */ | |
2104 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); | |
2105 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); | |
2106 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); | |
2107 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); | |
2108 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); | |
2109 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); | |
2110 | |
2111 /** | |
2112 * @} | |
2113 */ | |
2114 /* IO operation functions ****************************************************/ | |
2115 | |
2116 /** @addtogroup ETH_Exported_Functions_Group2 | |
2117 * @{ | |
2118 */ | |
2119 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); | |
2120 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); | |
2121 /* Communication with PHY functions*/ | |
2122 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); | |
2123 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); | |
2124 /* Non-Blocking mode: Interrupt */ | |
2125 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); | |
2126 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); | |
2127 /* Callback in non blocking modes (Interrupt) */ | |
2128 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); | |
2129 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); | |
2130 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); | |
2131 /** | |
2132 * @} | |
2133 */ | |
2134 | |
2135 /* Peripheral Control functions **********************************************/ | |
2136 | |
2137 /** @addtogroup ETH_Exported_Functions_Group3 | |
2138 * @{ | |
2139 */ | |
2140 | |
2141 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); | |
2142 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); | |
2143 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); | |
2144 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); | |
2145 /** | |
2146 * @} | |
2147 */ | |
2148 | |
2149 /* Peripheral State functions ************************************************/ | |
2150 | |
2151 /** @addtogroup ETH_Exported_Functions_Group4 | |
2152 * @{ | |
2153 */ | |
2154 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); | |
2155 /** | |
2156 * @} | |
2157 */ | |
2158 | |
2159 /** | |
2160 * @} | |
2161 */ | |
2162 | |
2163 /** | |
2164 * @} | |
2165 */ | |
2166 | |
2167 /** | |
2168 * @} | |
2169 */ | |
2170 | |
2171 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ | |
2172 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ | |
2173 | |
2174 #ifdef __cplusplus | |
2175 } | |
2176 #endif | |
2177 | |
2178 #endif /* __STM32F4xx_HAL_ETH_H */ | |
2179 | |
2180 | |
2181 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |