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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dsi.h
4 * @author MCD Application Team
5 * @brief Header file of DSI HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_HAL_DSI_H
38 #define __STM32F4xx_HAL_DSI_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 #if defined(DSI)
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32f4xx_hal_def.h"
47
48 /** @addtogroup STM32F4xx_HAL_Driver
49 * @{
50 */
51
52 /** @defgroup DSI DSI
53 * @brief DSI HAL module driver
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /**
59 * @brief DSI Init Structure definition
60 */
61 typedef struct
62 {
63 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
64 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
65
66 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
67 The values 0 and 1 stop the TX_ESC clock generation */
68
69 uint32_t NumberOfLanes; /*!< Number of lanes
70 This parameter can be any value of @ref DSI_Number_Of_Lanes */
71
72 }DSI_InitTypeDef;
73
74 /**
75 * @brief DSI PLL Clock structure definition
76 */
77 typedef struct
78 {
79 uint32_t PLLNDIV; /*!< PLL Loop Division Factor
80 This parameter must be a value between 10 and 125 */
81
82 uint32_t PLLIDF; /*!< PLL Input Division Factor
83 This parameter can be any value of @ref DSI_PLL_IDF */
84
85 uint32_t PLLODF; /*!< PLL Output Division Factor
86 This parameter can be any value of @ref DSI_PLL_ODF */
87
88 }DSI_PLLInitTypeDef;
89
90 /**
91 * @brief DSI Video mode configuration
92 */
93 typedef struct
94 {
95 uint32_t VirtualChannelID; /*!< Virtual channel ID */
96
97 uint32_t ColorCoding; /*!< Color coding for LTDC interface
98 This parameter can be any value of @ref DSI_Color_Coding */
99
100 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
101 18-bit configuration).
102 This parameter can be any value of @ref DSI_LooselyPacked */
103
104 uint32_t Mode; /*!< Video mode type
105 This parameter can be any value of @ref DSI_Video_Mode_Type */
106
107 uint32_t PacketSize; /*!< Video packet size */
108
109 uint32_t NumberOfChunks; /*!< Number of chunks */
110
111 uint32_t NullPacketSize; /*!< Null packet size */
112
113 uint32_t HSPolarity; /*!< HSYNC pin polarity
114 This parameter can be any value of @ref DSI_HSYNC_Polarity */
115
116 uint32_t VSPolarity; /*!< VSYNC pin polarity
117 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
118
119 uint32_t DEPolarity; /*!< Data Enable pin polarity
120 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
121
122 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
123
124 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
125
126 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
127
128 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
129
130 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
131
132 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
133
134 uint32_t VerticalActive; /*!< Vertical active duration */
135
136 uint32_t LPCommandEnable; /*!< Low-power command enable
137 This parameter can be any value of @ref DSI_LP_Command */
138
139 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
140 can fit in a line during VSA, VBP and VFP regions */
141
142 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
143 can fit in a line during VACT region */
144
145 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
146 This parameter can be any value of @ref DSI_LP_HFP */
147
148 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
149 This parameter can be any value of @ref DSI_LP_HBP */
150
151 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
152 This parameter can be any value of @ref DSI_LP_VACT */
153
154 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
155 This parameter can be any value of @ref DSI_LP_VFP */
156
157 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
158 This parameter can be any value of @ref DSI_LP_VBP */
159
160 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
161 This parameter can be any value of @ref DSI_LP_VSYNC */
162
163 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
164 This parameter can be any value of @ref DSI_FBTA_acknowledge */
165
166 }DSI_VidCfgTypeDef;
167
168 /**
169 * @brief DSI Adapted command mode configuration
170 */
171 typedef struct
172 {
173 uint32_t VirtualChannelID; /*!< Virtual channel ID */
174
175 uint32_t ColorCoding; /*!< Color coding for LTDC interface
176 This parameter can be any value of @ref DSI_Color_Coding */
177
178 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
179 pixels. This parameter can be any value between 0x00 and 0xFFFFU */
180
181 uint32_t TearingEffectSource; /*!< Tearing effect source
182 This parameter can be any value of @ref DSI_TearingEffectSource */
183
184 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
185 This parameter can be any value of @ref DSI_TearingEffectPolarity */
186
187 uint32_t HSPolarity; /*!< HSYNC pin polarity
188 This parameter can be any value of @ref DSI_HSYNC_Polarity */
189
190 uint32_t VSPolarity; /*!< VSYNC pin polarity
191 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
192
193 uint32_t DEPolarity; /*!< Data Enable pin polarity
194 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
195
196 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
197 This parameter can be any value of @ref DSI_Vsync_Polarity */
198
199 uint32_t AutomaticRefresh; /*!< Automatic refresh mode
200 This parameter can be any value of @ref DSI_AutomaticRefresh */
201
202 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
203 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
204
205 }DSI_CmdCfgTypeDef;
206
207 /**
208 * @brief DSI command transmission mode configuration
209 */
210 typedef struct
211 {
212 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
213 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
214
215 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
216 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
217
218 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
219 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
220
221 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
222 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
223
224 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
225 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
226
227 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
228 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
229
230 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
231 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
232
233 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
234 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
235
236 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
237 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
238
239 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
240 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
241
242 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
243 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
244
245 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
246 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
247
248 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
249 This parameter can be any value of @ref DSI_AcknowledgeRequest */
250
251 }DSI_LPCmdTypeDef;
252
253 /**
254 * @brief DSI PHY Timings definition
255 */
256 typedef struct
257 {
258 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
259 to low-power transmission */
260
261 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
262 to high-speed transmission */
263
264 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
265 to low-power transmission */
266
267 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
268 to high-speed transmission */
269
270 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
271
272 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
273 Stop state */
274
275 }DSI_PHY_TimerTypeDef;
276
277 /**
278 * @brief DSI HOST Timeouts definition
279 */
280 typedef struct
281 {
282 uint32_t TimeoutCkdiv; /*!< Time-out clock division */
283
284 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */
285
286 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */
287
288 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */
289
290 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */
291
292 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */
293
294 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
295 This parameter can be any value of @ref DSI_HS_PrespMode */
296
297 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */
298
299 uint32_t BTATimeout; /*!< BTA time-out */
300
301 }DSI_HOST_TimeoutTypeDef;
302
303 /**
304 * @brief DSI States Structure definition
305 */
306 typedef enum
307 {
308 HAL_DSI_STATE_RESET = 0x00U,
309 HAL_DSI_STATE_READY = 0x01U,
310 HAL_DSI_STATE_ERROR = 0x02U,
311 HAL_DSI_STATE_BUSY = 0x03U,
312 HAL_DSI_STATE_TIMEOUT = 0x04U
313 }HAL_DSI_StateTypeDef;
314
315 /**
316 * @brief DSI Handle Structure definition
317 */
318 typedef struct
319 {
320 DSI_TypeDef *Instance; /*!< Register base address */
321 DSI_InitTypeDef Init; /*!< DSI required parameters */
322 HAL_LockTypeDef Lock; /*!< DSI peripheral status */
323 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
324 __IO uint32_t ErrorCode; /*!< DSI Error code */
325 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
326 }DSI_HandleTypeDef;
327
328 /* Exported constants --------------------------------------------------------*/
329 /** @defgroup DSI_DCS_Command DSI DCS Command
330 * @{
331 */
332 #define DSI_ENTER_IDLE_MODE 0x39U
333 #define DSI_ENTER_INVERT_MODE 0x21U
334 #define DSI_ENTER_NORMAL_MODE 0x13U
335 #define DSI_ENTER_PARTIAL_MODE 0x12U
336 #define DSI_ENTER_SLEEP_MODE 0x10U
337 #define DSI_EXIT_IDLE_MODE 0x38U
338 #define DSI_EXIT_INVERT_MODE 0x20U
339 #define DSI_EXIT_SLEEP_MODE 0x11U
340 #define DSI_GET_3D_CONTROL 0x3FU
341 #define DSI_GET_ADDRESS_MODE 0x0BU
342 #define DSI_GET_BLUE_CHANNEL 0x08U
343 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
344 #define DSI_GET_DISPLAY_MODE 0x0DU
345 #define DSI_GET_GREEN_CHANNEL 0x07U
346 #define DSI_GET_PIXEL_FORMAT 0x0CU
347 #define DSI_GET_POWER_MODE 0x0AU
348 #define DSI_GET_RED_CHANNEL 0x06U
349 #define DSI_GET_SCANLINE 0x45U
350 #define DSI_GET_SIGNAL_MODE 0x0EU
351 #define DSI_NOP 0x00U
352 #define DSI_READ_DDB_CONTINUE 0xA8U
353 #define DSI_READ_DDB_START 0xA1U
354 #define DSI_READ_MEMORY_CONTINUE 0x3EU
355 #define DSI_READ_MEMORY_START 0x2EU
356 #define DSI_SET_3D_CONTROL 0x3DU
357 #define DSI_SET_ADDRESS_MODE 0x36U
358 #define DSI_SET_COLUMN_ADDRESS 0x2AU
359 #define DSI_SET_DISPLAY_OFF 0x28U
360 #define DSI_SET_DISPLAY_ON 0x29U
361 #define DSI_SET_GAMMA_CURVE 0x26U
362 #define DSI_SET_PAGE_ADDRESS 0x2BU
363 #define DSI_SET_PARTIAL_COLUMNS 0x31U
364 #define DSI_SET_PARTIAL_ROWS 0x30U
365 #define DSI_SET_PIXEL_FORMAT 0x3AU
366 #define DSI_SET_SCROLL_AREA 0x33U
367 #define DSI_SET_SCROLL_START 0x37U
368 #define DSI_SET_TEAR_OFF 0x34U
369 #define DSI_SET_TEAR_ON 0x35U
370 #define DSI_SET_TEAR_SCANLINE 0x44U
371 #define DSI_SET_VSYNC_TIMING 0x40U
372 #define DSI_SOFT_RESET 0x01U
373 #define DSI_WRITE_LUT 0x2DU
374 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
375 #define DSI_WRITE_MEMORY_START 0x2CU
376 /**
377 * @}
378 */
379
380 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
381 * @{
382 */
383 #define DSI_VID_MODE_NB_PULSES 0U
384 #define DSI_VID_MODE_NB_EVENTS 1U
385 #define DSI_VID_MODE_BURST 2U
386 /**
387 * @}
388 */
389
390 /** @defgroup DSI_Color_Mode DSI Color Mode
391 * @{
392 */
393 #define DSI_COLOR_MODE_FULL 0x00000000U
394 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
395 /**
396 * @}
397 */
398
399 /** @defgroup DSI_ShutDown DSI ShutDown
400 * @{
401 */
402 #define DSI_DISPLAY_ON 0x00000000U
403 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
404 /**
405 * @}
406 */
407
408 /** @defgroup DSI_LP_Command DSI LP Command
409 * @{
410 */
411 #define DSI_LP_COMMAND_DISABLE 0x00000000U
412 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
413 /**
414 * @}
415 */
416
417 /** @defgroup DSI_LP_HFP DSI LP HFP
418 * @{
419 */
420 #define DSI_LP_HFP_DISABLE 0x00000000U
421 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
422 /**
423 * @}
424 */
425
426 /** @defgroup DSI_LP_HBP DSI LP HBP
427 * @{
428 */
429 #define DSI_LP_HBP_DISABLE 0x00000000U
430 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
431 /**
432 * @}
433 */
434
435 /** @defgroup DSI_LP_VACT DSI LP VACT
436 * @{
437 */
438 #define DSI_LP_VACT_DISABLE 0x00000000U
439 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
440 /**
441 * @}
442 */
443
444 /** @defgroup DSI_LP_VFP DSI LP VFP
445 * @{
446 */
447 #define DSI_LP_VFP_DISABLE 0x00000000U
448 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
449 /**
450 * @}
451 */
452
453 /** @defgroup DSI_LP_VBP DSI LP VBP
454 * @{
455 */
456 #define DSI_LP_VBP_DISABLE 0x00000000U
457 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
458 /**
459 * @}
460 */
461
462 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC
463 * @{
464 */
465 #define DSI_LP_VSYNC_DISABLE 0x00000000U
466 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
467 /**
468 * @}
469 */
470
471 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
472 * @{
473 */
474 #define DSI_FBTAA_DISABLE 0x00000000U
475 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
476 /**
477 * @}
478 */
479
480 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
481 * @{
482 */
483 #define DSI_TE_DSILINK 0x00000000U
484 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
485 /**
486 * @}
487 */
488
489 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
490 * @{
491 */
492 #define DSI_TE_RISING_EDGE 0x00000000U
493 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
494 /**
495 * @}
496 */
497
498 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
499 * @{
500 */
501 #define DSI_VSYNC_FALLING 0x00000000U
502 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
503 /**
504 * @}
505 */
506
507 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
508 * @{
509 */
510 #define DSI_AR_DISABLE 0x00000000U
511 #define DSI_AR_ENABLE DSI_WCFGR_AR
512 /**
513 * @}
514 */
515
516 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
517 * @{
518 */
519 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
520 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
521 /**
522 * @}
523 */
524
525 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
526 * @{
527 */
528 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
529 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
530 /**
531 * @}
532 */
533
534 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
535 * @{
536 */
537 #define DSI_LP_GSW0P_DISABLE 0x00000000U
538 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
539 /**
540 * @}
541 */
542
543 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
544 * @{
545 */
546 #define DSI_LP_GSW1P_DISABLE 0x00000000U
547 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
548 /**
549 * @}
550 */
551
552 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
553 * @{
554 */
555 #define DSI_LP_GSW2P_DISABLE 0x00000000U
556 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
557 /**
558 * @}
559 */
560
561 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
562 * @{
563 */
564 #define DSI_LP_GSR0P_DISABLE 0x00000000U
565 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
566 /**
567 * @}
568 */
569
570 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
571 * @{
572 */
573 #define DSI_LP_GSR1P_DISABLE 0x00000000U
574 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
575 /**
576 * @}
577 */
578
579 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
580 * @{
581 */
582 #define DSI_LP_GSR2P_DISABLE 0x00000000U
583 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
584 /**
585 * @}
586 */
587
588 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
589 * @{
590 */
591 #define DSI_LP_GLW_DISABLE 0x00000000U
592 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
593 /**
594 * @}
595 */
596
597 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
598 * @{
599 */
600 #define DSI_LP_DSW0P_DISABLE 0x00000000U
601 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
602 /**
603 * @}
604 */
605
606 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
607 * @{
608 */
609 #define DSI_LP_DSW1P_DISABLE 0x00000000U
610 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
611 /**
612 * @}
613 */
614
615 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
616 * @{
617 */
618 #define DSI_LP_DSR0P_DISABLE 0x00000000U
619 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
620 /**
621 * @}
622 */
623
624 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
625 * @{
626 */
627 #define DSI_LP_DLW_DISABLE 0x00000000U
628 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
629 /**
630 * @}
631 */
632
633 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
634 * @{
635 */
636 #define DSI_LP_MRDP_DISABLE 0x00000000U
637 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
638 /**
639 * @}
640 */
641
642 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
643 * @{
644 */
645 #define DSI_HS_PM_DISABLE 0x00000000U
646 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
647 /**
648 * @}
649 */
650
651
652 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
653 * @{
654 */
655 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
656 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
657 /**
658 * @}
659 */
660
661 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
662 * @{
663 */
664 #define DSI_ONE_DATA_LANE 0U
665 #define DSI_TWO_DATA_LANES 1U
666 /**
667 * @}
668 */
669
670 /** @defgroup DSI_FlowControl DSI Flow Control
671 * @{
672 */
673 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
674 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
675 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
676 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
677 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
678 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
679 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
680 DSI_FLOW_CONTROL_EOTP_TX)
681 /**
682 * @}
683 */
684
685 /** @defgroup DSI_Color_Coding DSI Color Coding
686 * @{
687 */
688 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
689 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
690 #define DSI_RGB888 0x00000005U
691 /**
692 * @}
693 */
694
695 /** @defgroup DSI_LooselyPacked DSI Loosely Packed
696 * @{
697 */
698 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
699 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
700 /**
701 * @}
702 */
703
704 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
705 * @{
706 */
707 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
708 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
709 /**
710 * @}
711 */
712
713 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
714 * @{
715 */
716 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
717 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
718 /**
719 * @}
720 */
721
722 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
723 * @{
724 */
725 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
726 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
727 /**
728 * @}
729 */
730
731 /** @defgroup DSI_PLL_IDF DSI PLL IDF
732 * @{
733 */
734 #define DSI_PLL_IN_DIV1 0x00000001U
735 #define DSI_PLL_IN_DIV2 0x00000002U
736 #define DSI_PLL_IN_DIV3 0x00000003U
737 #define DSI_PLL_IN_DIV4 0x00000004U
738 #define DSI_PLL_IN_DIV5 0x00000005U
739 #define DSI_PLL_IN_DIV6 0x00000006U
740 #define DSI_PLL_IN_DIV7 0x00000007U
741 /**
742 * @}
743 */
744
745 /** @defgroup DSI_PLL_ODF DSI PLL ODF
746 * @{
747 */
748 #define DSI_PLL_OUT_DIV1 0x00000000U
749 #define DSI_PLL_OUT_DIV2 0x00000001U
750 #define DSI_PLL_OUT_DIV4 0x00000002U
751 #define DSI_PLL_OUT_DIV8 0x00000003U
752 /**
753 * @}
754 */
755
756 /** @defgroup DSI_Flags DSI Flags
757 * @{
758 */
759 #define DSI_FLAG_TE DSI_WISR_TEIF
760 #define DSI_FLAG_ER DSI_WISR_ERIF
761 #define DSI_FLAG_BUSY DSI_WISR_BUSY
762 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
763 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF
764 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF
765 #define DSI_FLAG_RRS DSI_WISR_RRS
766 #define DSI_FLAG_RR DSI_WISR_RRIF
767 /**
768 * @}
769 */
770
771 /** @defgroup DSI_Interrupts DSI Interrupts
772 * @{
773 */
774 #define DSI_IT_TE DSI_WIER_TEIE
775 #define DSI_IT_ER DSI_WIER_ERIE
776 #define DSI_IT_PLLL DSI_WIER_PLLLIE
777 #define DSI_IT_PLLU DSI_WIER_PLLUIE
778 #define DSI_IT_RR DSI_WIER_RRIE
779 /**
780 * @}
781 */
782
783 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
784 * @{
785 */
786 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */
787 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */
788 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */
789 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */
790 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */
791 /**
792 * @}
793 */
794
795 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
796 * @{
797 */
798 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */
799 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */
800 /**
801 * @}
802 */
803
804 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
805 * @{
806 */
807 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */
808 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */
809 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */
810 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */
811 /**
812 * @}
813 */
814
815 /** @defgroup DSI_Error_Data_Type DSI Error Data Type
816 * @{
817 */
818 #define HAL_DSI_ERROR_NONE 0U
819 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
820 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
821 #define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
822 #define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
823 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
824 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
825 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
826 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
827 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
828 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
829 /**
830 * @}
831 */
832
833 /** @defgroup DSI_Lane_Group DSI Lane Group
834 * @{
835 */
836 #define DSI_CLOCK_LANE 0x00000000U
837 #define DSI_DATA_LANES 0x00000001U
838 /**
839 * @}
840 */
841
842 /** @defgroup DSI_Communication_Delay DSI Communication Delay
843 * @{
844 */
845 #define DSI_SLEW_RATE_HSTX 0x00000000U
846 #define DSI_SLEW_RATE_LPTX 0x00000001U
847 #define DSI_HS_DELAY 0x00000002U
848 /**
849 * @}
850 */
851
852 /** @defgroup DSI_CustomLane DSI CustomLane
853 * @{
854 */
855 #define DSI_SWAP_LANE_PINS 0x00000000U
856 #define DSI_INVERT_HS_SIGNAL 0x00000001U
857 /**
858 * @}
859 */
860
861 /** @defgroup DSI_Lane_Select DSI Lane Select
862 * @{
863 */
864 #define DSI_CLK_LANE 0x00000000U
865 #define DSI_DATA_LANE0 0x00000001U
866 #define DSI_DATA_LANE1 0x00000002U
867 /**
868 * @}
869 */
870
871 /** @defgroup DSI_PHY_Timing DSI PHY Timing
872 * @{
873 */
874 #define DSI_TCLK_POST 0x00000000U
875 #define DSI_TLPX_CLK 0x00000001U
876 #define DSI_THS_EXIT 0x00000002U
877 #define DSI_TLPX_DATA 0x00000003U
878 #define DSI_THS_ZERO 0x00000004U
879 #define DSI_THS_TRAIL 0x00000005U
880 #define DSI_THS_PREPARE 0x00000006U
881 #define DSI_TCLK_ZERO 0x00000007U
882 #define DSI_TCLK_PREPARE 0x00000008U
883 /**
884 * @}
885 */
886
887 /* Exported macros -----------------------------------------------------------*/
888 /**
889 * @brief Enables the DSI host.
890 * @param __HANDLE__ DSI handle
891 * @retval None.
892 */
893 #define __HAL_DSI_ENABLE(__HANDLE__) do { \
894 __IO uint32_t tmpreg = 0x00U; \
895 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
896 /* Delay after an DSI Host enabling */ \
897 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
898 UNUSED(tmpreg); \
899 }while(0U)
900
901 /**
902 * @brief Disables the DSI host.
903 * @param __HANDLE__ DSI handle
904 * @retval None.
905 */
906 #define __HAL_DSI_DISABLE(__HANDLE__) do { \
907 __IO uint32_t tmpreg = 0x00U; \
908 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
909 /* Delay after an DSI Host disabling */ \
910 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
911 UNUSED(tmpreg); \
912 }while(0U)
913
914 /**
915 * @brief Enables the DSI wrapper.
916 * @param __HANDLE__ DSI handle
917 * @retval None.
918 */
919 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
920 __IO uint32_t tmpreg = 0x00U; \
921 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
922 /* Delay after an DSI warpper enabling */ \
923 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
924 UNUSED(tmpreg); \
925 }while(0U)
926
927 /**
928 * @brief Disable the DSI wrapper.
929 * @param __HANDLE__ DSI handle
930 * @retval None.
931 */
932 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
933 __IO uint32_t tmpreg = 0x00U; \
934 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
935 /* Delay after an DSI warpper disabling*/ \
936 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
937 UNUSED(tmpreg); \
938 }while(0U)
939
940 /**
941 * @brief Enables the DSI PLL.
942 * @param __HANDLE__ DSI handle
943 * @retval None.
944 */
945 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
946 __IO uint32_t tmpreg = 0x00U; \
947 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
948 /* Delay after an DSI PLL enabling */ \
949 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
950 UNUSED(tmpreg); \
951 }while(0U)
952
953 /**
954 * @brief Disables the DSI PLL.
955 * @param __HANDLE__ DSI handle
956 * @retval None.
957 */
958 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
959 __IO uint32_t tmpreg = 0x00U; \
960 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
961 /* Delay after an DSI PLL disabling */ \
962 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
963 UNUSED(tmpreg); \
964 }while(0U)
965
966 /**
967 * @brief Enables the DSI regulator.
968 * @param __HANDLE__ DSI handle
969 * @retval None.
970 */
971 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
972 __IO uint32_t tmpreg = 0x00U; \
973 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
974 /* Delay after an DSI regulator enabling */ \
975 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
976 UNUSED(tmpreg); \
977 }while(0U)
978
979 /**
980 * @brief Disables the DSI regulator.
981 * @param __HANDLE__ DSI handle
982 * @retval None.
983 */
984 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
985 __IO uint32_t tmpreg = 0x00U; \
986 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
987 /* Delay after an DSI regulator disabling */ \
988 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
989 UNUSED(tmpreg); \
990 }while(0U)
991
992 /**
993 * @brief Get the DSI pending flags.
994 * @param __HANDLE__ DSI handle.
995 * @param __FLAG__ Get the specified flag.
996 * This parameter can be any combination of the following values:
997 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
998 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
999 * @arg DSI_FLAG_BUSY : Busy Flag
1000 * @arg DSI_FLAG_PLLLS: PLL Lock Status
1001 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
1002 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
1003 * @arg DSI_FLAG_RRS : Regulator Ready Flag
1004 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
1005 * @retval The state of FLAG (SET or RESET).
1006 */
1007 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
1008
1009 /**
1010 * @brief Clears the DSI pending flags.
1011 * @param __HANDLE__ DSI handle.
1012 * @param __FLAG__ specifies the flag to clear.
1013 * This parameter can be any combination of the following values:
1014 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
1015 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
1016 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
1017 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
1018 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
1019 * @retval None
1020 */
1021 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
1022
1023 /**
1024 * @brief Enables the specified DSI interrupts.
1025 * @param __HANDLE__ DSI handle.
1026 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
1027 * This parameter can be any combination of the following values:
1028 * @arg DSI_IT_TE : Tearing Effect Interrupt
1029 * @arg DSI_IT_ER : End of Refresh Interrupt
1030 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1031 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1032 * @arg DSI_IT_RR : Regulator Ready Interrupt
1033 * @retval None
1034 */
1035 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
1036
1037 /**
1038 * @brief Disables the specified DSI interrupts.
1039 * @param __HANDLE__ DSI handle
1040 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
1041 * This parameter can be any combination of the following values:
1042 * @arg DSI_IT_TE : Tearing Effect Interrupt
1043 * @arg DSI_IT_ER : End of Refresh Interrupt
1044 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1045 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1046 * @arg DSI_IT_RR : Regulator Ready Interrupt
1047 * @retval None
1048 */
1049 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
1050
1051 /**
1052 * @brief Checks whether the specified DSI interrupt source is enabled or not.
1053 * @param __HANDLE__ DSI handle
1054 * @param __INTERRUPT__ specifies the DSI interrupt source to check.
1055 * This parameter can be one of the following values:
1056 * @arg DSI_IT_TE : Tearing Effect Interrupt
1057 * @arg DSI_IT_ER : End of Refresh Interrupt
1058 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1059 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1060 * @arg DSI_IT_RR : Regulator Ready Interrupt
1061 * @retval The state of INTERRUPT (SET or RESET).
1062 */
1063 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
1064
1065 /* Exported functions --------------------------------------------------------*/
1066 /** @defgroup DSI_Exported_Functions DSI Exported Functions
1067 * @{
1068 */
1069 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
1070 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
1071 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
1072 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
1073
1074 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
1075 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
1076 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
1077 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
1078
1079 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
1080 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
1081 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
1082 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
1083 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
1084 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
1085 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
1086 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
1087 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
1088 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
1089 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
1090 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
1091 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1092 uint32_t ChannelID,
1093 uint32_t Mode,
1094 uint32_t Param1,
1095 uint32_t Param2);
1096 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1097 uint32_t ChannelID,
1098 uint32_t Mode,
1099 uint32_t NbParams,
1100 uint32_t Param1,
1101 uint8_t* ParametersTable);
1102 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1103 uint32_t ChannelNbr,
1104 uint8_t* Array,
1105 uint32_t Size,
1106 uint32_t Mode,
1107 uint32_t DCSCmd,
1108 uint8_t* ParametersTable);
1109 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
1110 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
1111 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
1112 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
1113
1114 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
1115 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
1116
1117 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
1118 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
1119 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
1120 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
1121 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
1122 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
1123 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
1124 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
1125 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
1126 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
1127
1128 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
1129 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
1130 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
1131 /**
1132 * @}
1133 */
1134
1135 /* Private types -------------------------------------------------------------*/
1136 /** @defgroup DSI_Private_Types DSI Private Types
1137 * @{
1138 */
1139
1140 /**
1141 * @}
1142 */
1143
1144 /* Private defines -----------------------------------------------------------*/
1145 /** @defgroup DSI_Private_Defines DSI Private Defines
1146 * @{
1147 */
1148
1149 /**
1150 * @}
1151 */
1152
1153 /* Private variables ---------------------------------------------------------*/
1154 /** @defgroup DSI_Private_Variables DSI Private Variables
1155 * @{
1156 */
1157
1158 /**
1159 * @}
1160 */
1161
1162 /* Private constants ---------------------------------------------------------*/
1163 /** @defgroup DSI_Private_Constants DSI Private Constants
1164 * @{
1165 */
1166 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */
1167 /**
1168 * @}
1169 */
1170
1171 /* Private macros ------------------------------------------------------------*/
1172 /** @defgroup DSI_Private_Macros DSI Private Macros
1173 * @{
1174 */
1175 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
1176 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
1177 ((IDF) == DSI_PLL_IN_DIV2) || \
1178 ((IDF) == DSI_PLL_IN_DIV3) || \
1179 ((IDF) == DSI_PLL_IN_DIV4) || \
1180 ((IDF) == DSI_PLL_IN_DIV5) || \
1181 ((IDF) == DSI_PLL_IN_DIV6) || \
1182 ((IDF) == DSI_PLL_IN_DIV7))
1183 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
1184 ((ODF) == DSI_PLL_OUT_DIV2) || \
1185 ((ODF) == DSI_PLL_OUT_DIV4) || \
1186 ((ODF) == DSI_PLL_OUT_DIV8))
1187 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
1188 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
1189 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
1190 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
1191 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
1192 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
1193 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
1194 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
1195 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
1196 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
1197 ((VideoModeType) == DSI_VID_MODE_BURST))
1198 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
1199 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
1200 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
1201 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
1202 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
1203 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
1204 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
1205 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
1206 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
1207 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
1208 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
1209 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
1210 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
1211 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
1212 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
1213 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
1214 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
1215 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
1216 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
1217 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
1218 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
1219 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
1220 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
1221 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
1222 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
1223 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
1224 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
1225 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
1226 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
1227 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
1228 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
1229 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
1230 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
1231 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
1232 ((MODE) == DSI_GEN_LONG_PKT_WRITE))
1233 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
1234 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
1235 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
1236 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
1237 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
1238 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
1239 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
1240 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
1241 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
1242 ((Timing) == DSI_TLPX_CLK ) || \
1243 ((Timing) == DSI_THS_EXIT ) || \
1244 ((Timing) == DSI_TLPX_DATA ) || \
1245 ((Timing) == DSI_THS_ZERO ) || \
1246 ((Timing) == DSI_THS_TRAIL ) || \
1247 ((Timing) == DSI_THS_PREPARE ) || \
1248 ((Timing) == DSI_TCLK_ZERO ) || \
1249 ((Timing) == DSI_TCLK_PREPARE))
1250
1251 /**
1252 * @}
1253 */
1254
1255 /* Private functions prototypes ----------------------------------------------*/
1256 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
1257 * @{
1258 */
1259
1260 /**
1261 * @}
1262 */
1263
1264 /* Private functions ---------------------------------------------------------*/
1265 /** @defgroup DSI_Private_Functions DSI Private Functions
1266 * @{
1267 */
1268
1269 /**
1270 * @}
1271 */
1272
1273 /**
1274 * @}
1275 */
1276
1277 /**
1278 * @}
1279 */
1280 #endif /* DSI */
1281
1282 #ifdef __cplusplus
1283 }
1284 #endif
1285
1286 #endif /* __STM32F4xx_HAL_DSI_H */
1287
1288 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/