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comparison Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_dma2d.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of DMA2D HAL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_HAL_DMA2D_H | |
38 #define __STM32F4xx_HAL_DMA2D_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ | |
45 defined(STM32F469xx) || defined(STM32F479xx) | |
46 /* Includes ------------------------------------------------------------------*/ | |
47 #include "stm32f4xx_hal_def.h" | |
48 | |
49 /** @addtogroup STM32F4xx_HAL_Driver | |
50 * @{ | |
51 */ | |
52 | |
53 /** @addtogroup DMA2D DMA2D | |
54 * @brief DMA2D HAL module driver | |
55 * @{ | |
56 */ | |
57 | |
58 /* Exported types ------------------------------------------------------------*/ | |
59 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types | |
60 * @{ | |
61 */ | |
62 #define MAX_DMA2D_LAYER 2U | |
63 | |
64 /** | |
65 * @brief DMA2D color Structure definition | |
66 */ | |
67 typedef struct | |
68 { | |
69 uint32_t Blue; /*!< Configures the blue value. | |
70 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ | |
71 | |
72 uint32_t Green; /*!< Configures the green value. | |
73 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ | |
74 | |
75 uint32_t Red; /*!< Configures the red value. | |
76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ | |
77 } DMA2D_ColorTypeDef; | |
78 | |
79 /** | |
80 * @brief DMA2D CLUT Structure definition | |
81 */ | |
82 typedef struct | |
83 { | |
84 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ | |
85 | |
86 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. | |
87 This parameter can be one value of @ref DMA2D_CLUT_CM. */ | |
88 | |
89 uint32_t Size; /*!< Configures the DMA2D CLUT size. | |
90 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ | |
91 } DMA2D_CLUTCfgTypeDef; | |
92 | |
93 /** | |
94 * @brief DMA2D Init structure definition | |
95 */ | |
96 typedef struct | |
97 { | |
98 uint32_t Mode; /*!< Configures the DMA2D transfer mode. | |
99 This parameter can be one value of @ref DMA2D_Mode. */ | |
100 | |
101 uint32_t ColorMode; /*!< Configures the color format of the output image. | |
102 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ | |
103 | |
104 uint32_t OutputOffset; /*!< Specifies the Offset value. | |
105 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ | |
106 | |
107 } DMA2D_InitTypeDef; | |
108 | |
109 /** | |
110 * @brief DMA2D Layer structure definition | |
111 */ | |
112 typedef struct | |
113 { | |
114 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. | |
115 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ | |
116 | |
117 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. | |
118 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ | |
119 | |
120 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. | |
121 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ | |
122 | |
123 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. | |
124 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. | |
125 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between | |
126 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where | |
127 - InputAlpha[24:31] is the alpha value ALPHA[0:7] | |
128 - InputAlpha[16:23] is the red value RED[0:7] | |
129 - InputAlpha[8:15] is the green value GREEN[0:7] | |
130 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ | |
131 | |
132 } DMA2D_LayerCfgTypeDef; | |
133 | |
134 /** | |
135 * @brief HAL DMA2D State structures definition | |
136 */ | |
137 typedef enum | |
138 { | |
139 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ | |
140 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ | |
141 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ | |
142 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ | |
143 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ | |
144 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ | |
145 }HAL_DMA2D_StateTypeDef; | |
146 | |
147 /** | |
148 * @brief DMA2D handle Structure definition | |
149 */ | |
150 typedef struct __DMA2D_HandleTypeDef | |
151 { | |
152 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ | |
153 | |
154 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ | |
155 | |
156 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ | |
157 | |
158 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ | |
159 | |
160 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ | |
161 | |
162 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ | |
163 | |
164 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ | |
165 | |
166 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ | |
167 } DMA2D_HandleTypeDef; | |
168 /** | |
169 * @} | |
170 */ | |
171 | |
172 /* Exported constants --------------------------------------------------------*/ | |
173 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants | |
174 * @{ | |
175 */ | |
176 | |
177 /** @defgroup DMA2D_Error_Code DMA2D Error Code | |
178 * @{ | |
179 */ | |
180 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ | |
181 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ | |
182 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ | |
183 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ | |
184 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ | |
185 /** | |
186 * @} | |
187 */ | |
188 | |
189 /** @defgroup DMA2D_Mode DMA2D Mode | |
190 * @{ | |
191 */ | |
192 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ | |
193 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ | |
194 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ | |
195 #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ | |
196 /** | |
197 * @} | |
198 */ | |
199 | |
200 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode | |
201 * @{ | |
202 */ | |
203 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ | |
204 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ | |
205 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ | |
206 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ | |
207 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ | |
208 /** | |
209 * @} | |
210 */ | |
211 | |
212 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode | |
213 * @{ | |
214 */ | |
215 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ | |
216 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ | |
217 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ | |
218 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ | |
219 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ | |
220 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ | |
221 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ | |
222 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ | |
223 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ | |
224 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ | |
225 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ | |
226 /** | |
227 * @} | |
228 */ | |
229 | |
230 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode | |
231 * @{ | |
232 */ | |
233 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ | |
234 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ | |
235 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value | |
236 with original alpha channel value */ | |
237 /** | |
238 * @} | |
239 */ | |
240 | |
241 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode | |
242 * @{ | |
243 */ | |
244 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ | |
245 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ | |
246 /** | |
247 * @} | |
248 */ | |
249 | |
250 /** @defgroup DMA2D_Interrupts DMA2D Interrupts | |
251 * @{ | |
252 */ | |
253 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ | |
254 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ | |
255 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ | |
256 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ | |
257 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ | |
258 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ | |
259 /** | |
260 * @} | |
261 */ | |
262 | |
263 /** @defgroup DMA2D_Flags DMA2D Flags | |
264 * @{ | |
265 */ | |
266 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ | |
267 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ | |
268 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ | |
269 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ | |
270 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ | |
271 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ | |
272 /** | |
273 * @} | |
274 */ | |
275 | |
276 /** @defgroup DMA2D_Aliases DMA2D API Aliases | |
277 * @{ | |
278 */ | |
279 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ | |
280 /** | |
281 * @} | |
282 */ | |
283 | |
284 /** | |
285 * @} | |
286 */ | |
287 /* Exported macros ------------------------------------------------------------*/ | |
288 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros | |
289 * @{ | |
290 */ | |
291 | |
292 /** @brief Reset DMA2D handle state | |
293 * @param __HANDLE__ specifies the DMA2D handle. | |
294 * @retval None | |
295 */ | |
296 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) | |
297 | |
298 /** | |
299 * @brief Enable the DMA2D. | |
300 * @param __HANDLE__ DMA2D handle | |
301 * @retval None. | |
302 */ | |
303 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) | |
304 | |
305 /* Interrupt & Flag management */ | |
306 /** | |
307 * @brief Get the DMA2D pending flags. | |
308 * @param __HANDLE__ DMA2D handle | |
309 * @param __FLAG__ flag to check. | |
310 * This parameter can be any combination of the following values: | |
311 * @arg DMA2D_FLAG_CE: Configuration error flag | |
312 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag | |
313 * @arg DMA2D_FLAG_CAE: CLUT access error flag | |
314 * @arg DMA2D_FLAG_TW: Transfer Watermark flag | |
315 * @arg DMA2D_FLAG_TC: Transfer complete flag | |
316 * @arg DMA2D_FLAG_TE: Transfer error flag | |
317 * @retval The state of FLAG. | |
318 */ | |
319 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) | |
320 | |
321 /** | |
322 * @brief Clear the DMA2D pending flags. | |
323 * @param __HANDLE__ DMA2D handle | |
324 * @param __FLAG__ specifies the flag to clear. | |
325 * This parameter can be any combination of the following values: | |
326 * @arg DMA2D_FLAG_CE: Configuration error flag | |
327 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag | |
328 * @arg DMA2D_FLAG_CAE: CLUT access error flag | |
329 * @arg DMA2D_FLAG_TW: Transfer Watermark flag | |
330 * @arg DMA2D_FLAG_TC: Transfer complete flag | |
331 * @arg DMA2D_FLAG_TE: Transfer error flag | |
332 * @retval None | |
333 */ | |
334 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) | |
335 | |
336 /** | |
337 * @brief Enable the specified DMA2D interrupts. | |
338 * @param __HANDLE__ DMA2D handle | |
339 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. | |
340 * This parameter can be any combination of the following values: | |
341 * @arg DMA2D_IT_CE: Configuration error interrupt mask | |
342 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask | |
343 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask | |
344 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask | |
345 * @arg DMA2D_IT_TC: Transfer complete interrupt mask | |
346 * @arg DMA2D_IT_TE: Transfer error interrupt mask | |
347 * @retval None | |
348 */ | |
349 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) | |
350 | |
351 /** | |
352 * @brief Disable the specified DMA2D interrupts. | |
353 * @param __HANDLE__ DMA2D handle | |
354 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. | |
355 * This parameter can be any combination of the following values: | |
356 * @arg DMA2D_IT_CE: Configuration error interrupt mask | |
357 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask | |
358 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask | |
359 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask | |
360 * @arg DMA2D_IT_TC: Transfer complete interrupt mask | |
361 * @arg DMA2D_IT_TE: Transfer error interrupt mask | |
362 * @retval None | |
363 */ | |
364 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) | |
365 | |
366 /** | |
367 * @brief Check whether the specified DMA2D interrupt source is enabled or not. | |
368 * @param __HANDLE__ DMA2D handle | |
369 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. | |
370 * This parameter can be one of the following values: | |
371 * @arg DMA2D_IT_CE: Configuration error interrupt mask | |
372 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask | |
373 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask | |
374 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask | |
375 * @arg DMA2D_IT_TC: Transfer complete interrupt mask | |
376 * @arg DMA2D_IT_TE: Transfer error interrupt mask | |
377 * @retval The state of INTERRUPT source. | |
378 */ | |
379 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) | |
380 | |
381 /** | |
382 * @} | |
383 */ | |
384 | |
385 /* Exported functions --------------------------------------------------------*/ | |
386 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions | |
387 * @{ | |
388 */ | |
389 | |
390 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions | |
391 * @{ | |
392 */ | |
393 | |
394 /* Initialization and de-initialization functions *******************************/ | |
395 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); | |
396 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); | |
397 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); | |
398 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); | |
399 | |
400 /** | |
401 * @} | |
402 */ | |
403 | |
404 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions | |
405 * @{ | |
406 */ | |
407 | |
408 /* IO operation functions *******************************************************/ | |
409 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); | |
410 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); | |
411 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); | |
412 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); | |
413 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); | |
414 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); | |
415 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); | |
416 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); | |
417 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); | |
418 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); | |
419 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); | |
420 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); | |
421 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); | |
422 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); | |
423 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); | |
424 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); | |
425 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); | |
426 | |
427 /** | |
428 * @} | |
429 */ | |
430 | |
431 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions | |
432 * @{ | |
433 */ | |
434 | |
435 /* Peripheral Control functions *************************************************/ | |
436 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); | |
437 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); | |
438 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); | |
439 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); | |
440 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); | |
441 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); | |
442 | |
443 /** | |
444 * @} | |
445 */ | |
446 | |
447 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions | |
448 * @{ | |
449 */ | |
450 | |
451 /* Peripheral State functions ***************************************************/ | |
452 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); | |
453 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); | |
454 | |
455 /** | |
456 * @} | |
457 */ | |
458 | |
459 /** | |
460 * @} | |
461 */ | |
462 | |
463 /* Private constants ---------------------------------------------------------*/ | |
464 | |
465 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants | |
466 * @{ | |
467 */ | |
468 | |
469 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark | |
470 * @{ | |
471 */ | |
472 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ | |
473 /** | |
474 * @} | |
475 */ | |
476 | |
477 /** @defgroup DMA2D_Color_Value DMA2D Color Value | |
478 * @{ | |
479 */ | |
480 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ | |
481 /** | |
482 * @} | |
483 */ | |
484 | |
485 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers | |
486 * @{ | |
487 */ | |
488 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ | |
489 /** | |
490 * @} | |
491 */ | |
492 | |
493 /** @defgroup DMA2D_Offset DMA2D Offset | |
494 * @{ | |
495 */ | |
496 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ | |
497 /** | |
498 * @} | |
499 */ | |
500 | |
501 /** @defgroup DMA2D_Size DMA2D Size | |
502 * @{ | |
503 */ | |
504 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */ | |
505 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */ | |
506 /** | |
507 * @} | |
508 */ | |
509 | |
510 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size | |
511 * @{ | |
512 */ | |
513 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D CLUT size */ | |
514 /** | |
515 * @} | |
516 */ | |
517 | |
518 /** | |
519 * @} | |
520 */ | |
521 | |
522 /* Private macros ------------------------------------------------------------*/ | |
523 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros | |
524 * @{ | |
525 */ | |
526 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) | |
527 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ | |
528 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) | |
529 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ | |
530 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ | |
531 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) | |
532 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) | |
533 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) | |
534 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) | |
535 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) | |
536 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ | |
537 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ | |
538 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ | |
539 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ | |
540 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ | |
541 ((INPUT_CM) == DMA2D_INPUT_A4)) | |
542 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ | |
543 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ | |
544 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) | |
545 | |
546 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) | |
547 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) | |
548 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) | |
549 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ | |
550 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ | |
551 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) | |
552 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ | |
553 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ | |
554 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) | |
555 /** | |
556 * @} | |
557 */ | |
558 | |
559 /** | |
560 * @} | |
561 */ | |
562 | |
563 /** | |
564 * @} | |
565 */ | |
566 | |
567 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ | |
568 | |
569 #ifdef __cplusplus | |
570 } | |
571 #endif | |
572 | |
573 #endif /* __STM32F4xx_HAL_DMA2D_H */ | |
574 | |
575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |