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comparison Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_dma.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of DMA HAL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_HAL_DMA_H | |
38 #define __STM32F4xx_HAL_DMA_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 /* Includes ------------------------------------------------------------------*/ | |
45 #include "stm32f4xx_hal_def.h" | |
46 | |
47 /** @addtogroup STM32F4xx_HAL_Driver | |
48 * @{ | |
49 */ | |
50 | |
51 /** @addtogroup DMA | |
52 * @{ | |
53 */ | |
54 | |
55 /* Exported types ------------------------------------------------------------*/ | |
56 | |
57 /** @defgroup DMA_Exported_Types DMA Exported Types | |
58 * @brief DMA Exported Types | |
59 * @{ | |
60 */ | |
61 | |
62 /** | |
63 * @brief DMA Configuration Structure definition | |
64 */ | |
65 typedef struct | |
66 { | |
67 uint32_t Channel; /*!< Specifies the channel used for the specified stream. | |
68 This parameter can be a value of @ref DMA_Channel_selection */ | |
69 | |
70 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, | |
71 from memory to memory or from peripheral to memory. | |
72 This parameter can be a value of @ref DMA_Data_transfer_direction */ | |
73 | |
74 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. | |
75 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ | |
76 | |
77 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. | |
78 This parameter can be a value of @ref DMA_Memory_incremented_mode */ | |
79 | |
80 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. | |
81 This parameter can be a value of @ref DMA_Peripheral_data_size */ | |
82 | |
83 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. | |
84 This parameter can be a value of @ref DMA_Memory_data_size */ | |
85 | |
86 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. | |
87 This parameter can be a value of @ref DMA_mode | |
88 @note The circular buffer mode cannot be used if the memory-to-memory | |
89 data transfer is configured on the selected Stream */ | |
90 | |
91 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. | |
92 This parameter can be a value of @ref DMA_Priority_level */ | |
93 | |
94 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. | |
95 This parameter can be a value of @ref DMA_FIFO_direct_mode | |
96 @note The Direct mode (FIFO mode disabled) cannot be used if the | |
97 memory-to-memory data transfer is configured on the selected stream */ | |
98 | |
99 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. | |
100 This parameter can be a value of @ref DMA_FIFO_threshold_level */ | |
101 | |
102 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. | |
103 It specifies the amount of data to be transferred in a single non interruptible | |
104 transaction. | |
105 This parameter can be a value of @ref DMA_Memory_burst | |
106 @note The burst mode is possible only if the address Increment mode is enabled. */ | |
107 | |
108 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. | |
109 It specifies the amount of data to be transferred in a single non interruptible | |
110 transaction. | |
111 This parameter can be a value of @ref DMA_Peripheral_burst | |
112 @note The burst mode is possible only if the address Increment mode is enabled. */ | |
113 }DMA_InitTypeDef; | |
114 | |
115 | |
116 /** | |
117 * @brief HAL DMA State structures definition | |
118 */ | |
119 typedef enum | |
120 { | |
121 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ | |
122 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ | |
123 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ | |
124 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ | |
125 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ | |
126 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ | |
127 }HAL_DMA_StateTypeDef; | |
128 | |
129 /** | |
130 * @brief HAL DMA Error Code structure definition | |
131 */ | |
132 typedef enum | |
133 { | |
134 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ | |
135 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ | |
136 }HAL_DMA_LevelCompleteTypeDef; | |
137 | |
138 /** | |
139 * @brief HAL DMA Error Code structure definition | |
140 */ | |
141 typedef enum | |
142 { | |
143 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ | |
144 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ | |
145 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ | |
146 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ | |
147 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ | |
148 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ | |
149 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ | |
150 }HAL_DMA_CallbackIDTypeDef; | |
151 | |
152 /** | |
153 * @brief DMA handle Structure definition | |
154 */ | |
155 typedef struct __DMA_HandleTypeDef | |
156 { | |
157 DMA_Stream_TypeDef *Instance; /*!< Register base address */ | |
158 | |
159 DMA_InitTypeDef Init; /*!< DMA communication parameters */ | |
160 | |
161 HAL_LockTypeDef Lock; /*!< DMA locking object */ | |
162 | |
163 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ | |
164 | |
165 void *Parent; /*!< Parent object state */ | |
166 | |
167 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ | |
168 | |
169 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ | |
170 | |
171 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ | |
172 | |
173 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ | |
174 | |
175 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ | |
176 | |
177 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ | |
178 | |
179 __IO uint32_t ErrorCode; /*!< DMA Error code */ | |
180 | |
181 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ | |
182 | |
183 uint32_t StreamIndex; /*!< DMA Stream Index */ | |
184 | |
185 }DMA_HandleTypeDef; | |
186 | |
187 /** | |
188 * @} | |
189 */ | |
190 | |
191 /* Exported constants --------------------------------------------------------*/ | |
192 | |
193 /** @defgroup DMA_Exported_Constants DMA Exported Constants | |
194 * @brief DMA Exported constants | |
195 * @{ | |
196 */ | |
197 | |
198 /** @defgroup DMA_Error_Code DMA Error Code | |
199 * @brief DMA Error Code | |
200 * @{ | |
201 */ | |
202 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ | |
203 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ | |
204 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ | |
205 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ | |
206 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ | |
207 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ | |
208 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ | |
209 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ | |
210 /** | |
211 * @} | |
212 */ | |
213 | |
214 /** @defgroup DMA_Channel_selection DMA Channel selection | |
215 * @brief DMA channel selection | |
216 * @{ | |
217 */ | |
218 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ | |
219 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ | |
220 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ | |
221 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ | |
222 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ | |
223 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ | |
224 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ | |
225 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ | |
226 #if defined (DMA_SxCR_CHSEL_3) | |
227 #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ | |
228 #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ | |
229 #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ | |
230 #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ | |
231 #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ | |
232 #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ | |
233 #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ | |
234 #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ | |
235 #endif /* DMA_SxCR_CHSEL_3 */ | |
236 /** | |
237 * @} | |
238 */ | |
239 | |
240 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction | |
241 * @brief DMA data transfer direction | |
242 * @{ | |
243 */ | |
244 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ | |
245 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ | |
246 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ | |
247 /** | |
248 * @} | |
249 */ | |
250 | |
251 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode | |
252 * @brief DMA peripheral incremented mode | |
253 * @{ | |
254 */ | |
255 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ | |
256 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ | |
257 /** | |
258 * @} | |
259 */ | |
260 | |
261 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode | |
262 * @brief DMA memory incremented mode | |
263 * @{ | |
264 */ | |
265 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ | |
266 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ | |
267 /** | |
268 * @} | |
269 */ | |
270 | |
271 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size | |
272 * @brief DMA peripheral data size | |
273 * @{ | |
274 */ | |
275 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ | |
276 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ | |
277 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ | |
278 /** | |
279 * @} | |
280 */ | |
281 | |
282 /** @defgroup DMA_Memory_data_size DMA Memory data size | |
283 * @brief DMA memory data size | |
284 * @{ | |
285 */ | |
286 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ | |
287 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ | |
288 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ | |
289 /** | |
290 * @} | |
291 */ | |
292 | |
293 /** @defgroup DMA_mode DMA mode | |
294 * @brief DMA mode | |
295 * @{ | |
296 */ | |
297 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ | |
298 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ | |
299 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ | |
300 /** | |
301 * @} | |
302 */ | |
303 | |
304 /** @defgroup DMA_Priority_level DMA Priority level | |
305 * @brief DMA priority levels | |
306 * @{ | |
307 */ | |
308 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ | |
309 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ | |
310 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ | |
311 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ | |
312 /** | |
313 * @} | |
314 */ | |
315 | |
316 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode | |
317 * @brief DMA FIFO direct mode | |
318 * @{ | |
319 */ | |
320 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ | |
321 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ | |
322 /** | |
323 * @} | |
324 */ | |
325 | |
326 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level | |
327 * @brief DMA FIFO level | |
328 * @{ | |
329 */ | |
330 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ | |
331 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ | |
332 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ | |
333 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ | |
334 /** | |
335 * @} | |
336 */ | |
337 | |
338 /** @defgroup DMA_Memory_burst DMA Memory burst | |
339 * @brief DMA memory burst | |
340 * @{ | |
341 */ | |
342 #define DMA_MBURST_SINGLE 0x00000000U | |
343 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) | |
344 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) | |
345 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) | |
346 /** | |
347 * @} | |
348 */ | |
349 | |
350 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst | |
351 * @brief DMA peripheral burst | |
352 * @{ | |
353 */ | |
354 #define DMA_PBURST_SINGLE 0x00000000U | |
355 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) | |
356 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) | |
357 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) | |
358 /** | |
359 * @} | |
360 */ | |
361 | |
362 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions | |
363 * @brief DMA interrupts definition | |
364 * @{ | |
365 */ | |
366 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) | |
367 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) | |
368 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) | |
369 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) | |
370 #define DMA_IT_FE 0x00000080U | |
371 /** | |
372 * @} | |
373 */ | |
374 | |
375 /** @defgroup DMA_flag_definitions DMA flag definitions | |
376 * @brief DMA flag definitions | |
377 * @{ | |
378 */ | |
379 #define DMA_FLAG_FEIF0_4 0x00000001U | |
380 #define DMA_FLAG_DMEIF0_4 0x00000004U | |
381 #define DMA_FLAG_TEIF0_4 0x00000008U | |
382 #define DMA_FLAG_HTIF0_4 0x00000010U | |
383 #define DMA_FLAG_TCIF0_4 0x00000020U | |
384 #define DMA_FLAG_FEIF1_5 0x00000040U | |
385 #define DMA_FLAG_DMEIF1_5 0x00000100U | |
386 #define DMA_FLAG_TEIF1_5 0x00000200U | |
387 #define DMA_FLAG_HTIF1_5 0x00000400U | |
388 #define DMA_FLAG_TCIF1_5 0x00000800U | |
389 #define DMA_FLAG_FEIF2_6 0x00010000U | |
390 #define DMA_FLAG_DMEIF2_6 0x00040000U | |
391 #define DMA_FLAG_TEIF2_6 0x00080000U | |
392 #define DMA_FLAG_HTIF2_6 0x00100000U | |
393 #define DMA_FLAG_TCIF2_6 0x00200000U | |
394 #define DMA_FLAG_FEIF3_7 0x00400000U | |
395 #define DMA_FLAG_DMEIF3_7 0x01000000U | |
396 #define DMA_FLAG_TEIF3_7 0x02000000U | |
397 #define DMA_FLAG_HTIF3_7 0x04000000U | |
398 #define DMA_FLAG_TCIF3_7 0x08000000U | |
399 /** | |
400 * @} | |
401 */ | |
402 | |
403 /** | |
404 * @} | |
405 */ | |
406 | |
407 /* Exported macro ------------------------------------------------------------*/ | |
408 | |
409 /** @brief Reset DMA handle state | |
410 * @param __HANDLE__ specifies the DMA handle. | |
411 * @retval None | |
412 */ | |
413 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) | |
414 | |
415 /** | |
416 * @brief Return the current DMA Stream FIFO filled level. | |
417 * @param __HANDLE__ DMA handle | |
418 * @retval The FIFO filling state. | |
419 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full | |
420 * and not empty. | |
421 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. | |
422 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. | |
423 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. | |
424 * - DMA_FIFOStatus_Empty: when FIFO is empty | |
425 * - DMA_FIFOStatus_Full: when FIFO is full | |
426 */ | |
427 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) | |
428 | |
429 /** | |
430 * @brief Enable the specified DMA Stream. | |
431 * @param __HANDLE__ DMA handle | |
432 * @retval None | |
433 */ | |
434 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) | |
435 | |
436 /** | |
437 * @brief Disable the specified DMA Stream. | |
438 * @param __HANDLE__ DMA handle | |
439 * @retval None | |
440 */ | |
441 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) | |
442 | |
443 /* Interrupt & Flag management */ | |
444 | |
445 /** | |
446 * @brief Return the current DMA Stream transfer complete flag. | |
447 * @param __HANDLE__ DMA handle | |
448 * @retval The specified transfer complete flag index. | |
449 */ | |
450 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ | |
451 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ | |
452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ | |
453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ | |
454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ | |
455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ | |
456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ | |
457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ | |
458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ | |
459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ | |
460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ | |
461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ | |
462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ | |
463 DMA_FLAG_TCIF3_7) | |
464 | |
465 /** | |
466 * @brief Return the current DMA Stream half transfer complete flag. | |
467 * @param __HANDLE__ DMA handle | |
468 * @retval The specified half transfer complete flag index. | |
469 */ | |
470 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ | |
471 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ | |
472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ | |
473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ | |
474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ | |
475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ | |
476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ | |
477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ | |
478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ | |
479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ | |
480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ | |
481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ | |
482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ | |
483 DMA_FLAG_HTIF3_7) | |
484 | |
485 /** | |
486 * @brief Return the current DMA Stream transfer error flag. | |
487 * @param __HANDLE__ DMA handle | |
488 * @retval The specified transfer error flag index. | |
489 */ | |
490 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ | |
491 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ | |
492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ | |
493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ | |
494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ | |
495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ | |
496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ | |
497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ | |
498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ | |
499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ | |
500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ | |
501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ | |
502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ | |
503 DMA_FLAG_TEIF3_7) | |
504 | |
505 /** | |
506 * @brief Return the current DMA Stream FIFO error flag. | |
507 * @param __HANDLE__ DMA handle | |
508 * @retval The specified FIFO error flag index. | |
509 */ | |
510 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ | |
511 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ | |
512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ | |
513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ | |
514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ | |
515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ | |
516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ | |
517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ | |
518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ | |
519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ | |
520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ | |
521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ | |
522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ | |
523 DMA_FLAG_FEIF3_7) | |
524 | |
525 /** | |
526 * @brief Return the current DMA Stream direct mode error flag. | |
527 * @param __HANDLE__ DMA handle | |
528 * @retval The specified direct mode error flag index. | |
529 */ | |
530 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ | |
531 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ | |
532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ | |
533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ | |
534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ | |
535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ | |
536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ | |
537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ | |
538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ | |
539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ | |
540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ | |
541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ | |
542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ | |
543 DMA_FLAG_DMEIF3_7) | |
544 | |
545 /** | |
546 * @brief Get the DMA Stream pending flags. | |
547 * @param __HANDLE__ DMA handle | |
548 * @param __FLAG__ Get the specified flag. | |
549 * This parameter can be any combination of the following values: | |
550 * @arg DMA_FLAG_TCIFx: Transfer complete flag. | |
551 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. | |
552 * @arg DMA_FLAG_TEIFx: Transfer error flag. | |
553 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. | |
554 * @arg DMA_FLAG_FEIFx: FIFO error flag. | |
555 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. | |
556 * @retval The state of FLAG (SET or RESET). | |
557 */ | |
558 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ | |
559 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ | |
560 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ | |
561 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) | |
562 | |
563 /** | |
564 * @brief Clear the DMA Stream pending flags. | |
565 * @param __HANDLE__ DMA handle | |
566 * @param __FLAG__ specifies the flag to clear. | |
567 * This parameter can be any combination of the following values: | |
568 * @arg DMA_FLAG_TCIFx: Transfer complete flag. | |
569 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. | |
570 * @arg DMA_FLAG_TEIFx: Transfer error flag. | |
571 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. | |
572 * @arg DMA_FLAG_FEIFx: FIFO error flag. | |
573 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. | |
574 * @retval None | |
575 */ | |
576 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ | |
577 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ | |
578 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ | |
579 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) | |
580 | |
581 /** | |
582 * @brief Enable the specified DMA Stream interrupts. | |
583 * @param __HANDLE__ DMA handle | |
584 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. | |
585 * This parameter can be any combination of the following values: | |
586 * @arg DMA_IT_TC: Transfer complete interrupt mask. | |
587 * @arg DMA_IT_HT: Half transfer complete interrupt mask. | |
588 * @arg DMA_IT_TE: Transfer error interrupt mask. | |
589 * @arg DMA_IT_FE: FIFO error interrupt mask. | |
590 * @arg DMA_IT_DME: Direct mode error interrupt. | |
591 * @retval None | |
592 */ | |
593 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ | |
594 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) | |
595 | |
596 /** | |
597 * @brief Disable the specified DMA Stream interrupts. | |
598 * @param __HANDLE__ DMA handle | |
599 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. | |
600 * This parameter can be any combination of the following values: | |
601 * @arg DMA_IT_TC: Transfer complete interrupt mask. | |
602 * @arg DMA_IT_HT: Half transfer complete interrupt mask. | |
603 * @arg DMA_IT_TE: Transfer error interrupt mask. | |
604 * @arg DMA_IT_FE: FIFO error interrupt mask. | |
605 * @arg DMA_IT_DME: Direct mode error interrupt. | |
606 * @retval None | |
607 */ | |
608 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ | |
609 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) | |
610 | |
611 /** | |
612 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. | |
613 * @param __HANDLE__ DMA handle | |
614 * @param __INTERRUPT__ specifies the DMA interrupt source to check. | |
615 * This parameter can be one of the following values: | |
616 * @arg DMA_IT_TC: Transfer complete interrupt mask. | |
617 * @arg DMA_IT_HT: Half transfer complete interrupt mask. | |
618 * @arg DMA_IT_TE: Transfer error interrupt mask. | |
619 * @arg DMA_IT_FE: FIFO error interrupt mask. | |
620 * @arg DMA_IT_DME: Direct mode error interrupt. | |
621 * @retval The state of DMA_IT. | |
622 */ | |
623 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ | |
624 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ | |
625 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) | |
626 | |
627 /** | |
628 * @brief Writes the number of data units to be transferred on the DMA Stream. | |
629 * @param __HANDLE__ DMA handle | |
630 * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) | |
631 * Number of data items depends only on the Peripheral data format. | |
632 * | |
633 * @note If Peripheral data format is Bytes: number of data units is equal | |
634 * to total number of bytes to be transferred. | |
635 * | |
636 * @note If Peripheral data format is Half-Word: number of data units is | |
637 * equal to total number of bytes to be transferred / 2. | |
638 * | |
639 * @note If Peripheral data format is Word: number of data units is equal | |
640 * to total number of bytes to be transferred / 4. | |
641 * | |
642 * @retval The number of remaining data units in the current DMAy Streamx transfer. | |
643 */ | |
644 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) | |
645 | |
646 /** | |
647 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. | |
648 * @param __HANDLE__ DMA handle | |
649 * | |
650 * @retval The number of remaining data units in the current DMA Stream transfer. | |
651 */ | |
652 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) | |
653 | |
654 | |
655 /* Include DMA HAL Extension module */ | |
656 #include "stm32f4xx_hal_dma_ex.h" | |
657 | |
658 /* Exported functions --------------------------------------------------------*/ | |
659 | |
660 /** @defgroup DMA_Exported_Functions DMA Exported Functions | |
661 * @brief DMA Exported functions | |
662 * @{ | |
663 */ | |
664 | |
665 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions | |
666 * @brief Initialization and de-initialization functions | |
667 * @{ | |
668 */ | |
669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); | |
670 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); | |
671 /** | |
672 * @} | |
673 */ | |
674 | |
675 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions | |
676 * @brief I/O operation functions | |
677 * @{ | |
678 */ | |
679 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); | |
680 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); | |
681 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); | |
682 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); | |
683 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); | |
684 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); | |
685 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); | |
686 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); | |
687 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); | |
688 | |
689 /** | |
690 * @} | |
691 */ | |
692 | |
693 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions | |
694 * @brief Peripheral State functions | |
695 * @{ | |
696 */ | |
697 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); | |
698 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); | |
699 /** | |
700 * @} | |
701 */ | |
702 /** | |
703 * @} | |
704 */ | |
705 /* Private Constants -------------------------------------------------------------*/ | |
706 /** @defgroup DMA_Private_Constants DMA Private Constants | |
707 * @brief DMA private defines and constants | |
708 * @{ | |
709 */ | |
710 /** | |
711 * @} | |
712 */ | |
713 | |
714 /* Private macros ------------------------------------------------------------*/ | |
715 /** @defgroup DMA_Private_Macros DMA Private Macros | |
716 * @brief DMA private macros | |
717 * @{ | |
718 */ | |
719 #if defined (DMA_SxCR_CHSEL_3) | |
720 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ | |
721 ((CHANNEL) == DMA_CHANNEL_1) || \ | |
722 ((CHANNEL) == DMA_CHANNEL_2) || \ | |
723 ((CHANNEL) == DMA_CHANNEL_3) || \ | |
724 ((CHANNEL) == DMA_CHANNEL_4) || \ | |
725 ((CHANNEL) == DMA_CHANNEL_5) || \ | |
726 ((CHANNEL) == DMA_CHANNEL_6) || \ | |
727 ((CHANNEL) == DMA_CHANNEL_7) || \ | |
728 ((CHANNEL) == DMA_CHANNEL_8) || \ | |
729 ((CHANNEL) == DMA_CHANNEL_9) || \ | |
730 ((CHANNEL) == DMA_CHANNEL_10)|| \ | |
731 ((CHANNEL) == DMA_CHANNEL_11)|| \ | |
732 ((CHANNEL) == DMA_CHANNEL_12)|| \ | |
733 ((CHANNEL) == DMA_CHANNEL_13)|| \ | |
734 ((CHANNEL) == DMA_CHANNEL_14)|| \ | |
735 ((CHANNEL) == DMA_CHANNEL_15)) | |
736 #else | |
737 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ | |
738 ((CHANNEL) == DMA_CHANNEL_1) || \ | |
739 ((CHANNEL) == DMA_CHANNEL_2) || \ | |
740 ((CHANNEL) == DMA_CHANNEL_3) || \ | |
741 ((CHANNEL) == DMA_CHANNEL_4) || \ | |
742 ((CHANNEL) == DMA_CHANNEL_5) || \ | |
743 ((CHANNEL) == DMA_CHANNEL_6) || \ | |
744 ((CHANNEL) == DMA_CHANNEL_7)) | |
745 #endif /* DMA_SxCR_CHSEL_3 */ | |
746 | |
747 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ | |
748 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ | |
749 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) | |
750 | |
751 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) | |
752 | |
753 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ | |
754 ((STATE) == DMA_PINC_DISABLE)) | |
755 | |
756 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ | |
757 ((STATE) == DMA_MINC_DISABLE)) | |
758 | |
759 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ | |
760 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ | |
761 ((SIZE) == DMA_PDATAALIGN_WORD)) | |
762 | |
763 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ | |
764 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ | |
765 ((SIZE) == DMA_MDATAALIGN_WORD )) | |
766 | |
767 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ | |
768 ((MODE) == DMA_CIRCULAR) || \ | |
769 ((MODE) == DMA_PFCTRL)) | |
770 | |
771 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ | |
772 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ | |
773 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ | |
774 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) | |
775 | |
776 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ | |
777 ((STATE) == DMA_FIFOMODE_ENABLE)) | |
778 | |
779 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ | |
780 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ | |
781 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ | |
782 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) | |
783 | |
784 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ | |
785 ((BURST) == DMA_MBURST_INC4) || \ | |
786 ((BURST) == DMA_MBURST_INC8) || \ | |
787 ((BURST) == DMA_MBURST_INC16)) | |
788 | |
789 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ | |
790 ((BURST) == DMA_PBURST_INC4) || \ | |
791 ((BURST) == DMA_PBURST_INC8) || \ | |
792 ((BURST) == DMA_PBURST_INC16)) | |
793 /** | |
794 * @} | |
795 */ | |
796 | |
797 /* Private functions ---------------------------------------------------------*/ | |
798 /** @defgroup DMA_Private_Functions DMA Private Functions | |
799 * @brief DMA private functions | |
800 * @{ | |
801 */ | |
802 /** | |
803 * @} | |
804 */ | |
805 | |
806 /** | |
807 * @} | |
808 */ | |
809 | |
810 /** | |
811 * @} | |
812 */ | |
813 | |
814 #ifdef __cplusplus | |
815 } | |
816 #endif | |
817 | |
818 #endif /* __STM32F4xx_HAL_DMA_H */ | |
819 | |
820 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |