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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dfsdm.h
4 * @author MCD Application Team
5 * @brief Header file of DFSDM HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_HAL_DFSDM_H
38 #define __STM32F4xx_HAL_DFSDM_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32f4xx_hal_def.h"
47
48 /** @addtogroup STM32F4xx_HAL_Driver
49 * @{
50 */
51
52 /** @addtogroup DFSDM
53 * @{
54 */
55
56 /* Exported types ------------------------------------------------------------*/
57 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types
58 * @{
59 */
60
61 /**
62 * @brief HAL DFSDM Channel states definition
63 */
64 typedef enum
65 {
66 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
67 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
68 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
69 }HAL_DFSDM_Channel_StateTypeDef;
70
71 /**
72 * @brief DFSDM channel output clock structure definition
73 */
74 typedef struct
75 {
76 FunctionalState Activation; /*!< Output clock enable/disable */
77 uint32_t Selection; /*!< Output clock is system clock or audio clock.
78 This parameter can be a value of @ref DFSDM_Channel_OuputClock */
79 uint32_t Divider; /*!< Output clock divider.
80 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
81 }DFSDM_Channel_OutputClockTypeDef;
82
83 /**
84 * @brief DFSDM channel input structure definition
85 */
86 typedef struct
87 {
88 uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
89 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
90 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
91 This parameter can be a value of @ref DFSDM_Channel_DataPacking */
92 uint32_t Pins; /*!< Input pins are taken from same or following channel.
93 This parameter can be a value of @ref DFSDM_Channel_InputPins */
94 }DFSDM_Channel_InputTypeDef;
95
96 /**
97 * @brief DFSDM channel serial interface structure definition
98 */
99 typedef struct
100 {
101 uint32_t Type; /*!< SPI or Manchester modes.
102 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
103 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
104 This parameter can be a value of @ref DFSDM_Channel_SpiClock */
105 }DFSDM_Channel_SerialInterfaceTypeDef;
106
107 /**
108 * @brief DFSDM channel analog watchdog structure definition
109 */
110 typedef struct
111 {
112 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
113 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
114 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
115 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
116 }DFSDM_Channel_AwdTypeDef;
117
118 /**
119 * @brief DFSDM channel init structure definition
120 */
121 typedef struct
122 {
123 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
124 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
125 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
126 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
127 int32_t Offset; /*!< DFSDM channel offset.
128 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
129 uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
130 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
131 }DFSDM_Channel_InitTypeDef;
132
133 /**
134 * @brief DFSDM channel handle structure definition
135 */
136 typedef struct
137 {
138 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
139 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
140 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
141 }DFSDM_Channel_HandleTypeDef;
142
143 /**
144 * @brief HAL DFSDM Filter states definition
145 */
146 typedef enum
147 {
148 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
149 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */
150 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */
151 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */
152 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
153 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
154 }HAL_DFSDM_Filter_StateTypeDef;
155
156 /**
157 * @brief DFSDM filter regular conversion parameters structure definition
158 */
159 typedef struct
160 {
161 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
162 This parameter can be a value of @ref DFSDM_Filter_Trigger */
163 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
164 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
165 }DFSDM_Filter_RegularParamTypeDef;
166
167 /**
168 * @brief DFSDM filter injected conversion parameters structure definition
169 */
170 typedef struct
171 {
172 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
173 This parameter can be a value of @ref DFSDM_Filter_Trigger */
174 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
175 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
176 uint32_t ExtTrigger; /*!< External trigger.
177 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
178 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
179 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
180 }DFSDM_Filter_InjectedParamTypeDef;
181
182 /**
183 * @brief DFSDM filter parameters structure definition
184 */
185 typedef struct
186 {
187 uint32_t SincOrder; /*!< Sinc filter order.
188 This parameter can be a value of @ref DFSDM_Filter_SincOrder */
189 uint32_t Oversampling; /*!< Filter oversampling ratio.
190 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
191 uint32_t IntOversampling; /*!< Integrator oversampling ratio.
192 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
193 }DFSDM_Filter_FilterParamTypeDef;
194
195 /**
196 * @brief DFSDM filter init structure definition
197 */
198 typedef struct
199 {
200 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
201 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
202 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
203 }DFSDM_Filter_InitTypeDef;
204
205 /**
206 * @brief DFSDM filter handle structure definition
207 */
208 typedef struct
209 {
210 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
211 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
212 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
213 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
214 uint32_t RegularContMode; /*!< Regular conversion continuous mode */
215 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
216 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
217 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
218 FunctionalState InjectedScanMode; /*!< Injected scanning mode */
219 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
220 uint32_t InjConvRemaining; /*!< Injected conversions remaining */
221 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
222 uint32_t ErrorCode; /*!< DFSDM filter error code */
223 }DFSDM_Filter_HandleTypeDef;
224
225 /**
226 * @brief DFSDM filter analog watchdog parameters structure definition
227 */
228 typedef struct
229 {
230 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
231 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
232 uint32_t Channel; /*!< Analog watchdog channel selection.
233 This parameter can be a values combination of @ref DFSDM_Channel_Selection */
234 int32_t HighThreshold; /*!< High threshold for the analog watchdog.
235 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
236 int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
237 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
238 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
239 This parameter can be a values combination of @ref DFSDM_BreakSignals */
240 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
241 This parameter can be a values combination of @ref DFSDM_BreakSignals */
242 }DFSDM_Filter_AwdParamTypeDef;
243
244 /**
245 * @}
246 */
247 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
248 /**
249 * @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices
250 */
251 typedef struct
252 {
253 uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin.
254 This parameter can be a value of @ref DFSDM_1_CLOCKIN_SELECTION*/
255 uint32_t DFSDM2ClockIn; /*!< Source selection for DFSDM2_Ckin.
256 This parameter can be a value of @ref DFSDM_2_CLOCKIN_SELECTION*/
257 uint32_t DFSDM1ClockOut; /*!< Source selection for DFSDM1_Ckout.
258 This parameter can be a value of @ref DFSDM_1_CLOCKOUT_SELECTION*/
259 uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout.
260 This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/
261 uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2.
262 This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION
263 @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2
264 @note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */
265 uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4.
266 This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION
267 @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4
268 @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5
269 @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6
270 @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */
271 uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1.
272 This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */
273 uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2.
274 This parameter can be a value of @ref DFSDM_2_DATA_DISTRIBUTION */
275 }DFSDM_MultiChannelConfigTypeDef;
276 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */
277 /**
278 * @}
279 */
280
281 /* End of exported types -----------------------------------------------------*/
282
283 /* Exported constants --------------------------------------------------------*/
284 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
285 * @{
286 */
287
288 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
289 * @{
290 */
291 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
292 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
293 /**
294 * @}
295 */
296
297 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
298 * @{
299 */
300 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */
301 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
302 /**
303 * @}
304 */
305
306 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
307 * @{
308 */
309 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */
310 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
311 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
312 /**
313 * @}
314 */
315
316 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
317 * @{
318 */
319 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */
320 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
321 /**
322 * @}
323 */
324
325 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
326 * @{
327 */
328 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */
329 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
330 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
331 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
332 /**
333 * @}
334 */
335
336 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
337 * @{
338 */
339 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */
340 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
341 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
342 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
343 /**
344 * @}
345 */
346
347 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
348 * @{
349 */
350 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
351 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
352 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
353 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
354 /**
355 * @}
356 */
357
358 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
359 * @{
360 */
361 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */
362 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */
363 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */
364 /**
365 * @}
366 */
367
368 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
369 * @{
370 */
371 #if defined(STM32F413xx) || defined(STM32F423xx)
372 /* Trigger for stm32f413xx and STM32f423xx devices */
373 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For All DFSDM1/2 filters */
374 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For All DFSDM1/2 filters */
375 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For All DFSDM1/2 filters */
376 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */
377 #define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM2 filter 3 */
378 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */
379 #define DFSDM_FILTER_EXT_TRIG_TIM11_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM2 filter 3 */
380 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0 and 1 */
381 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM2 filter 2 and 3*/
382 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For All DFSDM1/2 filters */
383 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For All DFSDM1/2 filters */
384 #else
385 /* Trigger for stm32f412xx devices */
386 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM1 filter 0 and 1*/
387 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM1 filter 0 and 1*/
388 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM1 filter 0 and 1*/
389 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1*/
390 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1*/
391 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/
392 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/
393 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM1 filter 0 and 1*/
394 #endif
395 /**
396 * @}
397 */
398
399 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
400 * @{
401 */
402 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
403 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
404 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
405 /**
406 * @}
407 */
408
409 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
410 * @{
411 */
412 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
413 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
414 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
415 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
416 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
417 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
418 /**
419 * @}
420 */
421
422 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
423 * @{
424 */
425 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */
426 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
427 /**
428 * @}
429 */
430
431 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
432 * @{
433 */
434 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */
435 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */
436 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
437 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */
438 /**
439 * @}
440 */
441
442 /** @defgroup DFSDM_BreakSignals DFSDM break signals
443 * @{
444 */
445 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */
446 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */
447 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */
448 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */
449 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */
450 /**
451 * @}
452 */
453
454 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
455 * @{
456 */
457 /* DFSDM Channels ------------------------------------------------------------*/
458 /* The DFSDM channels are defined as follows:
459 - in 16-bit LSB the channel mask is set
460 - in 16-bit MSB the channel number is set
461 e.g. for channel 3 definition:
462 - the channel mask is 0x00000008 (bit 3 is set)
463 - the channel number 3 is 0x00030000
464 --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */
465 #define DFSDM_CHANNEL_0 0x00000001U
466 #define DFSDM_CHANNEL_1 0x00010002U
467 #define DFSDM_CHANNEL_2 0x00020004U
468 #define DFSDM_CHANNEL_3 0x00030008U
469 #define DFSDM_CHANNEL_4 0x00040010U /* only for stmm32f413xx and stm32f423xx devices */
470 #define DFSDM_CHANNEL_5 0x00050020U /* only for stmm32f413xx and stm32f423xx devices */
471 #define DFSDM_CHANNEL_6 0x00060040U /* only for stmm32f413xx and stm32f423xx devices */
472 #define DFSDM_CHANNEL_7 0x00070080U /* only for stmm32f413xx and stm32f423xx devices */
473 /**
474 * @}
475 */
476
477 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
478 * @{
479 */
480 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */
481 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */
482 /**
483 * @}
484 */
485
486 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
487 * @{
488 */
489 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */
490 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */
491 /**
492 * @}
493 */
494
495 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
496 /** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection
497 * @{
498 */
499 #define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U
500 #define DFSDM1_CKOUT_DFSDM1 0x00000000U
501 /**
502 * @}
503 */
504
505 /** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection
506 * @{
507 */
508 #define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U
509 #define DFSDM2_CKOUT_DFSDM2 0x00000000U
510 /**
511 * @}
512 */
513
514 /** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection
515 * @{
516 */
517 #define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U
518 #define DFSDM1_CKIN_PAD 0x00000000U
519 /**
520 * @}
521 */
522
523 /** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection
524 * @{
525 */
526 #define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U
527 #define DFSDM2_CKIN_PAD 0x00000000U
528 /**
529 * @}
530 */
531
532 /** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution
533 * @{
534 */
535 #define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */
536 #define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */
537 #define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */
538 #define DFSDM1_T4_OC1_BITSTREAM_CKIN1 0x00000000U /* TIM4_OC1 to CLKIN1 */
539 /**
540 * @}
541 */
542
543 /** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution
544 * @{
545 */
546 #define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */
547 #define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */
548 #define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */
549 #define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */
550 #define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */
551 #define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */
552 #define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */
553 #define DFSDM2_T3_OC1_BITSTREAM_CKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */
554 /**
555 * @}
556 */
557
558 /** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution
559 * @{
560 */
561 #define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U
562 #define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL
563 #define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U
564 #define DFSDM1_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM1D2SEL
565 /**
566 * @}
567 */
568
569 /** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution
570 * @{
571 */
572 #define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U
573 #define DFSDM2_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM2D0SEL
574 #define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U
575 #define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL
576 #define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U
577 #define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL
578 #define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U
579 #define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL
580 /**
581 * @}
582 */
583
584 /** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable
585 * @{
586 */
587 #define HAL_MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN
588 #define HAL_MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN
589 /**
590 * @}
591 */
592
593 /** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection
594 * @{
595 */
596 #define HAL_DFSDM2_CKIN_PAD 0x00040000U
597 #define HAL_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
598 #define HAL_DFSDM1_CKIN_PAD 0x00000000U
599 #define HAL_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
600 /**
601 * @}
602 */
603
604 /** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection
605 * @{
606 */
607 #define HAL_DFSDM2_CKOUT_DFSDM2 0x10000000U
608 #define HAL_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
609 #define HAL_DFSDM1_CKOUT_DFSDM1 0x00000000U
610 #define HAL_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
611 /**
612 * @}
613 */
614
615 /** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0
616 * @{
617 */
618 #define HAL_DATAIN0_DFSDM2_PAD 0x10000000U
619 #define HAL_DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL
620 #define HAL_DATAIN0_DFSDM1_PAD 0x00000000U
621 #define HAL_DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL
622 /**
623 * @}
624 */
625
626 /** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2
627 * @{
628 */
629 #define HAL_DATAIN2_DFSDM2_PAD 0x10000000U
630 #define HAL_DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL
631 #define HAL_DATAIN2_DFSDM1_PAD 0x00000000U
632 #define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL
633 /**
634 * @}
635 */
636
637 /** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4
638 * @{
639 */
640 #define HAL_DATAIN4_DFSDM2_PAD 0x00000000U
641 #define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL
642 /**
643 * @}
644 */
645
646 /** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6
647 * @{
648 */
649 #define HAL_DATAIN6_DFSDM2_PAD 0x00000000U
650 #define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL
651 /**
652 * @}
653 */
654
655 /** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN
656 * @{
657 */
658 #define HAL_DFSDM1_CLKIN0_TIM4OC2 0x01000000U
659 #define HAL_DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
660 #define HAL_DFSDM1_CLKIN1_TIM4OC1 0x02000000U
661 #define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
662 /**
663 * @}
664 */
665
666 /** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN
667 * @{
668 */
669 #define HAL_DFSDM2_CLKIN0_TIM3OC4 0x04000000U
670 #define HAL_DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
671 #define HAL_DFSDM2_CLKIN1_TIM3OC3 0x08000000U
672 #define HAL_DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
673 #define HAL_DFSDM2_CLKIN2_TIM3OC2 0x10000000U
674 #define HAL_DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
675 #define HAL_DFSDM2_CLKIN3_TIM3OC1 0x00000000U
676 #define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
677 /**
678 * @}
679 */
680
681 #endif /* SYSCFG_MCHDLYCR_BSCKSEL*/
682 /**
683 * @}
684 */
685 /* End of exported constants -------------------------------------------------*/
686
687 /* Exported macros -----------------------------------------------------------*/
688 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
689 * @{
690 */
691
692 /** @brief Reset DFSDM channel handle state.
693 * @param __HANDLE__ DFSDM channel handle.
694 * @retval None
695 */
696 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
697
698 /** @brief Reset DFSDM filter handle state.
699 * @param __HANDLE__ DFSDM filter handle.
700 * @retval None
701 */
702 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
703
704 /**
705 * @}
706 */
707 /* End of exported macros ----------------------------------------------------*/
708
709 /* Exported functions --------------------------------------------------------*/
710 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
711 * @{
712 */
713
714 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
715 * @{
716 */
717 /* Channel initialization and de-initialization functions *********************/
718 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
719 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
720 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
721 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
722 /**
723 * @}
724 */
725
726 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
727 * @{
728 */
729 /* Channel operation functions ************************************************/
730 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
731 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
732 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
733 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
734
735 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
736 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
737 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
738 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
739
740 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
741 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
742
743 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
744 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
745
746 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
747 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
748 /**
749 * @}
750 */
751
752 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
753 * @{
754 */
755 /* Channel state function *****************************************************/
756 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
757 /**
758 * @}
759 */
760
761 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
762 * @{
763 */
764 /* Filter initialization and de-initialization functions *********************/
765 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
766 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
767 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
768 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
769 /**
770 * @}
771 */
772
773 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
774 * @{
775 */
776 /* Filter control functions *********************/
777 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
778 uint32_t Channel,
779 uint32_t ContinuousMode);
780 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
781 uint32_t Channel);
782 /**
783 * @}
784 */
785
786 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
787 * @{
788 */
789 /* Filter operation functions *********************/
790 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
791 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
792 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
793 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
794 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
795 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
796 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
797 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
798 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
799 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
800 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
801 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
802 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
803 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
804 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
805 DFSDM_Filter_AwdParamTypeDef* awdParam);
806 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
807 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
808 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
809
810 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
811 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
812 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
813 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
814 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
815
816 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
817
818 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
819 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
820
821 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
822 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
823 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
824 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
825 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
826 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
827 /**
828 * @}
829 */
830
831 /** @addtogroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
832 * @{
833 */
834 /* Filter state functions *****************************************************/
835 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
836 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
837 /**
838 * @}
839 */
840 /** @addtogroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions
841 * @{
842 */
843 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
844 void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct);
845 void HAL_DFSDM_BitstreamClock_Start(void);
846 void HAL_DFSDM_BitstreamClock_Stop(void);
847 void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY);
848 void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY);
849 void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source);
850 void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source);
851 void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source);
852 void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source);
853 void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source);
854 void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source);
855 void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
856 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */
857 /**
858 * @}
859 */
860 /**
861 * @}
862 */
863 /* End of exported functions -------------------------------------------------*/
864
865 /* Private macros ------------------------------------------------------------*/
866 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros
867 * @{
868 */
869 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
870 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
871 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
872 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
873 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
874 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
875 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
876 ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
877 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
878 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
879 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
880 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
881 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
882 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
883 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
884 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
885 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
886 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
887 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
888 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
889 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
890 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
891 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
892 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
893 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
894 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
895 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
896 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
897 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
898 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
899 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
900 #if defined (STM32F413xx) || defined (STM32F423xx)
901 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
902 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
903 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
904 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
905 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \
906 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
907 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \
908 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
909 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
910 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
911 #define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \
912 ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1))
913 #else
914 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
915 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
916 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
917 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
918 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
919 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
920 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
921 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
922 #endif
923 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
924 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
925 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
926 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
927 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
928 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
929 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
930 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
931 ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
932 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
933 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
934 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
935 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
936 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
937 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU)
938 #if defined(DFSDM2_Channel0)
939 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
940 ((CHANNEL) == DFSDM_CHANNEL_1) || \
941 ((CHANNEL) == DFSDM_CHANNEL_2) || \
942 ((CHANNEL) == DFSDM_CHANNEL_3) || \
943 ((CHANNEL) == DFSDM_CHANNEL_4) || \
944 ((CHANNEL) == DFSDM_CHANNEL_5) || \
945 ((CHANNEL) == DFSDM_CHANNEL_6) || \
946 ((CHANNEL) == DFSDM_CHANNEL_7))
947 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
948 #else
949 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
950 ((CHANNEL) == DFSDM_CHANNEL_1) || \
951 ((CHANNEL) == DFSDM_CHANNEL_2) || \
952 ((CHANNEL) == DFSDM_CHANNEL_3))
953 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
954 #endif
955 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
956 ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
957 #if defined(DFSDM2_Channel0)
958 #define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
959 ((INSTANCE) == DFSDM1_Channel1) || \
960 ((INSTANCE) == DFSDM1_Channel2) || \
961 ((INSTANCE) == DFSDM1_Channel3))
962 #define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
963 ((INSTANCE) == DFSDM1_Filter1))
964 #endif /* DFSDM2_Channel0 */
965
966 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
967 #define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \
968 ((SELECTION) == HAL_DFSDM2_CKIN_DM) || \
969 ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \
970 ((SELECTION) == HAL_DFSDM1_CKIN_DM))
971 #define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \
972 ((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \
973 ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \
974 ((SELECTION) == HAL_DFSDM1_CKOUT_M27))
975 #define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \
976 ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \
977 ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \
978 ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1))
979 #define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD) || \
980 ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \
981 ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD) || \
982 ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3))
983 #define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD) || \
984 ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5))
985 #define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD) || \
986 ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7))
987 #define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \
988 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \
989 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \
990 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \
991 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \
992 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \
993 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \
994 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \
995 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \
996 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \
997 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \
998 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1))
999 #define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \
1000 ((CLKOUT) == DFSDM1_CKOUT_DFSDM1))
1001 #define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \
1002 ((CLKOUT) == DFSDM2_CKOUT_DFSDM2))
1003 #define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \
1004 ((CLKIN) == DFSDM1_CKIN_PAD))
1005 #define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \
1006 ((CLKIN) == DFSDM2_CKIN_PAD))
1007 #define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \
1008 ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \
1009 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \
1010 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \
1011 ((CLK) <= 0x30U))
1012
1013 #define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \
1014 ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \
1015 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5) || \
1016 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1) || \
1017 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6) || \
1018 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \
1019 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \
1020 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \
1021 ((CLK) <= 0x1E000U))
1022
1023 #define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \
1024 ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \
1025 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \
1026 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \
1027 ((DISTRIBUTION) <= 0xCU))
1028
1029 #define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \
1030 ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \
1031 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \
1032 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \
1033 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \
1034 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \
1035 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \
1036 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \
1037 ((DISTRIBUTION) <= 0x1D00U))
1038 #endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */
1039 /**
1040 * @}
1041 */
1042 /* End of private macros -----------------------------------------------------*/
1043
1044 /**
1045 * @}
1046 */
1047
1048 /**
1049 * @}
1050 */
1051 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
1052 #ifdef __cplusplus
1053 }
1054 #endif
1055
1056 #endif /* __STM32F4xx_HAL_DFSDM_H */
1057
1058 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/