Mercurial > public > ostc4

comparison Common/Drivers/STM32F4xx/Source/Templates/arm/startup_stm32f427xx.s @ 128:c78bcbd5deda FlipDisplay

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
parents
children
comparison
equal deleted inserted replaced
127:1369f8660eaa 128:c78bcbd5deda
1 ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
2 ;* File Name : startup_stm32f427xx.s
3 ;* Author : MCD Application Team
4 ;* Description : STM32F427x devices vector table for MDK-ARM toolchain.
5 ;* This module performs:
6 ;* - Set the initial SP
7 ;* - Set the initial PC == Reset_Handler
8 ;* - Set the vector table entries with the exceptions ISR address
9 ;* After Reset the CortexM4 processor is in Thread mode,
10 ;* priority is Privileged, and the Stack is set to Main.
11 ;* <<< Use Configuration Wizard in Context Menu >>>
12 ;*******************************************************************************
13 ;
14 ;* Redistribution and use in source and binary forms, with or without modification,
15 ;* are permitted provided that the following conditions are met:
16 ;* 1. Redistributions of source code must retain the above copyright notice,
17 ;* this list of conditions and the following disclaimer.
18 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
19 ;* this list of conditions and the following disclaimer in the documentation
20 ;* and/or other materials provided with the distribution.
21 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
22 ;* may be used to endorse or promote products derived from this software
23 ;* without specific prior written permission.
24 ;*
25 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ;
36 ;*******************************************************************************
37
38 ; Amount of memory (in bytes) allocated for Stack
39 ; Tailor this value to your application needs
40 ; <h> Stack Configuration
41 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
42 ; </h>
43
44 Stack_Size EQU 0x00000400
45
46 AREA STACK, NOINIT, READWRITE, ALIGN=3
47 Stack_Mem SPACE Stack_Size
48 __initial_sp
49
50
51 ; <h> Heap Configuration
52 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
53 ; </h>
54
55 Heap_Size EQU 0x00000200
56
57 AREA HEAP, NOINIT, READWRITE, ALIGN=3
58 __heap_base
59 Heap_Mem SPACE Heap_Size
60 __heap_limit
61
62 PRESERVE8
63 THUMB
64
65
66 ; Vector Table Mapped to Address 0 at Reset
67 AREA RESET, DATA, READONLY
68 EXPORT __Vectors
69 EXPORT __Vectors_End
70 EXPORT __Vectors_Size
71
72 __Vectors DCD __initial_sp ; Top of Stack
73 DCD Reset_Handler ; Reset Handler
74 DCD NMI_Handler ; NMI Handler
75 DCD HardFault_Handler ; Hard Fault Handler
76 DCD MemManage_Handler ; MPU Fault Handler
77 DCD BusFault_Handler ; Bus Fault Handler
78 DCD UsageFault_Handler ; Usage Fault Handler
79 DCD 0 ; Reserved
80 DCD 0 ; Reserved
81 DCD 0 ; Reserved
82 DCD 0 ; Reserved
83 DCD SVC_Handler ; SVCall Handler
84 DCD DebugMon_Handler ; Debug Monitor Handler
85 DCD 0 ; Reserved
86 DCD PendSV_Handler ; PendSV Handler
87 DCD SysTick_Handler ; SysTick Handler
88
89 ; External Interrupts
90 DCD WWDG_IRQHandler ; Window WatchDog
91 DCD PVD_IRQHandler ; PVD through EXTI Line detection
92 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
93 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
94 DCD FLASH_IRQHandler ; FLASH
95 DCD RCC_IRQHandler ; RCC
96 DCD EXTI0_IRQHandler ; EXTI Line0
97 DCD EXTI1_IRQHandler ; EXTI Line1
98 DCD EXTI2_IRQHandler ; EXTI Line2
99 DCD EXTI3_IRQHandler ; EXTI Line3
100 DCD EXTI4_IRQHandler ; EXTI Line4
101 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
102 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
103 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
104 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
105 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
106 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
107 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
108 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
109 DCD CAN1_TX_IRQHandler ; CAN1 TX
110 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
111 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
112 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
113 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
114 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
115 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
116 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
117 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
118 DCD TIM2_IRQHandler ; TIM2
119 DCD TIM3_IRQHandler ; TIM3
120 DCD TIM4_IRQHandler ; TIM4
121 DCD I2C1_EV_IRQHandler ; I2C1 Event
122 DCD I2C1_ER_IRQHandler ; I2C1 Error
123 DCD I2C2_EV_IRQHandler ; I2C2 Event
124 DCD I2C2_ER_IRQHandler ; I2C2 Error
125 DCD SPI1_IRQHandler ; SPI1
126 DCD SPI2_IRQHandler ; SPI2
127 DCD USART1_IRQHandler ; USART1
128 DCD USART2_IRQHandler ; USART2
129 DCD USART3_IRQHandler ; USART3
130 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
131 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
132 DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
133 DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
134 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
135 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
136 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
137 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
138 DCD FMC_IRQHandler ; FMC
139 DCD SDIO_IRQHandler ; SDIO
140 DCD TIM5_IRQHandler ; TIM5
141 DCD SPI3_IRQHandler ; SPI3
142 DCD UART4_IRQHandler ; UART4
143 DCD UART5_IRQHandler ; UART5
144 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
145 DCD TIM7_IRQHandler ; TIM7
146 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
147 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
148 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
149 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
150 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
151 DCD ETH_IRQHandler ; Ethernet
152 DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
153 DCD CAN2_TX_IRQHandler ; CAN2 TX
154 DCD CAN2_RX0_IRQHandler ; CAN2 RX0
155 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
156 DCD CAN2_SCE_IRQHandler ; CAN2 SCE
157 DCD OTG_FS_IRQHandler ; USB OTG FS
158 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
159 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
160 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
161 DCD USART6_IRQHandler ; USART6
162 DCD I2C3_EV_IRQHandler ; I2C3 event
163 DCD I2C3_ER_IRQHandler ; I2C3 error
164 DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
165 DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
166 DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
167 DCD OTG_HS_IRQHandler ; USB OTG HS
168 DCD DCMI_IRQHandler ; DCMI
169 DCD 0 ; Reserved
170 DCD HASH_RNG_IRQHandler ; Hash and Rng
171 DCD FPU_IRQHandler ; FPU
172 DCD UART7_IRQHandler ; UART7
173 DCD UART8_IRQHandler ; UART8
174 DCD SPI4_IRQHandler ; SPI4
175 DCD SPI5_IRQHandler ; SPI5
176 DCD SPI6_IRQHandler ; SPI6
177 DCD SAI1_IRQHandler ; SAI1
178 DCD 0 ; Reserved
179 DCD 0 ; Reserved
180 DCD DMA2D_IRQHandler ; DMA2D
181
182 __Vectors_End
183
184 __Vectors_Size EQU __Vectors_End - __Vectors
185
186 AREA |.text|, CODE, READONLY
187
188 ; Reset handler
189 Reset_Handler PROC
190 EXPORT Reset_Handler [WEAK]
191 IMPORT SystemInit
192 IMPORT __main
193
194 LDR R0, =SystemInit
195 BLX R0
196 LDR R0, =__main
197 BX R0
198 ENDP
199
200 ; Dummy Exception Handlers (infinite loops which can be modified)
201
202 NMI_Handler PROC
203 EXPORT NMI_Handler [WEAK]
204 B .
205 ENDP
206 HardFault_Handler\
207 PROC
208 EXPORT HardFault_Handler [WEAK]
209 B .
210 ENDP
211 MemManage_Handler\
212 PROC
213 EXPORT MemManage_Handler [WEAK]
214 B .
215 ENDP
216 BusFault_Handler\
217 PROC
218 EXPORT BusFault_Handler [WEAK]
219 B .
220 ENDP
221 UsageFault_Handler\
222 PROC
223 EXPORT UsageFault_Handler [WEAK]
224 B .
225 ENDP
226 SVC_Handler PROC
227 EXPORT SVC_Handler [WEAK]
228 B .
229 ENDP
230 DebugMon_Handler\
231 PROC
232 EXPORT DebugMon_Handler [WEAK]
233 B .
234 ENDP
235 PendSV_Handler PROC
236 EXPORT PendSV_Handler [WEAK]
237 B .
238 ENDP
239 SysTick_Handler PROC
240 EXPORT SysTick_Handler [WEAK]
241 B .
242 ENDP
243
244 Default_Handler PROC
245
246 EXPORT WWDG_IRQHandler [WEAK]
247 EXPORT PVD_IRQHandler [WEAK]
248 EXPORT TAMP_STAMP_IRQHandler [WEAK]
249 EXPORT RTC_WKUP_IRQHandler [WEAK]
250 EXPORT FLASH_IRQHandler [WEAK]
251 EXPORT RCC_IRQHandler [WEAK]
252 EXPORT EXTI0_IRQHandler [WEAK]
253 EXPORT EXTI1_IRQHandler [WEAK]
254 EXPORT EXTI2_IRQHandler [WEAK]
255 EXPORT EXTI3_IRQHandler [WEAK]
256 EXPORT EXTI4_IRQHandler [WEAK]
257 EXPORT DMA1_Stream0_IRQHandler [WEAK]
258 EXPORT DMA1_Stream1_IRQHandler [WEAK]
259 EXPORT DMA1_Stream2_IRQHandler [WEAK]
260 EXPORT DMA1_Stream3_IRQHandler [WEAK]
261 EXPORT DMA1_Stream4_IRQHandler [WEAK]
262 EXPORT DMA1_Stream5_IRQHandler [WEAK]
263 EXPORT DMA1_Stream6_IRQHandler [WEAK]
264 EXPORT ADC_IRQHandler [WEAK]
265 EXPORT CAN1_TX_IRQHandler [WEAK]
266 EXPORT CAN1_RX0_IRQHandler [WEAK]
267 EXPORT CAN1_RX1_IRQHandler [WEAK]
268 EXPORT CAN1_SCE_IRQHandler [WEAK]
269 EXPORT EXTI9_5_IRQHandler [WEAK]
270 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
271 EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
272 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
273 EXPORT TIM1_CC_IRQHandler [WEAK]
274 EXPORT TIM2_IRQHandler [WEAK]
275 EXPORT TIM3_IRQHandler [WEAK]
276 EXPORT TIM4_IRQHandler [WEAK]
277 EXPORT I2C1_EV_IRQHandler [WEAK]
278 EXPORT I2C1_ER_IRQHandler [WEAK]
279 EXPORT I2C2_EV_IRQHandler [WEAK]
280 EXPORT I2C2_ER_IRQHandler [WEAK]
281 EXPORT SPI1_IRQHandler [WEAK]
282 EXPORT SPI2_IRQHandler [WEAK]
283 EXPORT USART1_IRQHandler [WEAK]
284 EXPORT USART2_IRQHandler [WEAK]
285 EXPORT USART3_IRQHandler [WEAK]
286 EXPORT EXTI15_10_IRQHandler [WEAK]
287 EXPORT RTC_Alarm_IRQHandler [WEAK]
288 EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
289 EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
290 EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
291 EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
292 EXPORT TIM8_CC_IRQHandler [WEAK]
293 EXPORT DMA1_Stream7_IRQHandler [WEAK]
294 EXPORT FMC_IRQHandler [WEAK]
295 EXPORT SDIO_IRQHandler [WEAK]
296 EXPORT TIM5_IRQHandler [WEAK]
297 EXPORT SPI3_IRQHandler [WEAK]
298 EXPORT UART4_IRQHandler [WEAK]
299 EXPORT UART5_IRQHandler [WEAK]
300 EXPORT TIM6_DAC_IRQHandler [WEAK]
301 EXPORT TIM7_IRQHandler [WEAK]
302 EXPORT DMA2_Stream0_IRQHandler [WEAK]
303 EXPORT DMA2_Stream1_IRQHandler [WEAK]
304 EXPORT DMA2_Stream2_IRQHandler [WEAK]
305 EXPORT DMA2_Stream3_IRQHandler [WEAK]
306 EXPORT DMA2_Stream4_IRQHandler [WEAK]
307 EXPORT ETH_IRQHandler [WEAK]
308 EXPORT ETH_WKUP_IRQHandler [WEAK]
309 EXPORT CAN2_TX_IRQHandler [WEAK]
310 EXPORT CAN2_RX0_IRQHandler [WEAK]
311 EXPORT CAN2_RX1_IRQHandler [WEAK]
312 EXPORT CAN2_SCE_IRQHandler [WEAK]
313 EXPORT OTG_FS_IRQHandler [WEAK]
314 EXPORT DMA2_Stream5_IRQHandler [WEAK]
315 EXPORT DMA2_Stream6_IRQHandler [WEAK]
316 EXPORT DMA2_Stream7_IRQHandler [WEAK]
317 EXPORT USART6_IRQHandler [WEAK]
318 EXPORT I2C3_EV_IRQHandler [WEAK]
319 EXPORT I2C3_ER_IRQHandler [WEAK]
320 EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
321 EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
322 EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
323 EXPORT OTG_HS_IRQHandler [WEAK]
324 EXPORT DCMI_IRQHandler [WEAK]
325 EXPORT HASH_RNG_IRQHandler [WEAK]
326 EXPORT FPU_IRQHandler [WEAK]
327 EXPORT UART7_IRQHandler [WEAK]
328 EXPORT UART8_IRQHandler [WEAK]
329 EXPORT SPI4_IRQHandler [WEAK]
330 EXPORT SPI5_IRQHandler [WEAK]
331 EXPORT SPI6_IRQHandler [WEAK]
332 EXPORT SAI1_IRQHandler [WEAK]
333 EXPORT DMA2D_IRQHandler [WEAK]
334
335 WWDG_IRQHandler
336 PVD_IRQHandler
337 TAMP_STAMP_IRQHandler
338 RTC_WKUP_IRQHandler
339 FLASH_IRQHandler
340 RCC_IRQHandler
341 EXTI0_IRQHandler
342 EXTI1_IRQHandler
343 EXTI2_IRQHandler
344 EXTI3_IRQHandler
345 EXTI4_IRQHandler
346 DMA1_Stream0_IRQHandler
347 DMA1_Stream1_IRQHandler
348 DMA1_Stream2_IRQHandler
349 DMA1_Stream3_IRQHandler
350 DMA1_Stream4_IRQHandler
351 DMA1_Stream5_IRQHandler
352 DMA1_Stream6_IRQHandler
353 ADC_IRQHandler
354 CAN1_TX_IRQHandler
355 CAN1_RX0_IRQHandler
356 CAN1_RX1_IRQHandler
357 CAN1_SCE_IRQHandler
358 EXTI9_5_IRQHandler
359 TIM1_BRK_TIM9_IRQHandler
360 TIM1_UP_TIM10_IRQHandler
361 TIM1_TRG_COM_TIM11_IRQHandler
362 TIM1_CC_IRQHandler
363 TIM2_IRQHandler
364 TIM3_IRQHandler
365 TIM4_IRQHandler
366 I2C1_EV_IRQHandler
367 I2C1_ER_IRQHandler
368 I2C2_EV_IRQHandler
369 I2C2_ER_IRQHandler
370 SPI1_IRQHandler
371 SPI2_IRQHandler
372 USART1_IRQHandler
373 USART2_IRQHandler
374 USART3_IRQHandler
375 EXTI15_10_IRQHandler
376 RTC_Alarm_IRQHandler
377 OTG_FS_WKUP_IRQHandler
378 TIM8_BRK_TIM12_IRQHandler
379 TIM8_UP_TIM13_IRQHandler
380 TIM8_TRG_COM_TIM14_IRQHandler
381 TIM8_CC_IRQHandler
382 DMA1_Stream7_IRQHandler
383 FMC_IRQHandler
384 SDIO_IRQHandler
385 TIM5_IRQHandler
386 SPI3_IRQHandler
387 UART4_IRQHandler
388 UART5_IRQHandler
389 TIM6_DAC_IRQHandler
390 TIM7_IRQHandler
391 DMA2_Stream0_IRQHandler
392 DMA2_Stream1_IRQHandler
393 DMA2_Stream2_IRQHandler
394 DMA2_Stream3_IRQHandler
395 DMA2_Stream4_IRQHandler
396 ETH_IRQHandler
397 ETH_WKUP_IRQHandler
398 CAN2_TX_IRQHandler
399 CAN2_RX0_IRQHandler
400 CAN2_RX1_IRQHandler
401 CAN2_SCE_IRQHandler
402 OTG_FS_IRQHandler
403 DMA2_Stream5_IRQHandler
404 DMA2_Stream6_IRQHandler
405 DMA2_Stream7_IRQHandler
406 USART6_IRQHandler
407 I2C3_EV_IRQHandler
408 I2C3_ER_IRQHandler
409 OTG_HS_EP1_OUT_IRQHandler
410 OTG_HS_EP1_IN_IRQHandler
411 OTG_HS_WKUP_IRQHandler
412 OTG_HS_IRQHandler
413 DCMI_IRQHandler
414 HASH_RNG_IRQHandler
415 FPU_IRQHandler
416 UART7_IRQHandler
417 UART8_IRQHandler
418 SPI4_IRQHandler
419 SPI5_IRQHandler
420 SPI6_IRQHandler
421 SAI1_IRQHandler
422 DMA2D_IRQHandler
423 B .
424
425 ENDP
426
427 ALIGN
428
429 ;*******************************************************************************
430 ; User Stack and Heap initialization
431 ;*******************************************************************************
432 IF :DEF:__MICROLIB
433
434 EXPORT __initial_sp
435 EXPORT __heap_base
436 EXPORT __heap_limit
437
438 ELSE
439
440 IMPORT __use_two_region_memory
441 EXPORT __user_initial_stackheap
442
443 __user_initial_stackheap
444
445 LDR R0, = Heap_Mem
446 LDR R1, =(Stack_Mem + Stack_Size)
447 LDR R2, = (Heap_Mem + Heap_Size)
448 LDR R3, = Stack_Mem
449 BX LR
450
451 ALIGN
452
453 ENDIF
454
455 END
456
457 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****