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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f479xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F479xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - peripherals registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f479xx
47 * @{
48 */
49
50 #ifndef __STM32F479xx_H
51 #define __STM32F479xx_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #define __FPU_PRESENT 1U /*!< FPU present */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78 /**
79 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
87 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
88 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
89 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
91 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
92 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
93 /****** STM32 specific Interrupt Numbers **********************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
99 RCC_IRQn = 5, /*!< RCC global Interrupt */
100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
112 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
113 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
114 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
115 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
116 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
133 USART3_IRQn = 39, /*!< USART3 global Interrupt */
134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
137 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
138 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
139 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
140 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
141 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
142 FMC_IRQn = 48, /*!< FMC global Interrupt */
143 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
144 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
149 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
150 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
151 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
152 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
153 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
154 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
155 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
156 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
157 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
158 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
159 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
160 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
162 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
163 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
164 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
165 USART6_IRQn = 71, /*!< USART6 global interrupt */
166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
168 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
169 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
170 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
171 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
172 DCMI_IRQn = 78, /*!< DCMI global interrupt */
173 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
174 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
175 FPU_IRQn = 81, /*!< FPU global interrupt */
176 UART7_IRQn = 82, /*!< UART7 global interrupt */
177 UART8_IRQn = 83, /*!< UART8 global interrupt */
178 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
179 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
180 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
181 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
182 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
183 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
184 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
185 QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
186 DSI_IRQn = 92 /*!< DSI global Interrupt */
187 } IRQn_Type;
188
189 /**
190 * @}
191 */
192
193 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
194 #include "system_stm32f4xx.h"
195 #include <stdint.h>
196
197 /** @addtogroup Peripheral_registers_structures
198 * @{
199 */
200
201 /**
202 * @brief Analog to Digital Converter
203 */
204
205 typedef struct
206 {
207 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
208 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
209 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
210 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
211 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
212 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
213 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
214 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
215 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
216 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
217 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
218 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
219 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
220 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
221 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
222 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
223 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
224 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
225 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
226 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
227 } ADC_TypeDef;
228
229 typedef struct
230 {
231 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
232 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
233 __IO uint32_t CDR; /*!< ADC common regular data register for dual
234 AND triple modes, Address offset: ADC1 base address + 0x308 */
235 } ADC_Common_TypeDef;
236
237
238 /**
239 * @brief Controller Area Network TxMailBox
240 */
241
242 typedef struct
243 {
244 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
245 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
246 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
247 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
248 } CAN_TxMailBox_TypeDef;
249
250 /**
251 * @brief Controller Area Network FIFOMailBox
252 */
253
254 typedef struct
255 {
256 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
257 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
258 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
259 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
260 } CAN_FIFOMailBox_TypeDef;
261
262 /**
263 * @brief Controller Area Network FilterRegister
264 */
265
266 typedef struct
267 {
268 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
269 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
270 } CAN_FilterRegister_TypeDef;
271
272 /**
273 * @brief Controller Area Network
274 */
275
276 typedef struct
277 {
278 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
279 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
280 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
281 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
282 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
283 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
284 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
285 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
286 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
287 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
288 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
289 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
290 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
291 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
292 uint32_t RESERVED2; /*!< Reserved, 0x208 */
293 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
294 uint32_t RESERVED3; /*!< Reserved, 0x210 */
295 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
296 uint32_t RESERVED4; /*!< Reserved, 0x218 */
297 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
298 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
299 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
300 } CAN_TypeDef;
301
302 /**
303 * @brief CRC calculation unit
304 */
305
306 typedef struct
307 {
308 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
309 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
310 uint8_t RESERVED0; /*!< Reserved, 0x05 */
311 uint16_t RESERVED1; /*!< Reserved, 0x06 */
312 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
313 } CRC_TypeDef;
314
315 /**
316 * @brief Digital to Analog Converter
317 */
318
319 typedef struct
320 {
321 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
322 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
323 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
324 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
325 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
326 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
327 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
328 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
329 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
330 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
331 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
332 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
333 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
334 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
335 } DAC_TypeDef;
336
337 /**
338 * @brief Debug MCU
339 */
340
341 typedef struct
342 {
343 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
344 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
345 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
346 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
347 }DBGMCU_TypeDef;
348
349 /**
350 * @brief DCMI
351 */
352
353 typedef struct
354 {
355 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
356 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
357 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
358 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
359 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
360 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
361 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
362 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
363 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
364 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
365 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
366 } DCMI_TypeDef;
367
368 /**
369 * @brief DMA Controller
370 */
371
372 typedef struct
373 {
374 __IO uint32_t CR; /*!< DMA stream x configuration register */
375 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
376 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
377 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
378 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
379 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
380 } DMA_Stream_TypeDef;
381
382 typedef struct
383 {
384 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
385 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
386 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
387 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
388 } DMA_TypeDef;
389
390 /**
391 * @brief DMA2D Controller
392 */
393
394 typedef struct
395 {
396 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
397 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
398 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
399 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
400 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
401 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
402 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
403 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
404 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
405 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
406 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
407 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
408 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
409 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
410 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
411 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
412 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
413 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
414 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
415 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
416 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
417 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
418 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
419 } DMA2D_TypeDef;
420
421 /**
422 * @brief DSI Controller
423 */
424
425 typedef struct
426 {
427 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
428 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
429 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
430 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
431 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
432 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
433 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
434 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
435 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
436 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
437 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
438 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
439 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
440 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
441 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
442 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
443 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
444 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
445 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
446 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
447 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
448 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
449 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
450 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
451 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
452 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
453 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
454 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
455 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
456 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
457 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
458 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
459 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
460 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
461 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
462 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
463 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
464 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
465 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
466 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
467 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
468 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
469 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
470 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
471 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
472 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
473 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
474 uint32_t RESERVED5; /*!< Reserved, 0x114 */
475 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
476 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
477 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
478 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
479 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
480 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
481 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
482 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
483 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
484 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
485 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
486 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
487 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
488 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
489 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
490 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
491 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
492 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
493 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
494 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
495 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
496 uint32_t RESERVED9; /*!< Reserved, 0x414 */
497 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
498 uint32_t RESERVED10; /*!< Reserved, 0x42C */
499 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
500 } DSI_TypeDef;
501
502 /**
503 * @brief Ethernet MAC
504 */
505
506 typedef struct
507 {
508 __IO uint32_t MACCR;
509 __IO uint32_t MACFFR;
510 __IO uint32_t MACHTHR;
511 __IO uint32_t MACHTLR;
512 __IO uint32_t MACMIIAR;
513 __IO uint32_t MACMIIDR;
514 __IO uint32_t MACFCR;
515 __IO uint32_t MACVLANTR; /* 8 */
516 uint32_t RESERVED0[2];
517 __IO uint32_t MACRWUFFR; /* 11 */
518 __IO uint32_t MACPMTCSR;
519 uint32_t RESERVED1;
520 __IO uint32_t MACDBGR;
521 __IO uint32_t MACSR; /* 15 */
522 __IO uint32_t MACIMR;
523 __IO uint32_t MACA0HR;
524 __IO uint32_t MACA0LR;
525 __IO uint32_t MACA1HR;
526 __IO uint32_t MACA1LR;
527 __IO uint32_t MACA2HR;
528 __IO uint32_t MACA2LR;
529 __IO uint32_t MACA3HR;
530 __IO uint32_t MACA3LR; /* 24 */
531 uint32_t RESERVED2[40];
532 __IO uint32_t MMCCR; /* 65 */
533 __IO uint32_t MMCRIR;
534 __IO uint32_t MMCTIR;
535 __IO uint32_t MMCRIMR;
536 __IO uint32_t MMCTIMR; /* 69 */
537 uint32_t RESERVED3[14];
538 __IO uint32_t MMCTGFSCCR; /* 84 */
539 __IO uint32_t MMCTGFMSCCR;
540 uint32_t RESERVED4[5];
541 __IO uint32_t MMCTGFCR;
542 uint32_t RESERVED5[10];
543 __IO uint32_t MMCRFCECR;
544 __IO uint32_t MMCRFAECR;
545 uint32_t RESERVED6[10];
546 __IO uint32_t MMCRGUFCR;
547 uint32_t RESERVED7[334];
548 __IO uint32_t PTPTSCR;
549 __IO uint32_t PTPSSIR;
550 __IO uint32_t PTPTSHR;
551 __IO uint32_t PTPTSLR;
552 __IO uint32_t PTPTSHUR;
553 __IO uint32_t PTPTSLUR;
554 __IO uint32_t PTPTSAR;
555 __IO uint32_t PTPTTHR;
556 __IO uint32_t PTPTTLR;
557 __IO uint32_t RESERVED8;
558 __IO uint32_t PTPTSSR;
559 uint32_t RESERVED9[565];
560 __IO uint32_t DMABMR;
561 __IO uint32_t DMATPDR;
562 __IO uint32_t DMARPDR;
563 __IO uint32_t DMARDLAR;
564 __IO uint32_t DMATDLAR;
565 __IO uint32_t DMASR;
566 __IO uint32_t DMAOMR;
567 __IO uint32_t DMAIER;
568 __IO uint32_t DMAMFBOCR;
569 __IO uint32_t DMARSWTR;
570 uint32_t RESERVED10[8];
571 __IO uint32_t DMACHTDR;
572 __IO uint32_t DMACHRDR;
573 __IO uint32_t DMACHTBAR;
574 __IO uint32_t DMACHRBAR;
575 } ETH_TypeDef;
576
577 /**
578 * @brief External Interrupt/Event Controller
579 */
580
581 typedef struct
582 {
583 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
584 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
585 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
586 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
587 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
588 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
589 } EXTI_TypeDef;
590
591 /**
592 * @brief FLASH Registers
593 */
594
595 typedef struct
596 {
597 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
598 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
599 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
600 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
601 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
602 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
603 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
604 } FLASH_TypeDef;
605
606 /**
607 * @brief Flexible Memory Controller
608 */
609
610 typedef struct
611 {
612 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
613 } FMC_Bank1_TypeDef;
614
615 /**
616 * @brief Flexible Memory Controller Bank1E
617 */
618
619 typedef struct
620 {
621 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
622 } FMC_Bank1E_TypeDef;
623
624 /**
625 * @brief Flexible Memory Controller Bank3
626 */
627
628 typedef struct
629 {
630 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
631 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
632 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
633 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
634 uint32_t RESERVED; /*!< Reserved, 0x90 */
635 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
636 } FMC_Bank3_TypeDef;
637
638 /**
639 * @brief Flexible Memory Controller Bank5_6
640 */
641
642 typedef struct
643 {
644 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
645 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
646 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
647 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
648 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
649 } FMC_Bank5_6_TypeDef;
650
651 /**
652 * @brief General Purpose I/O
653 */
654
655 typedef struct
656 {
657 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
658 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
659 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
660 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
661 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
662 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
663 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
664 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
665 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
666 } GPIO_TypeDef;
667
668 /**
669 * @brief System configuration controller
670 */
671
672 typedef struct
673 {
674 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
675 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
676 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
677 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
678 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
679 } SYSCFG_TypeDef;
680
681 /**
682 * @brief Inter-integrated Circuit Interface
683 */
684
685 typedef struct
686 {
687 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
688 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
689 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
690 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
691 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
692 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
693 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
694 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
695 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
696 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
697 } I2C_TypeDef;
698
699 /**
700 * @brief Independent WATCHDOG
701 */
702
703 typedef struct
704 {
705 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
706 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
707 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
708 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
709 } IWDG_TypeDef;
710
711 /**
712 * @brief LCD-TFT Display Controller
713 */
714
715 typedef struct
716 {
717 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
718 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
719 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
720 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
721 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
722 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
723 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
724 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
725 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
726 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
727 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
728 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
729 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
730 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
731 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
732 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
733 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
734 } LTDC_TypeDef;
735
736 /**
737 * @brief LCD-TFT Display layer x Controller
738 */
739
740 typedef struct
741 {
742 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
743 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
744 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
745 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
746 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
747 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
748 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
749 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
750 uint32_t RESERVED0[2]; /*!< Reserved */
751 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
752 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
753 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
754 uint32_t RESERVED1[3]; /*!< Reserved */
755 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
756 } LTDC_Layer_TypeDef;
757
758 /**
759 * @brief Power Control
760 */
761
762 typedef struct
763 {
764 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
765 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
766 } PWR_TypeDef;
767
768 /**
769 * @brief Reset and Clock Control
770 */
771
772 typedef struct
773 {
774 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
775 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
776 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
777 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
778 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
779 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
780 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
781 uint32_t RESERVED0; /*!< Reserved, 0x1C */
782 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
783 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
784 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
785 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
786 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
787 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
788 uint32_t RESERVED2; /*!< Reserved, 0x3C */
789 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
790 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
791 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
792 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
793 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
794 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
795 uint32_t RESERVED4; /*!< Reserved, 0x5C */
796 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
797 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
798 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
799 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
800 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
801 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
802 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
803 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
804 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
805 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
806 } RCC_TypeDef;
807
808 /**
809 * @brief Real-Time Clock
810 */
811
812 typedef struct
813 {
814 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
815 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
816 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
817 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
818 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
819 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
820 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
821 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
822 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
823 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
824 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
825 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
826 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
827 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
828 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
829 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
830 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
831 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
832 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
833 uint32_t RESERVED7; /*!< Reserved, 0x4C */
834 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
835 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
836 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
837 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
838 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
839 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
840 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
841 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
842 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
843 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
844 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
845 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
846 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
847 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
848 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
849 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
850 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
851 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
852 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
853 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
854 } RTC_TypeDef;
855
856 /**
857 * @brief Serial Audio Interface
858 */
859
860 typedef struct
861 {
862 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
863 } SAI_TypeDef;
864
865 typedef struct
866 {
867 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
868 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
869 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
870 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
871 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
872 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
873 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
874 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
875 } SAI_Block_TypeDef;
876
877 /**
878 * @brief SD host Interface
879 */
880
881 typedef struct
882 {
883 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
884 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
885 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
886 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
887 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
888 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
889 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
890 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
891 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
892 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
893 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
894 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
895 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
896 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
897 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
898 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
899 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
900 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
901 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
902 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
903 } SDIO_TypeDef;
904
905 /**
906 * @brief Serial Peripheral Interface
907 */
908
909 typedef struct
910 {
911 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
912 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
913 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
914 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
915 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
916 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
917 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
918 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
919 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
920 } SPI_TypeDef;
921
922 /**
923 * @brief QUAD Serial Peripheral Interface
924 */
925
926 typedef struct
927 {
928 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
929 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
930 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
931 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
932 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
933 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
934 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
935 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
936 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
937 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
938 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
939 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
940 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
941 } QUADSPI_TypeDef;
942
943 /**
944 * @brief TIM
945 */
946
947 typedef struct
948 {
949 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
950 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
951 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
952 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
953 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
954 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
955 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
956 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
957 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
958 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
959 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
960 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
961 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
962 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
963 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
964 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
965 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
966 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
967 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
968 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
969 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
970 } TIM_TypeDef;
971
972 /**
973 * @brief Universal Synchronous Asynchronous Receiver Transmitter
974 */
975
976 typedef struct
977 {
978 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
979 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
980 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
981 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
982 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
983 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
984 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
985 } USART_TypeDef;
986
987 /**
988 * @brief Window WATCHDOG
989 */
990
991 typedef struct
992 {
993 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
994 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
995 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
996 } WWDG_TypeDef;
997
998 /**
999 * @brief Crypto Processor
1000 */
1001
1002 typedef struct
1003 {
1004 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
1005 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
1006 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
1007 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
1008 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
1009 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
1010 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
1011 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
1012 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
1013 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
1014 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
1015 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
1016 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
1017 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
1018 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
1019 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
1020 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
1021 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
1022 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
1023 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
1024 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
1025 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
1026 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
1027 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
1028 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
1029 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
1030 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
1031 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
1032 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
1033 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
1034 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
1035 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
1036 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
1037 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
1038 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
1039 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
1040 } CRYP_TypeDef;
1041
1042 /**
1043 * @brief HASH
1044 */
1045
1046 typedef struct
1047 {
1048 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
1049 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
1050 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
1051 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1052 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
1053 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
1054 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1055 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1056 } HASH_TypeDef;
1057
1058 /**
1059 * @brief HASH_DIGEST
1060 */
1061
1062 typedef struct
1063 {
1064 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1065 } HASH_DIGEST_TypeDef;
1066
1067 /**
1068 * @brief RNG
1069 */
1070
1071 typedef struct
1072 {
1073 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1074 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1075 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1076 } RNG_TypeDef;
1077
1078 /**
1079 * @brief USB_OTG_Core_Registers
1080 */
1081 typedef struct
1082 {
1083 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1084 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1085 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1086 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1087 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1088 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1089 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1090 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1091 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1092 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1093 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1094 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1095 uint32_t Reserved30[2]; /*!< Reserved 030h */
1096 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1097 __IO uint32_t CID; /*!< User ID Register 03Ch */
1098 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
1099 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1100 uint32_t Reserved6; /*!< Reserved 050h */
1101 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1102 uint32_t Reserved; /*!< Reserved 058h */
1103 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1104 uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
1105 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1106 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1107 } USB_OTG_GlobalTypeDef;
1108
1109 /**
1110 * @brief USB_OTG_device_Registers
1111 */
1112 typedef struct
1113 {
1114 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1115 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1116 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1117 uint32_t Reserved0C; /*!< Reserved 80Ch */
1118 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1119 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1120 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1121 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1122 uint32_t Reserved20; /*!< Reserved 820h */
1123 uint32_t Reserved9; /*!< Reserved 824h */
1124 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1125 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1126 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1127 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1128 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1129 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1130 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1131 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1132 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1133 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1134 } USB_OTG_DeviceTypeDef;
1135
1136 /**
1137 * @brief USB_OTG_IN_Endpoint-Specific_Register
1138 */
1139 typedef struct
1140 {
1141 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1142 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1143 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1144 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1145 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1146 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1147 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1148 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1149 } USB_OTG_INEndpointTypeDef;
1150
1151 /**
1152 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1153 */
1154 typedef struct
1155 {
1156 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1157 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1158 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1159 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1160 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1161 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1162 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1163 } USB_OTG_OUTEndpointTypeDef;
1164
1165 /**
1166 * @brief USB_OTG_Host_Mode_Register_Structures
1167 */
1168 typedef struct
1169 {
1170 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1171 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1172 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1173 uint32_t Reserved40C; /*!< Reserved 40Ch */
1174 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1175 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1176 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1177 } USB_OTG_HostTypeDef;
1178
1179 /**
1180 * @brief USB_OTG_Host_Channel_Specific_Registers
1181 */
1182 typedef struct
1183 {
1184 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1185 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1186 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1187 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1188 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1189 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1190 uint32_t Reserved[2]; /*!< Reserved */
1191 } USB_OTG_HostChannelTypeDef;
1192
1193 /**
1194 * @}
1195 */
1196
1197 /** @addtogroup Peripheral_memory_map
1198 * @{
1199 */
1200 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
1201 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
1202 #define SRAM1_BASE 0x20000000U /*!< SRAM1(160 KB) base address in the alias region */
1203 #define SRAM2_BASE 0x20028000U /*!< SRAM2(32 KB) base address in the alias region */
1204 #define SRAM3_BASE 0x20030000U /*!< SRAM3(128 KB) base address in the alias region */
1205 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
1206 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
1207 #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
1208 #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
1209 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
1210 #define SRAM2_BB_BASE 0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region */
1211 #define SRAM3_BB_BASE 0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region */
1212 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
1213 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
1214 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
1215 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
1216 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
1217 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
1218
1219 /* Legacy defines */
1220 #define SRAM_BASE SRAM1_BASE
1221 #define SRAM_BB_BASE SRAM1_BB_BASE
1222
1223 /*!< Peripheral memory map */
1224 #define APB1PERIPH_BASE PERIPH_BASE
1225 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1226 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1227 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1228
1229 /*!< APB1 peripherals */
1230 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1231 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1232 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1233 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1234 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1235 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1236 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1237 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1238 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1239 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1240 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1241 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1242 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1243 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1244 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1245 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1246 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1247 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1248 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1249 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1250 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1251 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1252 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1253 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1254 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1255 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1256 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1257 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1258 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1259
1260 /*!< APB2 peripherals */
1261 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1262 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1263 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1264 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1265 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1266 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1267 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1268 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
1269 /* Legacy define */
1270 #define ADC_BASE ADC123_COMMON_BASE
1271 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1272 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1273 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1274 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1275 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1276 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1277 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1278 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1279 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1280 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1281 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1282 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1283 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1284 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1285 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1286 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1287 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
1288
1289 /*!< AHB1 peripherals */
1290 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1291 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1292 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1293 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1294 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1295 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1296 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1297 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1298 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1299 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1300 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1301 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1302 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1303 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1304 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1305 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1306 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1307 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1308 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1309 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1310 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1311 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1312 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1313 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1314 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1315 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1316 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1317 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1318 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1319 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1320 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1321 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1322 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1323 #define ETH_MAC_BASE (ETH_BASE)
1324 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1325 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1326 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1327 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1328
1329 /*!< AHB2 peripherals */
1330 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1331 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1332 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1333 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1334 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1335
1336 /*!< FMC Bankx registers base address */
1337 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1338 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1339 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1340 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1341
1342
1343 /*!< Debug MCU registers base address */
1344 #define DBGMCU_BASE 0xE0042000U
1345 /*!< USB registers base address */
1346 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1347 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1348
1349 #define USB_OTG_GLOBAL_BASE 0x000U
1350 #define USB_OTG_DEVICE_BASE 0x800U
1351 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1352 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1353 #define USB_OTG_EP_REG_SIZE 0x20U
1354 #define USB_OTG_HOST_BASE 0x400U
1355 #define USB_OTG_HOST_PORT_BASE 0x440U
1356 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1357 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1358 #define USB_OTG_PCGCCTL_BASE 0xE00U
1359 #define USB_OTG_FIFO_BASE 0x1000U
1360 #define USB_OTG_FIFO_SIZE 0x1000U
1361
1362 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
1363 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
1364 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1365 /**
1366 * @}
1367 */
1368
1369 /** @addtogroup Peripheral_declaration
1370 * @{
1371 */
1372 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1373 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1374 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1375 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1376 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1377 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1378 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1379 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1380 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1381 #define RTC ((RTC_TypeDef *) RTC_BASE)
1382 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1383 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1384 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1385 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1386 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1387 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1388 #define USART2 ((USART_TypeDef *) USART2_BASE)
1389 #define USART3 ((USART_TypeDef *) USART3_BASE)
1390 #define UART4 ((USART_TypeDef *) UART4_BASE)
1391 #define UART5 ((USART_TypeDef *) UART5_BASE)
1392 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1393 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1394 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1395 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1396 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1397 #define PWR ((PWR_TypeDef *) PWR_BASE)
1398 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1399 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1400 #define UART7 ((USART_TypeDef *) UART7_BASE)
1401 #define UART8 ((USART_TypeDef *) UART8_BASE)
1402 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1403 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1404 #define USART1 ((USART_TypeDef *) USART1_BASE)
1405 #define USART6 ((USART_TypeDef *) USART6_BASE)
1406 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1407 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1408 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1409 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1410 /* Legacy define */
1411 #define ADC ADC123_COMMON
1412 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1413 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1414 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1415 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1416 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1417 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1418 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1419 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1420 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1421 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1422 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1423 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1424 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1425 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1426 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1427 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1428 #define DSI ((DSI_TypeDef *)DSI_BASE)
1429 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1430 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1431 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1432 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1433 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1434 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1435 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1436 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1437 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1438 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1439 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1440 #define CRC ((CRC_TypeDef *) CRC_BASE)
1441 #define RCC ((RCC_TypeDef *) RCC_BASE)
1442 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1443 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1444 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1445 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1446 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1447 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1448 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1449 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1450 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1451 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1452 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1453 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1454 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1455 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1456 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1457 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1458 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1459 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1460 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1461 #define ETH ((ETH_TypeDef *) ETH_BASE)
1462 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1463 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1464 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1465 #define HASH ((HASH_TypeDef *) HASH_BASE)
1466 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1467 #define RNG ((RNG_TypeDef *) RNG_BASE)
1468 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1469 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1470 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1471 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1472 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1473 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1474 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1475 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1476
1477 /**
1478 * @}
1479 */
1480
1481 /** @addtogroup Exported_constants
1482 * @{
1483 */
1484
1485 /** @addtogroup Peripheral_Registers_Bits_Definition
1486 * @{
1487 */
1488
1489 /******************************************************************************/
1490 /* Peripheral Registers_Bits_Definition */
1491 /******************************************************************************/
1492
1493 /******************************************************************************/
1494 /* */
1495 /* Analog to Digital Converter */
1496 /* */
1497 /******************************************************************************/
1498 /*
1499 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1500 */
1501 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
1502
1503 /******************** Bit definition for ADC_SR register ********************/
1504 #define ADC_SR_AWD_Pos (0U)
1505 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1506 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1507 #define ADC_SR_EOC_Pos (1U)
1508 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1509 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1510 #define ADC_SR_JEOC_Pos (2U)
1511 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1512 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1513 #define ADC_SR_JSTRT_Pos (3U)
1514 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1515 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1516 #define ADC_SR_STRT_Pos (4U)
1517 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1518 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1519 #define ADC_SR_OVR_Pos (5U)
1520 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1521 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1522
1523 /******************* Bit definition for ADC_CR1 register ********************/
1524 #define ADC_CR1_AWDCH_Pos (0U)
1525 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1526 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1527 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1528 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1529 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1530 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1531 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1532 #define ADC_CR1_EOCIE_Pos (5U)
1533 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1534 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1535 #define ADC_CR1_AWDIE_Pos (6U)
1536 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1537 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1538 #define ADC_CR1_JEOCIE_Pos (7U)
1539 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1540 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1541 #define ADC_CR1_SCAN_Pos (8U)
1542 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1543 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1544 #define ADC_CR1_AWDSGL_Pos (9U)
1545 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1546 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1547 #define ADC_CR1_JAUTO_Pos (10U)
1548 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1549 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1550 #define ADC_CR1_DISCEN_Pos (11U)
1551 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1552 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1553 #define ADC_CR1_JDISCEN_Pos (12U)
1554 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1555 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1556 #define ADC_CR1_DISCNUM_Pos (13U)
1557 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1558 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1559 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1560 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1561 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1562 #define ADC_CR1_JAWDEN_Pos (22U)
1563 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1564 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1565 #define ADC_CR1_AWDEN_Pos (23U)
1566 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1567 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1568 #define ADC_CR1_RES_Pos (24U)
1569 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1570 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1571 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1572 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1573 #define ADC_CR1_OVRIE_Pos (26U)
1574 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1575 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1576
1577 /******************* Bit definition for ADC_CR2 register ********************/
1578 #define ADC_CR2_ADON_Pos (0U)
1579 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1580 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1581 #define ADC_CR2_CONT_Pos (1U)
1582 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1583 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1584 #define ADC_CR2_DMA_Pos (8U)
1585 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1586 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1587 #define ADC_CR2_DDS_Pos (9U)
1588 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1589 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1590 #define ADC_CR2_EOCS_Pos (10U)
1591 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1592 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1593 #define ADC_CR2_ALIGN_Pos (11U)
1594 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1595 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1596 #define ADC_CR2_JEXTSEL_Pos (16U)
1597 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1598 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1599 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1600 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1601 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1602 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1603 #define ADC_CR2_JEXTEN_Pos (20U)
1604 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1605 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1606 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1607 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1608 #define ADC_CR2_JSWSTART_Pos (22U)
1609 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1610 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1611 #define ADC_CR2_EXTSEL_Pos (24U)
1612 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1613 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1614 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1615 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1616 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1617 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1618 #define ADC_CR2_EXTEN_Pos (28U)
1619 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1620 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1621 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1622 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1623 #define ADC_CR2_SWSTART_Pos (30U)
1624 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1625 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1626
1627 /****************** Bit definition for ADC_SMPR1 register *******************/
1628 #define ADC_SMPR1_SMP10_Pos (0U)
1629 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1630 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1631 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1632 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1633 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1634 #define ADC_SMPR1_SMP11_Pos (3U)
1635 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1636 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1637 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1638 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1639 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1640 #define ADC_SMPR1_SMP12_Pos (6U)
1641 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1642 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1643 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1644 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1645 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1646 #define ADC_SMPR1_SMP13_Pos (9U)
1647 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1648 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1649 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1650 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1651 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1652 #define ADC_SMPR1_SMP14_Pos (12U)
1653 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1654 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1655 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1656 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1657 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1658 #define ADC_SMPR1_SMP15_Pos (15U)
1659 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1660 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1661 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1662 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1663 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1664 #define ADC_SMPR1_SMP16_Pos (18U)
1665 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1666 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1667 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1668 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1669 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1670 #define ADC_SMPR1_SMP17_Pos (21U)
1671 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1672 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1673 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1674 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1675 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1676 #define ADC_SMPR1_SMP18_Pos (24U)
1677 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1678 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1679 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1680 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1681 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1682
1683 /****************** Bit definition for ADC_SMPR2 register *******************/
1684 #define ADC_SMPR2_SMP0_Pos (0U)
1685 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1686 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1687 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1688 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1689 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1690 #define ADC_SMPR2_SMP1_Pos (3U)
1691 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1692 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1693 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1694 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1695 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1696 #define ADC_SMPR2_SMP2_Pos (6U)
1697 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1698 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1699 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1700 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1701 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1702 #define ADC_SMPR2_SMP3_Pos (9U)
1703 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1704 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1705 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1706 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1707 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1708 #define ADC_SMPR2_SMP4_Pos (12U)
1709 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1710 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1711 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1712 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1713 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1714 #define ADC_SMPR2_SMP5_Pos (15U)
1715 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1716 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1717 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1718 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1719 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1720 #define ADC_SMPR2_SMP6_Pos (18U)
1721 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1722 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1723 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1724 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1725 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1726 #define ADC_SMPR2_SMP7_Pos (21U)
1727 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1728 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1729 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1730 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1731 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1732 #define ADC_SMPR2_SMP8_Pos (24U)
1733 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1734 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1735 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1736 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1737 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1738 #define ADC_SMPR2_SMP9_Pos (27U)
1739 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1740 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1741 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1742 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1743 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1744
1745 /****************** Bit definition for ADC_JOFR1 register *******************/
1746 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1747 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1748 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1749
1750 /****************** Bit definition for ADC_JOFR2 register *******************/
1751 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1752 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1753 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1754
1755 /****************** Bit definition for ADC_JOFR3 register *******************/
1756 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1757 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1758 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1759
1760 /****************** Bit definition for ADC_JOFR4 register *******************/
1761 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1762 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1763 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1764
1765 /******************* Bit definition for ADC_HTR register ********************/
1766 #define ADC_HTR_HT_Pos (0U)
1767 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1768 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1769
1770 /******************* Bit definition for ADC_LTR register ********************/
1771 #define ADC_LTR_LT_Pos (0U)
1772 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1773 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1774
1775 /******************* Bit definition for ADC_SQR1 register *******************/
1776 #define ADC_SQR1_SQ13_Pos (0U)
1777 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1778 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1779 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1780 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1781 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1782 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1783 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1784 #define ADC_SQR1_SQ14_Pos (5U)
1785 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1786 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1787 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1788 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1789 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1790 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1791 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1792 #define ADC_SQR1_SQ15_Pos (10U)
1793 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1794 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1795 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1796 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1797 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1798 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1799 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1800 #define ADC_SQR1_SQ16_Pos (15U)
1801 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1802 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1803 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1804 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1805 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1806 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1807 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1808 #define ADC_SQR1_L_Pos (20U)
1809 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1810 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1811 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1812 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1813 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1814 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1815
1816 /******************* Bit definition for ADC_SQR2 register *******************/
1817 #define ADC_SQR2_SQ7_Pos (0U)
1818 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1819 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1820 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1821 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1822 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1823 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1824 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1825 #define ADC_SQR2_SQ8_Pos (5U)
1826 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1827 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1828 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1829 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1830 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1831 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1832 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1833 #define ADC_SQR2_SQ9_Pos (10U)
1834 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1835 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1836 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1837 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1838 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1839 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1840 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1841 #define ADC_SQR2_SQ10_Pos (15U)
1842 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1843 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1844 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1845 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1846 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1847 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1848 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1849 #define ADC_SQR2_SQ11_Pos (20U)
1850 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1851 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1852 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1853 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1854 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1855 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1856 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1857 #define ADC_SQR2_SQ12_Pos (25U)
1858 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1859 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1860 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1861 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1862 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1863 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1864 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1865
1866 /******************* Bit definition for ADC_SQR3 register *******************/
1867 #define ADC_SQR3_SQ1_Pos (0U)
1868 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1869 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1870 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1871 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1872 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1873 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1874 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1875 #define ADC_SQR3_SQ2_Pos (5U)
1876 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1877 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1878 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1879 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1880 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1881 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1882 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1883 #define ADC_SQR3_SQ3_Pos (10U)
1884 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1885 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1886 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1887 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1888 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1889 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1890 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1891 #define ADC_SQR3_SQ4_Pos (15U)
1892 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1893 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1894 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1895 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1896 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1897 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1898 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1899 #define ADC_SQR3_SQ5_Pos (20U)
1900 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1901 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1902 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1903 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1904 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1905 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1906 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1907 #define ADC_SQR3_SQ6_Pos (25U)
1908 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1909 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1910 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1911 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1912 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1913 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1914 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1915
1916 /******************* Bit definition for ADC_JSQR register *******************/
1917 #define ADC_JSQR_JSQ1_Pos (0U)
1918 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1919 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1920 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1921 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1922 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1923 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1924 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1925 #define ADC_JSQR_JSQ2_Pos (5U)
1926 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1927 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1928 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1929 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1930 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1931 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1932 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1933 #define ADC_JSQR_JSQ3_Pos (10U)
1934 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1935 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1936 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1937 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1938 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1939 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1940 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1941 #define ADC_JSQR_JSQ4_Pos (15U)
1942 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1943 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1944 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1945 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1946 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1947 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1948 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1949 #define ADC_JSQR_JL_Pos (20U)
1950 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1951 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1952 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1953 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1954
1955 /******************* Bit definition for ADC_JDR1 register *******************/
1956 #define ADC_JDR1_JDATA_Pos (0U)
1957 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1958 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1959
1960 /******************* Bit definition for ADC_JDR2 register *******************/
1961 #define ADC_JDR2_JDATA_Pos (0U)
1962 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1963 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1964
1965 /******************* Bit definition for ADC_JDR3 register *******************/
1966 #define ADC_JDR3_JDATA_Pos (0U)
1967 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1968 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1969
1970 /******************* Bit definition for ADC_JDR4 register *******************/
1971 #define ADC_JDR4_JDATA_Pos (0U)
1972 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1973 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1974
1975 /******************** Bit definition for ADC_DR register ********************/
1976 #define ADC_DR_DATA_Pos (0U)
1977 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1978 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1979 #define ADC_DR_ADC2DATA_Pos (16U)
1980 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1981 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1982
1983 /******************* Bit definition for ADC_CSR register ********************/
1984 #define ADC_CSR_AWD1_Pos (0U)
1985 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1986 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1987 #define ADC_CSR_EOC1_Pos (1U)
1988 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1989 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1990 #define ADC_CSR_JEOC1_Pos (2U)
1991 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1992 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1993 #define ADC_CSR_JSTRT1_Pos (3U)
1994 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1995 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1996 #define ADC_CSR_STRT1_Pos (4U)
1997 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1998 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1999 #define ADC_CSR_OVR1_Pos (5U)
2000 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
2001 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
2002 #define ADC_CSR_AWD2_Pos (8U)
2003 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
2004 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
2005 #define ADC_CSR_EOC2_Pos (9U)
2006 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
2007 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
2008 #define ADC_CSR_JEOC2_Pos (10U)
2009 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
2010 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
2011 #define ADC_CSR_JSTRT2_Pos (11U)
2012 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
2013 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
2014 #define ADC_CSR_STRT2_Pos (12U)
2015 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
2016 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
2017 #define ADC_CSR_OVR2_Pos (13U)
2018 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
2019 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
2020 #define ADC_CSR_AWD3_Pos (16U)
2021 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
2022 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
2023 #define ADC_CSR_EOC3_Pos (17U)
2024 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
2025 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
2026 #define ADC_CSR_JEOC3_Pos (18U)
2027 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
2028 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
2029 #define ADC_CSR_JSTRT3_Pos (19U)
2030 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
2031 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
2032 #define ADC_CSR_STRT3_Pos (20U)
2033 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
2034 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
2035 #define ADC_CSR_OVR3_Pos (21U)
2036 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
2037 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
2038
2039 /* Legacy defines */
2040 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
2041 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
2042 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
2043
2044 /******************* Bit definition for ADC_CCR register ********************/
2045 #define ADC_CCR_MULTI_Pos (0U)
2046 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
2047 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
2048 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
2049 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
2050 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
2051 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
2052 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
2053 #define ADC_CCR_DELAY_Pos (8U)
2054 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2055 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
2056 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2057 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2058 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2059 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2060 #define ADC_CCR_DDS_Pos (13U)
2061 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
2062 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
2063 #define ADC_CCR_DMA_Pos (14U)
2064 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
2065 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
2066 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
2067 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
2068 #define ADC_CCR_ADCPRE_Pos (16U)
2069 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
2070 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
2071 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
2072 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
2073 #define ADC_CCR_VBATE_Pos (22U)
2074 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
2075 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
2076 #define ADC_CCR_TSVREFE_Pos (23U)
2077 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
2078 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
2079
2080 /******************* Bit definition for ADC_CDR register ********************/
2081 #define ADC_CDR_DATA1_Pos (0U)
2082 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
2083 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
2084 #define ADC_CDR_DATA2_Pos (16U)
2085 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
2086 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
2087
2088 /* Legacy defines */
2089 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
2090 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
2091
2092 /******************************************************************************/
2093 /* */
2094 /* Controller Area Network */
2095 /* */
2096 /******************************************************************************/
2097 /*!<CAN control and status registers */
2098 /******************* Bit definition for CAN_MCR register ********************/
2099 #define CAN_MCR_INRQ_Pos (0U)
2100 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2101 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2102 #define CAN_MCR_SLEEP_Pos (1U)
2103 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2104 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2105 #define CAN_MCR_TXFP_Pos (2U)
2106 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2107 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2108 #define CAN_MCR_RFLM_Pos (3U)
2109 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2110 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2111 #define CAN_MCR_NART_Pos (4U)
2112 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2113 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2114 #define CAN_MCR_AWUM_Pos (5U)
2115 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2116 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2117 #define CAN_MCR_ABOM_Pos (6U)
2118 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2119 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2120 #define CAN_MCR_TTCM_Pos (7U)
2121 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2122 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2123 #define CAN_MCR_RESET_Pos (15U)
2124 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2125 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2126 #define CAN_MCR_DBF_Pos (16U)
2127 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
2128 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
2129 /******************* Bit definition for CAN_MSR register ********************/
2130 #define CAN_MSR_INAK_Pos (0U)
2131 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2132 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2133 #define CAN_MSR_SLAK_Pos (1U)
2134 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2135 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2136 #define CAN_MSR_ERRI_Pos (2U)
2137 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2138 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2139 #define CAN_MSR_WKUI_Pos (3U)
2140 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2141 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2142 #define CAN_MSR_SLAKI_Pos (4U)
2143 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2144 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2145 #define CAN_MSR_TXM_Pos (8U)
2146 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2147 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2148 #define CAN_MSR_RXM_Pos (9U)
2149 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2150 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2151 #define CAN_MSR_SAMP_Pos (10U)
2152 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2153 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2154 #define CAN_MSR_RX_Pos (11U)
2155 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2156 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2157
2158 /******************* Bit definition for CAN_TSR register ********************/
2159 #define CAN_TSR_RQCP0_Pos (0U)
2160 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2161 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2162 #define CAN_TSR_TXOK0_Pos (1U)
2163 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2164 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2165 #define CAN_TSR_ALST0_Pos (2U)
2166 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2167 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2168 #define CAN_TSR_TERR0_Pos (3U)
2169 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2170 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2171 #define CAN_TSR_ABRQ0_Pos (7U)
2172 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2173 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2174 #define CAN_TSR_RQCP1_Pos (8U)
2175 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2176 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2177 #define CAN_TSR_TXOK1_Pos (9U)
2178 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2179 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2180 #define CAN_TSR_ALST1_Pos (10U)
2181 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2182 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2183 #define CAN_TSR_TERR1_Pos (11U)
2184 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2185 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2186 #define CAN_TSR_ABRQ1_Pos (15U)
2187 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2188 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2189 #define CAN_TSR_RQCP2_Pos (16U)
2190 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2191 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2192 #define CAN_TSR_TXOK2_Pos (17U)
2193 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2194 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2195 #define CAN_TSR_ALST2_Pos (18U)
2196 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2197 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2198 #define CAN_TSR_TERR2_Pos (19U)
2199 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2200 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2201 #define CAN_TSR_ABRQ2_Pos (23U)
2202 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2203 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2204 #define CAN_TSR_CODE_Pos (24U)
2205 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2206 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2207
2208 #define CAN_TSR_TME_Pos (26U)
2209 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2210 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2211 #define CAN_TSR_TME0_Pos (26U)
2212 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2213 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2214 #define CAN_TSR_TME1_Pos (27U)
2215 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2216 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2217 #define CAN_TSR_TME2_Pos (28U)
2218 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2219 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2220
2221 #define CAN_TSR_LOW_Pos (29U)
2222 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2223 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2224 #define CAN_TSR_LOW0_Pos (29U)
2225 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2226 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2227 #define CAN_TSR_LOW1_Pos (30U)
2228 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2229 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2230 #define CAN_TSR_LOW2_Pos (31U)
2231 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2232 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2233
2234 /******************* Bit definition for CAN_RF0R register *******************/
2235 #define CAN_RF0R_FMP0_Pos (0U)
2236 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2237 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2238 #define CAN_RF0R_FULL0_Pos (3U)
2239 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2240 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2241 #define CAN_RF0R_FOVR0_Pos (4U)
2242 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2243 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2244 #define CAN_RF0R_RFOM0_Pos (5U)
2245 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2246 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2247
2248 /******************* Bit definition for CAN_RF1R register *******************/
2249 #define CAN_RF1R_FMP1_Pos (0U)
2250 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2251 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2252 #define CAN_RF1R_FULL1_Pos (3U)
2253 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2254 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2255 #define CAN_RF1R_FOVR1_Pos (4U)
2256 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2257 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2258 #define CAN_RF1R_RFOM1_Pos (5U)
2259 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2260 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2261
2262 /******************** Bit definition for CAN_IER register *******************/
2263 #define CAN_IER_TMEIE_Pos (0U)
2264 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2265 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2266 #define CAN_IER_FMPIE0_Pos (1U)
2267 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2268 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2269 #define CAN_IER_FFIE0_Pos (2U)
2270 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2271 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2272 #define CAN_IER_FOVIE0_Pos (3U)
2273 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2274 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2275 #define CAN_IER_FMPIE1_Pos (4U)
2276 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2277 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2278 #define CAN_IER_FFIE1_Pos (5U)
2279 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2280 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2281 #define CAN_IER_FOVIE1_Pos (6U)
2282 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2283 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2284 #define CAN_IER_EWGIE_Pos (8U)
2285 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2286 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2287 #define CAN_IER_EPVIE_Pos (9U)
2288 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2289 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2290 #define CAN_IER_BOFIE_Pos (10U)
2291 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2292 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2293 #define CAN_IER_LECIE_Pos (11U)
2294 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2295 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2296 #define CAN_IER_ERRIE_Pos (15U)
2297 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2298 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2299 #define CAN_IER_WKUIE_Pos (16U)
2300 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2301 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2302 #define CAN_IER_SLKIE_Pos (17U)
2303 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2304 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2305 #define CAN_IER_EWGIE_Pos (8U)
2306
2307 /******************** Bit definition for CAN_ESR register *******************/
2308 #define CAN_ESR_EWGF_Pos (0U)
2309 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2310 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2311 #define CAN_ESR_EPVF_Pos (1U)
2312 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2313 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2314 #define CAN_ESR_BOFF_Pos (2U)
2315 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2316 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2317
2318 #define CAN_ESR_LEC_Pos (4U)
2319 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2320 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2321 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2322 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2323 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2324
2325 #define CAN_ESR_TEC_Pos (16U)
2326 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2327 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2328 #define CAN_ESR_REC_Pos (24U)
2329 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2330 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2331
2332 /******************* Bit definition for CAN_BTR register ********************/
2333 #define CAN_BTR_BRP_Pos (0U)
2334 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2335 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2336 #define CAN_BTR_TS1_Pos (16U)
2337 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2338 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2339 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2340 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2341 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2342 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2343 #define CAN_BTR_TS2_Pos (20U)
2344 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2345 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2346 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2347 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2348 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2349 #define CAN_BTR_SJW_Pos (24U)
2350 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2351 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2352 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2353 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2354 #define CAN_BTR_LBKM_Pos (30U)
2355 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2356 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2357 #define CAN_BTR_SILM_Pos (31U)
2358 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2359 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2360
2361
2362 /*!<Mailbox registers */
2363 /****************** Bit definition for CAN_TI0R register ********************/
2364 #define CAN_TI0R_TXRQ_Pos (0U)
2365 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2366 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2367 #define CAN_TI0R_RTR_Pos (1U)
2368 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2369 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2370 #define CAN_TI0R_IDE_Pos (2U)
2371 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2372 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2373 #define CAN_TI0R_EXID_Pos (3U)
2374 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2375 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2376 #define CAN_TI0R_STID_Pos (21U)
2377 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2378 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2379
2380 /****************** Bit definition for CAN_TDT0R register *******************/
2381 #define CAN_TDT0R_DLC_Pos (0U)
2382 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2383 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2384 #define CAN_TDT0R_TGT_Pos (8U)
2385 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2386 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2387 #define CAN_TDT0R_TIME_Pos (16U)
2388 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2389 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2390
2391 /****************** Bit definition for CAN_TDL0R register *******************/
2392 #define CAN_TDL0R_DATA0_Pos (0U)
2393 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2394 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2395 #define CAN_TDL0R_DATA1_Pos (8U)
2396 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2397 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2398 #define CAN_TDL0R_DATA2_Pos (16U)
2399 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2400 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2401 #define CAN_TDL0R_DATA3_Pos (24U)
2402 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2403 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2404
2405 /****************** Bit definition for CAN_TDH0R register *******************/
2406 #define CAN_TDH0R_DATA4_Pos (0U)
2407 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2408 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2409 #define CAN_TDH0R_DATA5_Pos (8U)
2410 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2411 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2412 #define CAN_TDH0R_DATA6_Pos (16U)
2413 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2414 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2415 #define CAN_TDH0R_DATA7_Pos (24U)
2416 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2417 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2418
2419 /******************* Bit definition for CAN_TI1R register *******************/
2420 #define CAN_TI1R_TXRQ_Pos (0U)
2421 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2422 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2423 #define CAN_TI1R_RTR_Pos (1U)
2424 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2425 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2426 #define CAN_TI1R_IDE_Pos (2U)
2427 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2428 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2429 #define CAN_TI1R_EXID_Pos (3U)
2430 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2431 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2432 #define CAN_TI1R_STID_Pos (21U)
2433 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2434 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2435
2436 /******************* Bit definition for CAN_TDT1R register ******************/
2437 #define CAN_TDT1R_DLC_Pos (0U)
2438 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2439 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2440 #define CAN_TDT1R_TGT_Pos (8U)
2441 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2442 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2443 #define CAN_TDT1R_TIME_Pos (16U)
2444 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2445 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2446
2447 /******************* Bit definition for CAN_TDL1R register ******************/
2448 #define CAN_TDL1R_DATA0_Pos (0U)
2449 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2450 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2451 #define CAN_TDL1R_DATA1_Pos (8U)
2452 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2453 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2454 #define CAN_TDL1R_DATA2_Pos (16U)
2455 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2456 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2457 #define CAN_TDL1R_DATA3_Pos (24U)
2458 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2459 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2460
2461 /******************* Bit definition for CAN_TDH1R register ******************/
2462 #define CAN_TDH1R_DATA4_Pos (0U)
2463 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2464 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2465 #define CAN_TDH1R_DATA5_Pos (8U)
2466 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2467 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2468 #define CAN_TDH1R_DATA6_Pos (16U)
2469 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2470 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2471 #define CAN_TDH1R_DATA7_Pos (24U)
2472 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2473 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2474
2475 /******************* Bit definition for CAN_TI2R register *******************/
2476 #define CAN_TI2R_TXRQ_Pos (0U)
2477 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2478 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2479 #define CAN_TI2R_RTR_Pos (1U)
2480 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2481 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2482 #define CAN_TI2R_IDE_Pos (2U)
2483 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2484 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2485 #define CAN_TI2R_EXID_Pos (3U)
2486 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2487 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2488 #define CAN_TI2R_STID_Pos (21U)
2489 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2490 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2491
2492 /******************* Bit definition for CAN_TDT2R register ******************/
2493 #define CAN_TDT2R_DLC_Pos (0U)
2494 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2495 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2496 #define CAN_TDT2R_TGT_Pos (8U)
2497 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2498 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2499 #define CAN_TDT2R_TIME_Pos (16U)
2500 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2501 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2502
2503 /******************* Bit definition for CAN_TDL2R register ******************/
2504 #define CAN_TDL2R_DATA0_Pos (0U)
2505 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2506 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2507 #define CAN_TDL2R_DATA1_Pos (8U)
2508 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2509 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2510 #define CAN_TDL2R_DATA2_Pos (16U)
2511 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2512 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2513 #define CAN_TDL2R_DATA3_Pos (24U)
2514 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2515 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2516
2517 /******************* Bit definition for CAN_TDH2R register ******************/
2518 #define CAN_TDH2R_DATA4_Pos (0U)
2519 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2520 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2521 #define CAN_TDH2R_DATA5_Pos (8U)
2522 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2523 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2524 #define CAN_TDH2R_DATA6_Pos (16U)
2525 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2526 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2527 #define CAN_TDH2R_DATA7_Pos (24U)
2528 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2529 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2530
2531 /******************* Bit definition for CAN_RI0R register *******************/
2532 #define CAN_RI0R_RTR_Pos (1U)
2533 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2534 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2535 #define CAN_RI0R_IDE_Pos (2U)
2536 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2537 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2538 #define CAN_RI0R_EXID_Pos (3U)
2539 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2540 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2541 #define CAN_RI0R_STID_Pos (21U)
2542 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2543 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2544
2545 /******************* Bit definition for CAN_RDT0R register ******************/
2546 #define CAN_RDT0R_DLC_Pos (0U)
2547 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2548 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2549 #define CAN_RDT0R_FMI_Pos (8U)
2550 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2551 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2552 #define CAN_RDT0R_TIME_Pos (16U)
2553 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2554 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2555
2556 /******************* Bit definition for CAN_RDL0R register ******************/
2557 #define CAN_RDL0R_DATA0_Pos (0U)
2558 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2559 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2560 #define CAN_RDL0R_DATA1_Pos (8U)
2561 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2562 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2563 #define CAN_RDL0R_DATA2_Pos (16U)
2564 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2565 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2566 #define CAN_RDL0R_DATA3_Pos (24U)
2567 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2568 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2569
2570 /******************* Bit definition for CAN_RDH0R register ******************/
2571 #define CAN_RDH0R_DATA4_Pos (0U)
2572 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2573 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2574 #define CAN_RDH0R_DATA5_Pos (8U)
2575 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2576 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2577 #define CAN_RDH0R_DATA6_Pos (16U)
2578 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2579 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2580 #define CAN_RDH0R_DATA7_Pos (24U)
2581 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2582 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2583
2584 /******************* Bit definition for CAN_RI1R register *******************/
2585 #define CAN_RI1R_RTR_Pos (1U)
2586 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2587 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2588 #define CAN_RI1R_IDE_Pos (2U)
2589 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2590 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2591 #define CAN_RI1R_EXID_Pos (3U)
2592 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2593 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2594 #define CAN_RI1R_STID_Pos (21U)
2595 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2596 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2597
2598 /******************* Bit definition for CAN_RDT1R register ******************/
2599 #define CAN_RDT1R_DLC_Pos (0U)
2600 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2601 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2602 #define CAN_RDT1R_FMI_Pos (8U)
2603 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2604 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2605 #define CAN_RDT1R_TIME_Pos (16U)
2606 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2607 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2608
2609 /******************* Bit definition for CAN_RDL1R register ******************/
2610 #define CAN_RDL1R_DATA0_Pos (0U)
2611 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2612 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2613 #define CAN_RDL1R_DATA1_Pos (8U)
2614 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2615 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2616 #define CAN_RDL1R_DATA2_Pos (16U)
2617 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2618 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2619 #define CAN_RDL1R_DATA3_Pos (24U)
2620 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2621 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2622
2623 /******************* Bit definition for CAN_RDH1R register ******************/
2624 #define CAN_RDH1R_DATA4_Pos (0U)
2625 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2626 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2627 #define CAN_RDH1R_DATA5_Pos (8U)
2628 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2629 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2630 #define CAN_RDH1R_DATA6_Pos (16U)
2631 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2632 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2633 #define CAN_RDH1R_DATA7_Pos (24U)
2634 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2635 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2636
2637 /*!<CAN filter registers */
2638 /******************* Bit definition for CAN_FMR register ********************/
2639 #define CAN_FMR_FINIT_Pos (0U)
2640 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2641 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2642 #define CAN_FMR_CAN2SB_Pos (8U)
2643 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2644 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2645
2646 /******************* Bit definition for CAN_FM1R register *******************/
2647 #define CAN_FM1R_FBM_Pos (0U)
2648 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2649 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2650 #define CAN_FM1R_FBM0_Pos (0U)
2651 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2652 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2653 #define CAN_FM1R_FBM1_Pos (1U)
2654 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2655 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2656 #define CAN_FM1R_FBM2_Pos (2U)
2657 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2658 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2659 #define CAN_FM1R_FBM3_Pos (3U)
2660 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2661 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2662 #define CAN_FM1R_FBM4_Pos (4U)
2663 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2664 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2665 #define CAN_FM1R_FBM5_Pos (5U)
2666 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2667 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2668 #define CAN_FM1R_FBM6_Pos (6U)
2669 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2670 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2671 #define CAN_FM1R_FBM7_Pos (7U)
2672 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2673 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2674 #define CAN_FM1R_FBM8_Pos (8U)
2675 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2676 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2677 #define CAN_FM1R_FBM9_Pos (9U)
2678 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2679 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2680 #define CAN_FM1R_FBM10_Pos (10U)
2681 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2682 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2683 #define CAN_FM1R_FBM11_Pos (11U)
2684 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2685 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2686 #define CAN_FM1R_FBM12_Pos (12U)
2687 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2688 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2689 #define CAN_FM1R_FBM13_Pos (13U)
2690 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2691 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2692 #define CAN_FM1R_FBM14_Pos (14U)
2693 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2694 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2695 #define CAN_FM1R_FBM15_Pos (15U)
2696 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2697 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2698 #define CAN_FM1R_FBM16_Pos (16U)
2699 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2700 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2701 #define CAN_FM1R_FBM17_Pos (17U)
2702 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2703 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2704 #define CAN_FM1R_FBM18_Pos (18U)
2705 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2706 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2707 #define CAN_FM1R_FBM19_Pos (19U)
2708 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2709 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2710 #define CAN_FM1R_FBM20_Pos (20U)
2711 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2712 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2713 #define CAN_FM1R_FBM21_Pos (21U)
2714 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2715 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2716 #define CAN_FM1R_FBM22_Pos (22U)
2717 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2718 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2719 #define CAN_FM1R_FBM23_Pos (23U)
2720 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2721 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2722 #define CAN_FM1R_FBM24_Pos (24U)
2723 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2724 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2725 #define CAN_FM1R_FBM25_Pos (25U)
2726 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2727 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2728 #define CAN_FM1R_FBM26_Pos (26U)
2729 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2730 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2731 #define CAN_FM1R_FBM27_Pos (27U)
2732 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2733 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2734
2735 /******************* Bit definition for CAN_FS1R register *******************/
2736 #define CAN_FS1R_FSC_Pos (0U)
2737 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2738 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2739 #define CAN_FS1R_FSC0_Pos (0U)
2740 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2741 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2742 #define CAN_FS1R_FSC1_Pos (1U)
2743 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2744 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2745 #define CAN_FS1R_FSC2_Pos (2U)
2746 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2747 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2748 #define CAN_FS1R_FSC3_Pos (3U)
2749 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2750 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2751 #define CAN_FS1R_FSC4_Pos (4U)
2752 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2753 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2754 #define CAN_FS1R_FSC5_Pos (5U)
2755 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2756 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2757 #define CAN_FS1R_FSC6_Pos (6U)
2758 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2759 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2760 #define CAN_FS1R_FSC7_Pos (7U)
2761 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2762 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2763 #define CAN_FS1R_FSC8_Pos (8U)
2764 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2765 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2766 #define CAN_FS1R_FSC9_Pos (9U)
2767 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2768 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2769 #define CAN_FS1R_FSC10_Pos (10U)
2770 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2771 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2772 #define CAN_FS1R_FSC11_Pos (11U)
2773 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2774 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2775 #define CAN_FS1R_FSC12_Pos (12U)
2776 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2777 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2778 #define CAN_FS1R_FSC13_Pos (13U)
2779 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2780 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2781 #define CAN_FS1R_FSC14_Pos (14U)
2782 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2783 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2784 #define CAN_FS1R_FSC15_Pos (15U)
2785 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2786 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2787 #define CAN_FS1R_FSC16_Pos (16U)
2788 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2789 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2790 #define CAN_FS1R_FSC17_Pos (17U)
2791 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2792 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2793 #define CAN_FS1R_FSC18_Pos (18U)
2794 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2795 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2796 #define CAN_FS1R_FSC19_Pos (19U)
2797 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2798 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2799 #define CAN_FS1R_FSC20_Pos (20U)
2800 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2801 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2802 #define CAN_FS1R_FSC21_Pos (21U)
2803 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2804 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2805 #define CAN_FS1R_FSC22_Pos (22U)
2806 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2807 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2808 #define CAN_FS1R_FSC23_Pos (23U)
2809 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2810 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2811 #define CAN_FS1R_FSC24_Pos (24U)
2812 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2813 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2814 #define CAN_FS1R_FSC25_Pos (25U)
2815 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2816 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2817 #define CAN_FS1R_FSC26_Pos (26U)
2818 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2819 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2820 #define CAN_FS1R_FSC27_Pos (27U)
2821 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2822 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2823
2824 /****************** Bit definition for CAN_FFA1R register *******************/
2825 #define CAN_FFA1R_FFA_Pos (0U)
2826 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2827 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2828 #define CAN_FFA1R_FFA0_Pos (0U)
2829 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2830 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2831 #define CAN_FFA1R_FFA1_Pos (1U)
2832 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2833 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2834 #define CAN_FFA1R_FFA2_Pos (2U)
2835 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2836 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2837 #define CAN_FFA1R_FFA3_Pos (3U)
2838 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2839 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2840 #define CAN_FFA1R_FFA4_Pos (4U)
2841 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2842 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2843 #define CAN_FFA1R_FFA5_Pos (5U)
2844 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2845 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2846 #define CAN_FFA1R_FFA6_Pos (6U)
2847 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2848 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2849 #define CAN_FFA1R_FFA7_Pos (7U)
2850 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2851 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2852 #define CAN_FFA1R_FFA8_Pos (8U)
2853 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2854 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2855 #define CAN_FFA1R_FFA9_Pos (9U)
2856 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2857 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2858 #define CAN_FFA1R_FFA10_Pos (10U)
2859 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2860 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2861 #define CAN_FFA1R_FFA11_Pos (11U)
2862 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2863 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2864 #define CAN_FFA1R_FFA12_Pos (12U)
2865 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2866 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2867 #define CAN_FFA1R_FFA13_Pos (13U)
2868 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2869 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2870 #define CAN_FFA1R_FFA14_Pos (14U)
2871 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2872 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2873 #define CAN_FFA1R_FFA15_Pos (15U)
2874 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2875 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2876 #define CAN_FFA1R_FFA16_Pos (16U)
2877 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2878 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2879 #define CAN_FFA1R_FFA17_Pos (17U)
2880 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2881 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2882 #define CAN_FFA1R_FFA18_Pos (18U)
2883 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2884 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2885 #define CAN_FFA1R_FFA19_Pos (19U)
2886 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2887 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2888 #define CAN_FFA1R_FFA20_Pos (20U)
2889 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2890 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2891 #define CAN_FFA1R_FFA21_Pos (21U)
2892 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2893 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2894 #define CAN_FFA1R_FFA22_Pos (22U)
2895 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2896 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2897 #define CAN_FFA1R_FFA23_Pos (23U)
2898 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2899 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2900 #define CAN_FFA1R_FFA24_Pos (24U)
2901 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2902 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2903 #define CAN_FFA1R_FFA25_Pos (25U)
2904 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2905 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2906 #define CAN_FFA1R_FFA26_Pos (26U)
2907 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2908 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2909 #define CAN_FFA1R_FFA27_Pos (27U)
2910 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2911 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2912
2913 /******************* Bit definition for CAN_FA1R register *******************/
2914 #define CAN_FA1R_FACT_Pos (0U)
2915 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2916 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2917 #define CAN_FA1R_FACT0_Pos (0U)
2918 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2919 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2920 #define CAN_FA1R_FACT1_Pos (1U)
2921 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2922 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2923 #define CAN_FA1R_FACT2_Pos (2U)
2924 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2925 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2926 #define CAN_FA1R_FACT3_Pos (3U)
2927 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2928 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2929 #define CAN_FA1R_FACT4_Pos (4U)
2930 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2931 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2932 #define CAN_FA1R_FACT5_Pos (5U)
2933 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2934 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2935 #define CAN_FA1R_FACT6_Pos (6U)
2936 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2937 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2938 #define CAN_FA1R_FACT7_Pos (7U)
2939 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2940 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2941 #define CAN_FA1R_FACT8_Pos (8U)
2942 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2943 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2944 #define CAN_FA1R_FACT9_Pos (9U)
2945 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2946 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2947 #define CAN_FA1R_FACT10_Pos (10U)
2948 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2949 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2950 #define CAN_FA1R_FACT11_Pos (11U)
2951 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2952 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2953 #define CAN_FA1R_FACT12_Pos (12U)
2954 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2955 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2956 #define CAN_FA1R_FACT13_Pos (13U)
2957 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2958 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2959 #define CAN_FA1R_FACT14_Pos (14U)
2960 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2961 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2962 #define CAN_FA1R_FACT15_Pos (15U)
2963 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2964 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2965 #define CAN_FA1R_FACT16_Pos (16U)
2966 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2967 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2968 #define CAN_FA1R_FACT17_Pos (17U)
2969 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2970 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2971 #define CAN_FA1R_FACT18_Pos (18U)
2972 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2973 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2974 #define CAN_FA1R_FACT19_Pos (19U)
2975 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2976 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2977 #define CAN_FA1R_FACT20_Pos (20U)
2978 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2979 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2980 #define CAN_FA1R_FACT21_Pos (21U)
2981 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2982 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2983 #define CAN_FA1R_FACT22_Pos (22U)
2984 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2985 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2986 #define CAN_FA1R_FACT23_Pos (23U)
2987 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2988 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2989 #define CAN_FA1R_FACT24_Pos (24U)
2990 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2991 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2992 #define CAN_FA1R_FACT25_Pos (25U)
2993 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2994 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2995 #define CAN_FA1R_FACT26_Pos (26U)
2996 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2997 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
2998 #define CAN_FA1R_FACT27_Pos (27U)
2999 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
3000 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
3001
3002
3003 /******************* Bit definition for CAN_F0R1 register *******************/
3004 #define CAN_F0R1_FB0_Pos (0U)
3005 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
3006 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
3007 #define CAN_F0R1_FB1_Pos (1U)
3008 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
3009 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
3010 #define CAN_F0R1_FB2_Pos (2U)
3011 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
3012 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
3013 #define CAN_F0R1_FB3_Pos (3U)
3014 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
3015 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
3016 #define CAN_F0R1_FB4_Pos (4U)
3017 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
3018 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
3019 #define CAN_F0R1_FB5_Pos (5U)
3020 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
3021 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
3022 #define CAN_F0R1_FB6_Pos (6U)
3023 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
3024 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
3025 #define CAN_F0R1_FB7_Pos (7U)
3026 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
3027 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
3028 #define CAN_F0R1_FB8_Pos (8U)
3029 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
3030 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
3031 #define CAN_F0R1_FB9_Pos (9U)
3032 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
3033 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
3034 #define CAN_F0R1_FB10_Pos (10U)
3035 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
3036 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
3037 #define CAN_F0R1_FB11_Pos (11U)
3038 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
3039 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
3040 #define CAN_F0R1_FB12_Pos (12U)
3041 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
3042 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
3043 #define CAN_F0R1_FB13_Pos (13U)
3044 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
3045 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
3046 #define CAN_F0R1_FB14_Pos (14U)
3047 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
3048 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
3049 #define CAN_F0R1_FB15_Pos (15U)
3050 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3051 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3052 #define CAN_F0R1_FB16_Pos (16U)
3053 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3054 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3055 #define CAN_F0R1_FB17_Pos (17U)
3056 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3057 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3058 #define CAN_F0R1_FB18_Pos (18U)
3059 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3060 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3061 #define CAN_F0R1_FB19_Pos (19U)
3062 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3063 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3064 #define CAN_F0R1_FB20_Pos (20U)
3065 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3066 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3067 #define CAN_F0R1_FB21_Pos (21U)
3068 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3069 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3070 #define CAN_F0R1_FB22_Pos (22U)
3071 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3072 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3073 #define CAN_F0R1_FB23_Pos (23U)
3074 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3075 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3076 #define CAN_F0R1_FB24_Pos (24U)
3077 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3078 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3079 #define CAN_F0R1_FB25_Pos (25U)
3080 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3081 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3082 #define CAN_F0R1_FB26_Pos (26U)
3083 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3084 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3085 #define CAN_F0R1_FB27_Pos (27U)
3086 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3087 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3088 #define CAN_F0R1_FB28_Pos (28U)
3089 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3090 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3091 #define CAN_F0R1_FB29_Pos (29U)
3092 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3093 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3094 #define CAN_F0R1_FB30_Pos (30U)
3095 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3096 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3097 #define CAN_F0R1_FB31_Pos (31U)
3098 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3099 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3100
3101 /******************* Bit definition for CAN_F1R1 register *******************/
3102 #define CAN_F1R1_FB0_Pos (0U)
3103 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3104 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3105 #define CAN_F1R1_FB1_Pos (1U)
3106 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3107 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3108 #define CAN_F1R1_FB2_Pos (2U)
3109 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3110 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3111 #define CAN_F1R1_FB3_Pos (3U)
3112 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3113 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3114 #define CAN_F1R1_FB4_Pos (4U)
3115 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3116 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3117 #define CAN_F1R1_FB5_Pos (5U)
3118 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3119 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3120 #define CAN_F1R1_FB6_Pos (6U)
3121 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3122 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3123 #define CAN_F1R1_FB7_Pos (7U)
3124 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3125 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3126 #define CAN_F1R1_FB8_Pos (8U)
3127 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3128 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3129 #define CAN_F1R1_FB9_Pos (9U)
3130 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3131 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3132 #define CAN_F1R1_FB10_Pos (10U)
3133 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3134 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3135 #define CAN_F1R1_FB11_Pos (11U)
3136 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3137 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3138 #define CAN_F1R1_FB12_Pos (12U)
3139 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3140 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3141 #define CAN_F1R1_FB13_Pos (13U)
3142 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3143 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3144 #define CAN_F1R1_FB14_Pos (14U)
3145 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3146 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3147 #define CAN_F1R1_FB15_Pos (15U)
3148 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3149 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3150 #define CAN_F1R1_FB16_Pos (16U)
3151 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3152 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3153 #define CAN_F1R1_FB17_Pos (17U)
3154 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3155 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3156 #define CAN_F1R1_FB18_Pos (18U)
3157 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3158 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3159 #define CAN_F1R1_FB19_Pos (19U)
3160 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3161 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3162 #define CAN_F1R1_FB20_Pos (20U)
3163 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3164 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3165 #define CAN_F1R1_FB21_Pos (21U)
3166 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3167 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3168 #define CAN_F1R1_FB22_Pos (22U)
3169 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3170 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3171 #define CAN_F1R1_FB23_Pos (23U)
3172 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3173 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3174 #define CAN_F1R1_FB24_Pos (24U)
3175 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3176 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3177 #define CAN_F1R1_FB25_Pos (25U)
3178 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3179 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3180 #define CAN_F1R1_FB26_Pos (26U)
3181 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3182 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3183 #define CAN_F1R1_FB27_Pos (27U)
3184 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3185 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3186 #define CAN_F1R1_FB28_Pos (28U)
3187 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3188 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3189 #define CAN_F1R1_FB29_Pos (29U)
3190 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3191 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3192 #define CAN_F1R1_FB30_Pos (30U)
3193 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3194 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3195 #define CAN_F1R1_FB31_Pos (31U)
3196 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3197 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3198
3199 /******************* Bit definition for CAN_F2R1 register *******************/
3200 #define CAN_F2R1_FB0_Pos (0U)
3201 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3202 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3203 #define CAN_F2R1_FB1_Pos (1U)
3204 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3205 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3206 #define CAN_F2R1_FB2_Pos (2U)
3207 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3208 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3209 #define CAN_F2R1_FB3_Pos (3U)
3210 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3211 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3212 #define CAN_F2R1_FB4_Pos (4U)
3213 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3214 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3215 #define CAN_F2R1_FB5_Pos (5U)
3216 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3217 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3218 #define CAN_F2R1_FB6_Pos (6U)
3219 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3220 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3221 #define CAN_F2R1_FB7_Pos (7U)
3222 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3223 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3224 #define CAN_F2R1_FB8_Pos (8U)
3225 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3226 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3227 #define CAN_F2R1_FB9_Pos (9U)
3228 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3229 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3230 #define CAN_F2R1_FB10_Pos (10U)
3231 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3232 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3233 #define CAN_F2R1_FB11_Pos (11U)
3234 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3235 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3236 #define CAN_F2R1_FB12_Pos (12U)
3237 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3238 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3239 #define CAN_F2R1_FB13_Pos (13U)
3240 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3241 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3242 #define CAN_F2R1_FB14_Pos (14U)
3243 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3244 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3245 #define CAN_F2R1_FB15_Pos (15U)
3246 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3247 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3248 #define CAN_F2R1_FB16_Pos (16U)
3249 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3250 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3251 #define CAN_F2R1_FB17_Pos (17U)
3252 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3253 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3254 #define CAN_F2R1_FB18_Pos (18U)
3255 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3256 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3257 #define CAN_F2R1_FB19_Pos (19U)
3258 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3259 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3260 #define CAN_F2R1_FB20_Pos (20U)
3261 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3262 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3263 #define CAN_F2R1_FB21_Pos (21U)
3264 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3265 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3266 #define CAN_F2R1_FB22_Pos (22U)
3267 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3268 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3269 #define CAN_F2R1_FB23_Pos (23U)
3270 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3271 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3272 #define CAN_F2R1_FB24_Pos (24U)
3273 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3274 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3275 #define CAN_F2R1_FB25_Pos (25U)
3276 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3277 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3278 #define CAN_F2R1_FB26_Pos (26U)
3279 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3280 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3281 #define CAN_F2R1_FB27_Pos (27U)
3282 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3283 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3284 #define CAN_F2R1_FB28_Pos (28U)
3285 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3286 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3287 #define CAN_F2R1_FB29_Pos (29U)
3288 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3289 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3290 #define CAN_F2R1_FB30_Pos (30U)
3291 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3292 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3293 #define CAN_F2R1_FB31_Pos (31U)
3294 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3295 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3296
3297 /******************* Bit definition for CAN_F3R1 register *******************/
3298 #define CAN_F3R1_FB0_Pos (0U)
3299 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3300 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3301 #define CAN_F3R1_FB1_Pos (1U)
3302 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3303 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3304 #define CAN_F3R1_FB2_Pos (2U)
3305 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3306 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3307 #define CAN_F3R1_FB3_Pos (3U)
3308 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3309 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3310 #define CAN_F3R1_FB4_Pos (4U)
3311 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3312 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3313 #define CAN_F3R1_FB5_Pos (5U)
3314 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3315 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3316 #define CAN_F3R1_FB6_Pos (6U)
3317 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3318 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3319 #define CAN_F3R1_FB7_Pos (7U)
3320 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3321 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3322 #define CAN_F3R1_FB8_Pos (8U)
3323 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3324 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3325 #define CAN_F3R1_FB9_Pos (9U)
3326 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3327 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3328 #define CAN_F3R1_FB10_Pos (10U)
3329 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3330 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3331 #define CAN_F3R1_FB11_Pos (11U)
3332 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3333 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3334 #define CAN_F3R1_FB12_Pos (12U)
3335 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3336 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3337 #define CAN_F3R1_FB13_Pos (13U)
3338 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3339 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3340 #define CAN_F3R1_FB14_Pos (14U)
3341 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3342 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3343 #define CAN_F3R1_FB15_Pos (15U)
3344 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3345 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3346 #define CAN_F3R1_FB16_Pos (16U)
3347 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3348 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3349 #define CAN_F3R1_FB17_Pos (17U)
3350 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3351 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3352 #define CAN_F3R1_FB18_Pos (18U)
3353 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3354 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3355 #define CAN_F3R1_FB19_Pos (19U)
3356 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3357 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3358 #define CAN_F3R1_FB20_Pos (20U)
3359 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3360 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3361 #define CAN_F3R1_FB21_Pos (21U)
3362 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3363 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3364 #define CAN_F3R1_FB22_Pos (22U)
3365 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3366 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3367 #define CAN_F3R1_FB23_Pos (23U)
3368 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3369 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3370 #define CAN_F3R1_FB24_Pos (24U)
3371 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3372 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3373 #define CAN_F3R1_FB25_Pos (25U)
3374 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3375 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3376 #define CAN_F3R1_FB26_Pos (26U)
3377 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3378 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3379 #define CAN_F3R1_FB27_Pos (27U)
3380 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3381 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3382 #define CAN_F3R1_FB28_Pos (28U)
3383 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3384 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3385 #define CAN_F3R1_FB29_Pos (29U)
3386 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3387 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3388 #define CAN_F3R1_FB30_Pos (30U)
3389 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3390 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3391 #define CAN_F3R1_FB31_Pos (31U)
3392 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3393 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3394
3395 /******************* Bit definition for CAN_F4R1 register *******************/
3396 #define CAN_F4R1_FB0_Pos (0U)
3397 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3398 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3399 #define CAN_F4R1_FB1_Pos (1U)
3400 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3401 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3402 #define CAN_F4R1_FB2_Pos (2U)
3403 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3404 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3405 #define CAN_F4R1_FB3_Pos (3U)
3406 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3407 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3408 #define CAN_F4R1_FB4_Pos (4U)
3409 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3410 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3411 #define CAN_F4R1_FB5_Pos (5U)
3412 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3413 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3414 #define CAN_F4R1_FB6_Pos (6U)
3415 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3416 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3417 #define CAN_F4R1_FB7_Pos (7U)
3418 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3419 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3420 #define CAN_F4R1_FB8_Pos (8U)
3421 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3422 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3423 #define CAN_F4R1_FB9_Pos (9U)
3424 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3425 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3426 #define CAN_F4R1_FB10_Pos (10U)
3427 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3428 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3429 #define CAN_F4R1_FB11_Pos (11U)
3430 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3431 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3432 #define CAN_F4R1_FB12_Pos (12U)
3433 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3434 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3435 #define CAN_F4R1_FB13_Pos (13U)
3436 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3437 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3438 #define CAN_F4R1_FB14_Pos (14U)
3439 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3440 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3441 #define CAN_F4R1_FB15_Pos (15U)
3442 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3443 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3444 #define CAN_F4R1_FB16_Pos (16U)
3445 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3446 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3447 #define CAN_F4R1_FB17_Pos (17U)
3448 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3449 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3450 #define CAN_F4R1_FB18_Pos (18U)
3451 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3452 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3453 #define CAN_F4R1_FB19_Pos (19U)
3454 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3455 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3456 #define CAN_F4R1_FB20_Pos (20U)
3457 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3458 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3459 #define CAN_F4R1_FB21_Pos (21U)
3460 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3461 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3462 #define CAN_F4R1_FB22_Pos (22U)
3463 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3464 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3465 #define CAN_F4R1_FB23_Pos (23U)
3466 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3467 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3468 #define CAN_F4R1_FB24_Pos (24U)
3469 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3470 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3471 #define CAN_F4R1_FB25_Pos (25U)
3472 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3473 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3474 #define CAN_F4R1_FB26_Pos (26U)
3475 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3476 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3477 #define CAN_F4R1_FB27_Pos (27U)
3478 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3479 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3480 #define CAN_F4R1_FB28_Pos (28U)
3481 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3482 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3483 #define CAN_F4R1_FB29_Pos (29U)
3484 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3485 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3486 #define CAN_F4R1_FB30_Pos (30U)
3487 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3488 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3489 #define CAN_F4R1_FB31_Pos (31U)
3490 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3491 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3492
3493 /******************* Bit definition for CAN_F5R1 register *******************/
3494 #define CAN_F5R1_FB0_Pos (0U)
3495 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3496 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3497 #define CAN_F5R1_FB1_Pos (1U)
3498 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3499 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3500 #define CAN_F5R1_FB2_Pos (2U)
3501 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3502 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3503 #define CAN_F5R1_FB3_Pos (3U)
3504 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3505 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3506 #define CAN_F5R1_FB4_Pos (4U)
3507 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3508 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3509 #define CAN_F5R1_FB5_Pos (5U)
3510 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3511 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3512 #define CAN_F5R1_FB6_Pos (6U)
3513 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3514 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3515 #define CAN_F5R1_FB7_Pos (7U)
3516 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3517 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3518 #define CAN_F5R1_FB8_Pos (8U)
3519 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3520 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3521 #define CAN_F5R1_FB9_Pos (9U)
3522 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3523 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3524 #define CAN_F5R1_FB10_Pos (10U)
3525 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3526 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3527 #define CAN_F5R1_FB11_Pos (11U)
3528 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3529 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3530 #define CAN_F5R1_FB12_Pos (12U)
3531 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3532 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3533 #define CAN_F5R1_FB13_Pos (13U)
3534 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3535 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3536 #define CAN_F5R1_FB14_Pos (14U)
3537 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3538 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3539 #define CAN_F5R1_FB15_Pos (15U)
3540 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3541 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3542 #define CAN_F5R1_FB16_Pos (16U)
3543 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3544 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3545 #define CAN_F5R1_FB17_Pos (17U)
3546 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3547 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3548 #define CAN_F5R1_FB18_Pos (18U)
3549 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3550 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3551 #define CAN_F5R1_FB19_Pos (19U)
3552 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3553 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3554 #define CAN_F5R1_FB20_Pos (20U)
3555 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3556 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3557 #define CAN_F5R1_FB21_Pos (21U)
3558 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3559 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3560 #define CAN_F5R1_FB22_Pos (22U)
3561 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3562 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3563 #define CAN_F5R1_FB23_Pos (23U)
3564 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3565 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3566 #define CAN_F5R1_FB24_Pos (24U)
3567 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3568 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3569 #define CAN_F5R1_FB25_Pos (25U)
3570 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3571 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3572 #define CAN_F5R1_FB26_Pos (26U)
3573 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3574 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3575 #define CAN_F5R1_FB27_Pos (27U)
3576 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3577 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3578 #define CAN_F5R1_FB28_Pos (28U)
3579 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3580 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3581 #define CAN_F5R1_FB29_Pos (29U)
3582 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3583 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3584 #define CAN_F5R1_FB30_Pos (30U)
3585 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3586 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3587 #define CAN_F5R1_FB31_Pos (31U)
3588 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3589 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3590
3591 /******************* Bit definition for CAN_F6R1 register *******************/
3592 #define CAN_F6R1_FB0_Pos (0U)
3593 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3594 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3595 #define CAN_F6R1_FB1_Pos (1U)
3596 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3597 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3598 #define CAN_F6R1_FB2_Pos (2U)
3599 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3600 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3601 #define CAN_F6R1_FB3_Pos (3U)
3602 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3603 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3604 #define CAN_F6R1_FB4_Pos (4U)
3605 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3606 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3607 #define CAN_F6R1_FB5_Pos (5U)
3608 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3609 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3610 #define CAN_F6R1_FB6_Pos (6U)
3611 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3612 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3613 #define CAN_F6R1_FB7_Pos (7U)
3614 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3615 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3616 #define CAN_F6R1_FB8_Pos (8U)
3617 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3618 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3619 #define CAN_F6R1_FB9_Pos (9U)
3620 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3621 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3622 #define CAN_F6R1_FB10_Pos (10U)
3623 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3624 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3625 #define CAN_F6R1_FB11_Pos (11U)
3626 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3627 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3628 #define CAN_F6R1_FB12_Pos (12U)
3629 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3630 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3631 #define CAN_F6R1_FB13_Pos (13U)
3632 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3633 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3634 #define CAN_F6R1_FB14_Pos (14U)
3635 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3636 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3637 #define CAN_F6R1_FB15_Pos (15U)
3638 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3639 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3640 #define CAN_F6R1_FB16_Pos (16U)
3641 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3642 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3643 #define CAN_F6R1_FB17_Pos (17U)
3644 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3645 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3646 #define CAN_F6R1_FB18_Pos (18U)
3647 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3648 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3649 #define CAN_F6R1_FB19_Pos (19U)
3650 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3651 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3652 #define CAN_F6R1_FB20_Pos (20U)
3653 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3654 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3655 #define CAN_F6R1_FB21_Pos (21U)
3656 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3657 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3658 #define CAN_F6R1_FB22_Pos (22U)
3659 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3660 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3661 #define CAN_F6R1_FB23_Pos (23U)
3662 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3663 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3664 #define CAN_F6R1_FB24_Pos (24U)
3665 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3666 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3667 #define CAN_F6R1_FB25_Pos (25U)
3668 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3669 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3670 #define CAN_F6R1_FB26_Pos (26U)
3671 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3672 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3673 #define CAN_F6R1_FB27_Pos (27U)
3674 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3675 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3676 #define CAN_F6R1_FB28_Pos (28U)
3677 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3678 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3679 #define CAN_F6R1_FB29_Pos (29U)
3680 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3681 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3682 #define CAN_F6R1_FB30_Pos (30U)
3683 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3684 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3685 #define CAN_F6R1_FB31_Pos (31U)
3686 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3687 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3688
3689 /******************* Bit definition for CAN_F7R1 register *******************/
3690 #define CAN_F7R1_FB0_Pos (0U)
3691 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3692 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3693 #define CAN_F7R1_FB1_Pos (1U)
3694 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3695 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3696 #define CAN_F7R1_FB2_Pos (2U)
3697 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3698 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3699 #define CAN_F7R1_FB3_Pos (3U)
3700 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3701 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3702 #define CAN_F7R1_FB4_Pos (4U)
3703 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3704 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3705 #define CAN_F7R1_FB5_Pos (5U)
3706 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3707 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3708 #define CAN_F7R1_FB6_Pos (6U)
3709 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3710 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3711 #define CAN_F7R1_FB7_Pos (7U)
3712 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3713 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3714 #define CAN_F7R1_FB8_Pos (8U)
3715 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3716 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3717 #define CAN_F7R1_FB9_Pos (9U)
3718 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3719 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3720 #define CAN_F7R1_FB10_Pos (10U)
3721 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3722 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3723 #define CAN_F7R1_FB11_Pos (11U)
3724 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3725 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3726 #define CAN_F7R1_FB12_Pos (12U)
3727 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3728 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3729 #define CAN_F7R1_FB13_Pos (13U)
3730 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3731 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3732 #define CAN_F7R1_FB14_Pos (14U)
3733 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3734 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3735 #define CAN_F7R1_FB15_Pos (15U)
3736 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3737 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3738 #define CAN_F7R1_FB16_Pos (16U)
3739 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3740 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3741 #define CAN_F7R1_FB17_Pos (17U)
3742 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3743 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3744 #define CAN_F7R1_FB18_Pos (18U)
3745 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3746 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3747 #define CAN_F7R1_FB19_Pos (19U)
3748 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3749 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3750 #define CAN_F7R1_FB20_Pos (20U)
3751 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3752 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3753 #define CAN_F7R1_FB21_Pos (21U)
3754 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3755 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3756 #define CAN_F7R1_FB22_Pos (22U)
3757 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3758 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3759 #define CAN_F7R1_FB23_Pos (23U)
3760 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3761 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3762 #define CAN_F7R1_FB24_Pos (24U)
3763 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3764 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3765 #define CAN_F7R1_FB25_Pos (25U)
3766 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3767 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3768 #define CAN_F7R1_FB26_Pos (26U)
3769 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3770 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3771 #define CAN_F7R1_FB27_Pos (27U)
3772 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3773 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3774 #define CAN_F7R1_FB28_Pos (28U)
3775 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3776 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3777 #define CAN_F7R1_FB29_Pos (29U)
3778 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3779 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3780 #define CAN_F7R1_FB30_Pos (30U)
3781 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3782 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3783 #define CAN_F7R1_FB31_Pos (31U)
3784 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3785 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3786
3787 /******************* Bit definition for CAN_F8R1 register *******************/
3788 #define CAN_F8R1_FB0_Pos (0U)
3789 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3790 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3791 #define CAN_F8R1_FB1_Pos (1U)
3792 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3793 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3794 #define CAN_F8R1_FB2_Pos (2U)
3795 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3796 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3797 #define CAN_F8R1_FB3_Pos (3U)
3798 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3799 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3800 #define CAN_F8R1_FB4_Pos (4U)
3801 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3802 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3803 #define CAN_F8R1_FB5_Pos (5U)
3804 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3805 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3806 #define CAN_F8R1_FB6_Pos (6U)
3807 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3808 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3809 #define CAN_F8R1_FB7_Pos (7U)
3810 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3811 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3812 #define CAN_F8R1_FB8_Pos (8U)
3813 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3814 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3815 #define CAN_F8R1_FB9_Pos (9U)
3816 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3817 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3818 #define CAN_F8R1_FB10_Pos (10U)
3819 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3820 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3821 #define CAN_F8R1_FB11_Pos (11U)
3822 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3823 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3824 #define CAN_F8R1_FB12_Pos (12U)
3825 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3826 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3827 #define CAN_F8R1_FB13_Pos (13U)
3828 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3829 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3830 #define CAN_F8R1_FB14_Pos (14U)
3831 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3832 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3833 #define CAN_F8R1_FB15_Pos (15U)
3834 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3835 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3836 #define CAN_F8R1_FB16_Pos (16U)
3837 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3838 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3839 #define CAN_F8R1_FB17_Pos (17U)
3840 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3841 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3842 #define CAN_F8R1_FB18_Pos (18U)
3843 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3844 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3845 #define CAN_F8R1_FB19_Pos (19U)
3846 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3847 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3848 #define CAN_F8R1_FB20_Pos (20U)
3849 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3850 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3851 #define CAN_F8R1_FB21_Pos (21U)
3852 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3853 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3854 #define CAN_F8R1_FB22_Pos (22U)
3855 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3856 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3857 #define CAN_F8R1_FB23_Pos (23U)
3858 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3859 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3860 #define CAN_F8R1_FB24_Pos (24U)
3861 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3862 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3863 #define CAN_F8R1_FB25_Pos (25U)
3864 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3865 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3866 #define CAN_F8R1_FB26_Pos (26U)
3867 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3868 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3869 #define CAN_F8R1_FB27_Pos (27U)
3870 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3871 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3872 #define CAN_F8R1_FB28_Pos (28U)
3873 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3874 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3875 #define CAN_F8R1_FB29_Pos (29U)
3876 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3877 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3878 #define CAN_F8R1_FB30_Pos (30U)
3879 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3880 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3881 #define CAN_F8R1_FB31_Pos (31U)
3882 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3883 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3884
3885 /******************* Bit definition for CAN_F9R1 register *******************/
3886 #define CAN_F9R1_FB0_Pos (0U)
3887 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3888 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3889 #define CAN_F9R1_FB1_Pos (1U)
3890 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3891 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3892 #define CAN_F9R1_FB2_Pos (2U)
3893 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3894 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3895 #define CAN_F9R1_FB3_Pos (3U)
3896 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3897 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3898 #define CAN_F9R1_FB4_Pos (4U)
3899 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3900 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3901 #define CAN_F9R1_FB5_Pos (5U)
3902 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3903 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3904 #define CAN_F9R1_FB6_Pos (6U)
3905 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3906 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3907 #define CAN_F9R1_FB7_Pos (7U)
3908 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3909 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3910 #define CAN_F9R1_FB8_Pos (8U)
3911 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3912 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3913 #define CAN_F9R1_FB9_Pos (9U)
3914 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3915 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3916 #define CAN_F9R1_FB10_Pos (10U)
3917 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3918 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3919 #define CAN_F9R1_FB11_Pos (11U)
3920 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3921 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3922 #define CAN_F9R1_FB12_Pos (12U)
3923 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3924 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3925 #define CAN_F9R1_FB13_Pos (13U)
3926 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3927 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3928 #define CAN_F9R1_FB14_Pos (14U)
3929 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3930 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3931 #define CAN_F9R1_FB15_Pos (15U)
3932 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3933 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3934 #define CAN_F9R1_FB16_Pos (16U)
3935 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3936 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3937 #define CAN_F9R1_FB17_Pos (17U)
3938 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3939 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3940 #define CAN_F9R1_FB18_Pos (18U)
3941 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3942 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3943 #define CAN_F9R1_FB19_Pos (19U)
3944 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3945 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3946 #define CAN_F9R1_FB20_Pos (20U)
3947 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3948 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3949 #define CAN_F9R1_FB21_Pos (21U)
3950 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3951 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3952 #define CAN_F9R1_FB22_Pos (22U)
3953 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3954 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3955 #define CAN_F9R1_FB23_Pos (23U)
3956 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3957 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3958 #define CAN_F9R1_FB24_Pos (24U)
3959 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3960 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3961 #define CAN_F9R1_FB25_Pos (25U)
3962 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3963 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3964 #define CAN_F9R1_FB26_Pos (26U)
3965 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3966 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3967 #define CAN_F9R1_FB27_Pos (27U)
3968 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3969 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3970 #define CAN_F9R1_FB28_Pos (28U)
3971 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3972 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3973 #define CAN_F9R1_FB29_Pos (29U)
3974 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3975 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3976 #define CAN_F9R1_FB30_Pos (30U)
3977 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3978 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3979 #define CAN_F9R1_FB31_Pos (31U)
3980 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3981 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3982
3983 /******************* Bit definition for CAN_F10R1 register ******************/
3984 #define CAN_F10R1_FB0_Pos (0U)
3985 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3986 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3987 #define CAN_F10R1_FB1_Pos (1U)
3988 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3989 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3990 #define CAN_F10R1_FB2_Pos (2U)
3991 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3992 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3993 #define CAN_F10R1_FB3_Pos (3U)
3994 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3995 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3996 #define CAN_F10R1_FB4_Pos (4U)
3997 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3998 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3999 #define CAN_F10R1_FB5_Pos (5U)
4000 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
4001 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
4002 #define CAN_F10R1_FB6_Pos (6U)
4003 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
4004 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
4005 #define CAN_F10R1_FB7_Pos (7U)
4006 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
4007 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
4008 #define CAN_F10R1_FB8_Pos (8U)
4009 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
4010 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
4011 #define CAN_F10R1_FB9_Pos (9U)
4012 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
4013 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
4014 #define CAN_F10R1_FB10_Pos (10U)
4015 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
4016 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
4017 #define CAN_F10R1_FB11_Pos (11U)
4018 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
4019 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
4020 #define CAN_F10R1_FB12_Pos (12U)
4021 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
4022 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
4023 #define CAN_F10R1_FB13_Pos (13U)
4024 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
4025 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
4026 #define CAN_F10R1_FB14_Pos (14U)
4027 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
4028 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
4029 #define CAN_F10R1_FB15_Pos (15U)
4030 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
4031 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
4032 #define CAN_F10R1_FB16_Pos (16U)
4033 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
4034 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
4035 #define CAN_F10R1_FB17_Pos (17U)
4036 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
4037 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
4038 #define CAN_F10R1_FB18_Pos (18U)
4039 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
4040 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
4041 #define CAN_F10R1_FB19_Pos (19U)
4042 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
4043 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
4044 #define CAN_F10R1_FB20_Pos (20U)
4045 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
4046 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
4047 #define CAN_F10R1_FB21_Pos (21U)
4048 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
4049 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
4050 #define CAN_F10R1_FB22_Pos (22U)
4051 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
4052 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
4053 #define CAN_F10R1_FB23_Pos (23U)
4054 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
4055 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
4056 #define CAN_F10R1_FB24_Pos (24U)
4057 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
4058 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
4059 #define CAN_F10R1_FB25_Pos (25U)
4060 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
4061 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
4062 #define CAN_F10R1_FB26_Pos (26U)
4063 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
4064 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
4065 #define CAN_F10R1_FB27_Pos (27U)
4066 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
4067 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
4068 #define CAN_F10R1_FB28_Pos (28U)
4069 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
4070 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
4071 #define CAN_F10R1_FB29_Pos (29U)
4072 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
4073 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
4074 #define CAN_F10R1_FB30_Pos (30U)
4075 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4076 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4077 #define CAN_F10R1_FB31_Pos (31U)
4078 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4079 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4080
4081 /******************* Bit definition for CAN_F11R1 register ******************/
4082 #define CAN_F11R1_FB0_Pos (0U)
4083 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4084 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4085 #define CAN_F11R1_FB1_Pos (1U)
4086 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4087 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4088 #define CAN_F11R1_FB2_Pos (2U)
4089 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4090 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4091 #define CAN_F11R1_FB3_Pos (3U)
4092 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4093 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4094 #define CAN_F11R1_FB4_Pos (4U)
4095 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4096 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4097 #define CAN_F11R1_FB5_Pos (5U)
4098 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4099 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4100 #define CAN_F11R1_FB6_Pos (6U)
4101 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4102 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4103 #define CAN_F11R1_FB7_Pos (7U)
4104 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4105 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4106 #define CAN_F11R1_FB8_Pos (8U)
4107 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4108 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4109 #define CAN_F11R1_FB9_Pos (9U)
4110 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4111 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4112 #define CAN_F11R1_FB10_Pos (10U)
4113 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4114 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4115 #define CAN_F11R1_FB11_Pos (11U)
4116 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4117 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4118 #define CAN_F11R1_FB12_Pos (12U)
4119 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4120 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4121 #define CAN_F11R1_FB13_Pos (13U)
4122 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4123 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4124 #define CAN_F11R1_FB14_Pos (14U)
4125 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4126 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4127 #define CAN_F11R1_FB15_Pos (15U)
4128 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4129 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4130 #define CAN_F11R1_FB16_Pos (16U)
4131 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4132 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4133 #define CAN_F11R1_FB17_Pos (17U)
4134 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4135 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4136 #define CAN_F11R1_FB18_Pos (18U)
4137 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4138 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4139 #define CAN_F11R1_FB19_Pos (19U)
4140 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4141 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4142 #define CAN_F11R1_FB20_Pos (20U)
4143 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4144 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4145 #define CAN_F11R1_FB21_Pos (21U)
4146 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4147 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4148 #define CAN_F11R1_FB22_Pos (22U)
4149 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4150 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4151 #define CAN_F11R1_FB23_Pos (23U)
4152 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4153 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4154 #define CAN_F11R1_FB24_Pos (24U)
4155 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4156 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4157 #define CAN_F11R1_FB25_Pos (25U)
4158 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4159 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4160 #define CAN_F11R1_FB26_Pos (26U)
4161 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4162 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4163 #define CAN_F11R1_FB27_Pos (27U)
4164 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4165 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4166 #define CAN_F11R1_FB28_Pos (28U)
4167 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4168 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4169 #define CAN_F11R1_FB29_Pos (29U)
4170 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4171 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4172 #define CAN_F11R1_FB30_Pos (30U)
4173 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4174 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4175 #define CAN_F11R1_FB31_Pos (31U)
4176 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4177 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4178
4179 /******************* Bit definition for CAN_F12R1 register ******************/
4180 #define CAN_F12R1_FB0_Pos (0U)
4181 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4182 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4183 #define CAN_F12R1_FB1_Pos (1U)
4184 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4185 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4186 #define CAN_F12R1_FB2_Pos (2U)
4187 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4188 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4189 #define CAN_F12R1_FB3_Pos (3U)
4190 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4191 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4192 #define CAN_F12R1_FB4_Pos (4U)
4193 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4194 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4195 #define CAN_F12R1_FB5_Pos (5U)
4196 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4197 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4198 #define CAN_F12R1_FB6_Pos (6U)
4199 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4200 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4201 #define CAN_F12R1_FB7_Pos (7U)
4202 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4203 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4204 #define CAN_F12R1_FB8_Pos (8U)
4205 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4206 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4207 #define CAN_F12R1_FB9_Pos (9U)
4208 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4209 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4210 #define CAN_F12R1_FB10_Pos (10U)
4211 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4212 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4213 #define CAN_F12R1_FB11_Pos (11U)
4214 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4215 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4216 #define CAN_F12R1_FB12_Pos (12U)
4217 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4218 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4219 #define CAN_F12R1_FB13_Pos (13U)
4220 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4221 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4222 #define CAN_F12R1_FB14_Pos (14U)
4223 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4224 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4225 #define CAN_F12R1_FB15_Pos (15U)
4226 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4227 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4228 #define CAN_F12R1_FB16_Pos (16U)
4229 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4230 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4231 #define CAN_F12R1_FB17_Pos (17U)
4232 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4233 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4234 #define CAN_F12R1_FB18_Pos (18U)
4235 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4236 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4237 #define CAN_F12R1_FB19_Pos (19U)
4238 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4239 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4240 #define CAN_F12R1_FB20_Pos (20U)
4241 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4242 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4243 #define CAN_F12R1_FB21_Pos (21U)
4244 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4245 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4246 #define CAN_F12R1_FB22_Pos (22U)
4247 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4248 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4249 #define CAN_F12R1_FB23_Pos (23U)
4250 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4251 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4252 #define CAN_F12R1_FB24_Pos (24U)
4253 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4254 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4255 #define CAN_F12R1_FB25_Pos (25U)
4256 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4257 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4258 #define CAN_F12R1_FB26_Pos (26U)
4259 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4260 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4261 #define CAN_F12R1_FB27_Pos (27U)
4262 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4263 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4264 #define CAN_F12R1_FB28_Pos (28U)
4265 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4266 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4267 #define CAN_F12R1_FB29_Pos (29U)
4268 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4269 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4270 #define CAN_F12R1_FB30_Pos (30U)
4271 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4272 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4273 #define CAN_F12R1_FB31_Pos (31U)
4274 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4275 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4276
4277 /******************* Bit definition for CAN_F13R1 register ******************/
4278 #define CAN_F13R1_FB0_Pos (0U)
4279 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4280 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4281 #define CAN_F13R1_FB1_Pos (1U)
4282 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4283 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4284 #define CAN_F13R1_FB2_Pos (2U)
4285 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4286 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4287 #define CAN_F13R1_FB3_Pos (3U)
4288 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4289 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4290 #define CAN_F13R1_FB4_Pos (4U)
4291 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4292 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4293 #define CAN_F13R1_FB5_Pos (5U)
4294 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4295 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4296 #define CAN_F13R1_FB6_Pos (6U)
4297 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4298 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4299 #define CAN_F13R1_FB7_Pos (7U)
4300 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4301 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4302 #define CAN_F13R1_FB8_Pos (8U)
4303 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4304 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4305 #define CAN_F13R1_FB9_Pos (9U)
4306 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4307 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4308 #define CAN_F13R1_FB10_Pos (10U)
4309 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4310 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4311 #define CAN_F13R1_FB11_Pos (11U)
4312 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4313 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4314 #define CAN_F13R1_FB12_Pos (12U)
4315 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4316 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4317 #define CAN_F13R1_FB13_Pos (13U)
4318 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4319 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4320 #define CAN_F13R1_FB14_Pos (14U)
4321 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4322 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4323 #define CAN_F13R1_FB15_Pos (15U)
4324 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4325 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4326 #define CAN_F13R1_FB16_Pos (16U)
4327 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4328 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4329 #define CAN_F13R1_FB17_Pos (17U)
4330 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4331 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4332 #define CAN_F13R1_FB18_Pos (18U)
4333 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4334 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4335 #define CAN_F13R1_FB19_Pos (19U)
4336 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4337 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4338 #define CAN_F13R1_FB20_Pos (20U)
4339 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4340 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4341 #define CAN_F13R1_FB21_Pos (21U)
4342 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4343 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4344 #define CAN_F13R1_FB22_Pos (22U)
4345 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4346 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4347 #define CAN_F13R1_FB23_Pos (23U)
4348 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4349 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4350 #define CAN_F13R1_FB24_Pos (24U)
4351 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4352 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4353 #define CAN_F13R1_FB25_Pos (25U)
4354 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4355 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4356 #define CAN_F13R1_FB26_Pos (26U)
4357 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4358 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4359 #define CAN_F13R1_FB27_Pos (27U)
4360 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4361 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4362 #define CAN_F13R1_FB28_Pos (28U)
4363 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4364 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4365 #define CAN_F13R1_FB29_Pos (29U)
4366 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4367 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4368 #define CAN_F13R1_FB30_Pos (30U)
4369 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4370 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4371 #define CAN_F13R1_FB31_Pos (31U)
4372 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4373 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4374
4375 /******************* Bit definition for CAN_F0R2 register *******************/
4376 #define CAN_F0R2_FB0_Pos (0U)
4377 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4378 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4379 #define CAN_F0R2_FB1_Pos (1U)
4380 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4381 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4382 #define CAN_F0R2_FB2_Pos (2U)
4383 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4384 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4385 #define CAN_F0R2_FB3_Pos (3U)
4386 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4387 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4388 #define CAN_F0R2_FB4_Pos (4U)
4389 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4390 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4391 #define CAN_F0R2_FB5_Pos (5U)
4392 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4393 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4394 #define CAN_F0R2_FB6_Pos (6U)
4395 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4396 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4397 #define CAN_F0R2_FB7_Pos (7U)
4398 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4399 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4400 #define CAN_F0R2_FB8_Pos (8U)
4401 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4402 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4403 #define CAN_F0R2_FB9_Pos (9U)
4404 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4405 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4406 #define CAN_F0R2_FB10_Pos (10U)
4407 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4408 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4409 #define CAN_F0R2_FB11_Pos (11U)
4410 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4411 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4412 #define CAN_F0R2_FB12_Pos (12U)
4413 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4414 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4415 #define CAN_F0R2_FB13_Pos (13U)
4416 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4417 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4418 #define CAN_F0R2_FB14_Pos (14U)
4419 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4420 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4421 #define CAN_F0R2_FB15_Pos (15U)
4422 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4423 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4424 #define CAN_F0R2_FB16_Pos (16U)
4425 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4426 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4427 #define CAN_F0R2_FB17_Pos (17U)
4428 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4429 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4430 #define CAN_F0R2_FB18_Pos (18U)
4431 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4432 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4433 #define CAN_F0R2_FB19_Pos (19U)
4434 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4435 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4436 #define CAN_F0R2_FB20_Pos (20U)
4437 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4438 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4439 #define CAN_F0R2_FB21_Pos (21U)
4440 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4441 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4442 #define CAN_F0R2_FB22_Pos (22U)
4443 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4444 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4445 #define CAN_F0R2_FB23_Pos (23U)
4446 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4447 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4448 #define CAN_F0R2_FB24_Pos (24U)
4449 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4450 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4451 #define CAN_F0R2_FB25_Pos (25U)
4452 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4453 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4454 #define CAN_F0R2_FB26_Pos (26U)
4455 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4456 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4457 #define CAN_F0R2_FB27_Pos (27U)
4458 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4459 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4460 #define CAN_F0R2_FB28_Pos (28U)
4461 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4462 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4463 #define CAN_F0R2_FB29_Pos (29U)
4464 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4465 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4466 #define CAN_F0R2_FB30_Pos (30U)
4467 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4468 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4469 #define CAN_F0R2_FB31_Pos (31U)
4470 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4471 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4472
4473 /******************* Bit definition for CAN_F1R2 register *******************/
4474 #define CAN_F1R2_FB0_Pos (0U)
4475 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4476 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4477 #define CAN_F1R2_FB1_Pos (1U)
4478 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4479 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4480 #define CAN_F1R2_FB2_Pos (2U)
4481 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4482 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4483 #define CAN_F1R2_FB3_Pos (3U)
4484 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4485 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4486 #define CAN_F1R2_FB4_Pos (4U)
4487 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4488 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4489 #define CAN_F1R2_FB5_Pos (5U)
4490 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4491 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4492 #define CAN_F1R2_FB6_Pos (6U)
4493 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4494 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4495 #define CAN_F1R2_FB7_Pos (7U)
4496 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4497 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4498 #define CAN_F1R2_FB8_Pos (8U)
4499 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4500 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4501 #define CAN_F1R2_FB9_Pos (9U)
4502 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4503 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4504 #define CAN_F1R2_FB10_Pos (10U)
4505 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4506 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4507 #define CAN_F1R2_FB11_Pos (11U)
4508 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4509 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4510 #define CAN_F1R2_FB12_Pos (12U)
4511 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4512 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4513 #define CAN_F1R2_FB13_Pos (13U)
4514 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4515 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4516 #define CAN_F1R2_FB14_Pos (14U)
4517 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4518 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4519 #define CAN_F1R2_FB15_Pos (15U)
4520 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4521 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4522 #define CAN_F1R2_FB16_Pos (16U)
4523 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4524 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4525 #define CAN_F1R2_FB17_Pos (17U)
4526 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4527 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4528 #define CAN_F1R2_FB18_Pos (18U)
4529 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4530 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4531 #define CAN_F1R2_FB19_Pos (19U)
4532 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4533 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4534 #define CAN_F1R2_FB20_Pos (20U)
4535 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4536 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4537 #define CAN_F1R2_FB21_Pos (21U)
4538 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4539 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4540 #define CAN_F1R2_FB22_Pos (22U)
4541 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4542 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4543 #define CAN_F1R2_FB23_Pos (23U)
4544 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4545 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4546 #define CAN_F1R2_FB24_Pos (24U)
4547 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4548 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4549 #define CAN_F1R2_FB25_Pos (25U)
4550 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4551 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4552 #define CAN_F1R2_FB26_Pos (26U)
4553 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4554 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4555 #define CAN_F1R2_FB27_Pos (27U)
4556 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4557 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4558 #define CAN_F1R2_FB28_Pos (28U)
4559 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4560 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4561 #define CAN_F1R2_FB29_Pos (29U)
4562 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4563 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4564 #define CAN_F1R2_FB30_Pos (30U)
4565 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4566 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4567 #define CAN_F1R2_FB31_Pos (31U)
4568 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4569 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4570
4571 /******************* Bit definition for CAN_F2R2 register *******************/
4572 #define CAN_F2R2_FB0_Pos (0U)
4573 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4574 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4575 #define CAN_F2R2_FB1_Pos (1U)
4576 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4577 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4578 #define CAN_F2R2_FB2_Pos (2U)
4579 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4580 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4581 #define CAN_F2R2_FB3_Pos (3U)
4582 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4583 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4584 #define CAN_F2R2_FB4_Pos (4U)
4585 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4586 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4587 #define CAN_F2R2_FB5_Pos (5U)
4588 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4589 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4590 #define CAN_F2R2_FB6_Pos (6U)
4591 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4592 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4593 #define CAN_F2R2_FB7_Pos (7U)
4594 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4595 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4596 #define CAN_F2R2_FB8_Pos (8U)
4597 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4598 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4599 #define CAN_F2R2_FB9_Pos (9U)
4600 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4601 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4602 #define CAN_F2R2_FB10_Pos (10U)
4603 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4604 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4605 #define CAN_F2R2_FB11_Pos (11U)
4606 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4607 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4608 #define CAN_F2R2_FB12_Pos (12U)
4609 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4610 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4611 #define CAN_F2R2_FB13_Pos (13U)
4612 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4613 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4614 #define CAN_F2R2_FB14_Pos (14U)
4615 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4616 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4617 #define CAN_F2R2_FB15_Pos (15U)
4618 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4619 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4620 #define CAN_F2R2_FB16_Pos (16U)
4621 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4622 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4623 #define CAN_F2R2_FB17_Pos (17U)
4624 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4625 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4626 #define CAN_F2R2_FB18_Pos (18U)
4627 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4628 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4629 #define CAN_F2R2_FB19_Pos (19U)
4630 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4631 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4632 #define CAN_F2R2_FB20_Pos (20U)
4633 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4634 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4635 #define CAN_F2R2_FB21_Pos (21U)
4636 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4637 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4638 #define CAN_F2R2_FB22_Pos (22U)
4639 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4640 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4641 #define CAN_F2R2_FB23_Pos (23U)
4642 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4643 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4644 #define CAN_F2R2_FB24_Pos (24U)
4645 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4646 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4647 #define CAN_F2R2_FB25_Pos (25U)
4648 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4649 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4650 #define CAN_F2R2_FB26_Pos (26U)
4651 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4652 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4653 #define CAN_F2R2_FB27_Pos (27U)
4654 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4655 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4656 #define CAN_F2R2_FB28_Pos (28U)
4657 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4658 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4659 #define CAN_F2R2_FB29_Pos (29U)
4660 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4661 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4662 #define CAN_F2R2_FB30_Pos (30U)
4663 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4664 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4665 #define CAN_F2R2_FB31_Pos (31U)
4666 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4667 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4668
4669 /******************* Bit definition for CAN_F3R2 register *******************/
4670 #define CAN_F3R2_FB0_Pos (0U)
4671 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4672 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4673 #define CAN_F3R2_FB1_Pos (1U)
4674 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4675 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4676 #define CAN_F3R2_FB2_Pos (2U)
4677 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4678 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4679 #define CAN_F3R2_FB3_Pos (3U)
4680 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4681 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4682 #define CAN_F3R2_FB4_Pos (4U)
4683 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4684 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4685 #define CAN_F3R2_FB5_Pos (5U)
4686 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4687 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4688 #define CAN_F3R2_FB6_Pos (6U)
4689 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4690 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4691 #define CAN_F3R2_FB7_Pos (7U)
4692 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4693 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4694 #define CAN_F3R2_FB8_Pos (8U)
4695 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4696 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4697 #define CAN_F3R2_FB9_Pos (9U)
4698 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4699 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4700 #define CAN_F3R2_FB10_Pos (10U)
4701 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4702 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4703 #define CAN_F3R2_FB11_Pos (11U)
4704 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4705 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4706 #define CAN_F3R2_FB12_Pos (12U)
4707 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4708 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4709 #define CAN_F3R2_FB13_Pos (13U)
4710 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4711 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4712 #define CAN_F3R2_FB14_Pos (14U)
4713 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4714 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4715 #define CAN_F3R2_FB15_Pos (15U)
4716 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4717 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4718 #define CAN_F3R2_FB16_Pos (16U)
4719 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4720 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4721 #define CAN_F3R2_FB17_Pos (17U)
4722 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4723 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4724 #define CAN_F3R2_FB18_Pos (18U)
4725 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4726 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4727 #define CAN_F3R2_FB19_Pos (19U)
4728 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4729 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4730 #define CAN_F3R2_FB20_Pos (20U)
4731 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4732 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4733 #define CAN_F3R2_FB21_Pos (21U)
4734 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4735 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4736 #define CAN_F3R2_FB22_Pos (22U)
4737 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4738 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4739 #define CAN_F3R2_FB23_Pos (23U)
4740 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4741 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4742 #define CAN_F3R2_FB24_Pos (24U)
4743 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4744 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4745 #define CAN_F3R2_FB25_Pos (25U)
4746 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4747 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4748 #define CAN_F3R2_FB26_Pos (26U)
4749 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4750 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4751 #define CAN_F3R2_FB27_Pos (27U)
4752 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4753 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4754 #define CAN_F3R2_FB28_Pos (28U)
4755 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4756 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4757 #define CAN_F3R2_FB29_Pos (29U)
4758 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4759 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4760 #define CAN_F3R2_FB30_Pos (30U)
4761 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4762 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4763 #define CAN_F3R2_FB31_Pos (31U)
4764 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4765 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4766
4767 /******************* Bit definition for CAN_F4R2 register *******************/
4768 #define CAN_F4R2_FB0_Pos (0U)
4769 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4770 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4771 #define CAN_F4R2_FB1_Pos (1U)
4772 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4773 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4774 #define CAN_F4R2_FB2_Pos (2U)
4775 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4776 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4777 #define CAN_F4R2_FB3_Pos (3U)
4778 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4779 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4780 #define CAN_F4R2_FB4_Pos (4U)
4781 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4782 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4783 #define CAN_F4R2_FB5_Pos (5U)
4784 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4785 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4786 #define CAN_F4R2_FB6_Pos (6U)
4787 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4788 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4789 #define CAN_F4R2_FB7_Pos (7U)
4790 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4791 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4792 #define CAN_F4R2_FB8_Pos (8U)
4793 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4794 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4795 #define CAN_F4R2_FB9_Pos (9U)
4796 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4797 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4798 #define CAN_F4R2_FB10_Pos (10U)
4799 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4800 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4801 #define CAN_F4R2_FB11_Pos (11U)
4802 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4803 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4804 #define CAN_F4R2_FB12_Pos (12U)
4805 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4806 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4807 #define CAN_F4R2_FB13_Pos (13U)
4808 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4809 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4810 #define CAN_F4R2_FB14_Pos (14U)
4811 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4812 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4813 #define CAN_F4R2_FB15_Pos (15U)
4814 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4815 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4816 #define CAN_F4R2_FB16_Pos (16U)
4817 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4818 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4819 #define CAN_F4R2_FB17_Pos (17U)
4820 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4821 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4822 #define CAN_F4R2_FB18_Pos (18U)
4823 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4824 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4825 #define CAN_F4R2_FB19_Pos (19U)
4826 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4827 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4828 #define CAN_F4R2_FB20_Pos (20U)
4829 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4830 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4831 #define CAN_F4R2_FB21_Pos (21U)
4832 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4833 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4834 #define CAN_F4R2_FB22_Pos (22U)
4835 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4836 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4837 #define CAN_F4R2_FB23_Pos (23U)
4838 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4839 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4840 #define CAN_F4R2_FB24_Pos (24U)
4841 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4842 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4843 #define CAN_F4R2_FB25_Pos (25U)
4844 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4845 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4846 #define CAN_F4R2_FB26_Pos (26U)
4847 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4848 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4849 #define CAN_F4R2_FB27_Pos (27U)
4850 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4851 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4852 #define CAN_F4R2_FB28_Pos (28U)
4853 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4854 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4855 #define CAN_F4R2_FB29_Pos (29U)
4856 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4857 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4858 #define CAN_F4R2_FB30_Pos (30U)
4859 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4860 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4861 #define CAN_F4R2_FB31_Pos (31U)
4862 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4863 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4864
4865 /******************* Bit definition for CAN_F5R2 register *******************/
4866 #define CAN_F5R2_FB0_Pos (0U)
4867 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4868 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4869 #define CAN_F5R2_FB1_Pos (1U)
4870 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4871 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4872 #define CAN_F5R2_FB2_Pos (2U)
4873 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4874 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4875 #define CAN_F5R2_FB3_Pos (3U)
4876 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4877 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4878 #define CAN_F5R2_FB4_Pos (4U)
4879 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4880 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4881 #define CAN_F5R2_FB5_Pos (5U)
4882 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4883 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4884 #define CAN_F5R2_FB6_Pos (6U)
4885 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4886 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4887 #define CAN_F5R2_FB7_Pos (7U)
4888 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4889 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4890 #define CAN_F5R2_FB8_Pos (8U)
4891 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4892 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4893 #define CAN_F5R2_FB9_Pos (9U)
4894 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4895 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4896 #define CAN_F5R2_FB10_Pos (10U)
4897 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4898 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4899 #define CAN_F5R2_FB11_Pos (11U)
4900 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4901 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4902 #define CAN_F5R2_FB12_Pos (12U)
4903 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4904 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4905 #define CAN_F5R2_FB13_Pos (13U)
4906 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4907 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4908 #define CAN_F5R2_FB14_Pos (14U)
4909 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4910 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4911 #define CAN_F5R2_FB15_Pos (15U)
4912 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4913 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4914 #define CAN_F5R2_FB16_Pos (16U)
4915 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4916 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4917 #define CAN_F5R2_FB17_Pos (17U)
4918 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4919 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4920 #define CAN_F5R2_FB18_Pos (18U)
4921 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4922 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4923 #define CAN_F5R2_FB19_Pos (19U)
4924 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4925 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4926 #define CAN_F5R2_FB20_Pos (20U)
4927 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4928 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4929 #define CAN_F5R2_FB21_Pos (21U)
4930 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4931 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4932 #define CAN_F5R2_FB22_Pos (22U)
4933 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4934 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4935 #define CAN_F5R2_FB23_Pos (23U)
4936 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4937 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4938 #define CAN_F5R2_FB24_Pos (24U)
4939 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4940 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4941 #define CAN_F5R2_FB25_Pos (25U)
4942 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4943 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4944 #define CAN_F5R2_FB26_Pos (26U)
4945 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4946 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4947 #define CAN_F5R2_FB27_Pos (27U)
4948 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4949 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4950 #define CAN_F5R2_FB28_Pos (28U)
4951 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4952 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4953 #define CAN_F5R2_FB29_Pos (29U)
4954 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4955 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4956 #define CAN_F5R2_FB30_Pos (30U)
4957 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4958 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4959 #define CAN_F5R2_FB31_Pos (31U)
4960 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4961 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4962
4963 /******************* Bit definition for CAN_F6R2 register *******************/
4964 #define CAN_F6R2_FB0_Pos (0U)
4965 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4966 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4967 #define CAN_F6R2_FB1_Pos (1U)
4968 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4969 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4970 #define CAN_F6R2_FB2_Pos (2U)
4971 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4972 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4973 #define CAN_F6R2_FB3_Pos (3U)
4974 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4975 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4976 #define CAN_F6R2_FB4_Pos (4U)
4977 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4978 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4979 #define CAN_F6R2_FB5_Pos (5U)
4980 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4981 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4982 #define CAN_F6R2_FB6_Pos (6U)
4983 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4984 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4985 #define CAN_F6R2_FB7_Pos (7U)
4986 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4987 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4988 #define CAN_F6R2_FB8_Pos (8U)
4989 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4990 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4991 #define CAN_F6R2_FB9_Pos (9U)
4992 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4993 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4994 #define CAN_F6R2_FB10_Pos (10U)
4995 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4996 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4997 #define CAN_F6R2_FB11_Pos (11U)
4998 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4999 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
5000 #define CAN_F6R2_FB12_Pos (12U)
5001 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
5002 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
5003 #define CAN_F6R2_FB13_Pos (13U)
5004 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
5005 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
5006 #define CAN_F6R2_FB14_Pos (14U)
5007 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
5008 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
5009 #define CAN_F6R2_FB15_Pos (15U)
5010 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
5011 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
5012 #define CAN_F6R2_FB16_Pos (16U)
5013 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
5014 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
5015 #define CAN_F6R2_FB17_Pos (17U)
5016 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
5017 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
5018 #define CAN_F6R2_FB18_Pos (18U)
5019 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
5020 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
5021 #define CAN_F6R2_FB19_Pos (19U)
5022 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
5023 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
5024 #define CAN_F6R2_FB20_Pos (20U)
5025 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
5026 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
5027 #define CAN_F6R2_FB21_Pos (21U)
5028 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
5029 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
5030 #define CAN_F6R2_FB22_Pos (22U)
5031 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
5032 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
5033 #define CAN_F6R2_FB23_Pos (23U)
5034 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
5035 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
5036 #define CAN_F6R2_FB24_Pos (24U)
5037 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
5038 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
5039 #define CAN_F6R2_FB25_Pos (25U)
5040 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
5041 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
5042 #define CAN_F6R2_FB26_Pos (26U)
5043 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
5044 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
5045 #define CAN_F6R2_FB27_Pos (27U)
5046 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
5047 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
5048 #define CAN_F6R2_FB28_Pos (28U)
5049 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
5050 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
5051 #define CAN_F6R2_FB29_Pos (29U)
5052 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
5053 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
5054 #define CAN_F6R2_FB30_Pos (30U)
5055 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
5056 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
5057 #define CAN_F6R2_FB31_Pos (31U)
5058 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
5059 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
5060
5061 /******************* Bit definition for CAN_F7R2 register *******************/
5062 #define CAN_F7R2_FB0_Pos (0U)
5063 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
5064 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
5065 #define CAN_F7R2_FB1_Pos (1U)
5066 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
5067 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
5068 #define CAN_F7R2_FB2_Pos (2U)
5069 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
5070 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
5071 #define CAN_F7R2_FB3_Pos (3U)
5072 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
5073 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
5074 #define CAN_F7R2_FB4_Pos (4U)
5075 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5076 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5077 #define CAN_F7R2_FB5_Pos (5U)
5078 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5079 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5080 #define CAN_F7R2_FB6_Pos (6U)
5081 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5082 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5083 #define CAN_F7R2_FB7_Pos (7U)
5084 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5085 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5086 #define CAN_F7R2_FB8_Pos (8U)
5087 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5088 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5089 #define CAN_F7R2_FB9_Pos (9U)
5090 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5091 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5092 #define CAN_F7R2_FB10_Pos (10U)
5093 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5094 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5095 #define CAN_F7R2_FB11_Pos (11U)
5096 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5097 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5098 #define CAN_F7R2_FB12_Pos (12U)
5099 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5100 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5101 #define CAN_F7R2_FB13_Pos (13U)
5102 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5103 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5104 #define CAN_F7R2_FB14_Pos (14U)
5105 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5106 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5107 #define CAN_F7R2_FB15_Pos (15U)
5108 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5109 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5110 #define CAN_F7R2_FB16_Pos (16U)
5111 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5112 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5113 #define CAN_F7R2_FB17_Pos (17U)
5114 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5115 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5116 #define CAN_F7R2_FB18_Pos (18U)
5117 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5118 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5119 #define CAN_F7R2_FB19_Pos (19U)
5120 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5121 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5122 #define CAN_F7R2_FB20_Pos (20U)
5123 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5124 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5125 #define CAN_F7R2_FB21_Pos (21U)
5126 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5127 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5128 #define CAN_F7R2_FB22_Pos (22U)
5129 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5130 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5131 #define CAN_F7R2_FB23_Pos (23U)
5132 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5133 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5134 #define CAN_F7R2_FB24_Pos (24U)
5135 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5136 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5137 #define CAN_F7R2_FB25_Pos (25U)
5138 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5139 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5140 #define CAN_F7R2_FB26_Pos (26U)
5141 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5142 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5143 #define CAN_F7R2_FB27_Pos (27U)
5144 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5145 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5146 #define CAN_F7R2_FB28_Pos (28U)
5147 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5148 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5149 #define CAN_F7R2_FB29_Pos (29U)
5150 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5151 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5152 #define CAN_F7R2_FB30_Pos (30U)
5153 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5154 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5155 #define CAN_F7R2_FB31_Pos (31U)
5156 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5157 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5158
5159 /******************* Bit definition for CAN_F8R2 register *******************/
5160 #define CAN_F8R2_FB0_Pos (0U)
5161 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5162 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5163 #define CAN_F8R2_FB1_Pos (1U)
5164 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5165 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5166 #define CAN_F8R2_FB2_Pos (2U)
5167 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5168 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5169 #define CAN_F8R2_FB3_Pos (3U)
5170 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5171 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5172 #define CAN_F8R2_FB4_Pos (4U)
5173 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5174 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5175 #define CAN_F8R2_FB5_Pos (5U)
5176 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5177 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5178 #define CAN_F8R2_FB6_Pos (6U)
5179 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5180 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5181 #define CAN_F8R2_FB7_Pos (7U)
5182 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5183 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5184 #define CAN_F8R2_FB8_Pos (8U)
5185 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5186 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5187 #define CAN_F8R2_FB9_Pos (9U)
5188 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5189 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5190 #define CAN_F8R2_FB10_Pos (10U)
5191 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5192 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5193 #define CAN_F8R2_FB11_Pos (11U)
5194 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5195 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5196 #define CAN_F8R2_FB12_Pos (12U)
5197 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5198 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5199 #define CAN_F8R2_FB13_Pos (13U)
5200 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5201 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5202 #define CAN_F8R2_FB14_Pos (14U)
5203 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5204 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5205 #define CAN_F8R2_FB15_Pos (15U)
5206 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5207 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5208 #define CAN_F8R2_FB16_Pos (16U)
5209 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5210 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5211 #define CAN_F8R2_FB17_Pos (17U)
5212 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5213 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5214 #define CAN_F8R2_FB18_Pos (18U)
5215 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5216 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5217 #define CAN_F8R2_FB19_Pos (19U)
5218 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5219 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5220 #define CAN_F8R2_FB20_Pos (20U)
5221 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5222 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5223 #define CAN_F8R2_FB21_Pos (21U)
5224 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5225 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5226 #define CAN_F8R2_FB22_Pos (22U)
5227 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5228 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5229 #define CAN_F8R2_FB23_Pos (23U)
5230 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5231 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5232 #define CAN_F8R2_FB24_Pos (24U)
5233 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5234 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5235 #define CAN_F8R2_FB25_Pos (25U)
5236 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5237 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5238 #define CAN_F8R2_FB26_Pos (26U)
5239 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5240 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5241 #define CAN_F8R2_FB27_Pos (27U)
5242 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5243 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5244 #define CAN_F8R2_FB28_Pos (28U)
5245 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5246 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5247 #define CAN_F8R2_FB29_Pos (29U)
5248 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5249 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5250 #define CAN_F8R2_FB30_Pos (30U)
5251 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5252 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5253 #define CAN_F8R2_FB31_Pos (31U)
5254 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5255 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5256
5257 /******************* Bit definition for CAN_F9R2 register *******************/
5258 #define CAN_F9R2_FB0_Pos (0U)
5259 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5260 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5261 #define CAN_F9R2_FB1_Pos (1U)
5262 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5263 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5264 #define CAN_F9R2_FB2_Pos (2U)
5265 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5266 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5267 #define CAN_F9R2_FB3_Pos (3U)
5268 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5269 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5270 #define CAN_F9R2_FB4_Pos (4U)
5271 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5272 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5273 #define CAN_F9R2_FB5_Pos (5U)
5274 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5275 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5276 #define CAN_F9R2_FB6_Pos (6U)
5277 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5278 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5279 #define CAN_F9R2_FB7_Pos (7U)
5280 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5281 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5282 #define CAN_F9R2_FB8_Pos (8U)
5283 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5284 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5285 #define CAN_F9R2_FB9_Pos (9U)
5286 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5287 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5288 #define CAN_F9R2_FB10_Pos (10U)
5289 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5290 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5291 #define CAN_F9R2_FB11_Pos (11U)
5292 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5293 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5294 #define CAN_F9R2_FB12_Pos (12U)
5295 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5296 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5297 #define CAN_F9R2_FB13_Pos (13U)
5298 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5299 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5300 #define CAN_F9R2_FB14_Pos (14U)
5301 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5302 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5303 #define CAN_F9R2_FB15_Pos (15U)
5304 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5305 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5306 #define CAN_F9R2_FB16_Pos (16U)
5307 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5308 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5309 #define CAN_F9R2_FB17_Pos (17U)
5310 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5311 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5312 #define CAN_F9R2_FB18_Pos (18U)
5313 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5314 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5315 #define CAN_F9R2_FB19_Pos (19U)
5316 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5317 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5318 #define CAN_F9R2_FB20_Pos (20U)
5319 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5320 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5321 #define CAN_F9R2_FB21_Pos (21U)
5322 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5323 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5324 #define CAN_F9R2_FB22_Pos (22U)
5325 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5326 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5327 #define CAN_F9R2_FB23_Pos (23U)
5328 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5329 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5330 #define CAN_F9R2_FB24_Pos (24U)
5331 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5332 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5333 #define CAN_F9R2_FB25_Pos (25U)
5334 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5335 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5336 #define CAN_F9R2_FB26_Pos (26U)
5337 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5338 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5339 #define CAN_F9R2_FB27_Pos (27U)
5340 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5341 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5342 #define CAN_F9R2_FB28_Pos (28U)
5343 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5344 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5345 #define CAN_F9R2_FB29_Pos (29U)
5346 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5347 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5348 #define CAN_F9R2_FB30_Pos (30U)
5349 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5350 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5351 #define CAN_F9R2_FB31_Pos (31U)
5352 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5353 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5354
5355 /******************* Bit definition for CAN_F10R2 register ******************/
5356 #define CAN_F10R2_FB0_Pos (0U)
5357 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5358 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5359 #define CAN_F10R2_FB1_Pos (1U)
5360 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5361 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5362 #define CAN_F10R2_FB2_Pos (2U)
5363 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5364 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5365 #define CAN_F10R2_FB3_Pos (3U)
5366 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5367 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5368 #define CAN_F10R2_FB4_Pos (4U)
5369 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5370 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5371 #define CAN_F10R2_FB5_Pos (5U)
5372 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5373 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5374 #define CAN_F10R2_FB6_Pos (6U)
5375 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5376 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5377 #define CAN_F10R2_FB7_Pos (7U)
5378 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5379 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5380 #define CAN_F10R2_FB8_Pos (8U)
5381 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5382 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5383 #define CAN_F10R2_FB9_Pos (9U)
5384 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5385 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5386 #define CAN_F10R2_FB10_Pos (10U)
5387 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5388 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5389 #define CAN_F10R2_FB11_Pos (11U)
5390 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5391 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5392 #define CAN_F10R2_FB12_Pos (12U)
5393 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5394 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5395 #define CAN_F10R2_FB13_Pos (13U)
5396 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5397 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5398 #define CAN_F10R2_FB14_Pos (14U)
5399 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5400 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5401 #define CAN_F10R2_FB15_Pos (15U)
5402 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5403 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5404 #define CAN_F10R2_FB16_Pos (16U)
5405 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5406 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5407 #define CAN_F10R2_FB17_Pos (17U)
5408 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5409 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5410 #define CAN_F10R2_FB18_Pos (18U)
5411 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5412 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5413 #define CAN_F10R2_FB19_Pos (19U)
5414 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5415 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5416 #define CAN_F10R2_FB20_Pos (20U)
5417 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5418 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5419 #define CAN_F10R2_FB21_Pos (21U)
5420 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5421 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5422 #define CAN_F10R2_FB22_Pos (22U)
5423 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5424 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5425 #define CAN_F10R2_FB23_Pos (23U)
5426 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5427 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5428 #define CAN_F10R2_FB24_Pos (24U)
5429 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5430 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5431 #define CAN_F10R2_FB25_Pos (25U)
5432 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5433 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5434 #define CAN_F10R2_FB26_Pos (26U)
5435 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5436 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5437 #define CAN_F10R2_FB27_Pos (27U)
5438 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5439 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5440 #define CAN_F10R2_FB28_Pos (28U)
5441 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5442 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5443 #define CAN_F10R2_FB29_Pos (29U)
5444 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5445 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5446 #define CAN_F10R2_FB30_Pos (30U)
5447 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5448 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5449 #define CAN_F10R2_FB31_Pos (31U)
5450 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5451 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5452
5453 /******************* Bit definition for CAN_F11R2 register ******************/
5454 #define CAN_F11R2_FB0_Pos (0U)
5455 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5456 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5457 #define CAN_F11R2_FB1_Pos (1U)
5458 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5459 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5460 #define CAN_F11R2_FB2_Pos (2U)
5461 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5462 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5463 #define CAN_F11R2_FB3_Pos (3U)
5464 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5465 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5466 #define CAN_F11R2_FB4_Pos (4U)
5467 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5468 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5469 #define CAN_F11R2_FB5_Pos (5U)
5470 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5471 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5472 #define CAN_F11R2_FB6_Pos (6U)
5473 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5474 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5475 #define CAN_F11R2_FB7_Pos (7U)
5476 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5477 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5478 #define CAN_F11R2_FB8_Pos (8U)
5479 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5480 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5481 #define CAN_F11R2_FB9_Pos (9U)
5482 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5483 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5484 #define CAN_F11R2_FB10_Pos (10U)
5485 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5486 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5487 #define CAN_F11R2_FB11_Pos (11U)
5488 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5489 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5490 #define CAN_F11R2_FB12_Pos (12U)
5491 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5492 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5493 #define CAN_F11R2_FB13_Pos (13U)
5494 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5495 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5496 #define CAN_F11R2_FB14_Pos (14U)
5497 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5498 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5499 #define CAN_F11R2_FB15_Pos (15U)
5500 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5501 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5502 #define CAN_F11R2_FB16_Pos (16U)
5503 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5504 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5505 #define CAN_F11R2_FB17_Pos (17U)
5506 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5507 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5508 #define CAN_F11R2_FB18_Pos (18U)
5509 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5510 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5511 #define CAN_F11R2_FB19_Pos (19U)
5512 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5513 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5514 #define CAN_F11R2_FB20_Pos (20U)
5515 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5516 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5517 #define CAN_F11R2_FB21_Pos (21U)
5518 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5519 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5520 #define CAN_F11R2_FB22_Pos (22U)
5521 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5522 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5523 #define CAN_F11R2_FB23_Pos (23U)
5524 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5525 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5526 #define CAN_F11R2_FB24_Pos (24U)
5527 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5528 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5529 #define CAN_F11R2_FB25_Pos (25U)
5530 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5531 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5532 #define CAN_F11R2_FB26_Pos (26U)
5533 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5534 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5535 #define CAN_F11R2_FB27_Pos (27U)
5536 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5537 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5538 #define CAN_F11R2_FB28_Pos (28U)
5539 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5540 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5541 #define CAN_F11R2_FB29_Pos (29U)
5542 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5543 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5544 #define CAN_F11R2_FB30_Pos (30U)
5545 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5546 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5547 #define CAN_F11R2_FB31_Pos (31U)
5548 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5549 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5550
5551 /******************* Bit definition for CAN_F12R2 register ******************/
5552 #define CAN_F12R2_FB0_Pos (0U)
5553 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5554 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5555 #define CAN_F12R2_FB1_Pos (1U)
5556 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5557 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5558 #define CAN_F12R2_FB2_Pos (2U)
5559 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5560 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5561 #define CAN_F12R2_FB3_Pos (3U)
5562 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5563 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5564 #define CAN_F12R2_FB4_Pos (4U)
5565 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5566 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5567 #define CAN_F12R2_FB5_Pos (5U)
5568 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5569 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5570 #define CAN_F12R2_FB6_Pos (6U)
5571 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5572 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5573 #define CAN_F12R2_FB7_Pos (7U)
5574 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5575 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5576 #define CAN_F12R2_FB8_Pos (8U)
5577 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5578 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5579 #define CAN_F12R2_FB9_Pos (9U)
5580 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5581 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5582 #define CAN_F12R2_FB10_Pos (10U)
5583 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5584 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5585 #define CAN_F12R2_FB11_Pos (11U)
5586 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5587 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5588 #define CAN_F12R2_FB12_Pos (12U)
5589 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5590 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5591 #define CAN_F12R2_FB13_Pos (13U)
5592 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5593 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5594 #define CAN_F12R2_FB14_Pos (14U)
5595 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5596 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5597 #define CAN_F12R2_FB15_Pos (15U)
5598 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5599 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5600 #define CAN_F12R2_FB16_Pos (16U)
5601 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5602 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5603 #define CAN_F12R2_FB17_Pos (17U)
5604 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5605 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5606 #define CAN_F12R2_FB18_Pos (18U)
5607 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5608 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5609 #define CAN_F12R2_FB19_Pos (19U)
5610 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5611 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5612 #define CAN_F12R2_FB20_Pos (20U)
5613 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5614 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5615 #define CAN_F12R2_FB21_Pos (21U)
5616 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5617 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5618 #define CAN_F12R2_FB22_Pos (22U)
5619 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5620 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5621 #define CAN_F12R2_FB23_Pos (23U)
5622 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5623 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5624 #define CAN_F12R2_FB24_Pos (24U)
5625 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5626 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5627 #define CAN_F12R2_FB25_Pos (25U)
5628 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5629 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5630 #define CAN_F12R2_FB26_Pos (26U)
5631 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5632 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5633 #define CAN_F12R2_FB27_Pos (27U)
5634 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5635 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5636 #define CAN_F12R2_FB28_Pos (28U)
5637 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5638 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5639 #define CAN_F12R2_FB29_Pos (29U)
5640 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5641 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5642 #define CAN_F12R2_FB30_Pos (30U)
5643 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5644 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5645 #define CAN_F12R2_FB31_Pos (31U)
5646 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5647 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5648
5649 /******************* Bit definition for CAN_F13R2 register ******************/
5650 #define CAN_F13R2_FB0_Pos (0U)
5651 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5652 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5653 #define CAN_F13R2_FB1_Pos (1U)
5654 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5655 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5656 #define CAN_F13R2_FB2_Pos (2U)
5657 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5658 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5659 #define CAN_F13R2_FB3_Pos (3U)
5660 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5661 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5662 #define CAN_F13R2_FB4_Pos (4U)
5663 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5664 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5665 #define CAN_F13R2_FB5_Pos (5U)
5666 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5667 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5668 #define CAN_F13R2_FB6_Pos (6U)
5669 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5670 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5671 #define CAN_F13R2_FB7_Pos (7U)
5672 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5673 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5674 #define CAN_F13R2_FB8_Pos (8U)
5675 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5676 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5677 #define CAN_F13R2_FB9_Pos (9U)
5678 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5679 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5680 #define CAN_F13R2_FB10_Pos (10U)
5681 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5682 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5683 #define CAN_F13R2_FB11_Pos (11U)
5684 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5685 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5686 #define CAN_F13R2_FB12_Pos (12U)
5687 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5688 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5689 #define CAN_F13R2_FB13_Pos (13U)
5690 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5691 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5692 #define CAN_F13R2_FB14_Pos (14U)
5693 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5694 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5695 #define CAN_F13R2_FB15_Pos (15U)
5696 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5697 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5698 #define CAN_F13R2_FB16_Pos (16U)
5699 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5700 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5701 #define CAN_F13R2_FB17_Pos (17U)
5702 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5703 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5704 #define CAN_F13R2_FB18_Pos (18U)
5705 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5706 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5707 #define CAN_F13R2_FB19_Pos (19U)
5708 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5709 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5710 #define CAN_F13R2_FB20_Pos (20U)
5711 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5712 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5713 #define CAN_F13R2_FB21_Pos (21U)
5714 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5715 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5716 #define CAN_F13R2_FB22_Pos (22U)
5717 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5718 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5719 #define CAN_F13R2_FB23_Pos (23U)
5720 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5721 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5722 #define CAN_F13R2_FB24_Pos (24U)
5723 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5724 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5725 #define CAN_F13R2_FB25_Pos (25U)
5726 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5727 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5728 #define CAN_F13R2_FB26_Pos (26U)
5729 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5730 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5731 #define CAN_F13R2_FB27_Pos (27U)
5732 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5733 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5734 #define CAN_F13R2_FB28_Pos (28U)
5735 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5736 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5737 #define CAN_F13R2_FB29_Pos (29U)
5738 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5739 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5740 #define CAN_F13R2_FB30_Pos (30U)
5741 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5742 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5743 #define CAN_F13R2_FB31_Pos (31U)
5744 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5745 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5746
5747 /******************************************************************************/
5748 /* */
5749 /* CRC calculation unit */
5750 /* */
5751 /******************************************************************************/
5752 /******************* Bit definition for CRC_DR register *********************/
5753 #define CRC_DR_DR_Pos (0U)
5754 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5755 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5756
5757
5758 /******************* Bit definition for CRC_IDR register ********************/
5759 #define CRC_IDR_IDR_Pos (0U)
5760 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5761 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5762
5763
5764 /******************** Bit definition for CRC_CR register ********************/
5765 #define CRC_CR_RESET_Pos (0U)
5766 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5767 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5768
5769 /******************************************************************************/
5770 /* */
5771 /* Crypto Processor */
5772 /* */
5773 /******************************************************************************/
5774 /******************* Bits definition for CRYP_CR register ********************/
5775 #define CRYP_CR_ALGODIR_Pos (2U)
5776 #define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
5777 #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5778
5779 #define CRYP_CR_ALGOMODE_Pos (3U)
5780 #define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
5781 #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5782 #define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
5783 #define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
5784 #define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
5785 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
5786 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5787 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5788 #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5789 #define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5790 #define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5791 #define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5792 #define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5793 #define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5794 #define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5795 #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5796 #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5797 #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5798 #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5799 #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5800 #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5801 #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5802 #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5803 #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5804 #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5805 #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5806 #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5807
5808 #define CRYP_CR_DATATYPE_Pos (6U)
5809 #define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
5810 #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5811 #define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
5812 #define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
5813 #define CRYP_CR_KEYSIZE_Pos (8U)
5814 #define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
5815 #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5816 #define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
5817 #define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
5818 #define CRYP_CR_FFLUSH_Pos (14U)
5819 #define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
5820 #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5821 #define CRYP_CR_CRYPEN_Pos (15U)
5822 #define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
5823 #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5824
5825 #define CRYP_CR_GCM_CCMPH_Pos (16U)
5826 #define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
5827 #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5828 #define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
5829 #define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
5830 #define CRYP_CR_ALGOMODE_3 0x00080000U
5831
5832 /****************** Bits definition for CRYP_SR register *********************/
5833 #define CRYP_SR_IFEM_Pos (0U)
5834 #define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
5835 #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5836 #define CRYP_SR_IFNF_Pos (1U)
5837 #define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
5838 #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5839 #define CRYP_SR_OFNE_Pos (2U)
5840 #define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
5841 #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5842 #define CRYP_SR_OFFU_Pos (3U)
5843 #define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
5844 #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5845 #define CRYP_SR_BUSY_Pos (4U)
5846 #define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
5847 #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5848 /****************** Bits definition for CRYP_DMACR register ******************/
5849 #define CRYP_DMACR_DIEN_Pos (0U)
5850 #define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
5851 #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5852 #define CRYP_DMACR_DOEN_Pos (1U)
5853 #define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
5854 #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5855 /***************** Bits definition for CRYP_IMSCR register ******************/
5856 #define CRYP_IMSCR_INIM_Pos (0U)
5857 #define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
5858 #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5859 #define CRYP_IMSCR_OUTIM_Pos (1U)
5860 #define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
5861 #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5862 /****************** Bits definition for CRYP_RISR register *******************/
5863 #define CRYP_RISR_OUTRIS_Pos (0U)
5864 #define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
5865 #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5866 #define CRYP_RISR_INRIS_Pos (1U)
5867 #define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
5868 #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5869 /****************** Bits definition for CRYP_MISR register *******************/
5870 #define CRYP_MISR_INMIS_Pos (0U)
5871 #define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
5872 #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5873 #define CRYP_MISR_OUTMIS_Pos (1U)
5874 #define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
5875 #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5876
5877 /******************************************************************************/
5878 /* */
5879 /* Digital to Analog Converter */
5880 /* */
5881 /******************************************************************************/
5882 /*
5883 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5884 */
5885 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5886 /******************** Bit definition for DAC_CR register ********************/
5887 #define DAC_CR_EN1_Pos (0U)
5888 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5889 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5890 #define DAC_CR_BOFF1_Pos (1U)
5891 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5892 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5893 #define DAC_CR_TEN1_Pos (2U)
5894 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5895 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5896
5897 #define DAC_CR_TSEL1_Pos (3U)
5898 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5899 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5900 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5901 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5902 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5903
5904 #define DAC_CR_WAVE1_Pos (6U)
5905 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5906 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5907 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5908 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5909
5910 #define DAC_CR_MAMP1_Pos (8U)
5911 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5912 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5913 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5914 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5915 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5916 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5917
5918 #define DAC_CR_DMAEN1_Pos (12U)
5919 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5920 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5921 #define DAC_CR_DMAUDRIE1_Pos (13U)
5922 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5923 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5924 #define DAC_CR_EN2_Pos (16U)
5925 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5926 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5927 #define DAC_CR_BOFF2_Pos (17U)
5928 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5929 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5930 #define DAC_CR_TEN2_Pos (18U)
5931 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5932 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5933
5934 #define DAC_CR_TSEL2_Pos (19U)
5935 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5936 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5937 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5938 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5939 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5940
5941 #define DAC_CR_WAVE2_Pos (22U)
5942 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5943 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5944 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5945 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5946
5947 #define DAC_CR_MAMP2_Pos (24U)
5948 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5949 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5950 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5951 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5952 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5953 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5954
5955 #define DAC_CR_DMAEN2_Pos (28U)
5956 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5957 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5958 #define DAC_CR_DMAUDRIE2_Pos (29U)
5959 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5960 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5961
5962 /***************** Bit definition for DAC_SWTRIGR register ******************/
5963 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5964 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5965 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5966 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5967 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5968 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5969
5970 /***************** Bit definition for DAC_DHR12R1 register ******************/
5971 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5972 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5973 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5974
5975 /***************** Bit definition for DAC_DHR12L1 register ******************/
5976 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5977 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5978 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5979
5980 /****************** Bit definition for DAC_DHR8R1 register ******************/
5981 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5982 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5983 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5984
5985 /***************** Bit definition for DAC_DHR12R2 register ******************/
5986 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5987 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5988 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5989
5990 /***************** Bit definition for DAC_DHR12L2 register ******************/
5991 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5992 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5993 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5994
5995 /****************** Bit definition for DAC_DHR8R2 register ******************/
5996 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5997 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5998 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5999
6000 /***************** Bit definition for DAC_DHR12RD register ******************/
6001 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
6002 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
6003 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6004 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
6005 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
6006 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6007
6008 /***************** Bit definition for DAC_DHR12LD register ******************/
6009 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
6010 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6011 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6012 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
6013 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
6014 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6015
6016 /****************** Bit definition for DAC_DHR8RD register ******************/
6017 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
6018 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
6019 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6020 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
6021 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
6022 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6023
6024 /******************* Bit definition for DAC_DOR1 register *******************/
6025 #define DAC_DOR1_DACC1DOR_Pos (0U)
6026 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
6027 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
6028
6029 /******************* Bit definition for DAC_DOR2 register *******************/
6030 #define DAC_DOR2_DACC2DOR_Pos (0U)
6031 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
6032 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
6033
6034 /******************** Bit definition for DAC_SR register ********************/
6035 #define DAC_SR_DMAUDR1_Pos (13U)
6036 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
6037 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
6038 #define DAC_SR_DMAUDR2_Pos (29U)
6039 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
6040 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
6041
6042 /******************************************************************************/
6043 /* */
6044 /* DCMI */
6045 /* */
6046 /******************************************************************************/
6047 /******************** Bits definition for DCMI_CR register ******************/
6048 #define DCMI_CR_CAPTURE_Pos (0U)
6049 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
6050 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6051 #define DCMI_CR_CM_Pos (1U)
6052 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
6053 #define DCMI_CR_CM DCMI_CR_CM_Msk
6054 #define DCMI_CR_CROP_Pos (2U)
6055 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
6056 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
6057 #define DCMI_CR_JPEG_Pos (3U)
6058 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
6059 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6060 #define DCMI_CR_ESS_Pos (4U)
6061 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
6062 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
6063 #define DCMI_CR_PCKPOL_Pos (5U)
6064 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
6065 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6066 #define DCMI_CR_HSPOL_Pos (6U)
6067 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
6068 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6069 #define DCMI_CR_VSPOL_Pos (7U)
6070 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
6071 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6072 #define DCMI_CR_FCRC_0 0x00000100U
6073 #define DCMI_CR_FCRC_1 0x00000200U
6074 #define DCMI_CR_EDM_0 0x00000400U
6075 #define DCMI_CR_EDM_1 0x00000800U
6076 #define DCMI_CR_OUTEN_Pos (13U)
6077 #define DCMI_CR_OUTEN_Msk (0x1U << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */
6078 #define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
6079 #define DCMI_CR_ENABLE_Pos (14U)
6080 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
6081 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6082 #define DCMI_CR_BSM_0 0x00010000U
6083 #define DCMI_CR_BSM_1 0x00020000U
6084 #define DCMI_CR_OEBS_Pos (18U)
6085 #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
6086 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6087 #define DCMI_CR_LSM_Pos (19U)
6088 #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
6089 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
6090 #define DCMI_CR_OELS_Pos (20U)
6091 #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
6092 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
6093
6094 /******************** Bits definition for DCMI_SR register ******************/
6095 #define DCMI_SR_HSYNC_Pos (0U)
6096 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
6097 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6098 #define DCMI_SR_VSYNC_Pos (1U)
6099 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
6100 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6101 #define DCMI_SR_FNE_Pos (2U)
6102 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
6103 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
6104
6105 /******************** Bits definition for DCMI_RIS register *****************/
6106 #define DCMI_RIS_FRAME_RIS_Pos (0U)
6107 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
6108 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6109 #define DCMI_RIS_OVR_RIS_Pos (1U)
6110 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
6111 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6112 #define DCMI_RIS_ERR_RIS_Pos (2U)
6113 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
6114 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6115 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
6116 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
6117 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6118 #define DCMI_RIS_LINE_RIS_Pos (4U)
6119 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
6120 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6121 /* Legacy defines */
6122 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
6123 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
6124 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
6125 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
6126 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
6127 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
6128
6129 /******************** Bits definition for DCMI_IER register *****************/
6130 #define DCMI_IER_FRAME_IE_Pos (0U)
6131 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
6132 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6133 #define DCMI_IER_OVR_IE_Pos (1U)
6134 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
6135 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6136 #define DCMI_IER_ERR_IE_Pos (2U)
6137 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
6138 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6139 #define DCMI_IER_VSYNC_IE_Pos (3U)
6140 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
6141 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6142 #define DCMI_IER_LINE_IE_Pos (4U)
6143 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
6144 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6145 /* Legacy defines */
6146 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
6147
6148 /******************** Bits definition for DCMI_MIS register *****************/
6149 #define DCMI_MIS_FRAME_MIS_Pos (0U)
6150 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
6151 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6152 #define DCMI_MIS_OVR_MIS_Pos (1U)
6153 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
6154 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6155 #define DCMI_MIS_ERR_MIS_Pos (2U)
6156 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
6157 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6158 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
6159 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6160 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6161 #define DCMI_MIS_LINE_MIS_Pos (4U)
6162 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6163 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6164
6165 /* Legacy defines */
6166 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
6167 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
6168 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
6169 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
6170 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
6171
6172 /******************** Bits definition for DCMI_ICR register *****************/
6173 #define DCMI_ICR_FRAME_ISC_Pos (0U)
6174 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6175 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6176 #define DCMI_ICR_OVR_ISC_Pos (1U)
6177 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6178 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6179 #define DCMI_ICR_ERR_ISC_Pos (2U)
6180 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6181 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6182 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
6183 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6184 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6185 #define DCMI_ICR_LINE_ISC_Pos (4U)
6186 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6187 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6188
6189 /* Legacy defines */
6190 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
6191
6192 /******************** Bits definition for DCMI_ESCR register ******************/
6193 #define DCMI_ESCR_FSC_Pos (0U)
6194 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6195 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6196 #define DCMI_ESCR_LSC_Pos (8U)
6197 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6198 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6199 #define DCMI_ESCR_LEC_Pos (16U)
6200 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6201 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6202 #define DCMI_ESCR_FEC_Pos (24U)
6203 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6204 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6205
6206 /******************** Bits definition for DCMI_ESUR register ******************/
6207 #define DCMI_ESUR_FSU_Pos (0U)
6208 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6209 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6210 #define DCMI_ESUR_LSU_Pos (8U)
6211 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6212 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6213 #define DCMI_ESUR_LEU_Pos (16U)
6214 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6215 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6216 #define DCMI_ESUR_FEU_Pos (24U)
6217 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6218 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6219
6220 /******************** Bits definition for DCMI_CWSTRT register ******************/
6221 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6222 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6223 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6224 #define DCMI_CWSTRT_VST_Pos (16U)
6225 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6226 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6227
6228 /******************** Bits definition for DCMI_CWSIZE register ******************/
6229 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
6230 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6231 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6232 #define DCMI_CWSIZE_VLINE_Pos (16U)
6233 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6234 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6235
6236 /******************** Bits definition for DCMI_DR register *********************/
6237 #define DCMI_DR_BYTE0_Pos (0U)
6238 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6239 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6240 #define DCMI_DR_BYTE1_Pos (8U)
6241 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6242 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6243 #define DCMI_DR_BYTE2_Pos (16U)
6244 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6245 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6246 #define DCMI_DR_BYTE3_Pos (24U)
6247 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6248 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6249
6250 /******************************************************************************/
6251 /* */
6252 /* DMA Controller */
6253 /* */
6254 /******************************************************************************/
6255 /******************** Bits definition for DMA_SxCR register *****************/
6256 #define DMA_SxCR_CHSEL_Pos (25U)
6257 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
6258 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6259 #define DMA_SxCR_CHSEL_0 0x02000000U
6260 #define DMA_SxCR_CHSEL_1 0x04000000U
6261 #define DMA_SxCR_CHSEL_2 0x08000000U
6262 #define DMA_SxCR_MBURST_Pos (23U)
6263 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
6264 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6265 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6266 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6267 #define DMA_SxCR_PBURST_Pos (21U)
6268 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6269 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6270 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6271 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6272 #define DMA_SxCR_CT_Pos (19U)
6273 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6274 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
6275 #define DMA_SxCR_DBM_Pos (18U)
6276 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6277 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6278 #define DMA_SxCR_PL_Pos (16U)
6279 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6280 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
6281 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6282 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6283 #define DMA_SxCR_PINCOS_Pos (15U)
6284 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6285 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6286 #define DMA_SxCR_MSIZE_Pos (13U)
6287 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6288 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6289 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6290 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6291 #define DMA_SxCR_PSIZE_Pos (11U)
6292 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6293 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6294 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6295 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6296 #define DMA_SxCR_MINC_Pos (10U)
6297 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6298 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6299 #define DMA_SxCR_PINC_Pos (9U)
6300 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6301 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6302 #define DMA_SxCR_CIRC_Pos (8U)
6303 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6304 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6305 #define DMA_SxCR_DIR_Pos (6U)
6306 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6307 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6308 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6309 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6310 #define DMA_SxCR_PFCTRL_Pos (5U)
6311 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6312 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6313 #define DMA_SxCR_TCIE_Pos (4U)
6314 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6315 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6316 #define DMA_SxCR_HTIE_Pos (3U)
6317 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6318 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6319 #define DMA_SxCR_TEIE_Pos (2U)
6320 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6321 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6322 #define DMA_SxCR_DMEIE_Pos (1U)
6323 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6324 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6325 #define DMA_SxCR_EN_Pos (0U)
6326 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6327 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
6328
6329 /* Legacy defines */
6330 #define DMA_SxCR_ACK_Pos (20U)
6331 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
6332 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6333
6334 /******************** Bits definition for DMA_SxCNDTR register **************/
6335 #define DMA_SxNDT_Pos (0U)
6336 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6337 #define DMA_SxNDT DMA_SxNDT_Msk
6338 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
6339 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
6340 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
6341 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
6342 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
6343 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
6344 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
6345 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
6346 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
6347 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
6348 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
6349 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
6350 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
6351 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
6352 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
6353 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
6354
6355 /******************** Bits definition for DMA_SxFCR register ****************/
6356 #define DMA_SxFCR_FEIE_Pos (7U)
6357 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6358 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6359 #define DMA_SxFCR_FS_Pos (3U)
6360 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6361 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6362 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6363 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6364 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6365 #define DMA_SxFCR_DMDIS_Pos (2U)
6366 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6367 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6368 #define DMA_SxFCR_FTH_Pos (0U)
6369 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6370 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6371 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6372 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6373
6374 /******************** Bits definition for DMA_LISR register *****************/
6375 #define DMA_LISR_TCIF3_Pos (27U)
6376 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6377 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6378 #define DMA_LISR_HTIF3_Pos (26U)
6379 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6380 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6381 #define DMA_LISR_TEIF3_Pos (25U)
6382 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6383 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6384 #define DMA_LISR_DMEIF3_Pos (24U)
6385 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6386 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6387 #define DMA_LISR_FEIF3_Pos (22U)
6388 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6389 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6390 #define DMA_LISR_TCIF2_Pos (21U)
6391 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6392 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6393 #define DMA_LISR_HTIF2_Pos (20U)
6394 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6395 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6396 #define DMA_LISR_TEIF2_Pos (19U)
6397 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6398 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6399 #define DMA_LISR_DMEIF2_Pos (18U)
6400 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6401 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6402 #define DMA_LISR_FEIF2_Pos (16U)
6403 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6404 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6405 #define DMA_LISR_TCIF1_Pos (11U)
6406 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6407 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6408 #define DMA_LISR_HTIF1_Pos (10U)
6409 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6410 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6411 #define DMA_LISR_TEIF1_Pos (9U)
6412 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6413 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6414 #define DMA_LISR_DMEIF1_Pos (8U)
6415 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6416 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6417 #define DMA_LISR_FEIF1_Pos (6U)
6418 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6419 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6420 #define DMA_LISR_TCIF0_Pos (5U)
6421 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6422 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6423 #define DMA_LISR_HTIF0_Pos (4U)
6424 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6425 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6426 #define DMA_LISR_TEIF0_Pos (3U)
6427 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6428 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6429 #define DMA_LISR_DMEIF0_Pos (2U)
6430 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6431 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6432 #define DMA_LISR_FEIF0_Pos (0U)
6433 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6434 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6435
6436 /******************** Bits definition for DMA_HISR register *****************/
6437 #define DMA_HISR_TCIF7_Pos (27U)
6438 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6439 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6440 #define DMA_HISR_HTIF7_Pos (26U)
6441 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6442 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6443 #define DMA_HISR_TEIF7_Pos (25U)
6444 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6445 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6446 #define DMA_HISR_DMEIF7_Pos (24U)
6447 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6448 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6449 #define DMA_HISR_FEIF7_Pos (22U)
6450 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6451 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6452 #define DMA_HISR_TCIF6_Pos (21U)
6453 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6454 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6455 #define DMA_HISR_HTIF6_Pos (20U)
6456 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6457 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6458 #define DMA_HISR_TEIF6_Pos (19U)
6459 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6460 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6461 #define DMA_HISR_DMEIF6_Pos (18U)
6462 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6463 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6464 #define DMA_HISR_FEIF6_Pos (16U)
6465 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6466 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6467 #define DMA_HISR_TCIF5_Pos (11U)
6468 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6469 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6470 #define DMA_HISR_HTIF5_Pos (10U)
6471 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6472 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6473 #define DMA_HISR_TEIF5_Pos (9U)
6474 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6475 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6476 #define DMA_HISR_DMEIF5_Pos (8U)
6477 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6478 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6479 #define DMA_HISR_FEIF5_Pos (6U)
6480 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6481 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6482 #define DMA_HISR_TCIF4_Pos (5U)
6483 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6484 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6485 #define DMA_HISR_HTIF4_Pos (4U)
6486 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6487 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6488 #define DMA_HISR_TEIF4_Pos (3U)
6489 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6490 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6491 #define DMA_HISR_DMEIF4_Pos (2U)
6492 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6493 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6494 #define DMA_HISR_FEIF4_Pos (0U)
6495 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6496 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6497
6498 /******************** Bits definition for DMA_LIFCR register ****************/
6499 #define DMA_LIFCR_CTCIF3_Pos (27U)
6500 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6501 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6502 #define DMA_LIFCR_CHTIF3_Pos (26U)
6503 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6504 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6505 #define DMA_LIFCR_CTEIF3_Pos (25U)
6506 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6507 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6508 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6509 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6510 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6511 #define DMA_LIFCR_CFEIF3_Pos (22U)
6512 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6513 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6514 #define DMA_LIFCR_CTCIF2_Pos (21U)
6515 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6516 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6517 #define DMA_LIFCR_CHTIF2_Pos (20U)
6518 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6519 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6520 #define DMA_LIFCR_CTEIF2_Pos (19U)
6521 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6522 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6523 #define DMA_LIFCR_CDMEIF2_Pos (18U)
6524 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6525 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6526 #define DMA_LIFCR_CFEIF2_Pos (16U)
6527 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6528 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6529 #define DMA_LIFCR_CTCIF1_Pos (11U)
6530 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6531 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6532 #define DMA_LIFCR_CHTIF1_Pos (10U)
6533 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6534 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6535 #define DMA_LIFCR_CTEIF1_Pos (9U)
6536 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6537 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6538 #define DMA_LIFCR_CDMEIF1_Pos (8U)
6539 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6540 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6541 #define DMA_LIFCR_CFEIF1_Pos (6U)
6542 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6543 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6544 #define DMA_LIFCR_CTCIF0_Pos (5U)
6545 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6546 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6547 #define DMA_LIFCR_CHTIF0_Pos (4U)
6548 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6549 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6550 #define DMA_LIFCR_CTEIF0_Pos (3U)
6551 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6552 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6553 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6554 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6555 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6556 #define DMA_LIFCR_CFEIF0_Pos (0U)
6557 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6558 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6559
6560 /******************** Bits definition for DMA_HIFCR register ****************/
6561 #define DMA_HIFCR_CTCIF7_Pos (27U)
6562 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6563 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6564 #define DMA_HIFCR_CHTIF7_Pos (26U)
6565 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6566 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6567 #define DMA_HIFCR_CTEIF7_Pos (25U)
6568 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6569 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6570 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6571 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6572 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6573 #define DMA_HIFCR_CFEIF7_Pos (22U)
6574 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6575 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6576 #define DMA_HIFCR_CTCIF6_Pos (21U)
6577 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6578 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6579 #define DMA_HIFCR_CHTIF6_Pos (20U)
6580 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6581 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6582 #define DMA_HIFCR_CTEIF6_Pos (19U)
6583 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6584 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6585 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6586 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6587 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6588 #define DMA_HIFCR_CFEIF6_Pos (16U)
6589 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6590 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6591 #define DMA_HIFCR_CTCIF5_Pos (11U)
6592 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6593 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6594 #define DMA_HIFCR_CHTIF5_Pos (10U)
6595 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6596 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6597 #define DMA_HIFCR_CTEIF5_Pos (9U)
6598 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6599 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6600 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6601 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6602 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6603 #define DMA_HIFCR_CFEIF5_Pos (6U)
6604 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6605 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6606 #define DMA_HIFCR_CTCIF4_Pos (5U)
6607 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6608 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6609 #define DMA_HIFCR_CHTIF4_Pos (4U)
6610 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6611 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6612 #define DMA_HIFCR_CTEIF4_Pos (3U)
6613 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6614 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6615 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6616 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6617 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6618 #define DMA_HIFCR_CFEIF4_Pos (0U)
6619 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6620 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6621
6622 /****************** Bit definition for DMA_SxPAR register ********************/
6623 #define DMA_SxPAR_PA_Pos (0U)
6624 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6625 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6626
6627 /****************** Bit definition for DMA_SxM0AR register ********************/
6628 #define DMA_SxM0AR_M0A_Pos (0U)
6629 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6630 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6631
6632 /****************** Bit definition for DMA_SxM1AR register ********************/
6633 #define DMA_SxM1AR_M1A_Pos (0U)
6634 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6635 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6636
6637
6638 /******************************************************************************/
6639 /* */
6640 /* AHB Master DMA2D Controller (DMA2D) */
6641 /* */
6642 /******************************************************************************/
6643
6644 /******************** Bit definition for DMA2D_CR register ******************/
6645
6646 #define DMA2D_CR_START_Pos (0U)
6647 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
6648 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
6649 #define DMA2D_CR_SUSP_Pos (1U)
6650 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
6651 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
6652 #define DMA2D_CR_ABORT_Pos (2U)
6653 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
6654 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
6655 #define DMA2D_CR_TEIE_Pos (8U)
6656 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
6657 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
6658 #define DMA2D_CR_TCIE_Pos (9U)
6659 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
6660 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
6661 #define DMA2D_CR_TWIE_Pos (10U)
6662 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
6663 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
6664 #define DMA2D_CR_CAEIE_Pos (11U)
6665 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
6666 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
6667 #define DMA2D_CR_CTCIE_Pos (12U)
6668 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
6669 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
6670 #define DMA2D_CR_CEIE_Pos (13U)
6671 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
6672 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
6673 #define DMA2D_CR_MODE_Pos (16U)
6674 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
6675 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
6676 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
6677 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
6678
6679 /******************** Bit definition for DMA2D_ISR register *****************/
6680
6681 #define DMA2D_ISR_TEIF_Pos (0U)
6682 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
6683 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
6684 #define DMA2D_ISR_TCIF_Pos (1U)
6685 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
6686 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
6687 #define DMA2D_ISR_TWIF_Pos (2U)
6688 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
6689 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
6690 #define DMA2D_ISR_CAEIF_Pos (3U)
6691 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
6692 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
6693 #define DMA2D_ISR_CTCIF_Pos (4U)
6694 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
6695 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
6696 #define DMA2D_ISR_CEIF_Pos (5U)
6697 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
6698 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
6699
6700 /******************** Bit definition for DMA2D_IFCR register ****************/
6701
6702 #define DMA2D_IFCR_CTEIF_Pos (0U)
6703 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
6704 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
6705 #define DMA2D_IFCR_CTCIF_Pos (1U)
6706 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
6707 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
6708 #define DMA2D_IFCR_CTWIF_Pos (2U)
6709 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
6710 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
6711 #define DMA2D_IFCR_CAECIF_Pos (3U)
6712 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
6713 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
6714 #define DMA2D_IFCR_CCTCIF_Pos (4U)
6715 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
6716 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
6717 #define DMA2D_IFCR_CCEIF_Pos (5U)
6718 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
6719 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
6720
6721 /* Legacy defines */
6722 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
6723 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
6724 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
6725 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
6726 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
6727 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
6728
6729 /******************** Bit definition for DMA2D_FGMAR register ***************/
6730
6731 #define DMA2D_FGMAR_MA_Pos (0U)
6732 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6733 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
6734
6735 /******************** Bit definition for DMA2D_FGOR register ****************/
6736
6737 #define DMA2D_FGOR_LO_Pos (0U)
6738 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
6739 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
6740
6741 /******************** Bit definition for DMA2D_BGMAR register ***************/
6742
6743 #define DMA2D_BGMAR_MA_Pos (0U)
6744 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6745 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
6746
6747 /******************** Bit definition for DMA2D_BGOR register ****************/
6748
6749 #define DMA2D_BGOR_LO_Pos (0U)
6750 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
6751 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
6752
6753 /******************** Bit definition for DMA2D_FGPFCCR register *************/
6754
6755 #define DMA2D_FGPFCCR_CM_Pos (0U)
6756 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
6757 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6758 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
6759 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
6760 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
6761 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
6762 #define DMA2D_FGPFCCR_CCM_Pos (4U)
6763 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
6764 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
6765 #define DMA2D_FGPFCCR_START_Pos (5U)
6766 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
6767 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
6768 #define DMA2D_FGPFCCR_CS_Pos (8U)
6769 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6770 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
6771 #define DMA2D_FGPFCCR_AM_Pos (16U)
6772 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
6773 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6774 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
6775 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
6776 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6777 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6778 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
6779
6780 /******************** Bit definition for DMA2D_FGCOLR register **************/
6781
6782 #define DMA2D_FGCOLR_BLUE_Pos (0U)
6783 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
6784 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
6785 #define DMA2D_FGCOLR_GREEN_Pos (8U)
6786 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6787 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
6788 #define DMA2D_FGCOLR_RED_Pos (16U)
6789 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
6790 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
6791
6792 /******************** Bit definition for DMA2D_BGPFCCR register *************/
6793
6794 #define DMA2D_BGPFCCR_CM_Pos (0U)
6795 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
6796 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6797 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
6798 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
6799 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
6800 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
6801 #define DMA2D_BGPFCCR_CCM_Pos (4U)
6802 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
6803 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
6804 #define DMA2D_BGPFCCR_START_Pos (5U)
6805 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
6806 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
6807 #define DMA2D_BGPFCCR_CS_Pos (8U)
6808 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6809 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
6810 #define DMA2D_BGPFCCR_AM_Pos (16U)
6811 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
6812 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6813 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
6814 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
6815 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6816 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6817 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
6818
6819 /******************** Bit definition for DMA2D_BGCOLR register **************/
6820
6821 #define DMA2D_BGCOLR_BLUE_Pos (0U)
6822 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
6823 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
6824 #define DMA2D_BGCOLR_GREEN_Pos (8U)
6825 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6826 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
6827 #define DMA2D_BGCOLR_RED_Pos (16U)
6828 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
6829 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
6830
6831 /******************** Bit definition for DMA2D_FGCMAR register **************/
6832
6833 #define DMA2D_FGCMAR_MA_Pos (0U)
6834 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6835 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
6836
6837 /******************** Bit definition for DMA2D_BGCMAR register **************/
6838
6839 #define DMA2D_BGCMAR_MA_Pos (0U)
6840 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6841 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
6842
6843 /******************** Bit definition for DMA2D_OPFCCR register **************/
6844
6845 #define DMA2D_OPFCCR_CM_Pos (0U)
6846 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
6847 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
6848 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
6849 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
6850 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
6851
6852 /******************** Bit definition for DMA2D_OCOLR register ***************/
6853
6854 /*!<Mode_ARGB8888/RGB888 */
6855
6856 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
6857 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
6858 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
6859 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
6860
6861 /*!<Mode_RGB565 */
6862 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
6863 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
6864 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
6865
6866 /*!<Mode_ARGB1555 */
6867 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
6868 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
6869 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
6870 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
6871
6872 /*!<Mode_ARGB4444 */
6873 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
6874 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
6875 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
6876 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
6877
6878 /******************** Bit definition for DMA2D_OMAR register ****************/
6879
6880 #define DMA2D_OMAR_MA_Pos (0U)
6881 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
6882 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
6883
6884 /******************** Bit definition for DMA2D_OOR register *****************/
6885
6886 #define DMA2D_OOR_LO_Pos (0U)
6887 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
6888 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
6889
6890 /******************** Bit definition for DMA2D_NLR register *****************/
6891
6892 #define DMA2D_NLR_NL_Pos (0U)
6893 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
6894 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
6895 #define DMA2D_NLR_PL_Pos (16U)
6896 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
6897 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
6898
6899 /******************** Bit definition for DMA2D_LWR register *****************/
6900
6901 #define DMA2D_LWR_LW_Pos (0U)
6902 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
6903 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
6904
6905 /******************** Bit definition for DMA2D_AMTCR register ***************/
6906
6907 #define DMA2D_AMTCR_EN_Pos (0U)
6908 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
6909 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
6910 #define DMA2D_AMTCR_DT_Pos (8U)
6911 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
6912 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
6913
6914 /******************** Bit definition for DMA2D_FGCLUT register **************/
6915
6916 /******************** Bit definition for DMA2D_BGCLUT register **************/
6917
6918
6919 /******************************************************************************/
6920 /* */
6921 /* Display Serial Interface (DSI) */
6922 /* */
6923 /******************************************************************************/
6924 /******************* Bit definition for DSI_VR register *****************/
6925 #define DSI_VR_Pos (1U)
6926 #define DSI_VR_Msk (0x18999815U << DSI_VR_Pos) /*!< 0x3133302A */
6927 #define DSI_VR DSI_VR_Msk /*!< DSI Host Version */
6928
6929 /******************* Bit definition for DSI_CR register *****************/
6930 #define DSI_CR_EN_Pos (0U)
6931 #define DSI_CR_EN_Msk (0x1U << DSI_CR_EN_Pos) /*!< 0x00000001 */
6932 #define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */
6933
6934 /******************* Bit definition for DSI_CCR register ****************/
6935 #define DSI_CCR_TXECKDIV_Pos (0U)
6936 #define DSI_CCR_TXECKDIV_Msk (0xFFU << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */
6937 #define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */
6938 #define DSI_CCR_TXECKDIV0_Pos (0U)
6939 #define DSI_CCR_TXECKDIV0_Msk (0x1U << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */
6940 #define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
6941 #define DSI_CCR_TXECKDIV1_Pos (1U)
6942 #define DSI_CCR_TXECKDIV1_Msk (0x1U << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */
6943 #define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
6944 #define DSI_CCR_TXECKDIV2_Pos (2U)
6945 #define DSI_CCR_TXECKDIV2_Msk (0x1U << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */
6946 #define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
6947 #define DSI_CCR_TXECKDIV3_Pos (3U)
6948 #define DSI_CCR_TXECKDIV3_Msk (0x1U << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */
6949 #define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
6950 #define DSI_CCR_TXECKDIV4_Pos (4U)
6951 #define DSI_CCR_TXECKDIV4_Msk (0x1U << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */
6952 #define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
6953 #define DSI_CCR_TXECKDIV5_Pos (5U)
6954 #define DSI_CCR_TXECKDIV5_Msk (0x1U << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */
6955 #define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
6956 #define DSI_CCR_TXECKDIV6_Pos (6U)
6957 #define DSI_CCR_TXECKDIV6_Msk (0x1U << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */
6958 #define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
6959 #define DSI_CCR_TXECKDIV7_Pos (7U)
6960 #define DSI_CCR_TXECKDIV7_Msk (0x1U << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */
6961 #define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
6962
6963 #define DSI_CCR_TOCKDIV_Pos (8U)
6964 #define DSI_CCR_TOCKDIV_Msk (0xFFU << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */
6965 #define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */
6966 #define DSI_CCR_TOCKDIV0_Pos (8U)
6967 #define DSI_CCR_TOCKDIV0_Msk (0x1U << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */
6968 #define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
6969 #define DSI_CCR_TOCKDIV1_Pos (9U)
6970 #define DSI_CCR_TOCKDIV1_Msk (0x1U << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */
6971 #define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
6972 #define DSI_CCR_TOCKDIV2_Pos (10U)
6973 #define DSI_CCR_TOCKDIV2_Msk (0x1U << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */
6974 #define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
6975 #define DSI_CCR_TOCKDIV3_Pos (11U)
6976 #define DSI_CCR_TOCKDIV3_Msk (0x1U << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */
6977 #define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
6978 #define DSI_CCR_TOCKDIV4_Pos (12U)
6979 #define DSI_CCR_TOCKDIV4_Msk (0x1U << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */
6980 #define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
6981 #define DSI_CCR_TOCKDIV5_Pos (13U)
6982 #define DSI_CCR_TOCKDIV5_Msk (0x1U << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */
6983 #define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
6984 #define DSI_CCR_TOCKDIV6_Pos (14U)
6985 #define DSI_CCR_TOCKDIV6_Msk (0x1U << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */
6986 #define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
6987 #define DSI_CCR_TOCKDIV7_Pos (15U)
6988 #define DSI_CCR_TOCKDIV7_Msk (0x1U << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */
6989 #define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
6990
6991 /******************* Bit definition for DSI_LVCIDR register *************/
6992 #define DSI_LVCIDR_VCID_Pos (0U)
6993 #define DSI_LVCIDR_VCID_Msk (0x3U << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */
6994 #define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */
6995 #define DSI_LVCIDR_VCID0_Pos (0U)
6996 #define DSI_LVCIDR_VCID0_Msk (0x1U << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */
6997 #define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
6998 #define DSI_LVCIDR_VCID1_Pos (1U)
6999 #define DSI_LVCIDR_VCID1_Msk (0x1U << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */
7000 #define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
7001
7002 /******************* Bit definition for DSI_LCOLCR register *************/
7003 #define DSI_LCOLCR_COLC_Pos (0U)
7004 #define DSI_LCOLCR_COLC_Msk (0xFU << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */
7005 #define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */
7006 #define DSI_LCOLCR_COLC0_Pos (0U)
7007 #define DSI_LCOLCR_COLC0_Msk (0x1U << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */
7008 #define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
7009 #define DSI_LCOLCR_COLC1_Pos (5U)
7010 #define DSI_LCOLCR_COLC1_Msk (0x1U << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */
7011 #define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
7012 #define DSI_LCOLCR_COLC2_Pos (6U)
7013 #define DSI_LCOLCR_COLC2_Msk (0x1U << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */
7014 #define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
7015 #define DSI_LCOLCR_COLC3_Pos (7U)
7016 #define DSI_LCOLCR_COLC3_Msk (0x1U << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */
7017 #define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
7018
7019 #define DSI_LCOLCR_LPE_Pos (8U)
7020 #define DSI_LCOLCR_LPE_Msk (0x1U << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
7021 #define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
7022
7023 /******************* Bit definition for DSI_LPCR register ***************/
7024 #define DSI_LPCR_DEP_Pos (0U)
7025 #define DSI_LPCR_DEP_Msk (0x1U << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */
7026 #define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */
7027 #define DSI_LPCR_VSP_Pos (1U)
7028 #define DSI_LPCR_VSP_Msk (0x1U << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */
7029 #define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */
7030 #define DSI_LPCR_HSP_Pos (2U)
7031 #define DSI_LPCR_HSP_Msk (0x1U << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */
7032 #define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */
7033
7034 /******************* Bit definition for DSI_LPMCR register **************/
7035 #define DSI_LPMCR_VLPSIZE_Pos (0U)
7036 #define DSI_LPMCR_VLPSIZE_Msk (0xFFU << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */
7037 #define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
7038 #define DSI_LPMCR_VLPSIZE0_Pos (0U)
7039 #define DSI_LPMCR_VLPSIZE0_Msk (0x1U << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */
7040 #define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
7041 #define DSI_LPMCR_VLPSIZE1_Pos (1U)
7042 #define DSI_LPMCR_VLPSIZE1_Msk (0x1U << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */
7043 #define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
7044 #define DSI_LPMCR_VLPSIZE2_Pos (2U)
7045 #define DSI_LPMCR_VLPSIZE2_Msk (0x1U << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */
7046 #define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
7047 #define DSI_LPMCR_VLPSIZE3_Pos (3U)
7048 #define DSI_LPMCR_VLPSIZE3_Msk (0x1U << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */
7049 #define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
7050 #define DSI_LPMCR_VLPSIZE4_Pos (4U)
7051 #define DSI_LPMCR_VLPSIZE4_Msk (0x1U << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */
7052 #define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
7053 #define DSI_LPMCR_VLPSIZE5_Pos (5U)
7054 #define DSI_LPMCR_VLPSIZE5_Msk (0x1U << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */
7055 #define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
7056 #define DSI_LPMCR_VLPSIZE6_Pos (6U)
7057 #define DSI_LPMCR_VLPSIZE6_Msk (0x1U << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */
7058 #define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
7059 #define DSI_LPMCR_VLPSIZE7_Pos (7U)
7060 #define DSI_LPMCR_VLPSIZE7_Msk (0x1U << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */
7061 #define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
7062
7063 #define DSI_LPMCR_LPSIZE_Pos (16U)
7064 #define DSI_LPMCR_LPSIZE_Msk (0xFFU << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */
7065 #define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */
7066 #define DSI_LPMCR_LPSIZE0_Pos (16U)
7067 #define DSI_LPMCR_LPSIZE0_Msk (0x1U << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */
7068 #define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
7069 #define DSI_LPMCR_LPSIZE1_Pos (17U)
7070 #define DSI_LPMCR_LPSIZE1_Msk (0x1U << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */
7071 #define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
7072 #define DSI_LPMCR_LPSIZE2_Pos (18U)
7073 #define DSI_LPMCR_LPSIZE2_Msk (0x1U << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */
7074 #define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
7075 #define DSI_LPMCR_LPSIZE3_Pos (19U)
7076 #define DSI_LPMCR_LPSIZE3_Msk (0x1U << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */
7077 #define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
7078 #define DSI_LPMCR_LPSIZE4_Pos (20U)
7079 #define DSI_LPMCR_LPSIZE4_Msk (0x1U << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */
7080 #define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
7081 #define DSI_LPMCR_LPSIZE5_Pos (21U)
7082 #define DSI_LPMCR_LPSIZE5_Msk (0x1U << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */
7083 #define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
7084 #define DSI_LPMCR_LPSIZE6_Pos (22U)
7085 #define DSI_LPMCR_LPSIZE6_Msk (0x1U << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */
7086 #define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
7087 #define DSI_LPMCR_LPSIZE7_Pos (23U)
7088 #define DSI_LPMCR_LPSIZE7_Msk (0x1U << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */
7089 #define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
7090
7091 /******************* Bit definition for DSI_PCR register ****************/
7092 #define DSI_PCR_ETTXE_Pos (0U)
7093 #define DSI_PCR_ETTXE_Msk (0x1U << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */
7094 #define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */
7095 #define DSI_PCR_ETRXE_Pos (1U)
7096 #define DSI_PCR_ETRXE_Msk (0x1U << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */
7097 #define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */
7098 #define DSI_PCR_BTAE_Pos (2U)
7099 #define DSI_PCR_BTAE_Msk (0x1U << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */
7100 #define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */
7101 #define DSI_PCR_ECCRXE_Pos (3U)
7102 #define DSI_PCR_ECCRXE_Msk (0x1U << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */
7103 #define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */
7104 #define DSI_PCR_CRCRXE_Pos (4U)
7105 #define DSI_PCR_CRCRXE_Msk (0x1U << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */
7106 #define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */
7107
7108 /******************* Bit definition for DSI_GVCIDR register *************/
7109 #define DSI_GVCIDR_VCID_Pos (0U)
7110 #define DSI_GVCIDR_VCID_Msk (0x3U << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */
7111 #define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */
7112 #define DSI_GVCIDR_VCID0_Pos (0U)
7113 #define DSI_GVCIDR_VCID0_Msk (0x1U << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */
7114 #define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
7115 #define DSI_GVCIDR_VCID1_Pos (1U)
7116 #define DSI_GVCIDR_VCID1_Msk (0x1U << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */
7117 #define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
7118
7119 /******************* Bit definition for DSI_MCR register ****************/
7120 #define DSI_MCR_CMDM_Pos (0U)
7121 #define DSI_MCR_CMDM_Msk (0x1U << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */
7122 #define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */
7123
7124 /******************* Bit definition for DSI_VMCR register ***************/
7125 #define DSI_VMCR_VMT_Pos (0U)
7126 #define DSI_VMCR_VMT_Msk (0x3U << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */
7127 #define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */
7128 #define DSI_VMCR_VMT0_Pos (0U)
7129 #define DSI_VMCR_VMT0_Msk (0x1U << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */
7130 #define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
7131 #define DSI_VMCR_VMT1_Pos (1U)
7132 #define DSI_VMCR_VMT1_Msk (0x1U << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */
7133 #define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
7134
7135 #define DSI_VMCR_LPVSAE_Pos (8U)
7136 #define DSI_VMCR_LPVSAE_Msk (0x1U << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */
7137 #define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */
7138 #define DSI_VMCR_LPVBPE_Pos (9U)
7139 #define DSI_VMCR_LPVBPE_Msk (0x1U << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */
7140 #define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */
7141 #define DSI_VMCR_LPVFPE_Pos (10U)
7142 #define DSI_VMCR_LPVFPE_Msk (0x1U << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */
7143 #define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
7144 #define DSI_VMCR_LPVAE_Pos (11U)
7145 #define DSI_VMCR_LPVAE_Msk (0x1U << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */
7146 #define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */
7147 #define DSI_VMCR_LPHBPE_Pos (12U)
7148 #define DSI_VMCR_LPHBPE_Msk (0x1U << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */
7149 #define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */
7150 #define DSI_VMCR_LPHFPE_Pos (13U)
7151 #define DSI_VMCR_LPHFPE_Msk (0x1U << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */
7152 #define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */
7153 #define DSI_VMCR_FBTAAE_Pos (14U)
7154 #define DSI_VMCR_FBTAAE_Msk (0x1U << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */
7155 #define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */
7156 #define DSI_VMCR_LPCE_Pos (15U)
7157 #define DSI_VMCR_LPCE_Msk (0x1U << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */
7158 #define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */
7159 #define DSI_VMCR_PGE_Pos (16U)
7160 #define DSI_VMCR_PGE_Msk (0x1U << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */
7161 #define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */
7162 #define DSI_VMCR_PGM_Pos (20U)
7163 #define DSI_VMCR_PGM_Msk (0x1U << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */
7164 #define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */
7165 #define DSI_VMCR_PGO_Pos (24U)
7166 #define DSI_VMCR_PGO_Msk (0x1U << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */
7167 #define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */
7168
7169 /******************* Bit definition for DSI_VPCR register ***************/
7170 #define DSI_VPCR_VPSIZE_Pos (0U)
7171 #define DSI_VPCR_VPSIZE_Msk (0x3FFFU << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */
7172 #define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */
7173 #define DSI_VPCR_VPSIZE0_Pos (0U)
7174 #define DSI_VPCR_VPSIZE0_Msk (0x1U << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */
7175 #define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
7176 #define DSI_VPCR_VPSIZE1_Pos (1U)
7177 #define DSI_VPCR_VPSIZE1_Msk (0x1U << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */
7178 #define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
7179 #define DSI_VPCR_VPSIZE2_Pos (2U)
7180 #define DSI_VPCR_VPSIZE2_Msk (0x1U << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */
7181 #define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
7182 #define DSI_VPCR_VPSIZE3_Pos (3U)
7183 #define DSI_VPCR_VPSIZE3_Msk (0x1U << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */
7184 #define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
7185 #define DSI_VPCR_VPSIZE4_Pos (4U)
7186 #define DSI_VPCR_VPSIZE4_Msk (0x1U << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */
7187 #define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
7188 #define DSI_VPCR_VPSIZE5_Pos (5U)
7189 #define DSI_VPCR_VPSIZE5_Msk (0x1U << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */
7190 #define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
7191 #define DSI_VPCR_VPSIZE6_Pos (6U)
7192 #define DSI_VPCR_VPSIZE6_Msk (0x1U << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */
7193 #define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
7194 #define DSI_VPCR_VPSIZE7_Pos (7U)
7195 #define DSI_VPCR_VPSIZE7_Msk (0x1U << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */
7196 #define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
7197 #define DSI_VPCR_VPSIZE8_Pos (8U)
7198 #define DSI_VPCR_VPSIZE8_Msk (0x1U << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */
7199 #define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
7200 #define DSI_VPCR_VPSIZE9_Pos (9U)
7201 #define DSI_VPCR_VPSIZE9_Msk (0x1U << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */
7202 #define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
7203 #define DSI_VPCR_VPSIZE10_Pos (10U)
7204 #define DSI_VPCR_VPSIZE10_Msk (0x1U << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */
7205 #define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
7206 #define DSI_VPCR_VPSIZE11_Pos (11U)
7207 #define DSI_VPCR_VPSIZE11_Msk (0x1U << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */
7208 #define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
7209 #define DSI_VPCR_VPSIZE12_Pos (12U)
7210 #define DSI_VPCR_VPSIZE12_Msk (0x1U << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */
7211 #define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
7212 #define DSI_VPCR_VPSIZE13_Pos (13U)
7213 #define DSI_VPCR_VPSIZE13_Msk (0x1U << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */
7214 #define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
7215
7216 /******************* Bit definition for DSI_VCCR register ***************/
7217 #define DSI_VCCR_NUMC_Pos (0U)
7218 #define DSI_VCCR_NUMC_Msk (0x1FFFU << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */
7219 #define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */
7220 #define DSI_VCCR_NUMC0_Pos (0U)
7221 #define DSI_VCCR_NUMC0_Msk (0x1U << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */
7222 #define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
7223 #define DSI_VCCR_NUMC1_Pos (1U)
7224 #define DSI_VCCR_NUMC1_Msk (0x1U << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */
7225 #define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
7226 #define DSI_VCCR_NUMC2_Pos (2U)
7227 #define DSI_VCCR_NUMC2_Msk (0x1U << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */
7228 #define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
7229 #define DSI_VCCR_NUMC3_Pos (3U)
7230 #define DSI_VCCR_NUMC3_Msk (0x1U << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */
7231 #define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
7232 #define DSI_VCCR_NUMC4_Pos (4U)
7233 #define DSI_VCCR_NUMC4_Msk (0x1U << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */
7234 #define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
7235 #define DSI_VCCR_NUMC5_Pos (5U)
7236 #define DSI_VCCR_NUMC5_Msk (0x1U << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */
7237 #define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
7238 #define DSI_VCCR_NUMC6_Pos (6U)
7239 #define DSI_VCCR_NUMC6_Msk (0x1U << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */
7240 #define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
7241 #define DSI_VCCR_NUMC7_Pos (7U)
7242 #define DSI_VCCR_NUMC7_Msk (0x1U << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */
7243 #define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
7244 #define DSI_VCCR_NUMC8_Pos (8U)
7245 #define DSI_VCCR_NUMC8_Msk (0x1U << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */
7246 #define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
7247 #define DSI_VCCR_NUMC9_Pos (9U)
7248 #define DSI_VCCR_NUMC9_Msk (0x1U << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */
7249 #define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
7250 #define DSI_VCCR_NUMC10_Pos (10U)
7251 #define DSI_VCCR_NUMC10_Msk (0x1U << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */
7252 #define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
7253 #define DSI_VCCR_NUMC11_Pos (11U)
7254 #define DSI_VCCR_NUMC11_Msk (0x1U << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */
7255 #define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
7256 #define DSI_VCCR_NUMC12_Pos (12U)
7257 #define DSI_VCCR_NUMC12_Msk (0x1U << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */
7258 #define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
7259
7260 /******************* Bit definition for DSI_VNPCR register **************/
7261 #define DSI_VNPCR_NPSIZE_Pos (0U)
7262 #define DSI_VNPCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */
7263 #define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */
7264 #define DSI_VNPCR_NPSIZE0_Pos (0U)
7265 #define DSI_VNPCR_NPSIZE0_Msk (0x1U << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */
7266 #define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
7267 #define DSI_VNPCR_NPSIZE1_Pos (1U)
7268 #define DSI_VNPCR_NPSIZE1_Msk (0x1U << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */
7269 #define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
7270 #define DSI_VNPCR_NPSIZE2_Pos (2U)
7271 #define DSI_VNPCR_NPSIZE2_Msk (0x1U << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */
7272 #define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
7273 #define DSI_VNPCR_NPSIZE3_Pos (3U)
7274 #define DSI_VNPCR_NPSIZE3_Msk (0x1U << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */
7275 #define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
7276 #define DSI_VNPCR_NPSIZE4_Pos (4U)
7277 #define DSI_VNPCR_NPSIZE4_Msk (0x1U << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */
7278 #define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
7279 #define DSI_VNPCR_NPSIZE5_Pos (5U)
7280 #define DSI_VNPCR_NPSIZE5_Msk (0x1U << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */
7281 #define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
7282 #define DSI_VNPCR_NPSIZE6_Pos (6U)
7283 #define DSI_VNPCR_NPSIZE6_Msk (0x1U << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */
7284 #define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
7285 #define DSI_VNPCR_NPSIZE7_Pos (7U)
7286 #define DSI_VNPCR_NPSIZE7_Msk (0x1U << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */
7287 #define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
7288 #define DSI_VNPCR_NPSIZE8_Pos (8U)
7289 #define DSI_VNPCR_NPSIZE8_Msk (0x1U << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */
7290 #define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
7291 #define DSI_VNPCR_NPSIZE9_Pos (9U)
7292 #define DSI_VNPCR_NPSIZE9_Msk (0x1U << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */
7293 #define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
7294 #define DSI_VNPCR_NPSIZE10_Pos (10U)
7295 #define DSI_VNPCR_NPSIZE10_Msk (0x1U << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */
7296 #define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
7297 #define DSI_VNPCR_NPSIZE11_Pos (11U)
7298 #define DSI_VNPCR_NPSIZE11_Msk (0x1U << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */
7299 #define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
7300 #define DSI_VNPCR_NPSIZE12_Pos (12U)
7301 #define DSI_VNPCR_NPSIZE12_Msk (0x1U << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */
7302 #define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
7303
7304 /******************* Bit definition for DSI_VHSACR register *************/
7305 #define DSI_VHSACR_HSA_Pos (0U)
7306 #define DSI_VHSACR_HSA_Msk (0xFFFU << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */
7307 #define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */
7308 #define DSI_VHSACR_HSA0_Pos (0U)
7309 #define DSI_VHSACR_HSA0_Msk (0x1U << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */
7310 #define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
7311 #define DSI_VHSACR_HSA1_Pos (1U)
7312 #define DSI_VHSACR_HSA1_Msk (0x1U << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */
7313 #define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
7314 #define DSI_VHSACR_HSA2_Pos (2U)
7315 #define DSI_VHSACR_HSA2_Msk (0x1U << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */
7316 #define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
7317 #define DSI_VHSACR_HSA3_Pos (3U)
7318 #define DSI_VHSACR_HSA3_Msk (0x1U << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */
7319 #define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
7320 #define DSI_VHSACR_HSA4_Pos (4U)
7321 #define DSI_VHSACR_HSA4_Msk (0x1U << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */
7322 #define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
7323 #define DSI_VHSACR_HSA5_Pos (5U)
7324 #define DSI_VHSACR_HSA5_Msk (0x1U << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */
7325 #define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
7326 #define DSI_VHSACR_HSA6_Pos (6U)
7327 #define DSI_VHSACR_HSA6_Msk (0x1U << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */
7328 #define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
7329 #define DSI_VHSACR_HSA7_Pos (7U)
7330 #define DSI_VHSACR_HSA7_Msk (0x1U << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */
7331 #define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
7332 #define DSI_VHSACR_HSA8_Pos (8U)
7333 #define DSI_VHSACR_HSA8_Msk (0x1U << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */
7334 #define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
7335 #define DSI_VHSACR_HSA9_Pos (9U)
7336 #define DSI_VHSACR_HSA9_Msk (0x1U << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */
7337 #define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
7338 #define DSI_VHSACR_HSA10_Pos (10U)
7339 #define DSI_VHSACR_HSA10_Msk (0x1U << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */
7340 #define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
7341 #define DSI_VHSACR_HSA11_Pos (11U)
7342 #define DSI_VHSACR_HSA11_Msk (0x1U << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */
7343 #define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
7344
7345 /******************* Bit definition for DSI_VHBPCR register *************/
7346 #define DSI_VHBPCR_HBP_Pos (0U)
7347 #define DSI_VHBPCR_HBP_Msk (0xFFFU << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */
7348 #define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
7349 #define DSI_VHBPCR_HBP0_Pos (0U)
7350 #define DSI_VHBPCR_HBP0_Msk (0x1U << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */
7351 #define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
7352 #define DSI_VHBPCR_HBP1_Pos (1U)
7353 #define DSI_VHBPCR_HBP1_Msk (0x1U << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */
7354 #define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
7355 #define DSI_VHBPCR_HBP2_Pos (2U)
7356 #define DSI_VHBPCR_HBP2_Msk (0x1U << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */
7357 #define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
7358 #define DSI_VHBPCR_HBP3_Pos (3U)
7359 #define DSI_VHBPCR_HBP3_Msk (0x1U << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */
7360 #define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
7361 #define DSI_VHBPCR_HBP4_Pos (4U)
7362 #define DSI_VHBPCR_HBP4_Msk (0x1U << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */
7363 #define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
7364 #define DSI_VHBPCR_HBP5_Pos (5U)
7365 #define DSI_VHBPCR_HBP5_Msk (0x1U << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */
7366 #define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
7367 #define DSI_VHBPCR_HBP6_Pos (6U)
7368 #define DSI_VHBPCR_HBP6_Msk (0x1U << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */
7369 #define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
7370 #define DSI_VHBPCR_HBP7_Pos (7U)
7371 #define DSI_VHBPCR_HBP7_Msk (0x1U << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */
7372 #define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
7373 #define DSI_VHBPCR_HBP8_Pos (8U)
7374 #define DSI_VHBPCR_HBP8_Msk (0x1U << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */
7375 #define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
7376 #define DSI_VHBPCR_HBP9_Pos (9U)
7377 #define DSI_VHBPCR_HBP9_Msk (0x1U << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */
7378 #define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
7379 #define DSI_VHBPCR_HBP10_Pos (10U)
7380 #define DSI_VHBPCR_HBP10_Msk (0x1U << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */
7381 #define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
7382 #define DSI_VHBPCR_HBP11_Pos (11U)
7383 #define DSI_VHBPCR_HBP11_Msk (0x1U << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */
7384 #define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
7385
7386 /******************* Bit definition for DSI_VLCR register ***************/
7387 #define DSI_VLCR_HLINE_Pos (0U)
7388 #define DSI_VLCR_HLINE_Msk (0x7FFFU << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */
7389 #define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */
7390 #define DSI_VLCR_HLINE0_Pos (0U)
7391 #define DSI_VLCR_HLINE0_Msk (0x1U << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */
7392 #define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
7393 #define DSI_VLCR_HLINE1_Pos (1U)
7394 #define DSI_VLCR_HLINE1_Msk (0x1U << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */
7395 #define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
7396 #define DSI_VLCR_HLINE2_Pos (2U)
7397 #define DSI_VLCR_HLINE2_Msk (0x1U << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */
7398 #define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
7399 #define DSI_VLCR_HLINE3_Pos (3U)
7400 #define DSI_VLCR_HLINE3_Msk (0x1U << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */
7401 #define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
7402 #define DSI_VLCR_HLINE4_Pos (4U)
7403 #define DSI_VLCR_HLINE4_Msk (0x1U << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */
7404 #define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
7405 #define DSI_VLCR_HLINE5_Pos (5U)
7406 #define DSI_VLCR_HLINE5_Msk (0x1U << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */
7407 #define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
7408 #define DSI_VLCR_HLINE6_Pos (6U)
7409 #define DSI_VLCR_HLINE6_Msk (0x1U << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */
7410 #define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
7411 #define DSI_VLCR_HLINE7_Pos (7U)
7412 #define DSI_VLCR_HLINE7_Msk (0x1U << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */
7413 #define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
7414 #define DSI_VLCR_HLINE8_Pos (8U)
7415 #define DSI_VLCR_HLINE8_Msk (0x1U << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */
7416 #define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
7417 #define DSI_VLCR_HLINE9_Pos (9U)
7418 #define DSI_VLCR_HLINE9_Msk (0x1U << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */
7419 #define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
7420 #define DSI_VLCR_HLINE10_Pos (10U)
7421 #define DSI_VLCR_HLINE10_Msk (0x1U << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */
7422 #define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
7423 #define DSI_VLCR_HLINE11_Pos (11U)
7424 #define DSI_VLCR_HLINE11_Msk (0x1U << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */
7425 #define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
7426 #define DSI_VLCR_HLINE12_Pos (12U)
7427 #define DSI_VLCR_HLINE12_Msk (0x1U << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */
7428 #define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
7429 #define DSI_VLCR_HLINE13_Pos (13U)
7430 #define DSI_VLCR_HLINE13_Msk (0x1U << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */
7431 #define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
7432 #define DSI_VLCR_HLINE14_Pos (14U)
7433 #define DSI_VLCR_HLINE14_Msk (0x1U << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */
7434 #define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
7435
7436 /******************* Bit definition for DSI_VVSACR register *************/
7437 #define DSI_VVSACR_VSA_Pos (0U)
7438 #define DSI_VVSACR_VSA_Msk (0x3FFU << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */
7439 #define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */
7440 #define DSI_VVSACR_VSA0_Pos (0U)
7441 #define DSI_VVSACR_VSA0_Msk (0x1U << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */
7442 #define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
7443 #define DSI_VVSACR_VSA1_Pos (1U)
7444 #define DSI_VVSACR_VSA1_Msk (0x1U << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */
7445 #define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
7446 #define DSI_VVSACR_VSA2_Pos (2U)
7447 #define DSI_VVSACR_VSA2_Msk (0x1U << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */
7448 #define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
7449 #define DSI_VVSACR_VSA3_Pos (3U)
7450 #define DSI_VVSACR_VSA3_Msk (0x1U << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */
7451 #define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
7452 #define DSI_VVSACR_VSA4_Pos (4U)
7453 #define DSI_VVSACR_VSA4_Msk (0x1U << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */
7454 #define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
7455 #define DSI_VVSACR_VSA5_Pos (5U)
7456 #define DSI_VVSACR_VSA5_Msk (0x1U << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */
7457 #define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
7458 #define DSI_VVSACR_VSA6_Pos (6U)
7459 #define DSI_VVSACR_VSA6_Msk (0x1U << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */
7460 #define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
7461 #define DSI_VVSACR_VSA7_Pos (7U)
7462 #define DSI_VVSACR_VSA7_Msk (0x1U << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */
7463 #define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
7464 #define DSI_VVSACR_VSA8_Pos (8U)
7465 #define DSI_VVSACR_VSA8_Msk (0x1U << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */
7466 #define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
7467 #define DSI_VVSACR_VSA9_Pos (9U)
7468 #define DSI_VVSACR_VSA9_Msk (0x1U << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */
7469 #define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
7470
7471 /******************* Bit definition for DSI_VVBPCR register *************/
7472 #define DSI_VVBPCR_VBP_Pos (0U)
7473 #define DSI_VVBPCR_VBP_Msk (0x3FFU << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */
7474 #define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */
7475 #define DSI_VVBPCR_VBP0_Pos (0U)
7476 #define DSI_VVBPCR_VBP0_Msk (0x1U << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */
7477 #define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
7478 #define DSI_VVBPCR_VBP1_Pos (1U)
7479 #define DSI_VVBPCR_VBP1_Msk (0x1U << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */
7480 #define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
7481 #define DSI_VVBPCR_VBP2_Pos (2U)
7482 #define DSI_VVBPCR_VBP2_Msk (0x1U << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */
7483 #define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
7484 #define DSI_VVBPCR_VBP3_Pos (3U)
7485 #define DSI_VVBPCR_VBP3_Msk (0x1U << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */
7486 #define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
7487 #define DSI_VVBPCR_VBP4_Pos (4U)
7488 #define DSI_VVBPCR_VBP4_Msk (0x1U << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */
7489 #define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
7490 #define DSI_VVBPCR_VBP5_Pos (5U)
7491 #define DSI_VVBPCR_VBP5_Msk (0x1U << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */
7492 #define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
7493 #define DSI_VVBPCR_VBP6_Pos (6U)
7494 #define DSI_VVBPCR_VBP6_Msk (0x1U << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */
7495 #define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
7496 #define DSI_VVBPCR_VBP7_Pos (7U)
7497 #define DSI_VVBPCR_VBP7_Msk (0x1U << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */
7498 #define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
7499 #define DSI_VVBPCR_VBP8_Pos (8U)
7500 #define DSI_VVBPCR_VBP8_Msk (0x1U << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */
7501 #define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
7502 #define DSI_VVBPCR_VBP9_Pos (9U)
7503 #define DSI_VVBPCR_VBP9_Msk (0x1U << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */
7504 #define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
7505
7506 /******************* Bit definition for DSI_VVFPCR register *************/
7507 #define DSI_VVFPCR_VFP_Pos (0U)
7508 #define DSI_VVFPCR_VFP_Msk (0x3FFU << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */
7509 #define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */
7510 #define DSI_VVFPCR_VFP0_Pos (0U)
7511 #define DSI_VVFPCR_VFP0_Msk (0x1U << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */
7512 #define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
7513 #define DSI_VVFPCR_VFP1_Pos (1U)
7514 #define DSI_VVFPCR_VFP1_Msk (0x1U << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */
7515 #define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
7516 #define DSI_VVFPCR_VFP2_Pos (2U)
7517 #define DSI_VVFPCR_VFP2_Msk (0x1U << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */
7518 #define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
7519 #define DSI_VVFPCR_VFP3_Pos (3U)
7520 #define DSI_VVFPCR_VFP3_Msk (0x1U << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */
7521 #define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
7522 #define DSI_VVFPCR_VFP4_Pos (4U)
7523 #define DSI_VVFPCR_VFP4_Msk (0x1U << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */
7524 #define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
7525 #define DSI_VVFPCR_VFP5_Pos (5U)
7526 #define DSI_VVFPCR_VFP5_Msk (0x1U << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */
7527 #define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
7528 #define DSI_VVFPCR_VFP6_Pos (6U)
7529 #define DSI_VVFPCR_VFP6_Msk (0x1U << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */
7530 #define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
7531 #define DSI_VVFPCR_VFP7_Pos (7U)
7532 #define DSI_VVFPCR_VFP7_Msk (0x1U << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */
7533 #define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
7534 #define DSI_VVFPCR_VFP8_Pos (8U)
7535 #define DSI_VVFPCR_VFP8_Msk (0x1U << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */
7536 #define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
7537 #define DSI_VVFPCR_VFP9_Pos (9U)
7538 #define DSI_VVFPCR_VFP9_Msk (0x1U << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */
7539 #define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
7540
7541 /******************* Bit definition for DSI_VVACR register **************/
7542 #define DSI_VVACR_VA_Pos (0U)
7543 #define DSI_VVACR_VA_Msk (0x3FFFU << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */
7544 #define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */
7545 #define DSI_VVACR_VA0_Pos (0U)
7546 #define DSI_VVACR_VA0_Msk (0x1U << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */
7547 #define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
7548 #define DSI_VVACR_VA1_Pos (1U)
7549 #define DSI_VVACR_VA1_Msk (0x1U << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */
7550 #define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
7551 #define DSI_VVACR_VA2_Pos (2U)
7552 #define DSI_VVACR_VA2_Msk (0x1U << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */
7553 #define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
7554 #define DSI_VVACR_VA3_Pos (3U)
7555 #define DSI_VVACR_VA3_Msk (0x1U << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */
7556 #define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
7557 #define DSI_VVACR_VA4_Pos (4U)
7558 #define DSI_VVACR_VA4_Msk (0x1U << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */
7559 #define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
7560 #define DSI_VVACR_VA5_Pos (5U)
7561 #define DSI_VVACR_VA5_Msk (0x1U << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */
7562 #define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
7563 #define DSI_VVACR_VA6_Pos (6U)
7564 #define DSI_VVACR_VA6_Msk (0x1U << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */
7565 #define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
7566 #define DSI_VVACR_VA7_Pos (7U)
7567 #define DSI_VVACR_VA7_Msk (0x1U << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */
7568 #define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
7569 #define DSI_VVACR_VA8_Pos (8U)
7570 #define DSI_VVACR_VA8_Msk (0x1U << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */
7571 #define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
7572 #define DSI_VVACR_VA9_Pos (9U)
7573 #define DSI_VVACR_VA9_Msk (0x1U << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */
7574 #define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
7575 #define DSI_VVACR_VA10_Pos (10U)
7576 #define DSI_VVACR_VA10_Msk (0x1U << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */
7577 #define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
7578 #define DSI_VVACR_VA11_Pos (11U)
7579 #define DSI_VVACR_VA11_Msk (0x1U << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */
7580 #define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
7581 #define DSI_VVACR_VA12_Pos (12U)
7582 #define DSI_VVACR_VA12_Msk (0x1U << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */
7583 #define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
7584 #define DSI_VVACR_VA13_Pos (13U)
7585 #define DSI_VVACR_VA13_Msk (0x1U << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */
7586 #define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
7587
7588 /******************* Bit definition for DSI_LCCR register ***************/
7589 #define DSI_LCCR_CMDSIZE_Pos (0U)
7590 #define DSI_LCCR_CMDSIZE_Msk (0xFFFFU << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */
7591 #define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */
7592 #define DSI_LCCR_CMDSIZE0_Pos (0U)
7593 #define DSI_LCCR_CMDSIZE0_Msk (0x1U << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */
7594 #define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
7595 #define DSI_LCCR_CMDSIZE1_Pos (1U)
7596 #define DSI_LCCR_CMDSIZE1_Msk (0x1U << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */
7597 #define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
7598 #define DSI_LCCR_CMDSIZE2_Pos (2U)
7599 #define DSI_LCCR_CMDSIZE2_Msk (0x1U << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */
7600 #define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
7601 #define DSI_LCCR_CMDSIZE3_Pos (3U)
7602 #define DSI_LCCR_CMDSIZE3_Msk (0x1U << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */
7603 #define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
7604 #define DSI_LCCR_CMDSIZE4_Pos (4U)
7605 #define DSI_LCCR_CMDSIZE4_Msk (0x1U << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */
7606 #define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
7607 #define DSI_LCCR_CMDSIZE5_Pos (5U)
7608 #define DSI_LCCR_CMDSIZE5_Msk (0x1U << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */
7609 #define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
7610 #define DSI_LCCR_CMDSIZE6_Pos (6U)
7611 #define DSI_LCCR_CMDSIZE6_Msk (0x1U << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */
7612 #define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
7613 #define DSI_LCCR_CMDSIZE7_Pos (7U)
7614 #define DSI_LCCR_CMDSIZE7_Msk (0x1U << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */
7615 #define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
7616 #define DSI_LCCR_CMDSIZE8_Pos (8U)
7617 #define DSI_LCCR_CMDSIZE8_Msk (0x1U << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */
7618 #define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
7619 #define DSI_LCCR_CMDSIZE9_Pos (9U)
7620 #define DSI_LCCR_CMDSIZE9_Msk (0x1U << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */
7621 #define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
7622 #define DSI_LCCR_CMDSIZE10_Pos (10U)
7623 #define DSI_LCCR_CMDSIZE10_Msk (0x1U << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */
7624 #define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
7625 #define DSI_LCCR_CMDSIZE11_Pos (11U)
7626 #define DSI_LCCR_CMDSIZE11_Msk (0x1U << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */
7627 #define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
7628 #define DSI_LCCR_CMDSIZE12_Pos (12U)
7629 #define DSI_LCCR_CMDSIZE12_Msk (0x1U << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */
7630 #define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
7631 #define DSI_LCCR_CMDSIZE13_Pos (13U)
7632 #define DSI_LCCR_CMDSIZE13_Msk (0x1U << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */
7633 #define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
7634 #define DSI_LCCR_CMDSIZE14_Pos (14U)
7635 #define DSI_LCCR_CMDSIZE14_Msk (0x1U << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */
7636 #define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
7637 #define DSI_LCCR_CMDSIZE15_Pos (15U)
7638 #define DSI_LCCR_CMDSIZE15_Msk (0x1U << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */
7639 #define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
7640
7641 /******************* Bit definition for DSI_CMCR register ***************/
7642 #define DSI_CMCR_TEARE_Pos (0U)
7643 #define DSI_CMCR_TEARE_Msk (0x1U << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */
7644 #define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */
7645 #define DSI_CMCR_ARE_Pos (1U)
7646 #define DSI_CMCR_ARE_Msk (0x1U << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */
7647 #define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */
7648 #define DSI_CMCR_GSW0TX_Pos (8U)
7649 #define DSI_CMCR_GSW0TX_Msk (0x1U << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */
7650 #define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */
7651 #define DSI_CMCR_GSW1TX_Pos (9U)
7652 #define DSI_CMCR_GSW1TX_Msk (0x1U << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */
7653 #define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */
7654 #define DSI_CMCR_GSW2TX_Pos (10U)
7655 #define DSI_CMCR_GSW2TX_Msk (0x1U << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */
7656 #define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */
7657 #define DSI_CMCR_GSR0TX_Pos (11U)
7658 #define DSI_CMCR_GSR0TX_Msk (0x1U << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */
7659 #define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */
7660 #define DSI_CMCR_GSR1TX_Pos (12U)
7661 #define DSI_CMCR_GSR1TX_Msk (0x1U << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */
7662 #define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */
7663 #define DSI_CMCR_GSR2TX_Pos (13U)
7664 #define DSI_CMCR_GSR2TX_Msk (0x1U << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */
7665 #define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */
7666 #define DSI_CMCR_GLWTX_Pos (14U)
7667 #define DSI_CMCR_GLWTX_Msk (0x1U << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */
7668 #define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */
7669 #define DSI_CMCR_DSW0TX_Pos (16U)
7670 #define DSI_CMCR_DSW0TX_Msk (0x1U << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */
7671 #define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */
7672 #define DSI_CMCR_DSW1TX_Pos (17U)
7673 #define DSI_CMCR_DSW1TX_Msk (0x1U << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */
7674 #define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */
7675 #define DSI_CMCR_DSR0TX_Pos (18U)
7676 #define DSI_CMCR_DSR0TX_Msk (0x1U << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */
7677 #define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */
7678 #define DSI_CMCR_DLWTX_Pos (19U)
7679 #define DSI_CMCR_DLWTX_Msk (0x1U << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */
7680 #define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */
7681 #define DSI_CMCR_MRDPS_Pos (24U)
7682 #define DSI_CMCR_MRDPS_Msk (0x1U << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */
7683 #define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */
7684
7685 /******************* Bit definition for DSI_GHCR register ***************/
7686 #define DSI_GHCR_DT_Pos (0U)
7687 #define DSI_GHCR_DT_Msk (0x3FU << DSI_GHCR_DT_Pos) /*!< 0x0000003F */
7688 #define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */
7689 #define DSI_GHCR_DT0_Pos (0U)
7690 #define DSI_GHCR_DT0_Msk (0x1U << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */
7691 #define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
7692 #define DSI_GHCR_DT1_Pos (1U)
7693 #define DSI_GHCR_DT1_Msk (0x1U << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */
7694 #define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
7695 #define DSI_GHCR_DT2_Pos (2U)
7696 #define DSI_GHCR_DT2_Msk (0x1U << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */
7697 #define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
7698 #define DSI_GHCR_DT3_Pos (3U)
7699 #define DSI_GHCR_DT3_Msk (0x1U << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */
7700 #define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
7701 #define DSI_GHCR_DT4_Pos (4U)
7702 #define DSI_GHCR_DT4_Msk (0x1U << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */
7703 #define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
7704 #define DSI_GHCR_DT5_Pos (5U)
7705 #define DSI_GHCR_DT5_Msk (0x1U << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */
7706 #define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
7707
7708 #define DSI_GHCR_VCID_Pos (6U)
7709 #define DSI_GHCR_VCID_Msk (0x3U << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */
7710 #define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */
7711 #define DSI_GHCR_VCID0_Pos (6U)
7712 #define DSI_GHCR_VCID0_Msk (0x1U << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */
7713 #define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
7714 #define DSI_GHCR_VCID1_Pos (7U)
7715 #define DSI_GHCR_VCID1_Msk (0x1U << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */
7716 #define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
7717
7718 #define DSI_GHCR_WCLSB_Pos (8U)
7719 #define DSI_GHCR_WCLSB_Msk (0xFFU << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */
7720 #define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */
7721 #define DSI_GHCR_WCLSB0_Pos (8U)
7722 #define DSI_GHCR_WCLSB0_Msk (0x1U << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */
7723 #define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
7724 #define DSI_GHCR_WCLSB1_Pos (9U)
7725 #define DSI_GHCR_WCLSB1_Msk (0x1U << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */
7726 #define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
7727 #define DSI_GHCR_WCLSB2_Pos (10U)
7728 #define DSI_GHCR_WCLSB2_Msk (0x1U << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */
7729 #define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
7730 #define DSI_GHCR_WCLSB3_Pos (11U)
7731 #define DSI_GHCR_WCLSB3_Msk (0x1U << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */
7732 #define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
7733 #define DSI_GHCR_WCLSB4_Pos (12U)
7734 #define DSI_GHCR_WCLSB4_Msk (0x1U << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */
7735 #define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
7736 #define DSI_GHCR_WCLSB5_Pos (13U)
7737 #define DSI_GHCR_WCLSB5_Msk (0x1U << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */
7738 #define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
7739 #define DSI_GHCR_WCLSB6_Pos (14U)
7740 #define DSI_GHCR_WCLSB6_Msk (0x1U << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */
7741 #define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
7742 #define DSI_GHCR_WCLSB7_Pos (15U)
7743 #define DSI_GHCR_WCLSB7_Msk (0x1U << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */
7744 #define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
7745
7746 #define DSI_GHCR_WCMSB_Pos (16U)
7747 #define DSI_GHCR_WCMSB_Msk (0xFFU << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */
7748 #define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */
7749 #define DSI_GHCR_WCMSB0_Pos (16U)
7750 #define DSI_GHCR_WCMSB0_Msk (0x1U << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */
7751 #define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
7752 #define DSI_GHCR_WCMSB1_Pos (17U)
7753 #define DSI_GHCR_WCMSB1_Msk (0x1U << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */
7754 #define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
7755 #define DSI_GHCR_WCMSB2_Pos (18U)
7756 #define DSI_GHCR_WCMSB2_Msk (0x1U << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */
7757 #define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
7758 #define DSI_GHCR_WCMSB3_Pos (19U)
7759 #define DSI_GHCR_WCMSB3_Msk (0x1U << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */
7760 #define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
7761 #define DSI_GHCR_WCMSB4_Pos (20U)
7762 #define DSI_GHCR_WCMSB4_Msk (0x1U << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */
7763 #define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
7764 #define DSI_GHCR_WCMSB5_Pos (21U)
7765 #define DSI_GHCR_WCMSB5_Msk (0x1U << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */
7766 #define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
7767 #define DSI_GHCR_WCMSB6_Pos (22U)
7768 #define DSI_GHCR_WCMSB6_Msk (0x1U << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */
7769 #define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
7770 #define DSI_GHCR_WCMSB7_Pos (23U)
7771 #define DSI_GHCR_WCMSB7_Msk (0x1U << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */
7772 #define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
7773
7774 /******************* Bit definition for DSI_GPDR register ***************/
7775 #define DSI_GPDR_DATA1_Pos (0U)
7776 #define DSI_GPDR_DATA1_Msk (0xFFU << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */
7777 #define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */
7778 #define DSI_GPDR_DATA1_0 (0x01U << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */
7779 #define DSI_GPDR_DATA1_1 (0x02U << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */
7780 #define DSI_GPDR_DATA1_2 (0x04U << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */
7781 #define DSI_GPDR_DATA1_3 (0x08U << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */
7782 #define DSI_GPDR_DATA1_4 (0x10U << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */
7783 #define DSI_GPDR_DATA1_5 (0x20U << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */
7784 #define DSI_GPDR_DATA1_6 (0x40U << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */
7785 #define DSI_GPDR_DATA1_7 (0x80U << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */
7786
7787 #define DSI_GPDR_DATA2_Pos (8U)
7788 #define DSI_GPDR_DATA2_Msk (0xFFU << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
7789 #define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */
7790 #define DSI_GPDR_DATA2_0 (0x01U << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
7791 #define DSI_GPDR_DATA2_1 (0x02U << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
7792 #define DSI_GPDR_DATA2_2 (0x04U << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
7793 #define DSI_GPDR_DATA2_3 (0x08U << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
7794 #define DSI_GPDR_DATA2_4 (0x10U << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
7795 #define DSI_GPDR_DATA2_5 (0x20U << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
7796 #define DSI_GPDR_DATA2_6 (0x40U << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
7797 #define DSI_GPDR_DATA2_7 (0x80U << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
7798
7799 #define DSI_GPDR_DATA3_Pos (16U)
7800 #define DSI_GPDR_DATA3_Msk (0xFFU << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
7801 #define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */
7802 #define DSI_GPDR_DATA3_0 (0x01U << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
7803 #define DSI_GPDR_DATA3_1 (0x02U << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
7804 #define DSI_GPDR_DATA3_2 (0x04U << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
7805 #define DSI_GPDR_DATA3_3 (0x08U << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
7806 #define DSI_GPDR_DATA3_4 (0x10U << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
7807 #define DSI_GPDR_DATA3_5 (0x20U << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
7808 #define DSI_GPDR_DATA3_6 (0x40U << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
7809 #define DSI_GPDR_DATA3_7 (0x80U << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
7810
7811 #define DSI_GPDR_DATA4_Pos (24U)
7812 #define DSI_GPDR_DATA4_Msk (0xFFU << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */
7813 #define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */
7814 #define DSI_GPDR_DATA4_0 (0x01U << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */
7815 #define DSI_GPDR_DATA4_1 (0x02U << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */
7816 #define DSI_GPDR_DATA4_2 (0x04U << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */
7817 #define DSI_GPDR_DATA4_3 (0x08U << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */
7818 #define DSI_GPDR_DATA4_4 (0x10U << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */
7819 #define DSI_GPDR_DATA4_5 (0x20U << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */
7820 #define DSI_GPDR_DATA4_6 (0x40U << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */
7821 #define DSI_GPDR_DATA4_7 (0x80U << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */
7822
7823 /******************* Bit definition for DSI_GPSR register ***************/
7824 #define DSI_GPSR_CMDFE_Pos (0U)
7825 #define DSI_GPSR_CMDFE_Msk (0x1U << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */
7826 #define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */
7827 #define DSI_GPSR_CMDFF_Pos (1U)
7828 #define DSI_GPSR_CMDFF_Msk (0x1U << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */
7829 #define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */
7830 #define DSI_GPSR_PWRFE_Pos (2U)
7831 #define DSI_GPSR_PWRFE_Msk (0x1U << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */
7832 #define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */
7833 #define DSI_GPSR_PWRFF_Pos (3U)
7834 #define DSI_GPSR_PWRFF_Msk (0x1U << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */
7835 #define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */
7836 #define DSI_GPSR_PRDFE_Pos (4U)
7837 #define DSI_GPSR_PRDFE_Msk (0x1U << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */
7838 #define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */
7839 #define DSI_GPSR_PRDFF_Pos (5U)
7840 #define DSI_GPSR_PRDFF_Msk (0x1U << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */
7841 #define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */
7842 #define DSI_GPSR_RCB_Pos (6U)
7843 #define DSI_GPSR_RCB_Msk (0x1U << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */
7844 #define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */
7845
7846 /******************* Bit definition for DSI_TCCR0 register **************/
7847 #define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
7848 #define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */
7849 #define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */
7850 #define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
7851 #define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */
7852 #define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
7853 #define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
7854 #define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */
7855 #define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
7856 #define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
7857 #define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */
7858 #define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
7859 #define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
7860 #define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */
7861 #define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
7862 #define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
7863 #define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */
7864 #define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
7865 #define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
7866 #define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */
7867 #define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
7868 #define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
7869 #define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */
7870 #define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
7871 #define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
7872 #define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */
7873 #define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
7874 #define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
7875 #define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */
7876 #define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
7877 #define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
7878 #define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */
7879 #define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
7880 #define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
7881 #define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */
7882 #define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
7883 #define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
7884 #define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */
7885 #define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
7886 #define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
7887 #define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */
7888 #define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
7889 #define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
7890 #define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */
7891 #define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
7892 #define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
7893 #define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */
7894 #define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
7895 #define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
7896 #define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */
7897 #define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
7898
7899 #define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
7900 #define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */
7901 #define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */
7902 #define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
7903 #define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */
7904 #define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
7905 #define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
7906 #define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */
7907 #define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
7908 #define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
7909 #define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */
7910 #define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
7911 #define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
7912 #define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */
7913 #define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
7914 #define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
7915 #define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */
7916 #define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
7917 #define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
7918 #define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */
7919 #define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
7920 #define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
7921 #define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */
7922 #define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
7923 #define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
7924 #define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */
7925 #define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
7926 #define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
7927 #define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */
7928 #define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
7929 #define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
7930 #define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */
7931 #define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
7932 #define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
7933 #define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */
7934 #define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
7935 #define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
7936 #define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */
7937 #define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
7938 #define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
7939 #define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */
7940 #define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
7941 #define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
7942 #define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */
7943 #define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
7944 #define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
7945 #define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */
7946 #define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
7947 #define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
7948 #define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */
7949 #define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
7950
7951 /******************* Bit definition for DSI_TCCR1 register **************/
7952 #define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
7953 #define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFU << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */
7954 #define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */
7955 #define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
7956 #define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */
7957 #define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
7958 #define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
7959 #define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */
7960 #define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
7961 #define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
7962 #define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */
7963 #define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
7964 #define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
7965 #define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */
7966 #define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
7967 #define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
7968 #define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */
7969 #define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
7970 #define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
7971 #define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */
7972 #define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
7973 #define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
7974 #define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */
7975 #define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
7976 #define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
7977 #define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */
7978 #define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
7979 #define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
7980 #define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */
7981 #define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
7982 #define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
7983 #define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */
7984 #define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
7985 #define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
7986 #define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */
7987 #define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
7988 #define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
7989 #define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */
7990 #define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
7991 #define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
7992 #define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */
7993 #define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
7994 #define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
7995 #define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */
7996 #define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
7997 #define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
7998 #define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */
7999 #define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
8000 #define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
8001 #define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */
8002 #define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
8003
8004 /******************* Bit definition for DSI_TCCR2 register **************/
8005 #define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
8006 #define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFU << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */
8007 #define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */
8008 #define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
8009 #define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */
8010 #define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
8011 #define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
8012 #define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */
8013 #define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
8014 #define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
8015 #define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */
8016 #define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
8017 #define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
8018 #define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */
8019 #define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
8020 #define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
8021 #define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */
8022 #define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
8023 #define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
8024 #define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */
8025 #define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
8026 #define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
8027 #define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */
8028 #define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
8029 #define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
8030 #define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */
8031 #define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
8032 #define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
8033 #define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */
8034 #define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
8035 #define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
8036 #define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */
8037 #define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
8038 #define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
8039 #define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */
8040 #define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
8041 #define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
8042 #define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */
8043 #define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
8044 #define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
8045 #define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */
8046 #define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
8047 #define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
8048 #define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */
8049 #define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
8050 #define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
8051 #define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */
8052 #define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
8053 #define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
8054 #define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */
8055 #define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
8056
8057 /******************* Bit definition for DSI_TCCR3 register **************/
8058 #define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
8059 #define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFU << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */
8060 #define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */
8061 #define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
8062 #define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */
8063 #define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
8064 #define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
8065 #define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */
8066 #define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
8067 #define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
8068 #define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */
8069 #define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
8070 #define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
8071 #define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */
8072 #define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
8073 #define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
8074 #define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */
8075 #define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
8076 #define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
8077 #define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */
8078 #define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
8079 #define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
8080 #define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */
8081 #define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
8082 #define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
8083 #define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */
8084 #define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
8085 #define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
8086 #define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */
8087 #define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
8088 #define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
8089 #define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */
8090 #define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
8091 #define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
8092 #define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */
8093 #define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
8094 #define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
8095 #define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */
8096 #define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
8097 #define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
8098 #define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */
8099 #define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
8100 #define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
8101 #define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */
8102 #define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
8103 #define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
8104 #define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */
8105 #define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
8106 #define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
8107 #define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */
8108 #define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
8109
8110 #define DSI_TCCR3_PM_Pos (24U)
8111 #define DSI_TCCR3_PM_Msk (0x1U << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */
8112 #define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */
8113
8114 /******************* Bit definition for DSI_TCCR4 register **************/
8115 #define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
8116 #define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFU << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */
8117 #define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */
8118 #define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
8119 #define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */
8120 #define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
8121 #define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
8122 #define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */
8123 #define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
8124 #define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
8125 #define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */
8126 #define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
8127 #define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
8128 #define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */
8129 #define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
8130 #define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
8131 #define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */
8132 #define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
8133 #define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
8134 #define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */
8135 #define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
8136 #define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
8137 #define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */
8138 #define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
8139 #define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
8140 #define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */
8141 #define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
8142 #define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
8143 #define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */
8144 #define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
8145 #define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
8146 #define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */
8147 #define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
8148 #define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
8149 #define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */
8150 #define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
8151 #define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
8152 #define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */
8153 #define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
8154 #define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
8155 #define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */
8156 #define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
8157 #define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
8158 #define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */
8159 #define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
8160 #define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
8161 #define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */
8162 #define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
8163 #define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
8164 #define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */
8165 #define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
8166
8167 /******************* Bit definition for DSI_TCCR5 register **************/
8168 #define DSI_TCCR5_BTA_TOCNT_Pos (0U)
8169 #define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFU << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */
8170 #define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */
8171 #define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
8172 #define DSI_TCCR5_BTA_TOCNT0_Msk (0x1U << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */
8173 #define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
8174 #define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
8175 #define DSI_TCCR5_BTA_TOCNT1_Msk (0x1U << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */
8176 #define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
8177 #define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
8178 #define DSI_TCCR5_BTA_TOCNT2_Msk (0x1U << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */
8179 #define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
8180 #define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
8181 #define DSI_TCCR5_BTA_TOCNT3_Msk (0x1U << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */
8182 #define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
8183 #define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
8184 #define DSI_TCCR5_BTA_TOCNT4_Msk (0x1U << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */
8185 #define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
8186 #define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
8187 #define DSI_TCCR5_BTA_TOCNT5_Msk (0x1U << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */
8188 #define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
8189 #define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
8190 #define DSI_TCCR5_BTA_TOCNT6_Msk (0x1U << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */
8191 #define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
8192 #define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
8193 #define DSI_TCCR5_BTA_TOCNT7_Msk (0x1U << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */
8194 #define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
8195 #define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
8196 #define DSI_TCCR5_BTA_TOCNT8_Msk (0x1U << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */
8197 #define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
8198 #define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
8199 #define DSI_TCCR5_BTA_TOCNT9_Msk (0x1U << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */
8200 #define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
8201 #define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
8202 #define DSI_TCCR5_BTA_TOCNT10_Msk (0x1U << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */
8203 #define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
8204 #define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
8205 #define DSI_TCCR5_BTA_TOCNT11_Msk (0x1U << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */
8206 #define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
8207 #define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
8208 #define DSI_TCCR5_BTA_TOCNT12_Msk (0x1U << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */
8209 #define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
8210 #define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
8211 #define DSI_TCCR5_BTA_TOCNT13_Msk (0x1U << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */
8212 #define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
8213 #define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
8214 #define DSI_TCCR5_BTA_TOCNT14_Msk (0x1U << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */
8215 #define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
8216 #define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
8217 #define DSI_TCCR5_BTA_TOCNT15_Msk (0x1U << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */
8218 #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
8219
8220 /******************* Bit definition for DSI_TDCR register ***************/
8221 #define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
8222 #define DSI_TDCR_3DM0 0x00000001U
8223 #define DSI_TDCR_3DM1 0x00000002U
8224
8225 #define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
8226 #define DSI_TDCR_3DF0 0x00000004U
8227 #define DSI_TDCR_3DF1 0x00000008U
8228
8229 #define DSI_TDCR_SVS_Pos (4U)
8230 #define DSI_TDCR_SVS_Msk (0x1U << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
8231 #define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */
8232 #define DSI_TDCR_RF_Pos (5U)
8233 #define DSI_TDCR_RF_Msk (0x1U << DSI_TDCR_RF_Pos) /*!< 0x00000020 */
8234 #define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */
8235 #define DSI_TDCR_S3DC_Pos (16U)
8236 #define DSI_TDCR_S3DC_Msk (0x1U << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */
8237 #define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */
8238
8239 /******************* Bit definition for DSI_CLCR register ***************/
8240 #define DSI_CLCR_DPCC_Pos (0U)
8241 #define DSI_CLCR_DPCC_Msk (0x1U << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */
8242 #define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */
8243 #define DSI_CLCR_ACR_Pos (1U)
8244 #define DSI_CLCR_ACR_Msk (0x1U << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */
8245 #define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */
8246
8247 /******************* Bit definition for DSI_CLTCR register **************/
8248 #define DSI_CLTCR_LP2HS_TIME_Pos (0U)
8249 #define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFU << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */
8250 #define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
8251 #define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
8252 #define DSI_CLTCR_LP2HS_TIME0_Msk (0x1U << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */
8253 #define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
8254 #define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
8255 #define DSI_CLTCR_LP2HS_TIME1_Msk (0x1U << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */
8256 #define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
8257 #define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
8258 #define DSI_CLTCR_LP2HS_TIME2_Msk (0x1U << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */
8259 #define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
8260 #define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
8261 #define DSI_CLTCR_LP2HS_TIME3_Msk (0x1U << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */
8262 #define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
8263 #define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
8264 #define DSI_CLTCR_LP2HS_TIME4_Msk (0x1U << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */
8265 #define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
8266 #define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
8267 #define DSI_CLTCR_LP2HS_TIME5_Msk (0x1U << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */
8268 #define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
8269 #define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
8270 #define DSI_CLTCR_LP2HS_TIME6_Msk (0x1U << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */
8271 #define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
8272 #define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
8273 #define DSI_CLTCR_LP2HS_TIME7_Msk (0x1U << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */
8274 #define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
8275 #define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
8276 #define DSI_CLTCR_LP2HS_TIME8_Msk (0x1U << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */
8277 #define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
8278 #define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
8279 #define DSI_CLTCR_LP2HS_TIME9_Msk (0x1U << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */
8280 #define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
8281
8282 #define DSI_CLTCR_HS2LP_TIME_Pos (16U)
8283 #define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFU << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */
8284 #define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
8285 #define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
8286 #define DSI_CLTCR_HS2LP_TIME0_Msk (0x1U << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */
8287 #define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
8288 #define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
8289 #define DSI_CLTCR_HS2LP_TIME1_Msk (0x1U << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */
8290 #define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
8291 #define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
8292 #define DSI_CLTCR_HS2LP_TIME2_Msk (0x1U << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */
8293 #define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
8294 #define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
8295 #define DSI_CLTCR_HS2LP_TIME3_Msk (0x1U << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */
8296 #define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
8297 #define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
8298 #define DSI_CLTCR_HS2LP_TIME4_Msk (0x1U << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */
8299 #define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
8300 #define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
8301 #define DSI_CLTCR_HS2LP_TIME5_Msk (0x1U << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */
8302 #define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
8303 #define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
8304 #define DSI_CLTCR_HS2LP_TIME6_Msk (0x1U << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */
8305 #define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
8306 #define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
8307 #define DSI_CLTCR_HS2LP_TIME7_Msk (0x1U << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */
8308 #define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
8309 #define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
8310 #define DSI_CLTCR_HS2LP_TIME8_Msk (0x1U << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */
8311 #define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
8312 #define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
8313 #define DSI_CLTCR_HS2LP_TIME9_Msk (0x1U << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */
8314 #define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
8315
8316 /******************* Bit definition for DSI_DLTCR register **************/
8317 #define DSI_DLTCR_MRD_TIME_Pos (0U)
8318 #define DSI_DLTCR_MRD_TIME_Msk (0x7FFFU << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */
8319 #define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */
8320 #define DSI_DLTCR_MRD_TIME0_Pos (0U)
8321 #define DSI_DLTCR_MRD_TIME0_Msk (0x1U << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */
8322 #define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
8323 #define DSI_DLTCR_MRD_TIME1_Pos (1U)
8324 #define DSI_DLTCR_MRD_TIME1_Msk (0x1U << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */
8325 #define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
8326 #define DSI_DLTCR_MRD_TIME2_Pos (2U)
8327 #define DSI_DLTCR_MRD_TIME2_Msk (0x1U << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */
8328 #define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
8329 #define DSI_DLTCR_MRD_TIME3_Pos (3U)
8330 #define DSI_DLTCR_MRD_TIME3_Msk (0x1U << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */
8331 #define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
8332 #define DSI_DLTCR_MRD_TIME4_Pos (4U)
8333 #define DSI_DLTCR_MRD_TIME4_Msk (0x1U << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */
8334 #define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
8335 #define DSI_DLTCR_MRD_TIME5_Pos (5U)
8336 #define DSI_DLTCR_MRD_TIME5_Msk (0x1U << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */
8337 #define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
8338 #define DSI_DLTCR_MRD_TIME6_Pos (6U)
8339 #define DSI_DLTCR_MRD_TIME6_Msk (0x1U << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */
8340 #define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
8341 #define DSI_DLTCR_MRD_TIME7_Pos (7U)
8342 #define DSI_DLTCR_MRD_TIME7_Msk (0x1U << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */
8343 #define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
8344 #define DSI_DLTCR_MRD_TIME8_Pos (8U)
8345 #define DSI_DLTCR_MRD_TIME8_Msk (0x1U << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */
8346 #define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
8347 #define DSI_DLTCR_MRD_TIME9_Pos (9U)
8348 #define DSI_DLTCR_MRD_TIME9_Msk (0x1U << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */
8349 #define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
8350 #define DSI_DLTCR_MRD_TIME10_Pos (10U)
8351 #define DSI_DLTCR_MRD_TIME10_Msk (0x1U << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */
8352 #define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
8353 #define DSI_DLTCR_MRD_TIME11_Pos (11U)
8354 #define DSI_DLTCR_MRD_TIME11_Msk (0x1U << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */
8355 #define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
8356 #define DSI_DLTCR_MRD_TIME12_Pos (12U)
8357 #define DSI_DLTCR_MRD_TIME12_Msk (0x1U << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */
8358 #define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
8359 #define DSI_DLTCR_MRD_TIME13_Pos (13U)
8360 #define DSI_DLTCR_MRD_TIME13_Msk (0x1U << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */
8361 #define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
8362 #define DSI_DLTCR_MRD_TIME14_Pos (14U)
8363 #define DSI_DLTCR_MRD_TIME14_Msk (0x1U << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */
8364 #define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
8365
8366 #define DSI_DLTCR_LP2HS_TIME_Pos (16U)
8367 #define DSI_DLTCR_LP2HS_TIME_Msk (0xFFU << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */
8368 #define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
8369 #define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
8370 #define DSI_DLTCR_LP2HS_TIME0_Msk (0x1U << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */
8371 #define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
8372 #define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
8373 #define DSI_DLTCR_LP2HS_TIME1_Msk (0x1U << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */
8374 #define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
8375 #define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
8376 #define DSI_DLTCR_LP2HS_TIME2_Msk (0x1U << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */
8377 #define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
8378 #define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
8379 #define DSI_DLTCR_LP2HS_TIME3_Msk (0x1U << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */
8380 #define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
8381 #define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
8382 #define DSI_DLTCR_LP2HS_TIME4_Msk (0x1U << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */
8383 #define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
8384 #define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
8385 #define DSI_DLTCR_LP2HS_TIME5_Msk (0x1U << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */
8386 #define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
8387 #define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
8388 #define DSI_DLTCR_LP2HS_TIME6_Msk (0x1U << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */
8389 #define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
8390 #define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
8391 #define DSI_DLTCR_LP2HS_TIME7_Msk (0x1U << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */
8392 #define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
8393
8394 #define DSI_DLTCR_HS2LP_TIME_Pos (24U)
8395 #define DSI_DLTCR_HS2LP_TIME_Msk (0xFFU << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */
8396 #define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
8397 #define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
8398 #define DSI_DLTCR_HS2LP_TIME0_Msk (0x1U << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */
8399 #define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
8400 #define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
8401 #define DSI_DLTCR_HS2LP_TIME1_Msk (0x1U << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */
8402 #define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
8403 #define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
8404 #define DSI_DLTCR_HS2LP_TIME2_Msk (0x1U << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */
8405 #define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
8406 #define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
8407 #define DSI_DLTCR_HS2LP_TIME3_Msk (0x1U << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */
8408 #define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
8409 #define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
8410 #define DSI_DLTCR_HS2LP_TIME4_Msk (0x1U << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */
8411 #define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
8412 #define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
8413 #define DSI_DLTCR_HS2LP_TIME5_Msk (0x1U << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */
8414 #define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
8415 #define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
8416 #define DSI_DLTCR_HS2LP_TIME6_Msk (0x1U << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */
8417 #define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
8418 #define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
8419 #define DSI_DLTCR_HS2LP_TIME7_Msk (0x1U << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */
8420 #define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
8421
8422 /******************* Bit definition for DSI_PCTLR register **************/
8423 #define DSI_PCTLR_DEN_Pos (1U)
8424 #define DSI_PCTLR_DEN_Msk (0x1U << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */
8425 #define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */
8426 #define DSI_PCTLR_CKE_Pos (2U)
8427 #define DSI_PCTLR_CKE_Msk (0x1U << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */
8428 #define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */
8429
8430 /******************* Bit definition for DSI_PCONFR register *************/
8431 #define DSI_PCONFR_NL_Pos (0U)
8432 #define DSI_PCONFR_NL_Msk (0x3U << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */
8433 #define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */
8434 #define DSI_PCONFR_NL0_Pos (0U)
8435 #define DSI_PCONFR_NL0_Msk (0x1U << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */
8436 #define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
8437 #define DSI_PCONFR_NL1_Pos (1U)
8438 #define DSI_PCONFR_NL1_Msk (0x1U << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */
8439 #define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
8440
8441 #define DSI_PCONFR_SW_TIME_Pos (8U)
8442 #define DSI_PCONFR_SW_TIME_Msk (0xFFU << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */
8443 #define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */
8444 #define DSI_PCONFR_SW_TIME0_Pos (8U)
8445 #define DSI_PCONFR_SW_TIME0_Msk (0x1U << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */
8446 #define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
8447 #define DSI_PCONFR_SW_TIME1_Pos (9U)
8448 #define DSI_PCONFR_SW_TIME1_Msk (0x1U << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */
8449 #define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
8450 #define DSI_PCONFR_SW_TIME2_Pos (10U)
8451 #define DSI_PCONFR_SW_TIME2_Msk (0x1U << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */
8452 #define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
8453 #define DSI_PCONFR_SW_TIME3_Pos (11U)
8454 #define DSI_PCONFR_SW_TIME3_Msk (0x1U << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */
8455 #define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
8456 #define DSI_PCONFR_SW_TIME4_Pos (12U)
8457 #define DSI_PCONFR_SW_TIME4_Msk (0x1U << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */
8458 #define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
8459 #define DSI_PCONFR_SW_TIME5_Pos (13U)
8460 #define DSI_PCONFR_SW_TIME5_Msk (0x1U << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */
8461 #define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
8462 #define DSI_PCONFR_SW_TIME6_Pos (14U)
8463 #define DSI_PCONFR_SW_TIME6_Msk (0x1U << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */
8464 #define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
8465 #define DSI_PCONFR_SW_TIME7_Pos (15U)
8466 #define DSI_PCONFR_SW_TIME7_Msk (0x1U << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */
8467 #define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
8468
8469 /******************* Bit definition for DSI_PUCR register ***************/
8470 #define DSI_PUCR_URCL_Pos (0U)
8471 #define DSI_PUCR_URCL_Msk (0x1U << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */
8472 #define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */
8473 #define DSI_PUCR_UECL_Pos (1U)
8474 #define DSI_PUCR_UECL_Msk (0x1U << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */
8475 #define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */
8476 #define DSI_PUCR_URDL_Pos (2U)
8477 #define DSI_PUCR_URDL_Msk (0x1U << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */
8478 #define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */
8479 #define DSI_PUCR_UEDL_Pos (3U)
8480 #define DSI_PUCR_UEDL_Msk (0x1U << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */
8481 #define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */
8482
8483 /******************* Bit definition for DSI_PTTCR register **************/
8484 #define DSI_PTTCR_TX_TRIG_Pos (0U)
8485 #define DSI_PTTCR_TX_TRIG_Msk (0xFU << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */
8486 #define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */
8487 #define DSI_PTTCR_TX_TRIG0_Pos (0U)
8488 #define DSI_PTTCR_TX_TRIG0_Msk (0x1U << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */
8489 #define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
8490 #define DSI_PTTCR_TX_TRIG1_Pos (1U)
8491 #define DSI_PTTCR_TX_TRIG1_Msk (0x1U << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */
8492 #define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
8493 #define DSI_PTTCR_TX_TRIG2_Pos (2U)
8494 #define DSI_PTTCR_TX_TRIG2_Msk (0x1U << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */
8495 #define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
8496 #define DSI_PTTCR_TX_TRIG3_Pos (3U)
8497 #define DSI_PTTCR_TX_TRIG3_Msk (0x1U << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */
8498 #define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
8499
8500 /******************* Bit definition for DSI_PSR register ****************/
8501 #define DSI_PSR_PD_Pos (1U)
8502 #define DSI_PSR_PD_Msk (0x1U << DSI_PSR_PD_Pos) /*!< 0x00000002 */
8503 #define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */
8504 #define DSI_PSR_PSSC_Pos (2U)
8505 #define DSI_PSR_PSSC_Msk (0x1U << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */
8506 #define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */
8507 #define DSI_PSR_UANC_Pos (3U)
8508 #define DSI_PSR_UANC_Msk (0x1U << DSI_PSR_UANC_Pos) /*!< 0x00000008 */
8509 #define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */
8510 #define DSI_PSR_PSS0_Pos (4U)
8511 #define DSI_PSR_PSS0_Msk (0x1U << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */
8512 #define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */
8513 #define DSI_PSR_UAN0_Pos (5U)
8514 #define DSI_PSR_UAN0_Msk (0x1U << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */
8515 #define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */
8516 #define DSI_PSR_RUE0_Pos (6U)
8517 #define DSI_PSR_RUE0_Msk (0x1U << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */
8518 #define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */
8519 #define DSI_PSR_PSS1_Pos (7U)
8520 #define DSI_PSR_PSS1_Msk (0x1U << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */
8521 #define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */
8522 #define DSI_PSR_UAN1_Pos (8U)
8523 #define DSI_PSR_UAN1_Msk (0x1U << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */
8524 #define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */
8525
8526 /******************* Bit definition for DSI_ISR0 register ***************/
8527 #define DSI_ISR0_AE0_Pos (0U)
8528 #define DSI_ISR0_AE0_Msk (0x1U << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */
8529 #define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */
8530 #define DSI_ISR0_AE1_Pos (1U)
8531 #define DSI_ISR0_AE1_Msk (0x1U << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */
8532 #define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */
8533 #define DSI_ISR0_AE2_Pos (2U)
8534 #define DSI_ISR0_AE2_Msk (0x1U << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */
8535 #define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */
8536 #define DSI_ISR0_AE3_Pos (3U)
8537 #define DSI_ISR0_AE3_Msk (0x1U << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */
8538 #define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */
8539 #define DSI_ISR0_AE4_Pos (4U)
8540 #define DSI_ISR0_AE4_Msk (0x1U << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */
8541 #define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */
8542 #define DSI_ISR0_AE5_Pos (5U)
8543 #define DSI_ISR0_AE5_Msk (0x1U << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */
8544 #define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */
8545 #define DSI_ISR0_AE6_Pos (6U)
8546 #define DSI_ISR0_AE6_Msk (0x1U << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */
8547 #define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */
8548 #define DSI_ISR0_AE7_Pos (7U)
8549 #define DSI_ISR0_AE7_Msk (0x1U << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */
8550 #define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */
8551 #define DSI_ISR0_AE8_Pos (8U)
8552 #define DSI_ISR0_AE8_Msk (0x1U << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */
8553 #define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */
8554 #define DSI_ISR0_AE9_Pos (9U)
8555 #define DSI_ISR0_AE9_Msk (0x1U << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */
8556 #define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */
8557 #define DSI_ISR0_AE10_Pos (10U)
8558 #define DSI_ISR0_AE10_Msk (0x1U << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */
8559 #define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */
8560 #define DSI_ISR0_AE11_Pos (11U)
8561 #define DSI_ISR0_AE11_Msk (0x1U << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */
8562 #define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */
8563 #define DSI_ISR0_AE12_Pos (12U)
8564 #define DSI_ISR0_AE12_Msk (0x1U << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */
8565 #define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */
8566 #define DSI_ISR0_AE13_Pos (13U)
8567 #define DSI_ISR0_AE13_Msk (0x1U << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */
8568 #define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */
8569 #define DSI_ISR0_AE14_Pos (14U)
8570 #define DSI_ISR0_AE14_Msk (0x1U << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */
8571 #define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */
8572 #define DSI_ISR0_AE15_Pos (15U)
8573 #define DSI_ISR0_AE15_Msk (0x1U << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */
8574 #define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */
8575 #define DSI_ISR0_PE0_Pos (16U)
8576 #define DSI_ISR0_PE0_Msk (0x1U << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */
8577 #define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */
8578 #define DSI_ISR0_PE1_Pos (17U)
8579 #define DSI_ISR0_PE1_Msk (0x1U << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */
8580 #define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */
8581 #define DSI_ISR0_PE2_Pos (18U)
8582 #define DSI_ISR0_PE2_Msk (0x1U << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */
8583 #define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */
8584 #define DSI_ISR0_PE3_Pos (19U)
8585 #define DSI_ISR0_PE3_Msk (0x1U << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */
8586 #define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */
8587 #define DSI_ISR0_PE4_Pos (20U)
8588 #define DSI_ISR0_PE4_Msk (0x1U << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */
8589 #define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */
8590
8591 /******************* Bit definition for DSI_ISR1 register ***************/
8592 #define DSI_ISR1_TOHSTX_Pos (0U)
8593 #define DSI_ISR1_TOHSTX_Msk (0x1U << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */
8594 #define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */
8595 #define DSI_ISR1_TOLPRX_Pos (1U)
8596 #define DSI_ISR1_TOLPRX_Msk (0x1U << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */
8597 #define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */
8598 #define DSI_ISR1_ECCSE_Pos (2U)
8599 #define DSI_ISR1_ECCSE_Msk (0x1U << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */
8600 #define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */
8601 #define DSI_ISR1_ECCME_Pos (3U)
8602 #define DSI_ISR1_ECCME_Msk (0x1U << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */
8603 #define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */
8604 #define DSI_ISR1_CRCE_Pos (4U)
8605 #define DSI_ISR1_CRCE_Msk (0x1U << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */
8606 #define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */
8607 #define DSI_ISR1_PSE_Pos (5U)
8608 #define DSI_ISR1_PSE_Msk (0x1U << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */
8609 #define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */
8610 #define DSI_ISR1_EOTPE_Pos (6U)
8611 #define DSI_ISR1_EOTPE_Msk (0x1U << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */
8612 #define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */
8613 #define DSI_ISR1_LPWRE_Pos (7U)
8614 #define DSI_ISR1_LPWRE_Msk (0x1U << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */
8615 #define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */
8616 #define DSI_ISR1_GCWRE_Pos (8U)
8617 #define DSI_ISR1_GCWRE_Msk (0x1U << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */
8618 #define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */
8619 #define DSI_ISR1_GPWRE_Pos (9U)
8620 #define DSI_ISR1_GPWRE_Msk (0x1U << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */
8621 #define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */
8622 #define DSI_ISR1_GPTXE_Pos (10U)
8623 #define DSI_ISR1_GPTXE_Msk (0x1U << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */
8624 #define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */
8625 #define DSI_ISR1_GPRDE_Pos (11U)
8626 #define DSI_ISR1_GPRDE_Msk (0x1U << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */
8627 #define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */
8628 #define DSI_ISR1_GPRXE_Pos (12U)
8629 #define DSI_ISR1_GPRXE_Msk (0x1U << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */
8630 #define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */
8631
8632 /******************* Bit definition for DSI_IER0 register ***************/
8633 #define DSI_IER0_AE0IE_Pos (0U)
8634 #define DSI_IER0_AE0IE_Msk (0x1U << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */
8635 #define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */
8636 #define DSI_IER0_AE1IE_Pos (1U)
8637 #define DSI_IER0_AE1IE_Msk (0x1U << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */
8638 #define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */
8639 #define DSI_IER0_AE2IE_Pos (2U)
8640 #define DSI_IER0_AE2IE_Msk (0x1U << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */
8641 #define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */
8642 #define DSI_IER0_AE3IE_Pos (3U)
8643 #define DSI_IER0_AE3IE_Msk (0x1U << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */
8644 #define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */
8645 #define DSI_IER0_AE4IE_Pos (4U)
8646 #define DSI_IER0_AE4IE_Msk (0x1U << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */
8647 #define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */
8648 #define DSI_IER0_AE5IE_Pos (5U)
8649 #define DSI_IER0_AE5IE_Msk (0x1U << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */
8650 #define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */
8651 #define DSI_IER0_AE6IE_Pos (6U)
8652 #define DSI_IER0_AE6IE_Msk (0x1U << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */
8653 #define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */
8654 #define DSI_IER0_AE7IE_Pos (7U)
8655 #define DSI_IER0_AE7IE_Msk (0x1U << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */
8656 #define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */
8657 #define DSI_IER0_AE8IE_Pos (8U)
8658 #define DSI_IER0_AE8IE_Msk (0x1U << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */
8659 #define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */
8660 #define DSI_IER0_AE9IE_Pos (9U)
8661 #define DSI_IER0_AE9IE_Msk (0x1U << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */
8662 #define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */
8663 #define DSI_IER0_AE10IE_Pos (10U)
8664 #define DSI_IER0_AE10IE_Msk (0x1U << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */
8665 #define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */
8666 #define DSI_IER0_AE11IE_Pos (11U)
8667 #define DSI_IER0_AE11IE_Msk (0x1U << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */
8668 #define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */
8669 #define DSI_IER0_AE12IE_Pos (12U)
8670 #define DSI_IER0_AE12IE_Msk (0x1U << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */
8671 #define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */
8672 #define DSI_IER0_AE13IE_Pos (13U)
8673 #define DSI_IER0_AE13IE_Msk (0x1U << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */
8674 #define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */
8675 #define DSI_IER0_AE14IE_Pos (14U)
8676 #define DSI_IER0_AE14IE_Msk (0x1U << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */
8677 #define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */
8678 #define DSI_IER0_AE15IE_Pos (15U)
8679 #define DSI_IER0_AE15IE_Msk (0x1U << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */
8680 #define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */
8681 #define DSI_IER0_PE0IE_Pos (16U)
8682 #define DSI_IER0_PE0IE_Msk (0x1U << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */
8683 #define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */
8684 #define DSI_IER0_PE1IE_Pos (17U)
8685 #define DSI_IER0_PE1IE_Msk (0x1U << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */
8686 #define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */
8687 #define DSI_IER0_PE2IE_Pos (18U)
8688 #define DSI_IER0_PE2IE_Msk (0x1U << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */
8689 #define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */
8690 #define DSI_IER0_PE3IE_Pos (19U)
8691 #define DSI_IER0_PE3IE_Msk (0x1U << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */
8692 #define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */
8693 #define DSI_IER0_PE4IE_Pos (20U)
8694 #define DSI_IER0_PE4IE_Msk (0x1U << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */
8695 #define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */
8696
8697 /******************* Bit definition for DSI_IER1 register ***************/
8698 #define DSI_IER1_TOHSTXIE_Pos (0U)
8699 #define DSI_IER1_TOHSTXIE_Msk (0x1U << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */
8700 #define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */
8701 #define DSI_IER1_TOLPRXIE_Pos (1U)
8702 #define DSI_IER1_TOLPRXIE_Msk (0x1U << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */
8703 #define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */
8704 #define DSI_IER1_ECCSEIE_Pos (2U)
8705 #define DSI_IER1_ECCSEIE_Msk (0x1U << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */
8706 #define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */
8707 #define DSI_IER1_ECCMEIE_Pos (3U)
8708 #define DSI_IER1_ECCMEIE_Msk (0x1U << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */
8709 #define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */
8710 #define DSI_IER1_CRCEIE_Pos (4U)
8711 #define DSI_IER1_CRCEIE_Msk (0x1U << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */
8712 #define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */
8713 #define DSI_IER1_PSEIE_Pos (5U)
8714 #define DSI_IER1_PSEIE_Msk (0x1U << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */
8715 #define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */
8716 #define DSI_IER1_EOTPEIE_Pos (6U)
8717 #define DSI_IER1_EOTPEIE_Msk (0x1U << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */
8718 #define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */
8719 #define DSI_IER1_LPWREIE_Pos (7U)
8720 #define DSI_IER1_LPWREIE_Msk (0x1U << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */
8721 #define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */
8722 #define DSI_IER1_GCWREIE_Pos (8U)
8723 #define DSI_IER1_GCWREIE_Msk (0x1U << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */
8724 #define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */
8725 #define DSI_IER1_GPWREIE_Pos (9U)
8726 #define DSI_IER1_GPWREIE_Msk (0x1U << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */
8727 #define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */
8728 #define DSI_IER1_GPTXEIE_Pos (10U)
8729 #define DSI_IER1_GPTXEIE_Msk (0x1U << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */
8730 #define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */
8731 #define DSI_IER1_GPRDEIE_Pos (11U)
8732 #define DSI_IER1_GPRDEIE_Msk (0x1U << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */
8733 #define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */
8734 #define DSI_IER1_GPRXEIE_Pos (12U)
8735 #define DSI_IER1_GPRXEIE_Msk (0x1U << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */
8736 #define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */
8737
8738 /******************* Bit definition for DSI_FIR0 register ***************/
8739 #define DSI_FIR0_FAE0_Pos (0U)
8740 #define DSI_FIR0_FAE0_Msk (0x1U << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */
8741 #define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */
8742 #define DSI_FIR0_FAE1_Pos (1U)
8743 #define DSI_FIR0_FAE1_Msk (0x1U << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */
8744 #define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */
8745 #define DSI_FIR0_FAE2_Pos (2U)
8746 #define DSI_FIR0_FAE2_Msk (0x1U << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */
8747 #define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */
8748 #define DSI_FIR0_FAE3_Pos (3U)
8749 #define DSI_FIR0_FAE3_Msk (0x1U << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */
8750 #define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */
8751 #define DSI_FIR0_FAE4_Pos (4U)
8752 #define DSI_FIR0_FAE4_Msk (0x1U << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */
8753 #define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */
8754 #define DSI_FIR0_FAE5_Pos (5U)
8755 #define DSI_FIR0_FAE5_Msk (0x1U << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */
8756 #define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */
8757 #define DSI_FIR0_FAE6_Pos (6U)
8758 #define DSI_FIR0_FAE6_Msk (0x1U << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */
8759 #define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */
8760 #define DSI_FIR0_FAE7_Pos (7U)
8761 #define DSI_FIR0_FAE7_Msk (0x1U << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */
8762 #define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */
8763 #define DSI_FIR0_FAE8_Pos (8U)
8764 #define DSI_FIR0_FAE8_Msk (0x1U << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */
8765 #define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */
8766 #define DSI_FIR0_FAE9_Pos (9U)
8767 #define DSI_FIR0_FAE9_Msk (0x1U << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */
8768 #define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */
8769 #define DSI_FIR0_FAE10_Pos (10U)
8770 #define DSI_FIR0_FAE10_Msk (0x1U << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */
8771 #define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */
8772 #define DSI_FIR0_FAE11_Pos (11U)
8773 #define DSI_FIR0_FAE11_Msk (0x1U << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */
8774 #define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */
8775 #define DSI_FIR0_FAE12_Pos (12U)
8776 #define DSI_FIR0_FAE12_Msk (0x1U << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */
8777 #define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */
8778 #define DSI_FIR0_FAE13_Pos (13U)
8779 #define DSI_FIR0_FAE13_Msk (0x1U << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */
8780 #define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */
8781 #define DSI_FIR0_FAE14_Pos (14U)
8782 #define DSI_FIR0_FAE14_Msk (0x1U << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */
8783 #define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */
8784 #define DSI_FIR0_FAE15_Pos (15U)
8785 #define DSI_FIR0_FAE15_Msk (0x1U << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */
8786 #define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */
8787 #define DSI_FIR0_FPE0_Pos (16U)
8788 #define DSI_FIR0_FPE0_Msk (0x1U << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */
8789 #define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */
8790 #define DSI_FIR0_FPE1_Pos (17U)
8791 #define DSI_FIR0_FPE1_Msk (0x1U << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */
8792 #define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */
8793 #define DSI_FIR0_FPE2_Pos (18U)
8794 #define DSI_FIR0_FPE2_Msk (0x1U << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */
8795 #define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */
8796 #define DSI_FIR0_FPE3_Pos (19U)
8797 #define DSI_FIR0_FPE3_Msk (0x1U << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */
8798 #define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */
8799 #define DSI_FIR0_FPE4_Pos (20U)
8800 #define DSI_FIR0_FPE4_Msk (0x1U << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */
8801 #define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */
8802
8803 /******************* Bit definition for DSI_FIR1 register ***************/
8804 #define DSI_FIR1_FTOHSTX_Pos (0U)
8805 #define DSI_FIR1_FTOHSTX_Msk (0x1U << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */
8806 #define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
8807 #define DSI_FIR1_FTOLPRX_Pos (1U)
8808 #define DSI_FIR1_FTOLPRX_Msk (0x1U << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */
8809 #define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
8810 #define DSI_FIR1_FECCSE_Pos (2U)
8811 #define DSI_FIR1_FECCSE_Msk (0x1U << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */
8812 #define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
8813 #define DSI_FIR1_FECCME_Pos (3U)
8814 #define DSI_FIR1_FECCME_Msk (0x1U << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */
8815 #define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
8816 #define DSI_FIR1_FCRCE_Pos (4U)
8817 #define DSI_FIR1_FCRCE_Msk (0x1U << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */
8818 #define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */
8819 #define DSI_FIR1_FPSE_Pos (5U)
8820 #define DSI_FIR1_FPSE_Msk (0x1U << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */
8821 #define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */
8822 #define DSI_FIR1_FEOTPE_Pos (6U)
8823 #define DSI_FIR1_FEOTPE_Msk (0x1U << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */
8824 #define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */
8825 #define DSI_FIR1_FLPWRE_Pos (7U)
8826 #define DSI_FIR1_FLPWRE_Msk (0x1U << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */
8827 #define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */
8828 #define DSI_FIR1_FGCWRE_Pos (8U)
8829 #define DSI_FIR1_FGCWRE_Msk (0x1U << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */
8830 #define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */
8831 #define DSI_FIR1_FGPWRE_Pos (9U)
8832 #define DSI_FIR1_FGPWRE_Msk (0x1U << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */
8833 #define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */
8834 #define DSI_FIR1_FGPTXE_Pos (10U)
8835 #define DSI_FIR1_FGPTXE_Msk (0x1U << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */
8836 #define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */
8837 #define DSI_FIR1_FGPRDE_Pos (11U)
8838 #define DSI_FIR1_FGPRDE_Msk (0x1U << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */
8839 #define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */
8840 #define DSI_FIR1_FGPRXE_Pos (12U)
8841 #define DSI_FIR1_FGPRXE_Msk (0x1U << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */
8842 #define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */
8843
8844 /******************* Bit definition for DSI_VSCR register ***************/
8845 #define DSI_VSCR_EN_Pos (0U)
8846 #define DSI_VSCR_EN_Msk (0x1U << DSI_VSCR_EN_Pos) /*!< 0x00000001 */
8847 #define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */
8848 #define DSI_VSCR_UR_Pos (8U)
8849 #define DSI_VSCR_UR_Msk (0x1U << DSI_VSCR_UR_Pos) /*!< 0x00000100 */
8850 #define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */
8851
8852 /******************* Bit definition for DSI_LCVCIDR register ************/
8853 #define DSI_LCVCIDR_VCID_Pos (0U)
8854 #define DSI_LCVCIDR_VCID_Msk (0x3U << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */
8855 #define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */
8856 #define DSI_LCVCIDR_VCID0_Pos (0U)
8857 #define DSI_LCVCIDR_VCID0_Msk (0x1U << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */
8858 #define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
8859 #define DSI_LCVCIDR_VCID1_Pos (1U)
8860 #define DSI_LCVCIDR_VCID1_Msk (0x1U << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */
8861 #define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
8862
8863 /******************* Bit definition for DSI_LCCCR register **************/
8864 #define DSI_LCCCR_COLC_Pos (0U)
8865 #define DSI_LCCCR_COLC_Msk (0xFU << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */
8866 #define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */
8867 #define DSI_LCCCR_COLC0_Pos (0U)
8868 #define DSI_LCCCR_COLC0_Msk (0x1U << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */
8869 #define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
8870 #define DSI_LCCCR_COLC1_Pos (1U)
8871 #define DSI_LCCCR_COLC1_Msk (0x1U << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */
8872 #define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
8873 #define DSI_LCCCR_COLC2_Pos (2U)
8874 #define DSI_LCCCR_COLC2_Msk (0x1U << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */
8875 #define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
8876 #define DSI_LCCCR_COLC3_Pos (3U)
8877 #define DSI_LCCCR_COLC3_Msk (0x1U << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */
8878 #define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
8879
8880 #define DSI_LCCCR_LPE_Pos (8U)
8881 #define DSI_LCCCR_LPE_Msk (0x1U << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */
8882 #define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */
8883
8884 /******************* Bit definition for DSI_LPMCCR register *************/
8885 #define DSI_LPMCCR_VLPSIZE_Pos (0U)
8886 #define DSI_LPMCCR_VLPSIZE_Msk (0xFFU << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */
8887 #define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
8888 #define DSI_LPMCCR_VLPSIZE0_Pos (0U)
8889 #define DSI_LPMCCR_VLPSIZE0_Msk (0x1U << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */
8890 #define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
8891 #define DSI_LPMCCR_VLPSIZE1_Pos (1U)
8892 #define DSI_LPMCCR_VLPSIZE1_Msk (0x1U << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */
8893 #define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
8894 #define DSI_LPMCCR_VLPSIZE2_Pos (2U)
8895 #define DSI_LPMCCR_VLPSIZE2_Msk (0x1U << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */
8896 #define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
8897 #define DSI_LPMCCR_VLPSIZE3_Pos (3U)
8898 #define DSI_LPMCCR_VLPSIZE3_Msk (0x1U << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */
8899 #define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
8900 #define DSI_LPMCCR_VLPSIZE4_Pos (4U)
8901 #define DSI_LPMCCR_VLPSIZE4_Msk (0x1U << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */
8902 #define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
8903 #define DSI_LPMCCR_VLPSIZE5_Pos (5U)
8904 #define DSI_LPMCCR_VLPSIZE5_Msk (0x1U << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */
8905 #define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
8906 #define DSI_LPMCCR_VLPSIZE6_Pos (6U)
8907 #define DSI_LPMCCR_VLPSIZE6_Msk (0x1U << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */
8908 #define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
8909 #define DSI_LPMCCR_VLPSIZE7_Pos (7U)
8910 #define DSI_LPMCCR_VLPSIZE7_Msk (0x1U << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */
8911 #define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
8912
8913 #define DSI_LPMCCR_LPSIZE_Pos (16U)
8914 #define DSI_LPMCCR_LPSIZE_Msk (0xFFU << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */
8915 #define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */
8916 #define DSI_LPMCCR_LPSIZE0_Pos (16U)
8917 #define DSI_LPMCCR_LPSIZE0_Msk (0x1U << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */
8918 #define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
8919 #define DSI_LPMCCR_LPSIZE1_Pos (17U)
8920 #define DSI_LPMCCR_LPSIZE1_Msk (0x1U << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */
8921 #define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
8922 #define DSI_LPMCCR_LPSIZE2_Pos (18U)
8923 #define DSI_LPMCCR_LPSIZE2_Msk (0x1U << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */
8924 #define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
8925 #define DSI_LPMCCR_LPSIZE3_Pos (19U)
8926 #define DSI_LPMCCR_LPSIZE3_Msk (0x1U << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */
8927 #define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
8928 #define DSI_LPMCCR_LPSIZE4_Pos (20U)
8929 #define DSI_LPMCCR_LPSIZE4_Msk (0x1U << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */
8930 #define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
8931 #define DSI_LPMCCR_LPSIZE5_Pos (21U)
8932 #define DSI_LPMCCR_LPSIZE5_Msk (0x1U << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */
8933 #define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
8934 #define DSI_LPMCCR_LPSIZE6_Pos (22U)
8935 #define DSI_LPMCCR_LPSIZE6_Msk (0x1U << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */
8936 #define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
8937 #define DSI_LPMCCR_LPSIZE7_Pos (23U)
8938 #define DSI_LPMCCR_LPSIZE7_Msk (0x1U << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */
8939 #define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
8940
8941 /******************* Bit definition for DSI_VMCCR register **************/
8942 #define DSI_VMCCR_VMT_Pos (0U)
8943 #define DSI_VMCCR_VMT_Msk (0x3U << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */
8944 #define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */
8945 #define DSI_VMCCR_VMT0_Pos (0U)
8946 #define DSI_VMCCR_VMT0_Msk (0x1U << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */
8947 #define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
8948 #define DSI_VMCCR_VMT1_Pos (1U)
8949 #define DSI_VMCCR_VMT1_Msk (0x1U << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */
8950 #define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
8951
8952 #define DSI_VMCCR_LPVSAE_Pos (8U)
8953 #define DSI_VMCCR_LPVSAE_Msk (0x1U << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */
8954 #define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */
8955 #define DSI_VMCCR_LPVBPE_Pos (9U)
8956 #define DSI_VMCCR_LPVBPE_Msk (0x1U << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */
8957 #define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */
8958 #define DSI_VMCCR_LPVFPE_Pos (10U)
8959 #define DSI_VMCCR_LPVFPE_Msk (0x1U << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */
8960 #define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
8961 #define DSI_VMCCR_LPVAE_Pos (11U)
8962 #define DSI_VMCCR_LPVAE_Msk (0x1U << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */
8963 #define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */
8964 #define DSI_VMCCR_LPHBPE_Pos (12U)
8965 #define DSI_VMCCR_LPHBPE_Msk (0x1U << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */
8966 #define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */
8967 #define DSI_VMCCR_LPHFE_Pos (13U)
8968 #define DSI_VMCCR_LPHFE_Msk (0x1U << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */
8969 #define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */
8970 #define DSI_VMCCR_FBTAAE_Pos (14U)
8971 #define DSI_VMCCR_FBTAAE_Msk (0x1U << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */
8972 #define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */
8973 #define DSI_VMCCR_LPCE_Pos (15U)
8974 #define DSI_VMCCR_LPCE_Msk (0x1U << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */
8975 #define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */
8976
8977 /******************* Bit definition for DSI_VPCCR register **************/
8978 #define DSI_VPCCR_VPSIZE_Pos (0U)
8979 #define DSI_VPCCR_VPSIZE_Msk (0x3FFFU << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */
8980 #define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */
8981 #define DSI_VPCCR_VPSIZE0_Pos (0U)
8982 #define DSI_VPCCR_VPSIZE0_Msk (0x1U << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */
8983 #define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
8984 #define DSI_VPCCR_VPSIZE1_Pos (1U)
8985 #define DSI_VPCCR_VPSIZE1_Msk (0x1U << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */
8986 #define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
8987 #define DSI_VPCCR_VPSIZE2_Pos (2U)
8988 #define DSI_VPCCR_VPSIZE2_Msk (0x1U << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */
8989 #define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
8990 #define DSI_VPCCR_VPSIZE3_Pos (3U)
8991 #define DSI_VPCCR_VPSIZE3_Msk (0x1U << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */
8992 #define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
8993 #define DSI_VPCCR_VPSIZE4_Pos (4U)
8994 #define DSI_VPCCR_VPSIZE4_Msk (0x1U << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */
8995 #define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
8996 #define DSI_VPCCR_VPSIZE5_Pos (5U)
8997 #define DSI_VPCCR_VPSIZE5_Msk (0x1U << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */
8998 #define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
8999 #define DSI_VPCCR_VPSIZE6_Pos (6U)
9000 #define DSI_VPCCR_VPSIZE6_Msk (0x1U << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */
9001 #define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
9002 #define DSI_VPCCR_VPSIZE7_Pos (7U)
9003 #define DSI_VPCCR_VPSIZE7_Msk (0x1U << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */
9004 #define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
9005 #define DSI_VPCCR_VPSIZE8_Pos (8U)
9006 #define DSI_VPCCR_VPSIZE8_Msk (0x1U << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */
9007 #define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
9008 #define DSI_VPCCR_VPSIZE9_Pos (9U)
9009 #define DSI_VPCCR_VPSIZE9_Msk (0x1U << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */
9010 #define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
9011 #define DSI_VPCCR_VPSIZE10_Pos (10U)
9012 #define DSI_VPCCR_VPSIZE10_Msk (0x1U << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */
9013 #define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
9014 #define DSI_VPCCR_VPSIZE11_Pos (11U)
9015 #define DSI_VPCCR_VPSIZE11_Msk (0x1U << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */
9016 #define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
9017 #define DSI_VPCCR_VPSIZE12_Pos (12U)
9018 #define DSI_VPCCR_VPSIZE12_Msk (0x1U << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */
9019 #define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
9020 #define DSI_VPCCR_VPSIZE13_Pos (13U)
9021 #define DSI_VPCCR_VPSIZE13_Msk (0x1U << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */
9022 #define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
9023
9024 /******************* Bit definition for DSI_VCCCR register **************/
9025 #define DSI_VCCCR_NUMC_Pos (0U)
9026 #define DSI_VCCCR_NUMC_Msk (0x1FFFU << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */
9027 #define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */
9028 #define DSI_VCCCR_NUMC0_Pos (0U)
9029 #define DSI_VCCCR_NUMC0_Msk (0x1U << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */
9030 #define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
9031 #define DSI_VCCCR_NUMC1_Pos (1U)
9032 #define DSI_VCCCR_NUMC1_Msk (0x1U << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */
9033 #define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
9034 #define DSI_VCCCR_NUMC2_Pos (2U)
9035 #define DSI_VCCCR_NUMC2_Msk (0x1U << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */
9036 #define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
9037 #define DSI_VCCCR_NUMC3_Pos (3U)
9038 #define DSI_VCCCR_NUMC3_Msk (0x1U << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */
9039 #define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
9040 #define DSI_VCCCR_NUMC4_Pos (4U)
9041 #define DSI_VCCCR_NUMC4_Msk (0x1U << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */
9042 #define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
9043 #define DSI_VCCCR_NUMC5_Pos (5U)
9044 #define DSI_VCCCR_NUMC5_Msk (0x1U << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */
9045 #define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
9046 #define DSI_VCCCR_NUMC6_Pos (6U)
9047 #define DSI_VCCCR_NUMC6_Msk (0x1U << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */
9048 #define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
9049 #define DSI_VCCCR_NUMC7_Pos (7U)
9050 #define DSI_VCCCR_NUMC7_Msk (0x1U << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */
9051 #define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
9052 #define DSI_VCCCR_NUMC8_Pos (8U)
9053 #define DSI_VCCCR_NUMC8_Msk (0x1U << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */
9054 #define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
9055 #define DSI_VCCCR_NUMC9_Pos (9U)
9056 #define DSI_VCCCR_NUMC9_Msk (0x1U << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */
9057 #define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
9058 #define DSI_VCCCR_NUMC10_Pos (10U)
9059 #define DSI_VCCCR_NUMC10_Msk (0x1U << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */
9060 #define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
9061 #define DSI_VCCCR_NUMC11_Pos (11U)
9062 #define DSI_VCCCR_NUMC11_Msk (0x1U << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */
9063 #define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
9064 #define DSI_VCCCR_NUMC12_Pos (12U)
9065 #define DSI_VCCCR_NUMC12_Msk (0x1U << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */
9066 #define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
9067
9068 /******************* Bit definition for DSI_VNPCCR register *************/
9069 #define DSI_VNPCCR_NPSIZE_Pos (0U)
9070 #define DSI_VNPCCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */
9071 #define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */
9072 #define DSI_VNPCCR_NPSIZE0_Pos (0U)
9073 #define DSI_VNPCCR_NPSIZE0_Msk (0x1U << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */
9074 #define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
9075 #define DSI_VNPCCR_NPSIZE1_Pos (1U)
9076 #define DSI_VNPCCR_NPSIZE1_Msk (0x1U << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */
9077 #define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
9078 #define DSI_VNPCCR_NPSIZE2_Pos (2U)
9079 #define DSI_VNPCCR_NPSIZE2_Msk (0x1U << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */
9080 #define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
9081 #define DSI_VNPCCR_NPSIZE3_Pos (3U)
9082 #define DSI_VNPCCR_NPSIZE3_Msk (0x1U << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */
9083 #define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
9084 #define DSI_VNPCCR_NPSIZE4_Pos (4U)
9085 #define DSI_VNPCCR_NPSIZE4_Msk (0x1U << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */
9086 #define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
9087 #define DSI_VNPCCR_NPSIZE5_Pos (5U)
9088 #define DSI_VNPCCR_NPSIZE5_Msk (0x1U << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */
9089 #define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
9090 #define DSI_VNPCCR_NPSIZE6_Pos (6U)
9091 #define DSI_VNPCCR_NPSIZE6_Msk (0x1U << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */
9092 #define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
9093 #define DSI_VNPCCR_NPSIZE7_Pos (7U)
9094 #define DSI_VNPCCR_NPSIZE7_Msk (0x1U << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */
9095 #define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
9096 #define DSI_VNPCCR_NPSIZE8_Pos (8U)
9097 #define DSI_VNPCCR_NPSIZE8_Msk (0x1U << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */
9098 #define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
9099 #define DSI_VNPCCR_NPSIZE9_Pos (9U)
9100 #define DSI_VNPCCR_NPSIZE9_Msk (0x1U << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */
9101 #define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
9102 #define DSI_VNPCCR_NPSIZE10_Pos (10U)
9103 #define DSI_VNPCCR_NPSIZE10_Msk (0x1U << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */
9104 #define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
9105 #define DSI_VNPCCR_NPSIZE11_Pos (11U)
9106 #define DSI_VNPCCR_NPSIZE11_Msk (0x1U << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */
9107 #define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
9108 #define DSI_VNPCCR_NPSIZE12_Pos (12U)
9109 #define DSI_VNPCCR_NPSIZE12_Msk (0x1U << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */
9110 #define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
9111
9112 /******************* Bit definition for DSI_VHSACCR register ************/
9113 #define DSI_VHSACCR_HSA_Pos (0U)
9114 #define DSI_VHSACCR_HSA_Msk (0xFFFU << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */
9115 #define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */
9116 #define DSI_VHSACCR_HSA0_Pos (0U)
9117 #define DSI_VHSACCR_HSA0_Msk (0x1U << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */
9118 #define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
9119 #define DSI_VHSACCR_HSA1_Pos (1U)
9120 #define DSI_VHSACCR_HSA1_Msk (0x1U << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */
9121 #define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
9122 #define DSI_VHSACCR_HSA2_Pos (2U)
9123 #define DSI_VHSACCR_HSA2_Msk (0x1U << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */
9124 #define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
9125 #define DSI_VHSACCR_HSA3_Pos (3U)
9126 #define DSI_VHSACCR_HSA3_Msk (0x1U << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */
9127 #define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
9128 #define DSI_VHSACCR_HSA4_Pos (4U)
9129 #define DSI_VHSACCR_HSA4_Msk (0x1U << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */
9130 #define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
9131 #define DSI_VHSACCR_HSA5_Pos (5U)
9132 #define DSI_VHSACCR_HSA5_Msk (0x1U << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */
9133 #define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
9134 #define DSI_VHSACCR_HSA6_Pos (6U)
9135 #define DSI_VHSACCR_HSA6_Msk (0x1U << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */
9136 #define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
9137 #define DSI_VHSACCR_HSA7_Pos (7U)
9138 #define DSI_VHSACCR_HSA7_Msk (0x1U << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */
9139 #define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
9140 #define DSI_VHSACCR_HSA8_Pos (8U)
9141 #define DSI_VHSACCR_HSA8_Msk (0x1U << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */
9142 #define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
9143 #define DSI_VHSACCR_HSA9_Pos (9U)
9144 #define DSI_VHSACCR_HSA9_Msk (0x1U << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */
9145 #define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
9146 #define DSI_VHSACCR_HSA10_Pos (10U)
9147 #define DSI_VHSACCR_HSA10_Msk (0x1U << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */
9148 #define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
9149 #define DSI_VHSACCR_HSA11_Pos (11U)
9150 #define DSI_VHSACCR_HSA11_Msk (0x1U << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */
9151 #define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
9152
9153 /******************* Bit definition for DSI_VHBPCCR register ************/
9154 #define DSI_VHBPCCR_HBP_Pos (0U)
9155 #define DSI_VHBPCCR_HBP_Msk (0xFFFU << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */
9156 #define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
9157 #define DSI_VHBPCCR_HBP0_Pos (0U)
9158 #define DSI_VHBPCCR_HBP0_Msk (0x1U << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */
9159 #define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
9160 #define DSI_VHBPCCR_HBP1_Pos (1U)
9161 #define DSI_VHBPCCR_HBP1_Msk (0x1U << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */
9162 #define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
9163 #define DSI_VHBPCCR_HBP2_Pos (2U)
9164 #define DSI_VHBPCCR_HBP2_Msk (0x1U << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */
9165 #define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
9166 #define DSI_VHBPCCR_HBP3_Pos (3U)
9167 #define DSI_VHBPCCR_HBP3_Msk (0x1U << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */
9168 #define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
9169 #define DSI_VHBPCCR_HBP4_Pos (4U)
9170 #define DSI_VHBPCCR_HBP4_Msk (0x1U << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */
9171 #define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
9172 #define DSI_VHBPCCR_HBP5_Pos (5U)
9173 #define DSI_VHBPCCR_HBP5_Msk (0x1U << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */
9174 #define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
9175 #define DSI_VHBPCCR_HBP6_Pos (6U)
9176 #define DSI_VHBPCCR_HBP6_Msk (0x1U << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */
9177 #define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
9178 #define DSI_VHBPCCR_HBP7_Pos (7U)
9179 #define DSI_VHBPCCR_HBP7_Msk (0x1U << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */
9180 #define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
9181 #define DSI_VHBPCCR_HBP8_Pos (8U)
9182 #define DSI_VHBPCCR_HBP8_Msk (0x1U << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */
9183 #define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
9184 #define DSI_VHBPCCR_HBP9_Pos (9U)
9185 #define DSI_VHBPCCR_HBP9_Msk (0x1U << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */
9186 #define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
9187 #define DSI_VHBPCCR_HBP10_Pos (10U)
9188 #define DSI_VHBPCCR_HBP10_Msk (0x1U << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */
9189 #define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
9190 #define DSI_VHBPCCR_HBP11_Pos (11U)
9191 #define DSI_VHBPCCR_HBP11_Msk (0x1U << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */
9192 #define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
9193
9194 /******************* Bit definition for DSI_VLCCR register **************/
9195 #define DSI_VLCCR_HLINE_Pos (0U)
9196 #define DSI_VLCCR_HLINE_Msk (0x7FFFU << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */
9197 #define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */
9198 #define DSI_VLCCR_HLINE0_Pos (0U)
9199 #define DSI_VLCCR_HLINE0_Msk (0x1U << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */
9200 #define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
9201 #define DSI_VLCCR_HLINE1_Pos (1U)
9202 #define DSI_VLCCR_HLINE1_Msk (0x1U << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */
9203 #define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
9204 #define DSI_VLCCR_HLINE2_Pos (2U)
9205 #define DSI_VLCCR_HLINE2_Msk (0x1U << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */
9206 #define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
9207 #define DSI_VLCCR_HLINE3_Pos (3U)
9208 #define DSI_VLCCR_HLINE3_Msk (0x1U << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */
9209 #define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
9210 #define DSI_VLCCR_HLINE4_Pos (4U)
9211 #define DSI_VLCCR_HLINE4_Msk (0x1U << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */
9212 #define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
9213 #define DSI_VLCCR_HLINE5_Pos (5U)
9214 #define DSI_VLCCR_HLINE5_Msk (0x1U << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */
9215 #define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
9216 #define DSI_VLCCR_HLINE6_Pos (6U)
9217 #define DSI_VLCCR_HLINE6_Msk (0x1U << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */
9218 #define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
9219 #define DSI_VLCCR_HLINE7_Pos (7U)
9220 #define DSI_VLCCR_HLINE7_Msk (0x1U << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */
9221 #define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
9222 #define DSI_VLCCR_HLINE8_Pos (8U)
9223 #define DSI_VLCCR_HLINE8_Msk (0x1U << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */
9224 #define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
9225 #define DSI_VLCCR_HLINE9_Pos (9U)
9226 #define DSI_VLCCR_HLINE9_Msk (0x1U << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */
9227 #define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
9228 #define DSI_VLCCR_HLINE10_Pos (10U)
9229 #define DSI_VLCCR_HLINE10_Msk (0x1U << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */
9230 #define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
9231 #define DSI_VLCCR_HLINE11_Pos (11U)
9232 #define DSI_VLCCR_HLINE11_Msk (0x1U << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */
9233 #define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
9234 #define DSI_VLCCR_HLINE12_Pos (12U)
9235 #define DSI_VLCCR_HLINE12_Msk (0x1U << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */
9236 #define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
9237 #define DSI_VLCCR_HLINE13_Pos (13U)
9238 #define DSI_VLCCR_HLINE13_Msk (0x1U << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */
9239 #define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
9240 #define DSI_VLCCR_HLINE14_Pos (14U)
9241 #define DSI_VLCCR_HLINE14_Msk (0x1U << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */
9242 #define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
9243
9244 /******************* Bit definition for DSI_VVSACCR register ***************/
9245 #define DSI_VVSACCR_VSA_Pos (0U)
9246 #define DSI_VVSACCR_VSA_Msk (0x3FFU << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */
9247 #define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */
9248 #define DSI_VVSACCR_VSA0_Pos (0U)
9249 #define DSI_VVSACCR_VSA0_Msk (0x1U << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */
9250 #define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
9251 #define DSI_VVSACCR_VSA1_Pos (1U)
9252 #define DSI_VVSACCR_VSA1_Msk (0x1U << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */
9253 #define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
9254 #define DSI_VVSACCR_VSA2_Pos (2U)
9255 #define DSI_VVSACCR_VSA2_Msk (0x1U << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */
9256 #define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
9257 #define DSI_VVSACCR_VSA3_Pos (3U)
9258 #define DSI_VVSACCR_VSA3_Msk (0x1U << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */
9259 #define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
9260 #define DSI_VVSACCR_VSA4_Pos (4U)
9261 #define DSI_VVSACCR_VSA4_Msk (0x1U << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */
9262 #define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
9263 #define DSI_VVSACCR_VSA5_Pos (5U)
9264 #define DSI_VVSACCR_VSA5_Msk (0x1U << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */
9265 #define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
9266 #define DSI_VVSACCR_VSA6_Pos (6U)
9267 #define DSI_VVSACCR_VSA6_Msk (0x1U << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */
9268 #define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
9269 #define DSI_VVSACCR_VSA7_Pos (7U)
9270 #define DSI_VVSACCR_VSA7_Msk (0x1U << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */
9271 #define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
9272 #define DSI_VVSACCR_VSA8_Pos (8U)
9273 #define DSI_VVSACCR_VSA8_Msk (0x1U << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */
9274 #define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
9275 #define DSI_VVSACCR_VSA9_Pos (9U)
9276 #define DSI_VVSACCR_VSA9_Msk (0x1U << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */
9277 #define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
9278
9279 /******************* Bit definition for DSI_VVBPCCR register ************/
9280 #define DSI_VVBPCCR_VBP_Pos (0U)
9281 #define DSI_VVBPCCR_VBP_Msk (0x3FFU << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */
9282 #define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */
9283 #define DSI_VVBPCCR_VBP0_Pos (0U)
9284 #define DSI_VVBPCCR_VBP0_Msk (0x1U << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */
9285 #define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
9286 #define DSI_VVBPCCR_VBP1_Pos (1U)
9287 #define DSI_VVBPCCR_VBP1_Msk (0x1U << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */
9288 #define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
9289 #define DSI_VVBPCCR_VBP2_Pos (2U)
9290 #define DSI_VVBPCCR_VBP2_Msk (0x1U << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */
9291 #define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
9292 #define DSI_VVBPCCR_VBP3_Pos (3U)
9293 #define DSI_VVBPCCR_VBP3_Msk (0x1U << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */
9294 #define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
9295 #define DSI_VVBPCCR_VBP4_Pos (4U)
9296 #define DSI_VVBPCCR_VBP4_Msk (0x1U << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */
9297 #define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
9298 #define DSI_VVBPCCR_VBP5_Pos (5U)
9299 #define DSI_VVBPCCR_VBP5_Msk (0x1U << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */
9300 #define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
9301 #define DSI_VVBPCCR_VBP6_Pos (6U)
9302 #define DSI_VVBPCCR_VBP6_Msk (0x1U << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */
9303 #define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
9304 #define DSI_VVBPCCR_VBP7_Pos (7U)
9305 #define DSI_VVBPCCR_VBP7_Msk (0x1U << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */
9306 #define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
9307 #define DSI_VVBPCCR_VBP8_Pos (8U)
9308 #define DSI_VVBPCCR_VBP8_Msk (0x1U << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */
9309 #define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
9310 #define DSI_VVBPCCR_VBP9_Pos (9U)
9311 #define DSI_VVBPCCR_VBP9_Msk (0x1U << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */
9312 #define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
9313
9314 /******************* Bit definition for DSI_VVFPCCR register ************/
9315 #define DSI_VVFPCCR_VFP_Pos (0U)
9316 #define DSI_VVFPCCR_VFP_Msk (0x3FFU << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */
9317 #define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */
9318 #define DSI_VVFPCCR_VFP0_Pos (0U)
9319 #define DSI_VVFPCCR_VFP0_Msk (0x1U << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */
9320 #define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
9321 #define DSI_VVFPCCR_VFP1_Pos (1U)
9322 #define DSI_VVFPCCR_VFP1_Msk (0x1U << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */
9323 #define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
9324 #define DSI_VVFPCCR_VFP2_Pos (2U)
9325 #define DSI_VVFPCCR_VFP2_Msk (0x1U << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */
9326 #define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
9327 #define DSI_VVFPCCR_VFP3_Pos (3U)
9328 #define DSI_VVFPCCR_VFP3_Msk (0x1U << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */
9329 #define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
9330 #define DSI_VVFPCCR_VFP4_Pos (4U)
9331 #define DSI_VVFPCCR_VFP4_Msk (0x1U << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */
9332 #define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
9333 #define DSI_VVFPCCR_VFP5_Pos (5U)
9334 #define DSI_VVFPCCR_VFP5_Msk (0x1U << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */
9335 #define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
9336 #define DSI_VVFPCCR_VFP6_Pos (6U)
9337 #define DSI_VVFPCCR_VFP6_Msk (0x1U << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */
9338 #define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
9339 #define DSI_VVFPCCR_VFP7_Pos (7U)
9340 #define DSI_VVFPCCR_VFP7_Msk (0x1U << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */
9341 #define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
9342 #define DSI_VVFPCCR_VFP8_Pos (8U)
9343 #define DSI_VVFPCCR_VFP8_Msk (0x1U << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */
9344 #define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
9345 #define DSI_VVFPCCR_VFP9_Pos (9U)
9346 #define DSI_VVFPCCR_VFP9_Msk (0x1U << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */
9347 #define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
9348
9349 /******************* Bit definition for DSI_VVACCR register *************/
9350 #define DSI_VVACCR_VA_Pos (0U)
9351 #define DSI_VVACCR_VA_Msk (0x3FFFU << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */
9352 #define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */
9353 #define DSI_VVACCR_VA0_Pos (0U)
9354 #define DSI_VVACCR_VA0_Msk (0x1U << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */
9355 #define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
9356 #define DSI_VVACCR_VA1_Pos (1U)
9357 #define DSI_VVACCR_VA1_Msk (0x1U << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */
9358 #define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
9359 #define DSI_VVACCR_VA2_Pos (2U)
9360 #define DSI_VVACCR_VA2_Msk (0x1U << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */
9361 #define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
9362 #define DSI_VVACCR_VA3_Pos (3U)
9363 #define DSI_VVACCR_VA3_Msk (0x1U << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */
9364 #define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
9365 #define DSI_VVACCR_VA4_Pos (4U)
9366 #define DSI_VVACCR_VA4_Msk (0x1U << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */
9367 #define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
9368 #define DSI_VVACCR_VA5_Pos (5U)
9369 #define DSI_VVACCR_VA5_Msk (0x1U << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */
9370 #define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
9371 #define DSI_VVACCR_VA6_Pos (6U)
9372 #define DSI_VVACCR_VA6_Msk (0x1U << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */
9373 #define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
9374 #define DSI_VVACCR_VA7_Pos (7U)
9375 #define DSI_VVACCR_VA7_Msk (0x1U << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */
9376 #define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
9377 #define DSI_VVACCR_VA8_Pos (8U)
9378 #define DSI_VVACCR_VA8_Msk (0x1U << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */
9379 #define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
9380 #define DSI_VVACCR_VA9_Pos (9U)
9381 #define DSI_VVACCR_VA9_Msk (0x1U << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */
9382 #define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
9383 #define DSI_VVACCR_VA10_Pos (10U)
9384 #define DSI_VVACCR_VA10_Msk (0x1U << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */
9385 #define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
9386 #define DSI_VVACCR_VA11_Pos (11U)
9387 #define DSI_VVACCR_VA11_Msk (0x1U << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */
9388 #define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
9389 #define DSI_VVACCR_VA12_Pos (12U)
9390 #define DSI_VVACCR_VA12_Msk (0x1U << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */
9391 #define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
9392 #define DSI_VVACCR_VA13_Pos (13U)
9393 #define DSI_VVACCR_VA13_Msk (0x1U << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */
9394 #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
9395
9396 /******************* Bit definition for DSI_TDCCR register **************/
9397 #define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
9398 #define DSI_TDCCR_3DM0 0x00000001U
9399 #define DSI_TDCCR_3DM1 0x00000002U
9400
9401 #define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
9402 #define DSI_TDCCR_3DF0 0x00000004U
9403 #define DSI_TDCCR_3DF1 0x00000008U
9404
9405 #define DSI_TDCCR_SVS_Pos (4U)
9406 #define DSI_TDCCR_SVS_Msk (0x1U << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
9407 #define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */
9408 #define DSI_TDCCR_RF_Pos (5U)
9409 #define DSI_TDCCR_RF_Msk (0x1U << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */
9410 #define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */
9411 #define DSI_TDCCR_S3DC_Pos (16U)
9412 #define DSI_TDCCR_S3DC_Msk (0x1U << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */
9413 #define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */
9414
9415 /******************* Bit definition for DSI_WCFGR register ***************/
9416 #define DSI_WCFGR_DSIM_Pos (0U)
9417 #define DSI_WCFGR_DSIM_Msk (0x1U << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */
9418 #define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */
9419 #define DSI_WCFGR_COLMUX_Pos (1U)
9420 #define DSI_WCFGR_COLMUX_Msk (0x7U << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */
9421 #define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */
9422 #define DSI_WCFGR_COLMUX0_Pos (1U)
9423 #define DSI_WCFGR_COLMUX0_Msk (0x1U << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */
9424 #define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
9425 #define DSI_WCFGR_COLMUX1_Pos (2U)
9426 #define DSI_WCFGR_COLMUX1_Msk (0x1U << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */
9427 #define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
9428 #define DSI_WCFGR_COLMUX2_Pos (3U)
9429 #define DSI_WCFGR_COLMUX2_Msk (0x1U << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */
9430 #define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
9431
9432 #define DSI_WCFGR_TESRC_Pos (4U)
9433 #define DSI_WCFGR_TESRC_Msk (0x1U << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */
9434 #define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */
9435 #define DSI_WCFGR_TEPOL_Pos (5U)
9436 #define DSI_WCFGR_TEPOL_Msk (0x1U << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */
9437 #define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */
9438 #define DSI_WCFGR_AR_Pos (6U)
9439 #define DSI_WCFGR_AR_Msk (0x1U << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */
9440 #define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */
9441 #define DSI_WCFGR_VSPOL_Pos (7U)
9442 #define DSI_WCFGR_VSPOL_Msk (0x1U << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */
9443 #define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */
9444
9445 /******************* Bit definition for DSI_WCR register *****************/
9446 #define DSI_WCR_COLM_Pos (0U)
9447 #define DSI_WCR_COLM_Msk (0x1U << DSI_WCR_COLM_Pos) /*!< 0x00000001 */
9448 #define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */
9449 #define DSI_WCR_SHTDN_Pos (1U)
9450 #define DSI_WCR_SHTDN_Msk (0x1U << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */
9451 #define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */
9452 #define DSI_WCR_LTDCEN_Pos (2U)
9453 #define DSI_WCR_LTDCEN_Msk (0x1U << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */
9454 #define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */
9455 #define DSI_WCR_DSIEN_Pos (3U)
9456 #define DSI_WCR_DSIEN_Msk (0x1U << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */
9457 #define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */
9458
9459 /******************* Bit definition for DSI_WIER register ****************/
9460 #define DSI_WIER_TEIE_Pos (0U)
9461 #define DSI_WIER_TEIE_Msk (0x1U << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */
9462 #define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */
9463 #define DSI_WIER_ERIE_Pos (1U)
9464 #define DSI_WIER_ERIE_Msk (0x1U << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */
9465 #define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */
9466 #define DSI_WIER_PLLLIE_Pos (9U)
9467 #define DSI_WIER_PLLLIE_Msk (0x1U << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */
9468 #define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */
9469 #define DSI_WIER_PLLUIE_Pos (10U)
9470 #define DSI_WIER_PLLUIE_Msk (0x1U << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */
9471 #define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */
9472 #define DSI_WIER_RRIE_Pos (13U)
9473 #define DSI_WIER_RRIE_Msk (0x1U << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */
9474 #define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */
9475
9476 /******************* Bit definition for DSI_WISR register ****************/
9477 #define DSI_WISR_TEIF_Pos (0U)
9478 #define DSI_WISR_TEIF_Msk (0x1U << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */
9479 #define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */
9480 #define DSI_WISR_ERIF_Pos (1U)
9481 #define DSI_WISR_ERIF_Msk (0x1U << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */
9482 #define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */
9483 #define DSI_WISR_BUSY_Pos (2U)
9484 #define DSI_WISR_BUSY_Msk (0x1U << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */
9485 #define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */
9486 #define DSI_WISR_PLLLS_Pos (8U)
9487 #define DSI_WISR_PLLLS_Msk (0x1U << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */
9488 #define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */
9489 #define DSI_WISR_PLLLIF_Pos (9U)
9490 #define DSI_WISR_PLLLIF_Msk (0x1U << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */
9491 #define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */
9492 #define DSI_WISR_PLLUIF_Pos (10U)
9493 #define DSI_WISR_PLLUIF_Msk (0x1U << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */
9494 #define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */
9495 #define DSI_WISR_RRS_Pos (12U)
9496 #define DSI_WISR_RRS_Msk (0x1U << DSI_WISR_RRS_Pos) /*!< 0x00001000 */
9497 #define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */
9498 #define DSI_WISR_RRIF_Pos (13U)
9499 #define DSI_WISR_RRIF_Msk (0x1U << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */
9500 #define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */
9501
9502 /******************* Bit definition for DSI_WIFCR register ***************/
9503 #define DSI_WIFCR_CTEIF_Pos (0U)
9504 #define DSI_WIFCR_CTEIF_Msk (0x1U << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */
9505 #define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */
9506 #define DSI_WIFCR_CERIF_Pos (1U)
9507 #define DSI_WIFCR_CERIF_Msk (0x1U << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */
9508 #define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */
9509 #define DSI_WIFCR_CPLLLIF_Pos (9U)
9510 #define DSI_WIFCR_CPLLLIF_Msk (0x1U << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */
9511 #define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */
9512 #define DSI_WIFCR_CPLLUIF_Pos (10U)
9513 #define DSI_WIFCR_CPLLUIF_Msk (0x1U << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */
9514 #define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */
9515 #define DSI_WIFCR_CRRIF_Pos (13U)
9516 #define DSI_WIFCR_CRRIF_Msk (0x1U << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */
9517 #define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */
9518
9519 /******************* Bit definition for DSI_WPCR0 register ***************/
9520 #define DSI_WPCR0_UIX4_Pos (0U)
9521 #define DSI_WPCR0_UIX4_Msk (0x3FU << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */
9522 #define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */
9523 #define DSI_WPCR0_UIX4_0 (0x01U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */
9524 #define DSI_WPCR0_UIX4_1 (0x02U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */
9525 #define DSI_WPCR0_UIX4_2 (0x04U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */
9526 #define DSI_WPCR0_UIX4_3 (0x08U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */
9527 #define DSI_WPCR0_UIX4_4 (0x10U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */
9528 #define DSI_WPCR0_UIX4_5 (0x20U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */
9529
9530 #define DSI_WPCR0_SWCL_Pos (6U)
9531 #define DSI_WPCR0_SWCL_Msk (0x1U << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */
9532 #define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */
9533 #define DSI_WPCR0_SWDL0_Pos (7U)
9534 #define DSI_WPCR0_SWDL0_Msk (0x1U << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */
9535 #define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */
9536 #define DSI_WPCR0_SWDL1_Pos (8U)
9537 #define DSI_WPCR0_SWDL1_Msk (0x1U << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */
9538 #define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */
9539 #define DSI_WPCR0_HSICL_Pos (9U)
9540 #define DSI_WPCR0_HSICL_Msk (0x1U << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */
9541 #define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */
9542 #define DSI_WPCR0_HSIDL0_Pos (10U)
9543 #define DSI_WPCR0_HSIDL0_Msk (0x1U << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */
9544 #define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */
9545 #define DSI_WPCR0_HSIDL1_Pos (11U)
9546 #define DSI_WPCR0_HSIDL1_Msk (0x1U << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */
9547 #define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */
9548 #define DSI_WPCR0_FTXSMCL_Pos (12U)
9549 #define DSI_WPCR0_FTXSMCL_Msk (0x1U << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */
9550 #define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */
9551 #define DSI_WPCR0_FTXSMDL_Pos (13U)
9552 #define DSI_WPCR0_FTXSMDL_Msk (0x1U << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */
9553 #define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */
9554 #define DSI_WPCR0_CDOFFDL_Pos (14U)
9555 #define DSI_WPCR0_CDOFFDL_Msk (0x1U << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */
9556 #define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */
9557 #define DSI_WPCR0_TDDL_Pos (16U)
9558 #define DSI_WPCR0_TDDL_Msk (0x1U << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */
9559 #define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */
9560 #define DSI_WPCR0_PDEN_Pos (18U)
9561 #define DSI_WPCR0_PDEN_Msk (0x1U << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */
9562 #define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */
9563 #define DSI_WPCR0_TCLKPREPEN_Pos (19U)
9564 #define DSI_WPCR0_TCLKPREPEN_Msk (0x1U << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */
9565 #define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */
9566 #define DSI_WPCR0_TCLKZEROEN_Pos (20U)
9567 #define DSI_WPCR0_TCLKZEROEN_Msk (0x1U << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */
9568 #define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */
9569 #define DSI_WPCR0_THSPREPEN_Pos (21U)
9570 #define DSI_WPCR0_THSPREPEN_Msk (0x1U << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */
9571 #define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */
9572 #define DSI_WPCR0_THSTRAILEN_Pos (22U)
9573 #define DSI_WPCR0_THSTRAILEN_Msk (0x1U << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */
9574 #define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */
9575 #define DSI_WPCR0_THSZEROEN_Pos (23U)
9576 #define DSI_WPCR0_THSZEROEN_Msk (0x1U << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */
9577 #define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */
9578 #define DSI_WPCR0_TLPXDEN_Pos (24U)
9579 #define DSI_WPCR0_TLPXDEN_Msk (0x1U << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */
9580 #define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */
9581 #define DSI_WPCR0_THSEXITEN_Pos (25U)
9582 #define DSI_WPCR0_THSEXITEN_Msk (0x1U << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */
9583 #define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */
9584 #define DSI_WPCR0_TLPXCEN_Pos (26U)
9585 #define DSI_WPCR0_TLPXCEN_Msk (0x1U << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */
9586 #define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */
9587 #define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
9588 #define DSI_WPCR0_TCLKPOSTEN_Msk (0x1U << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */
9589 #define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */
9590
9591 /******************* Bit definition for DSI_WPCR1 register ***************/
9592 #define DSI_WPCR1_HSTXDCL_Pos (0U)
9593 #define DSI_WPCR1_HSTXDCL_Msk (0x3U << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */
9594 #define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
9595 #define DSI_WPCR1_HSTXDCL0_Pos (0U)
9596 #define DSI_WPCR1_HSTXDCL0_Msk (0x1U << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */
9597 #define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
9598 #define DSI_WPCR1_HSTXDCL1_Pos (1U)
9599 #define DSI_WPCR1_HSTXDCL1_Msk (0x1U << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */
9600 #define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
9601
9602 #define DSI_WPCR1_HSTXDDL_Pos (2U)
9603 #define DSI_WPCR1_HSTXDDL_Msk (0x3U << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */
9604 #define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
9605 #define DSI_WPCR1_HSTXDDL0_Pos (2U)
9606 #define DSI_WPCR1_HSTXDDL0_Msk (0x1U << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */
9607 #define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
9608 #define DSI_WPCR1_HSTXDDL1_Pos (3U)
9609 #define DSI_WPCR1_HSTXDDL1_Msk (0x1U << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */
9610 #define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
9611
9612 #define DSI_WPCR1_LPSRCCL_Pos (6U)
9613 #define DSI_WPCR1_LPSRCCL_Msk (0x3U << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */
9614 #define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
9615 #define DSI_WPCR1_LPSRCCL0_Pos (6U)
9616 #define DSI_WPCR1_LPSRCCL0_Msk (0x1U << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */
9617 #define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
9618 #define DSI_WPCR1_LPSRCCL1_Pos (7U)
9619 #define DSI_WPCR1_LPSRCCL1_Msk (0x1U << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */
9620 #define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
9621
9622 #define DSI_WPCR1_LPSRCDL_Pos (8U)
9623 #define DSI_WPCR1_LPSRCDL_Msk (0x3U << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */
9624 #define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
9625 #define DSI_WPCR1_LPSRCDL0_Pos (8U)
9626 #define DSI_WPCR1_LPSRCDL0_Msk (0x1U << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */
9627 #define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
9628 #define DSI_WPCR1_LPSRCDL1_Pos (9U)
9629 #define DSI_WPCR1_LPSRCDL1_Msk (0x1U << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */
9630 #define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
9631
9632 #define DSI_WPCR1_SDDC_Pos (12U)
9633 #define DSI_WPCR1_SDDC_Msk (0x1U << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */
9634 #define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */
9635
9636 #define DSI_WPCR1_LPRXVCDL_Pos (14U)
9637 #define DSI_WPCR1_LPRXVCDL_Msk (0x3U << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */
9638 #define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */
9639 #define DSI_WPCR1_LPRXVCDL0_Pos (14U)
9640 #define DSI_WPCR1_LPRXVCDL0_Msk (0x1U << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */
9641 #define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
9642 #define DSI_WPCR1_LPRXVCDL1_Pos (15U)
9643 #define DSI_WPCR1_LPRXVCDL1_Msk (0x1U << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */
9644 #define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
9645
9646 #define DSI_WPCR1_HSTXSRCCL_Pos (16U)
9647 #define DSI_WPCR1_HSTXSRCCL_Msk (0x3U << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */
9648 #define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
9649 #define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
9650 #define DSI_WPCR1_HSTXSRCCL0_Msk (0x1U << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */
9651 #define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
9652 #define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
9653 #define DSI_WPCR1_HSTXSRCCL1_Msk (0x1U << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */
9654 #define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
9655
9656 #define DSI_WPCR1_HSTXSRCDL_Pos (18U)
9657 #define DSI_WPCR1_HSTXSRCDL_Msk (0x3U << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */
9658 #define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
9659 #define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
9660 #define DSI_WPCR1_HSTXSRCDL0_Msk (0x1U << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */
9661 #define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
9662 #define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
9663 #define DSI_WPCR1_HSTXSRCDL1_Msk (0x1U << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */
9664 #define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
9665
9666 #define DSI_WPCR1_FLPRXLPM_Pos (22U)
9667 #define DSI_WPCR1_FLPRXLPM_Msk (0x1U << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */
9668 #define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
9669
9670 #define DSI_WPCR1_LPRXFT_Pos (25U)
9671 #define DSI_WPCR1_LPRXFT_Msk (0x3U << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */
9672 #define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */
9673 #define DSI_WPCR1_LPRXFT0_Pos (25U)
9674 #define DSI_WPCR1_LPRXFT0_Msk (0x1U << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */
9675 #define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
9676 #define DSI_WPCR1_LPRXFT1_Pos (26U)
9677 #define DSI_WPCR1_LPRXFT1_Msk (0x1U << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */
9678 #define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
9679
9680 /******************* Bit definition for DSI_WPCR2 register ***************/
9681 #define DSI_WPCR2_TCLKPREP_Pos (0U)
9682 #define DSI_WPCR2_TCLKPREP_Msk (0xFFU << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */
9683 #define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
9684 #define DSI_WPCR2_TCLKPREP0_Pos (0U)
9685 #define DSI_WPCR2_TCLKPREP0_Msk (0x1U << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */
9686 #define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
9687 #define DSI_WPCR2_TCLKPREP1_Pos (1U)
9688 #define DSI_WPCR2_TCLKPREP1_Msk (0x1U << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */
9689 #define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
9690 #define DSI_WPCR2_TCLKPREP2_Pos (2U)
9691 #define DSI_WPCR2_TCLKPREP2_Msk (0x1U << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */
9692 #define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
9693 #define DSI_WPCR2_TCLKPREP3_Pos (3U)
9694 #define DSI_WPCR2_TCLKPREP3_Msk (0x1U << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */
9695 #define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
9696 #define DSI_WPCR2_TCLKPREP4_Pos (4U)
9697 #define DSI_WPCR2_TCLKPREP4_Msk (0x1U << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */
9698 #define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
9699 #define DSI_WPCR2_TCLKPREP5_Pos (5U)
9700 #define DSI_WPCR2_TCLKPREP5_Msk (0x1U << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */
9701 #define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
9702 #define DSI_WPCR2_TCLKPREP6_Pos (6U)
9703 #define DSI_WPCR2_TCLKPREP6_Msk (0x1U << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */
9704 #define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
9705 #define DSI_WPCR2_TCLKPREP7_Pos (7U)
9706 #define DSI_WPCR2_TCLKPREP7_Msk (0x1U << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */
9707 #define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
9708
9709 #define DSI_WPCR2_TCLKZERO_Pos (8U)
9710 #define DSI_WPCR2_TCLKZERO_Msk (0xFFU << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */
9711 #define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
9712 #define DSI_WPCR2_TCLKZERO0_Pos (8U)
9713 #define DSI_WPCR2_TCLKZERO0_Msk (0x1U << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */
9714 #define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
9715 #define DSI_WPCR2_TCLKZERO1_Pos (9U)
9716 #define DSI_WPCR2_TCLKZERO1_Msk (0x1U << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */
9717 #define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
9718 #define DSI_WPCR2_TCLKZERO2_Pos (10U)
9719 #define DSI_WPCR2_TCLKZERO2_Msk (0x1U << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */
9720 #define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
9721 #define DSI_WPCR2_TCLKZERO3_Pos (11U)
9722 #define DSI_WPCR2_TCLKZERO3_Msk (0x1U << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */
9723 #define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
9724 #define DSI_WPCR2_TCLKZERO4_Pos (12U)
9725 #define DSI_WPCR2_TCLKZERO4_Msk (0x1U << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */
9726 #define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
9727 #define DSI_WPCR2_TCLKZERO5_Pos (13U)
9728 #define DSI_WPCR2_TCLKZERO5_Msk (0x1U << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */
9729 #define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
9730 #define DSI_WPCR2_TCLKZERO6_Pos (14U)
9731 #define DSI_WPCR2_TCLKZERO6_Msk (0x1U << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */
9732 #define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
9733 #define DSI_WPCR2_TCLKZERO7_Pos (15U)
9734 #define DSI_WPCR2_TCLKZERO7_Msk (0x1U << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */
9735 #define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
9736
9737 #define DSI_WPCR2_THSPREP_Pos (16U)
9738 #define DSI_WPCR2_THSPREP_Msk (0xFFU << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */
9739 #define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
9740 #define DSI_WPCR2_THSPREP0_Pos (16U)
9741 #define DSI_WPCR2_THSPREP0_Msk (0x1U << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */
9742 #define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
9743 #define DSI_WPCR2_THSPREP1_Pos (17U)
9744 #define DSI_WPCR2_THSPREP1_Msk (0x1U << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */
9745 #define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
9746 #define DSI_WPCR2_THSPREP2_Pos (18U)
9747 #define DSI_WPCR2_THSPREP2_Msk (0x1U << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */
9748 #define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
9749 #define DSI_WPCR2_THSPREP3_Pos (19U)
9750 #define DSI_WPCR2_THSPREP3_Msk (0x1U << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */
9751 #define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
9752 #define DSI_WPCR2_THSPREP4_Pos (20U)
9753 #define DSI_WPCR2_THSPREP4_Msk (0x1U << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */
9754 #define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
9755 #define DSI_WPCR2_THSPREP5_Pos (21U)
9756 #define DSI_WPCR2_THSPREP5_Msk (0x1U << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */
9757 #define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
9758 #define DSI_WPCR2_THSPREP6_Pos (22U)
9759 #define DSI_WPCR2_THSPREP6_Msk (0x1U << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */
9760 #define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
9761 #define DSI_WPCR2_THSPREP7_Pos (23U)
9762 #define DSI_WPCR2_THSPREP7_Msk (0x1U << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */
9763 #define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
9764
9765 #define DSI_WPCR2_THSTRAIL_Pos (24U)
9766 #define DSI_WPCR2_THSTRAIL_Msk (0xFFU << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */
9767 #define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
9768 #define DSI_WPCR2_THSTRAIL0_Pos (24U)
9769 #define DSI_WPCR2_THSTRAIL0_Msk (0x1U << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */
9770 #define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
9771 #define DSI_WPCR2_THSTRAIL1_Pos (25U)
9772 #define DSI_WPCR2_THSTRAIL1_Msk (0x1U << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */
9773 #define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
9774 #define DSI_WPCR2_THSTRAIL2_Pos (26U)
9775 #define DSI_WPCR2_THSTRAIL2_Msk (0x1U << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */
9776 #define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
9777 #define DSI_WPCR2_THSTRAIL3_Pos (27U)
9778 #define DSI_WPCR2_THSTRAIL3_Msk (0x1U << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */
9779 #define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
9780 #define DSI_WPCR2_THSTRAIL4_Pos (28U)
9781 #define DSI_WPCR2_THSTRAIL4_Msk (0x1U << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */
9782 #define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
9783 #define DSI_WPCR2_THSTRAIL5_Pos (29U)
9784 #define DSI_WPCR2_THSTRAIL5_Msk (0x1U << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */
9785 #define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
9786 #define DSI_WPCR2_THSTRAIL6_Pos (30U)
9787 #define DSI_WPCR2_THSTRAIL6_Msk (0x1U << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */
9788 #define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
9789 #define DSI_WPCR2_THSTRAIL7_Pos (31U)
9790 #define DSI_WPCR2_THSTRAIL7_Msk (0x1U << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */
9791 #define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
9792
9793 /******************* Bit definition for DSI_WPCR3 register ***************/
9794 #define DSI_WPCR3_THSZERO_Pos (0U)
9795 #define DSI_WPCR3_THSZERO_Msk (0xFFU << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */
9796 #define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
9797 #define DSI_WPCR3_THSZERO0_Pos (0U)
9798 #define DSI_WPCR3_THSZERO0_Msk (0x1U << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */
9799 #define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
9800 #define DSI_WPCR3_THSZERO1_Pos (1U)
9801 #define DSI_WPCR3_THSZERO1_Msk (0x1U << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */
9802 #define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
9803 #define DSI_WPCR3_THSZERO2_Pos (2U)
9804 #define DSI_WPCR3_THSZERO2_Msk (0x1U << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */
9805 #define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
9806 #define DSI_WPCR3_THSZERO3_Pos (3U)
9807 #define DSI_WPCR3_THSZERO3_Msk (0x1U << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */
9808 #define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
9809 #define DSI_WPCR3_THSZERO4_Pos (4U)
9810 #define DSI_WPCR3_THSZERO4_Msk (0x1U << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */
9811 #define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
9812 #define DSI_WPCR3_THSZERO5_Pos (5U)
9813 #define DSI_WPCR3_THSZERO5_Msk (0x1U << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */
9814 #define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
9815 #define DSI_WPCR3_THSZERO6_Pos (6U)
9816 #define DSI_WPCR3_THSZERO6_Msk (0x1U << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */
9817 #define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
9818 #define DSI_WPCR3_THSZERO7_Pos (7U)
9819 #define DSI_WPCR3_THSZERO7_Msk (0x1U << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */
9820 #define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
9821
9822 #define DSI_WPCR3_TLPXD_Pos (8U)
9823 #define DSI_WPCR3_TLPXD_Msk (0xFFU << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */
9824 #define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
9825 #define DSI_WPCR3_TLPXD0_Pos (8U)
9826 #define DSI_WPCR3_TLPXD0_Msk (0x1U << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */
9827 #define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
9828 #define DSI_WPCR3_TLPXD1_Pos (9U)
9829 #define DSI_WPCR3_TLPXD1_Msk (0x1U << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */
9830 #define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
9831 #define DSI_WPCR3_TLPXD2_Pos (10U)
9832 #define DSI_WPCR3_TLPXD2_Msk (0x1U << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */
9833 #define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
9834 #define DSI_WPCR3_TLPXD3_Pos (11U)
9835 #define DSI_WPCR3_TLPXD3_Msk (0x1U << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */
9836 #define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
9837 #define DSI_WPCR3_TLPXD4_Pos (12U)
9838 #define DSI_WPCR3_TLPXD4_Msk (0x1U << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */
9839 #define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
9840 #define DSI_WPCR3_TLPXD5_Pos (13U)
9841 #define DSI_WPCR3_TLPXD5_Msk (0x1U << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */
9842 #define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
9843 #define DSI_WPCR3_TLPXD6_Pos (14U)
9844 #define DSI_WPCR3_TLPXD6_Msk (0x1U << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */
9845 #define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
9846 #define DSI_WPCR3_TLPXD7_Pos (15U)
9847 #define DSI_WPCR3_TLPXD7_Msk (0x1U << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */
9848 #define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
9849
9850 #define DSI_WPCR3_THSEXIT_Pos (16U)
9851 #define DSI_WPCR3_THSEXIT_Msk (0xFFU << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */
9852 #define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
9853 #define DSI_WPCR3_THSEXIT0_Pos (16U)
9854 #define DSI_WPCR3_THSEXIT0_Msk (0x1U << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */
9855 #define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
9856 #define DSI_WPCR3_THSEXIT1_Pos (17U)
9857 #define DSI_WPCR3_THSEXIT1_Msk (0x1U << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */
9858 #define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
9859 #define DSI_WPCR3_THSEXIT2_Pos (18U)
9860 #define DSI_WPCR3_THSEXIT2_Msk (0x1U << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */
9861 #define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
9862 #define DSI_WPCR3_THSEXIT3_Pos (19U)
9863 #define DSI_WPCR3_THSEXIT3_Msk (0x1U << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */
9864 #define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
9865 #define DSI_WPCR3_THSEXIT4_Pos (20U)
9866 #define DSI_WPCR3_THSEXIT4_Msk (0x1U << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */
9867 #define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
9868 #define DSI_WPCR3_THSEXIT5_Pos (21U)
9869 #define DSI_WPCR3_THSEXIT5_Msk (0x1U << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */
9870 #define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
9871 #define DSI_WPCR3_THSEXIT6_Pos (22U)
9872 #define DSI_WPCR3_THSEXIT6_Msk (0x1U << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */
9873 #define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
9874 #define DSI_WPCR3_THSEXIT7_Pos (23U)
9875 #define DSI_WPCR3_THSEXIT7_Msk (0x1U << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */
9876 #define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
9877
9878 #define DSI_WPCR3_TLPXC_Pos (24U)
9879 #define DSI_WPCR3_TLPXC_Msk (0xFFU << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */
9880 #define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
9881 #define DSI_WPCR3_TLPXC0_Pos (24U)
9882 #define DSI_WPCR3_TLPXC0_Msk (0x1U << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */
9883 #define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
9884 #define DSI_WPCR3_TLPXC1_Pos (25U)
9885 #define DSI_WPCR3_TLPXC1_Msk (0x1U << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */
9886 #define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
9887 #define DSI_WPCR3_TLPXC2_Pos (26U)
9888 #define DSI_WPCR3_TLPXC2_Msk (0x1U << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */
9889 #define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
9890 #define DSI_WPCR3_TLPXC3_Pos (27U)
9891 #define DSI_WPCR3_TLPXC3_Msk (0x1U << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */
9892 #define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
9893 #define DSI_WPCR3_TLPXC4_Pos (28U)
9894 #define DSI_WPCR3_TLPXC4_Msk (0x1U << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */
9895 #define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
9896 #define DSI_WPCR3_TLPXC5_Pos (29U)
9897 #define DSI_WPCR3_TLPXC5_Msk (0x1U << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */
9898 #define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
9899 #define DSI_WPCR3_TLPXC6_Pos (30U)
9900 #define DSI_WPCR3_TLPXC6_Msk (0x1U << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */
9901 #define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
9902 #define DSI_WPCR3_TLPXC7_Pos (31U)
9903 #define DSI_WPCR3_TLPXC7_Msk (0x1U << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */
9904 #define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
9905
9906 /******************* Bit definition for DSI_WPCR4 register ***************/
9907 #define DSI_WPCR4_TCLKPOST_Pos (0U)
9908 #define DSI_WPCR4_TCLKPOST_Msk (0xFFU << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */
9909 #define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
9910 #define DSI_WPCR4_TCLKPOST0_Pos (0U)
9911 #define DSI_WPCR4_TCLKPOST0_Msk (0x1U << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */
9912 #define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
9913 #define DSI_WPCR4_TCLKPOST1_Pos (1U)
9914 #define DSI_WPCR4_TCLKPOST1_Msk (0x1U << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */
9915 #define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
9916 #define DSI_WPCR4_TCLKPOST2_Pos (2U)
9917 #define DSI_WPCR4_TCLKPOST2_Msk (0x1U << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */
9918 #define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
9919 #define DSI_WPCR4_TCLKPOST3_Pos (3U)
9920 #define DSI_WPCR4_TCLKPOST3_Msk (0x1U << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */
9921 #define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
9922 #define DSI_WPCR4_TCLKPOST4_Pos (4U)
9923 #define DSI_WPCR4_TCLKPOST4_Msk (0x1U << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */
9924 #define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
9925 #define DSI_WPCR4_TCLKPOST5_Pos (5U)
9926 #define DSI_WPCR4_TCLKPOST5_Msk (0x1U << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */
9927 #define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
9928 #define DSI_WPCR4_TCLKPOST6_Pos (6U)
9929 #define DSI_WPCR4_TCLKPOST6_Msk (0x1U << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */
9930 #define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
9931 #define DSI_WPCR4_TCLKPOST7_Pos (7U)
9932 #define DSI_WPCR4_TCLKPOST7_Msk (0x1U << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */
9933 #define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
9934
9935 /******************* Bit definition for DSI_WRPCR register ***************/
9936 #define DSI_WRPCR_PLLEN_Pos (0U)
9937 #define DSI_WRPCR_PLLEN_Msk (0x1U << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */
9938 #define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */
9939 #define DSI_WRPCR_PLL_NDIV_Pos (2U)
9940 #define DSI_WRPCR_PLL_NDIV_Msk (0x7FU << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */
9941 #define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */
9942 #define DSI_WRPCR_PLL_NDIV0_Pos (2U)
9943 #define DSI_WRPCR_PLL_NDIV0_Msk (0x1U << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */
9944 #define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
9945 #define DSI_WRPCR_PLL_NDIV1_Pos (3U)
9946 #define DSI_WRPCR_PLL_NDIV1_Msk (0x1U << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */
9947 #define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
9948 #define DSI_WRPCR_PLL_NDIV2_Pos (4U)
9949 #define DSI_WRPCR_PLL_NDIV2_Msk (0x1U << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */
9950 #define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
9951 #define DSI_WRPCR_PLL_NDIV3_Pos (5U)
9952 #define DSI_WRPCR_PLL_NDIV3_Msk (0x1U << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */
9953 #define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
9954 #define DSI_WRPCR_PLL_NDIV4_Pos (6U)
9955 #define DSI_WRPCR_PLL_NDIV4_Msk (0x1U << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */
9956 #define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
9957 #define DSI_WRPCR_PLL_NDIV5_Pos (7U)
9958 #define DSI_WRPCR_PLL_NDIV5_Msk (0x1U << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */
9959 #define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
9960 #define DSI_WRPCR_PLL_NDIV6_Pos (8U)
9961 #define DSI_WRPCR_PLL_NDIV6_Msk (0x1U << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */
9962 #define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
9963
9964 #define DSI_WRPCR_PLL_IDF_Pos (11U)
9965 #define DSI_WRPCR_PLL_IDF_Msk (0xFU << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */
9966 #define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */
9967 #define DSI_WRPCR_PLL_IDF0_Pos (11U)
9968 #define DSI_WRPCR_PLL_IDF0_Msk (0x1U << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */
9969 #define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
9970 #define DSI_WRPCR_PLL_IDF1_Pos (12U)
9971 #define DSI_WRPCR_PLL_IDF1_Msk (0x1U << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */
9972 #define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
9973 #define DSI_WRPCR_PLL_IDF2_Pos (13U)
9974 #define DSI_WRPCR_PLL_IDF2_Msk (0x1U << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */
9975 #define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
9976 #define DSI_WRPCR_PLL_IDF3_Pos (14U)
9977 #define DSI_WRPCR_PLL_IDF3_Msk (0x1U << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */
9978 #define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
9979
9980 #define DSI_WRPCR_PLL_ODF_Pos (16U)
9981 #define DSI_WRPCR_PLL_ODF_Msk (0x3U << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */
9982 #define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */
9983 #define DSI_WRPCR_PLL_ODF0_Pos (16U)
9984 #define DSI_WRPCR_PLL_ODF0_Msk (0x1U << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */
9985 #define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
9986 #define DSI_WRPCR_PLL_ODF1_Pos (17U)
9987 #define DSI_WRPCR_PLL_ODF1_Msk (0x1U << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */
9988 #define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
9989
9990 #define DSI_WRPCR_REGEN_Pos (24U)
9991 #define DSI_WRPCR_REGEN_Msk (0x1U << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */
9992 #define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */
9993
9994 /******************************************************************************/
9995 /* */
9996 /* External Interrupt/Event Controller */
9997 /* */
9998 /******************************************************************************/
9999 /******************* Bit definition for EXTI_IMR register *******************/
10000 #define EXTI_IMR_MR0_Pos (0U)
10001 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
10002 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
10003 #define EXTI_IMR_MR1_Pos (1U)
10004 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
10005 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
10006 #define EXTI_IMR_MR2_Pos (2U)
10007 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
10008 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
10009 #define EXTI_IMR_MR3_Pos (3U)
10010 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
10011 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
10012 #define EXTI_IMR_MR4_Pos (4U)
10013 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
10014 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
10015 #define EXTI_IMR_MR5_Pos (5U)
10016 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
10017 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
10018 #define EXTI_IMR_MR6_Pos (6U)
10019 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
10020 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
10021 #define EXTI_IMR_MR7_Pos (7U)
10022 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
10023 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
10024 #define EXTI_IMR_MR8_Pos (8U)
10025 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
10026 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
10027 #define EXTI_IMR_MR9_Pos (9U)
10028 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
10029 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
10030 #define EXTI_IMR_MR10_Pos (10U)
10031 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
10032 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
10033 #define EXTI_IMR_MR11_Pos (11U)
10034 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
10035 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
10036 #define EXTI_IMR_MR12_Pos (12U)
10037 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
10038 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
10039 #define EXTI_IMR_MR13_Pos (13U)
10040 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
10041 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
10042 #define EXTI_IMR_MR14_Pos (14U)
10043 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
10044 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
10045 #define EXTI_IMR_MR15_Pos (15U)
10046 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
10047 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
10048 #define EXTI_IMR_MR16_Pos (16U)
10049 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
10050 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
10051 #define EXTI_IMR_MR17_Pos (17U)
10052 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
10053 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
10054 #define EXTI_IMR_MR18_Pos (18U)
10055 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
10056 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
10057 #define EXTI_IMR_MR19_Pos (19U)
10058 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
10059 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
10060 #define EXTI_IMR_MR20_Pos (20U)
10061 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
10062 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
10063 #define EXTI_IMR_MR21_Pos (21U)
10064 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
10065 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
10066 #define EXTI_IMR_MR22_Pos (22U)
10067 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
10068 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
10069
10070 /* Reference Defines */
10071 #define EXTI_IMR_IM0 EXTI_IMR_MR0
10072 #define EXTI_IMR_IM1 EXTI_IMR_MR1
10073 #define EXTI_IMR_IM2 EXTI_IMR_MR2
10074 #define EXTI_IMR_IM3 EXTI_IMR_MR3
10075 #define EXTI_IMR_IM4 EXTI_IMR_MR4
10076 #define EXTI_IMR_IM5 EXTI_IMR_MR5
10077 #define EXTI_IMR_IM6 EXTI_IMR_MR6
10078 #define EXTI_IMR_IM7 EXTI_IMR_MR7
10079 #define EXTI_IMR_IM8 EXTI_IMR_MR8
10080 #define EXTI_IMR_IM9 EXTI_IMR_MR9
10081 #define EXTI_IMR_IM10 EXTI_IMR_MR10
10082 #define EXTI_IMR_IM11 EXTI_IMR_MR11
10083 #define EXTI_IMR_IM12 EXTI_IMR_MR12
10084 #define EXTI_IMR_IM13 EXTI_IMR_MR13
10085 #define EXTI_IMR_IM14 EXTI_IMR_MR14
10086 #define EXTI_IMR_IM15 EXTI_IMR_MR15
10087 #define EXTI_IMR_IM16 EXTI_IMR_MR16
10088 #define EXTI_IMR_IM17 EXTI_IMR_MR17
10089 #define EXTI_IMR_IM18 EXTI_IMR_MR18
10090 #define EXTI_IMR_IM19 EXTI_IMR_MR19
10091 #define EXTI_IMR_IM20 EXTI_IMR_MR20
10092 #define EXTI_IMR_IM21 EXTI_IMR_MR21
10093 #define EXTI_IMR_IM22 EXTI_IMR_MR22
10094 #define EXTI_IMR_IM_Pos (0U)
10095 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
10096 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
10097
10098 /******************* Bit definition for EXTI_EMR register *******************/
10099 #define EXTI_EMR_MR0_Pos (0U)
10100 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
10101 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
10102 #define EXTI_EMR_MR1_Pos (1U)
10103 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
10104 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
10105 #define EXTI_EMR_MR2_Pos (2U)
10106 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
10107 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
10108 #define EXTI_EMR_MR3_Pos (3U)
10109 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
10110 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
10111 #define EXTI_EMR_MR4_Pos (4U)
10112 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
10113 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
10114 #define EXTI_EMR_MR5_Pos (5U)
10115 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
10116 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
10117 #define EXTI_EMR_MR6_Pos (6U)
10118 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
10119 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
10120 #define EXTI_EMR_MR7_Pos (7U)
10121 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
10122 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
10123 #define EXTI_EMR_MR8_Pos (8U)
10124 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
10125 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
10126 #define EXTI_EMR_MR9_Pos (9U)
10127 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
10128 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
10129 #define EXTI_EMR_MR10_Pos (10U)
10130 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
10131 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
10132 #define EXTI_EMR_MR11_Pos (11U)
10133 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
10134 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
10135 #define EXTI_EMR_MR12_Pos (12U)
10136 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
10137 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
10138 #define EXTI_EMR_MR13_Pos (13U)
10139 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
10140 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
10141 #define EXTI_EMR_MR14_Pos (14U)
10142 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
10143 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
10144 #define EXTI_EMR_MR15_Pos (15U)
10145 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
10146 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
10147 #define EXTI_EMR_MR16_Pos (16U)
10148 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
10149 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
10150 #define EXTI_EMR_MR17_Pos (17U)
10151 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
10152 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
10153 #define EXTI_EMR_MR18_Pos (18U)
10154 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
10155 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
10156 #define EXTI_EMR_MR19_Pos (19U)
10157 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
10158 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
10159 #define EXTI_EMR_MR20_Pos (20U)
10160 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
10161 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
10162 #define EXTI_EMR_MR21_Pos (21U)
10163 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
10164 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
10165 #define EXTI_EMR_MR22_Pos (22U)
10166 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
10167 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
10168
10169 /* Reference Defines */
10170 #define EXTI_EMR_EM0 EXTI_EMR_MR0
10171 #define EXTI_EMR_EM1 EXTI_EMR_MR1
10172 #define EXTI_EMR_EM2 EXTI_EMR_MR2
10173 #define EXTI_EMR_EM3 EXTI_EMR_MR3
10174 #define EXTI_EMR_EM4 EXTI_EMR_MR4
10175 #define EXTI_EMR_EM5 EXTI_EMR_MR5
10176 #define EXTI_EMR_EM6 EXTI_EMR_MR6
10177 #define EXTI_EMR_EM7 EXTI_EMR_MR7
10178 #define EXTI_EMR_EM8 EXTI_EMR_MR8
10179 #define EXTI_EMR_EM9 EXTI_EMR_MR9
10180 #define EXTI_EMR_EM10 EXTI_EMR_MR10
10181 #define EXTI_EMR_EM11 EXTI_EMR_MR11
10182 #define EXTI_EMR_EM12 EXTI_EMR_MR12
10183 #define EXTI_EMR_EM13 EXTI_EMR_MR13
10184 #define EXTI_EMR_EM14 EXTI_EMR_MR14
10185 #define EXTI_EMR_EM15 EXTI_EMR_MR15
10186 #define EXTI_EMR_EM16 EXTI_EMR_MR16
10187 #define EXTI_EMR_EM17 EXTI_EMR_MR17
10188 #define EXTI_EMR_EM18 EXTI_EMR_MR18
10189 #define EXTI_EMR_EM19 EXTI_EMR_MR19
10190 #define EXTI_EMR_EM20 EXTI_EMR_MR20
10191 #define EXTI_EMR_EM21 EXTI_EMR_MR21
10192 #define EXTI_EMR_EM22 EXTI_EMR_MR22
10193
10194 /****************** Bit definition for EXTI_RTSR register *******************/
10195 #define EXTI_RTSR_TR0_Pos (0U)
10196 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
10197 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
10198 #define EXTI_RTSR_TR1_Pos (1U)
10199 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
10200 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
10201 #define EXTI_RTSR_TR2_Pos (2U)
10202 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
10203 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
10204 #define EXTI_RTSR_TR3_Pos (3U)
10205 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
10206 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
10207 #define EXTI_RTSR_TR4_Pos (4U)
10208 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
10209 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
10210 #define EXTI_RTSR_TR5_Pos (5U)
10211 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
10212 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
10213 #define EXTI_RTSR_TR6_Pos (6U)
10214 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
10215 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
10216 #define EXTI_RTSR_TR7_Pos (7U)
10217 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
10218 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
10219 #define EXTI_RTSR_TR8_Pos (8U)
10220 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
10221 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
10222 #define EXTI_RTSR_TR9_Pos (9U)
10223 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
10224 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
10225 #define EXTI_RTSR_TR10_Pos (10U)
10226 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
10227 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
10228 #define EXTI_RTSR_TR11_Pos (11U)
10229 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
10230 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
10231 #define EXTI_RTSR_TR12_Pos (12U)
10232 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
10233 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
10234 #define EXTI_RTSR_TR13_Pos (13U)
10235 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
10236 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
10237 #define EXTI_RTSR_TR14_Pos (14U)
10238 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
10239 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
10240 #define EXTI_RTSR_TR15_Pos (15U)
10241 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
10242 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
10243 #define EXTI_RTSR_TR16_Pos (16U)
10244 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
10245 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
10246 #define EXTI_RTSR_TR17_Pos (17U)
10247 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
10248 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
10249 #define EXTI_RTSR_TR18_Pos (18U)
10250 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
10251 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
10252 #define EXTI_RTSR_TR19_Pos (19U)
10253 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
10254 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
10255 #define EXTI_RTSR_TR20_Pos (20U)
10256 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
10257 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
10258 #define EXTI_RTSR_TR21_Pos (21U)
10259 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
10260 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
10261 #define EXTI_RTSR_TR22_Pos (22U)
10262 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
10263 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
10264
10265 /****************** Bit definition for EXTI_FTSR register *******************/
10266 #define EXTI_FTSR_TR0_Pos (0U)
10267 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
10268 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
10269 #define EXTI_FTSR_TR1_Pos (1U)
10270 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
10271 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
10272 #define EXTI_FTSR_TR2_Pos (2U)
10273 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
10274 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
10275 #define EXTI_FTSR_TR3_Pos (3U)
10276 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
10277 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
10278 #define EXTI_FTSR_TR4_Pos (4U)
10279 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
10280 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
10281 #define EXTI_FTSR_TR5_Pos (5U)
10282 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
10283 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
10284 #define EXTI_FTSR_TR6_Pos (6U)
10285 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
10286 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
10287 #define EXTI_FTSR_TR7_Pos (7U)
10288 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
10289 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
10290 #define EXTI_FTSR_TR8_Pos (8U)
10291 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
10292 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
10293 #define EXTI_FTSR_TR9_Pos (9U)
10294 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
10295 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
10296 #define EXTI_FTSR_TR10_Pos (10U)
10297 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
10298 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
10299 #define EXTI_FTSR_TR11_Pos (11U)
10300 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
10301 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
10302 #define EXTI_FTSR_TR12_Pos (12U)
10303 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
10304 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
10305 #define EXTI_FTSR_TR13_Pos (13U)
10306 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
10307 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
10308 #define EXTI_FTSR_TR14_Pos (14U)
10309 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
10310 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
10311 #define EXTI_FTSR_TR15_Pos (15U)
10312 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
10313 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
10314 #define EXTI_FTSR_TR16_Pos (16U)
10315 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
10316 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
10317 #define EXTI_FTSR_TR17_Pos (17U)
10318 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
10319 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
10320 #define EXTI_FTSR_TR18_Pos (18U)
10321 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
10322 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
10323 #define EXTI_FTSR_TR19_Pos (19U)
10324 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
10325 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
10326 #define EXTI_FTSR_TR20_Pos (20U)
10327 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
10328 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
10329 #define EXTI_FTSR_TR21_Pos (21U)
10330 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
10331 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
10332 #define EXTI_FTSR_TR22_Pos (22U)
10333 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
10334 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
10335
10336 /****************** Bit definition for EXTI_SWIER register ******************/
10337 #define EXTI_SWIER_SWIER0_Pos (0U)
10338 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
10339 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
10340 #define EXTI_SWIER_SWIER1_Pos (1U)
10341 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
10342 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
10343 #define EXTI_SWIER_SWIER2_Pos (2U)
10344 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
10345 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
10346 #define EXTI_SWIER_SWIER3_Pos (3U)
10347 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
10348 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
10349 #define EXTI_SWIER_SWIER4_Pos (4U)
10350 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
10351 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
10352 #define EXTI_SWIER_SWIER5_Pos (5U)
10353 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
10354 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
10355 #define EXTI_SWIER_SWIER6_Pos (6U)
10356 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
10357 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
10358 #define EXTI_SWIER_SWIER7_Pos (7U)
10359 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
10360 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
10361 #define EXTI_SWIER_SWIER8_Pos (8U)
10362 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
10363 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
10364 #define EXTI_SWIER_SWIER9_Pos (9U)
10365 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
10366 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
10367 #define EXTI_SWIER_SWIER10_Pos (10U)
10368 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
10369 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
10370 #define EXTI_SWIER_SWIER11_Pos (11U)
10371 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
10372 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
10373 #define EXTI_SWIER_SWIER12_Pos (12U)
10374 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
10375 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
10376 #define EXTI_SWIER_SWIER13_Pos (13U)
10377 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
10378 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
10379 #define EXTI_SWIER_SWIER14_Pos (14U)
10380 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
10381 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
10382 #define EXTI_SWIER_SWIER15_Pos (15U)
10383 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
10384 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
10385 #define EXTI_SWIER_SWIER16_Pos (16U)
10386 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
10387 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
10388 #define EXTI_SWIER_SWIER17_Pos (17U)
10389 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
10390 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
10391 #define EXTI_SWIER_SWIER18_Pos (18U)
10392 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
10393 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
10394 #define EXTI_SWIER_SWIER19_Pos (19U)
10395 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
10396 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
10397 #define EXTI_SWIER_SWIER20_Pos (20U)
10398 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
10399 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
10400 #define EXTI_SWIER_SWIER21_Pos (21U)
10401 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
10402 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
10403 #define EXTI_SWIER_SWIER22_Pos (22U)
10404 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
10405 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
10406
10407 /******************* Bit definition for EXTI_PR register ********************/
10408 #define EXTI_PR_PR0_Pos (0U)
10409 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
10410 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
10411 #define EXTI_PR_PR1_Pos (1U)
10412 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
10413 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
10414 #define EXTI_PR_PR2_Pos (2U)
10415 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
10416 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
10417 #define EXTI_PR_PR3_Pos (3U)
10418 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
10419 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
10420 #define EXTI_PR_PR4_Pos (4U)
10421 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
10422 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
10423 #define EXTI_PR_PR5_Pos (5U)
10424 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
10425 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
10426 #define EXTI_PR_PR6_Pos (6U)
10427 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
10428 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
10429 #define EXTI_PR_PR7_Pos (7U)
10430 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
10431 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
10432 #define EXTI_PR_PR8_Pos (8U)
10433 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
10434 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
10435 #define EXTI_PR_PR9_Pos (9U)
10436 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
10437 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
10438 #define EXTI_PR_PR10_Pos (10U)
10439 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
10440 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
10441 #define EXTI_PR_PR11_Pos (11U)
10442 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
10443 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
10444 #define EXTI_PR_PR12_Pos (12U)
10445 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
10446 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
10447 #define EXTI_PR_PR13_Pos (13U)
10448 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
10449 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
10450 #define EXTI_PR_PR14_Pos (14U)
10451 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
10452 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
10453 #define EXTI_PR_PR15_Pos (15U)
10454 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
10455 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
10456 #define EXTI_PR_PR16_Pos (16U)
10457 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
10458 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
10459 #define EXTI_PR_PR17_Pos (17U)
10460 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
10461 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
10462 #define EXTI_PR_PR18_Pos (18U)
10463 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
10464 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
10465 #define EXTI_PR_PR19_Pos (19U)
10466 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
10467 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
10468 #define EXTI_PR_PR20_Pos (20U)
10469 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
10470 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
10471 #define EXTI_PR_PR21_Pos (21U)
10472 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
10473 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
10474 #define EXTI_PR_PR22_Pos (22U)
10475 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
10476 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
10477
10478 /******************************************************************************/
10479 /* */
10480 /* FLASH */
10481 /* */
10482 /******************************************************************************/
10483 /******************* Bits definition for FLASH_ACR register *****************/
10484 #define FLASH_ACR_LATENCY_Pos (0U)
10485 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
10486 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
10487 #define FLASH_ACR_LATENCY_0WS 0x00000000U
10488 #define FLASH_ACR_LATENCY_1WS 0x00000001U
10489 #define FLASH_ACR_LATENCY_2WS 0x00000002U
10490 #define FLASH_ACR_LATENCY_3WS 0x00000003U
10491 #define FLASH_ACR_LATENCY_4WS 0x00000004U
10492 #define FLASH_ACR_LATENCY_5WS 0x00000005U
10493 #define FLASH_ACR_LATENCY_6WS 0x00000006U
10494 #define FLASH_ACR_LATENCY_7WS 0x00000007U
10495
10496 #define FLASH_ACR_LATENCY_8WS 0x00000008U
10497 #define FLASH_ACR_LATENCY_9WS 0x00000009U
10498 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
10499 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
10500 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
10501 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
10502 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
10503 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
10504 #define FLASH_ACR_PRFTEN_Pos (8U)
10505 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
10506 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
10507 #define FLASH_ACR_ICEN_Pos (9U)
10508 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
10509 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
10510 #define FLASH_ACR_DCEN_Pos (10U)
10511 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
10512 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
10513 #define FLASH_ACR_ICRST_Pos (11U)
10514 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
10515 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
10516 #define FLASH_ACR_DCRST_Pos (12U)
10517 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
10518 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
10519 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
10520 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
10521 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
10522 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
10523 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
10524 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
10525
10526 /******************* Bits definition for FLASH_SR register ******************/
10527 #define FLASH_SR_EOP_Pos (0U)
10528 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
10529 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
10530 #define FLASH_SR_SOP_Pos (1U)
10531 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
10532 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
10533 #define FLASH_SR_WRPERR_Pos (4U)
10534 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
10535 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
10536 #define FLASH_SR_PGAERR_Pos (5U)
10537 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
10538 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
10539 #define FLASH_SR_PGPERR_Pos (6U)
10540 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
10541 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
10542 #define FLASH_SR_PGSERR_Pos (7U)
10543 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
10544 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
10545 #define FLASH_SR_RDERR_Pos (8U)
10546 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
10547 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
10548 #define FLASH_SR_BSY_Pos (16U)
10549 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
10550 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
10551
10552 /******************* Bits definition for FLASH_CR register ******************/
10553 #define FLASH_CR_PG_Pos (0U)
10554 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
10555 #define FLASH_CR_PG FLASH_CR_PG_Msk
10556 #define FLASH_CR_SER_Pos (1U)
10557 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
10558 #define FLASH_CR_SER FLASH_CR_SER_Msk
10559 #define FLASH_CR_MER_Pos (2U)
10560 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
10561 #define FLASH_CR_MER FLASH_CR_MER_Msk
10562 #define FLASH_CR_MER1 FLASH_CR_MER
10563 #define FLASH_CR_SNB_Pos (3U)
10564 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
10565 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
10566 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
10567 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
10568 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
10569 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
10570 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
10571 #define FLASH_CR_PSIZE_Pos (8U)
10572 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
10573 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
10574 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
10575 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
10576 #define FLASH_CR_MER2_Pos (15U)
10577 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
10578 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
10579 #define FLASH_CR_STRT_Pos (16U)
10580 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
10581 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
10582 #define FLASH_CR_EOPIE_Pos (24U)
10583 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
10584 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
10585 #define FLASH_CR_LOCK_Pos (31U)
10586 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
10587 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
10588
10589 /******************* Bits definition for FLASH_OPTCR register ***************/
10590 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
10591 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
10592 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
10593 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
10594 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
10595 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
10596
10597 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
10598 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
10599 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
10600 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
10601 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
10602 #define FLASH_OPTCR_BFB2_Pos (4U)
10603 #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
10604 #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
10605 #define FLASH_OPTCR_WDG_SW_Pos (5U)
10606 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
10607 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
10608 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
10609 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
10610 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
10611 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
10612 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
10613 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
10614 #define FLASH_OPTCR_RDP_Pos (8U)
10615 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
10616 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
10617 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
10618 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
10619 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
10620 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
10621 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
10622 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
10623 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
10624 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
10625 #define FLASH_OPTCR_nWRP_Pos (16U)
10626 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
10627 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
10628 #define FLASH_OPTCR_nWRP_0 0x00010000U
10629 #define FLASH_OPTCR_nWRP_1 0x00020000U
10630 #define FLASH_OPTCR_nWRP_2 0x00040000U
10631 #define FLASH_OPTCR_nWRP_3 0x00080000U
10632 #define FLASH_OPTCR_nWRP_4 0x00100000U
10633 #define FLASH_OPTCR_nWRP_5 0x00200000U
10634 #define FLASH_OPTCR_nWRP_6 0x00400000U
10635 #define FLASH_OPTCR_nWRP_7 0x00800000U
10636 #define FLASH_OPTCR_nWRP_8 0x01000000U
10637 #define FLASH_OPTCR_nWRP_9 0x02000000U
10638 #define FLASH_OPTCR_nWRP_10 0x04000000U
10639 #define FLASH_OPTCR_nWRP_11 0x08000000U
10640 #define FLASH_OPTCR_DB1M_Pos (30U)
10641 #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
10642 #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
10643 #define FLASH_OPTCR_SPRMOD_Pos (31U)
10644 #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
10645 #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
10646
10647 /****************** Bits definition for FLASH_OPTCR1 register ***************/
10648 #define FLASH_OPTCR1_nWRP_Pos (16U)
10649 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
10650 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
10651 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
10652 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
10653 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
10654 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
10655 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
10656 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
10657 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
10658 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
10659 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
10660 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
10661 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
10662 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
10663
10664 /******************************************************************************/
10665 /* */
10666 /* Flexible Memory Controller */
10667 /* */
10668 /******************************************************************************/
10669 /****************** Bit definition for FMC_BCR1 register *******************/
10670 #define FMC_BCR1_MBKEN_Pos (0U)
10671 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
10672 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
10673 #define FMC_BCR1_MUXEN_Pos (1U)
10674 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
10675 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10676
10677 #define FMC_BCR1_MTYP_Pos (2U)
10678 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
10679 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10680 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
10681 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
10682
10683 #define FMC_BCR1_MWID_Pos (4U)
10684 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
10685 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10686 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
10687 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
10688
10689 #define FMC_BCR1_FACCEN_Pos (6U)
10690 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
10691 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
10692 #define FMC_BCR1_BURSTEN_Pos (8U)
10693 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
10694 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
10695 #define FMC_BCR1_WAITPOL_Pos (9U)
10696 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
10697 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
10698 #define FMC_BCR1_WAITCFG_Pos (11U)
10699 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
10700 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
10701 #define FMC_BCR1_WREN_Pos (12U)
10702 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
10703 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
10704 #define FMC_BCR1_WAITEN_Pos (13U)
10705 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
10706 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
10707 #define FMC_BCR1_EXTMOD_Pos (14U)
10708 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
10709 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
10710 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
10711 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
10712 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
10713 #define FMC_BCR1_CPSIZE_Pos (16U)
10714 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
10715 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
10716 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
10717 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
10718 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
10719 #define FMC_BCR1_CBURSTRW_Pos (19U)
10720 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
10721 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
10722 #define FMC_BCR1_CCLKEN_Pos (20U)
10723 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
10724 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
10725 #define FMC_BCR1_WFDIS_Pos (21U)
10726 #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
10727 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
10728
10729 /****************** Bit definition for FMC_BCR2 register *******************/
10730 #define FMC_BCR2_MBKEN_Pos (0U)
10731 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
10732 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
10733 #define FMC_BCR2_MUXEN_Pos (1U)
10734 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
10735 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10736
10737 #define FMC_BCR2_MTYP_Pos (2U)
10738 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
10739 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10740 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
10741 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
10742
10743 #define FMC_BCR2_MWID_Pos (4U)
10744 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
10745 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10746 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
10747 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
10748
10749 #define FMC_BCR2_FACCEN_Pos (6U)
10750 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
10751 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
10752 #define FMC_BCR2_BURSTEN_Pos (8U)
10753 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
10754 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
10755 #define FMC_BCR2_WAITPOL_Pos (9U)
10756 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
10757 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
10758 #define FMC_BCR2_WAITCFG_Pos (11U)
10759 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
10760 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
10761 #define FMC_BCR2_WREN_Pos (12U)
10762 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
10763 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
10764 #define FMC_BCR2_WAITEN_Pos (13U)
10765 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
10766 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
10767 #define FMC_BCR2_EXTMOD_Pos (14U)
10768 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
10769 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
10770 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
10771 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
10772 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
10773 #define FMC_BCR2_CBURSTRW_Pos (19U)
10774 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
10775 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
10776
10777 /****************** Bit definition for FMC_BCR3 register *******************/
10778 #define FMC_BCR3_MBKEN_Pos (0U)
10779 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
10780 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
10781 #define FMC_BCR3_MUXEN_Pos (1U)
10782 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
10783 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10784
10785 #define FMC_BCR3_MTYP_Pos (2U)
10786 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
10787 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10788 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
10789 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
10790
10791 #define FMC_BCR3_MWID_Pos (4U)
10792 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
10793 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10794 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
10795 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
10796
10797 #define FMC_BCR3_FACCEN_Pos (6U)
10798 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
10799 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
10800 #define FMC_BCR3_BURSTEN_Pos (8U)
10801 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
10802 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
10803 #define FMC_BCR3_WAITPOL_Pos (9U)
10804 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
10805 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
10806 #define FMC_BCR3_WAITCFG_Pos (11U)
10807 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
10808 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
10809 #define FMC_BCR3_WREN_Pos (12U)
10810 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
10811 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
10812 #define FMC_BCR3_WAITEN_Pos (13U)
10813 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
10814 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
10815 #define FMC_BCR3_EXTMOD_Pos (14U)
10816 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
10817 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
10818 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
10819 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
10820 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
10821 #define FMC_BCR3_CBURSTRW_Pos (19U)
10822 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
10823 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
10824
10825 /****************** Bit definition for FMC_BCR4 register *******************/
10826 #define FMC_BCR4_MBKEN_Pos (0U)
10827 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
10828 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
10829 #define FMC_BCR4_MUXEN_Pos (1U)
10830 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
10831 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10832
10833 #define FMC_BCR4_MTYP_Pos (2U)
10834 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
10835 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10836 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
10837 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
10838
10839 #define FMC_BCR4_MWID_Pos (4U)
10840 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
10841 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10842 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
10843 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
10844
10845 #define FMC_BCR4_FACCEN_Pos (6U)
10846 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
10847 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
10848 #define FMC_BCR4_BURSTEN_Pos (8U)
10849 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
10850 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
10851 #define FMC_BCR4_WAITPOL_Pos (9U)
10852 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
10853 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
10854 #define FMC_BCR4_WAITCFG_Pos (11U)
10855 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
10856 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
10857 #define FMC_BCR4_WREN_Pos (12U)
10858 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
10859 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
10860 #define FMC_BCR4_WAITEN_Pos (13U)
10861 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
10862 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
10863 #define FMC_BCR4_EXTMOD_Pos (14U)
10864 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
10865 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
10866 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
10867 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
10868 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
10869 #define FMC_BCR4_CBURSTRW_Pos (19U)
10870 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
10871 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
10872
10873 /****************** Bit definition for FMC_BTR1 register ******************/
10874 #define FMC_BTR1_ADDSET_Pos (0U)
10875 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
10876 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10877 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
10878 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
10879 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
10880 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
10881
10882 #define FMC_BTR1_ADDHLD_Pos (4U)
10883 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
10884 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10885 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
10886 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
10887 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
10888 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
10889
10890 #define FMC_BTR1_DATAST_Pos (8U)
10891 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
10892 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10893 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
10894 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
10895 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
10896 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
10897 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
10898 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
10899 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
10900 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
10901
10902 #define FMC_BTR1_BUSTURN_Pos (16U)
10903 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
10904 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10905 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
10906 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
10907 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
10908 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
10909
10910 #define FMC_BTR1_CLKDIV_Pos (20U)
10911 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
10912 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10913 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
10914 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
10915 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
10916 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
10917
10918 #define FMC_BTR1_DATLAT_Pos (24U)
10919 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
10920 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
10921 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
10922 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
10923 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
10924 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
10925
10926 #define FMC_BTR1_ACCMOD_Pos (28U)
10927 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
10928 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10929 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
10930 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
10931
10932 /****************** Bit definition for FMC_BTR2 register *******************/
10933 #define FMC_BTR2_ADDSET_Pos (0U)
10934 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
10935 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10936 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
10937 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
10938 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
10939 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
10940
10941 #define FMC_BTR2_ADDHLD_Pos (4U)
10942 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
10943 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10944 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
10945 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
10946 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
10947 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
10948
10949 #define FMC_BTR2_DATAST_Pos (8U)
10950 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
10951 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10952 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
10953 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
10954 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
10955 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
10956 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
10957 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
10958 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
10959 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
10960
10961 #define FMC_BTR2_BUSTURN_Pos (16U)
10962 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
10963 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10964 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
10965 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
10966 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
10967 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
10968
10969 #define FMC_BTR2_CLKDIV_Pos (20U)
10970 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
10971 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10972 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
10973 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
10974 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
10975 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
10976
10977 #define FMC_BTR2_DATLAT_Pos (24U)
10978 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
10979 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
10980 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
10981 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
10982 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
10983 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
10984
10985 #define FMC_BTR2_ACCMOD_Pos (28U)
10986 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
10987 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10988 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
10989 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
10990
10991 /******************* Bit definition for FMC_BTR3 register *******************/
10992 #define FMC_BTR3_ADDSET_Pos (0U)
10993 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
10994 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10995 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
10996 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
10997 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
10998 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
10999
11000 #define FMC_BTR3_ADDHLD_Pos (4U)
11001 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
11002 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11003 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
11004 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
11005 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
11006 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
11007
11008 #define FMC_BTR3_DATAST_Pos (8U)
11009 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
11010 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11011 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
11012 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
11013 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
11014 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
11015 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
11016 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
11017 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
11018 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
11019
11020 #define FMC_BTR3_BUSTURN_Pos (16U)
11021 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
11022 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
11023 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
11024 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
11025 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
11026 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
11027
11028 #define FMC_BTR3_CLKDIV_Pos (20U)
11029 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
11030 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
11031 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
11032 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
11033 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
11034 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
11035
11036 #define FMC_BTR3_DATLAT_Pos (24U)
11037 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
11038 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
11039 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
11040 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
11041 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
11042 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
11043
11044 #define FMC_BTR3_ACCMOD_Pos (28U)
11045 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
11046 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11047 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
11048 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
11049
11050 /****************** Bit definition for FMC_BTR4 register *******************/
11051 #define FMC_BTR4_ADDSET_Pos (0U)
11052 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
11053 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11054 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
11055 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
11056 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
11057 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
11058
11059 #define FMC_BTR4_ADDHLD_Pos (4U)
11060 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
11061 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11062 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
11063 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
11064 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
11065 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
11066
11067 #define FMC_BTR4_DATAST_Pos (8U)
11068 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
11069 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11070 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
11071 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
11072 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
11073 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
11074 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
11075 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
11076 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
11077 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
11078
11079 #define FMC_BTR4_BUSTURN_Pos (16U)
11080 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
11081 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
11082 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
11083 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
11084 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
11085 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
11086
11087 #define FMC_BTR4_CLKDIV_Pos (20U)
11088 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
11089 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
11090 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
11091 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
11092 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
11093 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
11094
11095 #define FMC_BTR4_DATLAT_Pos (24U)
11096 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
11097 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
11098 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
11099 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
11100 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
11101 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
11102
11103 #define FMC_BTR4_ACCMOD_Pos (28U)
11104 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
11105 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11106 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
11107 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
11108
11109 /****************** Bit definition for FMC_BWTR1 register ******************/
11110 #define FMC_BWTR1_ADDSET_Pos (0U)
11111 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
11112 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11113 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
11114 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
11115 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
11116 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
11117
11118 #define FMC_BWTR1_ADDHLD_Pos (4U)
11119 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
11120 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11121 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
11122 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
11123 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
11124 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
11125
11126 #define FMC_BWTR1_DATAST_Pos (8U)
11127 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
11128 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11129 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
11130 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
11131 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
11132 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
11133 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
11134 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
11135 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
11136 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
11137
11138 #define FMC_BWTR1_BUSTURN_Pos (16U)
11139 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
11140 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11141 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
11142 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
11143 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
11144 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
11145
11146 #define FMC_BWTR1_ACCMOD_Pos (28U)
11147 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
11148 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11149 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
11150 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
11151
11152 /****************** Bit definition for FMC_BWTR2 register ******************/
11153 #define FMC_BWTR2_ADDSET_Pos (0U)
11154 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
11155 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11156 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
11157 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
11158 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
11159 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
11160
11161 #define FMC_BWTR2_ADDHLD_Pos (4U)
11162 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
11163 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11164 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
11165 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
11166 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
11167 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
11168
11169 #define FMC_BWTR2_DATAST_Pos (8U)
11170 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
11171 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11172 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
11173 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
11174 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
11175 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
11176 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
11177 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
11178 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
11179 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
11180
11181 #define FMC_BWTR2_BUSTURN_Pos (16U)
11182 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
11183 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11184 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
11185 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
11186 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
11187 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
11188
11189 #define FMC_BWTR2_ACCMOD_Pos (28U)
11190 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
11191 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11192 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
11193 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
11194
11195 /****************** Bit definition for FMC_BWTR3 register ******************/
11196 #define FMC_BWTR3_ADDSET_Pos (0U)
11197 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
11198 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11199 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
11200 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
11201 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
11202 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
11203
11204 #define FMC_BWTR3_ADDHLD_Pos (4U)
11205 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
11206 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11207 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
11208 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
11209 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
11210 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
11211
11212 #define FMC_BWTR3_DATAST_Pos (8U)
11213 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
11214 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11215 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
11216 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
11217 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
11218 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
11219 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
11220 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
11221 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
11222 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
11223
11224 #define FMC_BWTR3_BUSTURN_Pos (16U)
11225 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
11226 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11227 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
11228 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
11229 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
11230 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
11231
11232 #define FMC_BWTR3_ACCMOD_Pos (28U)
11233 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
11234 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11235 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
11236 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
11237
11238 /****************** Bit definition for FMC_BWTR4 register ******************/
11239 #define FMC_BWTR4_ADDSET_Pos (0U)
11240 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
11241 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11242 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
11243 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
11244 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
11245 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
11246
11247 #define FMC_BWTR4_ADDHLD_Pos (4U)
11248 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
11249 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11250 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
11251 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
11252 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
11253 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
11254
11255 #define FMC_BWTR4_DATAST_Pos (8U)
11256 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
11257 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11258 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
11259 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
11260 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
11261 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
11262 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
11263 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
11264 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
11265 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
11266
11267 #define FMC_BWTR4_BUSTURN_Pos (16U)
11268 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
11269 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11270 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
11271 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
11272 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
11273 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
11274
11275 #define FMC_BWTR4_ACCMOD_Pos (28U)
11276 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
11277 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11278 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
11279 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
11280
11281 /****************** Bit definition for FMC_PCR register *******************/
11282 #define FMC_PCR_PWAITEN_Pos (1U)
11283 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
11284 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
11285 #define FMC_PCR_PBKEN_Pos (2U)
11286 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
11287 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
11288 #define FMC_PCR_PTYP_Pos (3U)
11289 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
11290 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
11291
11292 #define FMC_PCR_PWID_Pos (4U)
11293 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
11294 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
11295 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
11296 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
11297
11298 #define FMC_PCR_ECCEN_Pos (6U)
11299 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
11300 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
11301
11302 #define FMC_PCR_TCLR_Pos (9U)
11303 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
11304 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
11305 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
11306 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
11307 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
11308 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
11309
11310 #define FMC_PCR_TAR_Pos (13U)
11311 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
11312 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
11313 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
11314 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
11315 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
11316 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
11317
11318 #define FMC_PCR_ECCPS_Pos (17U)
11319 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
11320 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
11321 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
11322 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
11323 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
11324
11325 /******************* Bit definition for FMC_SR register *******************/
11326 #define FMC_SR_IRS_Pos (0U)
11327 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
11328 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
11329 #define FMC_SR_ILS_Pos (1U)
11330 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
11331 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
11332 #define FMC_SR_IFS_Pos (2U)
11333 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
11334 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
11335 #define FMC_SR_IREN_Pos (3U)
11336 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
11337 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
11338 #define FMC_SR_ILEN_Pos (4U)
11339 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
11340 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
11341 #define FMC_SR_IFEN_Pos (5U)
11342 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
11343 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
11344 #define FMC_SR_FEMPT_Pos (6U)
11345 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
11346 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
11347
11348 /****************** Bit definition for FMC_PMEM register ******************/
11349 #define FMC_PMEM_MEMSET2_Pos (0U)
11350 #define FMC_PMEM_MEMSET2_Msk (0xFFU << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */
11351 #define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
11352 #define FMC_PMEM_MEMSET2_0 (0x01U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */
11353 #define FMC_PMEM_MEMSET2_1 (0x02U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */
11354 #define FMC_PMEM_MEMSET2_2 (0x04U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */
11355 #define FMC_PMEM_MEMSET2_3 (0x08U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */
11356 #define FMC_PMEM_MEMSET2_4 (0x10U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */
11357 #define FMC_PMEM_MEMSET2_5 (0x20U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */
11358 #define FMC_PMEM_MEMSET2_6 (0x40U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */
11359 #define FMC_PMEM_MEMSET2_7 (0x80U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */
11360
11361 #define FMC_PMEM_MEMWAIT2_Pos (8U)
11362 #define FMC_PMEM_MEMWAIT2_Msk (0xFFU << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */
11363 #define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
11364 #define FMC_PMEM_MEMWAIT2_0 (0x01U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */
11365 #define FMC_PMEM_MEMWAIT2_1 (0x02U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */
11366 #define FMC_PMEM_MEMWAIT2_2 (0x04U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */
11367 #define FMC_PMEM_MEMWAIT2_3 (0x08U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */
11368 #define FMC_PMEM_MEMWAIT2_4 (0x10U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */
11369 #define FMC_PMEM_MEMWAIT2_5 (0x20U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */
11370 #define FMC_PMEM_MEMWAIT2_6 (0x40U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */
11371 #define FMC_PMEM_MEMWAIT2_7 (0x80U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */
11372
11373 #define FMC_PMEM_MEMHOLD2_Pos (16U)
11374 #define FMC_PMEM_MEMHOLD2_Msk (0xFFU << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */
11375 #define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
11376 #define FMC_PMEM_MEMHOLD2_0 (0x01U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */
11377 #define FMC_PMEM_MEMHOLD2_1 (0x02U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */
11378 #define FMC_PMEM_MEMHOLD2_2 (0x04U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */
11379 #define FMC_PMEM_MEMHOLD2_3 (0x08U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */
11380 #define FMC_PMEM_MEMHOLD2_4 (0x10U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */
11381 #define FMC_PMEM_MEMHOLD2_5 (0x20U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */
11382 #define FMC_PMEM_MEMHOLD2_6 (0x40U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */
11383 #define FMC_PMEM_MEMHOLD2_7 (0x80U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */
11384
11385 #define FMC_PMEM_MEMHIZ2_Pos (24U)
11386 #define FMC_PMEM_MEMHIZ2_Msk (0xFFU << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */
11387 #define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
11388 #define FMC_PMEM_MEMHIZ2_0 (0x01U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */
11389 #define FMC_PMEM_MEMHIZ2_1 (0x02U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */
11390 #define FMC_PMEM_MEMHIZ2_2 (0x04U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */
11391 #define FMC_PMEM_MEMHIZ2_3 (0x08U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */
11392 #define FMC_PMEM_MEMHIZ2_4 (0x10U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */
11393 #define FMC_PMEM_MEMHIZ2_5 (0x20U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */
11394 #define FMC_PMEM_MEMHIZ2_6 (0x40U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */
11395 #define FMC_PMEM_MEMHIZ2_7 (0x80U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */
11396
11397 /****************** Bit definition for FMC_PATT register ******************/
11398 #define FMC_PATT_ATTSET2_Pos (0U)
11399 #define FMC_PATT_ATTSET2_Msk (0xFFU << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */
11400 #define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
11401 #define FMC_PATT_ATTSET2_0 (0x01U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */
11402 #define FMC_PATT_ATTSET2_1 (0x02U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */
11403 #define FMC_PATT_ATTSET2_2 (0x04U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */
11404 #define FMC_PATT_ATTSET2_3 (0x08U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */
11405 #define FMC_PATT_ATTSET2_4 (0x10U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */
11406 #define FMC_PATT_ATTSET2_5 (0x20U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */
11407 #define FMC_PATT_ATTSET2_6 (0x40U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */
11408 #define FMC_PATT_ATTSET2_7 (0x80U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */
11409
11410 #define FMC_PATT_ATTWAIT2_Pos (8U)
11411 #define FMC_PATT_ATTWAIT2_Msk (0xFFU << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */
11412 #define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
11413 #define FMC_PATT_ATTWAIT2_0 (0x01U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */
11414 #define FMC_PATT_ATTWAIT2_1 (0x02U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */
11415 #define FMC_PATT_ATTWAIT2_2 (0x04U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */
11416 #define FMC_PATT_ATTWAIT2_3 (0x08U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */
11417 #define FMC_PATT_ATTWAIT2_4 (0x10U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */
11418 #define FMC_PATT_ATTWAIT2_5 (0x20U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */
11419 #define FMC_PATT_ATTWAIT2_6 (0x40U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */
11420 #define FMC_PATT_ATTWAIT2_7 (0x80U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */
11421
11422 #define FMC_PATT_ATTHOLD2_Pos (16U)
11423 #define FMC_PATT_ATTHOLD2_Msk (0xFFU << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */
11424 #define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
11425 #define FMC_PATT_ATTHOLD2_0 (0x01U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */
11426 #define FMC_PATT_ATTHOLD2_1 (0x02U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */
11427 #define FMC_PATT_ATTHOLD2_2 (0x04U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */
11428 #define FMC_PATT_ATTHOLD2_3 (0x08U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */
11429 #define FMC_PATT_ATTHOLD2_4 (0x10U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */
11430 #define FMC_PATT_ATTHOLD2_5 (0x20U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */
11431 #define FMC_PATT_ATTHOLD2_6 (0x40U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */
11432 #define FMC_PATT_ATTHOLD2_7 (0x80U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */
11433
11434 #define FMC_PATT_ATTHIZ2_Pos (24U)
11435 #define FMC_PATT_ATTHIZ2_Msk (0xFFU << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */
11436 #define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
11437 #define FMC_PATT_ATTHIZ2_0 (0x01U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */
11438 #define FMC_PATT_ATTHIZ2_1 (0x02U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */
11439 #define FMC_PATT_ATTHIZ2_2 (0x04U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */
11440 #define FMC_PATT_ATTHIZ2_3 (0x08U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */
11441 #define FMC_PATT_ATTHIZ2_4 (0x10U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */
11442 #define FMC_PATT_ATTHIZ2_5 (0x20U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */
11443 #define FMC_PATT_ATTHIZ2_6 (0x40U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */
11444 #define FMC_PATT_ATTHIZ2_7 (0x80U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */
11445
11446 /****************** Bit definition for FMC_ECCR register ******************/
11447 #define FMC_ECCR_ECC2_Pos (0U)
11448 #define FMC_ECCR_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */
11449 #define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */
11450
11451 /****************** Bit definition for FMC_SDCR1 register ******************/
11452 #define FMC_SDCR1_NC_Pos (0U)
11453 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
11454 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
11455 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
11456 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
11457
11458 #define FMC_SDCR1_NR_Pos (2U)
11459 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
11460 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
11461 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
11462 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
11463
11464 #define FMC_SDCR1_MWID_Pos (4U)
11465 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
11466 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
11467 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
11468 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
11469
11470 #define FMC_SDCR1_NB_Pos (6U)
11471 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
11472 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
11473
11474 #define FMC_SDCR1_CAS_Pos (7U)
11475 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
11476 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
11477 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
11478 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
11479
11480 #define FMC_SDCR1_WP_Pos (9U)
11481 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
11482 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
11483
11484 #define FMC_SDCR1_SDCLK_Pos (10U)
11485 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
11486 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
11487 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
11488 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
11489
11490 #define FMC_SDCR1_RBURST_Pos (12U)
11491 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
11492 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
11493
11494 #define FMC_SDCR1_RPIPE_Pos (13U)
11495 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
11496 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
11497 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
11498 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
11499
11500 /****************** Bit definition for FMC_SDCR2 register ******************/
11501 #define FMC_SDCR2_NC_Pos (0U)
11502 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
11503 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
11504 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
11505 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
11506
11507 #define FMC_SDCR2_NR_Pos (2U)
11508 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
11509 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
11510 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
11511 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
11512
11513 #define FMC_SDCR2_MWID_Pos (4U)
11514 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
11515 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
11516 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
11517 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
11518
11519 #define FMC_SDCR2_NB_Pos (6U)
11520 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
11521 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
11522
11523 #define FMC_SDCR2_CAS_Pos (7U)
11524 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
11525 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
11526 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
11527 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
11528
11529 #define FMC_SDCR2_WP_Pos (9U)
11530 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
11531 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
11532
11533 #define FMC_SDCR2_SDCLK_Pos (10U)
11534 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
11535 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
11536 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
11537 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
11538
11539 #define FMC_SDCR2_RBURST_Pos (12U)
11540 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
11541 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
11542
11543 #define FMC_SDCR2_RPIPE_Pos (13U)
11544 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
11545 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
11546 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
11547 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
11548
11549 /****************** Bit definition for FMC_SDTR1 register ******************/
11550 #define FMC_SDTR1_TMRD_Pos (0U)
11551 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
11552 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
11553 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
11554 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
11555 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
11556 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
11557
11558 #define FMC_SDTR1_TXSR_Pos (4U)
11559 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
11560 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
11561 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
11562 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
11563 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
11564 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
11565
11566 #define FMC_SDTR1_TRAS_Pos (8U)
11567 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
11568 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
11569 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
11570 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
11571 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
11572 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
11573
11574 #define FMC_SDTR1_TRC_Pos (12U)
11575 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
11576 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
11577 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
11578 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
11579 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
11580
11581 #define FMC_SDTR1_TWR_Pos (16U)
11582 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
11583 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
11584 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
11585 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
11586 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
11587
11588 #define FMC_SDTR1_TRP_Pos (20U)
11589 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
11590 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
11591 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
11592 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
11593 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
11594
11595 #define FMC_SDTR1_TRCD_Pos (24U)
11596 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
11597 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
11598 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
11599 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
11600 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
11601
11602 /****************** Bit definition for FMC_SDTR2 register ******************/
11603 #define FMC_SDTR2_TMRD_Pos (0U)
11604 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
11605 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
11606 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
11607 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
11608 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
11609 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
11610
11611 #define FMC_SDTR2_TXSR_Pos (4U)
11612 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
11613 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
11614 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
11615 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
11616 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
11617 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
11618
11619 #define FMC_SDTR2_TRAS_Pos (8U)
11620 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
11621 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
11622 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
11623 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
11624 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
11625 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
11626
11627 #define FMC_SDTR2_TRC_Pos (12U)
11628 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
11629 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
11630 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
11631 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
11632 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
11633
11634 #define FMC_SDTR2_TWR_Pos (16U)
11635 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
11636 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
11637 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
11638 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
11639 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
11640
11641 #define FMC_SDTR2_TRP_Pos (20U)
11642 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
11643 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
11644 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
11645 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
11646 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
11647
11648 #define FMC_SDTR2_TRCD_Pos (24U)
11649 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
11650 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
11651 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
11652 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
11653 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
11654
11655 /****************** Bit definition for FMC_SDCMR register ******************/
11656 #define FMC_SDCMR_MODE_Pos (0U)
11657 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
11658 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
11659 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
11660 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
11661 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
11662
11663 #define FMC_SDCMR_CTB2_Pos (3U)
11664 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
11665 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
11666
11667 #define FMC_SDCMR_CTB1_Pos (4U)
11668 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
11669 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
11670
11671 #define FMC_SDCMR_NRFS_Pos (5U)
11672 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
11673 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
11674 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
11675 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
11676 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
11677 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
11678
11679 #define FMC_SDCMR_MRD_Pos (9U)
11680 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
11681 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
11682
11683 /****************** Bit definition for FMC_SDRTR register ******************/
11684 #define FMC_SDRTR_CRE_Pos (0U)
11685 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
11686 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
11687
11688 #define FMC_SDRTR_COUNT_Pos (1U)
11689 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
11690 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
11691
11692 #define FMC_SDRTR_REIE_Pos (14U)
11693 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
11694 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
11695
11696 /****************** Bit definition for FMC_SDSR register ******************/
11697 #define FMC_SDSR_RE_Pos (0U)
11698 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
11699 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
11700
11701 #define FMC_SDSR_MODES1_Pos (1U)
11702 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
11703 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
11704 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
11705 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
11706
11707 #define FMC_SDSR_MODES2_Pos (3U)
11708 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
11709 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
11710 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
11711 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
11712 #define FMC_SDSR_BUSY_Pos (5U)
11713 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
11714 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
11715
11716 /******************************************************************************/
11717 /* */
11718 /* General Purpose I/O */
11719 /* */
11720 /******************************************************************************/
11721 /****************** Bits definition for GPIO_MODER register *****************/
11722 #define GPIO_MODER_MODE0_Pos (0U)
11723 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
11724 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
11725 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
11726 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
11727 #define GPIO_MODER_MODE1_Pos (2U)
11728 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
11729 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
11730 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
11731 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
11732 #define GPIO_MODER_MODE2_Pos (4U)
11733 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
11734 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
11735 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
11736 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
11737 #define GPIO_MODER_MODE3_Pos (6U)
11738 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
11739 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
11740 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
11741 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
11742 #define GPIO_MODER_MODE4_Pos (8U)
11743 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
11744 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
11745 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
11746 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
11747 #define GPIO_MODER_MODE5_Pos (10U)
11748 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
11749 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
11750 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
11751 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
11752 #define GPIO_MODER_MODE6_Pos (12U)
11753 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
11754 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
11755 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
11756 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
11757 #define GPIO_MODER_MODE7_Pos (14U)
11758 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
11759 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
11760 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
11761 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
11762 #define GPIO_MODER_MODE8_Pos (16U)
11763 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
11764 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
11765 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
11766 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
11767 #define GPIO_MODER_MODE9_Pos (18U)
11768 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
11769 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
11770 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
11771 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
11772 #define GPIO_MODER_MODE10_Pos (20U)
11773 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
11774 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
11775 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
11776 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
11777 #define GPIO_MODER_MODE11_Pos (22U)
11778 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
11779 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
11780 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
11781 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
11782 #define GPIO_MODER_MODE12_Pos (24U)
11783 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
11784 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
11785 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
11786 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
11787 #define GPIO_MODER_MODE13_Pos (26U)
11788 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
11789 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
11790 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
11791 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
11792 #define GPIO_MODER_MODE14_Pos (28U)
11793 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
11794 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
11795 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
11796 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
11797 #define GPIO_MODER_MODE15_Pos (30U)
11798 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
11799 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
11800 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
11801 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
11802
11803 /* Legacy defines */
11804 #define GPIO_MODER_MODER0_Pos (0U)
11805 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
11806 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
11807 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
11808 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
11809 #define GPIO_MODER_MODER1_Pos (2U)
11810 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
11811 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
11812 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
11813 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
11814 #define GPIO_MODER_MODER2_Pos (4U)
11815 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
11816 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
11817 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
11818 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
11819 #define GPIO_MODER_MODER3_Pos (6U)
11820 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
11821 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
11822 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
11823 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
11824 #define GPIO_MODER_MODER4_Pos (8U)
11825 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
11826 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
11827 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
11828 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
11829 #define GPIO_MODER_MODER5_Pos (10U)
11830 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
11831 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
11832 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
11833 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
11834 #define GPIO_MODER_MODER6_Pos (12U)
11835 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
11836 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
11837 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
11838 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
11839 #define GPIO_MODER_MODER7_Pos (14U)
11840 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
11841 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
11842 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
11843 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
11844 #define GPIO_MODER_MODER8_Pos (16U)
11845 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
11846 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
11847 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
11848 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
11849 #define GPIO_MODER_MODER9_Pos (18U)
11850 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
11851 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
11852 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
11853 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
11854 #define GPIO_MODER_MODER10_Pos (20U)
11855 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
11856 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
11857 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
11858 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
11859 #define GPIO_MODER_MODER11_Pos (22U)
11860 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
11861 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
11862 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
11863 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
11864 #define GPIO_MODER_MODER12_Pos (24U)
11865 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
11866 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
11867 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
11868 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
11869 #define GPIO_MODER_MODER13_Pos (26U)
11870 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
11871 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
11872 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
11873 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
11874 #define GPIO_MODER_MODER14_Pos (28U)
11875 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
11876 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
11877 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
11878 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
11879 #define GPIO_MODER_MODER15_Pos (30U)
11880 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
11881 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
11882 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
11883 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
11884
11885 /****************** Bits definition for GPIO_OTYPER register ****************/
11886 #define GPIO_OTYPER_OT0_Pos (0U)
11887 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
11888 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
11889 #define GPIO_OTYPER_OT1_Pos (1U)
11890 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
11891 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
11892 #define GPIO_OTYPER_OT2_Pos (2U)
11893 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
11894 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
11895 #define GPIO_OTYPER_OT3_Pos (3U)
11896 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
11897 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
11898 #define GPIO_OTYPER_OT4_Pos (4U)
11899 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
11900 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
11901 #define GPIO_OTYPER_OT5_Pos (5U)
11902 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
11903 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
11904 #define GPIO_OTYPER_OT6_Pos (6U)
11905 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
11906 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
11907 #define GPIO_OTYPER_OT7_Pos (7U)
11908 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
11909 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
11910 #define GPIO_OTYPER_OT8_Pos (8U)
11911 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
11912 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
11913 #define GPIO_OTYPER_OT9_Pos (9U)
11914 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
11915 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
11916 #define GPIO_OTYPER_OT10_Pos (10U)
11917 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
11918 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
11919 #define GPIO_OTYPER_OT11_Pos (11U)
11920 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
11921 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
11922 #define GPIO_OTYPER_OT12_Pos (12U)
11923 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
11924 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
11925 #define GPIO_OTYPER_OT13_Pos (13U)
11926 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
11927 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
11928 #define GPIO_OTYPER_OT14_Pos (14U)
11929 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
11930 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
11931 #define GPIO_OTYPER_OT15_Pos (15U)
11932 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
11933 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
11934
11935 /* Legacy defines */
11936 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
11937 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
11938 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
11939 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
11940 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
11941 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
11942 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
11943 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
11944 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
11945 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
11946 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
11947 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
11948 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
11949 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
11950 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
11951 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
11952
11953 /****************** Bits definition for GPIO_OSPEEDR register ***************/
11954 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
11955 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
11956 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
11957 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
11958 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
11959 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
11960 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
11961 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
11962 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
11963 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
11964 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
11965 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
11966 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
11967 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
11968 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
11969 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
11970 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
11971 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
11972 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
11973 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
11974 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
11975 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
11976 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
11977 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
11978 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
11979 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
11980 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
11981 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
11982 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
11983 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
11984 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
11985 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
11986 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
11987 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
11988 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
11989 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
11990 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
11991 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
11992 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
11993 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
11994 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
11995 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
11996 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
11997 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
11998 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
11999 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
12000 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
12001 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
12002 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
12003 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
12004 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
12005 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
12006 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
12007 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
12008 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
12009 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
12010 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
12011 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
12012 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
12013 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
12014 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
12015 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
12016 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
12017 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
12018 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
12019 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
12020 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
12021 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
12022 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
12023 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
12024 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
12025 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
12026 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
12027 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
12028 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
12029 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
12030 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
12031 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
12032 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
12033 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
12034
12035 /* Legacy defines */
12036 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
12037 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
12038 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
12039 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
12040 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
12041 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
12042 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
12043 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
12044 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
12045 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
12046 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
12047 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
12048 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
12049 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
12050 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
12051 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
12052 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
12053 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
12054 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
12055 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
12056 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
12057 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
12058 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
12059 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
12060 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
12061 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
12062 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
12063 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
12064 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
12065 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
12066 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
12067 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
12068 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
12069 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
12070 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
12071 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
12072 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
12073 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
12074 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
12075 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
12076 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
12077 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
12078 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
12079 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
12080 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
12081 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
12082 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
12083 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
12084
12085 /****************** Bits definition for GPIO_PUPDR register *****************/
12086 #define GPIO_PUPDR_PUPD0_Pos (0U)
12087 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
12088 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
12089 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
12090 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
12091 #define GPIO_PUPDR_PUPD1_Pos (2U)
12092 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
12093 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
12094 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
12095 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
12096 #define GPIO_PUPDR_PUPD2_Pos (4U)
12097 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
12098 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
12099 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
12100 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
12101 #define GPIO_PUPDR_PUPD3_Pos (6U)
12102 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
12103 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
12104 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
12105 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
12106 #define GPIO_PUPDR_PUPD4_Pos (8U)
12107 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
12108 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
12109 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
12110 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
12111 #define GPIO_PUPDR_PUPD5_Pos (10U)
12112 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
12113 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
12114 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
12115 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
12116 #define GPIO_PUPDR_PUPD6_Pos (12U)
12117 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
12118 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
12119 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
12120 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
12121 #define GPIO_PUPDR_PUPD7_Pos (14U)
12122 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
12123 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
12124 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
12125 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
12126 #define GPIO_PUPDR_PUPD8_Pos (16U)
12127 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
12128 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
12129 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
12130 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
12131 #define GPIO_PUPDR_PUPD9_Pos (18U)
12132 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
12133 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
12134 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
12135 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
12136 #define GPIO_PUPDR_PUPD10_Pos (20U)
12137 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
12138 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
12139 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
12140 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
12141 #define GPIO_PUPDR_PUPD11_Pos (22U)
12142 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
12143 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
12144 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
12145 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
12146 #define GPIO_PUPDR_PUPD12_Pos (24U)
12147 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
12148 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
12149 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
12150 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
12151 #define GPIO_PUPDR_PUPD13_Pos (26U)
12152 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
12153 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
12154 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
12155 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
12156 #define GPIO_PUPDR_PUPD14_Pos (28U)
12157 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
12158 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
12159 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
12160 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
12161 #define GPIO_PUPDR_PUPD15_Pos (30U)
12162 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
12163 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
12164 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
12165 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
12166
12167 /* Legacy defines */
12168 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
12169 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
12170 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
12171 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
12172 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
12173 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
12174 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
12175 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
12176 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
12177 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
12178 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
12179 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
12180 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
12181 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
12182 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
12183 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
12184 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
12185 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
12186 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
12187 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
12188 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
12189 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
12190 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
12191 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
12192 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
12193 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
12194 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
12195 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
12196 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
12197 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
12198 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
12199 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
12200 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
12201 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
12202 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
12203 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
12204 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
12205 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
12206 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
12207 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
12208 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
12209 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
12210 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
12211 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
12212 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
12213 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
12214 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
12215 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
12216
12217 /****************** Bits definition for GPIO_IDR register *******************/
12218 #define GPIO_IDR_ID0_Pos (0U)
12219 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
12220 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
12221 #define GPIO_IDR_ID1_Pos (1U)
12222 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
12223 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
12224 #define GPIO_IDR_ID2_Pos (2U)
12225 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
12226 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
12227 #define GPIO_IDR_ID3_Pos (3U)
12228 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
12229 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
12230 #define GPIO_IDR_ID4_Pos (4U)
12231 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
12232 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
12233 #define GPIO_IDR_ID5_Pos (5U)
12234 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
12235 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
12236 #define GPIO_IDR_ID6_Pos (6U)
12237 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
12238 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
12239 #define GPIO_IDR_ID7_Pos (7U)
12240 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
12241 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
12242 #define GPIO_IDR_ID8_Pos (8U)
12243 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
12244 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
12245 #define GPIO_IDR_ID9_Pos (9U)
12246 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
12247 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
12248 #define GPIO_IDR_ID10_Pos (10U)
12249 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
12250 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
12251 #define GPIO_IDR_ID11_Pos (11U)
12252 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
12253 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
12254 #define GPIO_IDR_ID12_Pos (12U)
12255 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
12256 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
12257 #define GPIO_IDR_ID13_Pos (13U)
12258 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
12259 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
12260 #define GPIO_IDR_ID14_Pos (14U)
12261 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
12262 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
12263 #define GPIO_IDR_ID15_Pos (15U)
12264 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
12265 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
12266
12267 /* Legacy defines */
12268 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
12269 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
12270 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
12271 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
12272 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
12273 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
12274 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
12275 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
12276 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
12277 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
12278 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
12279 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
12280 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
12281 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
12282 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
12283 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
12284
12285 /****************** Bits definition for GPIO_ODR register *******************/
12286 #define GPIO_ODR_OD0_Pos (0U)
12287 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
12288 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
12289 #define GPIO_ODR_OD1_Pos (1U)
12290 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
12291 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
12292 #define GPIO_ODR_OD2_Pos (2U)
12293 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
12294 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
12295 #define GPIO_ODR_OD3_Pos (3U)
12296 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
12297 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
12298 #define GPIO_ODR_OD4_Pos (4U)
12299 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
12300 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
12301 #define GPIO_ODR_OD5_Pos (5U)
12302 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
12303 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
12304 #define GPIO_ODR_OD6_Pos (6U)
12305 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
12306 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
12307 #define GPIO_ODR_OD7_Pos (7U)
12308 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
12309 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
12310 #define GPIO_ODR_OD8_Pos (8U)
12311 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
12312 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
12313 #define GPIO_ODR_OD9_Pos (9U)
12314 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
12315 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
12316 #define GPIO_ODR_OD10_Pos (10U)
12317 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
12318 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
12319 #define GPIO_ODR_OD11_Pos (11U)
12320 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
12321 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
12322 #define GPIO_ODR_OD12_Pos (12U)
12323 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
12324 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
12325 #define GPIO_ODR_OD13_Pos (13U)
12326 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
12327 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
12328 #define GPIO_ODR_OD14_Pos (14U)
12329 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
12330 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
12331 #define GPIO_ODR_OD15_Pos (15U)
12332 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
12333 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
12334 /* Legacy defines */
12335 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
12336 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
12337 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
12338 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
12339 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
12340 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
12341 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
12342 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
12343 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
12344 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
12345 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
12346 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
12347 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
12348 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
12349 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
12350 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
12351
12352 /****************** Bits definition for GPIO_BSRR register ******************/
12353 #define GPIO_BSRR_BS0_Pos (0U)
12354 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
12355 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
12356 #define GPIO_BSRR_BS1_Pos (1U)
12357 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
12358 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
12359 #define GPIO_BSRR_BS2_Pos (2U)
12360 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
12361 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
12362 #define GPIO_BSRR_BS3_Pos (3U)
12363 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
12364 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
12365 #define GPIO_BSRR_BS4_Pos (4U)
12366 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
12367 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
12368 #define GPIO_BSRR_BS5_Pos (5U)
12369 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
12370 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
12371 #define GPIO_BSRR_BS6_Pos (6U)
12372 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
12373 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
12374 #define GPIO_BSRR_BS7_Pos (7U)
12375 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
12376 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
12377 #define GPIO_BSRR_BS8_Pos (8U)
12378 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
12379 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
12380 #define GPIO_BSRR_BS9_Pos (9U)
12381 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
12382 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
12383 #define GPIO_BSRR_BS10_Pos (10U)
12384 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
12385 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
12386 #define GPIO_BSRR_BS11_Pos (11U)
12387 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
12388 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
12389 #define GPIO_BSRR_BS12_Pos (12U)
12390 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
12391 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
12392 #define GPIO_BSRR_BS13_Pos (13U)
12393 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
12394 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
12395 #define GPIO_BSRR_BS14_Pos (14U)
12396 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
12397 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
12398 #define GPIO_BSRR_BS15_Pos (15U)
12399 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
12400 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
12401 #define GPIO_BSRR_BR0_Pos (16U)
12402 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
12403 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
12404 #define GPIO_BSRR_BR1_Pos (17U)
12405 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
12406 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
12407 #define GPIO_BSRR_BR2_Pos (18U)
12408 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
12409 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
12410 #define GPIO_BSRR_BR3_Pos (19U)
12411 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
12412 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
12413 #define GPIO_BSRR_BR4_Pos (20U)
12414 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
12415 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
12416 #define GPIO_BSRR_BR5_Pos (21U)
12417 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
12418 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
12419 #define GPIO_BSRR_BR6_Pos (22U)
12420 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
12421 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
12422 #define GPIO_BSRR_BR7_Pos (23U)
12423 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
12424 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
12425 #define GPIO_BSRR_BR8_Pos (24U)
12426 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
12427 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
12428 #define GPIO_BSRR_BR9_Pos (25U)
12429 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
12430 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
12431 #define GPIO_BSRR_BR10_Pos (26U)
12432 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
12433 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
12434 #define GPIO_BSRR_BR11_Pos (27U)
12435 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
12436 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
12437 #define GPIO_BSRR_BR12_Pos (28U)
12438 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
12439 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
12440 #define GPIO_BSRR_BR13_Pos (29U)
12441 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
12442 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
12443 #define GPIO_BSRR_BR14_Pos (30U)
12444 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
12445 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
12446 #define GPIO_BSRR_BR15_Pos (31U)
12447 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
12448 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
12449
12450 /* Legacy defines */
12451 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
12452 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
12453 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
12454 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
12455 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
12456 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
12457 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
12458 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
12459 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
12460 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
12461 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
12462 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
12463 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
12464 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
12465 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
12466 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
12467 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
12468 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
12469 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
12470 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
12471 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
12472 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
12473 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
12474 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
12475 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
12476 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
12477 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
12478 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
12479 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
12480 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
12481 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
12482 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
12483 /****************** Bit definition for GPIO_LCKR register *********************/
12484 #define GPIO_LCKR_LCK0_Pos (0U)
12485 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
12486 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
12487 #define GPIO_LCKR_LCK1_Pos (1U)
12488 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
12489 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
12490 #define GPIO_LCKR_LCK2_Pos (2U)
12491 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
12492 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
12493 #define GPIO_LCKR_LCK3_Pos (3U)
12494 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
12495 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
12496 #define GPIO_LCKR_LCK4_Pos (4U)
12497 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
12498 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
12499 #define GPIO_LCKR_LCK5_Pos (5U)
12500 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
12501 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
12502 #define GPIO_LCKR_LCK6_Pos (6U)
12503 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
12504 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
12505 #define GPIO_LCKR_LCK7_Pos (7U)
12506 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
12507 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
12508 #define GPIO_LCKR_LCK8_Pos (8U)
12509 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
12510 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
12511 #define GPIO_LCKR_LCK9_Pos (9U)
12512 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
12513 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
12514 #define GPIO_LCKR_LCK10_Pos (10U)
12515 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
12516 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
12517 #define GPIO_LCKR_LCK11_Pos (11U)
12518 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
12519 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
12520 #define GPIO_LCKR_LCK12_Pos (12U)
12521 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
12522 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
12523 #define GPIO_LCKR_LCK13_Pos (13U)
12524 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
12525 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
12526 #define GPIO_LCKR_LCK14_Pos (14U)
12527 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
12528 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
12529 #define GPIO_LCKR_LCK15_Pos (15U)
12530 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
12531 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
12532 #define GPIO_LCKR_LCKK_Pos (16U)
12533 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
12534 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
12535 /****************** Bit definition for GPIO_AFRL register *********************/
12536 #define GPIO_AFRL_AFSEL0_Pos (0U)
12537 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
12538 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12539 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
12540 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
12541 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
12542 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
12543 #define GPIO_AFRL_AFSEL1_Pos (4U)
12544 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
12545 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12546 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
12547 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
12548 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
12549 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
12550 #define GPIO_AFRL_AFSEL2_Pos (8U)
12551 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
12552 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12553 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
12554 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
12555 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
12556 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
12557 #define GPIO_AFRL_AFSEL3_Pos (12U)
12558 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
12559 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12560 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
12561 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
12562 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
12563 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
12564 #define GPIO_AFRL_AFSEL4_Pos (16U)
12565 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
12566 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12567 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
12568 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
12569 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
12570 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
12571 #define GPIO_AFRL_AFSEL5_Pos (20U)
12572 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
12573 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12574 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
12575 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
12576 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
12577 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
12578 #define GPIO_AFRL_AFSEL6_Pos (24U)
12579 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
12580 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12581 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
12582 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
12583 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
12584 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
12585 #define GPIO_AFRL_AFSEL7_Pos (28U)
12586 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
12587 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12588 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
12589 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
12590 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
12591 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
12592
12593 /* Legacy defines */
12594 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12595 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
12596 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
12597 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
12598 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
12599 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12600 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
12601 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
12602 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
12603 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
12604 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12605 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
12606 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
12607 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
12608 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
12609 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12610 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
12611 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
12612 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
12613 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
12614 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12615 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
12616 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
12617 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
12618 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
12619 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12620 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
12621 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
12622 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
12623 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
12624 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12625 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
12626 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
12627 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
12628 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
12629 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12630 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
12631 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
12632 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
12633 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
12634
12635 /****************** Bit definition for GPIO_AFRH register *********************/
12636 #define GPIO_AFRH_AFSEL8_Pos (0U)
12637 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
12638 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12639 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
12640 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
12641 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
12642 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
12643 #define GPIO_AFRH_AFSEL9_Pos (4U)
12644 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
12645 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12646 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
12647 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
12648 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
12649 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
12650 #define GPIO_AFRH_AFSEL10_Pos (8U)
12651 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
12652 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12653 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
12654 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
12655 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
12656 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
12657 #define GPIO_AFRH_AFSEL11_Pos (12U)
12658 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
12659 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12660 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
12661 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
12662 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
12663 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
12664 #define GPIO_AFRH_AFSEL12_Pos (16U)
12665 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
12666 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12667 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
12668 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
12669 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
12670 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
12671 #define GPIO_AFRH_AFSEL13_Pos (20U)
12672 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
12673 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12674 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
12675 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
12676 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
12677 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
12678 #define GPIO_AFRH_AFSEL14_Pos (24U)
12679 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
12680 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12681 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
12682 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
12683 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
12684 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
12685 #define GPIO_AFRH_AFSEL15_Pos (28U)
12686 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
12687 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12688 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
12689 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
12690 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
12691 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
12692
12693 /* Legacy defines */
12694 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12695 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
12696 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
12697 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
12698 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
12699 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12700 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
12701 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
12702 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
12703 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
12704 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12705 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
12706 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
12707 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
12708 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
12709 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12710 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
12711 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
12712 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
12713 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
12714 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12715 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
12716 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
12717 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
12718 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
12719 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12720 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
12721 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
12722 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
12723 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
12724 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12725 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
12726 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
12727 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
12728 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
12729 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12730 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
12731 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
12732 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
12733 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
12734
12735 /****************** Bits definition for GPIO_BRR register ******************/
12736 #define GPIO_BRR_BR0_Pos (0U)
12737 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
12738 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
12739 #define GPIO_BRR_BR1_Pos (1U)
12740 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
12741 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
12742 #define GPIO_BRR_BR2_Pos (2U)
12743 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
12744 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
12745 #define GPIO_BRR_BR3_Pos (3U)
12746 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
12747 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
12748 #define GPIO_BRR_BR4_Pos (4U)
12749 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
12750 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
12751 #define GPIO_BRR_BR5_Pos (5U)
12752 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
12753 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
12754 #define GPIO_BRR_BR6_Pos (6U)
12755 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
12756 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
12757 #define GPIO_BRR_BR7_Pos (7U)
12758 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
12759 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
12760 #define GPIO_BRR_BR8_Pos (8U)
12761 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
12762 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
12763 #define GPIO_BRR_BR9_Pos (9U)
12764 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
12765 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
12766 #define GPIO_BRR_BR10_Pos (10U)
12767 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
12768 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
12769 #define GPIO_BRR_BR11_Pos (11U)
12770 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
12771 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
12772 #define GPIO_BRR_BR12_Pos (12U)
12773 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
12774 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
12775 #define GPIO_BRR_BR13_Pos (13U)
12776 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
12777 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
12778 #define GPIO_BRR_BR14_Pos (14U)
12779 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
12780 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
12781 #define GPIO_BRR_BR15_Pos (15U)
12782 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
12783 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
12784
12785
12786 /******************************************************************************/
12787 /* */
12788 /* HASH */
12789 /* */
12790 /******************************************************************************/
12791 /****************** Bits definition for HASH_CR register ********************/
12792 #define HASH_CR_INIT_Pos (2U)
12793 #define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
12794 #define HASH_CR_INIT HASH_CR_INIT_Msk
12795 #define HASH_CR_DMAE_Pos (3U)
12796 #define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
12797 #define HASH_CR_DMAE HASH_CR_DMAE_Msk
12798 #define HASH_CR_DATATYPE_Pos (4U)
12799 #define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
12800 #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
12801 #define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
12802 #define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
12803 #define HASH_CR_MODE_Pos (6U)
12804 #define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
12805 #define HASH_CR_MODE HASH_CR_MODE_Msk
12806 #define HASH_CR_ALGO_Pos (7U)
12807 #define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
12808 #define HASH_CR_ALGO HASH_CR_ALGO_Msk
12809 #define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
12810 #define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
12811 #define HASH_CR_NBW_Pos (8U)
12812 #define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
12813 #define HASH_CR_NBW HASH_CR_NBW_Msk
12814 #define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
12815 #define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
12816 #define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
12817 #define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
12818 #define HASH_CR_DINNE_Pos (12U)
12819 #define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
12820 #define HASH_CR_DINNE HASH_CR_DINNE_Msk
12821 #define HASH_CR_MDMAT_Pos (13U)
12822 #define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
12823 #define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
12824 #define HASH_CR_LKEY_Pos (16U)
12825 #define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
12826 #define HASH_CR_LKEY HASH_CR_LKEY_Msk
12827
12828 /****************** Bits definition for HASH_STR register *******************/
12829 #define HASH_STR_NBLW_Pos (0U)
12830 #define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
12831 #define HASH_STR_NBLW HASH_STR_NBLW_Msk
12832 #define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
12833 #define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
12834 #define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
12835 #define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
12836 #define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
12837 #define HASH_STR_DCAL_Pos (8U)
12838 #define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
12839 #define HASH_STR_DCAL HASH_STR_DCAL_Msk
12840 /* Aliases for HASH_STR register */
12841 #define HASH_STR_NBW HASH_STR_NBLW
12842 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
12843 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
12844 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
12845 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
12846 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
12847
12848 /****************** Bits definition for HASH_IMR register *******************/
12849 #define HASH_IMR_DINIE_Pos (0U)
12850 #define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
12851 #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
12852 #define HASH_IMR_DCIE_Pos (1U)
12853 #define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
12854 #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
12855 /* Aliases for HASH_IMR register */
12856 #define HASH_IMR_DINIM HASH_IMR_DINIE
12857 #define HASH_IMR_DCIM HASH_IMR_DCIE
12858
12859 /****************** Bits definition for HASH_SR register ********************/
12860 #define HASH_SR_DINIS_Pos (0U)
12861 #define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
12862 #define HASH_SR_DINIS HASH_SR_DINIS_Msk
12863 #define HASH_SR_DCIS_Pos (1U)
12864 #define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
12865 #define HASH_SR_DCIS HASH_SR_DCIS_Msk
12866 #define HASH_SR_DMAS_Pos (2U)
12867 #define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
12868 #define HASH_SR_DMAS HASH_SR_DMAS_Msk
12869 #define HASH_SR_BUSY_Pos (3U)
12870 #define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
12871 #define HASH_SR_BUSY HASH_SR_BUSY_Msk
12872
12873 /******************************************************************************/
12874 /* */
12875 /* Inter-integrated Circuit Interface */
12876 /* */
12877 /******************************************************************************/
12878 /******************* Bit definition for I2C_CR1 register ********************/
12879 #define I2C_CR1_PE_Pos (0U)
12880 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
12881 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
12882 #define I2C_CR1_SMBUS_Pos (1U)
12883 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
12884 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
12885 #define I2C_CR1_SMBTYPE_Pos (3U)
12886 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
12887 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
12888 #define I2C_CR1_ENARP_Pos (4U)
12889 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
12890 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
12891 #define I2C_CR1_ENPEC_Pos (5U)
12892 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
12893 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
12894 #define I2C_CR1_ENGC_Pos (6U)
12895 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
12896 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
12897 #define I2C_CR1_NOSTRETCH_Pos (7U)
12898 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
12899 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
12900 #define I2C_CR1_START_Pos (8U)
12901 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
12902 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
12903 #define I2C_CR1_STOP_Pos (9U)
12904 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
12905 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
12906 #define I2C_CR1_ACK_Pos (10U)
12907 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
12908 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
12909 #define I2C_CR1_POS_Pos (11U)
12910 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
12911 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
12912 #define I2C_CR1_PEC_Pos (12U)
12913 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
12914 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
12915 #define I2C_CR1_ALERT_Pos (13U)
12916 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
12917 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
12918 #define I2C_CR1_SWRST_Pos (15U)
12919 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
12920 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
12921
12922 /******************* Bit definition for I2C_CR2 register ********************/
12923 #define I2C_CR2_FREQ_Pos (0U)
12924 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
12925 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
12926 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
12927 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
12928 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
12929 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
12930 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
12931 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
12932
12933 #define I2C_CR2_ITERREN_Pos (8U)
12934 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
12935 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
12936 #define I2C_CR2_ITEVTEN_Pos (9U)
12937 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
12938 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
12939 #define I2C_CR2_ITBUFEN_Pos (10U)
12940 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
12941 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
12942 #define I2C_CR2_DMAEN_Pos (11U)
12943 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
12944 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
12945 #define I2C_CR2_LAST_Pos (12U)
12946 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
12947 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
12948
12949 /******************* Bit definition for I2C_OAR1 register *******************/
12950 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
12951 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
12952
12953 #define I2C_OAR1_ADD0_Pos (0U)
12954 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
12955 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
12956 #define I2C_OAR1_ADD1_Pos (1U)
12957 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
12958 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
12959 #define I2C_OAR1_ADD2_Pos (2U)
12960 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
12961 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
12962 #define I2C_OAR1_ADD3_Pos (3U)
12963 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
12964 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
12965 #define I2C_OAR1_ADD4_Pos (4U)
12966 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
12967 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
12968 #define I2C_OAR1_ADD5_Pos (5U)
12969 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
12970 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
12971 #define I2C_OAR1_ADD6_Pos (6U)
12972 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
12973 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
12974 #define I2C_OAR1_ADD7_Pos (7U)
12975 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
12976 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
12977 #define I2C_OAR1_ADD8_Pos (8U)
12978 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
12979 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
12980 #define I2C_OAR1_ADD9_Pos (9U)
12981 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
12982 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
12983
12984 #define I2C_OAR1_ADDMODE_Pos (15U)
12985 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
12986 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
12987
12988 /******************* Bit definition for I2C_OAR2 register *******************/
12989 #define I2C_OAR2_ENDUAL_Pos (0U)
12990 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
12991 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
12992 #define I2C_OAR2_ADD2_Pos (1U)
12993 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
12994 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
12995
12996 /******************** Bit definition for I2C_DR register ********************/
12997 #define I2C_DR_DR_Pos (0U)
12998 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
12999 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
13000
13001 /******************* Bit definition for I2C_SR1 register ********************/
13002 #define I2C_SR1_SB_Pos (0U)
13003 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
13004 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
13005 #define I2C_SR1_ADDR_Pos (1U)
13006 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
13007 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
13008 #define I2C_SR1_BTF_Pos (2U)
13009 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
13010 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
13011 #define I2C_SR1_ADD10_Pos (3U)
13012 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
13013 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
13014 #define I2C_SR1_STOPF_Pos (4U)
13015 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
13016 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
13017 #define I2C_SR1_RXNE_Pos (6U)
13018 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
13019 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
13020 #define I2C_SR1_TXE_Pos (7U)
13021 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
13022 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
13023 #define I2C_SR1_BERR_Pos (8U)
13024 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
13025 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
13026 #define I2C_SR1_ARLO_Pos (9U)
13027 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
13028 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
13029 #define I2C_SR1_AF_Pos (10U)
13030 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
13031 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
13032 #define I2C_SR1_OVR_Pos (11U)
13033 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
13034 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
13035 #define I2C_SR1_PECERR_Pos (12U)
13036 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
13037 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
13038 #define I2C_SR1_TIMEOUT_Pos (14U)
13039 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
13040 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
13041 #define I2C_SR1_SMBALERT_Pos (15U)
13042 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
13043 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
13044
13045 /******************* Bit definition for I2C_SR2 register ********************/
13046 #define I2C_SR2_MSL_Pos (0U)
13047 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
13048 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
13049 #define I2C_SR2_BUSY_Pos (1U)
13050 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
13051 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
13052 #define I2C_SR2_TRA_Pos (2U)
13053 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
13054 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
13055 #define I2C_SR2_GENCALL_Pos (4U)
13056 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
13057 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
13058 #define I2C_SR2_SMBDEFAULT_Pos (5U)
13059 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
13060 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
13061 #define I2C_SR2_SMBHOST_Pos (6U)
13062 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
13063 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
13064 #define I2C_SR2_DUALF_Pos (7U)
13065 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
13066 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
13067 #define I2C_SR2_PEC_Pos (8U)
13068 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
13069 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
13070
13071 /******************* Bit definition for I2C_CCR register ********************/
13072 #define I2C_CCR_CCR_Pos (0U)
13073 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
13074 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
13075 #define I2C_CCR_DUTY_Pos (14U)
13076 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
13077 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
13078 #define I2C_CCR_FS_Pos (15U)
13079 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
13080 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
13081
13082 /****************** Bit definition for I2C_TRISE register *******************/
13083 #define I2C_TRISE_TRISE_Pos (0U)
13084 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
13085 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
13086
13087 /****************** Bit definition for I2C_FLTR register *******************/
13088 #define I2C_FLTR_DNF_Pos (0U)
13089 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
13090 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
13091 #define I2C_FLTR_ANOFF_Pos (4U)
13092 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
13093 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
13094
13095 /******************************************************************************/
13096 /* */
13097 /* Independent WATCHDOG */
13098 /* */
13099 /******************************************************************************/
13100 /******************* Bit definition for IWDG_KR register ********************/
13101 #define IWDG_KR_KEY_Pos (0U)
13102 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
13103 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
13104
13105 /******************* Bit definition for IWDG_PR register ********************/
13106 #define IWDG_PR_PR_Pos (0U)
13107 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
13108 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
13109 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
13110 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
13111 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
13112
13113 /******************* Bit definition for IWDG_RLR register *******************/
13114 #define IWDG_RLR_RL_Pos (0U)
13115 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
13116 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
13117
13118 /******************* Bit definition for IWDG_SR register ********************/
13119 #define IWDG_SR_PVU_Pos (0U)
13120 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
13121 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
13122 #define IWDG_SR_RVU_Pos (1U)
13123 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
13124 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
13125
13126
13127 /******************************************************************************/
13128 /* */
13129 /* LCD-TFT Display Controller (LTDC) */
13130 /* */
13131 /******************************************************************************/
13132
13133 /******************** Bit definition for LTDC_SSCR register *****************/
13134
13135 #define LTDC_SSCR_VSH_Pos (0U)
13136 #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
13137 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
13138 #define LTDC_SSCR_HSW_Pos (16U)
13139 #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
13140 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
13141
13142 /******************** Bit definition for LTDC_BPCR register *****************/
13143
13144 #define LTDC_BPCR_AVBP_Pos (0U)
13145 #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
13146 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
13147 #define LTDC_BPCR_AHBP_Pos (16U)
13148 #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
13149 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
13150
13151 /******************** Bit definition for LTDC_AWCR register *****************/
13152
13153 #define LTDC_AWCR_AAH_Pos (0U)
13154 #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
13155 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
13156 #define LTDC_AWCR_AAW_Pos (16U)
13157 #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
13158 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
13159
13160 /******************** Bit definition for LTDC_TWCR register *****************/
13161
13162 #define LTDC_TWCR_TOTALH_Pos (0U)
13163 #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
13164 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
13165 #define LTDC_TWCR_TOTALW_Pos (16U)
13166 #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
13167 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
13168
13169 /******************** Bit definition for LTDC_GCR register ******************/
13170
13171 #define LTDC_GCR_LTDCEN_Pos (0U)
13172 #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
13173 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
13174 #define LTDC_GCR_DBW_Pos (4U)
13175 #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
13176 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
13177 #define LTDC_GCR_DGW_Pos (8U)
13178 #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
13179 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
13180 #define LTDC_GCR_DRW_Pos (12U)
13181 #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
13182 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
13183 #define LTDC_GCR_DEN_Pos (16U)
13184 #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
13185 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
13186 #define LTDC_GCR_PCPOL_Pos (28U)
13187 #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
13188 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
13189 #define LTDC_GCR_DEPOL_Pos (29U)
13190 #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
13191 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
13192 #define LTDC_GCR_VSPOL_Pos (30U)
13193 #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
13194 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
13195 #define LTDC_GCR_HSPOL_Pos (31U)
13196 #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
13197 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
13198
13199 /* Legacy defines */
13200 #define LTDC_GCR_DTEN LTDC_GCR_DEN
13201
13202 /******************** Bit definition for LTDC_SRCR register *****************/
13203
13204 #define LTDC_SRCR_IMR_Pos (0U)
13205 #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
13206 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
13207 #define LTDC_SRCR_VBR_Pos (1U)
13208 #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
13209 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
13210
13211 /******************** Bit definition for LTDC_BCCR register *****************/
13212
13213 #define LTDC_BCCR_BCBLUE_Pos (0U)
13214 #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
13215 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
13216 #define LTDC_BCCR_BCGREEN_Pos (8U)
13217 #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
13218 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
13219 #define LTDC_BCCR_BCRED_Pos (16U)
13220 #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
13221 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
13222
13223 /******************** Bit definition for LTDC_IER register ******************/
13224
13225 #define LTDC_IER_LIE_Pos (0U)
13226 #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
13227 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
13228 #define LTDC_IER_FUIE_Pos (1U)
13229 #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
13230 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
13231 #define LTDC_IER_TERRIE_Pos (2U)
13232 #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
13233 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
13234 #define LTDC_IER_RRIE_Pos (3U)
13235 #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
13236 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
13237
13238 /******************** Bit definition for LTDC_ISR register ******************/
13239
13240 #define LTDC_ISR_LIF_Pos (0U)
13241 #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
13242 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
13243 #define LTDC_ISR_FUIF_Pos (1U)
13244 #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
13245 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
13246 #define LTDC_ISR_TERRIF_Pos (2U)
13247 #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
13248 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
13249 #define LTDC_ISR_RRIF_Pos (3U)
13250 #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
13251 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
13252
13253 /******************** Bit definition for LTDC_ICR register ******************/
13254
13255 #define LTDC_ICR_CLIF_Pos (0U)
13256 #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
13257 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
13258 #define LTDC_ICR_CFUIF_Pos (1U)
13259 #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
13260 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
13261 #define LTDC_ICR_CTERRIF_Pos (2U)
13262 #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
13263 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
13264 #define LTDC_ICR_CRRIF_Pos (3U)
13265 #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
13266 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
13267
13268 /******************** Bit definition for LTDC_LIPCR register ****************/
13269
13270 #define LTDC_LIPCR_LIPOS_Pos (0U)
13271 #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
13272 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
13273
13274 /******************** Bit definition for LTDC_CPSR register *****************/
13275
13276 #define LTDC_CPSR_CYPOS_Pos (0U)
13277 #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
13278 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
13279 #define LTDC_CPSR_CXPOS_Pos (16U)
13280 #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
13281 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
13282
13283 /******************** Bit definition for LTDC_CDSR register *****************/
13284
13285 #define LTDC_CDSR_VDES_Pos (0U)
13286 #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
13287 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
13288 #define LTDC_CDSR_HDES_Pos (1U)
13289 #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
13290 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
13291 #define LTDC_CDSR_VSYNCS_Pos (2U)
13292 #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
13293 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
13294 #define LTDC_CDSR_HSYNCS_Pos (3U)
13295 #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
13296 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
13297
13298 /******************** Bit definition for LTDC_LxCR register *****************/
13299
13300 #define LTDC_LxCR_LEN_Pos (0U)
13301 #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
13302 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
13303 #define LTDC_LxCR_COLKEN_Pos (1U)
13304 #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
13305 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
13306 #define LTDC_LxCR_CLUTEN_Pos (4U)
13307 #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
13308 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
13309
13310 /******************** Bit definition for LTDC_LxWHPCR register **************/
13311
13312 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
13313 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
13314 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
13315 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
13316 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
13317 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
13318
13319 /******************** Bit definition for LTDC_LxWVPCR register **************/
13320
13321 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
13322 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
13323 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
13324 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
13325 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
13326 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
13327
13328 /******************** Bit definition for LTDC_LxCKCR register ***************/
13329
13330 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
13331 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
13332 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
13333 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
13334 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
13335 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
13336 #define LTDC_LxCKCR_CKRED_Pos (16U)
13337 #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
13338 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
13339
13340 /******************** Bit definition for LTDC_LxPFCR register ***************/
13341
13342 #define LTDC_LxPFCR_PF_Pos (0U)
13343 #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
13344 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
13345
13346 /******************** Bit definition for LTDC_LxCACR register ***************/
13347
13348 #define LTDC_LxCACR_CONSTA_Pos (0U)
13349 #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
13350 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
13351
13352 /******************** Bit definition for LTDC_LxDCCR register ***************/
13353
13354 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
13355 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
13356 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
13357 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
13358 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
13359 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
13360 #define LTDC_LxDCCR_DCRED_Pos (16U)
13361 #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
13362 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
13363 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
13364 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
13365 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
13366
13367 /******************** Bit definition for LTDC_LxBFCR register ***************/
13368
13369 #define LTDC_LxBFCR_BF2_Pos (0U)
13370 #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
13371 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
13372 #define LTDC_LxBFCR_BF1_Pos (8U)
13373 #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
13374 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
13375
13376 /******************** Bit definition for LTDC_LxCFBAR register **************/
13377
13378 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
13379 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
13380 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
13381
13382 /******************** Bit definition for LTDC_LxCFBLR register **************/
13383
13384 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
13385 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
13386 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
13387 #define LTDC_LxCFBLR_CFBP_Pos (16U)
13388 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
13389 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
13390
13391 /******************** Bit definition for LTDC_LxCFBLNR register *************/
13392
13393 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
13394 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
13395 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
13396
13397 /******************** Bit definition for LTDC_LxCLUTWR register *************/
13398
13399 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
13400 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
13401 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
13402 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
13403 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
13404 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
13405 #define LTDC_LxCLUTWR_RED_Pos (16U)
13406 #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
13407 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
13408 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
13409 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
13410 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
13411
13412
13413 /******************************************************************************/
13414 /* */
13415 /* Power Control */
13416 /* */
13417 /******************************************************************************/
13418 /******************** Bit definition for PWR_CR register ********************/
13419 #define PWR_CR_LPDS_Pos (0U)
13420 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
13421 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
13422 #define PWR_CR_PDDS_Pos (1U)
13423 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
13424 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
13425 #define PWR_CR_CWUF_Pos (2U)
13426 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
13427 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
13428 #define PWR_CR_CSBF_Pos (3U)
13429 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
13430 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
13431 #define PWR_CR_PVDE_Pos (4U)
13432 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
13433 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
13434
13435 #define PWR_CR_PLS_Pos (5U)
13436 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
13437 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
13438 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
13439 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
13440 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
13441
13442 /*!< PVD level configuration */
13443 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
13444 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
13445 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
13446 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
13447 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
13448 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
13449 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
13450 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
13451 #define PWR_CR_DBP_Pos (8U)
13452 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
13453 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
13454 #define PWR_CR_FPDS_Pos (9U)
13455 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
13456 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
13457 #define PWR_CR_LPLVDS_Pos (10U)
13458 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
13459 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
13460 #define PWR_CR_MRLVDS_Pos (11U)
13461 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
13462 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
13463 #define PWR_CR_ADCDC1_Pos (13U)
13464 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
13465 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
13466 #define PWR_CR_VOS_Pos (14U)
13467 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
13468 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
13469 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
13470 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
13471 #define PWR_CR_ODEN_Pos (16U)
13472 #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
13473 #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
13474 #define PWR_CR_ODSWEN_Pos (17U)
13475 #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
13476 #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
13477 #define PWR_CR_UDEN_Pos (18U)
13478 #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
13479 #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
13480 #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
13481 #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
13482
13483 /* Legacy define */
13484 #define PWR_CR_PMODE PWR_CR_VOS
13485 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
13486 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
13487
13488 /******************* Bit definition for PWR_CSR register ********************/
13489 #define PWR_CSR_WUF_Pos (0U)
13490 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
13491 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
13492 #define PWR_CSR_SBF_Pos (1U)
13493 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
13494 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
13495 #define PWR_CSR_PVDO_Pos (2U)
13496 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
13497 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
13498 #define PWR_CSR_BRR_Pos (3U)
13499 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
13500 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
13501 #define PWR_CSR_WUPP_Pos (7U)
13502 #define PWR_CSR_WUPP_Msk (0x1U << PWR_CSR_WUPP_Pos) /*!< 0x00000080 */
13503 #define PWR_CSR_WUPP PWR_CSR_WUPP_Msk /*!< WKUP pin Polarity */
13504 #define PWR_CSR_EWUP_Pos (8U)
13505 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
13506 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
13507 #define PWR_CSR_BRE_Pos (9U)
13508 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
13509 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
13510 #define PWR_CSR_VOSRDY_Pos (14U)
13511 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
13512 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
13513 #define PWR_CSR_ODRDY_Pos (16U)
13514 #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
13515 #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
13516 #define PWR_CSR_ODSWRDY_Pos (17U)
13517 #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
13518 #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
13519 #define PWR_CSR_UDRDY_Pos (18U)
13520 #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
13521 #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
13522 /* Legacy define */
13523 #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
13524
13525 /* Legacy define */
13526 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
13527
13528 /******************************************************************************/
13529 /* */
13530 /* QUADSPI */
13531 /* */
13532 /******************************************************************************/
13533 /***************** Bit definition for QUADSPI_CR register *******************/
13534 #define QUADSPI_CR_EN_Pos (0U)
13535 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
13536 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
13537 #define QUADSPI_CR_ABORT_Pos (1U)
13538 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
13539 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
13540 #define QUADSPI_CR_DMAEN_Pos (2U)
13541 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
13542 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
13543 #define QUADSPI_CR_TCEN_Pos (3U)
13544 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
13545 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
13546 #define QUADSPI_CR_SSHIFT_Pos (4U)
13547 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
13548 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
13549 #define QUADSPI_CR_DFM_Pos (6U)
13550 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
13551 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
13552 #define QUADSPI_CR_FSEL_Pos (7U)
13553 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
13554 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
13555 #define QUADSPI_CR_FTHRES_Pos (8U)
13556 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
13557 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
13558 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
13559 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
13560 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
13561 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
13562 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
13563 #define QUADSPI_CR_TEIE_Pos (16U)
13564 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
13565 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
13566 #define QUADSPI_CR_TCIE_Pos (17U)
13567 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
13568 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
13569 #define QUADSPI_CR_FTIE_Pos (18U)
13570 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
13571 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
13572 #define QUADSPI_CR_SMIE_Pos (19U)
13573 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
13574 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
13575 #define QUADSPI_CR_TOIE_Pos (20U)
13576 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
13577 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
13578 #define QUADSPI_CR_APMS_Pos (22U)
13579 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
13580 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
13581 #define QUADSPI_CR_PMM_Pos (23U)
13582 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
13583 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
13584 #define QUADSPI_CR_PRESCALER_Pos (24U)
13585 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
13586 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
13587 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
13588 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
13589 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
13590 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
13591 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
13592 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
13593 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
13594 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
13595
13596 /***************** Bit definition for QUADSPI_DCR register ******************/
13597 #define QUADSPI_DCR_CKMODE_Pos (0U)
13598 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
13599 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
13600 #define QUADSPI_DCR_CSHT_Pos (8U)
13601 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
13602 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
13603 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
13604 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
13605 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
13606 #define QUADSPI_DCR_FSIZE_Pos (16U)
13607 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
13608 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
13609 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
13610 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
13611 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
13612 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
13613 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
13614
13615 /****************** Bit definition for QUADSPI_SR register *******************/
13616 #define QUADSPI_SR_TEF_Pos (0U)
13617 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
13618 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
13619 #define QUADSPI_SR_TCF_Pos (1U)
13620 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
13621 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
13622 #define QUADSPI_SR_FTF_Pos (2U)
13623 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
13624 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
13625 #define QUADSPI_SR_SMF_Pos (3U)
13626 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
13627 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
13628 #define QUADSPI_SR_TOF_Pos (4U)
13629 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
13630 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
13631 #define QUADSPI_SR_BUSY_Pos (5U)
13632 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
13633 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
13634 #define QUADSPI_SR_FLEVEL_Pos (8U)
13635 #define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
13636 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
13637 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
13638 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
13639 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
13640 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
13641 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
13642 #define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
13643
13644 /****************** Bit definition for QUADSPI_FCR register ******************/
13645 #define QUADSPI_FCR_CTEF_Pos (0U)
13646 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
13647 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
13648 #define QUADSPI_FCR_CTCF_Pos (1U)
13649 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
13650 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
13651 #define QUADSPI_FCR_CSMF_Pos (3U)
13652 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
13653 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
13654 #define QUADSPI_FCR_CTOF_Pos (4U)
13655 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
13656 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
13657
13658 /****************** Bit definition for QUADSPI_DLR register ******************/
13659 #define QUADSPI_DLR_DL_Pos (0U)
13660 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
13661 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
13662
13663 /****************** Bit definition for QUADSPI_CCR register ******************/
13664 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
13665 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
13666 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
13667 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
13668 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
13669 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
13670 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
13671 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
13672 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
13673 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
13674 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
13675 #define QUADSPI_CCR_IMODE_Pos (8U)
13676 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
13677 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
13678 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
13679 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
13680 #define QUADSPI_CCR_ADMODE_Pos (10U)
13681 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
13682 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
13683 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
13684 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
13685 #define QUADSPI_CCR_ADSIZE_Pos (12U)
13686 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
13687 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
13688 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
13689 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
13690 #define QUADSPI_CCR_ABMODE_Pos (14U)
13691 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
13692 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
13693 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
13694 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
13695 #define QUADSPI_CCR_ABSIZE_Pos (16U)
13696 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
13697 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
13698 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
13699 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
13700 #define QUADSPI_CCR_DCYC_Pos (18U)
13701 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
13702 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
13703 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
13704 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
13705 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
13706 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
13707 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
13708 #define QUADSPI_CCR_DMODE_Pos (24U)
13709 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
13710 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
13711 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
13712 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
13713 #define QUADSPI_CCR_FMODE_Pos (26U)
13714 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
13715 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
13716 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
13717 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
13718 #define QUADSPI_CCR_SIOO_Pos (28U)
13719 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
13720 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
13721 #define QUADSPI_CCR_DHHC_Pos (30U)
13722 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
13723 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
13724 #define QUADSPI_CCR_DDRM_Pos (31U)
13725 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
13726 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
13727 /****************** Bit definition for QUADSPI_AR register *******************/
13728 #define QUADSPI_AR_ADDRESS_Pos (0U)
13729 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
13730 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
13731
13732 /****************** Bit definition for QUADSPI_ABR register ******************/
13733 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
13734 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
13735 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
13736
13737 /****************** Bit definition for QUADSPI_DR register *******************/
13738 #define QUADSPI_DR_DATA_Pos (0U)
13739 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
13740 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
13741
13742 /****************** Bit definition for QUADSPI_PSMKR register ****************/
13743 #define QUADSPI_PSMKR_MASK_Pos (0U)
13744 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
13745 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
13746
13747 /****************** Bit definition for QUADSPI_PSMAR register ****************/
13748 #define QUADSPI_PSMAR_MATCH_Pos (0U)
13749 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
13750 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
13751
13752 /****************** Bit definition for QUADSPI_PIR register *****************/
13753 #define QUADSPI_PIR_INTERVAL_Pos (0U)
13754 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
13755 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
13756
13757 /****************** Bit definition for QUADSPI_LPTR register *****************/
13758 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
13759 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
13760 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
13761
13762 /******************************************************************************/
13763 /* */
13764 /* Reset and Clock Control */
13765 /* */
13766 /******************************************************************************/
13767 /******************** Bit definition for RCC_CR register ********************/
13768 #define RCC_CR_HSION_Pos (0U)
13769 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
13770 #define RCC_CR_HSION RCC_CR_HSION_Msk
13771 #define RCC_CR_HSIRDY_Pos (1U)
13772 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
13773 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
13774
13775 #define RCC_CR_HSITRIM_Pos (3U)
13776 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
13777 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
13778 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
13779 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
13780 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
13781 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
13782 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
13783
13784 #define RCC_CR_HSICAL_Pos (8U)
13785 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
13786 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
13787 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
13788 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
13789 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
13790 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
13791 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
13792 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
13793 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
13794 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
13795
13796 #define RCC_CR_HSEON_Pos (16U)
13797 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
13798 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
13799 #define RCC_CR_HSERDY_Pos (17U)
13800 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
13801 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
13802 #define RCC_CR_HSEBYP_Pos (18U)
13803 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
13804 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
13805 #define RCC_CR_CSSON_Pos (19U)
13806 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
13807 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
13808 #define RCC_CR_PLLON_Pos (24U)
13809 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
13810 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
13811 #define RCC_CR_PLLRDY_Pos (25U)
13812 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
13813 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
13814 /*
13815 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13816 */
13817 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
13818
13819 #define RCC_CR_PLLI2SON_Pos (26U)
13820 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
13821 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
13822 #define RCC_CR_PLLI2SRDY_Pos (27U)
13823 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
13824 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
13825 /*
13826 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13827 */
13828 #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
13829
13830 #define RCC_CR_PLLSAION_Pos (28U)
13831 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
13832 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
13833 #define RCC_CR_PLLSAIRDY_Pos (29U)
13834 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
13835 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
13836
13837 /******************** Bit definition for RCC_PLLCFGR register ***************/
13838 #define RCC_PLLCFGR_PLLM_Pos (0U)
13839 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
13840 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
13841 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
13842 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
13843 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
13844 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
13845 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
13846 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
13847
13848 #define RCC_PLLCFGR_PLLN_Pos (6U)
13849 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
13850 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
13851 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
13852 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
13853 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
13854 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
13855 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
13856 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
13857 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
13858 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
13859 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
13860
13861 #define RCC_PLLCFGR_PLLP_Pos (16U)
13862 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
13863 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
13864 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
13865 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
13866
13867 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
13868 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
13869 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
13870 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
13871 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
13872 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
13873 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
13874
13875 #define RCC_PLLCFGR_PLLQ_Pos (24U)
13876 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
13877 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
13878 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
13879 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
13880 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
13881 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
13882
13883 #define RCC_PLLCFGR_PLLR_Pos (28U)
13884 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
13885 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
13886 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
13887 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
13888 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
13889
13890 /******************** Bit definition for RCC_CFGR register ******************/
13891 /*!< SW configuration */
13892 #define RCC_CFGR_SW_Pos (0U)
13893 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
13894 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
13895 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
13896 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
13897
13898 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
13899 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
13900 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
13901
13902 /*!< SWS configuration */
13903 #define RCC_CFGR_SWS_Pos (2U)
13904 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
13905 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
13906 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
13907 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
13908
13909 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
13910 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
13911 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
13912
13913 /*!< HPRE configuration */
13914 #define RCC_CFGR_HPRE_Pos (4U)
13915 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
13916 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
13917 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
13918 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
13919 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
13920 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
13921
13922 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
13923 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
13924 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
13925 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
13926 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
13927 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
13928 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
13929 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
13930 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
13931
13932 /*!< PPRE1 configuration */
13933 #define RCC_CFGR_PPRE1_Pos (10U)
13934 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
13935 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
13936 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
13937 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
13938 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
13939
13940 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
13941 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
13942 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
13943 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
13944 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
13945
13946 /*!< PPRE2 configuration */
13947 #define RCC_CFGR_PPRE2_Pos (13U)
13948 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
13949 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
13950 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
13951 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
13952 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
13953
13954 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
13955 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
13956 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
13957 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
13958 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
13959
13960 /*!< RTCPRE configuration */
13961 #define RCC_CFGR_RTCPRE_Pos (16U)
13962 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
13963 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
13964 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
13965 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
13966 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
13967 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
13968 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
13969
13970 /*!< MCO1 configuration */
13971 #define RCC_CFGR_MCO1_Pos (21U)
13972 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
13973 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
13974 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
13975 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
13976
13977 #define RCC_CFGR_I2SSRC_Pos (23U)
13978 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
13979 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
13980
13981 #define RCC_CFGR_MCO1PRE_Pos (24U)
13982 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
13983 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
13984 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
13985 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
13986 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
13987
13988 #define RCC_CFGR_MCO2PRE_Pos (27U)
13989 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
13990 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
13991 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
13992 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
13993 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
13994
13995 #define RCC_CFGR_MCO2_Pos (30U)
13996 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
13997 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
13998 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
13999 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
14000
14001 /******************** Bit definition for RCC_CIR register *******************/
14002 #define RCC_CIR_LSIRDYF_Pos (0U)
14003 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
14004 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
14005 #define RCC_CIR_LSERDYF_Pos (1U)
14006 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
14007 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
14008 #define RCC_CIR_HSIRDYF_Pos (2U)
14009 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
14010 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
14011 #define RCC_CIR_HSERDYF_Pos (3U)
14012 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
14013 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
14014 #define RCC_CIR_PLLRDYF_Pos (4U)
14015 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
14016 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
14017 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
14018 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
14019 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
14020
14021 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
14022 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
14023 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
14024 #define RCC_CIR_CSSF_Pos (7U)
14025 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
14026 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
14027 #define RCC_CIR_LSIRDYIE_Pos (8U)
14028 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
14029 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
14030 #define RCC_CIR_LSERDYIE_Pos (9U)
14031 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
14032 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
14033 #define RCC_CIR_HSIRDYIE_Pos (10U)
14034 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
14035 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
14036 #define RCC_CIR_HSERDYIE_Pos (11U)
14037 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
14038 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
14039 #define RCC_CIR_PLLRDYIE_Pos (12U)
14040 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
14041 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
14042 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
14043 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
14044 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
14045
14046 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
14047 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
14048 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
14049 #define RCC_CIR_LSIRDYC_Pos (16U)
14050 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
14051 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
14052 #define RCC_CIR_LSERDYC_Pos (17U)
14053 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
14054 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
14055 #define RCC_CIR_HSIRDYC_Pos (18U)
14056 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
14057 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
14058 #define RCC_CIR_HSERDYC_Pos (19U)
14059 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
14060 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
14061 #define RCC_CIR_PLLRDYC_Pos (20U)
14062 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
14063 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
14064 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
14065 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
14066 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
14067 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
14068 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
14069 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
14070
14071 #define RCC_CIR_CSSC_Pos (23U)
14072 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
14073 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
14074
14075 /******************** Bit definition for RCC_AHB1RSTR register **************/
14076 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
14077 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
14078 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
14079 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
14080 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
14081 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
14082 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
14083 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
14084 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
14085 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
14086 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
14087 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
14088 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
14089 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
14090 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
14091 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
14092 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
14093 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
14094 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
14095 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
14096 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
14097 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
14098 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
14099 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
14100 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
14101 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
14102 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
14103 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
14104 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
14105 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
14106 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
14107 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
14108 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
14109 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
14110 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
14111 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
14112 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
14113 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
14114 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
14115 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
14116 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
14117 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
14118 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
14119 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
14120 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
14121 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
14122 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
14123 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
14124 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
14125 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
14126 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
14127
14128 /******************** Bit definition for RCC_AHB2RSTR register **************/
14129 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
14130 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
14131 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
14132 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
14133 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
14134 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
14135 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
14136 #define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
14137 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
14138 /* maintained for legacy purpose */
14139 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
14140 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
14141 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
14142 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
14143 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
14144 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
14145 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
14146 /******************** Bit definition for RCC_AHB3RSTR register **************/
14147 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
14148 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
14149 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
14150 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
14151 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
14152 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
14153
14154
14155 /******************** Bit definition for RCC_APB1RSTR register **************/
14156 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
14157 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
14158 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
14159 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
14160 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
14161 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
14162 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
14163 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
14164 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
14165 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
14166 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
14167 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
14168 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
14169 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
14170 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
14171 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
14172 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
14173 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
14174 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
14175 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
14176 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
14177 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
14178 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
14179 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
14180 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
14181 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
14182 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
14183 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
14184 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
14185 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
14186 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
14187 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
14188 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
14189 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
14190 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
14191 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
14192 #define RCC_APB1RSTR_USART2RST_Pos (17U)
14193 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
14194 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
14195 #define RCC_APB1RSTR_USART3RST_Pos (18U)
14196 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
14197 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
14198 #define RCC_APB1RSTR_UART4RST_Pos (19U)
14199 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
14200 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
14201 #define RCC_APB1RSTR_UART5RST_Pos (20U)
14202 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
14203 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
14204 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
14205 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
14206 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
14207 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
14208 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
14209 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
14210 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
14211 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
14212 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
14213 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
14214 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
14215 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
14216 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
14217 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
14218 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
14219 #define RCC_APB1RSTR_PWRRST_Pos (28U)
14220 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
14221 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
14222 #define RCC_APB1RSTR_DACRST_Pos (29U)
14223 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
14224 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
14225 #define RCC_APB1RSTR_UART7RST_Pos (30U)
14226 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
14227 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
14228 #define RCC_APB1RSTR_UART8RST_Pos (31U)
14229 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
14230 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
14231
14232 /******************** Bit definition for RCC_APB2RSTR register **************/
14233 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
14234 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
14235 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
14236 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
14237 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
14238 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
14239 #define RCC_APB2RSTR_USART1RST_Pos (4U)
14240 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
14241 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
14242 #define RCC_APB2RSTR_USART6RST_Pos (5U)
14243 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
14244 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
14245 #define RCC_APB2RSTR_ADCRST_Pos (8U)
14246 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
14247 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
14248 #define RCC_APB2RSTR_SDIORST_Pos (11U)
14249 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
14250 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
14251 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
14252 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
14253 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
14254 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
14255 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
14256 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
14257 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
14258 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
14259 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
14260 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
14261 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
14262 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
14263 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
14264 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
14265 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
14266 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
14267 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
14268 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
14269 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
14270 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
14271 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
14272 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
14273 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
14274 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
14275 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
14276 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
14277 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
14278 #define RCC_APB2RSTR_LTDCRST_Pos (26U)
14279 #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
14280 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
14281 #define RCC_APB2RSTR_DSIRST_Pos (27U)
14282 #define RCC_APB2RSTR_DSIRST_Msk (0x1U << RCC_APB2RSTR_DSIRST_Pos) /*!< 0x08000000 */
14283 #define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
14284
14285 /* Old SPI1RST bit definition, maintained for legacy purpose */
14286 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
14287
14288 /******************** Bit definition for RCC_AHB1ENR register ***************/
14289 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
14290 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
14291 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
14292 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
14293 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
14294 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
14295 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
14296 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
14297 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
14298 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
14299 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
14300 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
14301 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
14302 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
14303 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
14304 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
14305 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
14306 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
14307 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
14308 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
14309 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
14310 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
14311 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
14312 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
14313 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
14314 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
14315 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
14316 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
14317 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
14318 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
14319 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
14320 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
14321 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
14322 #define RCC_AHB1ENR_CRCEN_Pos (12U)
14323 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
14324 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
14325 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
14326 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
14327 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
14328 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
14329 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
14330 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
14331 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
14332 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
14333 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
14334 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
14335 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
14336 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
14337 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
14338 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
14339 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
14340 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
14341 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
14342 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
14343 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
14344 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
14345 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
14346 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
14347 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
14348 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
14349 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
14350 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
14351 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
14352 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
14353 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
14354 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
14355 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
14356 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
14357 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
14358 /******************** Bit definition for RCC_AHB2ENR register ***************/
14359 /*
14360 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14361 */
14362 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
14363
14364 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
14365 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
14366 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
14367 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
14368 #define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
14369 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
14370 #define RCC_AHB2ENR_HASHEN_Pos (5U)
14371 #define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
14372 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
14373 #define RCC_AHB2ENR_RNGEN_Pos (6U)
14374 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
14375 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
14376 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
14377 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
14378 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
14379
14380 /******************** Bit definition for RCC_AHB3ENR register ***************/
14381 /*
14382 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14383 */
14384 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
14385
14386 #define RCC_AHB3ENR_FMCEN_Pos (0U)
14387 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
14388 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
14389 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
14390 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
14391 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
14392
14393 /******************** Bit definition for RCC_APB1ENR register ***************/
14394 #define RCC_APB1ENR_TIM2EN_Pos (0U)
14395 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
14396 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
14397 #define RCC_APB1ENR_TIM3EN_Pos (1U)
14398 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
14399 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
14400 #define RCC_APB1ENR_TIM4EN_Pos (2U)
14401 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
14402 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
14403 #define RCC_APB1ENR_TIM5EN_Pos (3U)
14404 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
14405 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
14406 #define RCC_APB1ENR_TIM6EN_Pos (4U)
14407 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
14408 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
14409 #define RCC_APB1ENR_TIM7EN_Pos (5U)
14410 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
14411 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
14412 #define RCC_APB1ENR_TIM12EN_Pos (6U)
14413 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
14414 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
14415 #define RCC_APB1ENR_TIM13EN_Pos (7U)
14416 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
14417 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
14418 #define RCC_APB1ENR_TIM14EN_Pos (8U)
14419 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
14420 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
14421 #define RCC_APB1ENR_WWDGEN_Pos (11U)
14422 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
14423 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
14424 #define RCC_APB1ENR_SPI2EN_Pos (14U)
14425 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
14426 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
14427 #define RCC_APB1ENR_SPI3EN_Pos (15U)
14428 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
14429 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
14430 #define RCC_APB1ENR_USART2EN_Pos (17U)
14431 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
14432 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
14433 #define RCC_APB1ENR_USART3EN_Pos (18U)
14434 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
14435 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
14436 #define RCC_APB1ENR_UART4EN_Pos (19U)
14437 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
14438 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
14439 #define RCC_APB1ENR_UART5EN_Pos (20U)
14440 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
14441 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
14442 #define RCC_APB1ENR_I2C1EN_Pos (21U)
14443 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
14444 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
14445 #define RCC_APB1ENR_I2C2EN_Pos (22U)
14446 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
14447 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
14448 #define RCC_APB1ENR_I2C3EN_Pos (23U)
14449 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
14450 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
14451 #define RCC_APB1ENR_CAN1EN_Pos (25U)
14452 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
14453 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
14454 #define RCC_APB1ENR_CAN2EN_Pos (26U)
14455 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
14456 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
14457 #define RCC_APB1ENR_PWREN_Pos (28U)
14458 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
14459 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
14460 #define RCC_APB1ENR_DACEN_Pos (29U)
14461 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
14462 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
14463 #define RCC_APB1ENR_UART7EN_Pos (30U)
14464 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
14465 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
14466 #define RCC_APB1ENR_UART8EN_Pos (31U)
14467 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
14468 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
14469
14470 /******************** Bit definition for RCC_APB2ENR register ***************/
14471 #define RCC_APB2ENR_TIM1EN_Pos (0U)
14472 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
14473 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
14474 #define RCC_APB2ENR_TIM8EN_Pos (1U)
14475 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
14476 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
14477 #define RCC_APB2ENR_USART1EN_Pos (4U)
14478 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
14479 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
14480 #define RCC_APB2ENR_USART6EN_Pos (5U)
14481 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
14482 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
14483 #define RCC_APB2ENR_ADC1EN_Pos (8U)
14484 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
14485 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
14486 #define RCC_APB2ENR_ADC2EN_Pos (9U)
14487 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
14488 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
14489 #define RCC_APB2ENR_ADC3EN_Pos (10U)
14490 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
14491 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
14492 #define RCC_APB2ENR_SDIOEN_Pos (11U)
14493 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
14494 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
14495 #define RCC_APB2ENR_SPI1EN_Pos (12U)
14496 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
14497 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
14498 #define RCC_APB2ENR_SPI4EN_Pos (13U)
14499 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
14500 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
14501 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
14502 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
14503 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
14504 #define RCC_APB2ENR_TIM9EN_Pos (16U)
14505 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
14506 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
14507 #define RCC_APB2ENR_TIM10EN_Pos (17U)
14508 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
14509 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
14510 #define RCC_APB2ENR_TIM11EN_Pos (18U)
14511 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
14512 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
14513 #define RCC_APB2ENR_SPI5EN_Pos (20U)
14514 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
14515 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
14516 #define RCC_APB2ENR_SPI6EN_Pos (21U)
14517 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
14518 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
14519 #define RCC_APB2ENR_SAI1EN_Pos (22U)
14520 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
14521 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
14522 #define RCC_APB2ENR_LTDCEN_Pos (26U)
14523 #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
14524 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
14525 #define RCC_APB2ENR_DSIEN_Pos (27U)
14526 #define RCC_APB2ENR_DSIEN_Msk (0x1U << RCC_APB2ENR_DSIEN_Pos) /*!< 0x08000000 */
14527 #define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
14528
14529 /******************** Bit definition for RCC_AHB1LPENR register *************/
14530 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
14531 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
14532 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
14533 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
14534 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
14535 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
14536 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
14537 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
14538 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
14539 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
14540 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
14541 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
14542 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
14543 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
14544 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
14545 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
14546 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
14547 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
14548 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
14549 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
14550 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
14551 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
14552 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
14553 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
14554 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
14555 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
14556 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
14557 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
14558 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
14559 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
14560 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
14561 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
14562 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
14563 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
14564 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
14565 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
14566 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
14567 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
14568 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
14569 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
14570 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
14571 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
14572 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
14573 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
14574 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
14575 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
14576 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
14577 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
14578 #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
14579 #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
14580 #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
14581 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
14582 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
14583 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
14584 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
14585 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
14586 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
14587 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
14588 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
14589 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
14590
14591 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
14592 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
14593 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
14594 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
14595 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
14596 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
14597 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
14598 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
14599 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
14600 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
14601 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
14602 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
14603 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
14604 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
14605 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
14606 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
14607 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
14608 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
14609
14610 /******************** Bit definition for RCC_AHB2LPENR register *************/
14611 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
14612 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
14613 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
14614 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
14615 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
14616 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
14617 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
14618 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
14619 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
14620 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
14621 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
14622 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
14623 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
14624 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
14625 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
14626
14627 /******************** Bit definition for RCC_AHB3LPENR register *************/
14628 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
14629 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
14630 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
14631 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
14632 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
14633 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
14634
14635 /******************** Bit definition for RCC_APB1LPENR register *************/
14636 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
14637 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
14638 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
14639 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
14640 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
14641 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
14642 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
14643 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
14644 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
14645 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
14646 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
14647 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
14648 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
14649 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
14650 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
14651 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
14652 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
14653 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
14654 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
14655 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
14656 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
14657 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
14658 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
14659 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
14660 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
14661 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
14662 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
14663 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
14664 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
14665 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
14666 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
14667 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
14668 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
14669 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
14670 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
14671 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
14672 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
14673 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
14674 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
14675 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
14676 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
14677 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
14678 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
14679 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
14680 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
14681 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
14682 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
14683 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
14684 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
14685 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
14686 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
14687 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
14688 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
14689 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
14690 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
14691 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
14692 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
14693 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
14694 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
14695 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
14696 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
14697 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
14698 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
14699 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
14700 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
14701 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
14702 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
14703 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
14704 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
14705 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
14706 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
14707 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
14708 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
14709 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
14710 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
14711
14712 /******************** Bit definition for RCC_APB2LPENR register *************/
14713 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
14714 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
14715 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
14716 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
14717 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
14718 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
14719 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
14720 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
14721 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
14722 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
14723 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
14724 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
14725 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
14726 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
14727 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
14728 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
14729 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
14730 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
14731 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
14732 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
14733 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
14734 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
14735 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
14736 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
14737 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
14738 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
14739 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
14740 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
14741 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
14742 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
14743 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
14744 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
14745 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
14746 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
14747 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
14748 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
14749 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
14750 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
14751 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
14752 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
14753 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
14754 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
14755 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
14756 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
14757 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
14758 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
14759 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
14760 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
14761 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
14762 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
14763 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
14764 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
14765 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
14766 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
14767 #define RCC_APB2LPENR_DSILPEN_Pos (27U)
14768 #define RCC_APB2LPENR_DSILPEN_Msk (0x1U << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */
14769 #define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
14770
14771 /******************** Bit definition for RCC_BDCR register ******************/
14772 #define RCC_BDCR_LSEON_Pos (0U)
14773 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
14774 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
14775 #define RCC_BDCR_LSERDY_Pos (1U)
14776 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
14777 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
14778 #define RCC_BDCR_LSEBYP_Pos (2U)
14779 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
14780 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
14781 #define RCC_BDCR_LSEMOD_Pos (3U)
14782 #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
14783 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
14784
14785 #define RCC_BDCR_RTCSEL_Pos (8U)
14786 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
14787 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
14788 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
14789 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
14790
14791 #define RCC_BDCR_RTCEN_Pos (15U)
14792 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
14793 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
14794 #define RCC_BDCR_BDRST_Pos (16U)
14795 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
14796 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
14797
14798 /******************** Bit definition for RCC_CSR register *******************/
14799 #define RCC_CSR_LSION_Pos (0U)
14800 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
14801 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
14802 #define RCC_CSR_LSIRDY_Pos (1U)
14803 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
14804 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
14805 #define RCC_CSR_RMVF_Pos (24U)
14806 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
14807 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
14808 #define RCC_CSR_BORRSTF_Pos (25U)
14809 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
14810 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
14811 #define RCC_CSR_PINRSTF_Pos (26U)
14812 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
14813 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
14814 #define RCC_CSR_PORRSTF_Pos (27U)
14815 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
14816 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
14817 #define RCC_CSR_SFTRSTF_Pos (28U)
14818 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
14819 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
14820 #define RCC_CSR_IWDGRSTF_Pos (29U)
14821 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
14822 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
14823 #define RCC_CSR_WWDGRSTF_Pos (30U)
14824 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
14825 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
14826 #define RCC_CSR_LPWRRSTF_Pos (31U)
14827 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
14828 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
14829 /* Legacy defines */
14830 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
14831 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
14832
14833 /******************** Bit definition for RCC_SSCGR register *****************/
14834 #define RCC_SSCGR_MODPER_Pos (0U)
14835 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
14836 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
14837 #define RCC_SSCGR_INCSTEP_Pos (13U)
14838 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
14839 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
14840 #define RCC_SSCGR_SPREADSEL_Pos (30U)
14841 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
14842 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
14843 #define RCC_SSCGR_SSCGEN_Pos (31U)
14844 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
14845 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
14846
14847 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
14848 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
14849 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
14850 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
14851 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
14852 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
14853 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
14854 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
14855 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
14856 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
14857 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
14858 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
14859 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
14860
14861 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
14862 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
14863 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
14864 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
14865 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
14866 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
14867 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
14868 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
14869 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
14870 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
14871 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
14872 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
14873 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
14874
14875 /******************** Bit definition for RCC_PLLSAICFGR register ************/
14876 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
14877 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
14878 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
14879 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
14880 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
14881 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
14882 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
14883 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
14884 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
14885 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
14886 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
14887 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
14888
14889 #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
14890 #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
14891 #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
14892 #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
14893 #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
14894
14895 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
14896 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
14897 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
14898 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
14899 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
14900 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
14901 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
14902
14903 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
14904 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
14905 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
14906 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
14907 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
14908 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
14909
14910 /******************** Bit definition for RCC_DCKCFGR register ***************/
14911 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
14912 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
14913 #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
14914 #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
14915 #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
14916 #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
14917 #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
14918 #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
14919
14920 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
14921 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
14922 #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
14923 #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
14924 #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
14925 #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
14926 #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
14927 #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
14928 #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
14929 #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
14930 #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
14931 #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
14932 #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
14933
14934 #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
14935 #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
14936 #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
14937 #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
14938 #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
14939 #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
14940 #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
14941 #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
14942 #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
14943 #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
14944 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
14945 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
14946 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
14947 #define RCC_DCKCFGR_CK48MSEL_Pos (27U)
14948 #define RCC_DCKCFGR_CK48MSEL_Msk (0x1U << RCC_DCKCFGR_CK48MSEL_Pos) /*!< 0x08000000 */
14949 #define RCC_DCKCFGR_CK48MSEL RCC_DCKCFGR_CK48MSEL_Msk
14950 #define RCC_DCKCFGR_SDIOSEL_Pos (28U)
14951 #define RCC_DCKCFGR_SDIOSEL_Msk (0x1U << RCC_DCKCFGR_SDIOSEL_Pos) /*!< 0x10000000 */
14952 #define RCC_DCKCFGR_SDIOSEL RCC_DCKCFGR_SDIOSEL_Msk
14953 #define RCC_DCKCFGR_DSISEL_Pos (29U)
14954 #define RCC_DCKCFGR_DSISEL_Msk (0x1U << RCC_DCKCFGR_DSISEL_Pos) /*!< 0x20000000 */
14955 #define RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_Msk
14956
14957
14958 /******************************************************************************/
14959 /* */
14960 /* RNG */
14961 /* */
14962 /******************************************************************************/
14963 /******************** Bits definition for RNG_CR register *******************/
14964 #define RNG_CR_RNGEN_Pos (2U)
14965 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
14966 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
14967 #define RNG_CR_IE_Pos (3U)
14968 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
14969 #define RNG_CR_IE RNG_CR_IE_Msk
14970
14971 /******************** Bits definition for RNG_SR register *******************/
14972 #define RNG_SR_DRDY_Pos (0U)
14973 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
14974 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
14975 #define RNG_SR_CECS_Pos (1U)
14976 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
14977 #define RNG_SR_CECS RNG_SR_CECS_Msk
14978 #define RNG_SR_SECS_Pos (2U)
14979 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
14980 #define RNG_SR_SECS RNG_SR_SECS_Msk
14981 #define RNG_SR_CEIS_Pos (5U)
14982 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
14983 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
14984 #define RNG_SR_SEIS_Pos (6U)
14985 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
14986 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
14987
14988 /******************************************************************************/
14989 /* */
14990 /* Real-Time Clock (RTC) */
14991 /* */
14992 /******************************************************************************/
14993 /*
14994 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14995 */
14996 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
14997 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
14998 /******************** Bits definition for RTC_TR register *******************/
14999 #define RTC_TR_PM_Pos (22U)
15000 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
15001 #define RTC_TR_PM RTC_TR_PM_Msk
15002 #define RTC_TR_HT_Pos (20U)
15003 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
15004 #define RTC_TR_HT RTC_TR_HT_Msk
15005 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
15006 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
15007 #define RTC_TR_HU_Pos (16U)
15008 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
15009 #define RTC_TR_HU RTC_TR_HU_Msk
15010 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
15011 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
15012 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
15013 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
15014 #define RTC_TR_MNT_Pos (12U)
15015 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
15016 #define RTC_TR_MNT RTC_TR_MNT_Msk
15017 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
15018 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
15019 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
15020 #define RTC_TR_MNU_Pos (8U)
15021 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
15022 #define RTC_TR_MNU RTC_TR_MNU_Msk
15023 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
15024 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
15025 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
15026 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
15027 #define RTC_TR_ST_Pos (4U)
15028 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
15029 #define RTC_TR_ST RTC_TR_ST_Msk
15030 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
15031 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
15032 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
15033 #define RTC_TR_SU_Pos (0U)
15034 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
15035 #define RTC_TR_SU RTC_TR_SU_Msk
15036 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
15037 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
15038 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
15039 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
15040
15041 /******************** Bits definition for RTC_DR register *******************/
15042 #define RTC_DR_YT_Pos (20U)
15043 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
15044 #define RTC_DR_YT RTC_DR_YT_Msk
15045 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
15046 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
15047 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
15048 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
15049 #define RTC_DR_YU_Pos (16U)
15050 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
15051 #define RTC_DR_YU RTC_DR_YU_Msk
15052 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
15053 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
15054 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
15055 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
15056 #define RTC_DR_WDU_Pos (13U)
15057 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
15058 #define RTC_DR_WDU RTC_DR_WDU_Msk
15059 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
15060 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
15061 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
15062 #define RTC_DR_MT_Pos (12U)
15063 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
15064 #define RTC_DR_MT RTC_DR_MT_Msk
15065 #define RTC_DR_MU_Pos (8U)
15066 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
15067 #define RTC_DR_MU RTC_DR_MU_Msk
15068 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
15069 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
15070 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
15071 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
15072 #define RTC_DR_DT_Pos (4U)
15073 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
15074 #define RTC_DR_DT RTC_DR_DT_Msk
15075 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
15076 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
15077 #define RTC_DR_DU_Pos (0U)
15078 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
15079 #define RTC_DR_DU RTC_DR_DU_Msk
15080 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
15081 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
15082 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
15083 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
15084
15085 /******************** Bits definition for RTC_CR register *******************/
15086 #define RTC_CR_COE_Pos (23U)
15087 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
15088 #define RTC_CR_COE RTC_CR_COE_Msk
15089 #define RTC_CR_OSEL_Pos (21U)
15090 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
15091 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
15092 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
15093 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
15094 #define RTC_CR_POL_Pos (20U)
15095 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
15096 #define RTC_CR_POL RTC_CR_POL_Msk
15097 #define RTC_CR_COSEL_Pos (19U)
15098 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
15099 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
15100 #define RTC_CR_BKP_Pos (18U)
15101 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
15102 #define RTC_CR_BKP RTC_CR_BKP_Msk
15103 #define RTC_CR_SUB1H_Pos (17U)
15104 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
15105 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
15106 #define RTC_CR_ADD1H_Pos (16U)
15107 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
15108 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
15109 #define RTC_CR_TSIE_Pos (15U)
15110 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
15111 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
15112 #define RTC_CR_WUTIE_Pos (14U)
15113 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
15114 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
15115 #define RTC_CR_ALRBIE_Pos (13U)
15116 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
15117 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
15118 #define RTC_CR_ALRAIE_Pos (12U)
15119 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
15120 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
15121 #define RTC_CR_TSE_Pos (11U)
15122 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
15123 #define RTC_CR_TSE RTC_CR_TSE_Msk
15124 #define RTC_CR_WUTE_Pos (10U)
15125 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
15126 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
15127 #define RTC_CR_ALRBE_Pos (9U)
15128 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
15129 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
15130 #define RTC_CR_ALRAE_Pos (8U)
15131 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
15132 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
15133 #define RTC_CR_DCE_Pos (7U)
15134 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
15135 #define RTC_CR_DCE RTC_CR_DCE_Msk
15136 #define RTC_CR_FMT_Pos (6U)
15137 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
15138 #define RTC_CR_FMT RTC_CR_FMT_Msk
15139 #define RTC_CR_BYPSHAD_Pos (5U)
15140 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
15141 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
15142 #define RTC_CR_REFCKON_Pos (4U)
15143 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
15144 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
15145 #define RTC_CR_TSEDGE_Pos (3U)
15146 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
15147 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
15148 #define RTC_CR_WUCKSEL_Pos (0U)
15149 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
15150 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
15151 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
15152 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
15153 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
15154
15155 /* Legacy defines */
15156 #define RTC_CR_BCK RTC_CR_BKP
15157
15158 /******************** Bits definition for RTC_ISR register ******************/
15159 #define RTC_ISR_RECALPF_Pos (16U)
15160 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
15161 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
15162 #define RTC_ISR_TAMP1F_Pos (13U)
15163 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
15164 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
15165 #define RTC_ISR_TAMP2F_Pos (14U)
15166 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
15167 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
15168 #define RTC_ISR_TSOVF_Pos (12U)
15169 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
15170 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
15171 #define RTC_ISR_TSF_Pos (11U)
15172 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
15173 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
15174 #define RTC_ISR_WUTF_Pos (10U)
15175 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
15176 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
15177 #define RTC_ISR_ALRBF_Pos (9U)
15178 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
15179 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
15180 #define RTC_ISR_ALRAF_Pos (8U)
15181 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
15182 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
15183 #define RTC_ISR_INIT_Pos (7U)
15184 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
15185 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
15186 #define RTC_ISR_INITF_Pos (6U)
15187 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
15188 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
15189 #define RTC_ISR_RSF_Pos (5U)
15190 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
15191 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
15192 #define RTC_ISR_INITS_Pos (4U)
15193 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
15194 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
15195 #define RTC_ISR_SHPF_Pos (3U)
15196 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
15197 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
15198 #define RTC_ISR_WUTWF_Pos (2U)
15199 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
15200 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
15201 #define RTC_ISR_ALRBWF_Pos (1U)
15202 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
15203 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
15204 #define RTC_ISR_ALRAWF_Pos (0U)
15205 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
15206 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
15207
15208 /******************** Bits definition for RTC_PRER register *****************/
15209 #define RTC_PRER_PREDIV_A_Pos (16U)
15210 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
15211 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
15212 #define RTC_PRER_PREDIV_S_Pos (0U)
15213 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
15214 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
15215
15216 /******************** Bits definition for RTC_WUTR register *****************/
15217 #define RTC_WUTR_WUT_Pos (0U)
15218 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
15219 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
15220
15221 /******************** Bits definition for RTC_CALIBR register ***************/
15222 #define RTC_CALIBR_DCS_Pos (7U)
15223 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
15224 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
15225 #define RTC_CALIBR_DC_Pos (0U)
15226 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
15227 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
15228
15229 /******************** Bits definition for RTC_ALRMAR register ***************/
15230 #define RTC_ALRMAR_MSK4_Pos (31U)
15231 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
15232 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
15233 #define RTC_ALRMAR_WDSEL_Pos (30U)
15234 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
15235 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
15236 #define RTC_ALRMAR_DT_Pos (28U)
15237 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
15238 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
15239 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
15240 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
15241 #define RTC_ALRMAR_DU_Pos (24U)
15242 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
15243 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
15244 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
15245 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
15246 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
15247 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
15248 #define RTC_ALRMAR_MSK3_Pos (23U)
15249 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
15250 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
15251 #define RTC_ALRMAR_PM_Pos (22U)
15252 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
15253 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
15254 #define RTC_ALRMAR_HT_Pos (20U)
15255 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
15256 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
15257 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
15258 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
15259 #define RTC_ALRMAR_HU_Pos (16U)
15260 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
15261 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
15262 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
15263 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
15264 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
15265 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
15266 #define RTC_ALRMAR_MSK2_Pos (15U)
15267 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
15268 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
15269 #define RTC_ALRMAR_MNT_Pos (12U)
15270 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
15271 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
15272 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
15273 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
15274 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
15275 #define RTC_ALRMAR_MNU_Pos (8U)
15276 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
15277 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
15278 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
15279 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
15280 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
15281 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
15282 #define RTC_ALRMAR_MSK1_Pos (7U)
15283 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
15284 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
15285 #define RTC_ALRMAR_ST_Pos (4U)
15286 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
15287 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
15288 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
15289 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
15290 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
15291 #define RTC_ALRMAR_SU_Pos (0U)
15292 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
15293 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
15294 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
15295 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
15296 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
15297 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
15298
15299 /******************** Bits definition for RTC_ALRMBR register ***************/
15300 #define RTC_ALRMBR_MSK4_Pos (31U)
15301 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
15302 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
15303 #define RTC_ALRMBR_WDSEL_Pos (30U)
15304 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
15305 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
15306 #define RTC_ALRMBR_DT_Pos (28U)
15307 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
15308 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
15309 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
15310 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
15311 #define RTC_ALRMBR_DU_Pos (24U)
15312 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
15313 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
15314 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
15315 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
15316 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
15317 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
15318 #define RTC_ALRMBR_MSK3_Pos (23U)
15319 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
15320 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
15321 #define RTC_ALRMBR_PM_Pos (22U)
15322 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
15323 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
15324 #define RTC_ALRMBR_HT_Pos (20U)
15325 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
15326 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
15327 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
15328 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
15329 #define RTC_ALRMBR_HU_Pos (16U)
15330 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
15331 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
15332 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
15333 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
15334 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
15335 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
15336 #define RTC_ALRMBR_MSK2_Pos (15U)
15337 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
15338 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
15339 #define RTC_ALRMBR_MNT_Pos (12U)
15340 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
15341 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
15342 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
15343 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
15344 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
15345 #define RTC_ALRMBR_MNU_Pos (8U)
15346 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
15347 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
15348 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
15349 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
15350 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
15351 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
15352 #define RTC_ALRMBR_MSK1_Pos (7U)
15353 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
15354 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
15355 #define RTC_ALRMBR_ST_Pos (4U)
15356 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
15357 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
15358 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
15359 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
15360 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
15361 #define RTC_ALRMBR_SU_Pos (0U)
15362 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
15363 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
15364 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
15365 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
15366 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
15367 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
15368
15369 /******************** Bits definition for RTC_WPR register ******************/
15370 #define RTC_WPR_KEY_Pos (0U)
15371 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
15372 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
15373
15374 /******************** Bits definition for RTC_SSR register ******************/
15375 #define RTC_SSR_SS_Pos (0U)
15376 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
15377 #define RTC_SSR_SS RTC_SSR_SS_Msk
15378
15379 /******************** Bits definition for RTC_SHIFTR register ***************/
15380 #define RTC_SHIFTR_SUBFS_Pos (0U)
15381 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
15382 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
15383 #define RTC_SHIFTR_ADD1S_Pos (31U)
15384 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
15385 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
15386
15387 /******************** Bits definition for RTC_TSTR register *****************/
15388 #define RTC_TSTR_PM_Pos (22U)
15389 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
15390 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
15391 #define RTC_TSTR_HT_Pos (20U)
15392 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
15393 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
15394 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
15395 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
15396 #define RTC_TSTR_HU_Pos (16U)
15397 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
15398 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
15399 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
15400 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
15401 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
15402 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
15403 #define RTC_TSTR_MNT_Pos (12U)
15404 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
15405 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
15406 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
15407 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
15408 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
15409 #define RTC_TSTR_MNU_Pos (8U)
15410 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
15411 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
15412 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
15413 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
15414 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
15415 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
15416 #define RTC_TSTR_ST_Pos (4U)
15417 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
15418 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
15419 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
15420 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
15421 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
15422 #define RTC_TSTR_SU_Pos (0U)
15423 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
15424 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
15425 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
15426 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
15427 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
15428 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
15429
15430 /******************** Bits definition for RTC_TSDR register *****************/
15431 #define RTC_TSDR_WDU_Pos (13U)
15432 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
15433 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
15434 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
15435 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
15436 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
15437 #define RTC_TSDR_MT_Pos (12U)
15438 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
15439 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
15440 #define RTC_TSDR_MU_Pos (8U)
15441 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
15442 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
15443 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
15444 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
15445 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
15446 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
15447 #define RTC_TSDR_DT_Pos (4U)
15448 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
15449 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
15450 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
15451 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
15452 #define RTC_TSDR_DU_Pos (0U)
15453 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
15454 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
15455 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
15456 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
15457 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
15458 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
15459
15460 /******************** Bits definition for RTC_TSSSR register ****************/
15461 #define RTC_TSSSR_SS_Pos (0U)
15462 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
15463 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
15464
15465 /******************** Bits definition for RTC_CAL register *****************/
15466 #define RTC_CALR_CALP_Pos (15U)
15467 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
15468 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
15469 #define RTC_CALR_CALW8_Pos (14U)
15470 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
15471 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
15472 #define RTC_CALR_CALW16_Pos (13U)
15473 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
15474 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
15475 #define RTC_CALR_CALM_Pos (0U)
15476 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
15477 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
15478 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
15479 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
15480 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
15481 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
15482 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
15483 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
15484 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
15485 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
15486 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
15487
15488 /******************** Bits definition for RTC_TAFCR register ****************/
15489 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
15490 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
15491 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
15492 #define RTC_TAFCR_TSINSEL_Pos (17U)
15493 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
15494 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
15495 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
15496 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
15497 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
15498 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
15499 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
15500 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
15501 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
15502 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
15503 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
15504 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
15505 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
15506 #define RTC_TAFCR_TAMPFLT_Pos (11U)
15507 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
15508 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
15509 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
15510 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
15511 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
15512 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
15513 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
15514 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
15515 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
15516 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
15517 #define RTC_TAFCR_TAMPTS_Pos (7U)
15518 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
15519 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
15520 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
15521 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
15522 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
15523 #define RTC_TAFCR_TAMP2E_Pos (3U)
15524 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
15525 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
15526 #define RTC_TAFCR_TAMPIE_Pos (2U)
15527 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
15528 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
15529 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
15530 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
15531 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
15532 #define RTC_TAFCR_TAMP1E_Pos (0U)
15533 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
15534 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
15535
15536 /* Legacy defines */
15537 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
15538
15539 /******************** Bits definition for RTC_ALRMASSR register *************/
15540 #define RTC_ALRMASSR_MASKSS_Pos (24U)
15541 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
15542 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
15543 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
15544 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
15545 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
15546 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
15547 #define RTC_ALRMASSR_SS_Pos (0U)
15548 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
15549 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
15550
15551 /******************** Bits definition for RTC_ALRMBSSR register *************/
15552 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
15553 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
15554 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
15555 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
15556 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
15557 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
15558 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
15559 #define RTC_ALRMBSSR_SS_Pos (0U)
15560 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
15561 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
15562
15563 /******************** Bits definition for RTC_BKP0R register ****************/
15564 #define RTC_BKP0R_Pos (0U)
15565 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
15566 #define RTC_BKP0R RTC_BKP0R_Msk
15567
15568 /******************** Bits definition for RTC_BKP1R register ****************/
15569 #define RTC_BKP1R_Pos (0U)
15570 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
15571 #define RTC_BKP1R RTC_BKP1R_Msk
15572
15573 /******************** Bits definition for RTC_BKP2R register ****************/
15574 #define RTC_BKP2R_Pos (0U)
15575 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
15576 #define RTC_BKP2R RTC_BKP2R_Msk
15577
15578 /******************** Bits definition for RTC_BKP3R register ****************/
15579 #define RTC_BKP3R_Pos (0U)
15580 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
15581 #define RTC_BKP3R RTC_BKP3R_Msk
15582
15583 /******************** Bits definition for RTC_BKP4R register ****************/
15584 #define RTC_BKP4R_Pos (0U)
15585 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
15586 #define RTC_BKP4R RTC_BKP4R_Msk
15587
15588 /******************** Bits definition for RTC_BKP5R register ****************/
15589 #define RTC_BKP5R_Pos (0U)
15590 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
15591 #define RTC_BKP5R RTC_BKP5R_Msk
15592
15593 /******************** Bits definition for RTC_BKP6R register ****************/
15594 #define RTC_BKP6R_Pos (0U)
15595 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
15596 #define RTC_BKP6R RTC_BKP6R_Msk
15597
15598 /******************** Bits definition for RTC_BKP7R register ****************/
15599 #define RTC_BKP7R_Pos (0U)
15600 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
15601 #define RTC_BKP7R RTC_BKP7R_Msk
15602
15603 /******************** Bits definition for RTC_BKP8R register ****************/
15604 #define RTC_BKP8R_Pos (0U)
15605 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
15606 #define RTC_BKP8R RTC_BKP8R_Msk
15607
15608 /******************** Bits definition for RTC_BKP9R register ****************/
15609 #define RTC_BKP9R_Pos (0U)
15610 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
15611 #define RTC_BKP9R RTC_BKP9R_Msk
15612
15613 /******************** Bits definition for RTC_BKP10R register ***************/
15614 #define RTC_BKP10R_Pos (0U)
15615 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
15616 #define RTC_BKP10R RTC_BKP10R_Msk
15617
15618 /******************** Bits definition for RTC_BKP11R register ***************/
15619 #define RTC_BKP11R_Pos (0U)
15620 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
15621 #define RTC_BKP11R RTC_BKP11R_Msk
15622
15623 /******************** Bits definition for RTC_BKP12R register ***************/
15624 #define RTC_BKP12R_Pos (0U)
15625 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
15626 #define RTC_BKP12R RTC_BKP12R_Msk
15627
15628 /******************** Bits definition for RTC_BKP13R register ***************/
15629 #define RTC_BKP13R_Pos (0U)
15630 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
15631 #define RTC_BKP13R RTC_BKP13R_Msk
15632
15633 /******************** Bits definition for RTC_BKP14R register ***************/
15634 #define RTC_BKP14R_Pos (0U)
15635 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
15636 #define RTC_BKP14R RTC_BKP14R_Msk
15637
15638 /******************** Bits definition for RTC_BKP15R register ***************/
15639 #define RTC_BKP15R_Pos (0U)
15640 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
15641 #define RTC_BKP15R RTC_BKP15R_Msk
15642
15643 /******************** Bits definition for RTC_BKP16R register ***************/
15644 #define RTC_BKP16R_Pos (0U)
15645 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
15646 #define RTC_BKP16R RTC_BKP16R_Msk
15647
15648 /******************** Bits definition for RTC_BKP17R register ***************/
15649 #define RTC_BKP17R_Pos (0U)
15650 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
15651 #define RTC_BKP17R RTC_BKP17R_Msk
15652
15653 /******************** Bits definition for RTC_BKP18R register ***************/
15654 #define RTC_BKP18R_Pos (0U)
15655 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
15656 #define RTC_BKP18R RTC_BKP18R_Msk
15657
15658 /******************** Bits definition for RTC_BKP19R register ***************/
15659 #define RTC_BKP19R_Pos (0U)
15660 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
15661 #define RTC_BKP19R RTC_BKP19R_Msk
15662
15663 /******************** Number of backup registers ******************************/
15664 #define RTC_BKP_NUMBER 0x000000014U
15665
15666 /******************************************************************************/
15667 /* */
15668 /* Serial Audio Interface */
15669 /* */
15670 /******************************************************************************/
15671 /******************** Bit definition for SAI_GCR register *******************/
15672 #define SAI_GCR_SYNCIN_Pos (0U)
15673 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
15674 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
15675 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
15676 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
15677
15678 #define SAI_GCR_SYNCOUT_Pos (4U)
15679 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
15680 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
15681 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
15682 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
15683
15684 /******************* Bit definition for SAI_xCR1 register *******************/
15685 #define SAI_xCR1_MODE_Pos (0U)
15686 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
15687 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
15688 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
15689 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
15690
15691 #define SAI_xCR1_PRTCFG_Pos (2U)
15692 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
15693 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
15694 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
15695 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
15696
15697 #define SAI_xCR1_DS_Pos (5U)
15698 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
15699 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
15700 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
15701 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
15702 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
15703
15704 #define SAI_xCR1_LSBFIRST_Pos (8U)
15705 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
15706 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
15707 #define SAI_xCR1_CKSTR_Pos (9U)
15708 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
15709 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
15710
15711 #define SAI_xCR1_SYNCEN_Pos (10U)
15712 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
15713 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
15714 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
15715 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
15716
15717 #define SAI_xCR1_MONO_Pos (12U)
15718 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
15719 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
15720 #define SAI_xCR1_OUTDRIV_Pos (13U)
15721 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
15722 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
15723 #define SAI_xCR1_SAIEN_Pos (16U)
15724 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
15725 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
15726 #define SAI_xCR1_DMAEN_Pos (17U)
15727 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
15728 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
15729 #define SAI_xCR1_NODIV_Pos (19U)
15730 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
15731 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
15732
15733 #define SAI_xCR1_MCKDIV_Pos (20U)
15734 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
15735 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
15736 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
15737 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
15738 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
15739 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
15740
15741 /******************* Bit definition for SAI_xCR2 register *******************/
15742 #define SAI_xCR2_FTH_Pos (0U)
15743 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
15744 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
15745 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
15746 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
15747 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
15748
15749 #define SAI_xCR2_FFLUSH_Pos (3U)
15750 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
15751 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
15752 #define SAI_xCR2_TRIS_Pos (4U)
15753 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
15754 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
15755 #define SAI_xCR2_MUTE_Pos (5U)
15756 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
15757 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
15758 #define SAI_xCR2_MUTEVAL_Pos (6U)
15759 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
15760 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
15761
15762 #define SAI_xCR2_MUTECNT_Pos (7U)
15763 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
15764 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
15765 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
15766 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
15767 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
15768 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
15769 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
15770 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
15771
15772 #define SAI_xCR2_CPL_Pos (13U)
15773 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
15774 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
15775
15776 #define SAI_xCR2_COMP_Pos (14U)
15777 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
15778 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
15779 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
15780 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
15781
15782 /****************** Bit definition for SAI_xFRCR register *******************/
15783 #define SAI_xFRCR_FRL_Pos (0U)
15784 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
15785 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
15786 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
15787 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
15788 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
15789 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
15790 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
15791 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
15792 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
15793 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
15794
15795 #define SAI_xFRCR_FSALL_Pos (8U)
15796 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
15797 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
15798 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
15799 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
15800 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
15801 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
15802 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
15803 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
15804 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
15805
15806 #define SAI_xFRCR_FSDEF_Pos (16U)
15807 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
15808 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
15809 #define SAI_xFRCR_FSPOL_Pos (17U)
15810 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
15811 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
15812 #define SAI_xFRCR_FSOFF_Pos (18U)
15813 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
15814 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
15815 /* Legacy defines */
15816 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
15817
15818 /****************** Bit definition for SAI_xSLOTR register *******************/
15819 #define SAI_xSLOTR_FBOFF_Pos (0U)
15820 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
15821 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
15822 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
15823 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
15824 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
15825 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
15826 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
15827
15828 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
15829 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
15830 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
15831 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
15832 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
15833
15834 #define SAI_xSLOTR_NBSLOT_Pos (8U)
15835 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
15836 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
15837 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
15838 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
15839 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
15840 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
15841
15842 #define SAI_xSLOTR_SLOTEN_Pos (16U)
15843 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
15844 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
15845
15846 /******************* Bit definition for SAI_xIMR register *******************/
15847 #define SAI_xIMR_OVRUDRIE_Pos (0U)
15848 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
15849 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
15850 #define SAI_xIMR_MUTEDETIE_Pos (1U)
15851 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
15852 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
15853 #define SAI_xIMR_WCKCFGIE_Pos (2U)
15854 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
15855 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
15856 #define SAI_xIMR_FREQIE_Pos (3U)
15857 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
15858 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
15859 #define SAI_xIMR_CNRDYIE_Pos (4U)
15860 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
15861 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
15862 #define SAI_xIMR_AFSDETIE_Pos (5U)
15863 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
15864 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
15865 #define SAI_xIMR_LFSDETIE_Pos (6U)
15866 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
15867 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
15868
15869 /******************** Bit definition for SAI_xSR register *******************/
15870 #define SAI_xSR_OVRUDR_Pos (0U)
15871 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
15872 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
15873 #define SAI_xSR_MUTEDET_Pos (1U)
15874 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
15875 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
15876 #define SAI_xSR_WCKCFG_Pos (2U)
15877 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
15878 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
15879 #define SAI_xSR_FREQ_Pos (3U)
15880 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
15881 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
15882 #define SAI_xSR_CNRDY_Pos (4U)
15883 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
15884 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
15885 #define SAI_xSR_AFSDET_Pos (5U)
15886 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
15887 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
15888 #define SAI_xSR_LFSDET_Pos (6U)
15889 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
15890 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
15891
15892 #define SAI_xSR_FLVL_Pos (16U)
15893 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
15894 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
15895 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
15896 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
15897 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
15898
15899 /****************** Bit definition for SAI_xCLRFR register ******************/
15900 #define SAI_xCLRFR_COVRUDR_Pos (0U)
15901 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
15902 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
15903 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
15904 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
15905 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
15906 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
15907 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
15908 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
15909 #define SAI_xCLRFR_CFREQ_Pos (3U)
15910 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
15911 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
15912 #define SAI_xCLRFR_CCNRDY_Pos (4U)
15913 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
15914 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
15915 #define SAI_xCLRFR_CAFSDET_Pos (5U)
15916 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
15917 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
15918 #define SAI_xCLRFR_CLFSDET_Pos (6U)
15919 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
15920 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
15921
15922 /****************** Bit definition for SAI_xDR register ******************/
15923 #define SAI_xDR_DATA_Pos (0U)
15924 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
15925 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
15926
15927
15928 /******************************************************************************/
15929 /* */
15930 /* SD host Interface */
15931 /* */
15932 /******************************************************************************/
15933 /****************** Bit definition for SDIO_POWER register ******************/
15934 #define SDIO_POWER_PWRCTRL_Pos (0U)
15935 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
15936 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
15937 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
15938 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
15939
15940 /****************** Bit definition for SDIO_CLKCR register ******************/
15941 #define SDIO_CLKCR_CLKDIV_Pos (0U)
15942 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
15943 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
15944 #define SDIO_CLKCR_CLKEN_Pos (8U)
15945 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
15946 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
15947 #define SDIO_CLKCR_PWRSAV_Pos (9U)
15948 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
15949 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
15950 #define SDIO_CLKCR_BYPASS_Pos (10U)
15951 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
15952 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
15953
15954 #define SDIO_CLKCR_WIDBUS_Pos (11U)
15955 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
15956 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
15957 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
15958 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
15959
15960 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
15961 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
15962 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
15963 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
15964 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
15965 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
15966
15967 /******************* Bit definition for SDIO_ARG register *******************/
15968 #define SDIO_ARG_CMDARG_Pos (0U)
15969 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
15970 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
15971
15972 /******************* Bit definition for SDIO_CMD register *******************/
15973 #define SDIO_CMD_CMDINDEX_Pos (0U)
15974 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
15975 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
15976
15977 #define SDIO_CMD_WAITRESP_Pos (6U)
15978 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
15979 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
15980 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
15981 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
15982
15983 #define SDIO_CMD_WAITINT_Pos (8U)
15984 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
15985 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
15986 #define SDIO_CMD_WAITPEND_Pos (9U)
15987 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
15988 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
15989 #define SDIO_CMD_CPSMEN_Pos (10U)
15990 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
15991 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
15992 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
15993 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
15994 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
15995
15996 /***************** Bit definition for SDIO_RESPCMD register *****************/
15997 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
15998 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
15999 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
16000
16001 /****************** Bit definition for SDIO_RESP0 register ******************/
16002 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
16003 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
16004 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
16005
16006 /****************** Bit definition for SDIO_RESP1 register ******************/
16007 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
16008 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
16009 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
16010
16011 /****************** Bit definition for SDIO_RESP2 register ******************/
16012 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
16013 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
16014 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
16015
16016 /****************** Bit definition for SDIO_RESP3 register ******************/
16017 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
16018 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
16019 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
16020
16021 /****************** Bit definition for SDIO_RESP4 register ******************/
16022 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
16023 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
16024 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
16025
16026 /****************** Bit definition for SDIO_DTIMER register *****************/
16027 #define SDIO_DTIMER_DATATIME_Pos (0U)
16028 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
16029 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
16030
16031 /****************** Bit definition for SDIO_DLEN register *******************/
16032 #define SDIO_DLEN_DATALENGTH_Pos (0U)
16033 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
16034 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
16035
16036 /****************** Bit definition for SDIO_DCTRL register ******************/
16037 #define SDIO_DCTRL_DTEN_Pos (0U)
16038 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
16039 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
16040 #define SDIO_DCTRL_DTDIR_Pos (1U)
16041 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
16042 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
16043 #define SDIO_DCTRL_DTMODE_Pos (2U)
16044 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
16045 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
16046 #define SDIO_DCTRL_DMAEN_Pos (3U)
16047 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
16048 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
16049
16050 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
16051 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
16052 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
16053 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
16054 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
16055 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
16056 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
16057
16058 #define SDIO_DCTRL_RWSTART_Pos (8U)
16059 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
16060 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
16061 #define SDIO_DCTRL_RWSTOP_Pos (9U)
16062 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
16063 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
16064 #define SDIO_DCTRL_RWMOD_Pos (10U)
16065 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
16066 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
16067 #define SDIO_DCTRL_SDIOEN_Pos (11U)
16068 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
16069 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
16070
16071 /****************** Bit definition for SDIO_DCOUNT register *****************/
16072 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
16073 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
16074 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
16075
16076 /****************** Bit definition for SDIO_STA register ********************/
16077 #define SDIO_STA_CCRCFAIL_Pos (0U)
16078 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
16079 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
16080 #define SDIO_STA_DCRCFAIL_Pos (1U)
16081 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
16082 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
16083 #define SDIO_STA_CTIMEOUT_Pos (2U)
16084 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
16085 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
16086 #define SDIO_STA_DTIMEOUT_Pos (3U)
16087 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
16088 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
16089 #define SDIO_STA_TXUNDERR_Pos (4U)
16090 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
16091 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
16092 #define SDIO_STA_RXOVERR_Pos (5U)
16093 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
16094 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
16095 #define SDIO_STA_CMDREND_Pos (6U)
16096 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
16097 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
16098 #define SDIO_STA_CMDSENT_Pos (7U)
16099 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
16100 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
16101 #define SDIO_STA_DATAEND_Pos (8U)
16102 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
16103 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
16104 #define SDIO_STA_DBCKEND_Pos (10U)
16105 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
16106 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
16107 #define SDIO_STA_CMDACT_Pos (11U)
16108 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
16109 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
16110 #define SDIO_STA_TXACT_Pos (12U)
16111 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
16112 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
16113 #define SDIO_STA_RXACT_Pos (13U)
16114 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
16115 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
16116 #define SDIO_STA_TXFIFOHE_Pos (14U)
16117 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
16118 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
16119 #define SDIO_STA_RXFIFOHF_Pos (15U)
16120 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
16121 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
16122 #define SDIO_STA_TXFIFOF_Pos (16U)
16123 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
16124 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
16125 #define SDIO_STA_RXFIFOF_Pos (17U)
16126 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
16127 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
16128 #define SDIO_STA_TXFIFOE_Pos (18U)
16129 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
16130 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
16131 #define SDIO_STA_RXFIFOE_Pos (19U)
16132 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
16133 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
16134 #define SDIO_STA_TXDAVL_Pos (20U)
16135 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
16136 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
16137 #define SDIO_STA_RXDAVL_Pos (21U)
16138 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
16139 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
16140 #define SDIO_STA_SDIOIT_Pos (22U)
16141 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
16142 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
16143
16144 /******************* Bit definition for SDIO_ICR register *******************/
16145 #define SDIO_ICR_CCRCFAILC_Pos (0U)
16146 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
16147 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
16148 #define SDIO_ICR_DCRCFAILC_Pos (1U)
16149 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
16150 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
16151 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
16152 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
16153 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
16154 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
16155 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
16156 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
16157 #define SDIO_ICR_TXUNDERRC_Pos (4U)
16158 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
16159 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
16160 #define SDIO_ICR_RXOVERRC_Pos (5U)
16161 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
16162 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
16163 #define SDIO_ICR_CMDRENDC_Pos (6U)
16164 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
16165 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
16166 #define SDIO_ICR_CMDSENTC_Pos (7U)
16167 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
16168 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
16169 #define SDIO_ICR_DATAENDC_Pos (8U)
16170 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
16171 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
16172 #define SDIO_ICR_DBCKENDC_Pos (10U)
16173 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
16174 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
16175 #define SDIO_ICR_SDIOITC_Pos (22U)
16176 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
16177 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
16178
16179 /****************** Bit definition for SDIO_MASK register *******************/
16180 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
16181 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
16182 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
16183 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
16184 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
16185 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
16186 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
16187 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
16188 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
16189 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
16190 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
16191 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
16192 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
16193 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
16194 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
16195 #define SDIO_MASK_RXOVERRIE_Pos (5U)
16196 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
16197 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
16198 #define SDIO_MASK_CMDRENDIE_Pos (6U)
16199 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
16200 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
16201 #define SDIO_MASK_CMDSENTIE_Pos (7U)
16202 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
16203 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
16204 #define SDIO_MASK_DATAENDIE_Pos (8U)
16205 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
16206 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
16207 #define SDIO_MASK_DBCKENDIE_Pos (10U)
16208 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
16209 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
16210 #define SDIO_MASK_CMDACTIE_Pos (11U)
16211 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
16212 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
16213 #define SDIO_MASK_TXACTIE_Pos (12U)
16214 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
16215 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
16216 #define SDIO_MASK_RXACTIE_Pos (13U)
16217 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
16218 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
16219 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
16220 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
16221 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
16222 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
16223 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
16224 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
16225 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
16226 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
16227 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
16228 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
16229 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
16230 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
16231 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
16232 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
16233 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
16234 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
16235 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
16236 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
16237 #define SDIO_MASK_TXDAVLIE_Pos (20U)
16238 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
16239 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
16240 #define SDIO_MASK_RXDAVLIE_Pos (21U)
16241 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
16242 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
16243 #define SDIO_MASK_SDIOITIE_Pos (22U)
16244 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
16245 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
16246
16247 /***************** Bit definition for SDIO_FIFOCNT register *****************/
16248 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
16249 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
16250 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
16251
16252 /****************** Bit definition for SDIO_FIFO register *******************/
16253 #define SDIO_FIFO_FIFODATA_Pos (0U)
16254 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
16255 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
16256
16257 /******************************************************************************/
16258 /* */
16259 /* Serial Peripheral Interface */
16260 /* */
16261 /******************************************************************************/
16262 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
16263
16264 /******************* Bit definition for SPI_CR1 register ********************/
16265 #define SPI_CR1_CPHA_Pos (0U)
16266 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
16267 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
16268 #define SPI_CR1_CPOL_Pos (1U)
16269 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
16270 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
16271 #define SPI_CR1_MSTR_Pos (2U)
16272 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
16273 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
16274
16275 #define SPI_CR1_BR_Pos (3U)
16276 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
16277 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
16278 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
16279 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
16280 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
16281
16282 #define SPI_CR1_SPE_Pos (6U)
16283 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
16284 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
16285 #define SPI_CR1_LSBFIRST_Pos (7U)
16286 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
16287 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
16288 #define SPI_CR1_SSI_Pos (8U)
16289 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
16290 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
16291 #define SPI_CR1_SSM_Pos (9U)
16292 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
16293 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
16294 #define SPI_CR1_RXONLY_Pos (10U)
16295 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
16296 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
16297 #define SPI_CR1_DFF_Pos (11U)
16298 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
16299 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
16300 #define SPI_CR1_CRCNEXT_Pos (12U)
16301 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
16302 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
16303 #define SPI_CR1_CRCEN_Pos (13U)
16304 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
16305 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
16306 #define SPI_CR1_BIDIOE_Pos (14U)
16307 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
16308 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
16309 #define SPI_CR1_BIDIMODE_Pos (15U)
16310 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
16311 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
16312
16313 /******************* Bit definition for SPI_CR2 register ********************/
16314 #define SPI_CR2_RXDMAEN_Pos (0U)
16315 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
16316 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
16317 #define SPI_CR2_TXDMAEN_Pos (1U)
16318 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
16319 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
16320 #define SPI_CR2_SSOE_Pos (2U)
16321 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
16322 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
16323 #define SPI_CR2_FRF_Pos (4U)
16324 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
16325 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
16326 #define SPI_CR2_ERRIE_Pos (5U)
16327 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
16328 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
16329 #define SPI_CR2_RXNEIE_Pos (6U)
16330 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
16331 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
16332 #define SPI_CR2_TXEIE_Pos (7U)
16333 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
16334 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
16335
16336 /******************** Bit definition for SPI_SR register ********************/
16337 #define SPI_SR_RXNE_Pos (0U)
16338 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
16339 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
16340 #define SPI_SR_TXE_Pos (1U)
16341 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
16342 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
16343 #define SPI_SR_CHSIDE_Pos (2U)
16344 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
16345 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
16346 #define SPI_SR_UDR_Pos (3U)
16347 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
16348 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
16349 #define SPI_SR_CRCERR_Pos (4U)
16350 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
16351 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
16352 #define SPI_SR_MODF_Pos (5U)
16353 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
16354 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
16355 #define SPI_SR_OVR_Pos (6U)
16356 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
16357 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
16358 #define SPI_SR_BSY_Pos (7U)
16359 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
16360 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
16361 #define SPI_SR_FRE_Pos (8U)
16362 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
16363 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
16364
16365 /******************** Bit definition for SPI_DR register ********************/
16366 #define SPI_DR_DR_Pos (0U)
16367 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
16368 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
16369
16370 /******************* Bit definition for SPI_CRCPR register ******************/
16371 #define SPI_CRCPR_CRCPOLY_Pos (0U)
16372 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
16373 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
16374
16375 /****************** Bit definition for SPI_RXCRCR register ******************/
16376 #define SPI_RXCRCR_RXCRC_Pos (0U)
16377 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
16378 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
16379
16380 /****************** Bit definition for SPI_TXCRCR register ******************/
16381 #define SPI_TXCRCR_TXCRC_Pos (0U)
16382 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
16383 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
16384
16385 /****************** Bit definition for SPI_I2SCFGR register *****************/
16386 #define SPI_I2SCFGR_CHLEN_Pos (0U)
16387 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
16388 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
16389
16390 #define SPI_I2SCFGR_DATLEN_Pos (1U)
16391 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
16392 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
16393 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
16394 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
16395
16396 #define SPI_I2SCFGR_CKPOL_Pos (3U)
16397 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
16398 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
16399
16400 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
16401 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
16402 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
16403 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
16404 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
16405
16406 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
16407 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
16408 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
16409
16410 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
16411 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
16412 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
16413 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
16414 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
16415
16416 #define SPI_I2SCFGR_I2SE_Pos (10U)
16417 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
16418 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
16419 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
16420 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
16421 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
16422 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
16423 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
16424 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
16425
16426 /****************** Bit definition for SPI_I2SPR register *******************/
16427 #define SPI_I2SPR_I2SDIV_Pos (0U)
16428 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
16429 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
16430 #define SPI_I2SPR_ODD_Pos (8U)
16431 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
16432 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
16433 #define SPI_I2SPR_MCKOE_Pos (9U)
16434 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
16435 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
16436
16437 /******************************************************************************/
16438 /* */
16439 /* SYSCFG */
16440 /* */
16441 /******************************************************************************/
16442 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
16443 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
16444 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
16445 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
16446 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
16447 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
16448 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
16449 #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
16450 #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
16451 #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
16452 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
16453 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
16454 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
16455 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
16456 /* Legacy Defines */
16457 #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
16458 /****************** Bit definition for SYSCFG_PMC register ******************/
16459 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
16460 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
16461 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
16462 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
16463 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
16464 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
16465 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
16466 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
16467 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
16468 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
16469 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
16470 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
16471 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
16472 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
16473 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
16474
16475 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
16476 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
16477 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
16478 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
16479 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
16480 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
16481 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
16482 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
16483 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
16484 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
16485 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
16486 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
16487 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
16488 /**
16489 * @brief EXTI0 configuration
16490 */
16491 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
16492 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
16493 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
16494 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
16495 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
16496 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
16497 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
16498 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
16499 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
16500 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
16501 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
16502
16503 /**
16504 * @brief EXTI1 configuration
16505 */
16506 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
16507 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
16508 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
16509 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
16510 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
16511 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
16512 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
16513 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
16514 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
16515 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
16516 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
16517
16518 /**
16519 * @brief EXTI2 configuration
16520 */
16521 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
16522 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
16523 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
16524 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
16525 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
16526 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
16527 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
16528 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
16529 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
16530 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
16531 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
16532
16533 /**
16534 * @brief EXTI3 configuration
16535 */
16536 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
16537 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
16538 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
16539 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
16540 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
16541 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
16542 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
16543 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
16544 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
16545 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
16546 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
16547
16548 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
16549 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
16550 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
16551 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
16552 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
16553 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
16554 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
16555 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
16556 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
16557 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
16558 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
16559 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
16560 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
16561
16562 /**
16563 * @brief EXTI4 configuration
16564 */
16565 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
16566 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
16567 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
16568 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
16569 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
16570 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
16571 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
16572 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
16573 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
16574 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
16575 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
16576
16577 /**
16578 * @brief EXTI5 configuration
16579 */
16580 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
16581 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
16582 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
16583 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
16584 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
16585 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
16586 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
16587 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
16588 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
16589 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
16590 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
16591
16592 /**
16593 * @brief EXTI6 configuration
16594 */
16595 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
16596 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
16597 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
16598 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
16599 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
16600 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
16601 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
16602 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
16603 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
16604 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
16605 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
16606
16607 /**
16608 * @brief EXTI7 configuration
16609 */
16610 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
16611 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
16612 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
16613 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
16614 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
16615 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
16616 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
16617 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
16618 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
16619 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
16620 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
16621
16622 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
16623 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
16624 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
16625 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
16626 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
16627 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
16628 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
16629 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
16630 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
16631 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
16632 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
16633 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
16634 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
16635
16636 /**
16637 * @brief EXTI8 configuration
16638 */
16639 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
16640 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
16641 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
16642 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
16643 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
16644 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
16645 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
16646 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
16647 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
16648 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
16649
16650 /**
16651 * @brief EXTI9 configuration
16652 */
16653 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
16654 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
16655 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
16656 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
16657 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
16658 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
16659 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
16660 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
16661 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
16662 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
16663
16664 /**
16665 * @brief EXTI10 configuration
16666 */
16667 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
16668 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
16669 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
16670 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
16671 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
16672 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
16673 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
16674 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
16675 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
16676 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
16677
16678 /**
16679 * @brief EXTI11 configuration
16680 */
16681 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
16682 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
16683 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
16684 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
16685 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
16686 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
16687 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
16688 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
16689 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
16690 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
16691
16692
16693 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
16694 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
16695 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
16696 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
16697 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
16698 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
16699 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
16700 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
16701 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
16702 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
16703 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
16704 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
16705 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
16706
16707 /**
16708 * @brief EXTI12 configuration
16709 */
16710 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
16711 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
16712 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
16713 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
16714 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
16715 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
16716 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
16717 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
16718 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
16719 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
16720
16721 /**
16722 * @brief EXTI13 configuration
16723 */
16724 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
16725 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
16726 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
16727 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
16728 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
16729 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
16730 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
16731 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
16732 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
16733 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
16734
16735 /**
16736 * @brief EXTI14 configuration
16737 */
16738 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
16739 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
16740 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
16741 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
16742 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
16743 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
16744 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
16745 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
16746 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
16747 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
16748
16749 /**
16750 * @brief EXTI15 configuration
16751 */
16752 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
16753 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
16754 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
16755 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
16756 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
16757 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
16758 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
16759 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
16760 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
16761 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
16762
16763 /****************** Bit definition for SYSCFG_CMPCR register ****************/
16764 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
16765 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
16766 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
16767 #define SYSCFG_CMPCR_READY_Pos (8U)
16768 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
16769 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
16770
16771 /******************************************************************************/
16772 /* */
16773 /* TIM */
16774 /* */
16775 /******************************************************************************/
16776 /******************* Bit definition for TIM_CR1 register ********************/
16777 #define TIM_CR1_CEN_Pos (0U)
16778 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
16779 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
16780 #define TIM_CR1_UDIS_Pos (1U)
16781 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
16782 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
16783 #define TIM_CR1_URS_Pos (2U)
16784 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
16785 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
16786 #define TIM_CR1_OPM_Pos (3U)
16787 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
16788 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
16789 #define TIM_CR1_DIR_Pos (4U)
16790 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
16791 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
16792
16793 #define TIM_CR1_CMS_Pos (5U)
16794 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
16795 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
16796 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
16797 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
16798
16799 #define TIM_CR1_ARPE_Pos (7U)
16800 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
16801 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
16802
16803 #define TIM_CR1_CKD_Pos (8U)
16804 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
16805 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
16806 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
16807 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
16808
16809 /******************* Bit definition for TIM_CR2 register ********************/
16810 #define TIM_CR2_CCPC_Pos (0U)
16811 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
16812 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
16813 #define TIM_CR2_CCUS_Pos (2U)
16814 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
16815 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
16816 #define TIM_CR2_CCDS_Pos (3U)
16817 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
16818 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
16819
16820 #define TIM_CR2_MMS_Pos (4U)
16821 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
16822 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
16823 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
16824 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
16825 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
16826
16827 #define TIM_CR2_TI1S_Pos (7U)
16828 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
16829 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
16830 #define TIM_CR2_OIS1_Pos (8U)
16831 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
16832 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
16833 #define TIM_CR2_OIS1N_Pos (9U)
16834 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
16835 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
16836 #define TIM_CR2_OIS2_Pos (10U)
16837 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
16838 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
16839 #define TIM_CR2_OIS2N_Pos (11U)
16840 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
16841 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
16842 #define TIM_CR2_OIS3_Pos (12U)
16843 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
16844 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
16845 #define TIM_CR2_OIS3N_Pos (13U)
16846 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
16847 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
16848 #define TIM_CR2_OIS4_Pos (14U)
16849 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
16850 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
16851
16852 /******************* Bit definition for TIM_SMCR register *******************/
16853 #define TIM_SMCR_SMS_Pos (0U)
16854 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
16855 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
16856 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
16857 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
16858 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
16859
16860 #define TIM_SMCR_TS_Pos (4U)
16861 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
16862 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
16863 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
16864 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
16865 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
16866
16867 #define TIM_SMCR_MSM_Pos (7U)
16868 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
16869 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
16870
16871 #define TIM_SMCR_ETF_Pos (8U)
16872 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
16873 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
16874 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
16875 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
16876 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
16877 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
16878
16879 #define TIM_SMCR_ETPS_Pos (12U)
16880 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
16881 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
16882 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
16883 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
16884
16885 #define TIM_SMCR_ECE_Pos (14U)
16886 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
16887 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
16888 #define TIM_SMCR_ETP_Pos (15U)
16889 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
16890 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
16891
16892 /******************* Bit definition for TIM_DIER register *******************/
16893 #define TIM_DIER_UIE_Pos (0U)
16894 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
16895 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
16896 #define TIM_DIER_CC1IE_Pos (1U)
16897 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
16898 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
16899 #define TIM_DIER_CC2IE_Pos (2U)
16900 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
16901 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
16902 #define TIM_DIER_CC3IE_Pos (3U)
16903 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
16904 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
16905 #define TIM_DIER_CC4IE_Pos (4U)
16906 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
16907 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
16908 #define TIM_DIER_COMIE_Pos (5U)
16909 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
16910 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
16911 #define TIM_DIER_TIE_Pos (6U)
16912 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
16913 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
16914 #define TIM_DIER_BIE_Pos (7U)
16915 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
16916 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
16917 #define TIM_DIER_UDE_Pos (8U)
16918 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
16919 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
16920 #define TIM_DIER_CC1DE_Pos (9U)
16921 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
16922 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
16923 #define TIM_DIER_CC2DE_Pos (10U)
16924 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
16925 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
16926 #define TIM_DIER_CC3DE_Pos (11U)
16927 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
16928 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
16929 #define TIM_DIER_CC4DE_Pos (12U)
16930 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
16931 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
16932 #define TIM_DIER_COMDE_Pos (13U)
16933 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
16934 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
16935 #define TIM_DIER_TDE_Pos (14U)
16936 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
16937 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
16938
16939 /******************** Bit definition for TIM_SR register ********************/
16940 #define TIM_SR_UIF_Pos (0U)
16941 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
16942 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
16943 #define TIM_SR_CC1IF_Pos (1U)
16944 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
16945 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
16946 #define TIM_SR_CC2IF_Pos (2U)
16947 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
16948 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
16949 #define TIM_SR_CC3IF_Pos (3U)
16950 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
16951 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
16952 #define TIM_SR_CC4IF_Pos (4U)
16953 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
16954 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
16955 #define TIM_SR_COMIF_Pos (5U)
16956 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
16957 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
16958 #define TIM_SR_TIF_Pos (6U)
16959 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
16960 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
16961 #define TIM_SR_BIF_Pos (7U)
16962 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
16963 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
16964 #define TIM_SR_CC1OF_Pos (9U)
16965 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
16966 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
16967 #define TIM_SR_CC2OF_Pos (10U)
16968 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
16969 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
16970 #define TIM_SR_CC3OF_Pos (11U)
16971 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
16972 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
16973 #define TIM_SR_CC4OF_Pos (12U)
16974 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
16975 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
16976
16977 /******************* Bit definition for TIM_EGR register ********************/
16978 #define TIM_EGR_UG_Pos (0U)
16979 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
16980 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
16981 #define TIM_EGR_CC1G_Pos (1U)
16982 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
16983 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
16984 #define TIM_EGR_CC2G_Pos (2U)
16985 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
16986 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
16987 #define TIM_EGR_CC3G_Pos (3U)
16988 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
16989 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
16990 #define TIM_EGR_CC4G_Pos (4U)
16991 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
16992 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
16993 #define TIM_EGR_COMG_Pos (5U)
16994 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
16995 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
16996 #define TIM_EGR_TG_Pos (6U)
16997 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
16998 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
16999 #define TIM_EGR_BG_Pos (7U)
17000 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
17001 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
17002
17003 /****************** Bit definition for TIM_CCMR1 register *******************/
17004 #define TIM_CCMR1_CC1S_Pos (0U)
17005 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
17006 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
17007 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
17008 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
17009
17010 #define TIM_CCMR1_OC1FE_Pos (2U)
17011 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
17012 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
17013 #define TIM_CCMR1_OC1PE_Pos (3U)
17014 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
17015 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
17016
17017 #define TIM_CCMR1_OC1M_Pos (4U)
17018 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
17019 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
17020 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
17021 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
17022 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
17023
17024 #define TIM_CCMR1_OC1CE_Pos (7U)
17025 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
17026 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
17027
17028 #define TIM_CCMR1_CC2S_Pos (8U)
17029 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
17030 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
17031 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
17032 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
17033
17034 #define TIM_CCMR1_OC2FE_Pos (10U)
17035 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
17036 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
17037 #define TIM_CCMR1_OC2PE_Pos (11U)
17038 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
17039 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
17040
17041 #define TIM_CCMR1_OC2M_Pos (12U)
17042 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
17043 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
17044 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
17045 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
17046 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
17047
17048 #define TIM_CCMR1_OC2CE_Pos (15U)
17049 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
17050 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
17051
17052 /*----------------------------------------------------------------------------*/
17053
17054 #define TIM_CCMR1_IC1PSC_Pos (2U)
17055 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
17056 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
17057 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
17058 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
17059
17060 #define TIM_CCMR1_IC1F_Pos (4U)
17061 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
17062 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
17063 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
17064 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
17065 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
17066 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
17067
17068 #define TIM_CCMR1_IC2PSC_Pos (10U)
17069 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
17070 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
17071 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
17072 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
17073
17074 #define TIM_CCMR1_IC2F_Pos (12U)
17075 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
17076 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
17077 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
17078 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
17079 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
17080 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
17081
17082 /****************** Bit definition for TIM_CCMR2 register *******************/
17083 #define TIM_CCMR2_CC3S_Pos (0U)
17084 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
17085 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
17086 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
17087 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
17088
17089 #define TIM_CCMR2_OC3FE_Pos (2U)
17090 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
17091 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
17092 #define TIM_CCMR2_OC3PE_Pos (3U)
17093 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
17094 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
17095
17096 #define TIM_CCMR2_OC3M_Pos (4U)
17097 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
17098 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
17099 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
17100 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
17101 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
17102
17103 #define TIM_CCMR2_OC3CE_Pos (7U)
17104 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
17105 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
17106
17107 #define TIM_CCMR2_CC4S_Pos (8U)
17108 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
17109 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
17110 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
17111 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
17112
17113 #define TIM_CCMR2_OC4FE_Pos (10U)
17114 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
17115 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
17116 #define TIM_CCMR2_OC4PE_Pos (11U)
17117 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
17118 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
17119
17120 #define TIM_CCMR2_OC4M_Pos (12U)
17121 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
17122 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
17123 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
17124 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
17125 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
17126
17127 #define TIM_CCMR2_OC4CE_Pos (15U)
17128 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
17129 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
17130
17131 /*----------------------------------------------------------------------------*/
17132
17133 #define TIM_CCMR2_IC3PSC_Pos (2U)
17134 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
17135 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
17136 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
17137 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
17138
17139 #define TIM_CCMR2_IC3F_Pos (4U)
17140 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
17141 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
17142 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
17143 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
17144 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
17145 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
17146
17147 #define TIM_CCMR2_IC4PSC_Pos (10U)
17148 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
17149 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
17150 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
17151 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
17152
17153 #define TIM_CCMR2_IC4F_Pos (12U)
17154 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
17155 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
17156 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
17157 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
17158 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
17159 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
17160
17161 /******************* Bit definition for TIM_CCER register *******************/
17162 #define TIM_CCER_CC1E_Pos (0U)
17163 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
17164 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
17165 #define TIM_CCER_CC1P_Pos (1U)
17166 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
17167 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
17168 #define TIM_CCER_CC1NE_Pos (2U)
17169 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
17170 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
17171 #define TIM_CCER_CC1NP_Pos (3U)
17172 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
17173 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
17174 #define TIM_CCER_CC2E_Pos (4U)
17175 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
17176 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
17177 #define TIM_CCER_CC2P_Pos (5U)
17178 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
17179 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
17180 #define TIM_CCER_CC2NE_Pos (6U)
17181 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
17182 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
17183 #define TIM_CCER_CC2NP_Pos (7U)
17184 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
17185 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
17186 #define TIM_CCER_CC3E_Pos (8U)
17187 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
17188 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
17189 #define TIM_CCER_CC3P_Pos (9U)
17190 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
17191 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
17192 #define TIM_CCER_CC3NE_Pos (10U)
17193 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
17194 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
17195 #define TIM_CCER_CC3NP_Pos (11U)
17196 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
17197 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
17198 #define TIM_CCER_CC4E_Pos (12U)
17199 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
17200 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
17201 #define TIM_CCER_CC4P_Pos (13U)
17202 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
17203 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
17204 #define TIM_CCER_CC4NP_Pos (15U)
17205 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
17206 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
17207
17208 /******************* Bit definition for TIM_CNT register ********************/
17209 #define TIM_CNT_CNT_Pos (0U)
17210 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
17211 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
17212
17213 /******************* Bit definition for TIM_PSC register ********************/
17214 #define TIM_PSC_PSC_Pos (0U)
17215 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
17216 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
17217
17218 /******************* Bit definition for TIM_ARR register ********************/
17219 #define TIM_ARR_ARR_Pos (0U)
17220 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
17221 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
17222
17223 /******************* Bit definition for TIM_RCR register ********************/
17224 #define TIM_RCR_REP_Pos (0U)
17225 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
17226 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
17227
17228 /******************* Bit definition for TIM_CCR1 register *******************/
17229 #define TIM_CCR1_CCR1_Pos (0U)
17230 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
17231 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
17232
17233 /******************* Bit definition for TIM_CCR2 register *******************/
17234 #define TIM_CCR2_CCR2_Pos (0U)
17235 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
17236 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
17237
17238 /******************* Bit definition for TIM_CCR3 register *******************/
17239 #define TIM_CCR3_CCR3_Pos (0U)
17240 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
17241 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
17242
17243 /******************* Bit definition for TIM_CCR4 register *******************/
17244 #define TIM_CCR4_CCR4_Pos (0U)
17245 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
17246 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
17247
17248 /******************* Bit definition for TIM_BDTR register *******************/
17249 #define TIM_BDTR_DTG_Pos (0U)
17250 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
17251 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
17252 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
17253 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
17254 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
17255 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
17256 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
17257 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
17258 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
17259 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
17260
17261 #define TIM_BDTR_LOCK_Pos (8U)
17262 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
17263 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
17264 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
17265 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
17266
17267 #define TIM_BDTR_OSSI_Pos (10U)
17268 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
17269 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
17270 #define TIM_BDTR_OSSR_Pos (11U)
17271 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
17272 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
17273 #define TIM_BDTR_BKE_Pos (12U)
17274 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
17275 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
17276 #define TIM_BDTR_BKP_Pos (13U)
17277 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
17278 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
17279 #define TIM_BDTR_AOE_Pos (14U)
17280 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
17281 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
17282 #define TIM_BDTR_MOE_Pos (15U)
17283 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
17284 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
17285
17286 /******************* Bit definition for TIM_DCR register ********************/
17287 #define TIM_DCR_DBA_Pos (0U)
17288 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
17289 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
17290 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
17291 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
17292 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
17293 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
17294 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
17295
17296 #define TIM_DCR_DBL_Pos (8U)
17297 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
17298 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
17299 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
17300 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
17301 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
17302 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
17303 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
17304
17305 /******************* Bit definition for TIM_DMAR register *******************/
17306 #define TIM_DMAR_DMAB_Pos (0U)
17307 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
17308 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
17309
17310 /******************* Bit definition for TIM_OR register *********************/
17311 #define TIM_OR_TI1_RMP_Pos (0U)
17312 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
17313 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
17314 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
17315 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
17316
17317 #define TIM_OR_TI4_RMP_Pos (6U)
17318 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
17319 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
17320 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
17321 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
17322 #define TIM_OR_ITR1_RMP_Pos (10U)
17323 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
17324 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
17325 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
17326 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
17327
17328
17329 /******************************************************************************/
17330 /* */
17331 /* Universal Synchronous Asynchronous Receiver Transmitter */
17332 /* */
17333 /******************************************************************************/
17334 /******************* Bit definition for USART_SR register *******************/
17335 #define USART_SR_PE_Pos (0U)
17336 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
17337 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
17338 #define USART_SR_FE_Pos (1U)
17339 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
17340 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
17341 #define USART_SR_NE_Pos (2U)
17342 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
17343 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
17344 #define USART_SR_ORE_Pos (3U)
17345 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
17346 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
17347 #define USART_SR_IDLE_Pos (4U)
17348 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
17349 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
17350 #define USART_SR_RXNE_Pos (5U)
17351 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
17352 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
17353 #define USART_SR_TC_Pos (6U)
17354 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
17355 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
17356 #define USART_SR_TXE_Pos (7U)
17357 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
17358 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
17359 #define USART_SR_LBD_Pos (8U)
17360 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
17361 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
17362 #define USART_SR_CTS_Pos (9U)
17363 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
17364 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
17365
17366 /******************* Bit definition for USART_DR register *******************/
17367 #define USART_DR_DR_Pos (0U)
17368 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
17369 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
17370
17371 /****************** Bit definition for USART_BRR register *******************/
17372 #define USART_BRR_DIV_Fraction_Pos (0U)
17373 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
17374 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
17375 #define USART_BRR_DIV_Mantissa_Pos (4U)
17376 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
17377 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
17378
17379 /****************** Bit definition for USART_CR1 register *******************/
17380 #define USART_CR1_SBK_Pos (0U)
17381 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
17382 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
17383 #define USART_CR1_RWU_Pos (1U)
17384 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
17385 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
17386 #define USART_CR1_RE_Pos (2U)
17387 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
17388 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
17389 #define USART_CR1_TE_Pos (3U)
17390 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
17391 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
17392 #define USART_CR1_IDLEIE_Pos (4U)
17393 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
17394 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
17395 #define USART_CR1_RXNEIE_Pos (5U)
17396 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
17397 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
17398 #define USART_CR1_TCIE_Pos (6U)
17399 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
17400 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
17401 #define USART_CR1_TXEIE_Pos (7U)
17402 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
17403 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
17404 #define USART_CR1_PEIE_Pos (8U)
17405 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
17406 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
17407 #define USART_CR1_PS_Pos (9U)
17408 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
17409 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
17410 #define USART_CR1_PCE_Pos (10U)
17411 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
17412 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
17413 #define USART_CR1_WAKE_Pos (11U)
17414 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
17415 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
17416 #define USART_CR1_M_Pos (12U)
17417 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
17418 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
17419 #define USART_CR1_UE_Pos (13U)
17420 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
17421 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
17422 #define USART_CR1_OVER8_Pos (15U)
17423 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
17424 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
17425
17426 /****************** Bit definition for USART_CR2 register *******************/
17427 #define USART_CR2_ADD_Pos (0U)
17428 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
17429 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
17430 #define USART_CR2_LBDL_Pos (5U)
17431 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
17432 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
17433 #define USART_CR2_LBDIE_Pos (6U)
17434 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
17435 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
17436 #define USART_CR2_LBCL_Pos (8U)
17437 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
17438 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
17439 #define USART_CR2_CPHA_Pos (9U)
17440 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
17441 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
17442 #define USART_CR2_CPOL_Pos (10U)
17443 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
17444 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
17445 #define USART_CR2_CLKEN_Pos (11U)
17446 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
17447 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
17448
17449 #define USART_CR2_STOP_Pos (12U)
17450 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
17451 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
17452 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
17453 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
17454
17455 #define USART_CR2_LINEN_Pos (14U)
17456 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
17457 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
17458
17459 /****************** Bit definition for USART_CR3 register *******************/
17460 #define USART_CR3_EIE_Pos (0U)
17461 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
17462 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
17463 #define USART_CR3_IREN_Pos (1U)
17464 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
17465 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
17466 #define USART_CR3_IRLP_Pos (2U)
17467 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
17468 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
17469 #define USART_CR3_HDSEL_Pos (3U)
17470 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
17471 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
17472 #define USART_CR3_NACK_Pos (4U)
17473 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
17474 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
17475 #define USART_CR3_SCEN_Pos (5U)
17476 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
17477 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
17478 #define USART_CR3_DMAR_Pos (6U)
17479 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
17480 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
17481 #define USART_CR3_DMAT_Pos (7U)
17482 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
17483 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
17484 #define USART_CR3_RTSE_Pos (8U)
17485 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
17486 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
17487 #define USART_CR3_CTSE_Pos (9U)
17488 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
17489 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
17490 #define USART_CR3_CTSIE_Pos (10U)
17491 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
17492 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
17493 #define USART_CR3_ONEBIT_Pos (11U)
17494 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
17495 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
17496
17497 /****************** Bit definition for USART_GTPR register ******************/
17498 #define USART_GTPR_PSC_Pos (0U)
17499 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
17500 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
17501 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
17502 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
17503 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
17504 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
17505 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
17506 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
17507 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
17508 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
17509
17510 #define USART_GTPR_GT_Pos (8U)
17511 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
17512 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
17513
17514 /******************************************************************************/
17515 /* */
17516 /* Window WATCHDOG */
17517 /* */
17518 /******************************************************************************/
17519 /******************* Bit definition for WWDG_CR register ********************/
17520 #define WWDG_CR_T_Pos (0U)
17521 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
17522 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
17523 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
17524 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
17525 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
17526 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
17527 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
17528 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
17529 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
17530 /* Legacy defines */
17531 #define WWDG_CR_T0 WWDG_CR_T_0
17532 #define WWDG_CR_T1 WWDG_CR_T_1
17533 #define WWDG_CR_T2 WWDG_CR_T_2
17534 #define WWDG_CR_T3 WWDG_CR_T_3
17535 #define WWDG_CR_T4 WWDG_CR_T_4
17536 #define WWDG_CR_T5 WWDG_CR_T_5
17537 #define WWDG_CR_T6 WWDG_CR_T_6
17538
17539 #define WWDG_CR_WDGA_Pos (7U)
17540 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
17541 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
17542
17543 /******************* Bit definition for WWDG_CFR register *******************/
17544 #define WWDG_CFR_W_Pos (0U)
17545 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
17546 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
17547 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
17548 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
17549 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
17550 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
17551 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
17552 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
17553 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
17554 /* Legacy defines */
17555 #define WWDG_CFR_W0 WWDG_CFR_W_0
17556 #define WWDG_CFR_W1 WWDG_CFR_W_1
17557 #define WWDG_CFR_W2 WWDG_CFR_W_2
17558 #define WWDG_CFR_W3 WWDG_CFR_W_3
17559 #define WWDG_CFR_W4 WWDG_CFR_W_4
17560 #define WWDG_CFR_W5 WWDG_CFR_W_5
17561 #define WWDG_CFR_W6 WWDG_CFR_W_6
17562
17563 #define WWDG_CFR_WDGTB_Pos (7U)
17564 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
17565 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
17566 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
17567 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
17568 /* Legacy defines */
17569 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
17570 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
17571
17572 #define WWDG_CFR_EWI_Pos (9U)
17573 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
17574 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
17575
17576 /******************* Bit definition for WWDG_SR register ********************/
17577 #define WWDG_SR_EWIF_Pos (0U)
17578 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
17579 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
17580
17581
17582 /******************************************************************************/
17583 /* */
17584 /* DBG */
17585 /* */
17586 /******************************************************************************/
17587 /******************** Bit definition for DBGMCU_IDCODE register *************/
17588 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
17589 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
17590 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
17591 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
17592 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
17593 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
17594
17595 /******************** Bit definition for DBGMCU_CR register *****************/
17596 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
17597 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
17598 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
17599 #define DBGMCU_CR_DBG_STOP_Pos (1U)
17600 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
17601 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
17602 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
17603 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
17604 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
17605 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
17606 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
17607 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
17608
17609 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
17610 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
17611 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
17612 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
17613 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
17614
17615 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
17616 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
17617 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
17618 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
17619 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
17620 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
17621 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
17622 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
17623 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
17624 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
17625 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
17626 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
17627 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
17628 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
17629 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
17630 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
17631 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
17632 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
17633 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
17634 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
17635 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
17636 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
17637 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
17638 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
17639 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
17640 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
17641 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
17642 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
17643 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
17644 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
17645 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
17646 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
17647 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
17648 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
17649 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
17650 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
17651 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
17652 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
17653 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
17654 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
17655 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
17656 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
17657 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
17658 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
17659 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
17660 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
17661 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
17662 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
17663 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
17664 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
17665 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
17666 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
17667 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
17668 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
17669 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
17670 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
17671 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
17672
17673 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
17674 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
17675 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
17676 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
17677 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
17678 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
17679 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
17680 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
17681 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
17682 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
17683 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
17684 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
17685 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
17686 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
17687 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
17688 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
17689
17690 /******************************************************************************/
17691 /* */
17692 /* Ethernet MAC Registers bits definitions */
17693 /* */
17694 /******************************************************************************/
17695 /* Bit definition for Ethernet MAC Control Register register */
17696 #define ETH_MACCR_WD_Pos (23U)
17697 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
17698 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
17699 #define ETH_MACCR_JD_Pos (22U)
17700 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
17701 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
17702 #define ETH_MACCR_IFG_Pos (17U)
17703 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
17704 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
17705 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
17706 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
17707 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
17708 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
17709 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
17710 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
17711 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
17712 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
17713 #define ETH_MACCR_CSD_Pos (16U)
17714 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
17715 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
17716 #define ETH_MACCR_FES_Pos (14U)
17717 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
17718 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
17719 #define ETH_MACCR_ROD_Pos (13U)
17720 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
17721 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
17722 #define ETH_MACCR_LM_Pos (12U)
17723 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
17724 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
17725 #define ETH_MACCR_DM_Pos (11U)
17726 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
17727 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
17728 #define ETH_MACCR_IPCO_Pos (10U)
17729 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
17730 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
17731 #define ETH_MACCR_RD_Pos (9U)
17732 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
17733 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
17734 #define ETH_MACCR_APCS_Pos (7U)
17735 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
17736 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
17737 #define ETH_MACCR_BL_Pos (5U)
17738 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
17739 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
17740 a transmission attempt during retries after a collision: 0 =< r <2^k */
17741 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
17742 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
17743 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
17744 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
17745 #define ETH_MACCR_DC_Pos (4U)
17746 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
17747 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
17748 #define ETH_MACCR_TE_Pos (3U)
17749 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
17750 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
17751 #define ETH_MACCR_RE_Pos (2U)
17752 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
17753 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
17754
17755 /* Bit definition for Ethernet MAC Frame Filter Register */
17756 #define ETH_MACFFR_RA_Pos (31U)
17757 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
17758 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
17759 #define ETH_MACFFR_HPF_Pos (10U)
17760 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
17761 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
17762 #define ETH_MACFFR_SAF_Pos (9U)
17763 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
17764 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
17765 #define ETH_MACFFR_SAIF_Pos (8U)
17766 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
17767 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
17768 #define ETH_MACFFR_PCF_Pos (6U)
17769 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
17770 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
17771 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
17772 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
17773 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
17774 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
17775 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
17776 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
17777 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
17778 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
17779 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
17780 #define ETH_MACFFR_BFD_Pos (5U)
17781 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
17782 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
17783 #define ETH_MACFFR_PAM_Pos (4U)
17784 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
17785 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
17786 #define ETH_MACFFR_DAIF_Pos (3U)
17787 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
17788 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
17789 #define ETH_MACFFR_HM_Pos (2U)
17790 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
17791 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
17792 #define ETH_MACFFR_HU_Pos (1U)
17793 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
17794 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
17795 #define ETH_MACFFR_PM_Pos (0U)
17796 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
17797 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
17798
17799 /* Bit definition for Ethernet MAC Hash Table High Register */
17800 #define ETH_MACHTHR_HTH_Pos (0U)
17801 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
17802 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
17803
17804 /* Bit definition for Ethernet MAC Hash Table Low Register */
17805 #define ETH_MACHTLR_HTL_Pos (0U)
17806 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
17807 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
17808
17809 /* Bit definition for Ethernet MAC MII Address Register */
17810 #define ETH_MACMIIAR_PA_Pos (11U)
17811 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
17812 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
17813 #define ETH_MACMIIAR_MR_Pos (6U)
17814 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
17815 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
17816 #define ETH_MACMIIAR_CR_Pos (2U)
17817 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
17818 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
17819 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
17820 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
17821 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
17822 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
17823 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
17824 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
17825 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
17826 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
17827 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
17828 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
17829 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
17830 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
17831 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
17832 #define ETH_MACMIIAR_MW_Pos (1U)
17833 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
17834 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
17835 #define ETH_MACMIIAR_MB_Pos (0U)
17836 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
17837 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
17838
17839 /* Bit definition for Ethernet MAC MII Data Register */
17840 #define ETH_MACMIIDR_MD_Pos (0U)
17841 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
17842 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
17843
17844 /* Bit definition for Ethernet MAC Flow Control Register */
17845 #define ETH_MACFCR_PT_Pos (16U)
17846 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
17847 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
17848 #define ETH_MACFCR_ZQPD_Pos (7U)
17849 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
17850 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
17851 #define ETH_MACFCR_PLT_Pos (4U)
17852 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
17853 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
17854 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
17855 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
17856 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
17857 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
17858 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
17859 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
17860 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
17861 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
17862 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
17863 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
17864 #define ETH_MACFCR_UPFD_Pos (3U)
17865 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
17866 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
17867 #define ETH_MACFCR_RFCE_Pos (2U)
17868 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
17869 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
17870 #define ETH_MACFCR_TFCE_Pos (1U)
17871 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
17872 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
17873 #define ETH_MACFCR_FCBBPA_Pos (0U)
17874 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
17875 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
17876
17877 /* Bit definition for Ethernet MAC VLAN Tag Register */
17878 #define ETH_MACVLANTR_VLANTC_Pos (16U)
17879 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
17880 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
17881 #define ETH_MACVLANTR_VLANTI_Pos (0U)
17882 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
17883 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
17884
17885 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
17886 #define ETH_MACRWUFFR_D_Pos (0U)
17887 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
17888 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
17889 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
17890 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
17891 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
17892 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
17893 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
17894 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
17895 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
17896 RSVD - Filter1 Command - RSVD - Filter0 Command
17897 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
17898 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
17899 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
17900
17901 /* Bit definition for Ethernet MAC PMT Control and Status Register */
17902 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
17903 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
17904 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
17905 #define ETH_MACPMTCSR_GU_Pos (9U)
17906 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
17907 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
17908 #define ETH_MACPMTCSR_WFR_Pos (6U)
17909 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
17910 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
17911 #define ETH_MACPMTCSR_MPR_Pos (5U)
17912 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
17913 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
17914 #define ETH_MACPMTCSR_WFE_Pos (2U)
17915 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
17916 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
17917 #define ETH_MACPMTCSR_MPE_Pos (1U)
17918 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
17919 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
17920 #define ETH_MACPMTCSR_PD_Pos (0U)
17921 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
17922 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
17923
17924 /* Bit definition for Ethernet MAC debug Register */
17925 #define ETH_MACDBGR_TFF_Pos (25U)
17926 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
17927 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
17928 #define ETH_MACDBGR_TFNE_Pos (24U)
17929 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
17930 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
17931 #define ETH_MACDBGR_TFWA_Pos (22U)
17932 #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
17933 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
17934 #define ETH_MACDBGR_TFRS_Pos (20U)
17935 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
17936 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
17937 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
17938 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
17939 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
17940 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
17941 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
17942 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
17943 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
17944 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
17945 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
17946 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
17947 #define ETH_MACDBGR_MTP_Pos (19U)
17948 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
17949 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
17950 #define ETH_MACDBGR_MTFCS_Pos (17U)
17951 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
17952 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
17953 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
17954 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
17955 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
17956 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
17957 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
17958 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
17959 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
17960 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
17961 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
17962 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
17963 #define ETH_MACDBGR_MMTEA_Pos (16U)
17964 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
17965 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
17966 #define ETH_MACDBGR_RFFL_Pos (8U)
17967 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
17968 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
17969 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
17970 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
17971 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
17972 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
17973 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
17974 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
17975 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
17976 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
17977 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
17978 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
17979 #define ETH_MACDBGR_RFRCS_Pos (5U)
17980 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
17981 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
17982 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
17983 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
17984 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
17985 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
17986 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
17987 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
17988 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
17989 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
17990 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
17991 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
17992 #define ETH_MACDBGR_RFWRA_Pos (4U)
17993 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
17994 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
17995 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
17996 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
17997 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
17998 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
17999 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
18000 #define ETH_MACDBGR_MMRPEA_Pos (0U)
18001 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
18002 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
18003
18004 /* Bit definition for Ethernet MAC Status Register */
18005 #define ETH_MACSR_TSTS_Pos (9U)
18006 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
18007 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
18008 #define ETH_MACSR_MMCTS_Pos (6U)
18009 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
18010 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
18011 #define ETH_MACSR_MMMCRS_Pos (5U)
18012 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
18013 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
18014 #define ETH_MACSR_MMCS_Pos (4U)
18015 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
18016 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
18017 #define ETH_MACSR_PMTS_Pos (3U)
18018 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
18019 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
18020
18021 /* Bit definition for Ethernet MAC Interrupt Mask Register */
18022 #define ETH_MACIMR_TSTIM_Pos (9U)
18023 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
18024 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
18025 #define ETH_MACIMR_PMTIM_Pos (3U)
18026 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
18027 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
18028
18029 /* Bit definition for Ethernet MAC Address0 High Register */
18030 #define ETH_MACA0HR_MACA0H_Pos (0U)
18031 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
18032 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
18033
18034 /* Bit definition for Ethernet MAC Address0 Low Register */
18035 #define ETH_MACA0LR_MACA0L_Pos (0U)
18036 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
18037 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
18038
18039 /* Bit definition for Ethernet MAC Address1 High Register */
18040 #define ETH_MACA1HR_AE_Pos (31U)
18041 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
18042 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
18043 #define ETH_MACA1HR_SA_Pos (30U)
18044 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
18045 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
18046 #define ETH_MACA1HR_MBC_Pos (24U)
18047 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
18048 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
18049 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
18050 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
18051 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
18052 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
18053 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
18054 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
18055 #define ETH_MACA1HR_MACA1H_Pos (0U)
18056 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
18057 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
18058
18059 /* Bit definition for Ethernet MAC Address1 Low Register */
18060 #define ETH_MACA1LR_MACA1L_Pos (0U)
18061 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
18062 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
18063
18064 /* Bit definition for Ethernet MAC Address2 High Register */
18065 #define ETH_MACA2HR_AE_Pos (31U)
18066 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
18067 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
18068 #define ETH_MACA2HR_SA_Pos (30U)
18069 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
18070 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
18071 #define ETH_MACA2HR_MBC_Pos (24U)
18072 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
18073 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
18074 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
18075 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
18076 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
18077 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
18078 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
18079 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
18080 #define ETH_MACA2HR_MACA2H_Pos (0U)
18081 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
18082 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
18083
18084 /* Bit definition for Ethernet MAC Address2 Low Register */
18085 #define ETH_MACA2LR_MACA2L_Pos (0U)
18086 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
18087 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
18088
18089 /* Bit definition for Ethernet MAC Address3 High Register */
18090 #define ETH_MACA3HR_AE_Pos (31U)
18091 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
18092 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
18093 #define ETH_MACA3HR_SA_Pos (30U)
18094 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
18095 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
18096 #define ETH_MACA3HR_MBC_Pos (24U)
18097 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
18098 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
18099 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
18100 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
18101 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
18102 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
18103 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
18104 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
18105 #define ETH_MACA3HR_MACA3H_Pos (0U)
18106 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
18107 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
18108
18109 /* Bit definition for Ethernet MAC Address3 Low Register */
18110 #define ETH_MACA3LR_MACA3L_Pos (0U)
18111 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
18112 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
18113
18114 /******************************************************************************/
18115 /* Ethernet MMC Registers bits definition */
18116 /******************************************************************************/
18117
18118 /* Bit definition for Ethernet MMC Contol Register */
18119 #define ETH_MMCCR_MCFHP_Pos (5U)
18120 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
18121 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
18122 #define ETH_MMCCR_MCP_Pos (4U)
18123 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
18124 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
18125 #define ETH_MMCCR_MCF_Pos (3U)
18126 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
18127 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
18128 #define ETH_MMCCR_ROR_Pos (2U)
18129 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
18130 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
18131 #define ETH_MMCCR_CSR_Pos (1U)
18132 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
18133 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
18134 #define ETH_MMCCR_CR_Pos (0U)
18135 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
18136 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
18137
18138 /* Bit definition for Ethernet MMC Receive Interrupt Register */
18139 #define ETH_MMCRIR_RGUFS_Pos (17U)
18140 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
18141 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
18142 #define ETH_MMCRIR_RFAES_Pos (6U)
18143 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
18144 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
18145 #define ETH_MMCRIR_RFCES_Pos (5U)
18146 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
18147 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
18148
18149 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
18150 #define ETH_MMCTIR_TGFS_Pos (21U)
18151 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
18152 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
18153 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
18154 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
18155 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
18156 #define ETH_MMCTIR_TGFSCS_Pos (14U)
18157 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
18158 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
18159
18160 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
18161 #define ETH_MMCRIMR_RGUFM_Pos (17U)
18162 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
18163 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
18164 #define ETH_MMCRIMR_RFAEM_Pos (6U)
18165 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
18166 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
18167 #define ETH_MMCRIMR_RFCEM_Pos (5U)
18168 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
18169 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
18170
18171 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
18172 #define ETH_MMCTIMR_TGFM_Pos (21U)
18173 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
18174 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
18175 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
18176 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
18177 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
18178 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
18179 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
18180 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
18181
18182 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
18183 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
18184 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
18185 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
18186
18187 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
18188 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
18189 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
18190 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
18191
18192 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
18193 #define ETH_MMCTGFCR_TGFC_Pos (0U)
18194 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
18195 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
18196
18197 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
18198 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
18199 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
18200 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
18201
18202 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
18203 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
18204 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
18205 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
18206
18207 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
18208 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
18209 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
18210 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
18211
18212 /******************************************************************************/
18213 /* Ethernet PTP Registers bits definition */
18214 /******************************************************************************/
18215
18216 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
18217 #define ETH_PTPTSCR_TSCNT_Pos (16U)
18218 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
18219 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
18220 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
18221 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
18222 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
18223 #define ETH_PTPTSSR_TSSEME_Pos (14U)
18224 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
18225 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
18226 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
18227 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
18228 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
18229 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
18230 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
18231 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
18232 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
18233 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
18234 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
18235 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
18236 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
18237 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
18238 #define ETH_PTPTSSR_TSSSR_Pos (9U)
18239 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
18240 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
18241 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
18242 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
18243 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
18244
18245 #define ETH_PTPTSCR_TSARU_Pos (5U)
18246 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
18247 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
18248 #define ETH_PTPTSCR_TSITE_Pos (4U)
18249 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
18250 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
18251 #define ETH_PTPTSCR_TSSTU_Pos (3U)
18252 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
18253 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
18254 #define ETH_PTPTSCR_TSSTI_Pos (2U)
18255 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
18256 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
18257 #define ETH_PTPTSCR_TSFCU_Pos (1U)
18258 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
18259 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
18260 #define ETH_PTPTSCR_TSE_Pos (0U)
18261 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
18262 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
18263
18264 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
18265 #define ETH_PTPSSIR_STSSI_Pos (0U)
18266 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
18267 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
18268
18269 /* Bit definition for Ethernet PTP Time Stamp High Register */
18270 #define ETH_PTPTSHR_STS_Pos (0U)
18271 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
18272 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
18273
18274 /* Bit definition for Ethernet PTP Time Stamp Low Register */
18275 #define ETH_PTPTSLR_STPNS_Pos (31U)
18276 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
18277 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
18278 #define ETH_PTPTSLR_STSS_Pos (0U)
18279 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
18280 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
18281
18282 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
18283 #define ETH_PTPTSHUR_TSUS_Pos (0U)
18284 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
18285 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
18286
18287 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
18288 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
18289 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
18290 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
18291 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
18292 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
18293 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
18294
18295 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
18296 #define ETH_PTPTSAR_TSA_Pos (0U)
18297 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
18298 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
18299
18300 /* Bit definition for Ethernet PTP Target Time High Register */
18301 #define ETH_PTPTTHR_TTSH_Pos (0U)
18302 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
18303 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
18304
18305 /* Bit definition for Ethernet PTP Target Time Low Register */
18306 #define ETH_PTPTTLR_TTSL_Pos (0U)
18307 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
18308 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
18309
18310 /* Bit definition for Ethernet PTP Time Stamp Status Register */
18311 #define ETH_PTPTSSR_TSTTR_Pos (5U)
18312 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
18313 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
18314 #define ETH_PTPTSSR_TSSO_Pos (4U)
18315 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
18316 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
18317
18318 /******************************************************************************/
18319 /* Ethernet DMA Registers bits definition */
18320 /******************************************************************************/
18321
18322 /* Bit definition for Ethernet DMA Bus Mode Register */
18323 #define ETH_DMABMR_AAB_Pos (25U)
18324 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
18325 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
18326 #define ETH_DMABMR_FPM_Pos (24U)
18327 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
18328 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
18329 #define ETH_DMABMR_USP_Pos (23U)
18330 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
18331 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
18332 #define ETH_DMABMR_RDP_Pos (17U)
18333 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
18334 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
18335 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
18336 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
18337 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18338 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18339 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18340 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18341 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18342 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18343 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18344 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18345 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
18346 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
18347 #define ETH_DMABMR_FB_Pos (16U)
18348 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
18349 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
18350 #define ETH_DMABMR_RTPR_Pos (14U)
18351 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
18352 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
18353 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
18354 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
18355 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
18356 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
18357 #define ETH_DMABMR_PBL_Pos (8U)
18358 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
18359 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
18360 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
18361 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
18362 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18363 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18364 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18365 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18366 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18367 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18368 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18369 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18370 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
18371 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
18372 #define ETH_DMABMR_EDE_Pos (7U)
18373 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
18374 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
18375 #define ETH_DMABMR_DSL_Pos (2U)
18376 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
18377 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
18378 #define ETH_DMABMR_DA_Pos (1U)
18379 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
18380 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
18381 #define ETH_DMABMR_SR_Pos (0U)
18382 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
18383 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
18384
18385 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
18386 #define ETH_DMATPDR_TPD_Pos (0U)
18387 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
18388 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
18389
18390 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
18391 #define ETH_DMARPDR_RPD_Pos (0U)
18392 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
18393 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
18394
18395 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
18396 #define ETH_DMARDLAR_SRL_Pos (0U)
18397 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
18398 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
18399
18400 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
18401 #define ETH_DMATDLAR_STL_Pos (0U)
18402 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
18403 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
18404
18405 /* Bit definition for Ethernet DMA Status Register */
18406 #define ETH_DMASR_TSTS_Pos (29U)
18407 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
18408 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
18409 #define ETH_DMASR_PMTS_Pos (28U)
18410 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
18411 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
18412 #define ETH_DMASR_MMCS_Pos (27U)
18413 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
18414 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
18415 #define ETH_DMASR_EBS_Pos (23U)
18416 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
18417 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
18418 /* combination with EBS[2:0] for GetFlagStatus function */
18419 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
18420 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
18421 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
18422 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
18423 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
18424 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
18425 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
18426 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
18427 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
18428 #define ETH_DMASR_TPS_Pos (20U)
18429 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
18430 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
18431 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
18432 #define ETH_DMASR_TPS_Fetching_Pos (20U)
18433 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
18434 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
18435 #define ETH_DMASR_TPS_Waiting_Pos (21U)
18436 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
18437 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
18438 #define ETH_DMASR_TPS_Reading_Pos (20U)
18439 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
18440 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
18441 #define ETH_DMASR_TPS_Suspended_Pos (21U)
18442 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
18443 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
18444 #define ETH_DMASR_TPS_Closing_Pos (20U)
18445 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
18446 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
18447 #define ETH_DMASR_RPS_Pos (17U)
18448 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
18449 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
18450 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
18451 #define ETH_DMASR_RPS_Fetching_Pos (17U)
18452 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
18453 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
18454 #define ETH_DMASR_RPS_Waiting_Pos (17U)
18455 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
18456 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
18457 #define ETH_DMASR_RPS_Suspended_Pos (19U)
18458 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
18459 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
18460 #define ETH_DMASR_RPS_Closing_Pos (17U)
18461 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
18462 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
18463 #define ETH_DMASR_RPS_Queuing_Pos (17U)
18464 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
18465 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
18466 #define ETH_DMASR_NIS_Pos (16U)
18467 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
18468 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
18469 #define ETH_DMASR_AIS_Pos (15U)
18470 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
18471 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
18472 #define ETH_DMASR_ERS_Pos (14U)
18473 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
18474 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
18475 #define ETH_DMASR_FBES_Pos (13U)
18476 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
18477 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
18478 #define ETH_DMASR_ETS_Pos (10U)
18479 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
18480 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
18481 #define ETH_DMASR_RWTS_Pos (9U)
18482 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
18483 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
18484 #define ETH_DMASR_RPSS_Pos (8U)
18485 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
18486 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
18487 #define ETH_DMASR_RBUS_Pos (7U)
18488 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
18489 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
18490 #define ETH_DMASR_RS_Pos (6U)
18491 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
18492 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
18493 #define ETH_DMASR_TUS_Pos (5U)
18494 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
18495 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
18496 #define ETH_DMASR_ROS_Pos (4U)
18497 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
18498 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
18499 #define ETH_DMASR_TJTS_Pos (3U)
18500 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
18501 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
18502 #define ETH_DMASR_TBUS_Pos (2U)
18503 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
18504 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
18505 #define ETH_DMASR_TPSS_Pos (1U)
18506 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
18507 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
18508 #define ETH_DMASR_TS_Pos (0U)
18509 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
18510 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
18511
18512 /* Bit definition for Ethernet DMA Operation Mode Register */
18513 #define ETH_DMAOMR_DTCEFD_Pos (26U)
18514 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
18515 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
18516 #define ETH_DMAOMR_RSF_Pos (25U)
18517 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
18518 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
18519 #define ETH_DMAOMR_DFRF_Pos (24U)
18520 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
18521 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
18522 #define ETH_DMAOMR_TSF_Pos (21U)
18523 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
18524 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
18525 #define ETH_DMAOMR_FTF_Pos (20U)
18526 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
18527 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
18528 #define ETH_DMAOMR_TTC_Pos (14U)
18529 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
18530 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
18531 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
18532 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
18533 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
18534 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
18535 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
18536 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
18537 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
18538 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
18539 #define ETH_DMAOMR_ST_Pos (13U)
18540 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
18541 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
18542 #define ETH_DMAOMR_FEF_Pos (7U)
18543 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
18544 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
18545 #define ETH_DMAOMR_FUGF_Pos (6U)
18546 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
18547 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
18548 #define ETH_DMAOMR_RTC_Pos (3U)
18549 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
18550 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
18551 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
18552 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
18553 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
18554 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
18555 #define ETH_DMAOMR_OSF_Pos (2U)
18556 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
18557 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
18558 #define ETH_DMAOMR_SR_Pos (1U)
18559 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
18560 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
18561
18562 /* Bit definition for Ethernet DMA Interrupt Enable Register */
18563 #define ETH_DMAIER_NISE_Pos (16U)
18564 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
18565 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
18566 #define ETH_DMAIER_AISE_Pos (15U)
18567 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
18568 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
18569 #define ETH_DMAIER_ERIE_Pos (14U)
18570 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
18571 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
18572 #define ETH_DMAIER_FBEIE_Pos (13U)
18573 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
18574 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
18575 #define ETH_DMAIER_ETIE_Pos (10U)
18576 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
18577 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
18578 #define ETH_DMAIER_RWTIE_Pos (9U)
18579 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
18580 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
18581 #define ETH_DMAIER_RPSIE_Pos (8U)
18582 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
18583 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
18584 #define ETH_DMAIER_RBUIE_Pos (7U)
18585 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
18586 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
18587 #define ETH_DMAIER_RIE_Pos (6U)
18588 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
18589 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
18590 #define ETH_DMAIER_TUIE_Pos (5U)
18591 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
18592 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
18593 #define ETH_DMAIER_ROIE_Pos (4U)
18594 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
18595 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
18596 #define ETH_DMAIER_TJTIE_Pos (3U)
18597 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
18598 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
18599 #define ETH_DMAIER_TBUIE_Pos (2U)
18600 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
18601 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
18602 #define ETH_DMAIER_TPSIE_Pos (1U)
18603 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
18604 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
18605 #define ETH_DMAIER_TIE_Pos (0U)
18606 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
18607 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
18608
18609 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
18610 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
18611 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
18612 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
18613 #define ETH_DMAMFBOCR_MFA_Pos (17U)
18614 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
18615 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
18616 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
18617 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
18618 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
18619 #define ETH_DMAMFBOCR_MFC_Pos (0U)
18620 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
18621 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
18622
18623 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
18624 #define ETH_DMACHTDR_HTDAP_Pos (0U)
18625 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
18626 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
18627
18628 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
18629 #define ETH_DMACHRDR_HRDAP_Pos (0U)
18630 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
18631 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
18632
18633 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
18634 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
18635 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
18636 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
18637
18638 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
18639 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
18640 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
18641 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
18642
18643 /******************************************************************************/
18644 /* */
18645 /* USB_OTG */
18646 /* */
18647 /******************************************************************************/
18648 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
18649 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
18650 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
18651 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
18652 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
18653 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
18654 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
18655 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
18656 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
18657 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
18658 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
18659 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
18660 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
18661 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
18662 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
18663 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
18664 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
18665 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
18666 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
18667 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
18668 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
18669 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
18670 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
18671 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
18672 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
18673 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
18674 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
18675 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
18676 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
18677 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
18678 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
18679 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
18680 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
18681 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
18682 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
18683 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
18684 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
18685 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
18686 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
18687 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
18688 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
18689 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
18690 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
18691 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
18692 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
18693 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
18694 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
18695 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
18696 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
18697 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
18698 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
18699 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
18700 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
18701 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
18702 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
18703
18704 /******************** Bit definition forUSB_OTG_HCFG register ********************/
18705
18706 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
18707 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
18708 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
18709 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
18710 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
18711 #define USB_OTG_HCFG_FSLSS_Pos (2U)
18712 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
18713 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
18714
18715 /******************** Bit definition for USB_OTG_DCFG register ********************/
18716
18717 #define USB_OTG_DCFG_DSPD_Pos (0U)
18718 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
18719 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
18720 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
18721 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
18722 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
18723 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
18724 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
18725
18726 #define USB_OTG_DCFG_DAD_Pos (4U)
18727 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
18728 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
18729 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
18730 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
18731 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
18732 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
18733 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
18734 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
18735 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
18736
18737 #define USB_OTG_DCFG_PFIVL_Pos (11U)
18738 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
18739 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
18740 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
18741 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
18742
18743 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
18744 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
18745 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
18746 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
18747 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
18748
18749 /******************** Bit definition for USB_OTG_PCGCR register ********************/
18750 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
18751 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
18752 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
18753 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
18754 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
18755 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
18756 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
18757 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
18758 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
18759
18760 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
18761 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
18762 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
18763 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
18764 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
18765 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
18766 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
18767 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
18768 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
18769 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
18770 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
18771 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
18772 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
18773 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
18774 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
18775 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
18776 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
18777 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
18778 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
18779 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
18780 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
18781 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
18782
18783 /******************** Bit definition for USB_OTG_DCTL register ********************/
18784 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
18785 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
18786 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
18787 #define USB_OTG_DCTL_SDIS_Pos (1U)
18788 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
18789 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
18790 #define USB_OTG_DCTL_GINSTS_Pos (2U)
18791 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
18792 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
18793 #define USB_OTG_DCTL_GONSTS_Pos (3U)
18794 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
18795 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
18796
18797 #define USB_OTG_DCTL_TCTL_Pos (4U)
18798 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
18799 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
18800 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
18801 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
18802 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
18803 #define USB_OTG_DCTL_SGINAK_Pos (7U)
18804 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
18805 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
18806 #define USB_OTG_DCTL_CGINAK_Pos (8U)
18807 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
18808 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
18809 #define USB_OTG_DCTL_SGONAK_Pos (9U)
18810 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
18811 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
18812 #define USB_OTG_DCTL_CGONAK_Pos (10U)
18813 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
18814 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
18815 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
18816 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
18817 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
18818
18819 /******************** Bit definition for USB_OTG_HFIR register ********************/
18820 #define USB_OTG_HFIR_FRIVL_Pos (0U)
18821 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
18822 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
18823
18824 /******************** Bit definition for USB_OTG_HFNUM register ********************/
18825 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
18826 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
18827 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
18828 #define USB_OTG_HFNUM_FTREM_Pos (16U)
18829 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
18830 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
18831
18832 /******************** Bit definition for USB_OTG_DSTS register ********************/
18833 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
18834 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
18835 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
18836
18837 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
18838 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
18839 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
18840 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
18841 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
18842 #define USB_OTG_DSTS_EERR_Pos (3U)
18843 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
18844 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
18845 #define USB_OTG_DSTS_FNSOF_Pos (8U)
18846 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
18847 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
18848
18849 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
18850 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
18851 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
18852 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
18853 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
18854 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
18855 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
18856 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
18857 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
18858 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
18859 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
18860 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
18861 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
18862 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
18863 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
18864 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
18865 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
18866 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
18867 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
18868 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
18869 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
18870
18871 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
18872
18873 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
18874 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
18875 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
18876 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
18877 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
18878 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
18879 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
18880 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
18881 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
18882 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
18883 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
18884 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
18885 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
18886 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
18887 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
18888 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
18889 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
18890 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
18891 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
18892 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
18893 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
18894 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
18895 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
18896 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
18897 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
18898 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
18899 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
18900 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
18901 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
18902 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
18903 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
18904 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
18905 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
18906 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
18907 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
18908 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
18909 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
18910 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
18911 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
18912 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
18913 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
18914 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
18915 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
18916 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
18917 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
18918 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
18919 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
18920 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
18921 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
18922 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
18923 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
18924 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
18925 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
18926 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
18927 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
18928 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
18929 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
18930 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
18931 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
18932 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
18933 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
18934
18935 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
18936 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
18937 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
18938 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
18939 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
18940 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
18941 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
18942 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
18943 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
18944 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
18945 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
18946 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
18947 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
18948 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
18949 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
18950 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
18951
18952
18953 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
18954 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
18955 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
18956 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
18957 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
18958 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
18959 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
18960 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
18961 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
18962 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
18963 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
18964 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
18965 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
18966 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
18967
18968 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
18969 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
18970 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18971 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
18972 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
18973 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
18974 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
18975 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
18976 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
18977 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
18978 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
18979 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
18980 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
18981 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
18982 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
18983 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
18984 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
18985 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
18986 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
18987 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
18988 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
18989 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
18990 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
18991 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
18992 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
18993
18994 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
18995 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
18996 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
18997 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
18998 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
18999 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
19000 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
19001 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
19002 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
19003 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
19004 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
19005 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
19006 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
19007 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
19008 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
19009
19010 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
19011 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
19012 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
19013 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
19014 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
19015 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
19016 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
19017 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
19018 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
19019 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
19020 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
19021
19022 /******************** Bit definition for USB_OTG_HAINT register ********************/
19023 #define USB_OTG_HAINT_HAINT_Pos (0U)
19024 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
19025 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
19026
19027 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
19028 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
19029 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
19030 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
19031 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
19032 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
19033 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19034 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
19035 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
19036 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
19037 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
19038 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
19039 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
19040 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
19041 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
19042 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
19043 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
19044 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
19045 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
19046 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
19047 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
19048 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
19049 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
19050 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
19051 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
19052
19053 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
19054 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
19055 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
19056 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
19057 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
19058 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
19059 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
19060 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
19061 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
19062 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
19063 #define USB_OTG_GINTSTS_SOF_Pos (3U)
19064 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
19065 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
19066 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
19067 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
19068 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
19069 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
19070 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
19071 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
19072 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
19073 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
19074 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
19075 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
19076 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
19077 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
19078 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
19079 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
19080 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
19081 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
19082 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
19083 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
19084 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
19085 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
19086 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
19087 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
19088 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
19089 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
19090 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
19091 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
19092 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
19093 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
19094 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
19095 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
19096 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
19097 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
19098 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
19099 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
19100 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
19101 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
19102 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
19103 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
19104 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
19105 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
19106 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
19107 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
19108 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
19109 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
19110 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
19111 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
19112 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
19113 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
19114 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
19115 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
19116 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
19117 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
19118 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
19119 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
19120 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
19121 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
19122 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
19123 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
19124 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
19125 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
19126 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
19127 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
19128 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
19129 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
19130 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
19131 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
19132 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
19133 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
19134 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
19135 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
19136 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
19137 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
19138
19139 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
19140 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
19141 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
19142 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
19143 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
19144 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
19145 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
19146 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
19147 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
19148 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
19149 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
19150 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
19151 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
19152 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
19153 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
19154 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
19155 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
19156 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
19157 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
19158 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
19159 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
19160 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
19161 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
19162 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
19163 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
19164 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
19165 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
19166 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
19167 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
19168 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
19169 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
19170 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
19171 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
19172 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
19173 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
19174 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
19175 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
19176 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
19177 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
19178 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
19179 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
19180 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
19181 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
19182 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
19183 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
19184 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
19185 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
19186 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
19187 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
19188 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
19189 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
19190 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
19191 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
19192 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
19193 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
19194 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
19195 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
19196 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
19197 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
19198 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
19199 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
19200 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
19201 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
19202 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
19203 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
19204 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
19205 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
19206 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
19207 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
19208 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
19209 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
19210 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
19211 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
19212 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
19213 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
19214 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
19215 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
19216 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
19217 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
19218 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
19219 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
19220 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
19221 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
19222 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
19223 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
19224
19225 /******************** Bit definition for USB_OTG_DAINT register ********************/
19226 #define USB_OTG_DAINT_IEPINT_Pos (0U)
19227 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
19228 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
19229 #define USB_OTG_DAINT_OEPINT_Pos (16U)
19230 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
19231 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
19232
19233 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
19234 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
19235 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
19236 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
19237
19238 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
19239 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
19240 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
19241 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
19242 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
19243 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
19244 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
19245 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
19246 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
19247 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
19248 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
19249 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
19250 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
19251
19252 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
19253 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
19254 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
19255 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
19256 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
19257 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
19258 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
19259
19260 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
19261 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
19262 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
19263 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
19264
19265 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
19266 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
19267 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
19268 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
19269
19270 /******************** Bit definition for OTG register ********************/
19271 #define USB_OTG_NPTXFSA_Pos (0U)
19272 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
19273 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
19274 #define USB_OTG_NPTXFD_Pos (16U)
19275 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
19276 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
19277 #define USB_OTG_TX0FSA_Pos (0U)
19278 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
19279 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
19280 #define USB_OTG_TX0FD_Pos (16U)
19281 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
19282 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
19283
19284 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
19285 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
19286 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
19287 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
19288
19289 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
19290 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
19291 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
19292 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
19293
19294 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
19295 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
19296 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
19297 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
19298 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
19299 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
19300 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
19301 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
19302 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
19303 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
19304 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
19305
19306 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
19307 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
19308 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
19309 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
19310 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
19311 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
19312 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
19313 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
19314 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
19315 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
19316
19317 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
19318 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
19319 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
19320 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
19321 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
19322 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
19323 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
19324
19325 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
19326 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
19327 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
19328 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
19329 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
19330 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
19331 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
19332 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
19333 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
19334 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
19335 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
19336 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
19337 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
19338 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
19339 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
19340
19341 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
19342 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
19343 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
19344 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
19345 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
19346 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
19347 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
19348 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
19349 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
19350 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
19351 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
19352 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
19353 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
19354 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
19355 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
19356
19357 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
19358 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
19359 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
19360 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
19361
19362 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
19363 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
19364 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
19365 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
19366 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
19367 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
19368 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
19369
19370 /******************** Bit definition for USB_OTG_GCCFG register ********************/
19371 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
19372 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
19373 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
19374 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
19375 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
19376 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
19377
19378 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
19379 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
19380 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
19381 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
19382 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
19383 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
19384 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
19385
19386 /******************** Bit definition for USB_OTG_CID register ********************/
19387 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
19388 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
19389 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
19390
19391 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
19392 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
19393 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
19394 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
19395 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
19396 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
19397 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
19398 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
19399 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
19400 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
19401 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
19402 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
19403 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
19404 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
19405 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
19406 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
19407 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
19408 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
19409 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
19410 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
19411 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
19412 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
19413 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
19414 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
19415 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
19416 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
19417 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
19418 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
19419 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
19420 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
19421 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
19422 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
19423 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
19424 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
19425 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
19426 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
19427 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
19428 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
19429 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
19430 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
19431 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
19432 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
19433 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
19434 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
19435 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
19436 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
19437
19438 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
19439 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
19440 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19441 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
19442 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
19443 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19444 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19445 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
19446 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19447 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
19448 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
19449 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19450 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
19451 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
19452 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19453 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
19454 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
19455 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19456 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19457 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
19458 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19459 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
19460 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
19461 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19462 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
19463 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
19464 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19465 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19466
19467 /******************** Bit definition for USB_OTG_HPRT register ********************/
19468 #define USB_OTG_HPRT_PCSTS_Pos (0U)
19469 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
19470 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
19471 #define USB_OTG_HPRT_PCDET_Pos (1U)
19472 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
19473 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
19474 #define USB_OTG_HPRT_PENA_Pos (2U)
19475 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
19476 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
19477 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
19478 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
19479 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
19480 #define USB_OTG_HPRT_POCA_Pos (4U)
19481 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
19482 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
19483 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
19484 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
19485 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
19486 #define USB_OTG_HPRT_PRES_Pos (6U)
19487 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
19488 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
19489 #define USB_OTG_HPRT_PSUSP_Pos (7U)
19490 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
19491 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
19492 #define USB_OTG_HPRT_PRST_Pos (8U)
19493 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
19494 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
19495
19496 #define USB_OTG_HPRT_PLSTS_Pos (10U)
19497 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
19498 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
19499 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
19500 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
19501 #define USB_OTG_HPRT_PPWR_Pos (12U)
19502 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
19503 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
19504
19505 #define USB_OTG_HPRT_PTCTL_Pos (13U)
19506 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
19507 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
19508 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
19509 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
19510 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
19511 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
19512
19513 #define USB_OTG_HPRT_PSPD_Pos (17U)
19514 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
19515 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
19516 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
19517 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
19518
19519 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
19520 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
19521 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19522 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
19523 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
19524 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19525 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19526 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
19527 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19528 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
19529 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
19530 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19531 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
19532 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
19533 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19534 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
19535 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
19536 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19537 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19538 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
19539 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19540 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
19541 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
19542 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19543 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
19544 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
19545 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
19546 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
19547 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
19548 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19549 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19550 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
19551 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
19552 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
19553
19554 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
19555 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
19556 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
19557 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
19558 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
19559 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
19560 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
19561
19562 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
19563 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
19564 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19565 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
19566 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
19567 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19568 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
19569 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
19570 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
19571 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
19572 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
19573 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19574 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
19575
19576 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
19577 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19578 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
19579 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19580 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19581 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
19582 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
19583 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
19584
19585 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
19586 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
19587 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
19588 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
19589 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
19590 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
19591 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
19592 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
19593 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
19594 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
19595 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
19596 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
19597 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
19598 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
19599 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19600 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19601 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
19602 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19603 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
19604 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
19605 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19606 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
19607 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
19608 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
19609 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
19610
19611 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
19612 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
19613 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
19614 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
19615
19616 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
19617 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
19618 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
19619 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
19620 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
19621 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
19622 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
19623 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
19624 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
19625 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
19626 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
19627 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
19628 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
19629
19630 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
19631 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
19632 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
19633 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
19634 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
19635
19636 #define USB_OTG_HCCHAR_MC_Pos (20U)
19637 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
19638 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
19639 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
19640 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
19641
19642 #define USB_OTG_HCCHAR_DAD_Pos (22U)
19643 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
19644 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
19645 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
19646 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
19647 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
19648 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
19649 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
19650 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
19651 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
19652 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
19653 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
19654 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
19655 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
19656 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
19657 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
19658 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
19659 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
19660 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
19661
19662 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
19663
19664 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
19665 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
19666 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
19667 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
19668 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
19669 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
19670 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
19671 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
19672 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
19673 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
19674
19675 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
19676 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
19677 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
19678 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
19679 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
19680 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
19681 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
19682 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
19683 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
19684 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
19685
19686 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
19687 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
19688 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
19689 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
19690 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
19691 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
19692 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
19693 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
19694 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
19695 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
19696 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
19697
19698 /******************** Bit definition for USB_OTG_HCINT register ********************/
19699 #define USB_OTG_HCINT_XFRC_Pos (0U)
19700 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
19701 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
19702 #define USB_OTG_HCINT_CHH_Pos (1U)
19703 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
19704 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
19705 #define USB_OTG_HCINT_AHBERR_Pos (2U)
19706 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
19707 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
19708 #define USB_OTG_HCINT_STALL_Pos (3U)
19709 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
19710 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
19711 #define USB_OTG_HCINT_NAK_Pos (4U)
19712 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
19713 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
19714 #define USB_OTG_HCINT_ACK_Pos (5U)
19715 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
19716 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
19717 #define USB_OTG_HCINT_NYET_Pos (6U)
19718 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
19719 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
19720 #define USB_OTG_HCINT_TXERR_Pos (7U)
19721 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
19722 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
19723 #define USB_OTG_HCINT_BBERR_Pos (8U)
19724 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
19725 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
19726 #define USB_OTG_HCINT_FRMOR_Pos (9U)
19727 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
19728 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
19729 #define USB_OTG_HCINT_DTERR_Pos (10U)
19730 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
19731 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
19732
19733 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
19734 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
19735 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
19736 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
19737 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
19738 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
19739 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
19740 #define USB_OTG_DIEPINT_TOC_Pos (3U)
19741 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
19742 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
19743 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
19744 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
19745 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
19746 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
19747 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
19748 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
19749 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
19750 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
19751 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
19752 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
19753 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
19754 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
19755 #define USB_OTG_DIEPINT_BNA_Pos (9U)
19756 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
19757 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
19758 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
19759 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
19760 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
19761 #define USB_OTG_DIEPINT_BERR_Pos (12U)
19762 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
19763 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
19764 #define USB_OTG_DIEPINT_NAK_Pos (13U)
19765 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
19766 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
19767
19768 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
19769 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
19770 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
19771 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
19772 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
19773 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
19774 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
19775 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
19776 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
19777 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
19778 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
19779 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
19780 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
19781 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
19782 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
19783 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
19784 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
19785 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
19786 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
19787 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
19788 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
19789 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
19790 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
19791 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
19792 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
19793 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
19794 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
19795 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
19796 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
19797 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
19798 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
19799 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
19800 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
19801 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
19802
19803 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
19804
19805 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
19806 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19807 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
19808 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
19809 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19810 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
19811 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
19812 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
19813 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
19814 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
19815 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
19816 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19817 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
19818 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
19819 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19820 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
19821 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
19822 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
19823 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
19824 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
19825 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
19826 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
19827 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
19828 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
19829
19830 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
19831 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
19832 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19833 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
19834
19835 /******************** Bit definition for USB_OTG_HCDMA register ********************/
19836 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
19837 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19838 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
19839
19840 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
19841 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
19842 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
19843 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
19844
19845 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
19846 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
19847 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
19848 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
19849 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
19850 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
19851 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
19852
19853 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
19854
19855 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
19856 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19857 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
19858 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
19859 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19860 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
19861 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
19862 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19863 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
19864 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
19865 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19866 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19867 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
19868 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19869 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
19870 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
19871 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19872 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
19873 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19874 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19875 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
19876 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
19877 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
19878 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
19879 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
19880 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
19881 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
19882 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
19883 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
19884 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
19885 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
19886 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
19887 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
19888 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19889 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
19890 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
19891 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
19892 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
19893
19894 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
19895 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
19896 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
19897 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
19898 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
19899 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
19900 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
19901 #define USB_OTG_DOEPINT_STUP_Pos (3U)
19902 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
19903 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
19904 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
19905 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
19906 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
19907 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
19908 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
19909 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
19910 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
19911 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
19912 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
19913 #define USB_OTG_DOEPINT_NYET_Pos (14U)
19914 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
19915 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
19916
19917 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
19918
19919 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
19920 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19921 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
19922 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
19923 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19924 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
19925
19926 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
19927 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
19928 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
19929 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
19930 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
19931
19932 /******************** Bit definition for PCGCCTL register ********************/
19933 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
19934 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
19935 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
19936 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
19937 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
19938 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
19939 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
19940 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
19941 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
19942
19943 /* Legacy define */
19944 /******************** Bit definition for OTG register ********************/
19945 #define USB_OTG_CHNUM_Pos (0U)
19946 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
19947 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
19948 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
19949 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
19950 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
19951 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
19952 #define USB_OTG_BCNT_Pos (4U)
19953 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
19954 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
19955
19956 #define USB_OTG_DPID_Pos (15U)
19957 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
19958 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
19959 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
19960 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
19961
19962 #define USB_OTG_PKTSTS_Pos (17U)
19963 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
19964 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
19965 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
19966 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
19967 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
19968 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
19969
19970 #define USB_OTG_EPNUM_Pos (0U)
19971 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
19972 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
19973 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
19974 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
19975 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
19976 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
19977
19978 #define USB_OTG_FRMNUM_Pos (21U)
19979 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
19980 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
19981 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
19982 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
19983 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
19984 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
19985 /**
19986 * @}
19987 */
19988
19989 /**
19990 * @}
19991 */
19992
19993 /** @addtogroup Exported_macros
19994 * @{
19995 */
19996
19997 /******************************* ADC Instances ********************************/
19998 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
19999 ((INSTANCE) == ADC2) || \
20000 ((INSTANCE) == ADC3))
20001
20002 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
20003
20004 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
20005
20006 /******************************* CAN Instances ********************************/
20007 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
20008 ((INSTANCE) == CAN2))
20009 /******************************* CRC Instances ********************************/
20010 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
20011
20012 /******************************* DAC Instances ********************************/
20013 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
20014
20015 /******************************* DCMI Instances *******************************/
20016 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
20017
20018 /******************************* DMA2D Instances *******************************/
20019 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
20020
20021 /******************************** DMA Instances *******************************/
20022 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
20023 ((INSTANCE) == DMA1_Stream1) || \
20024 ((INSTANCE) == DMA1_Stream2) || \
20025 ((INSTANCE) == DMA1_Stream3) || \
20026 ((INSTANCE) == DMA1_Stream4) || \
20027 ((INSTANCE) == DMA1_Stream5) || \
20028 ((INSTANCE) == DMA1_Stream6) || \
20029 ((INSTANCE) == DMA1_Stream7) || \
20030 ((INSTANCE) == DMA2_Stream0) || \
20031 ((INSTANCE) == DMA2_Stream1) || \
20032 ((INSTANCE) == DMA2_Stream2) || \
20033 ((INSTANCE) == DMA2_Stream3) || \
20034 ((INSTANCE) == DMA2_Stream4) || \
20035 ((INSTANCE) == DMA2_Stream5) || \
20036 ((INSTANCE) == DMA2_Stream6) || \
20037 ((INSTANCE) == DMA2_Stream7))
20038
20039 /******************************* GPIO Instances *******************************/
20040 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
20041 ((INSTANCE) == GPIOB) || \
20042 ((INSTANCE) == GPIOC) || \
20043 ((INSTANCE) == GPIOD) || \
20044 ((INSTANCE) == GPIOE) || \
20045 ((INSTANCE) == GPIOF) || \
20046 ((INSTANCE) == GPIOG) || \
20047 ((INSTANCE) == GPIOH) || \
20048 ((INSTANCE) == GPIOI) || \
20049 ((INSTANCE) == GPIOJ) || \
20050 ((INSTANCE) == GPIOK))
20051
20052 /******************************** I2C Instances *******************************/
20053 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
20054 ((INSTANCE) == I2C2) || \
20055 ((INSTANCE) == I2C3))
20056
20057 /******************************* SMBUS Instances ******************************/
20058 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
20059
20060 /******************************** I2S Instances *******************************/
20061
20062 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
20063 ((INSTANCE) == SPI3))
20064
20065 /*************************** I2S Extended Instances ***************************/
20066 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
20067 ((INSTANCE) == I2S3ext))
20068 /* Legacy Defines */
20069 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
20070
20071 /****************************** LTDC Instances ********************************/
20072 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
20073 /******************************* RNG Instances ********************************/
20074 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
20075
20076 /****************************** RTC Instances *********************************/
20077 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
20078
20079 /******************************* SAI Instances ********************************/
20080 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
20081 ((PERIPH) == SAI1_Block_B))
20082 /* Legacy define */
20083
20084 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
20085
20086 /******************************** SPI Instances *******************************/
20087 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
20088 ((INSTANCE) == SPI2) || \
20089 ((INSTANCE) == SPI3) || \
20090 ((INSTANCE) == SPI4) || \
20091 ((INSTANCE) == SPI5) || \
20092 ((INSTANCE) == SPI6))
20093
20094
20095 /****************** TIM Instances : All supported instances *******************/
20096 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20097 ((INSTANCE) == TIM2) || \
20098 ((INSTANCE) == TIM3) || \
20099 ((INSTANCE) == TIM4) || \
20100 ((INSTANCE) == TIM5) || \
20101 ((INSTANCE) == TIM6) || \
20102 ((INSTANCE) == TIM7) || \
20103 ((INSTANCE) == TIM8) || \
20104 ((INSTANCE) == TIM9) || \
20105 ((INSTANCE) == TIM10)|| \
20106 ((INSTANCE) == TIM11)|| \
20107 ((INSTANCE) == TIM12)|| \
20108 ((INSTANCE) == TIM13)|| \
20109 ((INSTANCE) == TIM14))
20110
20111 /************* TIM Instances : at least 1 capture/compare channel *************/
20112 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20113 ((INSTANCE) == TIM2) || \
20114 ((INSTANCE) == TIM3) || \
20115 ((INSTANCE) == TIM4) || \
20116 ((INSTANCE) == TIM5) || \
20117 ((INSTANCE) == TIM8) || \
20118 ((INSTANCE) == TIM9) || \
20119 ((INSTANCE) == TIM10) || \
20120 ((INSTANCE) == TIM11) || \
20121 ((INSTANCE) == TIM12) || \
20122 ((INSTANCE) == TIM13) || \
20123 ((INSTANCE) == TIM14))
20124
20125 /************ TIM Instances : at least 2 capture/compare channels *************/
20126 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20127 ((INSTANCE) == TIM2) || \
20128 ((INSTANCE) == TIM3) || \
20129 ((INSTANCE) == TIM4) || \
20130 ((INSTANCE) == TIM5) || \
20131 ((INSTANCE) == TIM8) || \
20132 ((INSTANCE) == TIM9) || \
20133 ((INSTANCE) == TIM12))
20134
20135 /************ TIM Instances : at least 3 capture/compare channels *************/
20136 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20137 ((INSTANCE) == TIM2) || \
20138 ((INSTANCE) == TIM3) || \
20139 ((INSTANCE) == TIM4) || \
20140 ((INSTANCE) == TIM5) || \
20141 ((INSTANCE) == TIM8))
20142
20143 /************ TIM Instances : at least 4 capture/compare channels *************/
20144 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20145 ((INSTANCE) == TIM2) || \
20146 ((INSTANCE) == TIM3) || \
20147 ((INSTANCE) == TIM4) || \
20148 ((INSTANCE) == TIM5) || \
20149 ((INSTANCE) == TIM8))
20150
20151 /******************** TIM Instances : Advanced-control timers *****************/
20152 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20153 ((INSTANCE) == TIM8))
20154
20155 /******************* TIM Instances : Timer input XOR function *****************/
20156 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20157 ((INSTANCE) == TIM2) || \
20158 ((INSTANCE) == TIM3) || \
20159 ((INSTANCE) == TIM4) || \
20160 ((INSTANCE) == TIM5) || \
20161 ((INSTANCE) == TIM8))
20162
20163 /****************** TIM Instances : DMA requests generation (UDE) *************/
20164 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20165 ((INSTANCE) == TIM2) || \
20166 ((INSTANCE) == TIM3) || \
20167 ((INSTANCE) == TIM4) || \
20168 ((INSTANCE) == TIM5) || \
20169 ((INSTANCE) == TIM6) || \
20170 ((INSTANCE) == TIM7) || \
20171 ((INSTANCE) == TIM8))
20172
20173 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
20174 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20175 ((INSTANCE) == TIM2) || \
20176 ((INSTANCE) == TIM3) || \
20177 ((INSTANCE) == TIM4) || \
20178 ((INSTANCE) == TIM5) || \
20179 ((INSTANCE) == TIM8))
20180
20181 /************ TIM Instances : DMA requests generation (COMDE) *****************/
20182 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20183 ((INSTANCE) == TIM2) || \
20184 ((INSTANCE) == TIM3) || \
20185 ((INSTANCE) == TIM4) || \
20186 ((INSTANCE) == TIM5) || \
20187 ((INSTANCE) == TIM8))
20188
20189 /******************** TIM Instances : DMA burst feature ***********************/
20190 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20191 ((INSTANCE) == TIM2) || \
20192 ((INSTANCE) == TIM3) || \
20193 ((INSTANCE) == TIM4) || \
20194 ((INSTANCE) == TIM5) || \
20195 ((INSTANCE) == TIM8))
20196
20197 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
20198 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20199 ((INSTANCE) == TIM2) || \
20200 ((INSTANCE) == TIM3) || \
20201 ((INSTANCE) == TIM4) || \
20202 ((INSTANCE) == TIM5) || \
20203 ((INSTANCE) == TIM6) || \
20204 ((INSTANCE) == TIM7) || \
20205 ((INSTANCE) == TIM8))
20206
20207 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
20208 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20209 ((INSTANCE) == TIM2) || \
20210 ((INSTANCE) == TIM3) || \
20211 ((INSTANCE) == TIM4) || \
20212 ((INSTANCE) == TIM5) || \
20213 ((INSTANCE) == TIM8) || \
20214 ((INSTANCE) == TIM9) || \
20215 ((INSTANCE) == TIM12))
20216
20217 /********************** TIM Instances : 32 bit Counter ************************/
20218 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
20219 ((INSTANCE) == TIM5))
20220
20221 /***************** TIM Instances : external trigger input availabe ************/
20222 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20223 ((INSTANCE) == TIM2) || \
20224 ((INSTANCE) == TIM3) || \
20225 ((INSTANCE) == TIM4) || \
20226 ((INSTANCE) == TIM5) || \
20227 ((INSTANCE) == TIM8))
20228
20229 /****************** TIM Instances : remapping capability **********************/
20230 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
20231 ((INSTANCE) == TIM5) || \
20232 ((INSTANCE) == TIM11))
20233
20234 /******************* TIM Instances : output(s) available **********************/
20235 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
20236 ((((INSTANCE) == TIM1) && \
20237 (((CHANNEL) == TIM_CHANNEL_1) || \
20238 ((CHANNEL) == TIM_CHANNEL_2) || \
20239 ((CHANNEL) == TIM_CHANNEL_3) || \
20240 ((CHANNEL) == TIM_CHANNEL_4))) \
20241 || \
20242 (((INSTANCE) == TIM2) && \
20243 (((CHANNEL) == TIM_CHANNEL_1) || \
20244 ((CHANNEL) == TIM_CHANNEL_2) || \
20245 ((CHANNEL) == TIM_CHANNEL_3) || \
20246 ((CHANNEL) == TIM_CHANNEL_4))) \
20247 || \
20248 (((INSTANCE) == TIM3) && \
20249 (((CHANNEL) == TIM_CHANNEL_1) || \
20250 ((CHANNEL) == TIM_CHANNEL_2) || \
20251 ((CHANNEL) == TIM_CHANNEL_3) || \
20252 ((CHANNEL) == TIM_CHANNEL_4))) \
20253 || \
20254 (((INSTANCE) == TIM4) && \
20255 (((CHANNEL) == TIM_CHANNEL_1) || \
20256 ((CHANNEL) == TIM_CHANNEL_2) || \
20257 ((CHANNEL) == TIM_CHANNEL_3) || \
20258 ((CHANNEL) == TIM_CHANNEL_4))) \
20259 || \
20260 (((INSTANCE) == TIM5) && \
20261 (((CHANNEL) == TIM_CHANNEL_1) || \
20262 ((CHANNEL) == TIM_CHANNEL_2) || \
20263 ((CHANNEL) == TIM_CHANNEL_3) || \
20264 ((CHANNEL) == TIM_CHANNEL_4))) \
20265 || \
20266 (((INSTANCE) == TIM8) && \
20267 (((CHANNEL) == TIM_CHANNEL_1) || \
20268 ((CHANNEL) == TIM_CHANNEL_2) || \
20269 ((CHANNEL) == TIM_CHANNEL_3) || \
20270 ((CHANNEL) == TIM_CHANNEL_4))) \
20271 || \
20272 (((INSTANCE) == TIM9) && \
20273 (((CHANNEL) == TIM_CHANNEL_1) || \
20274 ((CHANNEL) == TIM_CHANNEL_2))) \
20275 || \
20276 (((INSTANCE) == TIM10) && \
20277 (((CHANNEL) == TIM_CHANNEL_1))) \
20278 || \
20279 (((INSTANCE) == TIM11) && \
20280 (((CHANNEL) == TIM_CHANNEL_1))) \
20281 || \
20282 (((INSTANCE) == TIM12) && \
20283 (((CHANNEL) == TIM_CHANNEL_1) || \
20284 ((CHANNEL) == TIM_CHANNEL_2))) \
20285 || \
20286 (((INSTANCE) == TIM13) && \
20287 (((CHANNEL) == TIM_CHANNEL_1))) \
20288 || \
20289 (((INSTANCE) == TIM14) && \
20290 (((CHANNEL) == TIM_CHANNEL_1))))
20291
20292 /************ TIM Instances : complementary output(s) available ***************/
20293 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
20294 ((((INSTANCE) == TIM1) && \
20295 (((CHANNEL) == TIM_CHANNEL_1) || \
20296 ((CHANNEL) == TIM_CHANNEL_2) || \
20297 ((CHANNEL) == TIM_CHANNEL_3))) \
20298 || \
20299 (((INSTANCE) == TIM8) && \
20300 (((CHANNEL) == TIM_CHANNEL_1) || \
20301 ((CHANNEL) == TIM_CHANNEL_2) || \
20302 ((CHANNEL) == TIM_CHANNEL_3))))
20303
20304 /****************** TIM Instances : supporting counting mode selection ********/
20305 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20306 ((INSTANCE) == TIM2) || \
20307 ((INSTANCE) == TIM3) || \
20308 ((INSTANCE) == TIM4) || \
20309 ((INSTANCE) == TIM5) || \
20310 ((INSTANCE) == TIM8))
20311
20312 /****************** TIM Instances : supporting clock division *****************/
20313 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20314 ((INSTANCE) == TIM2) || \
20315 ((INSTANCE) == TIM3) || \
20316 ((INSTANCE) == TIM4) || \
20317 ((INSTANCE) == TIM5) || \
20318 ((INSTANCE) == TIM8) || \
20319 ((INSTANCE) == TIM9) || \
20320 ((INSTANCE) == TIM10)|| \
20321 ((INSTANCE) == TIM11)|| \
20322 ((INSTANCE) == TIM12)|| \
20323 ((INSTANCE) == TIM13)|| \
20324 ((INSTANCE) == TIM14))
20325
20326 /****************** TIM Instances : supporting commutation event generation ***/
20327 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
20328 ((INSTANCE) == TIM8))
20329
20330
20331 /****************** TIM Instances : supporting OCxREF clear *******************/
20332 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20333 ((INSTANCE) == TIM2) || \
20334 ((INSTANCE) == TIM3) || \
20335 ((INSTANCE) == TIM4) || \
20336 ((INSTANCE) == TIM5) || \
20337 ((INSTANCE) == TIM8))
20338
20339 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
20340 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20341 ((INSTANCE) == TIM2) || \
20342 ((INSTANCE) == TIM3) || \
20343 ((INSTANCE) == TIM4) || \
20344 ((INSTANCE) == TIM5) || \
20345 ((INSTANCE) == TIM8) || \
20346 ((INSTANCE) == TIM9) || \
20347 ((INSTANCE) == TIM12))
20348
20349 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
20350 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20351 ((INSTANCE) == TIM2) || \
20352 ((INSTANCE) == TIM3) || \
20353 ((INSTANCE) == TIM4) || \
20354 ((INSTANCE) == TIM5) || \
20355 ((INSTANCE) == TIM8))
20356
20357 /****************** TIM Instances : supporting repetition counter *************/
20358 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20359 ((INSTANCE) == TIM8))
20360
20361 /****************** TIM Instances : supporting encoder interface **************/
20362 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20363 ((INSTANCE) == TIM2) || \
20364 ((INSTANCE) == TIM3) || \
20365 ((INSTANCE) == TIM4) || \
20366 ((INSTANCE) == TIM5) || \
20367 ((INSTANCE) == TIM8) || \
20368 ((INSTANCE) == TIM9) || \
20369 ((INSTANCE) == TIM12))
20370 /****************** TIM Instances : supporting Hall sensor interface **********/
20371 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20372 ((INSTANCE) == TIM2) || \
20373 ((INSTANCE) == TIM3) || \
20374 ((INSTANCE) == TIM4) || \
20375 ((INSTANCE) == TIM5) || \
20376 ((INSTANCE) == TIM8))
20377 /****************** TIM Instances : supporting the break function *************/
20378 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20379 ((INSTANCE) == TIM8))
20380
20381 /******************** USART Instances : Synchronous mode **********************/
20382 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20383 ((INSTANCE) == USART2) || \
20384 ((INSTANCE) == USART3) || \
20385 ((INSTANCE) == USART6))
20386
20387 /******************** UART Instances : Half-Duplex mode **********************/
20388 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20389 ((INSTANCE) == USART2) || \
20390 ((INSTANCE) == USART3) || \
20391 ((INSTANCE) == UART4) || \
20392 ((INSTANCE) == UART5) || \
20393 ((INSTANCE) == USART6) || \
20394 ((INSTANCE) == UART7) || \
20395 ((INSTANCE) == UART8))
20396
20397 /* Legacy defines */
20398 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20399
20400 /****************** UART Instances : Hardware Flow control ********************/
20401 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20402 ((INSTANCE) == USART2) || \
20403 ((INSTANCE) == USART3) || \
20404 ((INSTANCE) == USART6))
20405 /******************** UART Instances : LIN mode **********************/
20406 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20407
20408 /********************* UART Instances : Smart card mode ***********************/
20409 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20410 ((INSTANCE) == USART2) || \
20411 ((INSTANCE) == USART3) || \
20412 ((INSTANCE) == USART6))
20413
20414 /*********************** UART Instances : IRDA mode ***************************/
20415 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20416 ((INSTANCE) == USART2) || \
20417 ((INSTANCE) == USART3) || \
20418 ((INSTANCE) == UART4) || \
20419 ((INSTANCE) == UART5) || \
20420 ((INSTANCE) == USART6) || \
20421 ((INSTANCE) == UART7) || \
20422 ((INSTANCE) == UART8))
20423
20424 /*********************** PCD Instances ****************************************/
20425 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20426 ((INSTANCE) == USB_OTG_HS))
20427
20428 /*********************** HCD Instances ****************************************/
20429 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20430 ((INSTANCE) == USB_OTG_HS))
20431
20432 /****************************** SDIO Instances ********************************/
20433 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
20434
20435 /****************************** IWDG Instances ********************************/
20436 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
20437
20438 /****************************** WWDG Instances ********************************/
20439 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
20440
20441
20442 /****************************** QSPI Instances ********************************/
20443 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
20444 /****************************** USB Exported Constants ************************/
20445 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
20446 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
20447 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
20448 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
20449 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
20450 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
20451 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
20452 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
20453
20454 /*
20455 * @brief Specific devices reset values definitions
20456 */
20457 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
20458 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
20459 #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
20460
20461 #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
20462 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
20463 #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
20464 #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
20465 #define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
20466 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
20467 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
20468 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
20469
20470 #define RCC_PLLN_MIN_VALUE 50U
20471 #define RCC_PLLN_MAX_VALUE 432U
20472
20473 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
20474 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
20475 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
20476 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
20477 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
20478
20479 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
20480 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
20481 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
20482 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
20483 #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
20484
20485 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
20486 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
20487 #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
20488
20489 /******************************************************************************/
20490 /* For a painless codes migration between the STM32F4xx device product */
20491 /* lines, the aliases defined below are put in place to overcome the */
20492 /* differences in the interrupt handlers and IRQn definitions. */
20493 /* No need to update developed interrupt code when moving across */
20494 /* product lines within the same STM32F4 Family */
20495 /******************************************************************************/
20496 /* Aliases for __IRQn */
20497 #define FSMC_IRQn FMC_IRQn
20498
20499 /* Aliases for __IRQHandler */
20500 #define FSMC_IRQHandler FMC_IRQHandler
20501
20502 /**
20503 * @}
20504 */
20505
20506 /**
20507 * @}
20508 */
20509
20510 /**
20511 * @}
20512 */
20513
20514 #ifdef __cplusplus
20515 }
20516 #endif /* __cplusplus */
20517
20518 #endif /* __STM32F479xx_H */
20519
20520
20521
20522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/