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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f437xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F437xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - peripherals registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f437xx
47 * @{
48 */
49
50 #ifndef __STM32F437xx_H
51 #define __STM32F437xx_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #define __FPU_PRESENT 1U /*!< FPU present */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78 /**
79 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
87 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
88 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
89 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
91 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
92 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
93 /****** STM32 specific Interrupt Numbers **********************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
99 RCC_IRQn = 5, /*!< RCC global Interrupt */
100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
112 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
113 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
114 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
115 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
116 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
133 USART3_IRQn = 39, /*!< USART3 global Interrupt */
134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
137 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
138 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
139 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
140 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
141 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
142 FMC_IRQn = 48, /*!< FMC global Interrupt */
143 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
144 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
149 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
150 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
151 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
152 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
153 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
154 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
155 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
156 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
157 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
158 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
159 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
160 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
162 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
163 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
164 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
165 USART6_IRQn = 71, /*!< USART6 global interrupt */
166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
168 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
169 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
170 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
171 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
172 DCMI_IRQn = 78, /*!< DCMI global interrupt */
173 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
174 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
175 FPU_IRQn = 81, /*!< FPU global interrupt */
176 UART7_IRQn = 82, /*!< UART7 global interrupt */
177 UART8_IRQn = 83, /*!< UART8 global interrupt */
178 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
179 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
180 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
181 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
182 DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
183 } IRQn_Type;
184
185 /**
186 * @}
187 */
188
189 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
190 #include "system_stm32f4xx.h"
191 #include <stdint.h>
192
193 /** @addtogroup Peripheral_registers_structures
194 * @{
195 */
196
197 /**
198 * @brief Analog to Digital Converter
199 */
200
201 typedef struct
202 {
203 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
204 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
205 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
206 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
207 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
208 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
209 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
210 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
211 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
212 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
213 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
214 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
215 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
216 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
217 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
218 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
219 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
220 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
221 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
222 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
223 } ADC_TypeDef;
224
225 typedef struct
226 {
227 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
228 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
229 __IO uint32_t CDR; /*!< ADC common regular data register for dual
230 AND triple modes, Address offset: ADC1 base address + 0x308 */
231 } ADC_Common_TypeDef;
232
233
234 /**
235 * @brief Controller Area Network TxMailBox
236 */
237
238 typedef struct
239 {
240 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
241 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
242 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
243 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
244 } CAN_TxMailBox_TypeDef;
245
246 /**
247 * @brief Controller Area Network FIFOMailBox
248 */
249
250 typedef struct
251 {
252 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
253 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
254 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
255 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
256 } CAN_FIFOMailBox_TypeDef;
257
258 /**
259 * @brief Controller Area Network FilterRegister
260 */
261
262 typedef struct
263 {
264 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
265 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
266 } CAN_FilterRegister_TypeDef;
267
268 /**
269 * @brief Controller Area Network
270 */
271
272 typedef struct
273 {
274 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
275 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
276 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
277 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
278 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
279 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
280 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
281 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
282 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
283 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
284 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
285 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
286 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
287 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
288 uint32_t RESERVED2; /*!< Reserved, 0x208 */
289 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
290 uint32_t RESERVED3; /*!< Reserved, 0x210 */
291 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
292 uint32_t RESERVED4; /*!< Reserved, 0x218 */
293 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
294 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
295 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
296 } CAN_TypeDef;
297
298 /**
299 * @brief CRC calculation unit
300 */
301
302 typedef struct
303 {
304 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
305 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
306 uint8_t RESERVED0; /*!< Reserved, 0x05 */
307 uint16_t RESERVED1; /*!< Reserved, 0x06 */
308 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
309 } CRC_TypeDef;
310
311 /**
312 * @brief Digital to Analog Converter
313 */
314
315 typedef struct
316 {
317 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
318 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
319 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
320 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
321 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
322 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
323 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
324 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
325 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
326 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
327 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
328 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
329 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
330 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
331 } DAC_TypeDef;
332
333 /**
334 * @brief Debug MCU
335 */
336
337 typedef struct
338 {
339 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
340 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
341 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
342 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
343 }DBGMCU_TypeDef;
344
345 /**
346 * @brief DCMI
347 */
348
349 typedef struct
350 {
351 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
352 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
353 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
354 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
355 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
356 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
357 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
358 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
359 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
360 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
361 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
362 } DCMI_TypeDef;
363
364 /**
365 * @brief DMA Controller
366 */
367
368 typedef struct
369 {
370 __IO uint32_t CR; /*!< DMA stream x configuration register */
371 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
372 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
373 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
374 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
375 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
376 } DMA_Stream_TypeDef;
377
378 typedef struct
379 {
380 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
381 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
382 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
383 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
384 } DMA_TypeDef;
385
386 /**
387 * @brief DMA2D Controller
388 */
389
390 typedef struct
391 {
392 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
393 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
394 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
395 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
396 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
397 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
398 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
399 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
400 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
401 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
402 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
403 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
404 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
405 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
406 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
407 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
408 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
409 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
410 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
411 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
412 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
413 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
414 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
415 } DMA2D_TypeDef;
416
417 /**
418 * @brief Ethernet MAC
419 */
420
421 typedef struct
422 {
423 __IO uint32_t MACCR;
424 __IO uint32_t MACFFR;
425 __IO uint32_t MACHTHR;
426 __IO uint32_t MACHTLR;
427 __IO uint32_t MACMIIAR;
428 __IO uint32_t MACMIIDR;
429 __IO uint32_t MACFCR;
430 __IO uint32_t MACVLANTR; /* 8 */
431 uint32_t RESERVED0[2];
432 __IO uint32_t MACRWUFFR; /* 11 */
433 __IO uint32_t MACPMTCSR;
434 uint32_t RESERVED1;
435 __IO uint32_t MACDBGR;
436 __IO uint32_t MACSR; /* 15 */
437 __IO uint32_t MACIMR;
438 __IO uint32_t MACA0HR;
439 __IO uint32_t MACA0LR;
440 __IO uint32_t MACA1HR;
441 __IO uint32_t MACA1LR;
442 __IO uint32_t MACA2HR;
443 __IO uint32_t MACA2LR;
444 __IO uint32_t MACA3HR;
445 __IO uint32_t MACA3LR; /* 24 */
446 uint32_t RESERVED2[40];
447 __IO uint32_t MMCCR; /* 65 */
448 __IO uint32_t MMCRIR;
449 __IO uint32_t MMCTIR;
450 __IO uint32_t MMCRIMR;
451 __IO uint32_t MMCTIMR; /* 69 */
452 uint32_t RESERVED3[14];
453 __IO uint32_t MMCTGFSCCR; /* 84 */
454 __IO uint32_t MMCTGFMSCCR;
455 uint32_t RESERVED4[5];
456 __IO uint32_t MMCTGFCR;
457 uint32_t RESERVED5[10];
458 __IO uint32_t MMCRFCECR;
459 __IO uint32_t MMCRFAECR;
460 uint32_t RESERVED6[10];
461 __IO uint32_t MMCRGUFCR;
462 uint32_t RESERVED7[334];
463 __IO uint32_t PTPTSCR;
464 __IO uint32_t PTPSSIR;
465 __IO uint32_t PTPTSHR;
466 __IO uint32_t PTPTSLR;
467 __IO uint32_t PTPTSHUR;
468 __IO uint32_t PTPTSLUR;
469 __IO uint32_t PTPTSAR;
470 __IO uint32_t PTPTTHR;
471 __IO uint32_t PTPTTLR;
472 __IO uint32_t RESERVED8;
473 __IO uint32_t PTPTSSR;
474 uint32_t RESERVED9[565];
475 __IO uint32_t DMABMR;
476 __IO uint32_t DMATPDR;
477 __IO uint32_t DMARPDR;
478 __IO uint32_t DMARDLAR;
479 __IO uint32_t DMATDLAR;
480 __IO uint32_t DMASR;
481 __IO uint32_t DMAOMR;
482 __IO uint32_t DMAIER;
483 __IO uint32_t DMAMFBOCR;
484 __IO uint32_t DMARSWTR;
485 uint32_t RESERVED10[8];
486 __IO uint32_t DMACHTDR;
487 __IO uint32_t DMACHRDR;
488 __IO uint32_t DMACHTBAR;
489 __IO uint32_t DMACHRBAR;
490 } ETH_TypeDef;
491
492 /**
493 * @brief External Interrupt/Event Controller
494 */
495
496 typedef struct
497 {
498 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
499 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
500 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
501 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
502 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
503 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
504 } EXTI_TypeDef;
505
506 /**
507 * @brief FLASH Registers
508 */
509
510 typedef struct
511 {
512 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
513 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
514 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
515 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
516 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
517 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
518 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
519 } FLASH_TypeDef;
520
521 /**
522 * @brief Flexible Memory Controller
523 */
524
525 typedef struct
526 {
527 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
528 } FMC_Bank1_TypeDef;
529
530 /**
531 * @brief Flexible Memory Controller Bank1E
532 */
533
534 typedef struct
535 {
536 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
537 } FMC_Bank1E_TypeDef;
538 /**
539 * @brief Flexible Memory Controller Bank2
540 */
541
542 typedef struct
543 {
544 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
545 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
546 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
547 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
548 uint32_t RESERVED0; /*!< Reserved, 0x70 */
549 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
550 uint32_t RESERVED1; /*!< Reserved, 0x78 */
551 uint32_t RESERVED2; /*!< Reserved, 0x7C */
552 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
553 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
554 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
555 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
556 uint32_t RESERVED3; /*!< Reserved, 0x90 */
557 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
558 } FMC_Bank2_3_TypeDef;
559
560 /**
561 * @brief Flexible Memory Controller Bank4
562 */
563
564 typedef struct
565 {
566 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
567 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
568 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
569 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
570 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
571 } FMC_Bank4_TypeDef;
572
573 /**
574 * @brief Flexible Memory Controller Bank5_6
575 */
576
577 typedef struct
578 {
579 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
580 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
581 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
582 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
583 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
584 } FMC_Bank5_6_TypeDef;
585
586 /**
587 * @brief General Purpose I/O
588 */
589
590 typedef struct
591 {
592 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
593 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
594 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
595 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
596 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
597 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
598 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
599 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
600 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
601 } GPIO_TypeDef;
602
603 /**
604 * @brief System configuration controller
605 */
606
607 typedef struct
608 {
609 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
610 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
611 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
612 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
613 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
614 } SYSCFG_TypeDef;
615
616 /**
617 * @brief Inter-integrated Circuit Interface
618 */
619
620 typedef struct
621 {
622 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
623 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
624 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
625 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
626 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
627 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
628 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
629 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
630 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
631 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
632 } I2C_TypeDef;
633
634 /**
635 * @brief Independent WATCHDOG
636 */
637
638 typedef struct
639 {
640 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
641 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
642 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
643 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
644 } IWDG_TypeDef;
645
646
647 /**
648 * @brief Power Control
649 */
650
651 typedef struct
652 {
653 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
654 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
655 } PWR_TypeDef;
656
657 /**
658 * @brief Reset and Clock Control
659 */
660
661 typedef struct
662 {
663 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
664 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
665 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
666 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
667 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
668 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
669 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
670 uint32_t RESERVED0; /*!< Reserved, 0x1C */
671 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
672 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
673 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
674 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
675 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
676 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
677 uint32_t RESERVED2; /*!< Reserved, 0x3C */
678 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
679 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
680 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
681 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
682 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
683 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
684 uint32_t RESERVED4; /*!< Reserved, 0x5C */
685 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
686 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
687 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
688 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
689 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
690 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
691 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
692 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
693 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
694 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
695 } RCC_TypeDef;
696
697 /**
698 * @brief Real-Time Clock
699 */
700
701 typedef struct
702 {
703 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
704 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
705 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
706 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
707 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
708 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
709 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
710 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
711 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
712 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
713 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
714 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
715 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
716 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
717 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
718 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
719 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
720 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
721 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
722 uint32_t RESERVED7; /*!< Reserved, 0x4C */
723 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
724 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
725 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
726 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
727 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
728 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
729 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
730 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
731 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
732 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
733 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
734 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
735 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
736 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
737 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
738 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
739 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
740 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
741 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
742 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
743 } RTC_TypeDef;
744
745 /**
746 * @brief Serial Audio Interface
747 */
748
749 typedef struct
750 {
751 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
752 } SAI_TypeDef;
753
754 typedef struct
755 {
756 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
757 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
758 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
759 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
760 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
761 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
762 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
763 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
764 } SAI_Block_TypeDef;
765
766 /**
767 * @brief SD host Interface
768 */
769
770 typedef struct
771 {
772 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
773 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
774 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
775 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
776 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
777 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
778 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
779 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
780 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
781 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
782 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
783 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
784 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
785 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
786 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
787 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
788 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
789 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
790 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
791 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
792 } SDIO_TypeDef;
793
794 /**
795 * @brief Serial Peripheral Interface
796 */
797
798 typedef struct
799 {
800 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
801 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
802 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
803 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
804 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
805 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
806 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
807 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
808 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
809 } SPI_TypeDef;
810
811
812 /**
813 * @brief TIM
814 */
815
816 typedef struct
817 {
818 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
819 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
820 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
821 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
822 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
823 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
824 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
825 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
826 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
827 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
828 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
829 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
830 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
831 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
832 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
833 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
834 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
835 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
836 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
837 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
838 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
839 } TIM_TypeDef;
840
841 /**
842 * @brief Universal Synchronous Asynchronous Receiver Transmitter
843 */
844
845 typedef struct
846 {
847 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
848 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
849 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
850 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
851 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
852 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
853 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
854 } USART_TypeDef;
855
856 /**
857 * @brief Window WATCHDOG
858 */
859
860 typedef struct
861 {
862 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
863 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
864 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
865 } WWDG_TypeDef;
866
867 /**
868 * @brief Crypto Processor
869 */
870
871 typedef struct
872 {
873 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
874 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
875 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
876 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
877 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
878 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
879 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
880 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
881 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
882 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
883 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
884 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
885 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
886 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
887 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
888 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
889 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
890 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
891 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
892 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
893 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
894 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
895 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
896 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
897 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
898 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
899 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
900 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
901 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
902 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
903 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
904 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
905 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
906 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
907 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
908 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
909 } CRYP_TypeDef;
910
911 /**
912 * @brief HASH
913 */
914
915 typedef struct
916 {
917 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
918 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
919 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
920 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
921 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
922 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
923 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
924 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
925 } HASH_TypeDef;
926
927 /**
928 * @brief HASH_DIGEST
929 */
930
931 typedef struct
932 {
933 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
934 } HASH_DIGEST_TypeDef;
935
936 /**
937 * @brief RNG
938 */
939
940 typedef struct
941 {
942 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
943 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
944 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
945 } RNG_TypeDef;
946
947 /**
948 * @brief USB_OTG_Core_Registers
949 */
950 typedef struct
951 {
952 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
953 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
954 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
955 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
956 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
957 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
958 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
959 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
960 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
961 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
962 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
963 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
964 uint32_t Reserved30[2]; /*!< Reserved 030h */
965 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
966 __IO uint32_t CID; /*!< User ID Register 03Ch */
967 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
968 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
969 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
970 } USB_OTG_GlobalTypeDef;
971
972 /**
973 * @brief USB_OTG_device_Registers
974 */
975 typedef struct
976 {
977 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
978 __IO uint32_t DCTL; /*!< dev Control Register 804h */
979 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
980 uint32_t Reserved0C; /*!< Reserved 80Ch */
981 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
982 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
983 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
984 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
985 uint32_t Reserved20; /*!< Reserved 820h */
986 uint32_t Reserved9; /*!< Reserved 824h */
987 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
988 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
989 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
990 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
991 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
992 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
993 uint32_t Reserved40; /*!< dedicated EP mask 840h */
994 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
995 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
996 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
997 } USB_OTG_DeviceTypeDef;
998
999 /**
1000 * @brief USB_OTG_IN_Endpoint-Specific_Register
1001 */
1002 typedef struct
1003 {
1004 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1005 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1006 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1007 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1008 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1009 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1010 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1011 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1012 } USB_OTG_INEndpointTypeDef;
1013
1014 /**
1015 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1016 */
1017 typedef struct
1018 {
1019 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1020 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1021 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1022 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1023 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1024 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1025 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1026 } USB_OTG_OUTEndpointTypeDef;
1027
1028 /**
1029 * @brief USB_OTG_Host_Mode_Register_Structures
1030 */
1031 typedef struct
1032 {
1033 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1034 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1035 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1036 uint32_t Reserved40C; /*!< Reserved 40Ch */
1037 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1038 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1039 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1040 } USB_OTG_HostTypeDef;
1041
1042 /**
1043 * @brief USB_OTG_Host_Channel_Specific_Registers
1044 */
1045 typedef struct
1046 {
1047 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1048 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1049 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1050 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1051 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1052 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1053 uint32_t Reserved[2]; /*!< Reserved */
1054 } USB_OTG_HostChannelTypeDef;
1055
1056 /**
1057 * @}
1058 */
1059
1060 /** @addtogroup Peripheral_memory_map
1061 * @{
1062 */
1063 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
1064 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
1065 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
1066 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
1067 #define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
1068 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
1069 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
1070 #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
1071 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
1072 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
1073 #define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
1074 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
1075 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
1076 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
1077 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
1078 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
1079 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
1080
1081 /* Legacy defines */
1082 #define SRAM_BASE SRAM1_BASE
1083 #define SRAM_BB_BASE SRAM1_BB_BASE
1084
1085 /*!< Peripheral memory map */
1086 #define APB1PERIPH_BASE PERIPH_BASE
1087 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1088 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1089 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1090
1091 /*!< APB1 peripherals */
1092 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1093 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1094 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1095 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1096 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1097 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1098 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1099 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1100 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1101 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1102 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1103 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1104 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1105 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1106 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1107 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1108 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1109 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1110 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1111 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1112 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1113 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1114 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1115 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1116 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1117 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1118 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1119 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1120 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1121
1122 /*!< APB2 peripherals */
1123 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1124 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1125 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1126 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1127 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1128 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1129 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1130 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
1131 /* Legacy define */
1132 #define ADC_BASE ADC123_COMMON_BASE
1133 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1134 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1135 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1136 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1137 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1138 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1139 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1140 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1141 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1142 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1143 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1144 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1145 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1146
1147 /*!< AHB1 peripherals */
1148 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1149 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1150 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1151 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1152 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1153 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1154 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1155 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1156 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1157 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1158 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1159 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1160 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1161 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1162 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1163 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1164 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1165 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1166 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1167 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1168 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1169 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1170 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1171 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1172 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1173 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1174 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1175 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1176 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1177 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1178 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1179 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1180 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1181 #define ETH_MAC_BASE (ETH_BASE)
1182 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1183 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1184 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1185 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1186
1187 /*!< AHB2 peripherals */
1188 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1189 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1190 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1191 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1192 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1193
1194 /*!< FMC Bankx registers base address */
1195 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1196 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1197 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
1198 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
1199 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1200
1201
1202 /*!< Debug MCU registers base address */
1203 #define DBGMCU_BASE 0xE0042000U
1204 /*!< USB registers base address */
1205 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1206 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1207
1208 #define USB_OTG_GLOBAL_BASE 0x000U
1209 #define USB_OTG_DEVICE_BASE 0x800U
1210 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1211 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1212 #define USB_OTG_EP_REG_SIZE 0x20U
1213 #define USB_OTG_HOST_BASE 0x400U
1214 #define USB_OTG_HOST_PORT_BASE 0x440U
1215 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1216 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1217 #define USB_OTG_PCGCCTL_BASE 0xE00U
1218 #define USB_OTG_FIFO_BASE 0x1000U
1219 #define USB_OTG_FIFO_SIZE 0x1000U
1220
1221 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
1222 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
1223 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1224 /**
1225 * @}
1226 */
1227
1228 /** @addtogroup Peripheral_declaration
1229 * @{
1230 */
1231 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1232 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1233 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1234 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1235 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1236 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1237 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1238 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1239 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1240 #define RTC ((RTC_TypeDef *) RTC_BASE)
1241 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1242 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1243 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1244 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1245 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1246 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1247 #define USART2 ((USART_TypeDef *) USART2_BASE)
1248 #define USART3 ((USART_TypeDef *) USART3_BASE)
1249 #define UART4 ((USART_TypeDef *) UART4_BASE)
1250 #define UART5 ((USART_TypeDef *) UART5_BASE)
1251 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1252 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1253 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1254 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1255 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1256 #define PWR ((PWR_TypeDef *) PWR_BASE)
1257 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1258 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1259 #define UART7 ((USART_TypeDef *) UART7_BASE)
1260 #define UART8 ((USART_TypeDef *) UART8_BASE)
1261 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1262 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1263 #define USART1 ((USART_TypeDef *) USART1_BASE)
1264 #define USART6 ((USART_TypeDef *) USART6_BASE)
1265 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1266 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1267 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1268 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1269 /* Legacy define */
1270 #define ADC ADC123_COMMON
1271 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1272 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1273 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1274 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1275 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1276 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1277 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1278 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1279 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1280 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1281 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1282 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1283 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1284 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1285 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1286 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1287 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1288 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1289 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1290 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1291 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1292 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1293 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1294 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1295 #define CRC ((CRC_TypeDef *) CRC_BASE)
1296 #define RCC ((RCC_TypeDef *) RCC_BASE)
1297 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1298 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1299 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1300 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1301 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1302 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1303 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1304 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1305 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1306 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1307 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1308 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1309 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1310 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1311 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1312 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1313 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1314 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1315 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1316 #define ETH ((ETH_TypeDef *) ETH_BASE)
1317 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1318 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1319 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1320 #define HASH ((HASH_TypeDef *) HASH_BASE)
1321 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1322 #define RNG ((RNG_TypeDef *) RNG_BASE)
1323 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1324 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1325 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1326 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1327 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1328 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1329 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1330 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1331
1332 /**
1333 * @}
1334 */
1335
1336 /** @addtogroup Exported_constants
1337 * @{
1338 */
1339
1340 /** @addtogroup Peripheral_Registers_Bits_Definition
1341 * @{
1342 */
1343
1344 /******************************************************************************/
1345 /* Peripheral Registers_Bits_Definition */
1346 /******************************************************************************/
1347
1348 /******************************************************************************/
1349 /* */
1350 /* Analog to Digital Converter */
1351 /* */
1352 /******************************************************************************/
1353 /*
1354 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1355 */
1356 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
1357
1358 /******************** Bit definition for ADC_SR register ********************/
1359 #define ADC_SR_AWD_Pos (0U)
1360 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1361 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1362 #define ADC_SR_EOC_Pos (1U)
1363 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1364 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1365 #define ADC_SR_JEOC_Pos (2U)
1366 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1367 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1368 #define ADC_SR_JSTRT_Pos (3U)
1369 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1370 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1371 #define ADC_SR_STRT_Pos (4U)
1372 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1373 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1374 #define ADC_SR_OVR_Pos (5U)
1375 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1376 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1377
1378 /******************* Bit definition for ADC_CR1 register ********************/
1379 #define ADC_CR1_AWDCH_Pos (0U)
1380 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1381 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1382 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1383 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1384 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1385 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1386 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1387 #define ADC_CR1_EOCIE_Pos (5U)
1388 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1389 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1390 #define ADC_CR1_AWDIE_Pos (6U)
1391 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1392 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1393 #define ADC_CR1_JEOCIE_Pos (7U)
1394 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1395 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1396 #define ADC_CR1_SCAN_Pos (8U)
1397 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1398 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1399 #define ADC_CR1_AWDSGL_Pos (9U)
1400 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1401 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1402 #define ADC_CR1_JAUTO_Pos (10U)
1403 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1404 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1405 #define ADC_CR1_DISCEN_Pos (11U)
1406 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1407 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1408 #define ADC_CR1_JDISCEN_Pos (12U)
1409 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1410 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1411 #define ADC_CR1_DISCNUM_Pos (13U)
1412 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1413 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1414 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1415 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1416 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1417 #define ADC_CR1_JAWDEN_Pos (22U)
1418 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1419 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1420 #define ADC_CR1_AWDEN_Pos (23U)
1421 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1422 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1423 #define ADC_CR1_RES_Pos (24U)
1424 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1425 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1426 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1427 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1428 #define ADC_CR1_OVRIE_Pos (26U)
1429 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1430 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1431
1432 /******************* Bit definition for ADC_CR2 register ********************/
1433 #define ADC_CR2_ADON_Pos (0U)
1434 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1435 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1436 #define ADC_CR2_CONT_Pos (1U)
1437 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1438 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1439 #define ADC_CR2_DMA_Pos (8U)
1440 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1441 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1442 #define ADC_CR2_DDS_Pos (9U)
1443 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1444 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1445 #define ADC_CR2_EOCS_Pos (10U)
1446 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1447 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1448 #define ADC_CR2_ALIGN_Pos (11U)
1449 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1450 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1451 #define ADC_CR2_JEXTSEL_Pos (16U)
1452 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1453 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1454 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1455 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1456 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1457 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1458 #define ADC_CR2_JEXTEN_Pos (20U)
1459 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1460 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1461 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1462 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1463 #define ADC_CR2_JSWSTART_Pos (22U)
1464 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1465 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1466 #define ADC_CR2_EXTSEL_Pos (24U)
1467 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1468 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1469 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1470 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1471 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1472 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1473 #define ADC_CR2_EXTEN_Pos (28U)
1474 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1475 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1476 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1477 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1478 #define ADC_CR2_SWSTART_Pos (30U)
1479 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1480 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1481
1482 /****************** Bit definition for ADC_SMPR1 register *******************/
1483 #define ADC_SMPR1_SMP10_Pos (0U)
1484 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1485 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1486 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1487 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1488 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1489 #define ADC_SMPR1_SMP11_Pos (3U)
1490 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1491 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1492 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1493 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1494 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1495 #define ADC_SMPR1_SMP12_Pos (6U)
1496 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1497 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1498 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1499 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1500 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1501 #define ADC_SMPR1_SMP13_Pos (9U)
1502 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1503 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1504 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1505 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1506 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1507 #define ADC_SMPR1_SMP14_Pos (12U)
1508 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1509 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1510 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1511 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1512 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1513 #define ADC_SMPR1_SMP15_Pos (15U)
1514 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1515 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1516 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1517 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1518 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1519 #define ADC_SMPR1_SMP16_Pos (18U)
1520 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1521 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1522 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1523 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1524 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1525 #define ADC_SMPR1_SMP17_Pos (21U)
1526 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1527 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1528 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1529 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1530 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1531 #define ADC_SMPR1_SMP18_Pos (24U)
1532 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1533 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1534 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1535 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1536 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1537
1538 /****************** Bit definition for ADC_SMPR2 register *******************/
1539 #define ADC_SMPR2_SMP0_Pos (0U)
1540 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1541 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1542 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1543 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1544 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1545 #define ADC_SMPR2_SMP1_Pos (3U)
1546 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1547 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1548 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1549 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1550 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1551 #define ADC_SMPR2_SMP2_Pos (6U)
1552 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1553 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1554 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1555 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1556 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1557 #define ADC_SMPR2_SMP3_Pos (9U)
1558 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1559 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1560 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1561 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1562 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1563 #define ADC_SMPR2_SMP4_Pos (12U)
1564 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1565 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1566 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1567 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1568 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1569 #define ADC_SMPR2_SMP5_Pos (15U)
1570 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1571 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1572 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1573 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1574 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1575 #define ADC_SMPR2_SMP6_Pos (18U)
1576 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1577 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1578 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1579 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1580 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1581 #define ADC_SMPR2_SMP7_Pos (21U)
1582 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1583 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1584 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1585 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1586 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1587 #define ADC_SMPR2_SMP8_Pos (24U)
1588 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1589 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1590 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1591 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1592 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1593 #define ADC_SMPR2_SMP9_Pos (27U)
1594 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1595 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1596 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1597 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1598 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1599
1600 /****************** Bit definition for ADC_JOFR1 register *******************/
1601 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1602 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1603 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1604
1605 /****************** Bit definition for ADC_JOFR2 register *******************/
1606 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1607 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1608 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1609
1610 /****************** Bit definition for ADC_JOFR3 register *******************/
1611 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1612 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1613 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1614
1615 /****************** Bit definition for ADC_JOFR4 register *******************/
1616 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1617 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1618 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1619
1620 /******************* Bit definition for ADC_HTR register ********************/
1621 #define ADC_HTR_HT_Pos (0U)
1622 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1623 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1624
1625 /******************* Bit definition for ADC_LTR register ********************/
1626 #define ADC_LTR_LT_Pos (0U)
1627 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1628 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1629
1630 /******************* Bit definition for ADC_SQR1 register *******************/
1631 #define ADC_SQR1_SQ13_Pos (0U)
1632 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1633 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1634 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1635 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1636 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1637 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1638 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1639 #define ADC_SQR1_SQ14_Pos (5U)
1640 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1641 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1642 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1643 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1644 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1645 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1646 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1647 #define ADC_SQR1_SQ15_Pos (10U)
1648 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1649 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1650 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1651 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1652 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1653 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1654 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1655 #define ADC_SQR1_SQ16_Pos (15U)
1656 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1657 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1658 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1659 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1660 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1661 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1662 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1663 #define ADC_SQR1_L_Pos (20U)
1664 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1665 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1666 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1667 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1668 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1669 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1670
1671 /******************* Bit definition for ADC_SQR2 register *******************/
1672 #define ADC_SQR2_SQ7_Pos (0U)
1673 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1674 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1675 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1676 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1677 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1678 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1679 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1680 #define ADC_SQR2_SQ8_Pos (5U)
1681 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1682 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1683 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1684 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1685 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1686 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1687 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1688 #define ADC_SQR2_SQ9_Pos (10U)
1689 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1690 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1691 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1692 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1693 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1694 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1695 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1696 #define ADC_SQR2_SQ10_Pos (15U)
1697 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1698 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1699 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1700 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1701 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1702 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1703 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1704 #define ADC_SQR2_SQ11_Pos (20U)
1705 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1706 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1707 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1708 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1709 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1710 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1711 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1712 #define ADC_SQR2_SQ12_Pos (25U)
1713 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1714 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1715 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1716 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1717 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1718 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1719 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1720
1721 /******************* Bit definition for ADC_SQR3 register *******************/
1722 #define ADC_SQR3_SQ1_Pos (0U)
1723 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1724 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1725 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1726 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1727 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1728 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1729 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1730 #define ADC_SQR3_SQ2_Pos (5U)
1731 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1732 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1733 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1734 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1735 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1736 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1737 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1738 #define ADC_SQR3_SQ3_Pos (10U)
1739 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1740 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1741 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1742 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1743 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1744 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1745 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1746 #define ADC_SQR3_SQ4_Pos (15U)
1747 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1748 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1749 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1750 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1751 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1752 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1753 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1754 #define ADC_SQR3_SQ5_Pos (20U)
1755 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1756 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1757 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1758 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1759 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1760 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1761 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1762 #define ADC_SQR3_SQ6_Pos (25U)
1763 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1764 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1765 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1766 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1767 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1768 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1769 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1770
1771 /******************* Bit definition for ADC_JSQR register *******************/
1772 #define ADC_JSQR_JSQ1_Pos (0U)
1773 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1774 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1775 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1776 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1777 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1778 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1779 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1780 #define ADC_JSQR_JSQ2_Pos (5U)
1781 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1782 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1783 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1784 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1785 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1786 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1787 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1788 #define ADC_JSQR_JSQ3_Pos (10U)
1789 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1790 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1791 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1792 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1793 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1794 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1795 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1796 #define ADC_JSQR_JSQ4_Pos (15U)
1797 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1798 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1799 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1800 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1801 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1802 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1803 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1804 #define ADC_JSQR_JL_Pos (20U)
1805 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1806 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1807 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1808 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1809
1810 /******************* Bit definition for ADC_JDR1 register *******************/
1811 #define ADC_JDR1_JDATA_Pos (0U)
1812 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1813 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1814
1815 /******************* Bit definition for ADC_JDR2 register *******************/
1816 #define ADC_JDR2_JDATA_Pos (0U)
1817 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1818 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1819
1820 /******************* Bit definition for ADC_JDR3 register *******************/
1821 #define ADC_JDR3_JDATA_Pos (0U)
1822 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1823 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1824
1825 /******************* Bit definition for ADC_JDR4 register *******************/
1826 #define ADC_JDR4_JDATA_Pos (0U)
1827 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1828 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1829
1830 /******************** Bit definition for ADC_DR register ********************/
1831 #define ADC_DR_DATA_Pos (0U)
1832 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1833 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1834 #define ADC_DR_ADC2DATA_Pos (16U)
1835 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1836 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1837
1838 /******************* Bit definition for ADC_CSR register ********************/
1839 #define ADC_CSR_AWD1_Pos (0U)
1840 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1841 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1842 #define ADC_CSR_EOC1_Pos (1U)
1843 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1844 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1845 #define ADC_CSR_JEOC1_Pos (2U)
1846 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1847 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1848 #define ADC_CSR_JSTRT1_Pos (3U)
1849 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1850 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1851 #define ADC_CSR_STRT1_Pos (4U)
1852 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1853 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1854 #define ADC_CSR_OVR1_Pos (5U)
1855 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1856 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1857 #define ADC_CSR_AWD2_Pos (8U)
1858 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
1859 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
1860 #define ADC_CSR_EOC2_Pos (9U)
1861 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
1862 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
1863 #define ADC_CSR_JEOC2_Pos (10U)
1864 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
1865 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
1866 #define ADC_CSR_JSTRT2_Pos (11U)
1867 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
1868 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
1869 #define ADC_CSR_STRT2_Pos (12U)
1870 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
1871 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
1872 #define ADC_CSR_OVR2_Pos (13U)
1873 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
1874 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
1875 #define ADC_CSR_AWD3_Pos (16U)
1876 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
1877 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
1878 #define ADC_CSR_EOC3_Pos (17U)
1879 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
1880 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
1881 #define ADC_CSR_JEOC3_Pos (18U)
1882 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
1883 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
1884 #define ADC_CSR_JSTRT3_Pos (19U)
1885 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
1886 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
1887 #define ADC_CSR_STRT3_Pos (20U)
1888 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
1889 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
1890 #define ADC_CSR_OVR3_Pos (21U)
1891 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
1892 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
1893
1894 /* Legacy defines */
1895 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1896 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1897 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1898
1899 /******************* Bit definition for ADC_CCR register ********************/
1900 #define ADC_CCR_MULTI_Pos (0U)
1901 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1902 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1903 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1904 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1905 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1906 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1907 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1908 #define ADC_CCR_DELAY_Pos (8U)
1909 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1910 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1911 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1912 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1913 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1914 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1915 #define ADC_CCR_DDS_Pos (13U)
1916 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1917 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1918 #define ADC_CCR_DMA_Pos (14U)
1919 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1920 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1921 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1922 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1923 #define ADC_CCR_ADCPRE_Pos (16U)
1924 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1925 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1926 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1927 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1928 #define ADC_CCR_VBATE_Pos (22U)
1929 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1930 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1931 #define ADC_CCR_TSVREFE_Pos (23U)
1932 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1933 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1934
1935 /******************* Bit definition for ADC_CDR register ********************/
1936 #define ADC_CDR_DATA1_Pos (0U)
1937 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1938 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1939 #define ADC_CDR_DATA2_Pos (16U)
1940 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1941 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1942
1943 /* Legacy defines */
1944 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1945 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1946
1947 /******************************************************************************/
1948 /* */
1949 /* Controller Area Network */
1950 /* */
1951 /******************************************************************************/
1952 /*!<CAN control and status registers */
1953 /******************* Bit definition for CAN_MCR register ********************/
1954 #define CAN_MCR_INRQ_Pos (0U)
1955 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
1956 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
1957 #define CAN_MCR_SLEEP_Pos (1U)
1958 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
1959 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
1960 #define CAN_MCR_TXFP_Pos (2U)
1961 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
1962 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
1963 #define CAN_MCR_RFLM_Pos (3U)
1964 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
1965 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
1966 #define CAN_MCR_NART_Pos (4U)
1967 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
1968 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
1969 #define CAN_MCR_AWUM_Pos (5U)
1970 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
1971 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
1972 #define CAN_MCR_ABOM_Pos (6U)
1973 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
1974 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
1975 #define CAN_MCR_TTCM_Pos (7U)
1976 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
1977 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
1978 #define CAN_MCR_RESET_Pos (15U)
1979 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
1980 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
1981 #define CAN_MCR_DBF_Pos (16U)
1982 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
1983 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
1984 /******************* Bit definition for CAN_MSR register ********************/
1985 #define CAN_MSR_INAK_Pos (0U)
1986 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
1987 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
1988 #define CAN_MSR_SLAK_Pos (1U)
1989 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
1990 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
1991 #define CAN_MSR_ERRI_Pos (2U)
1992 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
1993 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
1994 #define CAN_MSR_WKUI_Pos (3U)
1995 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
1996 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
1997 #define CAN_MSR_SLAKI_Pos (4U)
1998 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
1999 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2000 #define CAN_MSR_TXM_Pos (8U)
2001 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2002 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2003 #define CAN_MSR_RXM_Pos (9U)
2004 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2005 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2006 #define CAN_MSR_SAMP_Pos (10U)
2007 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2008 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2009 #define CAN_MSR_RX_Pos (11U)
2010 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2011 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2012
2013 /******************* Bit definition for CAN_TSR register ********************/
2014 #define CAN_TSR_RQCP0_Pos (0U)
2015 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2016 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2017 #define CAN_TSR_TXOK0_Pos (1U)
2018 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2019 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2020 #define CAN_TSR_ALST0_Pos (2U)
2021 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2022 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2023 #define CAN_TSR_TERR0_Pos (3U)
2024 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2025 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2026 #define CAN_TSR_ABRQ0_Pos (7U)
2027 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2028 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2029 #define CAN_TSR_RQCP1_Pos (8U)
2030 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2031 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2032 #define CAN_TSR_TXOK1_Pos (9U)
2033 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2034 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2035 #define CAN_TSR_ALST1_Pos (10U)
2036 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2037 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2038 #define CAN_TSR_TERR1_Pos (11U)
2039 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2040 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2041 #define CAN_TSR_ABRQ1_Pos (15U)
2042 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2043 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2044 #define CAN_TSR_RQCP2_Pos (16U)
2045 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2046 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2047 #define CAN_TSR_TXOK2_Pos (17U)
2048 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2049 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2050 #define CAN_TSR_ALST2_Pos (18U)
2051 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2052 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2053 #define CAN_TSR_TERR2_Pos (19U)
2054 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2055 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2056 #define CAN_TSR_ABRQ2_Pos (23U)
2057 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2058 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2059 #define CAN_TSR_CODE_Pos (24U)
2060 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2061 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2062
2063 #define CAN_TSR_TME_Pos (26U)
2064 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2065 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2066 #define CAN_TSR_TME0_Pos (26U)
2067 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2068 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2069 #define CAN_TSR_TME1_Pos (27U)
2070 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2071 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2072 #define CAN_TSR_TME2_Pos (28U)
2073 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2074 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2075
2076 #define CAN_TSR_LOW_Pos (29U)
2077 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2078 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2079 #define CAN_TSR_LOW0_Pos (29U)
2080 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2081 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2082 #define CAN_TSR_LOW1_Pos (30U)
2083 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2084 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2085 #define CAN_TSR_LOW2_Pos (31U)
2086 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2087 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2088
2089 /******************* Bit definition for CAN_RF0R register *******************/
2090 #define CAN_RF0R_FMP0_Pos (0U)
2091 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2092 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2093 #define CAN_RF0R_FULL0_Pos (3U)
2094 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2095 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2096 #define CAN_RF0R_FOVR0_Pos (4U)
2097 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2098 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2099 #define CAN_RF0R_RFOM0_Pos (5U)
2100 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2101 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2102
2103 /******************* Bit definition for CAN_RF1R register *******************/
2104 #define CAN_RF1R_FMP1_Pos (0U)
2105 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2106 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2107 #define CAN_RF1R_FULL1_Pos (3U)
2108 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2109 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2110 #define CAN_RF1R_FOVR1_Pos (4U)
2111 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2112 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2113 #define CAN_RF1R_RFOM1_Pos (5U)
2114 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2115 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2116
2117 /******************** Bit definition for CAN_IER register *******************/
2118 #define CAN_IER_TMEIE_Pos (0U)
2119 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2120 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2121 #define CAN_IER_FMPIE0_Pos (1U)
2122 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2123 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2124 #define CAN_IER_FFIE0_Pos (2U)
2125 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2126 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2127 #define CAN_IER_FOVIE0_Pos (3U)
2128 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2129 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2130 #define CAN_IER_FMPIE1_Pos (4U)
2131 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2132 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2133 #define CAN_IER_FFIE1_Pos (5U)
2134 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2135 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2136 #define CAN_IER_FOVIE1_Pos (6U)
2137 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2138 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2139 #define CAN_IER_EWGIE_Pos (8U)
2140 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2141 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2142 #define CAN_IER_EPVIE_Pos (9U)
2143 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2144 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2145 #define CAN_IER_BOFIE_Pos (10U)
2146 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2147 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2148 #define CAN_IER_LECIE_Pos (11U)
2149 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2150 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2151 #define CAN_IER_ERRIE_Pos (15U)
2152 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2153 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2154 #define CAN_IER_WKUIE_Pos (16U)
2155 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2156 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2157 #define CAN_IER_SLKIE_Pos (17U)
2158 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2159 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2160 #define CAN_IER_EWGIE_Pos (8U)
2161
2162 /******************** Bit definition for CAN_ESR register *******************/
2163 #define CAN_ESR_EWGF_Pos (0U)
2164 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2165 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2166 #define CAN_ESR_EPVF_Pos (1U)
2167 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2168 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2169 #define CAN_ESR_BOFF_Pos (2U)
2170 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2171 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2172
2173 #define CAN_ESR_LEC_Pos (4U)
2174 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2175 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2176 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2177 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2178 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2179
2180 #define CAN_ESR_TEC_Pos (16U)
2181 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2182 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2183 #define CAN_ESR_REC_Pos (24U)
2184 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2185 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2186
2187 /******************* Bit definition for CAN_BTR register ********************/
2188 #define CAN_BTR_BRP_Pos (0U)
2189 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2190 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2191 #define CAN_BTR_TS1_Pos (16U)
2192 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2193 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2194 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2195 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2196 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2197 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2198 #define CAN_BTR_TS2_Pos (20U)
2199 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2200 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2201 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2202 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2203 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2204 #define CAN_BTR_SJW_Pos (24U)
2205 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2206 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2207 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2208 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2209 #define CAN_BTR_LBKM_Pos (30U)
2210 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2211 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2212 #define CAN_BTR_SILM_Pos (31U)
2213 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2214 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2215
2216
2217 /*!<Mailbox registers */
2218 /****************** Bit definition for CAN_TI0R register ********************/
2219 #define CAN_TI0R_TXRQ_Pos (0U)
2220 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2221 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2222 #define CAN_TI0R_RTR_Pos (1U)
2223 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2224 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2225 #define CAN_TI0R_IDE_Pos (2U)
2226 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2227 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2228 #define CAN_TI0R_EXID_Pos (3U)
2229 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2230 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2231 #define CAN_TI0R_STID_Pos (21U)
2232 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2233 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2234
2235 /****************** Bit definition for CAN_TDT0R register *******************/
2236 #define CAN_TDT0R_DLC_Pos (0U)
2237 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2238 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2239 #define CAN_TDT0R_TGT_Pos (8U)
2240 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2241 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2242 #define CAN_TDT0R_TIME_Pos (16U)
2243 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2244 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2245
2246 /****************** Bit definition for CAN_TDL0R register *******************/
2247 #define CAN_TDL0R_DATA0_Pos (0U)
2248 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2249 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2250 #define CAN_TDL0R_DATA1_Pos (8U)
2251 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2252 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2253 #define CAN_TDL0R_DATA2_Pos (16U)
2254 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2255 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2256 #define CAN_TDL0R_DATA3_Pos (24U)
2257 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2258 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2259
2260 /****************** Bit definition for CAN_TDH0R register *******************/
2261 #define CAN_TDH0R_DATA4_Pos (0U)
2262 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2263 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2264 #define CAN_TDH0R_DATA5_Pos (8U)
2265 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2266 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2267 #define CAN_TDH0R_DATA6_Pos (16U)
2268 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2269 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2270 #define CAN_TDH0R_DATA7_Pos (24U)
2271 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2272 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2273
2274 /******************* Bit definition for CAN_TI1R register *******************/
2275 #define CAN_TI1R_TXRQ_Pos (0U)
2276 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2277 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2278 #define CAN_TI1R_RTR_Pos (1U)
2279 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2280 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2281 #define CAN_TI1R_IDE_Pos (2U)
2282 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2283 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2284 #define CAN_TI1R_EXID_Pos (3U)
2285 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2286 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2287 #define CAN_TI1R_STID_Pos (21U)
2288 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2289 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2290
2291 /******************* Bit definition for CAN_TDT1R register ******************/
2292 #define CAN_TDT1R_DLC_Pos (0U)
2293 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2294 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2295 #define CAN_TDT1R_TGT_Pos (8U)
2296 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2297 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2298 #define CAN_TDT1R_TIME_Pos (16U)
2299 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2300 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2301
2302 /******************* Bit definition for CAN_TDL1R register ******************/
2303 #define CAN_TDL1R_DATA0_Pos (0U)
2304 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2305 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2306 #define CAN_TDL1R_DATA1_Pos (8U)
2307 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2308 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2309 #define CAN_TDL1R_DATA2_Pos (16U)
2310 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2311 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2312 #define CAN_TDL1R_DATA3_Pos (24U)
2313 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2314 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2315
2316 /******************* Bit definition for CAN_TDH1R register ******************/
2317 #define CAN_TDH1R_DATA4_Pos (0U)
2318 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2319 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2320 #define CAN_TDH1R_DATA5_Pos (8U)
2321 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2322 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2323 #define CAN_TDH1R_DATA6_Pos (16U)
2324 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2325 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2326 #define CAN_TDH1R_DATA7_Pos (24U)
2327 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2328 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2329
2330 /******************* Bit definition for CAN_TI2R register *******************/
2331 #define CAN_TI2R_TXRQ_Pos (0U)
2332 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2333 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2334 #define CAN_TI2R_RTR_Pos (1U)
2335 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2336 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2337 #define CAN_TI2R_IDE_Pos (2U)
2338 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2339 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2340 #define CAN_TI2R_EXID_Pos (3U)
2341 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2342 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2343 #define CAN_TI2R_STID_Pos (21U)
2344 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2345 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2346
2347 /******************* Bit definition for CAN_TDT2R register ******************/
2348 #define CAN_TDT2R_DLC_Pos (0U)
2349 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2350 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2351 #define CAN_TDT2R_TGT_Pos (8U)
2352 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2353 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2354 #define CAN_TDT2R_TIME_Pos (16U)
2355 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2356 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2357
2358 /******************* Bit definition for CAN_TDL2R register ******************/
2359 #define CAN_TDL2R_DATA0_Pos (0U)
2360 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2361 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2362 #define CAN_TDL2R_DATA1_Pos (8U)
2363 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2364 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2365 #define CAN_TDL2R_DATA2_Pos (16U)
2366 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2367 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2368 #define CAN_TDL2R_DATA3_Pos (24U)
2369 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2370 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2371
2372 /******************* Bit definition for CAN_TDH2R register ******************/
2373 #define CAN_TDH2R_DATA4_Pos (0U)
2374 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2375 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2376 #define CAN_TDH2R_DATA5_Pos (8U)
2377 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2378 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2379 #define CAN_TDH2R_DATA6_Pos (16U)
2380 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2381 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2382 #define CAN_TDH2R_DATA7_Pos (24U)
2383 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2384 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2385
2386 /******************* Bit definition for CAN_RI0R register *******************/
2387 #define CAN_RI0R_RTR_Pos (1U)
2388 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2389 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2390 #define CAN_RI0R_IDE_Pos (2U)
2391 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2392 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2393 #define CAN_RI0R_EXID_Pos (3U)
2394 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2395 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2396 #define CAN_RI0R_STID_Pos (21U)
2397 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2398 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2399
2400 /******************* Bit definition for CAN_RDT0R register ******************/
2401 #define CAN_RDT0R_DLC_Pos (0U)
2402 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2403 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2404 #define CAN_RDT0R_FMI_Pos (8U)
2405 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2406 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2407 #define CAN_RDT0R_TIME_Pos (16U)
2408 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2409 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2410
2411 /******************* Bit definition for CAN_RDL0R register ******************/
2412 #define CAN_RDL0R_DATA0_Pos (0U)
2413 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2414 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2415 #define CAN_RDL0R_DATA1_Pos (8U)
2416 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2417 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2418 #define CAN_RDL0R_DATA2_Pos (16U)
2419 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2420 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2421 #define CAN_RDL0R_DATA3_Pos (24U)
2422 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2423 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2424
2425 /******************* Bit definition for CAN_RDH0R register ******************/
2426 #define CAN_RDH0R_DATA4_Pos (0U)
2427 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2428 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2429 #define CAN_RDH0R_DATA5_Pos (8U)
2430 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2431 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2432 #define CAN_RDH0R_DATA6_Pos (16U)
2433 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2434 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2435 #define CAN_RDH0R_DATA7_Pos (24U)
2436 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2437 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2438
2439 /******************* Bit definition for CAN_RI1R register *******************/
2440 #define CAN_RI1R_RTR_Pos (1U)
2441 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2442 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2443 #define CAN_RI1R_IDE_Pos (2U)
2444 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2445 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2446 #define CAN_RI1R_EXID_Pos (3U)
2447 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2448 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2449 #define CAN_RI1R_STID_Pos (21U)
2450 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2451 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2452
2453 /******************* Bit definition for CAN_RDT1R register ******************/
2454 #define CAN_RDT1R_DLC_Pos (0U)
2455 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2456 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2457 #define CAN_RDT1R_FMI_Pos (8U)
2458 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2459 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2460 #define CAN_RDT1R_TIME_Pos (16U)
2461 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2462 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2463
2464 /******************* Bit definition for CAN_RDL1R register ******************/
2465 #define CAN_RDL1R_DATA0_Pos (0U)
2466 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2467 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2468 #define CAN_RDL1R_DATA1_Pos (8U)
2469 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2470 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2471 #define CAN_RDL1R_DATA2_Pos (16U)
2472 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2473 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2474 #define CAN_RDL1R_DATA3_Pos (24U)
2475 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2476 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2477
2478 /******************* Bit definition for CAN_RDH1R register ******************/
2479 #define CAN_RDH1R_DATA4_Pos (0U)
2480 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2481 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2482 #define CAN_RDH1R_DATA5_Pos (8U)
2483 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2484 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2485 #define CAN_RDH1R_DATA6_Pos (16U)
2486 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2487 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2488 #define CAN_RDH1R_DATA7_Pos (24U)
2489 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2490 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2491
2492 /*!<CAN filter registers */
2493 /******************* Bit definition for CAN_FMR register ********************/
2494 #define CAN_FMR_FINIT_Pos (0U)
2495 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2496 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2497 #define CAN_FMR_CAN2SB_Pos (8U)
2498 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2499 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2500
2501 /******************* Bit definition for CAN_FM1R register *******************/
2502 #define CAN_FM1R_FBM_Pos (0U)
2503 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2504 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2505 #define CAN_FM1R_FBM0_Pos (0U)
2506 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2507 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2508 #define CAN_FM1R_FBM1_Pos (1U)
2509 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2510 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2511 #define CAN_FM1R_FBM2_Pos (2U)
2512 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2513 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2514 #define CAN_FM1R_FBM3_Pos (3U)
2515 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2516 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2517 #define CAN_FM1R_FBM4_Pos (4U)
2518 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2519 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2520 #define CAN_FM1R_FBM5_Pos (5U)
2521 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2522 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2523 #define CAN_FM1R_FBM6_Pos (6U)
2524 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2525 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2526 #define CAN_FM1R_FBM7_Pos (7U)
2527 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2528 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2529 #define CAN_FM1R_FBM8_Pos (8U)
2530 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2531 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2532 #define CAN_FM1R_FBM9_Pos (9U)
2533 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2534 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2535 #define CAN_FM1R_FBM10_Pos (10U)
2536 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2537 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2538 #define CAN_FM1R_FBM11_Pos (11U)
2539 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2540 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2541 #define CAN_FM1R_FBM12_Pos (12U)
2542 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2543 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2544 #define CAN_FM1R_FBM13_Pos (13U)
2545 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2546 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2547 #define CAN_FM1R_FBM14_Pos (14U)
2548 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2549 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2550 #define CAN_FM1R_FBM15_Pos (15U)
2551 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2552 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2553 #define CAN_FM1R_FBM16_Pos (16U)
2554 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2555 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2556 #define CAN_FM1R_FBM17_Pos (17U)
2557 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2558 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2559 #define CAN_FM1R_FBM18_Pos (18U)
2560 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2561 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2562 #define CAN_FM1R_FBM19_Pos (19U)
2563 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2564 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2565 #define CAN_FM1R_FBM20_Pos (20U)
2566 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2567 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2568 #define CAN_FM1R_FBM21_Pos (21U)
2569 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2570 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2571 #define CAN_FM1R_FBM22_Pos (22U)
2572 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2573 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2574 #define CAN_FM1R_FBM23_Pos (23U)
2575 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2576 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2577 #define CAN_FM1R_FBM24_Pos (24U)
2578 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2579 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2580 #define CAN_FM1R_FBM25_Pos (25U)
2581 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2582 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2583 #define CAN_FM1R_FBM26_Pos (26U)
2584 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2585 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2586 #define CAN_FM1R_FBM27_Pos (27U)
2587 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2588 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2589
2590 /******************* Bit definition for CAN_FS1R register *******************/
2591 #define CAN_FS1R_FSC_Pos (0U)
2592 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2593 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2594 #define CAN_FS1R_FSC0_Pos (0U)
2595 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2596 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2597 #define CAN_FS1R_FSC1_Pos (1U)
2598 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2599 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2600 #define CAN_FS1R_FSC2_Pos (2U)
2601 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2602 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2603 #define CAN_FS1R_FSC3_Pos (3U)
2604 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2605 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2606 #define CAN_FS1R_FSC4_Pos (4U)
2607 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2608 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2609 #define CAN_FS1R_FSC5_Pos (5U)
2610 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2611 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2612 #define CAN_FS1R_FSC6_Pos (6U)
2613 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2614 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2615 #define CAN_FS1R_FSC7_Pos (7U)
2616 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2617 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2618 #define CAN_FS1R_FSC8_Pos (8U)
2619 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2620 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2621 #define CAN_FS1R_FSC9_Pos (9U)
2622 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2623 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2624 #define CAN_FS1R_FSC10_Pos (10U)
2625 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2626 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2627 #define CAN_FS1R_FSC11_Pos (11U)
2628 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2629 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2630 #define CAN_FS1R_FSC12_Pos (12U)
2631 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2632 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2633 #define CAN_FS1R_FSC13_Pos (13U)
2634 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2635 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2636 #define CAN_FS1R_FSC14_Pos (14U)
2637 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2638 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2639 #define CAN_FS1R_FSC15_Pos (15U)
2640 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2641 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2642 #define CAN_FS1R_FSC16_Pos (16U)
2643 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2644 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2645 #define CAN_FS1R_FSC17_Pos (17U)
2646 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2647 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2648 #define CAN_FS1R_FSC18_Pos (18U)
2649 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2650 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2651 #define CAN_FS1R_FSC19_Pos (19U)
2652 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2653 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2654 #define CAN_FS1R_FSC20_Pos (20U)
2655 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2656 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2657 #define CAN_FS1R_FSC21_Pos (21U)
2658 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2659 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2660 #define CAN_FS1R_FSC22_Pos (22U)
2661 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2662 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2663 #define CAN_FS1R_FSC23_Pos (23U)
2664 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2665 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2666 #define CAN_FS1R_FSC24_Pos (24U)
2667 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2668 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2669 #define CAN_FS1R_FSC25_Pos (25U)
2670 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2671 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2672 #define CAN_FS1R_FSC26_Pos (26U)
2673 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2674 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2675 #define CAN_FS1R_FSC27_Pos (27U)
2676 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2677 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2678
2679 /****************** Bit definition for CAN_FFA1R register *******************/
2680 #define CAN_FFA1R_FFA_Pos (0U)
2681 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2682 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2683 #define CAN_FFA1R_FFA0_Pos (0U)
2684 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2685 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2686 #define CAN_FFA1R_FFA1_Pos (1U)
2687 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2688 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2689 #define CAN_FFA1R_FFA2_Pos (2U)
2690 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2691 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2692 #define CAN_FFA1R_FFA3_Pos (3U)
2693 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2694 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2695 #define CAN_FFA1R_FFA4_Pos (4U)
2696 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2697 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2698 #define CAN_FFA1R_FFA5_Pos (5U)
2699 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2700 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2701 #define CAN_FFA1R_FFA6_Pos (6U)
2702 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2703 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2704 #define CAN_FFA1R_FFA7_Pos (7U)
2705 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2706 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2707 #define CAN_FFA1R_FFA8_Pos (8U)
2708 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2709 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2710 #define CAN_FFA1R_FFA9_Pos (9U)
2711 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2712 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2713 #define CAN_FFA1R_FFA10_Pos (10U)
2714 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2715 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2716 #define CAN_FFA1R_FFA11_Pos (11U)
2717 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2718 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2719 #define CAN_FFA1R_FFA12_Pos (12U)
2720 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2721 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2722 #define CAN_FFA1R_FFA13_Pos (13U)
2723 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2724 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2725 #define CAN_FFA1R_FFA14_Pos (14U)
2726 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2727 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2728 #define CAN_FFA1R_FFA15_Pos (15U)
2729 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2730 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2731 #define CAN_FFA1R_FFA16_Pos (16U)
2732 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2733 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2734 #define CAN_FFA1R_FFA17_Pos (17U)
2735 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2736 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2737 #define CAN_FFA1R_FFA18_Pos (18U)
2738 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2739 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2740 #define CAN_FFA1R_FFA19_Pos (19U)
2741 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2742 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2743 #define CAN_FFA1R_FFA20_Pos (20U)
2744 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2745 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2746 #define CAN_FFA1R_FFA21_Pos (21U)
2747 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2748 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2749 #define CAN_FFA1R_FFA22_Pos (22U)
2750 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2751 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2752 #define CAN_FFA1R_FFA23_Pos (23U)
2753 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2754 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2755 #define CAN_FFA1R_FFA24_Pos (24U)
2756 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2757 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2758 #define CAN_FFA1R_FFA25_Pos (25U)
2759 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2760 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2761 #define CAN_FFA1R_FFA26_Pos (26U)
2762 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2763 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2764 #define CAN_FFA1R_FFA27_Pos (27U)
2765 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2766 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2767
2768 /******************* Bit definition for CAN_FA1R register *******************/
2769 #define CAN_FA1R_FACT_Pos (0U)
2770 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2771 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2772 #define CAN_FA1R_FACT0_Pos (0U)
2773 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2774 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2775 #define CAN_FA1R_FACT1_Pos (1U)
2776 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2777 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2778 #define CAN_FA1R_FACT2_Pos (2U)
2779 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2780 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2781 #define CAN_FA1R_FACT3_Pos (3U)
2782 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2783 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2784 #define CAN_FA1R_FACT4_Pos (4U)
2785 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2786 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2787 #define CAN_FA1R_FACT5_Pos (5U)
2788 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2789 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2790 #define CAN_FA1R_FACT6_Pos (6U)
2791 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2792 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2793 #define CAN_FA1R_FACT7_Pos (7U)
2794 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2795 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2796 #define CAN_FA1R_FACT8_Pos (8U)
2797 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2798 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2799 #define CAN_FA1R_FACT9_Pos (9U)
2800 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2801 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2802 #define CAN_FA1R_FACT10_Pos (10U)
2803 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2804 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2805 #define CAN_FA1R_FACT11_Pos (11U)
2806 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2807 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2808 #define CAN_FA1R_FACT12_Pos (12U)
2809 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2810 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2811 #define CAN_FA1R_FACT13_Pos (13U)
2812 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2813 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2814 #define CAN_FA1R_FACT14_Pos (14U)
2815 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2816 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2817 #define CAN_FA1R_FACT15_Pos (15U)
2818 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2819 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2820 #define CAN_FA1R_FACT16_Pos (16U)
2821 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2822 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2823 #define CAN_FA1R_FACT17_Pos (17U)
2824 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2825 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2826 #define CAN_FA1R_FACT18_Pos (18U)
2827 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2828 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2829 #define CAN_FA1R_FACT19_Pos (19U)
2830 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2831 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2832 #define CAN_FA1R_FACT20_Pos (20U)
2833 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2834 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2835 #define CAN_FA1R_FACT21_Pos (21U)
2836 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2837 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2838 #define CAN_FA1R_FACT22_Pos (22U)
2839 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2840 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2841 #define CAN_FA1R_FACT23_Pos (23U)
2842 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2843 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2844 #define CAN_FA1R_FACT24_Pos (24U)
2845 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2846 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2847 #define CAN_FA1R_FACT25_Pos (25U)
2848 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2849 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2850 #define CAN_FA1R_FACT26_Pos (26U)
2851 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2852 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
2853 #define CAN_FA1R_FACT27_Pos (27U)
2854 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
2855 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
2856
2857
2858 /******************* Bit definition for CAN_F0R1 register *******************/
2859 #define CAN_F0R1_FB0_Pos (0U)
2860 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2861 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2862 #define CAN_F0R1_FB1_Pos (1U)
2863 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2864 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2865 #define CAN_F0R1_FB2_Pos (2U)
2866 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2867 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2868 #define CAN_F0R1_FB3_Pos (3U)
2869 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2870 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2871 #define CAN_F0R1_FB4_Pos (4U)
2872 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2873 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2874 #define CAN_F0R1_FB5_Pos (5U)
2875 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2876 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2877 #define CAN_F0R1_FB6_Pos (6U)
2878 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2879 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2880 #define CAN_F0R1_FB7_Pos (7U)
2881 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2882 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2883 #define CAN_F0R1_FB8_Pos (8U)
2884 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2885 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2886 #define CAN_F0R1_FB9_Pos (9U)
2887 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2888 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2889 #define CAN_F0R1_FB10_Pos (10U)
2890 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2891 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2892 #define CAN_F0R1_FB11_Pos (11U)
2893 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2894 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2895 #define CAN_F0R1_FB12_Pos (12U)
2896 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2897 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2898 #define CAN_F0R1_FB13_Pos (13U)
2899 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2900 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2901 #define CAN_F0R1_FB14_Pos (14U)
2902 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2903 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2904 #define CAN_F0R1_FB15_Pos (15U)
2905 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2906 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2907 #define CAN_F0R1_FB16_Pos (16U)
2908 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2909 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2910 #define CAN_F0R1_FB17_Pos (17U)
2911 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2912 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2913 #define CAN_F0R1_FB18_Pos (18U)
2914 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2915 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2916 #define CAN_F0R1_FB19_Pos (19U)
2917 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2918 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2919 #define CAN_F0R1_FB20_Pos (20U)
2920 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2921 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2922 #define CAN_F0R1_FB21_Pos (21U)
2923 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2924 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2925 #define CAN_F0R1_FB22_Pos (22U)
2926 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2927 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2928 #define CAN_F0R1_FB23_Pos (23U)
2929 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2930 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
2931 #define CAN_F0R1_FB24_Pos (24U)
2932 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
2933 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
2934 #define CAN_F0R1_FB25_Pos (25U)
2935 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
2936 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
2937 #define CAN_F0R1_FB26_Pos (26U)
2938 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
2939 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
2940 #define CAN_F0R1_FB27_Pos (27U)
2941 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
2942 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
2943 #define CAN_F0R1_FB28_Pos (28U)
2944 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
2945 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
2946 #define CAN_F0R1_FB29_Pos (29U)
2947 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
2948 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
2949 #define CAN_F0R1_FB30_Pos (30U)
2950 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
2951 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
2952 #define CAN_F0R1_FB31_Pos (31U)
2953 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
2954 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
2955
2956 /******************* Bit definition for CAN_F1R1 register *******************/
2957 #define CAN_F1R1_FB0_Pos (0U)
2958 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
2959 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
2960 #define CAN_F1R1_FB1_Pos (1U)
2961 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
2962 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
2963 #define CAN_F1R1_FB2_Pos (2U)
2964 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
2965 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
2966 #define CAN_F1R1_FB3_Pos (3U)
2967 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
2968 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
2969 #define CAN_F1R1_FB4_Pos (4U)
2970 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
2971 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
2972 #define CAN_F1R1_FB5_Pos (5U)
2973 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
2974 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
2975 #define CAN_F1R1_FB6_Pos (6U)
2976 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
2977 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
2978 #define CAN_F1R1_FB7_Pos (7U)
2979 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
2980 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
2981 #define CAN_F1R1_FB8_Pos (8U)
2982 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
2983 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
2984 #define CAN_F1R1_FB9_Pos (9U)
2985 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
2986 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
2987 #define CAN_F1R1_FB10_Pos (10U)
2988 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
2989 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
2990 #define CAN_F1R1_FB11_Pos (11U)
2991 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
2992 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
2993 #define CAN_F1R1_FB12_Pos (12U)
2994 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
2995 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
2996 #define CAN_F1R1_FB13_Pos (13U)
2997 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
2998 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
2999 #define CAN_F1R1_FB14_Pos (14U)
3000 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3001 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3002 #define CAN_F1R1_FB15_Pos (15U)
3003 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3004 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3005 #define CAN_F1R1_FB16_Pos (16U)
3006 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3007 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3008 #define CAN_F1R1_FB17_Pos (17U)
3009 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3010 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3011 #define CAN_F1R1_FB18_Pos (18U)
3012 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3013 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3014 #define CAN_F1R1_FB19_Pos (19U)
3015 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3016 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3017 #define CAN_F1R1_FB20_Pos (20U)
3018 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3019 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3020 #define CAN_F1R1_FB21_Pos (21U)
3021 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3022 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3023 #define CAN_F1R1_FB22_Pos (22U)
3024 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3025 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3026 #define CAN_F1R1_FB23_Pos (23U)
3027 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3028 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3029 #define CAN_F1R1_FB24_Pos (24U)
3030 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3031 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3032 #define CAN_F1R1_FB25_Pos (25U)
3033 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3034 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3035 #define CAN_F1R1_FB26_Pos (26U)
3036 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3037 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3038 #define CAN_F1R1_FB27_Pos (27U)
3039 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3040 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3041 #define CAN_F1R1_FB28_Pos (28U)
3042 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3043 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3044 #define CAN_F1R1_FB29_Pos (29U)
3045 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3046 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3047 #define CAN_F1R1_FB30_Pos (30U)
3048 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3049 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3050 #define CAN_F1R1_FB31_Pos (31U)
3051 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3052 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3053
3054 /******************* Bit definition for CAN_F2R1 register *******************/
3055 #define CAN_F2R1_FB0_Pos (0U)
3056 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3057 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3058 #define CAN_F2R1_FB1_Pos (1U)
3059 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3060 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3061 #define CAN_F2R1_FB2_Pos (2U)
3062 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3063 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3064 #define CAN_F2R1_FB3_Pos (3U)
3065 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3066 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3067 #define CAN_F2R1_FB4_Pos (4U)
3068 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3069 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3070 #define CAN_F2R1_FB5_Pos (5U)
3071 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3072 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3073 #define CAN_F2R1_FB6_Pos (6U)
3074 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3075 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3076 #define CAN_F2R1_FB7_Pos (7U)
3077 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3078 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3079 #define CAN_F2R1_FB8_Pos (8U)
3080 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3081 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3082 #define CAN_F2R1_FB9_Pos (9U)
3083 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3084 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3085 #define CAN_F2R1_FB10_Pos (10U)
3086 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3087 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3088 #define CAN_F2R1_FB11_Pos (11U)
3089 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3090 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3091 #define CAN_F2R1_FB12_Pos (12U)
3092 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3093 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3094 #define CAN_F2R1_FB13_Pos (13U)
3095 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3096 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3097 #define CAN_F2R1_FB14_Pos (14U)
3098 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3099 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3100 #define CAN_F2R1_FB15_Pos (15U)
3101 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3102 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3103 #define CAN_F2R1_FB16_Pos (16U)
3104 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3105 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3106 #define CAN_F2R1_FB17_Pos (17U)
3107 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3108 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3109 #define CAN_F2R1_FB18_Pos (18U)
3110 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3111 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3112 #define CAN_F2R1_FB19_Pos (19U)
3113 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3114 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3115 #define CAN_F2R1_FB20_Pos (20U)
3116 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3117 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3118 #define CAN_F2R1_FB21_Pos (21U)
3119 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3120 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3121 #define CAN_F2R1_FB22_Pos (22U)
3122 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3123 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3124 #define CAN_F2R1_FB23_Pos (23U)
3125 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3126 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3127 #define CAN_F2R1_FB24_Pos (24U)
3128 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3129 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3130 #define CAN_F2R1_FB25_Pos (25U)
3131 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3132 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3133 #define CAN_F2R1_FB26_Pos (26U)
3134 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3135 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3136 #define CAN_F2R1_FB27_Pos (27U)
3137 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3138 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3139 #define CAN_F2R1_FB28_Pos (28U)
3140 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3141 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3142 #define CAN_F2R1_FB29_Pos (29U)
3143 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3144 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3145 #define CAN_F2R1_FB30_Pos (30U)
3146 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3147 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3148 #define CAN_F2R1_FB31_Pos (31U)
3149 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3150 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3151
3152 /******************* Bit definition for CAN_F3R1 register *******************/
3153 #define CAN_F3R1_FB0_Pos (0U)
3154 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3155 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3156 #define CAN_F3R1_FB1_Pos (1U)
3157 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3158 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3159 #define CAN_F3R1_FB2_Pos (2U)
3160 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3161 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3162 #define CAN_F3R1_FB3_Pos (3U)
3163 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3164 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3165 #define CAN_F3R1_FB4_Pos (4U)
3166 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3167 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3168 #define CAN_F3R1_FB5_Pos (5U)
3169 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3170 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3171 #define CAN_F3R1_FB6_Pos (6U)
3172 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3173 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3174 #define CAN_F3R1_FB7_Pos (7U)
3175 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3176 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3177 #define CAN_F3R1_FB8_Pos (8U)
3178 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3179 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3180 #define CAN_F3R1_FB9_Pos (9U)
3181 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3182 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3183 #define CAN_F3R1_FB10_Pos (10U)
3184 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3185 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3186 #define CAN_F3R1_FB11_Pos (11U)
3187 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3188 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3189 #define CAN_F3R1_FB12_Pos (12U)
3190 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3191 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3192 #define CAN_F3R1_FB13_Pos (13U)
3193 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3194 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3195 #define CAN_F3R1_FB14_Pos (14U)
3196 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3197 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3198 #define CAN_F3R1_FB15_Pos (15U)
3199 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3200 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3201 #define CAN_F3R1_FB16_Pos (16U)
3202 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3203 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3204 #define CAN_F3R1_FB17_Pos (17U)
3205 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3206 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3207 #define CAN_F3R1_FB18_Pos (18U)
3208 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3209 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3210 #define CAN_F3R1_FB19_Pos (19U)
3211 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3212 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3213 #define CAN_F3R1_FB20_Pos (20U)
3214 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3215 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3216 #define CAN_F3R1_FB21_Pos (21U)
3217 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3218 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3219 #define CAN_F3R1_FB22_Pos (22U)
3220 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3221 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3222 #define CAN_F3R1_FB23_Pos (23U)
3223 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3224 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3225 #define CAN_F3R1_FB24_Pos (24U)
3226 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3227 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3228 #define CAN_F3R1_FB25_Pos (25U)
3229 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3230 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3231 #define CAN_F3R1_FB26_Pos (26U)
3232 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3233 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3234 #define CAN_F3R1_FB27_Pos (27U)
3235 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3236 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3237 #define CAN_F3R1_FB28_Pos (28U)
3238 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3239 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3240 #define CAN_F3R1_FB29_Pos (29U)
3241 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3242 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3243 #define CAN_F3R1_FB30_Pos (30U)
3244 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3245 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3246 #define CAN_F3R1_FB31_Pos (31U)
3247 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3248 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3249
3250 /******************* Bit definition for CAN_F4R1 register *******************/
3251 #define CAN_F4R1_FB0_Pos (0U)
3252 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3253 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3254 #define CAN_F4R1_FB1_Pos (1U)
3255 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3256 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3257 #define CAN_F4R1_FB2_Pos (2U)
3258 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3259 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3260 #define CAN_F4R1_FB3_Pos (3U)
3261 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3262 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3263 #define CAN_F4R1_FB4_Pos (4U)
3264 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3265 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3266 #define CAN_F4R1_FB5_Pos (5U)
3267 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3268 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3269 #define CAN_F4R1_FB6_Pos (6U)
3270 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3271 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3272 #define CAN_F4R1_FB7_Pos (7U)
3273 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3274 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3275 #define CAN_F4R1_FB8_Pos (8U)
3276 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3277 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3278 #define CAN_F4R1_FB9_Pos (9U)
3279 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3280 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3281 #define CAN_F4R1_FB10_Pos (10U)
3282 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3283 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3284 #define CAN_F4R1_FB11_Pos (11U)
3285 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3286 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3287 #define CAN_F4R1_FB12_Pos (12U)
3288 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3289 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3290 #define CAN_F4R1_FB13_Pos (13U)
3291 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3292 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3293 #define CAN_F4R1_FB14_Pos (14U)
3294 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3295 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3296 #define CAN_F4R1_FB15_Pos (15U)
3297 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3298 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3299 #define CAN_F4R1_FB16_Pos (16U)
3300 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3301 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3302 #define CAN_F4R1_FB17_Pos (17U)
3303 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3304 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3305 #define CAN_F4R1_FB18_Pos (18U)
3306 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3307 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3308 #define CAN_F4R1_FB19_Pos (19U)
3309 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3310 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3311 #define CAN_F4R1_FB20_Pos (20U)
3312 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3313 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3314 #define CAN_F4R1_FB21_Pos (21U)
3315 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3316 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3317 #define CAN_F4R1_FB22_Pos (22U)
3318 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3319 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3320 #define CAN_F4R1_FB23_Pos (23U)
3321 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3322 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3323 #define CAN_F4R1_FB24_Pos (24U)
3324 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3325 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3326 #define CAN_F4R1_FB25_Pos (25U)
3327 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3328 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3329 #define CAN_F4R1_FB26_Pos (26U)
3330 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3331 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3332 #define CAN_F4R1_FB27_Pos (27U)
3333 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3334 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3335 #define CAN_F4R1_FB28_Pos (28U)
3336 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3337 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3338 #define CAN_F4R1_FB29_Pos (29U)
3339 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3340 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3341 #define CAN_F4R1_FB30_Pos (30U)
3342 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3343 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3344 #define CAN_F4R1_FB31_Pos (31U)
3345 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3346 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3347
3348 /******************* Bit definition for CAN_F5R1 register *******************/
3349 #define CAN_F5R1_FB0_Pos (0U)
3350 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3351 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3352 #define CAN_F5R1_FB1_Pos (1U)
3353 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3354 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3355 #define CAN_F5R1_FB2_Pos (2U)
3356 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3357 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3358 #define CAN_F5R1_FB3_Pos (3U)
3359 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3360 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3361 #define CAN_F5R1_FB4_Pos (4U)
3362 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3363 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3364 #define CAN_F5R1_FB5_Pos (5U)
3365 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3366 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3367 #define CAN_F5R1_FB6_Pos (6U)
3368 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3369 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3370 #define CAN_F5R1_FB7_Pos (7U)
3371 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3372 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3373 #define CAN_F5R1_FB8_Pos (8U)
3374 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3375 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3376 #define CAN_F5R1_FB9_Pos (9U)
3377 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3378 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3379 #define CAN_F5R1_FB10_Pos (10U)
3380 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3381 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3382 #define CAN_F5R1_FB11_Pos (11U)
3383 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3384 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3385 #define CAN_F5R1_FB12_Pos (12U)
3386 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3387 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3388 #define CAN_F5R1_FB13_Pos (13U)
3389 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3390 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3391 #define CAN_F5R1_FB14_Pos (14U)
3392 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3393 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3394 #define CAN_F5R1_FB15_Pos (15U)
3395 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3396 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3397 #define CAN_F5R1_FB16_Pos (16U)
3398 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3399 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3400 #define CAN_F5R1_FB17_Pos (17U)
3401 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3402 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3403 #define CAN_F5R1_FB18_Pos (18U)
3404 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3405 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3406 #define CAN_F5R1_FB19_Pos (19U)
3407 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3408 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3409 #define CAN_F5R1_FB20_Pos (20U)
3410 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3411 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3412 #define CAN_F5R1_FB21_Pos (21U)
3413 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3414 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3415 #define CAN_F5R1_FB22_Pos (22U)
3416 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3417 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3418 #define CAN_F5R1_FB23_Pos (23U)
3419 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3420 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3421 #define CAN_F5R1_FB24_Pos (24U)
3422 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3423 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3424 #define CAN_F5R1_FB25_Pos (25U)
3425 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3426 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3427 #define CAN_F5R1_FB26_Pos (26U)
3428 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3429 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3430 #define CAN_F5R1_FB27_Pos (27U)
3431 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3432 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3433 #define CAN_F5R1_FB28_Pos (28U)
3434 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3435 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3436 #define CAN_F5R1_FB29_Pos (29U)
3437 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3438 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3439 #define CAN_F5R1_FB30_Pos (30U)
3440 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3441 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3442 #define CAN_F5R1_FB31_Pos (31U)
3443 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3444 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3445
3446 /******************* Bit definition for CAN_F6R1 register *******************/
3447 #define CAN_F6R1_FB0_Pos (0U)
3448 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3449 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3450 #define CAN_F6R1_FB1_Pos (1U)
3451 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3452 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3453 #define CAN_F6R1_FB2_Pos (2U)
3454 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3455 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3456 #define CAN_F6R1_FB3_Pos (3U)
3457 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3458 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3459 #define CAN_F6R1_FB4_Pos (4U)
3460 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3461 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3462 #define CAN_F6R1_FB5_Pos (5U)
3463 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3464 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3465 #define CAN_F6R1_FB6_Pos (6U)
3466 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3467 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3468 #define CAN_F6R1_FB7_Pos (7U)
3469 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3470 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3471 #define CAN_F6R1_FB8_Pos (8U)
3472 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3473 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3474 #define CAN_F6R1_FB9_Pos (9U)
3475 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3476 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3477 #define CAN_F6R1_FB10_Pos (10U)
3478 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3479 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3480 #define CAN_F6R1_FB11_Pos (11U)
3481 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3482 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3483 #define CAN_F6R1_FB12_Pos (12U)
3484 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3485 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3486 #define CAN_F6R1_FB13_Pos (13U)
3487 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3488 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3489 #define CAN_F6R1_FB14_Pos (14U)
3490 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3491 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3492 #define CAN_F6R1_FB15_Pos (15U)
3493 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3494 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3495 #define CAN_F6R1_FB16_Pos (16U)
3496 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3497 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3498 #define CAN_F6R1_FB17_Pos (17U)
3499 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3500 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3501 #define CAN_F6R1_FB18_Pos (18U)
3502 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3503 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3504 #define CAN_F6R1_FB19_Pos (19U)
3505 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3506 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3507 #define CAN_F6R1_FB20_Pos (20U)
3508 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3509 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3510 #define CAN_F6R1_FB21_Pos (21U)
3511 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3512 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3513 #define CAN_F6R1_FB22_Pos (22U)
3514 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3515 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3516 #define CAN_F6R1_FB23_Pos (23U)
3517 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3518 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3519 #define CAN_F6R1_FB24_Pos (24U)
3520 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3521 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3522 #define CAN_F6R1_FB25_Pos (25U)
3523 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3524 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3525 #define CAN_F6R1_FB26_Pos (26U)
3526 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3527 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3528 #define CAN_F6R1_FB27_Pos (27U)
3529 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3530 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3531 #define CAN_F6R1_FB28_Pos (28U)
3532 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3533 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3534 #define CAN_F6R1_FB29_Pos (29U)
3535 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3536 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3537 #define CAN_F6R1_FB30_Pos (30U)
3538 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3539 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3540 #define CAN_F6R1_FB31_Pos (31U)
3541 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3542 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3543
3544 /******************* Bit definition for CAN_F7R1 register *******************/
3545 #define CAN_F7R1_FB0_Pos (0U)
3546 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3547 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3548 #define CAN_F7R1_FB1_Pos (1U)
3549 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3550 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3551 #define CAN_F7R1_FB2_Pos (2U)
3552 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3553 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3554 #define CAN_F7R1_FB3_Pos (3U)
3555 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3556 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3557 #define CAN_F7R1_FB4_Pos (4U)
3558 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3559 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3560 #define CAN_F7R1_FB5_Pos (5U)
3561 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3562 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3563 #define CAN_F7R1_FB6_Pos (6U)
3564 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3565 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3566 #define CAN_F7R1_FB7_Pos (7U)
3567 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3568 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3569 #define CAN_F7R1_FB8_Pos (8U)
3570 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3571 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3572 #define CAN_F7R1_FB9_Pos (9U)
3573 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3574 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3575 #define CAN_F7R1_FB10_Pos (10U)
3576 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3577 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3578 #define CAN_F7R1_FB11_Pos (11U)
3579 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3580 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3581 #define CAN_F7R1_FB12_Pos (12U)
3582 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3583 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3584 #define CAN_F7R1_FB13_Pos (13U)
3585 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3586 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3587 #define CAN_F7R1_FB14_Pos (14U)
3588 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3589 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3590 #define CAN_F7R1_FB15_Pos (15U)
3591 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3592 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3593 #define CAN_F7R1_FB16_Pos (16U)
3594 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3595 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3596 #define CAN_F7R1_FB17_Pos (17U)
3597 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3598 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3599 #define CAN_F7R1_FB18_Pos (18U)
3600 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3601 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3602 #define CAN_F7R1_FB19_Pos (19U)
3603 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3604 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3605 #define CAN_F7R1_FB20_Pos (20U)
3606 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3607 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3608 #define CAN_F7R1_FB21_Pos (21U)
3609 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3610 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3611 #define CAN_F7R1_FB22_Pos (22U)
3612 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3613 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3614 #define CAN_F7R1_FB23_Pos (23U)
3615 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3616 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3617 #define CAN_F7R1_FB24_Pos (24U)
3618 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3619 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3620 #define CAN_F7R1_FB25_Pos (25U)
3621 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3622 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3623 #define CAN_F7R1_FB26_Pos (26U)
3624 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3625 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3626 #define CAN_F7R1_FB27_Pos (27U)
3627 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3628 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3629 #define CAN_F7R1_FB28_Pos (28U)
3630 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3631 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3632 #define CAN_F7R1_FB29_Pos (29U)
3633 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3634 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3635 #define CAN_F7R1_FB30_Pos (30U)
3636 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3637 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3638 #define CAN_F7R1_FB31_Pos (31U)
3639 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3640 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3641
3642 /******************* Bit definition for CAN_F8R1 register *******************/
3643 #define CAN_F8R1_FB0_Pos (0U)
3644 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3645 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3646 #define CAN_F8R1_FB1_Pos (1U)
3647 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3648 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3649 #define CAN_F8R1_FB2_Pos (2U)
3650 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3651 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3652 #define CAN_F8R1_FB3_Pos (3U)
3653 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3654 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3655 #define CAN_F8R1_FB4_Pos (4U)
3656 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3657 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3658 #define CAN_F8R1_FB5_Pos (5U)
3659 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3660 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3661 #define CAN_F8R1_FB6_Pos (6U)
3662 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3663 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3664 #define CAN_F8R1_FB7_Pos (7U)
3665 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3666 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3667 #define CAN_F8R1_FB8_Pos (8U)
3668 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3669 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3670 #define CAN_F8R1_FB9_Pos (9U)
3671 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3672 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3673 #define CAN_F8R1_FB10_Pos (10U)
3674 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3675 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3676 #define CAN_F8R1_FB11_Pos (11U)
3677 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3678 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3679 #define CAN_F8R1_FB12_Pos (12U)
3680 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3681 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3682 #define CAN_F8R1_FB13_Pos (13U)
3683 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3684 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3685 #define CAN_F8R1_FB14_Pos (14U)
3686 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3687 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3688 #define CAN_F8R1_FB15_Pos (15U)
3689 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3690 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3691 #define CAN_F8R1_FB16_Pos (16U)
3692 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3693 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3694 #define CAN_F8R1_FB17_Pos (17U)
3695 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3696 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3697 #define CAN_F8R1_FB18_Pos (18U)
3698 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3699 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3700 #define CAN_F8R1_FB19_Pos (19U)
3701 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3702 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3703 #define CAN_F8R1_FB20_Pos (20U)
3704 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3705 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3706 #define CAN_F8R1_FB21_Pos (21U)
3707 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3708 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3709 #define CAN_F8R1_FB22_Pos (22U)
3710 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3711 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3712 #define CAN_F8R1_FB23_Pos (23U)
3713 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3714 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3715 #define CAN_F8R1_FB24_Pos (24U)
3716 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3717 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3718 #define CAN_F8R1_FB25_Pos (25U)
3719 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3720 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3721 #define CAN_F8R1_FB26_Pos (26U)
3722 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3723 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3724 #define CAN_F8R1_FB27_Pos (27U)
3725 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3726 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3727 #define CAN_F8R1_FB28_Pos (28U)
3728 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3729 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3730 #define CAN_F8R1_FB29_Pos (29U)
3731 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3732 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3733 #define CAN_F8R1_FB30_Pos (30U)
3734 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3735 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3736 #define CAN_F8R1_FB31_Pos (31U)
3737 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3738 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3739
3740 /******************* Bit definition for CAN_F9R1 register *******************/
3741 #define CAN_F9R1_FB0_Pos (0U)
3742 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3743 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3744 #define CAN_F9R1_FB1_Pos (1U)
3745 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3746 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3747 #define CAN_F9R1_FB2_Pos (2U)
3748 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3749 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3750 #define CAN_F9R1_FB3_Pos (3U)
3751 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3752 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3753 #define CAN_F9R1_FB4_Pos (4U)
3754 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3755 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3756 #define CAN_F9R1_FB5_Pos (5U)
3757 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3758 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3759 #define CAN_F9R1_FB6_Pos (6U)
3760 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3761 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3762 #define CAN_F9R1_FB7_Pos (7U)
3763 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3764 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3765 #define CAN_F9R1_FB8_Pos (8U)
3766 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3767 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3768 #define CAN_F9R1_FB9_Pos (9U)
3769 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3770 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3771 #define CAN_F9R1_FB10_Pos (10U)
3772 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3773 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3774 #define CAN_F9R1_FB11_Pos (11U)
3775 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3776 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3777 #define CAN_F9R1_FB12_Pos (12U)
3778 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3779 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3780 #define CAN_F9R1_FB13_Pos (13U)
3781 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3782 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3783 #define CAN_F9R1_FB14_Pos (14U)
3784 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3785 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3786 #define CAN_F9R1_FB15_Pos (15U)
3787 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3788 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3789 #define CAN_F9R1_FB16_Pos (16U)
3790 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3791 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3792 #define CAN_F9R1_FB17_Pos (17U)
3793 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3794 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3795 #define CAN_F9R1_FB18_Pos (18U)
3796 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3797 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3798 #define CAN_F9R1_FB19_Pos (19U)
3799 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3800 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3801 #define CAN_F9R1_FB20_Pos (20U)
3802 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3803 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3804 #define CAN_F9R1_FB21_Pos (21U)
3805 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3806 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3807 #define CAN_F9R1_FB22_Pos (22U)
3808 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3809 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3810 #define CAN_F9R1_FB23_Pos (23U)
3811 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3812 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3813 #define CAN_F9R1_FB24_Pos (24U)
3814 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3815 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3816 #define CAN_F9R1_FB25_Pos (25U)
3817 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3818 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3819 #define CAN_F9R1_FB26_Pos (26U)
3820 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3821 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3822 #define CAN_F9R1_FB27_Pos (27U)
3823 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3824 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3825 #define CAN_F9R1_FB28_Pos (28U)
3826 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3827 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3828 #define CAN_F9R1_FB29_Pos (29U)
3829 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3830 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3831 #define CAN_F9R1_FB30_Pos (30U)
3832 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3833 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3834 #define CAN_F9R1_FB31_Pos (31U)
3835 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3836 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3837
3838 /******************* Bit definition for CAN_F10R1 register ******************/
3839 #define CAN_F10R1_FB0_Pos (0U)
3840 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3841 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3842 #define CAN_F10R1_FB1_Pos (1U)
3843 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3844 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3845 #define CAN_F10R1_FB2_Pos (2U)
3846 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3847 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3848 #define CAN_F10R1_FB3_Pos (3U)
3849 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3850 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3851 #define CAN_F10R1_FB4_Pos (4U)
3852 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3853 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3854 #define CAN_F10R1_FB5_Pos (5U)
3855 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3856 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3857 #define CAN_F10R1_FB6_Pos (6U)
3858 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3859 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3860 #define CAN_F10R1_FB7_Pos (7U)
3861 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3862 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3863 #define CAN_F10R1_FB8_Pos (8U)
3864 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3865 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3866 #define CAN_F10R1_FB9_Pos (9U)
3867 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3868 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3869 #define CAN_F10R1_FB10_Pos (10U)
3870 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3871 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3872 #define CAN_F10R1_FB11_Pos (11U)
3873 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3874 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3875 #define CAN_F10R1_FB12_Pos (12U)
3876 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3877 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3878 #define CAN_F10R1_FB13_Pos (13U)
3879 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3880 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3881 #define CAN_F10R1_FB14_Pos (14U)
3882 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3883 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3884 #define CAN_F10R1_FB15_Pos (15U)
3885 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3886 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3887 #define CAN_F10R1_FB16_Pos (16U)
3888 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3889 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3890 #define CAN_F10R1_FB17_Pos (17U)
3891 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3892 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3893 #define CAN_F10R1_FB18_Pos (18U)
3894 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3895 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3896 #define CAN_F10R1_FB19_Pos (19U)
3897 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3898 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3899 #define CAN_F10R1_FB20_Pos (20U)
3900 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3901 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3902 #define CAN_F10R1_FB21_Pos (21U)
3903 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3904 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
3905 #define CAN_F10R1_FB22_Pos (22U)
3906 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
3907 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
3908 #define CAN_F10R1_FB23_Pos (23U)
3909 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
3910 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
3911 #define CAN_F10R1_FB24_Pos (24U)
3912 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
3913 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
3914 #define CAN_F10R1_FB25_Pos (25U)
3915 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
3916 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
3917 #define CAN_F10R1_FB26_Pos (26U)
3918 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
3919 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
3920 #define CAN_F10R1_FB27_Pos (27U)
3921 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
3922 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
3923 #define CAN_F10R1_FB28_Pos (28U)
3924 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
3925 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
3926 #define CAN_F10R1_FB29_Pos (29U)
3927 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
3928 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
3929 #define CAN_F10R1_FB30_Pos (30U)
3930 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
3931 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
3932 #define CAN_F10R1_FB31_Pos (31U)
3933 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
3934 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
3935
3936 /******************* Bit definition for CAN_F11R1 register ******************/
3937 #define CAN_F11R1_FB0_Pos (0U)
3938 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
3939 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
3940 #define CAN_F11R1_FB1_Pos (1U)
3941 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
3942 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
3943 #define CAN_F11R1_FB2_Pos (2U)
3944 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
3945 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
3946 #define CAN_F11R1_FB3_Pos (3U)
3947 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
3948 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
3949 #define CAN_F11R1_FB4_Pos (4U)
3950 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
3951 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
3952 #define CAN_F11R1_FB5_Pos (5U)
3953 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
3954 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
3955 #define CAN_F11R1_FB6_Pos (6U)
3956 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
3957 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
3958 #define CAN_F11R1_FB7_Pos (7U)
3959 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
3960 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
3961 #define CAN_F11R1_FB8_Pos (8U)
3962 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
3963 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
3964 #define CAN_F11R1_FB9_Pos (9U)
3965 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
3966 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
3967 #define CAN_F11R1_FB10_Pos (10U)
3968 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
3969 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
3970 #define CAN_F11R1_FB11_Pos (11U)
3971 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
3972 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
3973 #define CAN_F11R1_FB12_Pos (12U)
3974 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
3975 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
3976 #define CAN_F11R1_FB13_Pos (13U)
3977 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
3978 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
3979 #define CAN_F11R1_FB14_Pos (14U)
3980 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
3981 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
3982 #define CAN_F11R1_FB15_Pos (15U)
3983 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
3984 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
3985 #define CAN_F11R1_FB16_Pos (16U)
3986 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
3987 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
3988 #define CAN_F11R1_FB17_Pos (17U)
3989 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
3990 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
3991 #define CAN_F11R1_FB18_Pos (18U)
3992 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
3993 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
3994 #define CAN_F11R1_FB19_Pos (19U)
3995 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
3996 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
3997 #define CAN_F11R1_FB20_Pos (20U)
3998 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
3999 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4000 #define CAN_F11R1_FB21_Pos (21U)
4001 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4002 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4003 #define CAN_F11R1_FB22_Pos (22U)
4004 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4005 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4006 #define CAN_F11R1_FB23_Pos (23U)
4007 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4008 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4009 #define CAN_F11R1_FB24_Pos (24U)
4010 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4011 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4012 #define CAN_F11R1_FB25_Pos (25U)
4013 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4014 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4015 #define CAN_F11R1_FB26_Pos (26U)
4016 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4017 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4018 #define CAN_F11R1_FB27_Pos (27U)
4019 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4020 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4021 #define CAN_F11R1_FB28_Pos (28U)
4022 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4023 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4024 #define CAN_F11R1_FB29_Pos (29U)
4025 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4026 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4027 #define CAN_F11R1_FB30_Pos (30U)
4028 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4029 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4030 #define CAN_F11R1_FB31_Pos (31U)
4031 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4032 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4033
4034 /******************* Bit definition for CAN_F12R1 register ******************/
4035 #define CAN_F12R1_FB0_Pos (0U)
4036 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4037 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4038 #define CAN_F12R1_FB1_Pos (1U)
4039 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4040 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4041 #define CAN_F12R1_FB2_Pos (2U)
4042 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4043 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4044 #define CAN_F12R1_FB3_Pos (3U)
4045 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4046 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4047 #define CAN_F12R1_FB4_Pos (4U)
4048 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4049 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4050 #define CAN_F12R1_FB5_Pos (5U)
4051 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4052 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4053 #define CAN_F12R1_FB6_Pos (6U)
4054 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4055 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4056 #define CAN_F12R1_FB7_Pos (7U)
4057 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4058 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4059 #define CAN_F12R1_FB8_Pos (8U)
4060 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4061 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4062 #define CAN_F12R1_FB9_Pos (9U)
4063 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4064 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4065 #define CAN_F12R1_FB10_Pos (10U)
4066 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4067 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4068 #define CAN_F12R1_FB11_Pos (11U)
4069 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4070 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4071 #define CAN_F12R1_FB12_Pos (12U)
4072 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4073 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4074 #define CAN_F12R1_FB13_Pos (13U)
4075 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4076 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4077 #define CAN_F12R1_FB14_Pos (14U)
4078 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4079 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4080 #define CAN_F12R1_FB15_Pos (15U)
4081 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4082 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4083 #define CAN_F12R1_FB16_Pos (16U)
4084 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4085 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4086 #define CAN_F12R1_FB17_Pos (17U)
4087 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4088 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4089 #define CAN_F12R1_FB18_Pos (18U)
4090 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4091 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4092 #define CAN_F12R1_FB19_Pos (19U)
4093 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4094 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4095 #define CAN_F12R1_FB20_Pos (20U)
4096 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4097 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4098 #define CAN_F12R1_FB21_Pos (21U)
4099 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4100 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4101 #define CAN_F12R1_FB22_Pos (22U)
4102 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4103 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4104 #define CAN_F12R1_FB23_Pos (23U)
4105 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4106 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4107 #define CAN_F12R1_FB24_Pos (24U)
4108 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4109 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4110 #define CAN_F12R1_FB25_Pos (25U)
4111 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4112 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4113 #define CAN_F12R1_FB26_Pos (26U)
4114 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4115 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4116 #define CAN_F12R1_FB27_Pos (27U)
4117 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4118 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4119 #define CAN_F12R1_FB28_Pos (28U)
4120 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4121 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4122 #define CAN_F12R1_FB29_Pos (29U)
4123 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4124 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4125 #define CAN_F12R1_FB30_Pos (30U)
4126 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4127 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4128 #define CAN_F12R1_FB31_Pos (31U)
4129 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4130 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4131
4132 /******************* Bit definition for CAN_F13R1 register ******************/
4133 #define CAN_F13R1_FB0_Pos (0U)
4134 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4135 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4136 #define CAN_F13R1_FB1_Pos (1U)
4137 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4138 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4139 #define CAN_F13R1_FB2_Pos (2U)
4140 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4141 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4142 #define CAN_F13R1_FB3_Pos (3U)
4143 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4144 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4145 #define CAN_F13R1_FB4_Pos (4U)
4146 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4147 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4148 #define CAN_F13R1_FB5_Pos (5U)
4149 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4150 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4151 #define CAN_F13R1_FB6_Pos (6U)
4152 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4153 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4154 #define CAN_F13R1_FB7_Pos (7U)
4155 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4156 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4157 #define CAN_F13R1_FB8_Pos (8U)
4158 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4159 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4160 #define CAN_F13R1_FB9_Pos (9U)
4161 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4162 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4163 #define CAN_F13R1_FB10_Pos (10U)
4164 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4165 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4166 #define CAN_F13R1_FB11_Pos (11U)
4167 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4168 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4169 #define CAN_F13R1_FB12_Pos (12U)
4170 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4171 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4172 #define CAN_F13R1_FB13_Pos (13U)
4173 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4174 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4175 #define CAN_F13R1_FB14_Pos (14U)
4176 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4177 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4178 #define CAN_F13R1_FB15_Pos (15U)
4179 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4180 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4181 #define CAN_F13R1_FB16_Pos (16U)
4182 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4183 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4184 #define CAN_F13R1_FB17_Pos (17U)
4185 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4186 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4187 #define CAN_F13R1_FB18_Pos (18U)
4188 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4189 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4190 #define CAN_F13R1_FB19_Pos (19U)
4191 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4192 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4193 #define CAN_F13R1_FB20_Pos (20U)
4194 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4195 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4196 #define CAN_F13R1_FB21_Pos (21U)
4197 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4198 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4199 #define CAN_F13R1_FB22_Pos (22U)
4200 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4201 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4202 #define CAN_F13R1_FB23_Pos (23U)
4203 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4204 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4205 #define CAN_F13R1_FB24_Pos (24U)
4206 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4207 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4208 #define CAN_F13R1_FB25_Pos (25U)
4209 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4210 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4211 #define CAN_F13R1_FB26_Pos (26U)
4212 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4213 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4214 #define CAN_F13R1_FB27_Pos (27U)
4215 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4216 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4217 #define CAN_F13R1_FB28_Pos (28U)
4218 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4219 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4220 #define CAN_F13R1_FB29_Pos (29U)
4221 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4222 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4223 #define CAN_F13R1_FB30_Pos (30U)
4224 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4225 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4226 #define CAN_F13R1_FB31_Pos (31U)
4227 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4228 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4229
4230 /******************* Bit definition for CAN_F0R2 register *******************/
4231 #define CAN_F0R2_FB0_Pos (0U)
4232 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4233 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4234 #define CAN_F0R2_FB1_Pos (1U)
4235 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4236 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4237 #define CAN_F0R2_FB2_Pos (2U)
4238 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4239 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4240 #define CAN_F0R2_FB3_Pos (3U)
4241 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4242 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4243 #define CAN_F0R2_FB4_Pos (4U)
4244 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4245 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4246 #define CAN_F0R2_FB5_Pos (5U)
4247 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4248 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4249 #define CAN_F0R2_FB6_Pos (6U)
4250 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4251 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4252 #define CAN_F0R2_FB7_Pos (7U)
4253 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4254 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4255 #define CAN_F0R2_FB8_Pos (8U)
4256 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4257 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4258 #define CAN_F0R2_FB9_Pos (9U)
4259 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4260 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4261 #define CAN_F0R2_FB10_Pos (10U)
4262 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4263 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4264 #define CAN_F0R2_FB11_Pos (11U)
4265 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4266 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4267 #define CAN_F0R2_FB12_Pos (12U)
4268 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4269 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4270 #define CAN_F0R2_FB13_Pos (13U)
4271 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4272 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4273 #define CAN_F0R2_FB14_Pos (14U)
4274 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4275 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4276 #define CAN_F0R2_FB15_Pos (15U)
4277 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4278 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4279 #define CAN_F0R2_FB16_Pos (16U)
4280 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4281 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4282 #define CAN_F0R2_FB17_Pos (17U)
4283 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4284 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4285 #define CAN_F0R2_FB18_Pos (18U)
4286 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4287 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4288 #define CAN_F0R2_FB19_Pos (19U)
4289 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4290 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4291 #define CAN_F0R2_FB20_Pos (20U)
4292 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4293 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4294 #define CAN_F0R2_FB21_Pos (21U)
4295 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4296 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4297 #define CAN_F0R2_FB22_Pos (22U)
4298 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4299 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4300 #define CAN_F0R2_FB23_Pos (23U)
4301 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4302 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4303 #define CAN_F0R2_FB24_Pos (24U)
4304 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4305 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4306 #define CAN_F0R2_FB25_Pos (25U)
4307 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4308 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4309 #define CAN_F0R2_FB26_Pos (26U)
4310 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4311 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4312 #define CAN_F0R2_FB27_Pos (27U)
4313 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4314 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4315 #define CAN_F0R2_FB28_Pos (28U)
4316 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4317 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4318 #define CAN_F0R2_FB29_Pos (29U)
4319 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4320 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4321 #define CAN_F0R2_FB30_Pos (30U)
4322 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4323 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4324 #define CAN_F0R2_FB31_Pos (31U)
4325 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4326 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4327
4328 /******************* Bit definition for CAN_F1R2 register *******************/
4329 #define CAN_F1R2_FB0_Pos (0U)
4330 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4331 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4332 #define CAN_F1R2_FB1_Pos (1U)
4333 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4334 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4335 #define CAN_F1R2_FB2_Pos (2U)
4336 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4337 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4338 #define CAN_F1R2_FB3_Pos (3U)
4339 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4340 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4341 #define CAN_F1R2_FB4_Pos (4U)
4342 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4343 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4344 #define CAN_F1R2_FB5_Pos (5U)
4345 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4346 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4347 #define CAN_F1R2_FB6_Pos (6U)
4348 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4349 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4350 #define CAN_F1R2_FB7_Pos (7U)
4351 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4352 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4353 #define CAN_F1R2_FB8_Pos (8U)
4354 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4355 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4356 #define CAN_F1R2_FB9_Pos (9U)
4357 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4358 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4359 #define CAN_F1R2_FB10_Pos (10U)
4360 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4361 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4362 #define CAN_F1R2_FB11_Pos (11U)
4363 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4364 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4365 #define CAN_F1R2_FB12_Pos (12U)
4366 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4367 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4368 #define CAN_F1R2_FB13_Pos (13U)
4369 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4370 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4371 #define CAN_F1R2_FB14_Pos (14U)
4372 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4373 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4374 #define CAN_F1R2_FB15_Pos (15U)
4375 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4376 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4377 #define CAN_F1R2_FB16_Pos (16U)
4378 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4379 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4380 #define CAN_F1R2_FB17_Pos (17U)
4381 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4382 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4383 #define CAN_F1R2_FB18_Pos (18U)
4384 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4385 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4386 #define CAN_F1R2_FB19_Pos (19U)
4387 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4388 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4389 #define CAN_F1R2_FB20_Pos (20U)
4390 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4391 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4392 #define CAN_F1R2_FB21_Pos (21U)
4393 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4394 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4395 #define CAN_F1R2_FB22_Pos (22U)
4396 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4397 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4398 #define CAN_F1R2_FB23_Pos (23U)
4399 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4400 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4401 #define CAN_F1R2_FB24_Pos (24U)
4402 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4403 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4404 #define CAN_F1R2_FB25_Pos (25U)
4405 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4406 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4407 #define CAN_F1R2_FB26_Pos (26U)
4408 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4409 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4410 #define CAN_F1R2_FB27_Pos (27U)
4411 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4412 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4413 #define CAN_F1R2_FB28_Pos (28U)
4414 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4415 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4416 #define CAN_F1R2_FB29_Pos (29U)
4417 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4418 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4419 #define CAN_F1R2_FB30_Pos (30U)
4420 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4421 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4422 #define CAN_F1R2_FB31_Pos (31U)
4423 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4424 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4425
4426 /******************* Bit definition for CAN_F2R2 register *******************/
4427 #define CAN_F2R2_FB0_Pos (0U)
4428 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4429 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4430 #define CAN_F2R2_FB1_Pos (1U)
4431 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4432 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4433 #define CAN_F2R2_FB2_Pos (2U)
4434 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4435 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4436 #define CAN_F2R2_FB3_Pos (3U)
4437 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4438 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4439 #define CAN_F2R2_FB4_Pos (4U)
4440 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4441 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4442 #define CAN_F2R2_FB5_Pos (5U)
4443 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4444 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4445 #define CAN_F2R2_FB6_Pos (6U)
4446 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4447 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4448 #define CAN_F2R2_FB7_Pos (7U)
4449 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4450 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4451 #define CAN_F2R2_FB8_Pos (8U)
4452 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4453 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4454 #define CAN_F2R2_FB9_Pos (9U)
4455 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4456 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4457 #define CAN_F2R2_FB10_Pos (10U)
4458 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4459 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4460 #define CAN_F2R2_FB11_Pos (11U)
4461 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4462 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4463 #define CAN_F2R2_FB12_Pos (12U)
4464 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4465 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4466 #define CAN_F2R2_FB13_Pos (13U)
4467 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4468 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4469 #define CAN_F2R2_FB14_Pos (14U)
4470 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4471 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4472 #define CAN_F2R2_FB15_Pos (15U)
4473 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4474 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4475 #define CAN_F2R2_FB16_Pos (16U)
4476 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4477 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4478 #define CAN_F2R2_FB17_Pos (17U)
4479 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4480 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4481 #define CAN_F2R2_FB18_Pos (18U)
4482 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4483 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4484 #define CAN_F2R2_FB19_Pos (19U)
4485 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4486 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4487 #define CAN_F2R2_FB20_Pos (20U)
4488 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4489 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4490 #define CAN_F2R2_FB21_Pos (21U)
4491 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4492 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4493 #define CAN_F2R2_FB22_Pos (22U)
4494 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4495 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4496 #define CAN_F2R2_FB23_Pos (23U)
4497 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4498 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4499 #define CAN_F2R2_FB24_Pos (24U)
4500 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4501 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4502 #define CAN_F2R2_FB25_Pos (25U)
4503 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4504 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4505 #define CAN_F2R2_FB26_Pos (26U)
4506 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4507 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4508 #define CAN_F2R2_FB27_Pos (27U)
4509 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4510 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4511 #define CAN_F2R2_FB28_Pos (28U)
4512 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4513 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4514 #define CAN_F2R2_FB29_Pos (29U)
4515 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4516 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4517 #define CAN_F2R2_FB30_Pos (30U)
4518 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4519 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4520 #define CAN_F2R2_FB31_Pos (31U)
4521 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4522 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4523
4524 /******************* Bit definition for CAN_F3R2 register *******************/
4525 #define CAN_F3R2_FB0_Pos (0U)
4526 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4527 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4528 #define CAN_F3R2_FB1_Pos (1U)
4529 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4530 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4531 #define CAN_F3R2_FB2_Pos (2U)
4532 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4533 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4534 #define CAN_F3R2_FB3_Pos (3U)
4535 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4536 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4537 #define CAN_F3R2_FB4_Pos (4U)
4538 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4539 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4540 #define CAN_F3R2_FB5_Pos (5U)
4541 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4542 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4543 #define CAN_F3R2_FB6_Pos (6U)
4544 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4545 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4546 #define CAN_F3R2_FB7_Pos (7U)
4547 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4548 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4549 #define CAN_F3R2_FB8_Pos (8U)
4550 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4551 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4552 #define CAN_F3R2_FB9_Pos (9U)
4553 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4554 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4555 #define CAN_F3R2_FB10_Pos (10U)
4556 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4557 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4558 #define CAN_F3R2_FB11_Pos (11U)
4559 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4560 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4561 #define CAN_F3R2_FB12_Pos (12U)
4562 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4563 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4564 #define CAN_F3R2_FB13_Pos (13U)
4565 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4566 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4567 #define CAN_F3R2_FB14_Pos (14U)
4568 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4569 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4570 #define CAN_F3R2_FB15_Pos (15U)
4571 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4572 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4573 #define CAN_F3R2_FB16_Pos (16U)
4574 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4575 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4576 #define CAN_F3R2_FB17_Pos (17U)
4577 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4578 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4579 #define CAN_F3R2_FB18_Pos (18U)
4580 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4581 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4582 #define CAN_F3R2_FB19_Pos (19U)
4583 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4584 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4585 #define CAN_F3R2_FB20_Pos (20U)
4586 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4587 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4588 #define CAN_F3R2_FB21_Pos (21U)
4589 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4590 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4591 #define CAN_F3R2_FB22_Pos (22U)
4592 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4593 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4594 #define CAN_F3R2_FB23_Pos (23U)
4595 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4596 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4597 #define CAN_F3R2_FB24_Pos (24U)
4598 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4599 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4600 #define CAN_F3R2_FB25_Pos (25U)
4601 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4602 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4603 #define CAN_F3R2_FB26_Pos (26U)
4604 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4605 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4606 #define CAN_F3R2_FB27_Pos (27U)
4607 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4608 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4609 #define CAN_F3R2_FB28_Pos (28U)
4610 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4611 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4612 #define CAN_F3R2_FB29_Pos (29U)
4613 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4614 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4615 #define CAN_F3R2_FB30_Pos (30U)
4616 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4617 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4618 #define CAN_F3R2_FB31_Pos (31U)
4619 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4620 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4621
4622 /******************* Bit definition for CAN_F4R2 register *******************/
4623 #define CAN_F4R2_FB0_Pos (0U)
4624 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4625 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4626 #define CAN_F4R2_FB1_Pos (1U)
4627 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4628 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4629 #define CAN_F4R2_FB2_Pos (2U)
4630 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4631 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4632 #define CAN_F4R2_FB3_Pos (3U)
4633 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4634 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4635 #define CAN_F4R2_FB4_Pos (4U)
4636 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4637 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4638 #define CAN_F4R2_FB5_Pos (5U)
4639 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4640 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4641 #define CAN_F4R2_FB6_Pos (6U)
4642 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4643 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4644 #define CAN_F4R2_FB7_Pos (7U)
4645 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4646 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4647 #define CAN_F4R2_FB8_Pos (8U)
4648 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4649 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4650 #define CAN_F4R2_FB9_Pos (9U)
4651 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4652 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4653 #define CAN_F4R2_FB10_Pos (10U)
4654 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4655 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4656 #define CAN_F4R2_FB11_Pos (11U)
4657 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4658 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4659 #define CAN_F4R2_FB12_Pos (12U)
4660 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4661 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4662 #define CAN_F4R2_FB13_Pos (13U)
4663 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4664 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4665 #define CAN_F4R2_FB14_Pos (14U)
4666 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4667 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4668 #define CAN_F4R2_FB15_Pos (15U)
4669 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4670 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4671 #define CAN_F4R2_FB16_Pos (16U)
4672 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4673 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4674 #define CAN_F4R2_FB17_Pos (17U)
4675 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4676 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4677 #define CAN_F4R2_FB18_Pos (18U)
4678 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4679 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4680 #define CAN_F4R2_FB19_Pos (19U)
4681 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4682 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4683 #define CAN_F4R2_FB20_Pos (20U)
4684 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4685 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4686 #define CAN_F4R2_FB21_Pos (21U)
4687 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4688 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4689 #define CAN_F4R2_FB22_Pos (22U)
4690 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4691 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4692 #define CAN_F4R2_FB23_Pos (23U)
4693 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4694 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4695 #define CAN_F4R2_FB24_Pos (24U)
4696 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4697 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4698 #define CAN_F4R2_FB25_Pos (25U)
4699 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4700 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4701 #define CAN_F4R2_FB26_Pos (26U)
4702 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4703 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4704 #define CAN_F4R2_FB27_Pos (27U)
4705 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4706 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4707 #define CAN_F4R2_FB28_Pos (28U)
4708 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4709 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4710 #define CAN_F4R2_FB29_Pos (29U)
4711 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4712 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4713 #define CAN_F4R2_FB30_Pos (30U)
4714 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4715 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4716 #define CAN_F4R2_FB31_Pos (31U)
4717 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4718 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4719
4720 /******************* Bit definition for CAN_F5R2 register *******************/
4721 #define CAN_F5R2_FB0_Pos (0U)
4722 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4723 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4724 #define CAN_F5R2_FB1_Pos (1U)
4725 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4726 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4727 #define CAN_F5R2_FB2_Pos (2U)
4728 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4729 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4730 #define CAN_F5R2_FB3_Pos (3U)
4731 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4732 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4733 #define CAN_F5R2_FB4_Pos (4U)
4734 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4735 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4736 #define CAN_F5R2_FB5_Pos (5U)
4737 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4738 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4739 #define CAN_F5R2_FB6_Pos (6U)
4740 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4741 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4742 #define CAN_F5R2_FB7_Pos (7U)
4743 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4744 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4745 #define CAN_F5R2_FB8_Pos (8U)
4746 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4747 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4748 #define CAN_F5R2_FB9_Pos (9U)
4749 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4750 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4751 #define CAN_F5R2_FB10_Pos (10U)
4752 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4753 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4754 #define CAN_F5R2_FB11_Pos (11U)
4755 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4756 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4757 #define CAN_F5R2_FB12_Pos (12U)
4758 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4759 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4760 #define CAN_F5R2_FB13_Pos (13U)
4761 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4762 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4763 #define CAN_F5R2_FB14_Pos (14U)
4764 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4765 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4766 #define CAN_F5R2_FB15_Pos (15U)
4767 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4768 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4769 #define CAN_F5R2_FB16_Pos (16U)
4770 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4771 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4772 #define CAN_F5R2_FB17_Pos (17U)
4773 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4774 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4775 #define CAN_F5R2_FB18_Pos (18U)
4776 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4777 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4778 #define CAN_F5R2_FB19_Pos (19U)
4779 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4780 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4781 #define CAN_F5R2_FB20_Pos (20U)
4782 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4783 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4784 #define CAN_F5R2_FB21_Pos (21U)
4785 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4786 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4787 #define CAN_F5R2_FB22_Pos (22U)
4788 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4789 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4790 #define CAN_F5R2_FB23_Pos (23U)
4791 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4792 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4793 #define CAN_F5R2_FB24_Pos (24U)
4794 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4795 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4796 #define CAN_F5R2_FB25_Pos (25U)
4797 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4798 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4799 #define CAN_F5R2_FB26_Pos (26U)
4800 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4801 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4802 #define CAN_F5R2_FB27_Pos (27U)
4803 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4804 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4805 #define CAN_F5R2_FB28_Pos (28U)
4806 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4807 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4808 #define CAN_F5R2_FB29_Pos (29U)
4809 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4810 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4811 #define CAN_F5R2_FB30_Pos (30U)
4812 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4813 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4814 #define CAN_F5R2_FB31_Pos (31U)
4815 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4816 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4817
4818 /******************* Bit definition for CAN_F6R2 register *******************/
4819 #define CAN_F6R2_FB0_Pos (0U)
4820 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4821 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4822 #define CAN_F6R2_FB1_Pos (1U)
4823 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4824 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4825 #define CAN_F6R2_FB2_Pos (2U)
4826 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4827 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4828 #define CAN_F6R2_FB3_Pos (3U)
4829 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4830 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4831 #define CAN_F6R2_FB4_Pos (4U)
4832 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4833 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4834 #define CAN_F6R2_FB5_Pos (5U)
4835 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4836 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4837 #define CAN_F6R2_FB6_Pos (6U)
4838 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4839 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4840 #define CAN_F6R2_FB7_Pos (7U)
4841 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4842 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4843 #define CAN_F6R2_FB8_Pos (8U)
4844 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4845 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4846 #define CAN_F6R2_FB9_Pos (9U)
4847 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4848 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4849 #define CAN_F6R2_FB10_Pos (10U)
4850 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4851 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4852 #define CAN_F6R2_FB11_Pos (11U)
4853 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4854 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4855 #define CAN_F6R2_FB12_Pos (12U)
4856 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4857 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4858 #define CAN_F6R2_FB13_Pos (13U)
4859 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4860 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4861 #define CAN_F6R2_FB14_Pos (14U)
4862 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4863 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4864 #define CAN_F6R2_FB15_Pos (15U)
4865 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4866 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4867 #define CAN_F6R2_FB16_Pos (16U)
4868 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4869 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4870 #define CAN_F6R2_FB17_Pos (17U)
4871 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4872 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4873 #define CAN_F6R2_FB18_Pos (18U)
4874 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4875 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4876 #define CAN_F6R2_FB19_Pos (19U)
4877 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4878 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4879 #define CAN_F6R2_FB20_Pos (20U)
4880 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4881 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4882 #define CAN_F6R2_FB21_Pos (21U)
4883 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4884 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4885 #define CAN_F6R2_FB22_Pos (22U)
4886 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4887 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4888 #define CAN_F6R2_FB23_Pos (23U)
4889 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4890 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4891 #define CAN_F6R2_FB24_Pos (24U)
4892 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4893 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4894 #define CAN_F6R2_FB25_Pos (25U)
4895 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4896 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4897 #define CAN_F6R2_FB26_Pos (26U)
4898 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4899 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4900 #define CAN_F6R2_FB27_Pos (27U)
4901 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4902 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4903 #define CAN_F6R2_FB28_Pos (28U)
4904 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
4905 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
4906 #define CAN_F6R2_FB29_Pos (29U)
4907 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
4908 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
4909 #define CAN_F6R2_FB30_Pos (30U)
4910 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
4911 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
4912 #define CAN_F6R2_FB31_Pos (31U)
4913 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
4914 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
4915
4916 /******************* Bit definition for CAN_F7R2 register *******************/
4917 #define CAN_F7R2_FB0_Pos (0U)
4918 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
4919 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
4920 #define CAN_F7R2_FB1_Pos (1U)
4921 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
4922 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
4923 #define CAN_F7R2_FB2_Pos (2U)
4924 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
4925 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
4926 #define CAN_F7R2_FB3_Pos (3U)
4927 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
4928 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
4929 #define CAN_F7R2_FB4_Pos (4U)
4930 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
4931 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
4932 #define CAN_F7R2_FB5_Pos (5U)
4933 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
4934 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
4935 #define CAN_F7R2_FB6_Pos (6U)
4936 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
4937 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
4938 #define CAN_F7R2_FB7_Pos (7U)
4939 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
4940 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
4941 #define CAN_F7R2_FB8_Pos (8U)
4942 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
4943 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
4944 #define CAN_F7R2_FB9_Pos (9U)
4945 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
4946 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
4947 #define CAN_F7R2_FB10_Pos (10U)
4948 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
4949 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
4950 #define CAN_F7R2_FB11_Pos (11U)
4951 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
4952 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
4953 #define CAN_F7R2_FB12_Pos (12U)
4954 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
4955 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
4956 #define CAN_F7R2_FB13_Pos (13U)
4957 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
4958 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
4959 #define CAN_F7R2_FB14_Pos (14U)
4960 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
4961 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
4962 #define CAN_F7R2_FB15_Pos (15U)
4963 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
4964 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
4965 #define CAN_F7R2_FB16_Pos (16U)
4966 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
4967 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
4968 #define CAN_F7R2_FB17_Pos (17U)
4969 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
4970 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
4971 #define CAN_F7R2_FB18_Pos (18U)
4972 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
4973 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
4974 #define CAN_F7R2_FB19_Pos (19U)
4975 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
4976 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
4977 #define CAN_F7R2_FB20_Pos (20U)
4978 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
4979 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
4980 #define CAN_F7R2_FB21_Pos (21U)
4981 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
4982 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
4983 #define CAN_F7R2_FB22_Pos (22U)
4984 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
4985 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
4986 #define CAN_F7R2_FB23_Pos (23U)
4987 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
4988 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
4989 #define CAN_F7R2_FB24_Pos (24U)
4990 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
4991 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
4992 #define CAN_F7R2_FB25_Pos (25U)
4993 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
4994 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
4995 #define CAN_F7R2_FB26_Pos (26U)
4996 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
4997 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
4998 #define CAN_F7R2_FB27_Pos (27U)
4999 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5000 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5001 #define CAN_F7R2_FB28_Pos (28U)
5002 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5003 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5004 #define CAN_F7R2_FB29_Pos (29U)
5005 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5006 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5007 #define CAN_F7R2_FB30_Pos (30U)
5008 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5009 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5010 #define CAN_F7R2_FB31_Pos (31U)
5011 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5012 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5013
5014 /******************* Bit definition for CAN_F8R2 register *******************/
5015 #define CAN_F8R2_FB0_Pos (0U)
5016 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5017 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5018 #define CAN_F8R2_FB1_Pos (1U)
5019 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5020 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5021 #define CAN_F8R2_FB2_Pos (2U)
5022 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5023 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5024 #define CAN_F8R2_FB3_Pos (3U)
5025 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5026 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5027 #define CAN_F8R2_FB4_Pos (4U)
5028 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5029 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5030 #define CAN_F8R2_FB5_Pos (5U)
5031 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5032 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5033 #define CAN_F8R2_FB6_Pos (6U)
5034 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5035 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5036 #define CAN_F8R2_FB7_Pos (7U)
5037 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5038 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5039 #define CAN_F8R2_FB8_Pos (8U)
5040 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5041 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5042 #define CAN_F8R2_FB9_Pos (9U)
5043 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5044 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5045 #define CAN_F8R2_FB10_Pos (10U)
5046 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5047 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5048 #define CAN_F8R2_FB11_Pos (11U)
5049 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5050 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5051 #define CAN_F8R2_FB12_Pos (12U)
5052 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5053 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5054 #define CAN_F8R2_FB13_Pos (13U)
5055 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5056 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5057 #define CAN_F8R2_FB14_Pos (14U)
5058 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5059 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5060 #define CAN_F8R2_FB15_Pos (15U)
5061 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5062 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5063 #define CAN_F8R2_FB16_Pos (16U)
5064 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5065 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5066 #define CAN_F8R2_FB17_Pos (17U)
5067 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5068 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5069 #define CAN_F8R2_FB18_Pos (18U)
5070 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5071 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5072 #define CAN_F8R2_FB19_Pos (19U)
5073 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5074 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5075 #define CAN_F8R2_FB20_Pos (20U)
5076 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5077 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5078 #define CAN_F8R2_FB21_Pos (21U)
5079 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5080 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5081 #define CAN_F8R2_FB22_Pos (22U)
5082 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5083 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5084 #define CAN_F8R2_FB23_Pos (23U)
5085 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5086 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5087 #define CAN_F8R2_FB24_Pos (24U)
5088 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5089 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5090 #define CAN_F8R2_FB25_Pos (25U)
5091 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5092 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5093 #define CAN_F8R2_FB26_Pos (26U)
5094 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5095 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5096 #define CAN_F8R2_FB27_Pos (27U)
5097 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5098 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5099 #define CAN_F8R2_FB28_Pos (28U)
5100 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5101 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5102 #define CAN_F8R2_FB29_Pos (29U)
5103 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5104 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5105 #define CAN_F8R2_FB30_Pos (30U)
5106 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5107 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5108 #define CAN_F8R2_FB31_Pos (31U)
5109 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5110 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5111
5112 /******************* Bit definition for CAN_F9R2 register *******************/
5113 #define CAN_F9R2_FB0_Pos (0U)
5114 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5115 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5116 #define CAN_F9R2_FB1_Pos (1U)
5117 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5118 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5119 #define CAN_F9R2_FB2_Pos (2U)
5120 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5121 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5122 #define CAN_F9R2_FB3_Pos (3U)
5123 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5124 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5125 #define CAN_F9R2_FB4_Pos (4U)
5126 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5127 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5128 #define CAN_F9R2_FB5_Pos (5U)
5129 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5130 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5131 #define CAN_F9R2_FB6_Pos (6U)
5132 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5133 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5134 #define CAN_F9R2_FB7_Pos (7U)
5135 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5136 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5137 #define CAN_F9R2_FB8_Pos (8U)
5138 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5139 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5140 #define CAN_F9R2_FB9_Pos (9U)
5141 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5142 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5143 #define CAN_F9R2_FB10_Pos (10U)
5144 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5145 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5146 #define CAN_F9R2_FB11_Pos (11U)
5147 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5148 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5149 #define CAN_F9R2_FB12_Pos (12U)
5150 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5151 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5152 #define CAN_F9R2_FB13_Pos (13U)
5153 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5154 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5155 #define CAN_F9R2_FB14_Pos (14U)
5156 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5157 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5158 #define CAN_F9R2_FB15_Pos (15U)
5159 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5160 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5161 #define CAN_F9R2_FB16_Pos (16U)
5162 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5163 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5164 #define CAN_F9R2_FB17_Pos (17U)
5165 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5166 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5167 #define CAN_F9R2_FB18_Pos (18U)
5168 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5169 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5170 #define CAN_F9R2_FB19_Pos (19U)
5171 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5172 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5173 #define CAN_F9R2_FB20_Pos (20U)
5174 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5175 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5176 #define CAN_F9R2_FB21_Pos (21U)
5177 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5178 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5179 #define CAN_F9R2_FB22_Pos (22U)
5180 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5181 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5182 #define CAN_F9R2_FB23_Pos (23U)
5183 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5184 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5185 #define CAN_F9R2_FB24_Pos (24U)
5186 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5187 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5188 #define CAN_F9R2_FB25_Pos (25U)
5189 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5190 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5191 #define CAN_F9R2_FB26_Pos (26U)
5192 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5193 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5194 #define CAN_F9R2_FB27_Pos (27U)
5195 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5196 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5197 #define CAN_F9R2_FB28_Pos (28U)
5198 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5199 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5200 #define CAN_F9R2_FB29_Pos (29U)
5201 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5202 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5203 #define CAN_F9R2_FB30_Pos (30U)
5204 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5205 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5206 #define CAN_F9R2_FB31_Pos (31U)
5207 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5208 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5209
5210 /******************* Bit definition for CAN_F10R2 register ******************/
5211 #define CAN_F10R2_FB0_Pos (0U)
5212 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5213 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5214 #define CAN_F10R2_FB1_Pos (1U)
5215 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5216 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5217 #define CAN_F10R2_FB2_Pos (2U)
5218 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5219 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5220 #define CAN_F10R2_FB3_Pos (3U)
5221 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5222 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5223 #define CAN_F10R2_FB4_Pos (4U)
5224 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5225 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5226 #define CAN_F10R2_FB5_Pos (5U)
5227 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5228 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5229 #define CAN_F10R2_FB6_Pos (6U)
5230 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5231 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5232 #define CAN_F10R2_FB7_Pos (7U)
5233 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5234 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5235 #define CAN_F10R2_FB8_Pos (8U)
5236 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5237 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5238 #define CAN_F10R2_FB9_Pos (9U)
5239 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5240 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5241 #define CAN_F10R2_FB10_Pos (10U)
5242 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5243 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5244 #define CAN_F10R2_FB11_Pos (11U)
5245 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5246 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5247 #define CAN_F10R2_FB12_Pos (12U)
5248 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5249 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5250 #define CAN_F10R2_FB13_Pos (13U)
5251 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5252 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5253 #define CAN_F10R2_FB14_Pos (14U)
5254 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5255 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5256 #define CAN_F10R2_FB15_Pos (15U)
5257 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5258 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5259 #define CAN_F10R2_FB16_Pos (16U)
5260 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5261 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5262 #define CAN_F10R2_FB17_Pos (17U)
5263 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5264 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5265 #define CAN_F10R2_FB18_Pos (18U)
5266 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5267 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5268 #define CAN_F10R2_FB19_Pos (19U)
5269 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5270 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5271 #define CAN_F10R2_FB20_Pos (20U)
5272 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5273 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5274 #define CAN_F10R2_FB21_Pos (21U)
5275 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5276 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5277 #define CAN_F10R2_FB22_Pos (22U)
5278 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5279 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5280 #define CAN_F10R2_FB23_Pos (23U)
5281 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5282 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5283 #define CAN_F10R2_FB24_Pos (24U)
5284 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5285 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5286 #define CAN_F10R2_FB25_Pos (25U)
5287 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5288 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5289 #define CAN_F10R2_FB26_Pos (26U)
5290 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5291 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5292 #define CAN_F10R2_FB27_Pos (27U)
5293 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5294 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5295 #define CAN_F10R2_FB28_Pos (28U)
5296 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5297 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5298 #define CAN_F10R2_FB29_Pos (29U)
5299 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5300 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5301 #define CAN_F10R2_FB30_Pos (30U)
5302 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5303 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5304 #define CAN_F10R2_FB31_Pos (31U)
5305 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5306 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5307
5308 /******************* Bit definition for CAN_F11R2 register ******************/
5309 #define CAN_F11R2_FB0_Pos (0U)
5310 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5311 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5312 #define CAN_F11R2_FB1_Pos (1U)
5313 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5314 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5315 #define CAN_F11R2_FB2_Pos (2U)
5316 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5317 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5318 #define CAN_F11R2_FB3_Pos (3U)
5319 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5320 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5321 #define CAN_F11R2_FB4_Pos (4U)
5322 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5323 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5324 #define CAN_F11R2_FB5_Pos (5U)
5325 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5326 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5327 #define CAN_F11R2_FB6_Pos (6U)
5328 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5329 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5330 #define CAN_F11R2_FB7_Pos (7U)
5331 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5332 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5333 #define CAN_F11R2_FB8_Pos (8U)
5334 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5335 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5336 #define CAN_F11R2_FB9_Pos (9U)
5337 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5338 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5339 #define CAN_F11R2_FB10_Pos (10U)
5340 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5341 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5342 #define CAN_F11R2_FB11_Pos (11U)
5343 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5344 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5345 #define CAN_F11R2_FB12_Pos (12U)
5346 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5347 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5348 #define CAN_F11R2_FB13_Pos (13U)
5349 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5350 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5351 #define CAN_F11R2_FB14_Pos (14U)
5352 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5353 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5354 #define CAN_F11R2_FB15_Pos (15U)
5355 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5356 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5357 #define CAN_F11R2_FB16_Pos (16U)
5358 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5359 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5360 #define CAN_F11R2_FB17_Pos (17U)
5361 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5362 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5363 #define CAN_F11R2_FB18_Pos (18U)
5364 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5365 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5366 #define CAN_F11R2_FB19_Pos (19U)
5367 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5368 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5369 #define CAN_F11R2_FB20_Pos (20U)
5370 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5371 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5372 #define CAN_F11R2_FB21_Pos (21U)
5373 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5374 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5375 #define CAN_F11R2_FB22_Pos (22U)
5376 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5377 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5378 #define CAN_F11R2_FB23_Pos (23U)
5379 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5380 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5381 #define CAN_F11R2_FB24_Pos (24U)
5382 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5383 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5384 #define CAN_F11R2_FB25_Pos (25U)
5385 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5386 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5387 #define CAN_F11R2_FB26_Pos (26U)
5388 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5389 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5390 #define CAN_F11R2_FB27_Pos (27U)
5391 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5392 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5393 #define CAN_F11R2_FB28_Pos (28U)
5394 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5395 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5396 #define CAN_F11R2_FB29_Pos (29U)
5397 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5398 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5399 #define CAN_F11R2_FB30_Pos (30U)
5400 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5401 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5402 #define CAN_F11R2_FB31_Pos (31U)
5403 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5404 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5405
5406 /******************* Bit definition for CAN_F12R2 register ******************/
5407 #define CAN_F12R2_FB0_Pos (0U)
5408 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5409 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5410 #define CAN_F12R2_FB1_Pos (1U)
5411 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5412 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5413 #define CAN_F12R2_FB2_Pos (2U)
5414 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5415 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5416 #define CAN_F12R2_FB3_Pos (3U)
5417 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5418 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5419 #define CAN_F12R2_FB4_Pos (4U)
5420 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5421 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5422 #define CAN_F12R2_FB5_Pos (5U)
5423 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5424 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5425 #define CAN_F12R2_FB6_Pos (6U)
5426 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5427 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5428 #define CAN_F12R2_FB7_Pos (7U)
5429 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5430 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5431 #define CAN_F12R2_FB8_Pos (8U)
5432 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5433 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5434 #define CAN_F12R2_FB9_Pos (9U)
5435 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5436 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5437 #define CAN_F12R2_FB10_Pos (10U)
5438 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5439 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5440 #define CAN_F12R2_FB11_Pos (11U)
5441 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5442 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5443 #define CAN_F12R2_FB12_Pos (12U)
5444 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5445 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5446 #define CAN_F12R2_FB13_Pos (13U)
5447 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5448 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5449 #define CAN_F12R2_FB14_Pos (14U)
5450 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5451 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5452 #define CAN_F12R2_FB15_Pos (15U)
5453 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5454 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5455 #define CAN_F12R2_FB16_Pos (16U)
5456 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5457 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5458 #define CAN_F12R2_FB17_Pos (17U)
5459 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5460 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5461 #define CAN_F12R2_FB18_Pos (18U)
5462 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5463 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5464 #define CAN_F12R2_FB19_Pos (19U)
5465 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5466 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5467 #define CAN_F12R2_FB20_Pos (20U)
5468 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5469 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5470 #define CAN_F12R2_FB21_Pos (21U)
5471 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5472 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5473 #define CAN_F12R2_FB22_Pos (22U)
5474 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5475 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5476 #define CAN_F12R2_FB23_Pos (23U)
5477 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5478 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5479 #define CAN_F12R2_FB24_Pos (24U)
5480 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5481 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5482 #define CAN_F12R2_FB25_Pos (25U)
5483 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5484 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5485 #define CAN_F12R2_FB26_Pos (26U)
5486 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5487 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5488 #define CAN_F12R2_FB27_Pos (27U)
5489 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5490 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5491 #define CAN_F12R2_FB28_Pos (28U)
5492 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5493 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5494 #define CAN_F12R2_FB29_Pos (29U)
5495 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5496 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5497 #define CAN_F12R2_FB30_Pos (30U)
5498 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5499 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5500 #define CAN_F12R2_FB31_Pos (31U)
5501 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5502 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5503
5504 /******************* Bit definition for CAN_F13R2 register ******************/
5505 #define CAN_F13R2_FB0_Pos (0U)
5506 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5507 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5508 #define CAN_F13R2_FB1_Pos (1U)
5509 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5510 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5511 #define CAN_F13R2_FB2_Pos (2U)
5512 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5513 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5514 #define CAN_F13R2_FB3_Pos (3U)
5515 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5516 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5517 #define CAN_F13R2_FB4_Pos (4U)
5518 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5519 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5520 #define CAN_F13R2_FB5_Pos (5U)
5521 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5522 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5523 #define CAN_F13R2_FB6_Pos (6U)
5524 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5525 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5526 #define CAN_F13R2_FB7_Pos (7U)
5527 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5528 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5529 #define CAN_F13R2_FB8_Pos (8U)
5530 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5531 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5532 #define CAN_F13R2_FB9_Pos (9U)
5533 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5534 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5535 #define CAN_F13R2_FB10_Pos (10U)
5536 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5537 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5538 #define CAN_F13R2_FB11_Pos (11U)
5539 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5540 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5541 #define CAN_F13R2_FB12_Pos (12U)
5542 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5543 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5544 #define CAN_F13R2_FB13_Pos (13U)
5545 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5546 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5547 #define CAN_F13R2_FB14_Pos (14U)
5548 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5549 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5550 #define CAN_F13R2_FB15_Pos (15U)
5551 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5552 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5553 #define CAN_F13R2_FB16_Pos (16U)
5554 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5555 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5556 #define CAN_F13R2_FB17_Pos (17U)
5557 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5558 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5559 #define CAN_F13R2_FB18_Pos (18U)
5560 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5561 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5562 #define CAN_F13R2_FB19_Pos (19U)
5563 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5564 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5565 #define CAN_F13R2_FB20_Pos (20U)
5566 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5567 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5568 #define CAN_F13R2_FB21_Pos (21U)
5569 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5570 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5571 #define CAN_F13R2_FB22_Pos (22U)
5572 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5573 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5574 #define CAN_F13R2_FB23_Pos (23U)
5575 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5576 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5577 #define CAN_F13R2_FB24_Pos (24U)
5578 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5579 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5580 #define CAN_F13R2_FB25_Pos (25U)
5581 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5582 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5583 #define CAN_F13R2_FB26_Pos (26U)
5584 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5585 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5586 #define CAN_F13R2_FB27_Pos (27U)
5587 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5588 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5589 #define CAN_F13R2_FB28_Pos (28U)
5590 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5591 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5592 #define CAN_F13R2_FB29_Pos (29U)
5593 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5594 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5595 #define CAN_F13R2_FB30_Pos (30U)
5596 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5597 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5598 #define CAN_F13R2_FB31_Pos (31U)
5599 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5600 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5601
5602 /******************************************************************************/
5603 /* */
5604 /* CRC calculation unit */
5605 /* */
5606 /******************************************************************************/
5607 /******************* Bit definition for CRC_DR register *********************/
5608 #define CRC_DR_DR_Pos (0U)
5609 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5610 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5611
5612
5613 /******************* Bit definition for CRC_IDR register ********************/
5614 #define CRC_IDR_IDR_Pos (0U)
5615 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5616 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5617
5618
5619 /******************** Bit definition for CRC_CR register ********************/
5620 #define CRC_CR_RESET_Pos (0U)
5621 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5622 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5623
5624 /******************************************************************************/
5625 /* */
5626 /* Crypto Processor */
5627 /* */
5628 /******************************************************************************/
5629 /******************* Bits definition for CRYP_CR register ********************/
5630 #define CRYP_CR_ALGODIR_Pos (2U)
5631 #define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
5632 #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5633
5634 #define CRYP_CR_ALGOMODE_Pos (3U)
5635 #define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
5636 #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5637 #define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
5638 #define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
5639 #define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
5640 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
5641 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5642 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5643 #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5644 #define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5645 #define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5646 #define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5647 #define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5648 #define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5649 #define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5650 #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5651 #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5652 #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5653 #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5654 #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5655 #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5656 #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5657 #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5658 #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5659 #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5660 #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5661 #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5662
5663 #define CRYP_CR_DATATYPE_Pos (6U)
5664 #define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
5665 #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5666 #define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
5667 #define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
5668 #define CRYP_CR_KEYSIZE_Pos (8U)
5669 #define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
5670 #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5671 #define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
5672 #define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
5673 #define CRYP_CR_FFLUSH_Pos (14U)
5674 #define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
5675 #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5676 #define CRYP_CR_CRYPEN_Pos (15U)
5677 #define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
5678 #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5679
5680 #define CRYP_CR_GCM_CCMPH_Pos (16U)
5681 #define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
5682 #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5683 #define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
5684 #define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
5685 #define CRYP_CR_ALGOMODE_3 0x00080000U
5686
5687 /****************** Bits definition for CRYP_SR register *********************/
5688 #define CRYP_SR_IFEM_Pos (0U)
5689 #define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
5690 #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5691 #define CRYP_SR_IFNF_Pos (1U)
5692 #define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
5693 #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5694 #define CRYP_SR_OFNE_Pos (2U)
5695 #define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
5696 #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5697 #define CRYP_SR_OFFU_Pos (3U)
5698 #define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
5699 #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5700 #define CRYP_SR_BUSY_Pos (4U)
5701 #define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
5702 #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5703 /****************** Bits definition for CRYP_DMACR register ******************/
5704 #define CRYP_DMACR_DIEN_Pos (0U)
5705 #define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
5706 #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5707 #define CRYP_DMACR_DOEN_Pos (1U)
5708 #define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
5709 #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5710 /***************** Bits definition for CRYP_IMSCR register ******************/
5711 #define CRYP_IMSCR_INIM_Pos (0U)
5712 #define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
5713 #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5714 #define CRYP_IMSCR_OUTIM_Pos (1U)
5715 #define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
5716 #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5717 /****************** Bits definition for CRYP_RISR register *******************/
5718 #define CRYP_RISR_OUTRIS_Pos (0U)
5719 #define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
5720 #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5721 #define CRYP_RISR_INRIS_Pos (1U)
5722 #define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
5723 #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5724 /****************** Bits definition for CRYP_MISR register *******************/
5725 #define CRYP_MISR_INMIS_Pos (0U)
5726 #define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
5727 #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5728 #define CRYP_MISR_OUTMIS_Pos (1U)
5729 #define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
5730 #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5731
5732 /******************************************************************************/
5733 /* */
5734 /* Digital to Analog Converter */
5735 /* */
5736 /******************************************************************************/
5737 /*
5738 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5739 */
5740 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5741 /******************** Bit definition for DAC_CR register ********************/
5742 #define DAC_CR_EN1_Pos (0U)
5743 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5744 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5745 #define DAC_CR_BOFF1_Pos (1U)
5746 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5747 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5748 #define DAC_CR_TEN1_Pos (2U)
5749 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5750 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5751
5752 #define DAC_CR_TSEL1_Pos (3U)
5753 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5754 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5755 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5756 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5757 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5758
5759 #define DAC_CR_WAVE1_Pos (6U)
5760 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5761 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5762 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5763 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5764
5765 #define DAC_CR_MAMP1_Pos (8U)
5766 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5767 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5768 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5769 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5770 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5771 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5772
5773 #define DAC_CR_DMAEN1_Pos (12U)
5774 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5775 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5776 #define DAC_CR_DMAUDRIE1_Pos (13U)
5777 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5778 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5779 #define DAC_CR_EN2_Pos (16U)
5780 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5781 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5782 #define DAC_CR_BOFF2_Pos (17U)
5783 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5784 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5785 #define DAC_CR_TEN2_Pos (18U)
5786 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5787 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5788
5789 #define DAC_CR_TSEL2_Pos (19U)
5790 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5791 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5792 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5793 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5794 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5795
5796 #define DAC_CR_WAVE2_Pos (22U)
5797 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5798 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5799 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5800 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5801
5802 #define DAC_CR_MAMP2_Pos (24U)
5803 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5804 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5805 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5806 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5807 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5808 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5809
5810 #define DAC_CR_DMAEN2_Pos (28U)
5811 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5812 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5813 #define DAC_CR_DMAUDRIE2_Pos (29U)
5814 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5815 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5816
5817 /***************** Bit definition for DAC_SWTRIGR register ******************/
5818 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5819 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5820 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5821 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5822 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5823 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5824
5825 /***************** Bit definition for DAC_DHR12R1 register ******************/
5826 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5827 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5828 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5829
5830 /***************** Bit definition for DAC_DHR12L1 register ******************/
5831 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5832 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5833 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5834
5835 /****************** Bit definition for DAC_DHR8R1 register ******************/
5836 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5837 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5838 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5839
5840 /***************** Bit definition for DAC_DHR12R2 register ******************/
5841 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5842 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5843 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5844
5845 /***************** Bit definition for DAC_DHR12L2 register ******************/
5846 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5847 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5848 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5849
5850 /****************** Bit definition for DAC_DHR8R2 register ******************/
5851 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5852 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5853 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5854
5855 /***************** Bit definition for DAC_DHR12RD register ******************/
5856 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5857 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5858 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5859 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5860 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5861 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5862
5863 /***************** Bit definition for DAC_DHR12LD register ******************/
5864 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5865 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5866 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5867 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5868 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5869 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5870
5871 /****************** Bit definition for DAC_DHR8RD register ******************/
5872 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5873 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5874 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5875 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5876 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5877 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5878
5879 /******************* Bit definition for DAC_DOR1 register *******************/
5880 #define DAC_DOR1_DACC1DOR_Pos (0U)
5881 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5882 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5883
5884 /******************* Bit definition for DAC_DOR2 register *******************/
5885 #define DAC_DOR2_DACC2DOR_Pos (0U)
5886 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5887 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5888
5889 /******************** Bit definition for DAC_SR register ********************/
5890 #define DAC_SR_DMAUDR1_Pos (13U)
5891 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5892 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5893 #define DAC_SR_DMAUDR2_Pos (29U)
5894 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5895 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5896
5897 /******************************************************************************/
5898 /* */
5899 /* DCMI */
5900 /* */
5901 /******************************************************************************/
5902 /******************** Bits definition for DCMI_CR register ******************/
5903 #define DCMI_CR_CAPTURE_Pos (0U)
5904 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5905 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5906 #define DCMI_CR_CM_Pos (1U)
5907 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5908 #define DCMI_CR_CM DCMI_CR_CM_Msk
5909 #define DCMI_CR_CROP_Pos (2U)
5910 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5911 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
5912 #define DCMI_CR_JPEG_Pos (3U)
5913 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5914 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5915 #define DCMI_CR_ESS_Pos (4U)
5916 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5917 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
5918 #define DCMI_CR_PCKPOL_Pos (5U)
5919 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5920 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5921 #define DCMI_CR_HSPOL_Pos (6U)
5922 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5923 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5924 #define DCMI_CR_VSPOL_Pos (7U)
5925 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5926 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5927 #define DCMI_CR_FCRC_0 0x00000100U
5928 #define DCMI_CR_FCRC_1 0x00000200U
5929 #define DCMI_CR_EDM_0 0x00000400U
5930 #define DCMI_CR_EDM_1 0x00000800U
5931 #define DCMI_CR_ENABLE_Pos (14U)
5932 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5933 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5934
5935 /******************** Bits definition for DCMI_SR register ******************/
5936 #define DCMI_SR_HSYNC_Pos (0U)
5937 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
5938 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5939 #define DCMI_SR_VSYNC_Pos (1U)
5940 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
5941 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5942 #define DCMI_SR_FNE_Pos (2U)
5943 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
5944 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
5945
5946 /******************** Bits definition for DCMI_RIS register *****************/
5947 #define DCMI_RIS_FRAME_RIS_Pos (0U)
5948 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
5949 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5950 #define DCMI_RIS_OVR_RIS_Pos (1U)
5951 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
5952 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5953 #define DCMI_RIS_ERR_RIS_Pos (2U)
5954 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
5955 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5956 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
5957 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
5958 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5959 #define DCMI_RIS_LINE_RIS_Pos (4U)
5960 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
5961 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5962 /* Legacy defines */
5963 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5964 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5965 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5966 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5967 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5968 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5969
5970 /******************** Bits definition for DCMI_IER register *****************/
5971 #define DCMI_IER_FRAME_IE_Pos (0U)
5972 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
5973 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5974 #define DCMI_IER_OVR_IE_Pos (1U)
5975 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
5976 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5977 #define DCMI_IER_ERR_IE_Pos (2U)
5978 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
5979 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5980 #define DCMI_IER_VSYNC_IE_Pos (3U)
5981 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
5982 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5983 #define DCMI_IER_LINE_IE_Pos (4U)
5984 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
5985 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5986 /* Legacy defines */
5987 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5988
5989 /******************** Bits definition for DCMI_MIS register *****************/
5990 #define DCMI_MIS_FRAME_MIS_Pos (0U)
5991 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
5992 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5993 #define DCMI_MIS_OVR_MIS_Pos (1U)
5994 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
5995 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5996 #define DCMI_MIS_ERR_MIS_Pos (2U)
5997 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
5998 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5999 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
6000 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6001 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6002 #define DCMI_MIS_LINE_MIS_Pos (4U)
6003 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6004 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6005
6006 /* Legacy defines */
6007 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
6008 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
6009 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
6010 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
6011 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
6012
6013 /******************** Bits definition for DCMI_ICR register *****************/
6014 #define DCMI_ICR_FRAME_ISC_Pos (0U)
6015 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6016 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6017 #define DCMI_ICR_OVR_ISC_Pos (1U)
6018 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6019 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6020 #define DCMI_ICR_ERR_ISC_Pos (2U)
6021 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6022 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6023 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
6024 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6025 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6026 #define DCMI_ICR_LINE_ISC_Pos (4U)
6027 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6028 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6029
6030 /* Legacy defines */
6031 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
6032
6033 /******************** Bits definition for DCMI_ESCR register ******************/
6034 #define DCMI_ESCR_FSC_Pos (0U)
6035 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6036 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6037 #define DCMI_ESCR_LSC_Pos (8U)
6038 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6039 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6040 #define DCMI_ESCR_LEC_Pos (16U)
6041 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6042 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6043 #define DCMI_ESCR_FEC_Pos (24U)
6044 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6045 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6046
6047 /******************** Bits definition for DCMI_ESUR register ******************/
6048 #define DCMI_ESUR_FSU_Pos (0U)
6049 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6050 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6051 #define DCMI_ESUR_LSU_Pos (8U)
6052 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6053 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6054 #define DCMI_ESUR_LEU_Pos (16U)
6055 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6056 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6057 #define DCMI_ESUR_FEU_Pos (24U)
6058 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6059 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6060
6061 /******************** Bits definition for DCMI_CWSTRT register ******************/
6062 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6063 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6064 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6065 #define DCMI_CWSTRT_VST_Pos (16U)
6066 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6067 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6068
6069 /******************** Bits definition for DCMI_CWSIZE register ******************/
6070 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
6071 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6072 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6073 #define DCMI_CWSIZE_VLINE_Pos (16U)
6074 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6075 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6076
6077 /******************** Bits definition for DCMI_DR register *********************/
6078 #define DCMI_DR_BYTE0_Pos (0U)
6079 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6080 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6081 #define DCMI_DR_BYTE1_Pos (8U)
6082 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6083 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6084 #define DCMI_DR_BYTE2_Pos (16U)
6085 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6086 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6087 #define DCMI_DR_BYTE3_Pos (24U)
6088 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6089 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6090
6091 /******************************************************************************/
6092 /* */
6093 /* DMA Controller */
6094 /* */
6095 /******************************************************************************/
6096 /******************** Bits definition for DMA_SxCR register *****************/
6097 #define DMA_SxCR_CHSEL_Pos (25U)
6098 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
6099 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6100 #define DMA_SxCR_CHSEL_0 0x02000000U
6101 #define DMA_SxCR_CHSEL_1 0x04000000U
6102 #define DMA_SxCR_CHSEL_2 0x08000000U
6103 #define DMA_SxCR_MBURST_Pos (23U)
6104 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
6105 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6106 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6107 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6108 #define DMA_SxCR_PBURST_Pos (21U)
6109 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6110 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6111 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6112 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6113 #define DMA_SxCR_CT_Pos (19U)
6114 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6115 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
6116 #define DMA_SxCR_DBM_Pos (18U)
6117 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6118 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6119 #define DMA_SxCR_PL_Pos (16U)
6120 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6121 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
6122 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6123 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6124 #define DMA_SxCR_PINCOS_Pos (15U)
6125 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6126 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6127 #define DMA_SxCR_MSIZE_Pos (13U)
6128 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6129 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6130 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6131 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6132 #define DMA_SxCR_PSIZE_Pos (11U)
6133 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6134 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6135 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6136 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6137 #define DMA_SxCR_MINC_Pos (10U)
6138 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6139 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6140 #define DMA_SxCR_PINC_Pos (9U)
6141 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6142 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6143 #define DMA_SxCR_CIRC_Pos (8U)
6144 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6145 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6146 #define DMA_SxCR_DIR_Pos (6U)
6147 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6148 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6149 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6150 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6151 #define DMA_SxCR_PFCTRL_Pos (5U)
6152 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6153 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6154 #define DMA_SxCR_TCIE_Pos (4U)
6155 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6156 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6157 #define DMA_SxCR_HTIE_Pos (3U)
6158 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6159 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6160 #define DMA_SxCR_TEIE_Pos (2U)
6161 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6162 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6163 #define DMA_SxCR_DMEIE_Pos (1U)
6164 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6165 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6166 #define DMA_SxCR_EN_Pos (0U)
6167 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6168 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
6169
6170 /* Legacy defines */
6171 #define DMA_SxCR_ACK_Pos (20U)
6172 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
6173 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6174
6175 /******************** Bits definition for DMA_SxCNDTR register **************/
6176 #define DMA_SxNDT_Pos (0U)
6177 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6178 #define DMA_SxNDT DMA_SxNDT_Msk
6179 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
6180 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
6181 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
6182 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
6183 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
6184 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
6185 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
6186 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
6187 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
6188 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
6189 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
6190 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
6191 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
6192 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
6193 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
6194 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
6195
6196 /******************** Bits definition for DMA_SxFCR register ****************/
6197 #define DMA_SxFCR_FEIE_Pos (7U)
6198 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6199 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6200 #define DMA_SxFCR_FS_Pos (3U)
6201 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6202 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6203 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6204 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6205 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6206 #define DMA_SxFCR_DMDIS_Pos (2U)
6207 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6208 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6209 #define DMA_SxFCR_FTH_Pos (0U)
6210 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6211 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6212 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6213 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6214
6215 /******************** Bits definition for DMA_LISR register *****************/
6216 #define DMA_LISR_TCIF3_Pos (27U)
6217 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6218 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6219 #define DMA_LISR_HTIF3_Pos (26U)
6220 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6221 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6222 #define DMA_LISR_TEIF3_Pos (25U)
6223 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6224 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6225 #define DMA_LISR_DMEIF3_Pos (24U)
6226 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6227 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6228 #define DMA_LISR_FEIF3_Pos (22U)
6229 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6230 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6231 #define DMA_LISR_TCIF2_Pos (21U)
6232 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6233 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6234 #define DMA_LISR_HTIF2_Pos (20U)
6235 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6236 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6237 #define DMA_LISR_TEIF2_Pos (19U)
6238 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6239 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6240 #define DMA_LISR_DMEIF2_Pos (18U)
6241 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6242 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6243 #define DMA_LISR_FEIF2_Pos (16U)
6244 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6245 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6246 #define DMA_LISR_TCIF1_Pos (11U)
6247 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6248 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6249 #define DMA_LISR_HTIF1_Pos (10U)
6250 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6251 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6252 #define DMA_LISR_TEIF1_Pos (9U)
6253 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6254 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6255 #define DMA_LISR_DMEIF1_Pos (8U)
6256 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6257 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6258 #define DMA_LISR_FEIF1_Pos (6U)
6259 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6260 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6261 #define DMA_LISR_TCIF0_Pos (5U)
6262 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6263 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6264 #define DMA_LISR_HTIF0_Pos (4U)
6265 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6266 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6267 #define DMA_LISR_TEIF0_Pos (3U)
6268 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6269 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6270 #define DMA_LISR_DMEIF0_Pos (2U)
6271 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6272 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6273 #define DMA_LISR_FEIF0_Pos (0U)
6274 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6275 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6276
6277 /******************** Bits definition for DMA_HISR register *****************/
6278 #define DMA_HISR_TCIF7_Pos (27U)
6279 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6280 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6281 #define DMA_HISR_HTIF7_Pos (26U)
6282 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6283 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6284 #define DMA_HISR_TEIF7_Pos (25U)
6285 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6286 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6287 #define DMA_HISR_DMEIF7_Pos (24U)
6288 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6289 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6290 #define DMA_HISR_FEIF7_Pos (22U)
6291 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6292 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6293 #define DMA_HISR_TCIF6_Pos (21U)
6294 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6295 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6296 #define DMA_HISR_HTIF6_Pos (20U)
6297 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6298 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6299 #define DMA_HISR_TEIF6_Pos (19U)
6300 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6301 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6302 #define DMA_HISR_DMEIF6_Pos (18U)
6303 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6304 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6305 #define DMA_HISR_FEIF6_Pos (16U)
6306 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6307 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6308 #define DMA_HISR_TCIF5_Pos (11U)
6309 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6310 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6311 #define DMA_HISR_HTIF5_Pos (10U)
6312 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6313 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6314 #define DMA_HISR_TEIF5_Pos (9U)
6315 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6316 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6317 #define DMA_HISR_DMEIF5_Pos (8U)
6318 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6319 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6320 #define DMA_HISR_FEIF5_Pos (6U)
6321 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6322 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6323 #define DMA_HISR_TCIF4_Pos (5U)
6324 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6325 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6326 #define DMA_HISR_HTIF4_Pos (4U)
6327 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6328 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6329 #define DMA_HISR_TEIF4_Pos (3U)
6330 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6331 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6332 #define DMA_HISR_DMEIF4_Pos (2U)
6333 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6334 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6335 #define DMA_HISR_FEIF4_Pos (0U)
6336 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6337 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6338
6339 /******************** Bits definition for DMA_LIFCR register ****************/
6340 #define DMA_LIFCR_CTCIF3_Pos (27U)
6341 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6342 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6343 #define DMA_LIFCR_CHTIF3_Pos (26U)
6344 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6345 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6346 #define DMA_LIFCR_CTEIF3_Pos (25U)
6347 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6348 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6349 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6350 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6351 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6352 #define DMA_LIFCR_CFEIF3_Pos (22U)
6353 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6354 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6355 #define DMA_LIFCR_CTCIF2_Pos (21U)
6356 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6357 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6358 #define DMA_LIFCR_CHTIF2_Pos (20U)
6359 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6360 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6361 #define DMA_LIFCR_CTEIF2_Pos (19U)
6362 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6363 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6364 #define DMA_LIFCR_CDMEIF2_Pos (18U)
6365 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6366 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6367 #define DMA_LIFCR_CFEIF2_Pos (16U)
6368 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6369 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6370 #define DMA_LIFCR_CTCIF1_Pos (11U)
6371 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6372 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6373 #define DMA_LIFCR_CHTIF1_Pos (10U)
6374 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6375 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6376 #define DMA_LIFCR_CTEIF1_Pos (9U)
6377 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6378 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6379 #define DMA_LIFCR_CDMEIF1_Pos (8U)
6380 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6381 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6382 #define DMA_LIFCR_CFEIF1_Pos (6U)
6383 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6384 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6385 #define DMA_LIFCR_CTCIF0_Pos (5U)
6386 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6387 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6388 #define DMA_LIFCR_CHTIF0_Pos (4U)
6389 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6390 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6391 #define DMA_LIFCR_CTEIF0_Pos (3U)
6392 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6393 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6394 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6395 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6396 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6397 #define DMA_LIFCR_CFEIF0_Pos (0U)
6398 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6399 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6400
6401 /******************** Bits definition for DMA_HIFCR register ****************/
6402 #define DMA_HIFCR_CTCIF7_Pos (27U)
6403 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6404 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6405 #define DMA_HIFCR_CHTIF7_Pos (26U)
6406 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6407 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6408 #define DMA_HIFCR_CTEIF7_Pos (25U)
6409 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6410 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6411 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6412 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6413 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6414 #define DMA_HIFCR_CFEIF7_Pos (22U)
6415 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6416 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6417 #define DMA_HIFCR_CTCIF6_Pos (21U)
6418 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6419 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6420 #define DMA_HIFCR_CHTIF6_Pos (20U)
6421 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6422 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6423 #define DMA_HIFCR_CTEIF6_Pos (19U)
6424 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6425 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6426 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6427 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6428 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6429 #define DMA_HIFCR_CFEIF6_Pos (16U)
6430 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6431 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6432 #define DMA_HIFCR_CTCIF5_Pos (11U)
6433 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6434 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6435 #define DMA_HIFCR_CHTIF5_Pos (10U)
6436 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6437 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6438 #define DMA_HIFCR_CTEIF5_Pos (9U)
6439 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6440 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6441 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6442 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6443 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6444 #define DMA_HIFCR_CFEIF5_Pos (6U)
6445 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6446 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6447 #define DMA_HIFCR_CTCIF4_Pos (5U)
6448 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6449 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6450 #define DMA_HIFCR_CHTIF4_Pos (4U)
6451 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6452 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6453 #define DMA_HIFCR_CTEIF4_Pos (3U)
6454 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6455 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6456 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6457 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6458 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6459 #define DMA_HIFCR_CFEIF4_Pos (0U)
6460 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6461 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6462
6463 /****************** Bit definition for DMA_SxPAR register ********************/
6464 #define DMA_SxPAR_PA_Pos (0U)
6465 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6466 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6467
6468 /****************** Bit definition for DMA_SxM0AR register ********************/
6469 #define DMA_SxM0AR_M0A_Pos (0U)
6470 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6471 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6472
6473 /****************** Bit definition for DMA_SxM1AR register ********************/
6474 #define DMA_SxM1AR_M1A_Pos (0U)
6475 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6476 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6477
6478
6479 /******************************************************************************/
6480 /* */
6481 /* AHB Master DMA2D Controller (DMA2D) */
6482 /* */
6483 /******************************************************************************/
6484
6485 /******************** Bit definition for DMA2D_CR register ******************/
6486
6487 #define DMA2D_CR_START_Pos (0U)
6488 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
6489 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
6490 #define DMA2D_CR_SUSP_Pos (1U)
6491 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
6492 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
6493 #define DMA2D_CR_ABORT_Pos (2U)
6494 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
6495 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
6496 #define DMA2D_CR_TEIE_Pos (8U)
6497 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
6498 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
6499 #define DMA2D_CR_TCIE_Pos (9U)
6500 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
6501 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
6502 #define DMA2D_CR_TWIE_Pos (10U)
6503 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
6504 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
6505 #define DMA2D_CR_CAEIE_Pos (11U)
6506 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
6507 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
6508 #define DMA2D_CR_CTCIE_Pos (12U)
6509 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
6510 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
6511 #define DMA2D_CR_CEIE_Pos (13U)
6512 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
6513 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
6514 #define DMA2D_CR_MODE_Pos (16U)
6515 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
6516 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
6517 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
6518 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
6519
6520 /******************** Bit definition for DMA2D_ISR register *****************/
6521
6522 #define DMA2D_ISR_TEIF_Pos (0U)
6523 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
6524 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
6525 #define DMA2D_ISR_TCIF_Pos (1U)
6526 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
6527 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
6528 #define DMA2D_ISR_TWIF_Pos (2U)
6529 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
6530 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
6531 #define DMA2D_ISR_CAEIF_Pos (3U)
6532 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
6533 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
6534 #define DMA2D_ISR_CTCIF_Pos (4U)
6535 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
6536 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
6537 #define DMA2D_ISR_CEIF_Pos (5U)
6538 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
6539 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
6540
6541 /******************** Bit definition for DMA2D_IFCR register ****************/
6542
6543 #define DMA2D_IFCR_CTEIF_Pos (0U)
6544 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
6545 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
6546 #define DMA2D_IFCR_CTCIF_Pos (1U)
6547 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
6548 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
6549 #define DMA2D_IFCR_CTWIF_Pos (2U)
6550 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
6551 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
6552 #define DMA2D_IFCR_CAECIF_Pos (3U)
6553 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
6554 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
6555 #define DMA2D_IFCR_CCTCIF_Pos (4U)
6556 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
6557 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
6558 #define DMA2D_IFCR_CCEIF_Pos (5U)
6559 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
6560 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
6561
6562 /* Legacy defines */
6563 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
6564 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
6565 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
6566 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
6567 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
6568 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
6569
6570 /******************** Bit definition for DMA2D_FGMAR register ***************/
6571
6572 #define DMA2D_FGMAR_MA_Pos (0U)
6573 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6574 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
6575
6576 /******************** Bit definition for DMA2D_FGOR register ****************/
6577
6578 #define DMA2D_FGOR_LO_Pos (0U)
6579 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
6580 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
6581
6582 /******************** Bit definition for DMA2D_BGMAR register ***************/
6583
6584 #define DMA2D_BGMAR_MA_Pos (0U)
6585 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6586 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
6587
6588 /******************** Bit definition for DMA2D_BGOR register ****************/
6589
6590 #define DMA2D_BGOR_LO_Pos (0U)
6591 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
6592 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
6593
6594 /******************** Bit definition for DMA2D_FGPFCCR register *************/
6595
6596 #define DMA2D_FGPFCCR_CM_Pos (0U)
6597 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
6598 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6599 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
6600 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
6601 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
6602 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
6603 #define DMA2D_FGPFCCR_CCM_Pos (4U)
6604 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
6605 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
6606 #define DMA2D_FGPFCCR_START_Pos (5U)
6607 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
6608 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
6609 #define DMA2D_FGPFCCR_CS_Pos (8U)
6610 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6611 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
6612 #define DMA2D_FGPFCCR_AM_Pos (16U)
6613 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
6614 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6615 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
6616 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
6617 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6618 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6619 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
6620
6621 /******************** Bit definition for DMA2D_FGCOLR register **************/
6622
6623 #define DMA2D_FGCOLR_BLUE_Pos (0U)
6624 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
6625 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
6626 #define DMA2D_FGCOLR_GREEN_Pos (8U)
6627 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6628 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
6629 #define DMA2D_FGCOLR_RED_Pos (16U)
6630 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
6631 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
6632
6633 /******************** Bit definition for DMA2D_BGPFCCR register *************/
6634
6635 #define DMA2D_BGPFCCR_CM_Pos (0U)
6636 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
6637 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6638 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
6639 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
6640 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
6641 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
6642 #define DMA2D_BGPFCCR_CCM_Pos (4U)
6643 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
6644 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
6645 #define DMA2D_BGPFCCR_START_Pos (5U)
6646 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
6647 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
6648 #define DMA2D_BGPFCCR_CS_Pos (8U)
6649 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6650 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
6651 #define DMA2D_BGPFCCR_AM_Pos (16U)
6652 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
6653 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6654 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
6655 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
6656 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6657 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6658 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
6659
6660 /******************** Bit definition for DMA2D_BGCOLR register **************/
6661
6662 #define DMA2D_BGCOLR_BLUE_Pos (0U)
6663 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
6664 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
6665 #define DMA2D_BGCOLR_GREEN_Pos (8U)
6666 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6667 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
6668 #define DMA2D_BGCOLR_RED_Pos (16U)
6669 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
6670 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
6671
6672 /******************** Bit definition for DMA2D_FGCMAR register **************/
6673
6674 #define DMA2D_FGCMAR_MA_Pos (0U)
6675 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6676 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
6677
6678 /******************** Bit definition for DMA2D_BGCMAR register **************/
6679
6680 #define DMA2D_BGCMAR_MA_Pos (0U)
6681 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6682 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
6683
6684 /******************** Bit definition for DMA2D_OPFCCR register **************/
6685
6686 #define DMA2D_OPFCCR_CM_Pos (0U)
6687 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
6688 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
6689 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
6690 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
6691 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
6692
6693 /******************** Bit definition for DMA2D_OCOLR register ***************/
6694
6695 /*!<Mode_ARGB8888/RGB888 */
6696
6697 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
6698 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
6699 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
6700 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
6701
6702 /*!<Mode_RGB565 */
6703 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
6704 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
6705 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
6706
6707 /*!<Mode_ARGB1555 */
6708 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
6709 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
6710 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
6711 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
6712
6713 /*!<Mode_ARGB4444 */
6714 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
6715 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
6716 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
6717 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
6718
6719 /******************** Bit definition for DMA2D_OMAR register ****************/
6720
6721 #define DMA2D_OMAR_MA_Pos (0U)
6722 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
6723 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
6724
6725 /******************** Bit definition for DMA2D_OOR register *****************/
6726
6727 #define DMA2D_OOR_LO_Pos (0U)
6728 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
6729 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
6730
6731 /******************** Bit definition for DMA2D_NLR register *****************/
6732
6733 #define DMA2D_NLR_NL_Pos (0U)
6734 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
6735 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
6736 #define DMA2D_NLR_PL_Pos (16U)
6737 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
6738 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
6739
6740 /******************** Bit definition for DMA2D_LWR register *****************/
6741
6742 #define DMA2D_LWR_LW_Pos (0U)
6743 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
6744 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
6745
6746 /******************** Bit definition for DMA2D_AMTCR register ***************/
6747
6748 #define DMA2D_AMTCR_EN_Pos (0U)
6749 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
6750 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
6751 #define DMA2D_AMTCR_DT_Pos (8U)
6752 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
6753 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
6754
6755 /******************** Bit definition for DMA2D_FGCLUT register **************/
6756
6757 /******************** Bit definition for DMA2D_BGCLUT register **************/
6758
6759
6760 /******************************************************************************/
6761 /* */
6762 /* External Interrupt/Event Controller */
6763 /* */
6764 /******************************************************************************/
6765 /******************* Bit definition for EXTI_IMR register *******************/
6766 #define EXTI_IMR_MR0_Pos (0U)
6767 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
6768 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
6769 #define EXTI_IMR_MR1_Pos (1U)
6770 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
6771 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
6772 #define EXTI_IMR_MR2_Pos (2U)
6773 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
6774 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
6775 #define EXTI_IMR_MR3_Pos (3U)
6776 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
6777 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
6778 #define EXTI_IMR_MR4_Pos (4U)
6779 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
6780 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
6781 #define EXTI_IMR_MR5_Pos (5U)
6782 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
6783 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
6784 #define EXTI_IMR_MR6_Pos (6U)
6785 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
6786 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
6787 #define EXTI_IMR_MR7_Pos (7U)
6788 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
6789 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
6790 #define EXTI_IMR_MR8_Pos (8U)
6791 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
6792 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
6793 #define EXTI_IMR_MR9_Pos (9U)
6794 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
6795 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
6796 #define EXTI_IMR_MR10_Pos (10U)
6797 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
6798 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
6799 #define EXTI_IMR_MR11_Pos (11U)
6800 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
6801 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
6802 #define EXTI_IMR_MR12_Pos (12U)
6803 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
6804 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
6805 #define EXTI_IMR_MR13_Pos (13U)
6806 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
6807 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
6808 #define EXTI_IMR_MR14_Pos (14U)
6809 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
6810 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
6811 #define EXTI_IMR_MR15_Pos (15U)
6812 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
6813 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
6814 #define EXTI_IMR_MR16_Pos (16U)
6815 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
6816 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
6817 #define EXTI_IMR_MR17_Pos (17U)
6818 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
6819 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
6820 #define EXTI_IMR_MR18_Pos (18U)
6821 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
6822 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
6823 #define EXTI_IMR_MR19_Pos (19U)
6824 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
6825 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
6826 #define EXTI_IMR_MR20_Pos (20U)
6827 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
6828 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
6829 #define EXTI_IMR_MR21_Pos (21U)
6830 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
6831 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
6832 #define EXTI_IMR_MR22_Pos (22U)
6833 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
6834 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
6835
6836 /* Reference Defines */
6837 #define EXTI_IMR_IM0 EXTI_IMR_MR0
6838 #define EXTI_IMR_IM1 EXTI_IMR_MR1
6839 #define EXTI_IMR_IM2 EXTI_IMR_MR2
6840 #define EXTI_IMR_IM3 EXTI_IMR_MR3
6841 #define EXTI_IMR_IM4 EXTI_IMR_MR4
6842 #define EXTI_IMR_IM5 EXTI_IMR_MR5
6843 #define EXTI_IMR_IM6 EXTI_IMR_MR6
6844 #define EXTI_IMR_IM7 EXTI_IMR_MR7
6845 #define EXTI_IMR_IM8 EXTI_IMR_MR8
6846 #define EXTI_IMR_IM9 EXTI_IMR_MR9
6847 #define EXTI_IMR_IM10 EXTI_IMR_MR10
6848 #define EXTI_IMR_IM11 EXTI_IMR_MR11
6849 #define EXTI_IMR_IM12 EXTI_IMR_MR12
6850 #define EXTI_IMR_IM13 EXTI_IMR_MR13
6851 #define EXTI_IMR_IM14 EXTI_IMR_MR14
6852 #define EXTI_IMR_IM15 EXTI_IMR_MR15
6853 #define EXTI_IMR_IM16 EXTI_IMR_MR16
6854 #define EXTI_IMR_IM17 EXTI_IMR_MR17
6855 #define EXTI_IMR_IM18 EXTI_IMR_MR18
6856 #define EXTI_IMR_IM19 EXTI_IMR_MR19
6857 #define EXTI_IMR_IM20 EXTI_IMR_MR20
6858 #define EXTI_IMR_IM21 EXTI_IMR_MR21
6859 #define EXTI_IMR_IM22 EXTI_IMR_MR22
6860 #define EXTI_IMR_IM_Pos (0U)
6861 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
6862 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
6863
6864 /******************* Bit definition for EXTI_EMR register *******************/
6865 #define EXTI_EMR_MR0_Pos (0U)
6866 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
6867 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
6868 #define EXTI_EMR_MR1_Pos (1U)
6869 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
6870 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
6871 #define EXTI_EMR_MR2_Pos (2U)
6872 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
6873 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
6874 #define EXTI_EMR_MR3_Pos (3U)
6875 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
6876 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
6877 #define EXTI_EMR_MR4_Pos (4U)
6878 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
6879 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
6880 #define EXTI_EMR_MR5_Pos (5U)
6881 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
6882 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
6883 #define EXTI_EMR_MR6_Pos (6U)
6884 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
6885 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
6886 #define EXTI_EMR_MR7_Pos (7U)
6887 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
6888 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
6889 #define EXTI_EMR_MR8_Pos (8U)
6890 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
6891 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
6892 #define EXTI_EMR_MR9_Pos (9U)
6893 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
6894 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
6895 #define EXTI_EMR_MR10_Pos (10U)
6896 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
6897 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
6898 #define EXTI_EMR_MR11_Pos (11U)
6899 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
6900 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
6901 #define EXTI_EMR_MR12_Pos (12U)
6902 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
6903 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
6904 #define EXTI_EMR_MR13_Pos (13U)
6905 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
6906 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
6907 #define EXTI_EMR_MR14_Pos (14U)
6908 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
6909 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
6910 #define EXTI_EMR_MR15_Pos (15U)
6911 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
6912 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
6913 #define EXTI_EMR_MR16_Pos (16U)
6914 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
6915 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
6916 #define EXTI_EMR_MR17_Pos (17U)
6917 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
6918 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
6919 #define EXTI_EMR_MR18_Pos (18U)
6920 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
6921 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
6922 #define EXTI_EMR_MR19_Pos (19U)
6923 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
6924 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
6925 #define EXTI_EMR_MR20_Pos (20U)
6926 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
6927 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
6928 #define EXTI_EMR_MR21_Pos (21U)
6929 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
6930 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
6931 #define EXTI_EMR_MR22_Pos (22U)
6932 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
6933 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
6934
6935 /* Reference Defines */
6936 #define EXTI_EMR_EM0 EXTI_EMR_MR0
6937 #define EXTI_EMR_EM1 EXTI_EMR_MR1
6938 #define EXTI_EMR_EM2 EXTI_EMR_MR2
6939 #define EXTI_EMR_EM3 EXTI_EMR_MR3
6940 #define EXTI_EMR_EM4 EXTI_EMR_MR4
6941 #define EXTI_EMR_EM5 EXTI_EMR_MR5
6942 #define EXTI_EMR_EM6 EXTI_EMR_MR6
6943 #define EXTI_EMR_EM7 EXTI_EMR_MR7
6944 #define EXTI_EMR_EM8 EXTI_EMR_MR8
6945 #define EXTI_EMR_EM9 EXTI_EMR_MR9
6946 #define EXTI_EMR_EM10 EXTI_EMR_MR10
6947 #define EXTI_EMR_EM11 EXTI_EMR_MR11
6948 #define EXTI_EMR_EM12 EXTI_EMR_MR12
6949 #define EXTI_EMR_EM13 EXTI_EMR_MR13
6950 #define EXTI_EMR_EM14 EXTI_EMR_MR14
6951 #define EXTI_EMR_EM15 EXTI_EMR_MR15
6952 #define EXTI_EMR_EM16 EXTI_EMR_MR16
6953 #define EXTI_EMR_EM17 EXTI_EMR_MR17
6954 #define EXTI_EMR_EM18 EXTI_EMR_MR18
6955 #define EXTI_EMR_EM19 EXTI_EMR_MR19
6956 #define EXTI_EMR_EM20 EXTI_EMR_MR20
6957 #define EXTI_EMR_EM21 EXTI_EMR_MR21
6958 #define EXTI_EMR_EM22 EXTI_EMR_MR22
6959
6960 /****************** Bit definition for EXTI_RTSR register *******************/
6961 #define EXTI_RTSR_TR0_Pos (0U)
6962 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
6963 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
6964 #define EXTI_RTSR_TR1_Pos (1U)
6965 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
6966 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
6967 #define EXTI_RTSR_TR2_Pos (2U)
6968 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
6969 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
6970 #define EXTI_RTSR_TR3_Pos (3U)
6971 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
6972 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
6973 #define EXTI_RTSR_TR4_Pos (4U)
6974 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
6975 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
6976 #define EXTI_RTSR_TR5_Pos (5U)
6977 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
6978 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
6979 #define EXTI_RTSR_TR6_Pos (6U)
6980 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
6981 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
6982 #define EXTI_RTSR_TR7_Pos (7U)
6983 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
6984 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
6985 #define EXTI_RTSR_TR8_Pos (8U)
6986 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
6987 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
6988 #define EXTI_RTSR_TR9_Pos (9U)
6989 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
6990 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
6991 #define EXTI_RTSR_TR10_Pos (10U)
6992 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
6993 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
6994 #define EXTI_RTSR_TR11_Pos (11U)
6995 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
6996 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
6997 #define EXTI_RTSR_TR12_Pos (12U)
6998 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
6999 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
7000 #define EXTI_RTSR_TR13_Pos (13U)
7001 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
7002 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
7003 #define EXTI_RTSR_TR14_Pos (14U)
7004 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
7005 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
7006 #define EXTI_RTSR_TR15_Pos (15U)
7007 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
7008 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
7009 #define EXTI_RTSR_TR16_Pos (16U)
7010 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
7011 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
7012 #define EXTI_RTSR_TR17_Pos (17U)
7013 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
7014 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
7015 #define EXTI_RTSR_TR18_Pos (18U)
7016 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
7017 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
7018 #define EXTI_RTSR_TR19_Pos (19U)
7019 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
7020 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
7021 #define EXTI_RTSR_TR20_Pos (20U)
7022 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
7023 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
7024 #define EXTI_RTSR_TR21_Pos (21U)
7025 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
7026 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
7027 #define EXTI_RTSR_TR22_Pos (22U)
7028 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
7029 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
7030
7031 /****************** Bit definition for EXTI_FTSR register *******************/
7032 #define EXTI_FTSR_TR0_Pos (0U)
7033 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
7034 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
7035 #define EXTI_FTSR_TR1_Pos (1U)
7036 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
7037 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
7038 #define EXTI_FTSR_TR2_Pos (2U)
7039 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
7040 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
7041 #define EXTI_FTSR_TR3_Pos (3U)
7042 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
7043 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
7044 #define EXTI_FTSR_TR4_Pos (4U)
7045 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
7046 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
7047 #define EXTI_FTSR_TR5_Pos (5U)
7048 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
7049 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
7050 #define EXTI_FTSR_TR6_Pos (6U)
7051 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
7052 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
7053 #define EXTI_FTSR_TR7_Pos (7U)
7054 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
7055 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
7056 #define EXTI_FTSR_TR8_Pos (8U)
7057 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
7058 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
7059 #define EXTI_FTSR_TR9_Pos (9U)
7060 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
7061 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
7062 #define EXTI_FTSR_TR10_Pos (10U)
7063 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
7064 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
7065 #define EXTI_FTSR_TR11_Pos (11U)
7066 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
7067 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
7068 #define EXTI_FTSR_TR12_Pos (12U)
7069 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
7070 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
7071 #define EXTI_FTSR_TR13_Pos (13U)
7072 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
7073 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
7074 #define EXTI_FTSR_TR14_Pos (14U)
7075 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
7076 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
7077 #define EXTI_FTSR_TR15_Pos (15U)
7078 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
7079 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
7080 #define EXTI_FTSR_TR16_Pos (16U)
7081 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
7082 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
7083 #define EXTI_FTSR_TR17_Pos (17U)
7084 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
7085 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
7086 #define EXTI_FTSR_TR18_Pos (18U)
7087 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
7088 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
7089 #define EXTI_FTSR_TR19_Pos (19U)
7090 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
7091 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
7092 #define EXTI_FTSR_TR20_Pos (20U)
7093 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
7094 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
7095 #define EXTI_FTSR_TR21_Pos (21U)
7096 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
7097 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
7098 #define EXTI_FTSR_TR22_Pos (22U)
7099 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
7100 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
7101
7102 /****************** Bit definition for EXTI_SWIER register ******************/
7103 #define EXTI_SWIER_SWIER0_Pos (0U)
7104 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
7105 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
7106 #define EXTI_SWIER_SWIER1_Pos (1U)
7107 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
7108 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
7109 #define EXTI_SWIER_SWIER2_Pos (2U)
7110 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
7111 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
7112 #define EXTI_SWIER_SWIER3_Pos (3U)
7113 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
7114 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
7115 #define EXTI_SWIER_SWIER4_Pos (4U)
7116 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
7117 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
7118 #define EXTI_SWIER_SWIER5_Pos (5U)
7119 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
7120 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
7121 #define EXTI_SWIER_SWIER6_Pos (6U)
7122 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
7123 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
7124 #define EXTI_SWIER_SWIER7_Pos (7U)
7125 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
7126 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
7127 #define EXTI_SWIER_SWIER8_Pos (8U)
7128 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
7129 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
7130 #define EXTI_SWIER_SWIER9_Pos (9U)
7131 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
7132 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
7133 #define EXTI_SWIER_SWIER10_Pos (10U)
7134 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
7135 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
7136 #define EXTI_SWIER_SWIER11_Pos (11U)
7137 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
7138 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
7139 #define EXTI_SWIER_SWIER12_Pos (12U)
7140 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
7141 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
7142 #define EXTI_SWIER_SWIER13_Pos (13U)
7143 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
7144 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
7145 #define EXTI_SWIER_SWIER14_Pos (14U)
7146 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
7147 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
7148 #define EXTI_SWIER_SWIER15_Pos (15U)
7149 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
7150 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
7151 #define EXTI_SWIER_SWIER16_Pos (16U)
7152 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
7153 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
7154 #define EXTI_SWIER_SWIER17_Pos (17U)
7155 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
7156 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
7157 #define EXTI_SWIER_SWIER18_Pos (18U)
7158 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
7159 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
7160 #define EXTI_SWIER_SWIER19_Pos (19U)
7161 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
7162 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
7163 #define EXTI_SWIER_SWIER20_Pos (20U)
7164 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
7165 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
7166 #define EXTI_SWIER_SWIER21_Pos (21U)
7167 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
7168 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
7169 #define EXTI_SWIER_SWIER22_Pos (22U)
7170 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
7171 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
7172
7173 /******************* Bit definition for EXTI_PR register ********************/
7174 #define EXTI_PR_PR0_Pos (0U)
7175 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
7176 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
7177 #define EXTI_PR_PR1_Pos (1U)
7178 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
7179 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
7180 #define EXTI_PR_PR2_Pos (2U)
7181 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
7182 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
7183 #define EXTI_PR_PR3_Pos (3U)
7184 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
7185 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
7186 #define EXTI_PR_PR4_Pos (4U)
7187 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
7188 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
7189 #define EXTI_PR_PR5_Pos (5U)
7190 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
7191 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
7192 #define EXTI_PR_PR6_Pos (6U)
7193 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
7194 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
7195 #define EXTI_PR_PR7_Pos (7U)
7196 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
7197 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
7198 #define EXTI_PR_PR8_Pos (8U)
7199 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
7200 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
7201 #define EXTI_PR_PR9_Pos (9U)
7202 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
7203 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
7204 #define EXTI_PR_PR10_Pos (10U)
7205 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
7206 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
7207 #define EXTI_PR_PR11_Pos (11U)
7208 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
7209 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
7210 #define EXTI_PR_PR12_Pos (12U)
7211 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
7212 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
7213 #define EXTI_PR_PR13_Pos (13U)
7214 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
7215 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
7216 #define EXTI_PR_PR14_Pos (14U)
7217 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
7218 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
7219 #define EXTI_PR_PR15_Pos (15U)
7220 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
7221 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
7222 #define EXTI_PR_PR16_Pos (16U)
7223 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
7224 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
7225 #define EXTI_PR_PR17_Pos (17U)
7226 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
7227 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
7228 #define EXTI_PR_PR18_Pos (18U)
7229 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
7230 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
7231 #define EXTI_PR_PR19_Pos (19U)
7232 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
7233 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
7234 #define EXTI_PR_PR20_Pos (20U)
7235 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
7236 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
7237 #define EXTI_PR_PR21_Pos (21U)
7238 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
7239 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
7240 #define EXTI_PR_PR22_Pos (22U)
7241 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
7242 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
7243
7244 /******************************************************************************/
7245 /* */
7246 /* FLASH */
7247 /* */
7248 /******************************************************************************/
7249 /******************* Bits definition for FLASH_ACR register *****************/
7250 #define FLASH_ACR_LATENCY_Pos (0U)
7251 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
7252 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7253 #define FLASH_ACR_LATENCY_0WS 0x00000000U
7254 #define FLASH_ACR_LATENCY_1WS 0x00000001U
7255 #define FLASH_ACR_LATENCY_2WS 0x00000002U
7256 #define FLASH_ACR_LATENCY_3WS 0x00000003U
7257 #define FLASH_ACR_LATENCY_4WS 0x00000004U
7258 #define FLASH_ACR_LATENCY_5WS 0x00000005U
7259 #define FLASH_ACR_LATENCY_6WS 0x00000006U
7260 #define FLASH_ACR_LATENCY_7WS 0x00000007U
7261
7262 #define FLASH_ACR_LATENCY_8WS 0x00000008U
7263 #define FLASH_ACR_LATENCY_9WS 0x00000009U
7264 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
7265 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
7266 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
7267 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
7268 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
7269 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
7270 #define FLASH_ACR_PRFTEN_Pos (8U)
7271 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
7272 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7273 #define FLASH_ACR_ICEN_Pos (9U)
7274 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
7275 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
7276 #define FLASH_ACR_DCEN_Pos (10U)
7277 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
7278 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
7279 #define FLASH_ACR_ICRST_Pos (11U)
7280 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
7281 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
7282 #define FLASH_ACR_DCRST_Pos (12U)
7283 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
7284 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
7285 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
7286 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
7287 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
7288 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
7289 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
7290 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
7291
7292 /******************* Bits definition for FLASH_SR register ******************/
7293 #define FLASH_SR_EOP_Pos (0U)
7294 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
7295 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
7296 #define FLASH_SR_SOP_Pos (1U)
7297 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
7298 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
7299 #define FLASH_SR_WRPERR_Pos (4U)
7300 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
7301 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7302 #define FLASH_SR_PGAERR_Pos (5U)
7303 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
7304 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7305 #define FLASH_SR_PGPERR_Pos (6U)
7306 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
7307 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
7308 #define FLASH_SR_PGSERR_Pos (7U)
7309 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
7310 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
7311 #define FLASH_SR_RDERR_Pos (8U)
7312 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
7313 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
7314 #define FLASH_SR_BSY_Pos (16U)
7315 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
7316 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
7317
7318 /******************* Bits definition for FLASH_CR register ******************/
7319 #define FLASH_CR_PG_Pos (0U)
7320 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
7321 #define FLASH_CR_PG FLASH_CR_PG_Msk
7322 #define FLASH_CR_SER_Pos (1U)
7323 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
7324 #define FLASH_CR_SER FLASH_CR_SER_Msk
7325 #define FLASH_CR_MER_Pos (2U)
7326 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
7327 #define FLASH_CR_MER FLASH_CR_MER_Msk
7328 #define FLASH_CR_MER1 FLASH_CR_MER
7329 #define FLASH_CR_SNB_Pos (3U)
7330 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
7331 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
7332 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
7333 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
7334 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
7335 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
7336 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
7337 #define FLASH_CR_PSIZE_Pos (8U)
7338 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
7339 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
7340 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
7341 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
7342 #define FLASH_CR_MER2_Pos (15U)
7343 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
7344 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
7345 #define FLASH_CR_STRT_Pos (16U)
7346 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
7347 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
7348 #define FLASH_CR_EOPIE_Pos (24U)
7349 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
7350 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7351 #define FLASH_CR_LOCK_Pos (31U)
7352 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
7353 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7354
7355 /******************* Bits definition for FLASH_OPTCR register ***************/
7356 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
7357 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
7358 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
7359 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
7360 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
7361 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
7362
7363 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
7364 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
7365 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
7366 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
7367 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
7368 #define FLASH_OPTCR_BFB2_Pos (4U)
7369 #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
7370 #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
7371 #define FLASH_OPTCR_WDG_SW_Pos (5U)
7372 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
7373 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
7374 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
7375 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
7376 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
7377 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
7378 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
7379 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
7380 #define FLASH_OPTCR_RDP_Pos (8U)
7381 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
7382 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
7383 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
7384 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
7385 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
7386 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
7387 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
7388 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
7389 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
7390 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
7391 #define FLASH_OPTCR_nWRP_Pos (16U)
7392 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
7393 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
7394 #define FLASH_OPTCR_nWRP_0 0x00010000U
7395 #define FLASH_OPTCR_nWRP_1 0x00020000U
7396 #define FLASH_OPTCR_nWRP_2 0x00040000U
7397 #define FLASH_OPTCR_nWRP_3 0x00080000U
7398 #define FLASH_OPTCR_nWRP_4 0x00100000U
7399 #define FLASH_OPTCR_nWRP_5 0x00200000U
7400 #define FLASH_OPTCR_nWRP_6 0x00400000U
7401 #define FLASH_OPTCR_nWRP_7 0x00800000U
7402 #define FLASH_OPTCR_nWRP_8 0x01000000U
7403 #define FLASH_OPTCR_nWRP_9 0x02000000U
7404 #define FLASH_OPTCR_nWRP_10 0x04000000U
7405 #define FLASH_OPTCR_nWRP_11 0x08000000U
7406 #define FLASH_OPTCR_DB1M_Pos (30U)
7407 #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
7408 #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
7409 #define FLASH_OPTCR_SPRMOD_Pos (31U)
7410 #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
7411 #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
7412
7413 /****************** Bits definition for FLASH_OPTCR1 register ***************/
7414 #define FLASH_OPTCR1_nWRP_Pos (16U)
7415 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
7416 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
7417 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
7418 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
7419 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
7420 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
7421 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
7422 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
7423 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
7424 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
7425 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
7426 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
7427 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
7428 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
7429
7430 /******************************************************************************/
7431 /* */
7432 /* Flexible Memory Controller */
7433 /* */
7434 /******************************************************************************/
7435 /****************** Bit definition for FMC_BCR1 register *******************/
7436 #define FMC_BCR1_MBKEN_Pos (0U)
7437 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
7438 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
7439 #define FMC_BCR1_MUXEN_Pos (1U)
7440 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
7441 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7442
7443 #define FMC_BCR1_MTYP_Pos (2U)
7444 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
7445 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7446 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
7447 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
7448
7449 #define FMC_BCR1_MWID_Pos (4U)
7450 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
7451 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7452 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
7453 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
7454
7455 #define FMC_BCR1_FACCEN_Pos (6U)
7456 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
7457 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
7458 #define FMC_BCR1_BURSTEN_Pos (8U)
7459 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
7460 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
7461 #define FMC_BCR1_WAITPOL_Pos (9U)
7462 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
7463 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
7464 #define FMC_BCR1_WRAPMOD_Pos (10U)
7465 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
7466 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
7467 #define FMC_BCR1_WAITCFG_Pos (11U)
7468 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
7469 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
7470 #define FMC_BCR1_WREN_Pos (12U)
7471 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
7472 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
7473 #define FMC_BCR1_WAITEN_Pos (13U)
7474 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
7475 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
7476 #define FMC_BCR1_EXTMOD_Pos (14U)
7477 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
7478 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
7479 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
7480 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
7481 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
7482 #define FMC_BCR1_CPSIZE_Pos (16U)
7483 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
7484 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
7485 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
7486 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
7487 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
7488 #define FMC_BCR1_CBURSTRW_Pos (19U)
7489 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
7490 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
7491 #define FMC_BCR1_CCLKEN_Pos (20U)
7492 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
7493 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
7494
7495 /****************** Bit definition for FMC_BCR2 register *******************/
7496 #define FMC_BCR2_MBKEN_Pos (0U)
7497 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
7498 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
7499 #define FMC_BCR2_MUXEN_Pos (1U)
7500 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
7501 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7502
7503 #define FMC_BCR2_MTYP_Pos (2U)
7504 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
7505 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7506 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
7507 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
7508
7509 #define FMC_BCR2_MWID_Pos (4U)
7510 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
7511 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7512 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
7513 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
7514
7515 #define FMC_BCR2_FACCEN_Pos (6U)
7516 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
7517 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
7518 #define FMC_BCR2_BURSTEN_Pos (8U)
7519 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
7520 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
7521 #define FMC_BCR2_WAITPOL_Pos (9U)
7522 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
7523 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
7524 #define FMC_BCR2_WRAPMOD_Pos (10U)
7525 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
7526 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
7527 #define FMC_BCR2_WAITCFG_Pos (11U)
7528 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
7529 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
7530 #define FMC_BCR2_WREN_Pos (12U)
7531 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
7532 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
7533 #define FMC_BCR2_WAITEN_Pos (13U)
7534 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
7535 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
7536 #define FMC_BCR2_EXTMOD_Pos (14U)
7537 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
7538 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
7539 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
7540 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
7541 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
7542 #define FMC_BCR2_CPSIZE_Pos (16U)
7543 #define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
7544 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
7545 #define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
7546 #define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
7547 #define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
7548 #define FMC_BCR2_CBURSTRW_Pos (19U)
7549 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
7550 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
7551
7552 /****************** Bit definition for FMC_BCR3 register *******************/
7553 #define FMC_BCR3_MBKEN_Pos (0U)
7554 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
7555 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
7556 #define FMC_BCR3_MUXEN_Pos (1U)
7557 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
7558 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7559
7560 #define FMC_BCR3_MTYP_Pos (2U)
7561 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
7562 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7563 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
7564 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
7565
7566 #define FMC_BCR3_MWID_Pos (4U)
7567 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
7568 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7569 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
7570 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
7571
7572 #define FMC_BCR3_FACCEN_Pos (6U)
7573 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
7574 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
7575 #define FMC_BCR3_BURSTEN_Pos (8U)
7576 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
7577 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
7578 #define FMC_BCR3_WAITPOL_Pos (9U)
7579 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
7580 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
7581 #define FMC_BCR3_WRAPMOD_Pos (10U)
7582 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
7583 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
7584 #define FMC_BCR3_WAITCFG_Pos (11U)
7585 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
7586 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
7587 #define FMC_BCR3_WREN_Pos (12U)
7588 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
7589 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
7590 #define FMC_BCR3_WAITEN_Pos (13U)
7591 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
7592 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
7593 #define FMC_BCR3_EXTMOD_Pos (14U)
7594 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
7595 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
7596 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
7597 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
7598 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
7599 #define FMC_BCR3_CPSIZE_Pos (16U)
7600 #define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
7601 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
7602 #define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
7603 #define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
7604 #define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
7605 #define FMC_BCR3_CBURSTRW_Pos (19U)
7606 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
7607 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
7608
7609 /****************** Bit definition for FMC_BCR4 register *******************/
7610 #define FMC_BCR4_MBKEN_Pos (0U)
7611 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
7612 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
7613 #define FMC_BCR4_MUXEN_Pos (1U)
7614 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
7615 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7616
7617 #define FMC_BCR4_MTYP_Pos (2U)
7618 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
7619 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7620 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
7621 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
7622
7623 #define FMC_BCR4_MWID_Pos (4U)
7624 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
7625 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7626 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
7627 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
7628
7629 #define FMC_BCR4_FACCEN_Pos (6U)
7630 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
7631 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
7632 #define FMC_BCR4_BURSTEN_Pos (8U)
7633 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
7634 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
7635 #define FMC_BCR4_WAITPOL_Pos (9U)
7636 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
7637 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
7638 #define FMC_BCR4_WRAPMOD_Pos (10U)
7639 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
7640 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
7641 #define FMC_BCR4_WAITCFG_Pos (11U)
7642 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
7643 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
7644 #define FMC_BCR4_WREN_Pos (12U)
7645 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
7646 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
7647 #define FMC_BCR4_WAITEN_Pos (13U)
7648 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
7649 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
7650 #define FMC_BCR4_EXTMOD_Pos (14U)
7651 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
7652 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
7653 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
7654 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
7655 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
7656 #define FMC_BCR4_CPSIZE_Pos (16U)
7657 #define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
7658 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
7659 #define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
7660 #define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
7661 #define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
7662 #define FMC_BCR4_CBURSTRW_Pos (19U)
7663 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
7664 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
7665
7666 /****************** Bit definition for FMC_BTR1 register ******************/
7667 #define FMC_BTR1_ADDSET_Pos (0U)
7668 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7669 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7670 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7671 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7672 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7673 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
7674
7675 #define FMC_BTR1_ADDHLD_Pos (4U)
7676 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7677 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7678 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
7679 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
7680 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
7681 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
7682
7683 #define FMC_BTR1_DATAST_Pos (8U)
7684 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
7685 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7686 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
7687 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
7688 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
7689 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
7690 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
7691 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
7692 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
7693 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
7694
7695 #define FMC_BTR1_BUSTURN_Pos (16U)
7696 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7697 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7698 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
7699 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
7700 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
7701 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
7702
7703 #define FMC_BTR1_CLKDIV_Pos (20U)
7704 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
7705 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7706 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
7707 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
7708 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
7709 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
7710
7711 #define FMC_BTR1_DATLAT_Pos (24U)
7712 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
7713 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7714 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
7715 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
7716 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
7717 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
7718
7719 #define FMC_BTR1_ACCMOD_Pos (28U)
7720 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
7721 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7722 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
7723 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
7724
7725 /****************** Bit definition for FMC_BTR2 register *******************/
7726 #define FMC_BTR2_ADDSET_Pos (0U)
7727 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
7728 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7729 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
7730 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
7731 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
7732 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
7733
7734 #define FMC_BTR2_ADDHLD_Pos (4U)
7735 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7736 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7737 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
7738 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
7739 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
7740 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7741
7742 #define FMC_BTR2_DATAST_Pos (8U)
7743 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
7744 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7745 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
7746 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
7747 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
7748 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
7749 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
7750 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
7751 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
7752 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
7753
7754 #define FMC_BTR2_BUSTURN_Pos (16U)
7755 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7756 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7757 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
7758 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
7759 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
7760 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
7761
7762 #define FMC_BTR2_CLKDIV_Pos (20U)
7763 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
7764 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7765 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
7766 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
7767 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
7768 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
7769
7770 #define FMC_BTR2_DATLAT_Pos (24U)
7771 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
7772 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7773 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
7774 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
7775 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
7776 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
7777
7778 #define FMC_BTR2_ACCMOD_Pos (28U)
7779 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
7780 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7781 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
7782 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
7783
7784 /******************* Bit definition for FMC_BTR3 register *******************/
7785 #define FMC_BTR3_ADDSET_Pos (0U)
7786 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7787 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7788 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7789 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7790 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7791 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7792
7793 #define FMC_BTR3_ADDHLD_Pos (4U)
7794 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7795 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7796 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7797 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7798 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7799 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
7800
7801 #define FMC_BTR3_DATAST_Pos (8U)
7802 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
7803 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7804 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
7805 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
7806 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
7807 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
7808 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
7809 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
7810 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
7811 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
7812
7813 #define FMC_BTR3_BUSTURN_Pos (16U)
7814 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7815 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7816 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
7817 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
7818 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
7819 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
7820
7821 #define FMC_BTR3_CLKDIV_Pos (20U)
7822 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
7823 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7824 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
7825 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
7826 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
7827 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
7828
7829 #define FMC_BTR3_DATLAT_Pos (24U)
7830 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
7831 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7832 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
7833 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
7834 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
7835 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
7836
7837 #define FMC_BTR3_ACCMOD_Pos (28U)
7838 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
7839 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7840 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
7841 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
7842
7843 /****************** Bit definition for FMC_BTR4 register *******************/
7844 #define FMC_BTR4_ADDSET_Pos (0U)
7845 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
7846 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7847 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
7848 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
7849 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
7850 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7851
7852 #define FMC_BTR4_ADDHLD_Pos (4U)
7853 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7854 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7855 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
7856 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
7857 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
7858 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
7859
7860 #define FMC_BTR4_DATAST_Pos (8U)
7861 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
7862 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7863 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
7864 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
7865 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
7866 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
7867 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
7868 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
7869 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
7870 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
7871
7872 #define FMC_BTR4_BUSTURN_Pos (16U)
7873 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7874 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7875 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
7876 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
7877 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
7878 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
7879
7880 #define FMC_BTR4_CLKDIV_Pos (20U)
7881 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
7882 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7883 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
7884 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
7885 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
7886 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
7887
7888 #define FMC_BTR4_DATLAT_Pos (24U)
7889 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
7890 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7891 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
7892 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
7893 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
7894 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
7895
7896 #define FMC_BTR4_ACCMOD_Pos (28U)
7897 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
7898 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7899 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
7900 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
7901
7902 /****************** Bit definition for FMC_BWTR1 register ******************/
7903 #define FMC_BWTR1_ADDSET_Pos (0U)
7904 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
7905 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7906 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
7907 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
7908 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
7909 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
7910
7911 #define FMC_BWTR1_ADDHLD_Pos (4U)
7912 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7913 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7914 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
7915 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
7916 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
7917 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
7918
7919 #define FMC_BWTR1_DATAST_Pos (8U)
7920 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
7921 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7922 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
7923 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
7924 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
7925 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
7926 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
7927 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
7928 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
7929 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
7930
7931 #define FMC_BWTR1_BUSTURN_Pos (16U)
7932 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7933 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7934 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
7935 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
7936 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
7937 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
7938
7939 #define FMC_BWTR1_ACCMOD_Pos (28U)
7940 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
7941 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7942 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
7943 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
7944
7945 /****************** Bit definition for FMC_BWTR2 register ******************/
7946 #define FMC_BWTR2_ADDSET_Pos (0U)
7947 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7948 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7949 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7950 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7951 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7952 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7953
7954 #define FMC_BWTR2_ADDHLD_Pos (4U)
7955 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7956 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7957 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
7958 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
7959 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
7960 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
7961
7962 #define FMC_BWTR2_DATAST_Pos (8U)
7963 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
7964 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7965 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
7966 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
7967 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
7968 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
7969 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
7970 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
7971 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
7972 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
7973
7974 #define FMC_BWTR2_BUSTURN_Pos (16U)
7975 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7976 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7977 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
7978 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
7979 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
7980 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
7981
7982 #define FMC_BWTR2_ACCMOD_Pos (28U)
7983 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
7984 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7985 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
7986 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
7987
7988 /****************** Bit definition for FMC_BWTR3 register ******************/
7989 #define FMC_BWTR3_ADDSET_Pos (0U)
7990 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
7991 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7992 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
7993 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
7994 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
7995 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7996
7997 #define FMC_BWTR3_ADDHLD_Pos (4U)
7998 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7999 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8000 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
8001 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
8002 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
8003 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
8004
8005 #define FMC_BWTR3_DATAST_Pos (8U)
8006 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
8007 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8008 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
8009 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
8010 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
8011 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
8012 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
8013 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
8014 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
8015 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
8016
8017 #define FMC_BWTR3_BUSTURN_Pos (16U)
8018 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
8019 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
8020 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
8021 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
8022 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
8023 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
8024
8025 #define FMC_BWTR3_ACCMOD_Pos (28U)
8026 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
8027 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8028 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
8029 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
8030
8031 /****************** Bit definition for FMC_BWTR4 register ******************/
8032 #define FMC_BWTR4_ADDSET_Pos (0U)
8033 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
8034 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8035 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
8036 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
8037 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
8038 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
8039
8040 #define FMC_BWTR4_ADDHLD_Pos (4U)
8041 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
8042 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8043 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
8044 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
8045 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
8046 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
8047
8048 #define FMC_BWTR4_DATAST_Pos (8U)
8049 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
8050 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8051 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
8052 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
8053 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
8054 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
8055 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
8056 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
8057 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
8058 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
8059
8060 #define FMC_BWTR4_BUSTURN_Pos (16U)
8061 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
8062 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
8063 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
8064 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
8065 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
8066 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
8067
8068 #define FMC_BWTR4_ACCMOD_Pos (28U)
8069 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
8070 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8071 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
8072 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
8073
8074 /****************** Bit definition for FMC_PCR2 register *******************/
8075
8076 #define FMC_PCR2_PWAITEN_Pos (1U)
8077 #define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
8078 #define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
8079 #define FMC_PCR2_PBKEN_Pos (2U)
8080 #define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
8081 #define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
8082 #define FMC_PCR2_PTYP_Pos (3U)
8083 #define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
8084 #define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
8085
8086 #define FMC_PCR2_PWID_Pos (4U)
8087 #define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
8088 #define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
8089 #define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
8090 #define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
8091
8092 #define FMC_PCR2_ECCEN_Pos (6U)
8093 #define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
8094 #define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
8095
8096 #define FMC_PCR2_TCLR_Pos (9U)
8097 #define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
8098 #define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
8099 #define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
8100 #define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
8101 #define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
8102 #define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
8103
8104 #define FMC_PCR2_TAR_Pos (13U)
8105 #define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
8106 #define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
8107 #define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
8108 #define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
8109 #define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
8110 #define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
8111
8112 #define FMC_PCR2_ECCPS_Pos (17U)
8113 #define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
8114 #define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
8115 #define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
8116 #define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
8117 #define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
8118
8119 /****************** Bit definition for FMC_PCR3 register *******************/
8120 #define FMC_PCR3_PWAITEN_Pos (1U)
8121 #define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
8122 #define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
8123 #define FMC_PCR3_PBKEN_Pos (2U)
8124 #define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
8125 #define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
8126 #define FMC_PCR3_PTYP_Pos (3U)
8127 #define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
8128 #define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
8129
8130 #define FMC_PCR3_PWID_Pos (4U)
8131 #define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
8132 #define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
8133 #define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
8134 #define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
8135
8136 #define FMC_PCR3_ECCEN_Pos (6U)
8137 #define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
8138 #define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
8139
8140 #define FMC_PCR3_TCLR_Pos (9U)
8141 #define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
8142 #define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
8143 #define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
8144 #define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
8145 #define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
8146 #define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
8147
8148 #define FMC_PCR3_TAR_Pos (13U)
8149 #define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
8150 #define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
8151 #define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
8152 #define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
8153 #define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
8154 #define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
8155
8156 #define FMC_PCR3_ECCPS_Pos (17U)
8157 #define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
8158 #define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
8159 #define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
8160 #define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
8161 #define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
8162
8163 /****************** Bit definition for FMC_PCR4 register *******************/
8164 #define FMC_PCR4_PWAITEN_Pos (1U)
8165 #define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
8166 #define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
8167 #define FMC_PCR4_PBKEN_Pos (2U)
8168 #define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
8169 #define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
8170 #define FMC_PCR4_PTYP_Pos (3U)
8171 #define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
8172 #define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
8173
8174 #define FMC_PCR4_PWID_Pos (4U)
8175 #define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
8176 #define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
8177 #define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
8178 #define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
8179
8180 #define FMC_PCR4_ECCEN_Pos (6U)
8181 #define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
8182 #define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
8183
8184 #define FMC_PCR4_TCLR_Pos (9U)
8185 #define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
8186 #define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
8187 #define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
8188 #define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
8189 #define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
8190 #define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
8191
8192 #define FMC_PCR4_TAR_Pos (13U)
8193 #define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
8194 #define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
8195 #define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
8196 #define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
8197 #define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
8198 #define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
8199
8200 #define FMC_PCR4_ECCPS_Pos (17U)
8201 #define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
8202 #define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
8203 #define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
8204 #define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
8205 #define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
8206
8207 /******************* Bit definition for FMC_SR2 register *******************/
8208 #define FMC_SR2_IRS_Pos (0U)
8209 #define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
8210 #define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
8211 #define FMC_SR2_ILS_Pos (1U)
8212 #define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
8213 #define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
8214 #define FMC_SR2_IFS_Pos (2U)
8215 #define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
8216 #define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
8217 #define FMC_SR2_IREN_Pos (3U)
8218 #define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
8219 #define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8220 #define FMC_SR2_ILEN_Pos (4U)
8221 #define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
8222 #define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8223 #define FMC_SR2_IFEN_Pos (5U)
8224 #define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
8225 #define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8226 #define FMC_SR2_FEMPT_Pos (6U)
8227 #define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
8228 #define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
8229
8230 /******************* Bit definition for FMC_SR3 register *******************/
8231 #define FMC_SR3_IRS_Pos (0U)
8232 #define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
8233 #define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
8234 #define FMC_SR3_ILS_Pos (1U)
8235 #define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
8236 #define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
8237 #define FMC_SR3_IFS_Pos (2U)
8238 #define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
8239 #define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
8240 #define FMC_SR3_IREN_Pos (3U)
8241 #define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
8242 #define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8243 #define FMC_SR3_ILEN_Pos (4U)
8244 #define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
8245 #define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8246 #define FMC_SR3_IFEN_Pos (5U)
8247 #define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
8248 #define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8249 #define FMC_SR3_FEMPT_Pos (6U)
8250 #define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
8251 #define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
8252
8253 /******************* Bit definition for FMC_SR4 register *******************/
8254 #define FMC_SR4_IRS_Pos (0U)
8255 #define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
8256 #define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
8257 #define FMC_SR4_ILS_Pos (1U)
8258 #define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
8259 #define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
8260 #define FMC_SR4_IFS_Pos (2U)
8261 #define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
8262 #define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
8263 #define FMC_SR4_IREN_Pos (3U)
8264 #define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
8265 #define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8266 #define FMC_SR4_ILEN_Pos (4U)
8267 #define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
8268 #define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8269 #define FMC_SR4_IFEN_Pos (5U)
8270 #define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
8271 #define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8272 #define FMC_SR4_FEMPT_Pos (6U)
8273 #define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
8274 #define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
8275
8276 /****************** Bit definition for FMC_PMEM2 register ******************/
8277 #define FMC_PMEM2_MEMSET2_Pos (0U)
8278 #define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
8279 #define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
8280 #define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
8281 #define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
8282 #define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
8283 #define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
8284 #define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
8285 #define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
8286 #define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
8287 #define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
8288
8289 #define FMC_PMEM2_MEMWAIT2_Pos (8U)
8290 #define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
8291 #define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
8292 #define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
8293 #define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
8294 #define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
8295 #define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
8296 #define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
8297 #define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
8298 #define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
8299 #define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
8300
8301 #define FMC_PMEM2_MEMHOLD2_Pos (16U)
8302 #define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
8303 #define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
8304 #define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
8305 #define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
8306 #define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
8307 #define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
8308 #define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
8309 #define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
8310 #define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
8311 #define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
8312
8313 #define FMC_PMEM2_MEMHIZ2_Pos (24U)
8314 #define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
8315 #define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
8316 #define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
8317 #define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
8318 #define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
8319 #define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
8320 #define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
8321 #define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
8322 #define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
8323 #define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
8324
8325 /****************** Bit definition for FMC_PMEM3 register ******************/
8326 #define FMC_PMEM3_MEMSET3_Pos (0U)
8327 #define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
8328 #define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
8329 #define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
8330 #define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
8331 #define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
8332 #define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
8333 #define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
8334 #define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
8335 #define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
8336 #define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
8337
8338 #define FMC_PMEM3_MEMWAIT3_Pos (8U)
8339 #define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
8340 #define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
8341 #define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
8342 #define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
8343 #define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
8344 #define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
8345 #define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
8346 #define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
8347 #define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
8348 #define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
8349
8350 #define FMC_PMEM3_MEMHOLD3_Pos (16U)
8351 #define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
8352 #define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
8353 #define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
8354 #define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
8355 #define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
8356 #define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
8357 #define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
8358 #define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
8359 #define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
8360 #define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
8361
8362 #define FMC_PMEM3_MEMHIZ3_Pos (24U)
8363 #define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
8364 #define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
8365 #define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
8366 #define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
8367 #define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
8368 #define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
8369 #define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
8370 #define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
8371 #define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
8372 #define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
8373
8374 /****************** Bit definition for FMC_PMEM4 register ******************/
8375 #define FMC_PMEM4_MEMSET4_Pos (0U)
8376 #define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
8377 #define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
8378 #define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
8379 #define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
8380 #define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
8381 #define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
8382 #define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
8383 #define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
8384 #define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
8385 #define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
8386
8387 #define FMC_PMEM4_MEMWAIT4_Pos (8U)
8388 #define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
8389 #define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
8390 #define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
8391 #define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
8392 #define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
8393 #define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
8394 #define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
8395 #define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
8396 #define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
8397 #define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
8398
8399 #define FMC_PMEM4_MEMHOLD4_Pos (16U)
8400 #define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
8401 #define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
8402 #define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
8403 #define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
8404 #define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
8405 #define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
8406 #define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
8407 #define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
8408 #define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
8409 #define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
8410
8411 #define FMC_PMEM4_MEMHIZ4_Pos (24U)
8412 #define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
8413 #define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
8414 #define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
8415 #define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
8416 #define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
8417 #define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
8418 #define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
8419 #define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
8420 #define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
8421 #define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
8422
8423 /****************** Bit definition for FMC_PATT2 register ******************/
8424 #define FMC_PATT2_ATTSET2_Pos (0U)
8425 #define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
8426 #define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
8427 #define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
8428 #define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
8429 #define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
8430 #define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
8431 #define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
8432 #define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
8433 #define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
8434 #define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
8435
8436 #define FMC_PATT2_ATTWAIT2_Pos (8U)
8437 #define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
8438 #define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
8439 #define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
8440 #define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
8441 #define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
8442 #define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
8443 #define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
8444 #define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
8445 #define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
8446 #define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
8447
8448 #define FMC_PATT2_ATTHOLD2_Pos (16U)
8449 #define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
8450 #define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
8451 #define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
8452 #define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
8453 #define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
8454 #define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
8455 #define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
8456 #define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
8457 #define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
8458 #define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
8459
8460 #define FMC_PATT2_ATTHIZ2_Pos (24U)
8461 #define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
8462 #define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
8463 #define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
8464 #define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
8465 #define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
8466 #define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
8467 #define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
8468 #define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
8469 #define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
8470 #define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
8471
8472 /****************** Bit definition for FMC_PATT3 register ******************/
8473 #define FMC_PATT3_ATTSET3_Pos (0U)
8474 #define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
8475 #define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
8476 #define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
8477 #define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
8478 #define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
8479 #define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
8480 #define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
8481 #define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
8482 #define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
8483 #define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
8484
8485 #define FMC_PATT3_ATTWAIT3_Pos (8U)
8486 #define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
8487 #define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
8488 #define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
8489 #define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
8490 #define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
8491 #define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
8492 #define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
8493 #define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
8494 #define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
8495 #define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
8496
8497 #define FMC_PATT3_ATTHOLD3_Pos (16U)
8498 #define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
8499 #define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
8500 #define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
8501 #define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
8502 #define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
8503 #define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
8504 #define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
8505 #define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
8506 #define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
8507 #define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
8508
8509 #define FMC_PATT3_ATTHIZ3_Pos (24U)
8510 #define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
8511 #define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
8512 #define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
8513 #define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
8514 #define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
8515 #define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
8516 #define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
8517 #define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
8518 #define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
8519 #define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
8520
8521 /****************** Bit definition for FMC_PATT4 register ******************/
8522 #define FMC_PATT4_ATTSET4_Pos (0U)
8523 #define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
8524 #define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
8525 #define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
8526 #define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
8527 #define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
8528 #define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
8529 #define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
8530 #define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
8531 #define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
8532 #define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
8533
8534 #define FMC_PATT4_ATTWAIT4_Pos (8U)
8535 #define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
8536 #define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
8537 #define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
8538 #define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
8539 #define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
8540 #define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
8541 #define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
8542 #define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
8543 #define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
8544 #define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
8545
8546 #define FMC_PATT4_ATTHOLD4_Pos (16U)
8547 #define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
8548 #define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
8549 #define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
8550 #define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
8551 #define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
8552 #define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
8553 #define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
8554 #define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
8555 #define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
8556 #define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
8557
8558 #define FMC_PATT4_ATTHIZ4_Pos (24U)
8559 #define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
8560 #define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
8561 #define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
8562 #define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
8563 #define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
8564 #define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
8565 #define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
8566 #define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
8567 #define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
8568 #define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
8569
8570 /****************** Bit definition for FMC_PIO4 register *******************/
8571 #define FMC_PIO4_IOSET4_Pos (0U)
8572 #define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
8573 #define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
8574 #define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
8575 #define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
8576 #define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
8577 #define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
8578 #define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
8579 #define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
8580 #define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
8581 #define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
8582
8583 #define FMC_PIO4_IOWAIT4_Pos (8U)
8584 #define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
8585 #define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
8586 #define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
8587 #define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
8588 #define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
8589 #define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
8590 #define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
8591 #define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
8592 #define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
8593 #define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
8594
8595 #define FMC_PIO4_IOHOLD4_Pos (16U)
8596 #define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
8597 #define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
8598 #define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
8599 #define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
8600 #define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
8601 #define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
8602 #define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
8603 #define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
8604 #define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
8605 #define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
8606
8607 #define FMC_PIO4_IOHIZ4_Pos (24U)
8608 #define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
8609 #define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
8610 #define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
8611 #define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
8612 #define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
8613 #define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
8614 #define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
8615 #define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
8616 #define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
8617 #define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
8618
8619
8620 /****************** Bit definition for FMC_ECCR2 register ******************/
8621 #define FMC_ECCR2_ECC2_Pos (0U)
8622 #define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
8623 #define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
8624
8625 /****************** Bit definition for FMC_ECCR3 register ******************/
8626 #define FMC_ECCR3_ECC3_Pos (0U)
8627 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
8628 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
8629
8630 /****************** Bit definition for FMC_SDCR1 register ******************/
8631 #define FMC_SDCR1_NC_Pos (0U)
8632 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
8633 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
8634 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
8635 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
8636
8637 #define FMC_SDCR1_NR_Pos (2U)
8638 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
8639 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
8640 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
8641 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
8642
8643 #define FMC_SDCR1_MWID_Pos (4U)
8644 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
8645 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
8646 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
8647 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
8648
8649 #define FMC_SDCR1_NB_Pos (6U)
8650 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
8651 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
8652
8653 #define FMC_SDCR1_CAS_Pos (7U)
8654 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
8655 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
8656 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
8657 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
8658
8659 #define FMC_SDCR1_WP_Pos (9U)
8660 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
8661 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
8662
8663 #define FMC_SDCR1_SDCLK_Pos (10U)
8664 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8665 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
8666 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8667 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
8668
8669 #define FMC_SDCR1_RBURST_Pos (12U)
8670 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
8671 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
8672
8673 #define FMC_SDCR1_RPIPE_Pos (13U)
8674 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
8675 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
8676 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
8677 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
8678
8679 /****************** Bit definition for FMC_SDCR2 register ******************/
8680 #define FMC_SDCR2_NC_Pos (0U)
8681 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
8682 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
8683 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
8684 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
8685
8686 #define FMC_SDCR2_NR_Pos (2U)
8687 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
8688 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
8689 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
8690 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
8691
8692 #define FMC_SDCR2_MWID_Pos (4U)
8693 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
8694 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
8695 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
8696 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
8697
8698 #define FMC_SDCR2_NB_Pos (6U)
8699 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
8700 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
8701
8702 #define FMC_SDCR2_CAS_Pos (7U)
8703 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
8704 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
8705 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
8706 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
8707
8708 #define FMC_SDCR2_WP_Pos (9U)
8709 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
8710 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
8711
8712 #define FMC_SDCR2_SDCLK_Pos (10U)
8713 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
8714 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
8715 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
8716 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
8717
8718 #define FMC_SDCR2_RBURST_Pos (12U)
8719 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
8720 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
8721
8722 #define FMC_SDCR2_RPIPE_Pos (13U)
8723 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
8724 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
8725 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
8726 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
8727
8728 /****************** Bit definition for FMC_SDTR1 register ******************/
8729 #define FMC_SDTR1_TMRD_Pos (0U)
8730 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
8731 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
8732 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
8733 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
8734 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
8735 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
8736
8737 #define FMC_SDTR1_TXSR_Pos (4U)
8738 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
8739 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
8740 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
8741 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
8742 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
8743 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
8744
8745 #define FMC_SDTR1_TRAS_Pos (8U)
8746 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
8747 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
8748 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
8749 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
8750 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
8751 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
8752
8753 #define FMC_SDTR1_TRC_Pos (12U)
8754 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
8755 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
8756 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
8757 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
8758 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
8759
8760 #define FMC_SDTR1_TWR_Pos (16U)
8761 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8762 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
8763 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8764 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8765 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
8766
8767 #define FMC_SDTR1_TRP_Pos (20U)
8768 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
8769 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
8770 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
8771 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
8772 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
8773
8774 #define FMC_SDTR1_TRCD_Pos (24U)
8775 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8776 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
8777 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8778 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8779 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
8780
8781 /****************** Bit definition for FMC_SDTR2 register ******************/
8782 #define FMC_SDTR2_TMRD_Pos (0U)
8783 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
8784 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
8785 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
8786 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
8787 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
8788 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
8789
8790 #define FMC_SDTR2_TXSR_Pos (4U)
8791 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
8792 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
8793 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
8794 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
8795 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
8796 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
8797
8798 #define FMC_SDTR2_TRAS_Pos (8U)
8799 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8800 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
8801 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8802 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8803 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8804 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
8805
8806 #define FMC_SDTR2_TRC_Pos (12U)
8807 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8808 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
8809 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8810 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8811 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
8812
8813 #define FMC_SDTR2_TWR_Pos (16U)
8814 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8815 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
8816 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8817 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8818 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
8819
8820 #define FMC_SDTR2_TRP_Pos (20U)
8821 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
8822 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
8823 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
8824 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
8825 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
8826
8827 #define FMC_SDTR2_TRCD_Pos (24U)
8828 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
8829 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
8830 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
8831 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
8832 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
8833
8834 /****************** Bit definition for FMC_SDCMR register ******************/
8835 #define FMC_SDCMR_MODE_Pos (0U)
8836 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
8837 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
8838 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
8839 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
8840 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
8841
8842 #define FMC_SDCMR_CTB2_Pos (3U)
8843 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
8844 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
8845
8846 #define FMC_SDCMR_CTB1_Pos (4U)
8847 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
8848 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
8849
8850 #define FMC_SDCMR_NRFS_Pos (5U)
8851 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
8852 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
8853 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
8854 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
8855 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
8856 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
8857
8858 #define FMC_SDCMR_MRD_Pos (9U)
8859 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
8860 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
8861
8862 /****************** Bit definition for FMC_SDRTR register ******************/
8863 #define FMC_SDRTR_CRE_Pos (0U)
8864 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
8865 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
8866
8867 #define FMC_SDRTR_COUNT_Pos (1U)
8868 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
8869 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
8870
8871 #define FMC_SDRTR_REIE_Pos (14U)
8872 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
8873 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
8874
8875 /****************** Bit definition for FMC_SDSR register ******************/
8876 #define FMC_SDSR_RE_Pos (0U)
8877 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
8878 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
8879
8880 #define FMC_SDSR_MODES1_Pos (1U)
8881 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
8882 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
8883 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
8884 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
8885
8886 #define FMC_SDSR_MODES2_Pos (3U)
8887 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
8888 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
8889 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
8890 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
8891 #define FMC_SDSR_BUSY_Pos (5U)
8892 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
8893 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
8894
8895 /******************************************************************************/
8896 /* */
8897 /* General Purpose I/O */
8898 /* */
8899 /******************************************************************************/
8900 /****************** Bits definition for GPIO_MODER register *****************/
8901 #define GPIO_MODER_MODE0_Pos (0U)
8902 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
8903 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
8904 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
8905 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
8906 #define GPIO_MODER_MODE1_Pos (2U)
8907 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
8908 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
8909 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
8910 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
8911 #define GPIO_MODER_MODE2_Pos (4U)
8912 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
8913 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
8914 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
8915 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
8916 #define GPIO_MODER_MODE3_Pos (6U)
8917 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
8918 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
8919 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
8920 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
8921 #define GPIO_MODER_MODE4_Pos (8U)
8922 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
8923 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
8924 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
8925 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
8926 #define GPIO_MODER_MODE5_Pos (10U)
8927 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
8928 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
8929 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
8930 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
8931 #define GPIO_MODER_MODE6_Pos (12U)
8932 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
8933 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
8934 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
8935 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
8936 #define GPIO_MODER_MODE7_Pos (14U)
8937 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
8938 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
8939 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
8940 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
8941 #define GPIO_MODER_MODE8_Pos (16U)
8942 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
8943 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
8944 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
8945 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
8946 #define GPIO_MODER_MODE9_Pos (18U)
8947 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
8948 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
8949 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
8950 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
8951 #define GPIO_MODER_MODE10_Pos (20U)
8952 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
8953 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
8954 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
8955 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
8956 #define GPIO_MODER_MODE11_Pos (22U)
8957 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
8958 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
8959 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
8960 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
8961 #define GPIO_MODER_MODE12_Pos (24U)
8962 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
8963 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
8964 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
8965 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
8966 #define GPIO_MODER_MODE13_Pos (26U)
8967 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
8968 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
8969 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
8970 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
8971 #define GPIO_MODER_MODE14_Pos (28U)
8972 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
8973 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8974 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
8975 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
8976 #define GPIO_MODER_MODE15_Pos (30U)
8977 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
8978 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8979 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
8980 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
8981
8982 /* Legacy defines */
8983 #define GPIO_MODER_MODER0_Pos (0U)
8984 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
8985 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8986 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
8987 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
8988 #define GPIO_MODER_MODER1_Pos (2U)
8989 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
8990 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8991 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
8992 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
8993 #define GPIO_MODER_MODER2_Pos (4U)
8994 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
8995 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8996 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
8997 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
8998 #define GPIO_MODER_MODER3_Pos (6U)
8999 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
9000 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
9001 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
9002 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
9003 #define GPIO_MODER_MODER4_Pos (8U)
9004 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
9005 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
9006 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
9007 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
9008 #define GPIO_MODER_MODER5_Pos (10U)
9009 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
9010 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
9011 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
9012 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
9013 #define GPIO_MODER_MODER6_Pos (12U)
9014 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
9015 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
9016 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
9017 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
9018 #define GPIO_MODER_MODER7_Pos (14U)
9019 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
9020 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
9021 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
9022 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
9023 #define GPIO_MODER_MODER8_Pos (16U)
9024 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
9025 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
9026 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
9027 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
9028 #define GPIO_MODER_MODER9_Pos (18U)
9029 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
9030 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
9031 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
9032 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
9033 #define GPIO_MODER_MODER10_Pos (20U)
9034 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
9035 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
9036 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
9037 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
9038 #define GPIO_MODER_MODER11_Pos (22U)
9039 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
9040 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
9041 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
9042 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
9043 #define GPIO_MODER_MODER12_Pos (24U)
9044 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
9045 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
9046 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
9047 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
9048 #define GPIO_MODER_MODER13_Pos (26U)
9049 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
9050 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
9051 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
9052 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
9053 #define GPIO_MODER_MODER14_Pos (28U)
9054 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
9055 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
9056 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
9057 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
9058 #define GPIO_MODER_MODER15_Pos (30U)
9059 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
9060 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
9061 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
9062 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
9063
9064 /****************** Bits definition for GPIO_OTYPER register ****************/
9065 #define GPIO_OTYPER_OT0_Pos (0U)
9066 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
9067 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
9068 #define GPIO_OTYPER_OT1_Pos (1U)
9069 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
9070 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
9071 #define GPIO_OTYPER_OT2_Pos (2U)
9072 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
9073 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
9074 #define GPIO_OTYPER_OT3_Pos (3U)
9075 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
9076 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
9077 #define GPIO_OTYPER_OT4_Pos (4U)
9078 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
9079 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
9080 #define GPIO_OTYPER_OT5_Pos (5U)
9081 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
9082 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
9083 #define GPIO_OTYPER_OT6_Pos (6U)
9084 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
9085 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
9086 #define GPIO_OTYPER_OT7_Pos (7U)
9087 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
9088 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
9089 #define GPIO_OTYPER_OT8_Pos (8U)
9090 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
9091 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
9092 #define GPIO_OTYPER_OT9_Pos (9U)
9093 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
9094 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
9095 #define GPIO_OTYPER_OT10_Pos (10U)
9096 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
9097 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
9098 #define GPIO_OTYPER_OT11_Pos (11U)
9099 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
9100 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
9101 #define GPIO_OTYPER_OT12_Pos (12U)
9102 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
9103 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
9104 #define GPIO_OTYPER_OT13_Pos (13U)
9105 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
9106 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
9107 #define GPIO_OTYPER_OT14_Pos (14U)
9108 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
9109 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
9110 #define GPIO_OTYPER_OT15_Pos (15U)
9111 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
9112 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
9113
9114 /* Legacy defines */
9115 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
9116 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
9117 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
9118 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
9119 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
9120 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
9121 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
9122 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
9123 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
9124 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
9125 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
9126 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
9127 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
9128 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
9129 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
9130 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
9131
9132 /****************** Bits definition for GPIO_OSPEEDR register ***************/
9133 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
9134 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
9135 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
9136 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
9137 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
9138 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
9139 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
9140 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
9141 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
9142 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
9143 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
9144 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
9145 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
9146 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
9147 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
9148 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
9149 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
9150 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
9151 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
9152 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
9153 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
9154 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
9155 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
9156 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
9157 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
9158 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
9159 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
9160 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
9161 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
9162 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
9163 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
9164 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
9165 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
9166 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
9167 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
9168 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
9169 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
9170 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
9171 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
9172 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
9173 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
9174 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
9175 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
9176 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
9177 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
9178 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
9179 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
9180 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
9181 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
9182 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
9183 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
9184 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
9185 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
9186 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
9187 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
9188 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
9189 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
9190 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
9191 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
9192 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
9193 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
9194 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
9195 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
9196 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
9197 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
9198 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
9199 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
9200 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
9201 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
9202 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
9203 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
9204 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
9205 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
9206 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
9207 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
9208 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
9209 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
9210 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
9211 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
9212 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
9213
9214 /* Legacy defines */
9215 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
9216 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
9217 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
9218 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
9219 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
9220 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
9221 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
9222 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
9223 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
9224 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
9225 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
9226 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
9227 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
9228 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
9229 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
9230 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
9231 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
9232 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
9233 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
9234 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
9235 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
9236 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
9237 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
9238 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
9239 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
9240 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
9241 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
9242 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
9243 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
9244 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
9245 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
9246 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
9247 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
9248 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
9249 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
9250 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
9251 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
9252 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
9253 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
9254 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
9255 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
9256 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
9257 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
9258 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
9259 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
9260 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
9261 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
9262 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
9263
9264 /****************** Bits definition for GPIO_PUPDR register *****************/
9265 #define GPIO_PUPDR_PUPD0_Pos (0U)
9266 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
9267 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
9268 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
9269 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
9270 #define GPIO_PUPDR_PUPD1_Pos (2U)
9271 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
9272 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
9273 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
9274 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
9275 #define GPIO_PUPDR_PUPD2_Pos (4U)
9276 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
9277 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
9278 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
9279 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
9280 #define GPIO_PUPDR_PUPD3_Pos (6U)
9281 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
9282 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
9283 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
9284 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
9285 #define GPIO_PUPDR_PUPD4_Pos (8U)
9286 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
9287 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
9288 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
9289 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
9290 #define GPIO_PUPDR_PUPD5_Pos (10U)
9291 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
9292 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
9293 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
9294 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
9295 #define GPIO_PUPDR_PUPD6_Pos (12U)
9296 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
9297 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
9298 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
9299 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
9300 #define GPIO_PUPDR_PUPD7_Pos (14U)
9301 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
9302 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
9303 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
9304 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
9305 #define GPIO_PUPDR_PUPD8_Pos (16U)
9306 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
9307 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
9308 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
9309 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
9310 #define GPIO_PUPDR_PUPD9_Pos (18U)
9311 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
9312 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
9313 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
9314 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
9315 #define GPIO_PUPDR_PUPD10_Pos (20U)
9316 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
9317 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
9318 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
9319 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
9320 #define GPIO_PUPDR_PUPD11_Pos (22U)
9321 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
9322 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
9323 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
9324 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
9325 #define GPIO_PUPDR_PUPD12_Pos (24U)
9326 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
9327 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
9328 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
9329 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
9330 #define GPIO_PUPDR_PUPD13_Pos (26U)
9331 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
9332 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
9333 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
9334 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
9335 #define GPIO_PUPDR_PUPD14_Pos (28U)
9336 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
9337 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
9338 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
9339 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
9340 #define GPIO_PUPDR_PUPD15_Pos (30U)
9341 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
9342 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
9343 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
9344 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
9345
9346 /* Legacy defines */
9347 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
9348 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
9349 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
9350 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
9351 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
9352 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
9353 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
9354 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
9355 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
9356 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
9357 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
9358 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
9359 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
9360 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
9361 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
9362 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
9363 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
9364 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
9365 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
9366 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
9367 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
9368 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
9369 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
9370 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
9371 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
9372 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
9373 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
9374 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
9375 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
9376 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
9377 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
9378 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
9379 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
9380 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
9381 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
9382 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
9383 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
9384 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
9385 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
9386 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
9387 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
9388 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
9389 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
9390 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
9391 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
9392 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
9393 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
9394 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
9395
9396 /****************** Bits definition for GPIO_IDR register *******************/
9397 #define GPIO_IDR_ID0_Pos (0U)
9398 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
9399 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
9400 #define GPIO_IDR_ID1_Pos (1U)
9401 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
9402 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
9403 #define GPIO_IDR_ID2_Pos (2U)
9404 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
9405 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
9406 #define GPIO_IDR_ID3_Pos (3U)
9407 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
9408 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
9409 #define GPIO_IDR_ID4_Pos (4U)
9410 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
9411 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
9412 #define GPIO_IDR_ID5_Pos (5U)
9413 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
9414 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
9415 #define GPIO_IDR_ID6_Pos (6U)
9416 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
9417 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
9418 #define GPIO_IDR_ID7_Pos (7U)
9419 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
9420 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
9421 #define GPIO_IDR_ID8_Pos (8U)
9422 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
9423 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
9424 #define GPIO_IDR_ID9_Pos (9U)
9425 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
9426 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
9427 #define GPIO_IDR_ID10_Pos (10U)
9428 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
9429 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
9430 #define GPIO_IDR_ID11_Pos (11U)
9431 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
9432 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
9433 #define GPIO_IDR_ID12_Pos (12U)
9434 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
9435 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
9436 #define GPIO_IDR_ID13_Pos (13U)
9437 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
9438 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
9439 #define GPIO_IDR_ID14_Pos (14U)
9440 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
9441 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
9442 #define GPIO_IDR_ID15_Pos (15U)
9443 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
9444 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
9445
9446 /* Legacy defines */
9447 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
9448 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
9449 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
9450 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
9451 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
9452 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
9453 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
9454 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
9455 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
9456 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
9457 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
9458 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
9459 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
9460 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
9461 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
9462 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
9463
9464 /****************** Bits definition for GPIO_ODR register *******************/
9465 #define GPIO_ODR_OD0_Pos (0U)
9466 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
9467 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
9468 #define GPIO_ODR_OD1_Pos (1U)
9469 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
9470 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
9471 #define GPIO_ODR_OD2_Pos (2U)
9472 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
9473 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
9474 #define GPIO_ODR_OD3_Pos (3U)
9475 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
9476 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
9477 #define GPIO_ODR_OD4_Pos (4U)
9478 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
9479 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
9480 #define GPIO_ODR_OD5_Pos (5U)
9481 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
9482 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
9483 #define GPIO_ODR_OD6_Pos (6U)
9484 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
9485 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
9486 #define GPIO_ODR_OD7_Pos (7U)
9487 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
9488 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
9489 #define GPIO_ODR_OD8_Pos (8U)
9490 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
9491 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
9492 #define GPIO_ODR_OD9_Pos (9U)
9493 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
9494 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
9495 #define GPIO_ODR_OD10_Pos (10U)
9496 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
9497 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
9498 #define GPIO_ODR_OD11_Pos (11U)
9499 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
9500 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
9501 #define GPIO_ODR_OD12_Pos (12U)
9502 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
9503 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
9504 #define GPIO_ODR_OD13_Pos (13U)
9505 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
9506 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
9507 #define GPIO_ODR_OD14_Pos (14U)
9508 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
9509 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
9510 #define GPIO_ODR_OD15_Pos (15U)
9511 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
9512 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
9513 /* Legacy defines */
9514 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
9515 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
9516 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
9517 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
9518 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
9519 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
9520 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
9521 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
9522 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
9523 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
9524 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
9525 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
9526 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
9527 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
9528 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
9529 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
9530
9531 /****************** Bits definition for GPIO_BSRR register ******************/
9532 #define GPIO_BSRR_BS0_Pos (0U)
9533 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
9534 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
9535 #define GPIO_BSRR_BS1_Pos (1U)
9536 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
9537 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
9538 #define GPIO_BSRR_BS2_Pos (2U)
9539 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
9540 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
9541 #define GPIO_BSRR_BS3_Pos (3U)
9542 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
9543 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
9544 #define GPIO_BSRR_BS4_Pos (4U)
9545 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
9546 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
9547 #define GPIO_BSRR_BS5_Pos (5U)
9548 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
9549 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
9550 #define GPIO_BSRR_BS6_Pos (6U)
9551 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
9552 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
9553 #define GPIO_BSRR_BS7_Pos (7U)
9554 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
9555 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
9556 #define GPIO_BSRR_BS8_Pos (8U)
9557 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
9558 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
9559 #define GPIO_BSRR_BS9_Pos (9U)
9560 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
9561 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
9562 #define GPIO_BSRR_BS10_Pos (10U)
9563 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
9564 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
9565 #define GPIO_BSRR_BS11_Pos (11U)
9566 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
9567 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
9568 #define GPIO_BSRR_BS12_Pos (12U)
9569 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
9570 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
9571 #define GPIO_BSRR_BS13_Pos (13U)
9572 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
9573 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
9574 #define GPIO_BSRR_BS14_Pos (14U)
9575 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
9576 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
9577 #define GPIO_BSRR_BS15_Pos (15U)
9578 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
9579 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
9580 #define GPIO_BSRR_BR0_Pos (16U)
9581 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
9582 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
9583 #define GPIO_BSRR_BR1_Pos (17U)
9584 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
9585 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
9586 #define GPIO_BSRR_BR2_Pos (18U)
9587 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
9588 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
9589 #define GPIO_BSRR_BR3_Pos (19U)
9590 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
9591 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
9592 #define GPIO_BSRR_BR4_Pos (20U)
9593 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
9594 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
9595 #define GPIO_BSRR_BR5_Pos (21U)
9596 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
9597 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
9598 #define GPIO_BSRR_BR6_Pos (22U)
9599 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
9600 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
9601 #define GPIO_BSRR_BR7_Pos (23U)
9602 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
9603 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
9604 #define GPIO_BSRR_BR8_Pos (24U)
9605 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
9606 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
9607 #define GPIO_BSRR_BR9_Pos (25U)
9608 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
9609 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
9610 #define GPIO_BSRR_BR10_Pos (26U)
9611 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
9612 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
9613 #define GPIO_BSRR_BR11_Pos (27U)
9614 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
9615 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
9616 #define GPIO_BSRR_BR12_Pos (28U)
9617 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
9618 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
9619 #define GPIO_BSRR_BR13_Pos (29U)
9620 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
9621 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
9622 #define GPIO_BSRR_BR14_Pos (30U)
9623 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
9624 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
9625 #define GPIO_BSRR_BR15_Pos (31U)
9626 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
9627 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
9628
9629 /* Legacy defines */
9630 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
9631 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
9632 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
9633 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
9634 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
9635 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
9636 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
9637 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
9638 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
9639 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
9640 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
9641 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
9642 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
9643 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
9644 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
9645 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
9646 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
9647 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
9648 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
9649 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
9650 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
9651 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
9652 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
9653 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
9654 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
9655 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
9656 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
9657 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
9658 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
9659 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
9660 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
9661 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
9662 /****************** Bit definition for GPIO_LCKR register *********************/
9663 #define GPIO_LCKR_LCK0_Pos (0U)
9664 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
9665 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
9666 #define GPIO_LCKR_LCK1_Pos (1U)
9667 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
9668 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
9669 #define GPIO_LCKR_LCK2_Pos (2U)
9670 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
9671 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
9672 #define GPIO_LCKR_LCK3_Pos (3U)
9673 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
9674 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
9675 #define GPIO_LCKR_LCK4_Pos (4U)
9676 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
9677 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
9678 #define GPIO_LCKR_LCK5_Pos (5U)
9679 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
9680 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
9681 #define GPIO_LCKR_LCK6_Pos (6U)
9682 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
9683 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
9684 #define GPIO_LCKR_LCK7_Pos (7U)
9685 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
9686 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
9687 #define GPIO_LCKR_LCK8_Pos (8U)
9688 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
9689 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
9690 #define GPIO_LCKR_LCK9_Pos (9U)
9691 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
9692 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
9693 #define GPIO_LCKR_LCK10_Pos (10U)
9694 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
9695 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
9696 #define GPIO_LCKR_LCK11_Pos (11U)
9697 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
9698 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
9699 #define GPIO_LCKR_LCK12_Pos (12U)
9700 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
9701 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
9702 #define GPIO_LCKR_LCK13_Pos (13U)
9703 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
9704 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
9705 #define GPIO_LCKR_LCK14_Pos (14U)
9706 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
9707 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
9708 #define GPIO_LCKR_LCK15_Pos (15U)
9709 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
9710 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
9711 #define GPIO_LCKR_LCKK_Pos (16U)
9712 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
9713 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
9714 /****************** Bit definition for GPIO_AFRL register *********************/
9715 #define GPIO_AFRL_AFSEL0_Pos (0U)
9716 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
9717 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
9718 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
9719 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
9720 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
9721 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
9722 #define GPIO_AFRL_AFSEL1_Pos (4U)
9723 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
9724 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
9725 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
9726 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
9727 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
9728 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
9729 #define GPIO_AFRL_AFSEL2_Pos (8U)
9730 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
9731 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
9732 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
9733 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
9734 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
9735 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
9736 #define GPIO_AFRL_AFSEL3_Pos (12U)
9737 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
9738 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
9739 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
9740 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
9741 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
9742 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
9743 #define GPIO_AFRL_AFSEL4_Pos (16U)
9744 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
9745 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
9746 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
9747 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
9748 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
9749 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
9750 #define GPIO_AFRL_AFSEL5_Pos (20U)
9751 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
9752 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
9753 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
9754 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
9755 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
9756 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
9757 #define GPIO_AFRL_AFSEL6_Pos (24U)
9758 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
9759 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
9760 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
9761 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
9762 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
9763 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
9764 #define GPIO_AFRL_AFSEL7_Pos (28U)
9765 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
9766 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
9767 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
9768 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
9769 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
9770 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
9771
9772 /* Legacy defines */
9773 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
9774 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
9775 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
9776 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
9777 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
9778 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
9779 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
9780 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
9781 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
9782 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
9783 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
9784 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
9785 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
9786 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
9787 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
9788 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
9789 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
9790 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
9791 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
9792 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
9793 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
9794 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
9795 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
9796 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
9797 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
9798 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
9799 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
9800 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
9801 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
9802 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
9803 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
9804 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
9805 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
9806 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
9807 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
9808 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9809 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
9810 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
9811 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
9812 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
9813
9814 /****************** Bit definition for GPIO_AFRH register *********************/
9815 #define GPIO_AFRH_AFSEL8_Pos (0U)
9816 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
9817 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9818 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
9819 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
9820 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
9821 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
9822 #define GPIO_AFRH_AFSEL9_Pos (4U)
9823 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
9824 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9825 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
9826 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
9827 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
9828 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
9829 #define GPIO_AFRH_AFSEL10_Pos (8U)
9830 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
9831 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9832 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
9833 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
9834 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
9835 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
9836 #define GPIO_AFRH_AFSEL11_Pos (12U)
9837 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
9838 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9839 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
9840 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
9841 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
9842 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
9843 #define GPIO_AFRH_AFSEL12_Pos (16U)
9844 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
9845 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9846 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
9847 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
9848 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
9849 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
9850 #define GPIO_AFRH_AFSEL13_Pos (20U)
9851 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
9852 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9853 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
9854 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
9855 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
9856 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
9857 #define GPIO_AFRH_AFSEL14_Pos (24U)
9858 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
9859 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9860 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
9861 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
9862 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
9863 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
9864 #define GPIO_AFRH_AFSEL15_Pos (28U)
9865 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
9866 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9867 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
9868 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
9869 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
9870 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
9871
9872 /* Legacy defines */
9873 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9874 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
9875 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
9876 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
9877 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
9878 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9879 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
9880 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
9881 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
9882 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
9883 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9884 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
9885 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
9886 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
9887 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
9888 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9889 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
9890 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
9891 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
9892 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
9893 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9894 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
9895 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
9896 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
9897 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
9898 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9899 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
9900 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
9901 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
9902 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
9903 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9904 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
9905 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
9906 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
9907 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
9908 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9909 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
9910 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
9911 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
9912 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
9913
9914 /****************** Bits definition for GPIO_BRR register ******************/
9915 #define GPIO_BRR_BR0_Pos (0U)
9916 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
9917 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
9918 #define GPIO_BRR_BR1_Pos (1U)
9919 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
9920 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
9921 #define GPIO_BRR_BR2_Pos (2U)
9922 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
9923 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
9924 #define GPIO_BRR_BR3_Pos (3U)
9925 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
9926 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
9927 #define GPIO_BRR_BR4_Pos (4U)
9928 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
9929 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
9930 #define GPIO_BRR_BR5_Pos (5U)
9931 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
9932 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
9933 #define GPIO_BRR_BR6_Pos (6U)
9934 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
9935 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
9936 #define GPIO_BRR_BR7_Pos (7U)
9937 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
9938 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
9939 #define GPIO_BRR_BR8_Pos (8U)
9940 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
9941 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
9942 #define GPIO_BRR_BR9_Pos (9U)
9943 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
9944 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
9945 #define GPIO_BRR_BR10_Pos (10U)
9946 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
9947 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
9948 #define GPIO_BRR_BR11_Pos (11U)
9949 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
9950 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
9951 #define GPIO_BRR_BR12_Pos (12U)
9952 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
9953 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
9954 #define GPIO_BRR_BR13_Pos (13U)
9955 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
9956 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
9957 #define GPIO_BRR_BR14_Pos (14U)
9958 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
9959 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
9960 #define GPIO_BRR_BR15_Pos (15U)
9961 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
9962 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
9963
9964
9965 /******************************************************************************/
9966 /* */
9967 /* HASH */
9968 /* */
9969 /******************************************************************************/
9970 /****************** Bits definition for HASH_CR register ********************/
9971 #define HASH_CR_INIT_Pos (2U)
9972 #define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
9973 #define HASH_CR_INIT HASH_CR_INIT_Msk
9974 #define HASH_CR_DMAE_Pos (3U)
9975 #define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
9976 #define HASH_CR_DMAE HASH_CR_DMAE_Msk
9977 #define HASH_CR_DATATYPE_Pos (4U)
9978 #define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
9979 #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
9980 #define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
9981 #define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
9982 #define HASH_CR_MODE_Pos (6U)
9983 #define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
9984 #define HASH_CR_MODE HASH_CR_MODE_Msk
9985 #define HASH_CR_ALGO_Pos (7U)
9986 #define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
9987 #define HASH_CR_ALGO HASH_CR_ALGO_Msk
9988 #define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
9989 #define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
9990 #define HASH_CR_NBW_Pos (8U)
9991 #define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
9992 #define HASH_CR_NBW HASH_CR_NBW_Msk
9993 #define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
9994 #define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
9995 #define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
9996 #define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
9997 #define HASH_CR_DINNE_Pos (12U)
9998 #define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
9999 #define HASH_CR_DINNE HASH_CR_DINNE_Msk
10000 #define HASH_CR_MDMAT_Pos (13U)
10001 #define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
10002 #define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
10003 #define HASH_CR_LKEY_Pos (16U)
10004 #define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
10005 #define HASH_CR_LKEY HASH_CR_LKEY_Msk
10006
10007 /****************** Bits definition for HASH_STR register *******************/
10008 #define HASH_STR_NBLW_Pos (0U)
10009 #define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
10010 #define HASH_STR_NBLW HASH_STR_NBLW_Msk
10011 #define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
10012 #define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
10013 #define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
10014 #define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
10015 #define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
10016 #define HASH_STR_DCAL_Pos (8U)
10017 #define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
10018 #define HASH_STR_DCAL HASH_STR_DCAL_Msk
10019 /* Aliases for HASH_STR register */
10020 #define HASH_STR_NBW HASH_STR_NBLW
10021 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
10022 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
10023 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
10024 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
10025 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
10026
10027 /****************** Bits definition for HASH_IMR register *******************/
10028 #define HASH_IMR_DINIE_Pos (0U)
10029 #define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
10030 #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
10031 #define HASH_IMR_DCIE_Pos (1U)
10032 #define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
10033 #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
10034 /* Aliases for HASH_IMR register */
10035 #define HASH_IMR_DINIM HASH_IMR_DINIE
10036 #define HASH_IMR_DCIM HASH_IMR_DCIE
10037
10038 /****************** Bits definition for HASH_SR register ********************/
10039 #define HASH_SR_DINIS_Pos (0U)
10040 #define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
10041 #define HASH_SR_DINIS HASH_SR_DINIS_Msk
10042 #define HASH_SR_DCIS_Pos (1U)
10043 #define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
10044 #define HASH_SR_DCIS HASH_SR_DCIS_Msk
10045 #define HASH_SR_DMAS_Pos (2U)
10046 #define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
10047 #define HASH_SR_DMAS HASH_SR_DMAS_Msk
10048 #define HASH_SR_BUSY_Pos (3U)
10049 #define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
10050 #define HASH_SR_BUSY HASH_SR_BUSY_Msk
10051
10052 /******************************************************************************/
10053 /* */
10054 /* Inter-integrated Circuit Interface */
10055 /* */
10056 /******************************************************************************/
10057 /******************* Bit definition for I2C_CR1 register ********************/
10058 #define I2C_CR1_PE_Pos (0U)
10059 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
10060 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
10061 #define I2C_CR1_SMBUS_Pos (1U)
10062 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
10063 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
10064 #define I2C_CR1_SMBTYPE_Pos (3U)
10065 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
10066 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
10067 #define I2C_CR1_ENARP_Pos (4U)
10068 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
10069 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
10070 #define I2C_CR1_ENPEC_Pos (5U)
10071 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
10072 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
10073 #define I2C_CR1_ENGC_Pos (6U)
10074 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
10075 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
10076 #define I2C_CR1_NOSTRETCH_Pos (7U)
10077 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
10078 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
10079 #define I2C_CR1_START_Pos (8U)
10080 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
10081 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
10082 #define I2C_CR1_STOP_Pos (9U)
10083 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
10084 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
10085 #define I2C_CR1_ACK_Pos (10U)
10086 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
10087 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
10088 #define I2C_CR1_POS_Pos (11U)
10089 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
10090 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
10091 #define I2C_CR1_PEC_Pos (12U)
10092 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
10093 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
10094 #define I2C_CR1_ALERT_Pos (13U)
10095 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
10096 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
10097 #define I2C_CR1_SWRST_Pos (15U)
10098 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
10099 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
10100
10101 /******************* Bit definition for I2C_CR2 register ********************/
10102 #define I2C_CR2_FREQ_Pos (0U)
10103 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
10104 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
10105 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
10106 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
10107 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
10108 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
10109 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
10110 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
10111
10112 #define I2C_CR2_ITERREN_Pos (8U)
10113 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
10114 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
10115 #define I2C_CR2_ITEVTEN_Pos (9U)
10116 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
10117 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
10118 #define I2C_CR2_ITBUFEN_Pos (10U)
10119 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
10120 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
10121 #define I2C_CR2_DMAEN_Pos (11U)
10122 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
10123 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
10124 #define I2C_CR2_LAST_Pos (12U)
10125 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
10126 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
10127
10128 /******************* Bit definition for I2C_OAR1 register *******************/
10129 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
10130 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
10131
10132 #define I2C_OAR1_ADD0_Pos (0U)
10133 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
10134 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
10135 #define I2C_OAR1_ADD1_Pos (1U)
10136 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
10137 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
10138 #define I2C_OAR1_ADD2_Pos (2U)
10139 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
10140 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
10141 #define I2C_OAR1_ADD3_Pos (3U)
10142 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
10143 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
10144 #define I2C_OAR1_ADD4_Pos (4U)
10145 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
10146 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
10147 #define I2C_OAR1_ADD5_Pos (5U)
10148 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
10149 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
10150 #define I2C_OAR1_ADD6_Pos (6U)
10151 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
10152 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
10153 #define I2C_OAR1_ADD7_Pos (7U)
10154 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
10155 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
10156 #define I2C_OAR1_ADD8_Pos (8U)
10157 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
10158 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
10159 #define I2C_OAR1_ADD9_Pos (9U)
10160 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
10161 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
10162
10163 #define I2C_OAR1_ADDMODE_Pos (15U)
10164 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
10165 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
10166
10167 /******************* Bit definition for I2C_OAR2 register *******************/
10168 #define I2C_OAR2_ENDUAL_Pos (0U)
10169 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
10170 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
10171 #define I2C_OAR2_ADD2_Pos (1U)
10172 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
10173 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
10174
10175 /******************** Bit definition for I2C_DR register ********************/
10176 #define I2C_DR_DR_Pos (0U)
10177 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
10178 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
10179
10180 /******************* Bit definition for I2C_SR1 register ********************/
10181 #define I2C_SR1_SB_Pos (0U)
10182 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
10183 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
10184 #define I2C_SR1_ADDR_Pos (1U)
10185 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
10186 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
10187 #define I2C_SR1_BTF_Pos (2U)
10188 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
10189 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
10190 #define I2C_SR1_ADD10_Pos (3U)
10191 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
10192 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
10193 #define I2C_SR1_STOPF_Pos (4U)
10194 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
10195 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
10196 #define I2C_SR1_RXNE_Pos (6U)
10197 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
10198 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
10199 #define I2C_SR1_TXE_Pos (7U)
10200 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
10201 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
10202 #define I2C_SR1_BERR_Pos (8U)
10203 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
10204 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
10205 #define I2C_SR1_ARLO_Pos (9U)
10206 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
10207 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
10208 #define I2C_SR1_AF_Pos (10U)
10209 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
10210 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
10211 #define I2C_SR1_OVR_Pos (11U)
10212 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
10213 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
10214 #define I2C_SR1_PECERR_Pos (12U)
10215 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
10216 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
10217 #define I2C_SR1_TIMEOUT_Pos (14U)
10218 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
10219 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
10220 #define I2C_SR1_SMBALERT_Pos (15U)
10221 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
10222 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
10223
10224 /******************* Bit definition for I2C_SR2 register ********************/
10225 #define I2C_SR2_MSL_Pos (0U)
10226 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
10227 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
10228 #define I2C_SR2_BUSY_Pos (1U)
10229 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
10230 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
10231 #define I2C_SR2_TRA_Pos (2U)
10232 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
10233 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
10234 #define I2C_SR2_GENCALL_Pos (4U)
10235 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
10236 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
10237 #define I2C_SR2_SMBDEFAULT_Pos (5U)
10238 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
10239 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
10240 #define I2C_SR2_SMBHOST_Pos (6U)
10241 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
10242 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
10243 #define I2C_SR2_DUALF_Pos (7U)
10244 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
10245 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
10246 #define I2C_SR2_PEC_Pos (8U)
10247 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
10248 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
10249
10250 /******************* Bit definition for I2C_CCR register ********************/
10251 #define I2C_CCR_CCR_Pos (0U)
10252 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
10253 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
10254 #define I2C_CCR_DUTY_Pos (14U)
10255 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
10256 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
10257 #define I2C_CCR_FS_Pos (15U)
10258 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
10259 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
10260
10261 /****************** Bit definition for I2C_TRISE register *******************/
10262 #define I2C_TRISE_TRISE_Pos (0U)
10263 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
10264 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
10265
10266 /****************** Bit definition for I2C_FLTR register *******************/
10267 #define I2C_FLTR_DNF_Pos (0U)
10268 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
10269 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
10270 #define I2C_FLTR_ANOFF_Pos (4U)
10271 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
10272 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
10273
10274 /******************************************************************************/
10275 /* */
10276 /* Independent WATCHDOG */
10277 /* */
10278 /******************************************************************************/
10279 /******************* Bit definition for IWDG_KR register ********************/
10280 #define IWDG_KR_KEY_Pos (0U)
10281 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
10282 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
10283
10284 /******************* Bit definition for IWDG_PR register ********************/
10285 #define IWDG_PR_PR_Pos (0U)
10286 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
10287 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
10288 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
10289 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
10290 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
10291
10292 /******************* Bit definition for IWDG_RLR register *******************/
10293 #define IWDG_RLR_RL_Pos (0U)
10294 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
10295 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
10296
10297 /******************* Bit definition for IWDG_SR register ********************/
10298 #define IWDG_SR_PVU_Pos (0U)
10299 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
10300 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
10301 #define IWDG_SR_RVU_Pos (1U)
10302 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
10303 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
10304
10305
10306
10307 /******************************************************************************/
10308 /* */
10309 /* Power Control */
10310 /* */
10311 /******************************************************************************/
10312 /******************** Bit definition for PWR_CR register ********************/
10313 #define PWR_CR_LPDS_Pos (0U)
10314 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
10315 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
10316 #define PWR_CR_PDDS_Pos (1U)
10317 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
10318 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
10319 #define PWR_CR_CWUF_Pos (2U)
10320 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
10321 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
10322 #define PWR_CR_CSBF_Pos (3U)
10323 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
10324 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
10325 #define PWR_CR_PVDE_Pos (4U)
10326 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
10327 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
10328
10329 #define PWR_CR_PLS_Pos (5U)
10330 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
10331 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
10332 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
10333 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
10334 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
10335
10336 /*!< PVD level configuration */
10337 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
10338 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
10339 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
10340 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
10341 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
10342 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
10343 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
10344 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
10345 #define PWR_CR_DBP_Pos (8U)
10346 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
10347 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
10348 #define PWR_CR_FPDS_Pos (9U)
10349 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
10350 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
10351 #define PWR_CR_LPLVDS_Pos (10U)
10352 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
10353 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
10354 #define PWR_CR_MRLVDS_Pos (11U)
10355 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
10356 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
10357 #define PWR_CR_ADCDC1_Pos (13U)
10358 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
10359 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
10360 #define PWR_CR_VOS_Pos (14U)
10361 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
10362 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10363 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
10364 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
10365 #define PWR_CR_ODEN_Pos (16U)
10366 #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
10367 #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
10368 #define PWR_CR_ODSWEN_Pos (17U)
10369 #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
10370 #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
10371 #define PWR_CR_UDEN_Pos (18U)
10372 #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
10373 #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
10374 #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
10375 #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
10376
10377 /* Legacy define */
10378 #define PWR_CR_PMODE PWR_CR_VOS
10379 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
10380 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
10381
10382 /******************* Bit definition for PWR_CSR register ********************/
10383 #define PWR_CSR_WUF_Pos (0U)
10384 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
10385 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
10386 #define PWR_CSR_SBF_Pos (1U)
10387 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
10388 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
10389 #define PWR_CSR_PVDO_Pos (2U)
10390 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
10391 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
10392 #define PWR_CSR_BRR_Pos (3U)
10393 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
10394 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
10395 #define PWR_CSR_EWUP_Pos (8U)
10396 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
10397 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
10398 #define PWR_CSR_BRE_Pos (9U)
10399 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
10400 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
10401 #define PWR_CSR_VOSRDY_Pos (14U)
10402 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
10403 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
10404 #define PWR_CSR_ODRDY_Pos (16U)
10405 #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
10406 #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
10407 #define PWR_CSR_ODSWRDY_Pos (17U)
10408 #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
10409 #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
10410 #define PWR_CSR_UDRDY_Pos (18U)
10411 #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
10412 #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
10413 /* Legacy define */
10414 #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
10415
10416 /* Legacy define */
10417 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
10418
10419 /******************************************************************************/
10420 /* */
10421 /* Reset and Clock Control */
10422 /* */
10423 /******************************************************************************/
10424 /******************** Bit definition for RCC_CR register ********************/
10425 #define RCC_CR_HSION_Pos (0U)
10426 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
10427 #define RCC_CR_HSION RCC_CR_HSION_Msk
10428 #define RCC_CR_HSIRDY_Pos (1U)
10429 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
10430 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10431
10432 #define RCC_CR_HSITRIM_Pos (3U)
10433 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
10434 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10435 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
10436 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
10437 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
10438 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
10439 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
10440
10441 #define RCC_CR_HSICAL_Pos (8U)
10442 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
10443 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10444 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
10445 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
10446 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
10447 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
10448 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
10449 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
10450 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
10451 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
10452
10453 #define RCC_CR_HSEON_Pos (16U)
10454 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
10455 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
10456 #define RCC_CR_HSERDY_Pos (17U)
10457 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
10458 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10459 #define RCC_CR_HSEBYP_Pos (18U)
10460 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
10461 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10462 #define RCC_CR_CSSON_Pos (19U)
10463 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
10464 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
10465 #define RCC_CR_PLLON_Pos (24U)
10466 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
10467 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
10468 #define RCC_CR_PLLRDY_Pos (25U)
10469 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
10470 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10471 /*
10472 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10473 */
10474 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
10475
10476 #define RCC_CR_PLLI2SON_Pos (26U)
10477 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
10478 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
10479 #define RCC_CR_PLLI2SRDY_Pos (27U)
10480 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
10481 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
10482 /*
10483 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10484 */
10485 #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
10486
10487 #define RCC_CR_PLLSAION_Pos (28U)
10488 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
10489 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
10490 #define RCC_CR_PLLSAIRDY_Pos (29U)
10491 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
10492 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
10493
10494 /******************** Bit definition for RCC_PLLCFGR register ***************/
10495 #define RCC_PLLCFGR_PLLM_Pos (0U)
10496 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
10497 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10498 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
10499 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
10500 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
10501 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
10502 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
10503 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
10504
10505 #define RCC_PLLCFGR_PLLN_Pos (6U)
10506 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
10507 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10508 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
10509 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
10510 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
10511 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
10512 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
10513 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
10514 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
10515 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
10516 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
10517
10518 #define RCC_PLLCFGR_PLLP_Pos (16U)
10519 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
10520 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10521 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
10522 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
10523
10524 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
10525 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
10526 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10527 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
10528 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
10529 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10530 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
10531
10532 #define RCC_PLLCFGR_PLLQ_Pos (24U)
10533 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
10534 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10535 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
10536 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
10537 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
10538 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
10539
10540
10541 /******************** Bit definition for RCC_CFGR register ******************/
10542 /*!< SW configuration */
10543 #define RCC_CFGR_SW_Pos (0U)
10544 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
10545 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
10546 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
10547 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
10548
10549 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
10550 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
10551 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
10552
10553 /*!< SWS configuration */
10554 #define RCC_CFGR_SWS_Pos (2U)
10555 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
10556 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
10557 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
10558 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
10559
10560 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
10561 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
10562 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
10563
10564 /*!< HPRE configuration */
10565 #define RCC_CFGR_HPRE_Pos (4U)
10566 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
10567 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
10568 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
10569 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
10570 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
10571 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
10572
10573 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
10574 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
10575 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
10576 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
10577 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
10578 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
10579 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
10580 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
10581 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
10582
10583 /*!< PPRE1 configuration */
10584 #define RCC_CFGR_PPRE1_Pos (10U)
10585 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
10586 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
10587 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
10588 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
10589 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
10590
10591 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
10592 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
10593 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
10594 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
10595 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
10596
10597 /*!< PPRE2 configuration */
10598 #define RCC_CFGR_PPRE2_Pos (13U)
10599 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
10600 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
10601 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
10602 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
10603 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
10604
10605 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
10606 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
10607 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
10608 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
10609 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
10610
10611 /*!< RTCPRE configuration */
10612 #define RCC_CFGR_RTCPRE_Pos (16U)
10613 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
10614 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
10615 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
10616 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
10617 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
10618 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
10619 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
10620
10621 /*!< MCO1 configuration */
10622 #define RCC_CFGR_MCO1_Pos (21U)
10623 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
10624 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
10625 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
10626 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
10627
10628 #define RCC_CFGR_I2SSRC_Pos (23U)
10629 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
10630 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
10631
10632 #define RCC_CFGR_MCO1PRE_Pos (24U)
10633 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
10634 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
10635 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
10636 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
10637 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
10638
10639 #define RCC_CFGR_MCO2PRE_Pos (27U)
10640 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
10641 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
10642 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
10643 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
10644 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
10645
10646 #define RCC_CFGR_MCO2_Pos (30U)
10647 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
10648 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
10649 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
10650 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
10651
10652 /******************** Bit definition for RCC_CIR register *******************/
10653 #define RCC_CIR_LSIRDYF_Pos (0U)
10654 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
10655 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
10656 #define RCC_CIR_LSERDYF_Pos (1U)
10657 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
10658 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
10659 #define RCC_CIR_HSIRDYF_Pos (2U)
10660 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
10661 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
10662 #define RCC_CIR_HSERDYF_Pos (3U)
10663 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
10664 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
10665 #define RCC_CIR_PLLRDYF_Pos (4U)
10666 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
10667 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
10668 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
10669 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
10670 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
10671
10672 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
10673 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
10674 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
10675 #define RCC_CIR_CSSF_Pos (7U)
10676 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
10677 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
10678 #define RCC_CIR_LSIRDYIE_Pos (8U)
10679 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
10680 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
10681 #define RCC_CIR_LSERDYIE_Pos (9U)
10682 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
10683 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
10684 #define RCC_CIR_HSIRDYIE_Pos (10U)
10685 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
10686 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
10687 #define RCC_CIR_HSERDYIE_Pos (11U)
10688 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
10689 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
10690 #define RCC_CIR_PLLRDYIE_Pos (12U)
10691 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
10692 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
10693 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
10694 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
10695 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
10696
10697 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
10698 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
10699 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
10700 #define RCC_CIR_LSIRDYC_Pos (16U)
10701 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
10702 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
10703 #define RCC_CIR_LSERDYC_Pos (17U)
10704 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
10705 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
10706 #define RCC_CIR_HSIRDYC_Pos (18U)
10707 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
10708 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
10709 #define RCC_CIR_HSERDYC_Pos (19U)
10710 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
10711 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
10712 #define RCC_CIR_PLLRDYC_Pos (20U)
10713 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
10714 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
10715 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
10716 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
10717 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
10718 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
10719 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
10720 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
10721
10722 #define RCC_CIR_CSSC_Pos (23U)
10723 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
10724 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
10725
10726 /******************** Bit definition for RCC_AHB1RSTR register **************/
10727 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
10728 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
10729 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
10730 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
10731 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
10732 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
10733 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
10734 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
10735 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
10736 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
10737 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
10738 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
10739 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
10740 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
10741 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
10742 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
10743 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
10744 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
10745 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
10746 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
10747 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
10748 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
10749 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
10750 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
10751 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
10752 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
10753 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
10754 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
10755 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
10756 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
10757 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
10758 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
10759 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
10760 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
10761 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
10762 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10763 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
10764 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
10765 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10766 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
10767 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
10768 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10769 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
10770 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
10771 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
10772 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
10773 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
10774 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
10775 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
10776 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
10777 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
10778
10779 /******************** Bit definition for RCC_AHB2RSTR register **************/
10780 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
10781 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
10782 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
10783 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
10784 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
10785 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
10786 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
10787 #define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
10788 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
10789 /* maintained for legacy purpose */
10790 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
10791 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
10792 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
10793 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
10794 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
10795 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
10796 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
10797 /******************** Bit definition for RCC_AHB3RSTR register **************/
10798 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
10799 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
10800 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
10801
10802
10803 /******************** Bit definition for RCC_APB1RSTR register **************/
10804 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
10805 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
10806 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
10807 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
10808 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
10809 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
10810 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
10811 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
10812 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
10813 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
10814 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
10815 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
10816 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
10817 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
10818 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
10819 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
10820 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
10821 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
10822 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
10823 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
10824 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
10825 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
10826 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
10827 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
10828 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
10829 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
10830 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
10831 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
10832 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
10833 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
10834 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
10835 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
10836 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
10837 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
10838 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
10839 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
10840 #define RCC_APB1RSTR_USART2RST_Pos (17U)
10841 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
10842 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
10843 #define RCC_APB1RSTR_USART3RST_Pos (18U)
10844 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
10845 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
10846 #define RCC_APB1RSTR_UART4RST_Pos (19U)
10847 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
10848 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
10849 #define RCC_APB1RSTR_UART5RST_Pos (20U)
10850 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
10851 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
10852 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
10853 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
10854 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
10855 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
10856 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
10857 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
10858 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
10859 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
10860 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
10861 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
10862 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
10863 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
10864 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
10865 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
10866 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
10867 #define RCC_APB1RSTR_PWRRST_Pos (28U)
10868 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
10869 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
10870 #define RCC_APB1RSTR_DACRST_Pos (29U)
10871 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
10872 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
10873 #define RCC_APB1RSTR_UART7RST_Pos (30U)
10874 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
10875 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
10876 #define RCC_APB1RSTR_UART8RST_Pos (31U)
10877 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
10878 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
10879
10880 /******************** Bit definition for RCC_APB2RSTR register **************/
10881 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
10882 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
10883 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10884 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
10885 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
10886 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
10887 #define RCC_APB2RSTR_USART1RST_Pos (4U)
10888 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
10889 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10890 #define RCC_APB2RSTR_USART6RST_Pos (5U)
10891 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
10892 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
10893 #define RCC_APB2RSTR_ADCRST_Pos (8U)
10894 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
10895 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
10896 #define RCC_APB2RSTR_SDIORST_Pos (11U)
10897 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
10898 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
10899 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
10900 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
10901 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10902 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
10903 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
10904 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
10905 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
10906 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
10907 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10908 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
10909 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
10910 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
10911 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
10912 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
10913 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
10914 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
10915 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
10916 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
10917 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
10918 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
10919 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
10920 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
10921 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
10922 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
10923 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
10924 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
10925 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
10926
10927 /* Old SPI1RST bit definition, maintained for legacy purpose */
10928 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
10929
10930 /******************** Bit definition for RCC_AHB1ENR register ***************/
10931 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
10932 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
10933 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
10934 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
10935 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
10936 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
10937 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
10938 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
10939 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
10940 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
10941 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
10942 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
10943 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
10944 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
10945 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
10946 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
10947 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
10948 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
10949 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
10950 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
10951 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
10952 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
10953 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
10954 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
10955 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
10956 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
10957 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
10958 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
10959 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
10960 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
10961 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
10962 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
10963 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
10964 #define RCC_AHB1ENR_CRCEN_Pos (12U)
10965 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
10966 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
10967 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
10968 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
10969 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
10970 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
10971 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
10972 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
10973 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
10974 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
10975 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
10976 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
10977 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
10978 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
10979 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
10980 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
10981 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
10982 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
10983 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
10984 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
10985 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
10986 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
10987 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
10988 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
10989 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
10990 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
10991 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
10992 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
10993 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
10994 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
10995 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
10996 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
10997 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
10998 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
10999 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
11000 /******************** Bit definition for RCC_AHB2ENR register ***************/
11001 /*
11002 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11003 */
11004 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
11005
11006 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
11007 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
11008 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
11009 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
11010 #define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
11011 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
11012 #define RCC_AHB2ENR_HASHEN_Pos (5U)
11013 #define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
11014 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
11015 #define RCC_AHB2ENR_RNGEN_Pos (6U)
11016 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
11017 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11018 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
11019 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
11020 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11021
11022 /******************** Bit definition for RCC_AHB3ENR register ***************/
11023 /*
11024 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11025 */
11026 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
11027
11028 #define RCC_AHB3ENR_FMCEN_Pos (0U)
11029 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
11030 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11031
11032 /******************** Bit definition for RCC_APB1ENR register ***************/
11033 #define RCC_APB1ENR_TIM2EN_Pos (0U)
11034 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
11035 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
11036 #define RCC_APB1ENR_TIM3EN_Pos (1U)
11037 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
11038 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
11039 #define RCC_APB1ENR_TIM4EN_Pos (2U)
11040 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
11041 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
11042 #define RCC_APB1ENR_TIM5EN_Pos (3U)
11043 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
11044 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
11045 #define RCC_APB1ENR_TIM6EN_Pos (4U)
11046 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
11047 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
11048 #define RCC_APB1ENR_TIM7EN_Pos (5U)
11049 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
11050 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
11051 #define RCC_APB1ENR_TIM12EN_Pos (6U)
11052 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
11053 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
11054 #define RCC_APB1ENR_TIM13EN_Pos (7U)
11055 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
11056 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
11057 #define RCC_APB1ENR_TIM14EN_Pos (8U)
11058 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
11059 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
11060 #define RCC_APB1ENR_WWDGEN_Pos (11U)
11061 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
11062 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
11063 #define RCC_APB1ENR_SPI2EN_Pos (14U)
11064 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
11065 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
11066 #define RCC_APB1ENR_SPI3EN_Pos (15U)
11067 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
11068 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
11069 #define RCC_APB1ENR_USART2EN_Pos (17U)
11070 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
11071 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
11072 #define RCC_APB1ENR_USART3EN_Pos (18U)
11073 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
11074 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
11075 #define RCC_APB1ENR_UART4EN_Pos (19U)
11076 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
11077 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
11078 #define RCC_APB1ENR_UART5EN_Pos (20U)
11079 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
11080 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
11081 #define RCC_APB1ENR_I2C1EN_Pos (21U)
11082 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
11083 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
11084 #define RCC_APB1ENR_I2C2EN_Pos (22U)
11085 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
11086 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
11087 #define RCC_APB1ENR_I2C3EN_Pos (23U)
11088 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
11089 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
11090 #define RCC_APB1ENR_CAN1EN_Pos (25U)
11091 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
11092 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
11093 #define RCC_APB1ENR_CAN2EN_Pos (26U)
11094 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
11095 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
11096 #define RCC_APB1ENR_PWREN_Pos (28U)
11097 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
11098 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
11099 #define RCC_APB1ENR_DACEN_Pos (29U)
11100 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
11101 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
11102 #define RCC_APB1ENR_UART7EN_Pos (30U)
11103 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
11104 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
11105 #define RCC_APB1ENR_UART8EN_Pos (31U)
11106 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
11107 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
11108
11109 /******************** Bit definition for RCC_APB2ENR register ***************/
11110 #define RCC_APB2ENR_TIM1EN_Pos (0U)
11111 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
11112 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11113 #define RCC_APB2ENR_TIM8EN_Pos (1U)
11114 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
11115 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11116 #define RCC_APB2ENR_USART1EN_Pos (4U)
11117 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
11118 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11119 #define RCC_APB2ENR_USART6EN_Pos (5U)
11120 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
11121 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
11122 #define RCC_APB2ENR_ADC1EN_Pos (8U)
11123 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
11124 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
11125 #define RCC_APB2ENR_ADC2EN_Pos (9U)
11126 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
11127 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
11128 #define RCC_APB2ENR_ADC3EN_Pos (10U)
11129 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
11130 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
11131 #define RCC_APB2ENR_SDIOEN_Pos (11U)
11132 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
11133 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
11134 #define RCC_APB2ENR_SPI1EN_Pos (12U)
11135 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
11136 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11137 #define RCC_APB2ENR_SPI4EN_Pos (13U)
11138 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
11139 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
11140 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
11141 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
11142 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11143 #define RCC_APB2ENR_TIM9EN_Pos (16U)
11144 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
11145 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
11146 #define RCC_APB2ENR_TIM10EN_Pos (17U)
11147 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
11148 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
11149 #define RCC_APB2ENR_TIM11EN_Pos (18U)
11150 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
11151 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
11152 #define RCC_APB2ENR_SPI5EN_Pos (20U)
11153 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
11154 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
11155 #define RCC_APB2ENR_SPI6EN_Pos (21U)
11156 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
11157 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
11158 #define RCC_APB2ENR_SAI1EN_Pos (22U)
11159 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
11160 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11161
11162 /******************** Bit definition for RCC_AHB1LPENR register *************/
11163 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
11164 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
11165 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
11166 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
11167 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
11168 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
11169 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
11170 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
11171 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
11172 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
11173 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
11174 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
11175 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
11176 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
11177 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
11178 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
11179 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
11180 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
11181 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
11182 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
11183 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
11184 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
11185 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
11186 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
11187 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
11188 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
11189 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
11190 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
11191 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
11192 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
11193 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
11194 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
11195 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
11196 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
11197 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
11198 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
11199 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
11200 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
11201 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
11202 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
11203 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
11204 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
11205 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
11206 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
11207 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
11208 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
11209 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
11210 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
11211 #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
11212 #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
11213 #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
11214 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
11215 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
11216 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
11217 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
11218 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
11219 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
11220 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
11221 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
11222 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
11223
11224 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
11225 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
11226 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
11227 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
11228 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
11229 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
11230 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
11231 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
11232 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
11233 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
11234 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
11235 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
11236 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
11237 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
11238 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
11239 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
11240 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
11241 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
11242
11243 /******************** Bit definition for RCC_AHB2LPENR register *************/
11244 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
11245 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
11246 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
11247 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
11248 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
11249 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
11250 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
11251 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
11252 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
11253 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
11254 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
11255 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
11256 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
11257 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
11258 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
11259
11260 /******************** Bit definition for RCC_AHB3LPENR register *************/
11261 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
11262 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
11263 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
11264
11265 /******************** Bit definition for RCC_APB1LPENR register *************/
11266 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
11267 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
11268 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
11269 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
11270 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
11271 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
11272 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
11273 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
11274 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
11275 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
11276 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
11277 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
11278 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
11279 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
11280 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
11281 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
11282 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
11283 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
11284 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
11285 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
11286 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
11287 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
11288 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
11289 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
11290 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
11291 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
11292 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
11293 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
11294 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
11295 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
11296 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
11297 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
11298 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
11299 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
11300 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
11301 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
11302 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
11303 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
11304 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
11305 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
11306 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
11307 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
11308 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
11309 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
11310 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
11311 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
11312 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
11313 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
11314 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
11315 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
11316 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
11317 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
11318 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
11319 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
11320 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
11321 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
11322 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
11323 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
11324 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
11325 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
11326 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
11327 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
11328 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
11329 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
11330 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
11331 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
11332 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
11333 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
11334 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
11335 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
11336 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
11337 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
11338 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
11339 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
11340 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
11341
11342 /******************** Bit definition for RCC_APB2LPENR register *************/
11343 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
11344 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
11345 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
11346 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
11347 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
11348 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
11349 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
11350 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
11351 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
11352 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
11353 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
11354 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
11355 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
11356 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
11357 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
11358 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
11359 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
11360 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
11361 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
11362 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
11363 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
11364 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
11365 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
11366 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
11367 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
11368 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
11369 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
11370 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
11371 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
11372 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
11373 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
11374 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
11375 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
11376 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
11377 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
11378 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
11379 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
11380 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
11381 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
11382 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
11383 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
11384 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
11385 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
11386 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
11387 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
11388 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
11389 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
11390 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
11391 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
11392 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
11393 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
11394
11395 /******************** Bit definition for RCC_BDCR register ******************/
11396 #define RCC_BDCR_LSEON_Pos (0U)
11397 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
11398 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11399 #define RCC_BDCR_LSERDY_Pos (1U)
11400 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
11401 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11402 #define RCC_BDCR_LSEBYP_Pos (2U)
11403 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
11404 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11405
11406 #define RCC_BDCR_RTCSEL_Pos (8U)
11407 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
11408 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11409 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
11410 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
11411
11412 #define RCC_BDCR_RTCEN_Pos (15U)
11413 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
11414 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11415 #define RCC_BDCR_BDRST_Pos (16U)
11416 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
11417 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11418
11419 /******************** Bit definition for RCC_CSR register *******************/
11420 #define RCC_CSR_LSION_Pos (0U)
11421 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
11422 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
11423 #define RCC_CSR_LSIRDY_Pos (1U)
11424 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
11425 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11426 #define RCC_CSR_RMVF_Pos (24U)
11427 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
11428 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11429 #define RCC_CSR_BORRSTF_Pos (25U)
11430 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
11431 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11432 #define RCC_CSR_PINRSTF_Pos (26U)
11433 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
11434 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11435 #define RCC_CSR_PORRSTF_Pos (27U)
11436 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
11437 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
11438 #define RCC_CSR_SFTRSTF_Pos (28U)
11439 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
11440 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11441 #define RCC_CSR_IWDGRSTF_Pos (29U)
11442 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
11443 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11444 #define RCC_CSR_WWDGRSTF_Pos (30U)
11445 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
11446 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11447 #define RCC_CSR_LPWRRSTF_Pos (31U)
11448 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
11449 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11450 /* Legacy defines */
11451 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
11452 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
11453
11454 /******************** Bit definition for RCC_SSCGR register *****************/
11455 #define RCC_SSCGR_MODPER_Pos (0U)
11456 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
11457 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
11458 #define RCC_SSCGR_INCSTEP_Pos (13U)
11459 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
11460 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
11461 #define RCC_SSCGR_SPREADSEL_Pos (30U)
11462 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
11463 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
11464 #define RCC_SSCGR_SSCGEN_Pos (31U)
11465 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
11466 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
11467
11468 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
11469 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
11470 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
11471 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
11472 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
11473 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
11474 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
11475 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
11476 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
11477 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
11478 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
11479 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
11480 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
11481
11482 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
11483 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
11484 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
11485 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
11486 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
11487 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
11488 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
11489 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
11490 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
11491 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
11492 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
11493 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
11494 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
11495
11496 /******************** Bit definition for RCC_PLLSAICFGR register ************/
11497 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
11498 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
11499 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
11500 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
11501 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
11502 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
11503 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
11504 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
11505 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
11506 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
11507 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
11508 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
11509
11510
11511 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
11512 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
11513 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
11514 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
11515 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
11516 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
11517 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
11518
11519 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
11520 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
11521 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
11522 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
11523 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
11524 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
11525
11526 /******************** Bit definition for RCC_DCKCFGR register ***************/
11527 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
11528 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
11529 #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
11530 #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
11531 #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
11532 #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
11533 #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
11534 #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
11535
11536 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
11537 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
11538 #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
11539 #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
11540 #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
11541 #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
11542 #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
11543 #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
11544 #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
11545 #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11546 #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
11547 #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11548 #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
11549
11550 #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
11551 #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
11552 #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
11553 #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
11554 #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
11555 #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
11556 #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
11557 #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
11558 #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
11559 #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
11560 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
11561 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
11562 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
11563
11564
11565 /******************************************************************************/
11566 /* */
11567 /* RNG */
11568 /* */
11569 /******************************************************************************/
11570 /******************** Bits definition for RNG_CR register *******************/
11571 #define RNG_CR_RNGEN_Pos (2U)
11572 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
11573 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11574 #define RNG_CR_IE_Pos (3U)
11575 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
11576 #define RNG_CR_IE RNG_CR_IE_Msk
11577
11578 /******************** Bits definition for RNG_SR register *******************/
11579 #define RNG_SR_DRDY_Pos (0U)
11580 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
11581 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
11582 #define RNG_SR_CECS_Pos (1U)
11583 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
11584 #define RNG_SR_CECS RNG_SR_CECS_Msk
11585 #define RNG_SR_SECS_Pos (2U)
11586 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
11587 #define RNG_SR_SECS RNG_SR_SECS_Msk
11588 #define RNG_SR_CEIS_Pos (5U)
11589 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
11590 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
11591 #define RNG_SR_SEIS_Pos (6U)
11592 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
11593 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
11594
11595 /******************************************************************************/
11596 /* */
11597 /* Real-Time Clock (RTC) */
11598 /* */
11599 /******************************************************************************/
11600 /*
11601 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11602 */
11603 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
11604 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
11605 /******************** Bits definition for RTC_TR register *******************/
11606 #define RTC_TR_PM_Pos (22U)
11607 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
11608 #define RTC_TR_PM RTC_TR_PM_Msk
11609 #define RTC_TR_HT_Pos (20U)
11610 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
11611 #define RTC_TR_HT RTC_TR_HT_Msk
11612 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
11613 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
11614 #define RTC_TR_HU_Pos (16U)
11615 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
11616 #define RTC_TR_HU RTC_TR_HU_Msk
11617 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
11618 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
11619 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
11620 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
11621 #define RTC_TR_MNT_Pos (12U)
11622 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
11623 #define RTC_TR_MNT RTC_TR_MNT_Msk
11624 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
11625 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
11626 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
11627 #define RTC_TR_MNU_Pos (8U)
11628 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
11629 #define RTC_TR_MNU RTC_TR_MNU_Msk
11630 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
11631 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
11632 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
11633 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
11634 #define RTC_TR_ST_Pos (4U)
11635 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
11636 #define RTC_TR_ST RTC_TR_ST_Msk
11637 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
11638 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
11639 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
11640 #define RTC_TR_SU_Pos (0U)
11641 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
11642 #define RTC_TR_SU RTC_TR_SU_Msk
11643 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
11644 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
11645 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
11646 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
11647
11648 /******************** Bits definition for RTC_DR register *******************/
11649 #define RTC_DR_YT_Pos (20U)
11650 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
11651 #define RTC_DR_YT RTC_DR_YT_Msk
11652 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
11653 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
11654 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
11655 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
11656 #define RTC_DR_YU_Pos (16U)
11657 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
11658 #define RTC_DR_YU RTC_DR_YU_Msk
11659 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
11660 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
11661 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
11662 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
11663 #define RTC_DR_WDU_Pos (13U)
11664 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
11665 #define RTC_DR_WDU RTC_DR_WDU_Msk
11666 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
11667 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
11668 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
11669 #define RTC_DR_MT_Pos (12U)
11670 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
11671 #define RTC_DR_MT RTC_DR_MT_Msk
11672 #define RTC_DR_MU_Pos (8U)
11673 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
11674 #define RTC_DR_MU RTC_DR_MU_Msk
11675 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
11676 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
11677 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
11678 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
11679 #define RTC_DR_DT_Pos (4U)
11680 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
11681 #define RTC_DR_DT RTC_DR_DT_Msk
11682 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
11683 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
11684 #define RTC_DR_DU_Pos (0U)
11685 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
11686 #define RTC_DR_DU RTC_DR_DU_Msk
11687 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
11688 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
11689 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
11690 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
11691
11692 /******************** Bits definition for RTC_CR register *******************/
11693 #define RTC_CR_COE_Pos (23U)
11694 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
11695 #define RTC_CR_COE RTC_CR_COE_Msk
11696 #define RTC_CR_OSEL_Pos (21U)
11697 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
11698 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
11699 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
11700 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
11701 #define RTC_CR_POL_Pos (20U)
11702 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
11703 #define RTC_CR_POL RTC_CR_POL_Msk
11704 #define RTC_CR_COSEL_Pos (19U)
11705 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
11706 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
11707 #define RTC_CR_BKP_Pos (18U)
11708 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
11709 #define RTC_CR_BKP RTC_CR_BKP_Msk
11710 #define RTC_CR_SUB1H_Pos (17U)
11711 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
11712 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11713 #define RTC_CR_ADD1H_Pos (16U)
11714 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
11715 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11716 #define RTC_CR_TSIE_Pos (15U)
11717 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
11718 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
11719 #define RTC_CR_WUTIE_Pos (14U)
11720 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
11721 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11722 #define RTC_CR_ALRBIE_Pos (13U)
11723 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
11724 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11725 #define RTC_CR_ALRAIE_Pos (12U)
11726 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
11727 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11728 #define RTC_CR_TSE_Pos (11U)
11729 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
11730 #define RTC_CR_TSE RTC_CR_TSE_Msk
11731 #define RTC_CR_WUTE_Pos (10U)
11732 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
11733 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
11734 #define RTC_CR_ALRBE_Pos (9U)
11735 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
11736 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11737 #define RTC_CR_ALRAE_Pos (8U)
11738 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
11739 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11740 #define RTC_CR_DCE_Pos (7U)
11741 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
11742 #define RTC_CR_DCE RTC_CR_DCE_Msk
11743 #define RTC_CR_FMT_Pos (6U)
11744 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
11745 #define RTC_CR_FMT RTC_CR_FMT_Msk
11746 #define RTC_CR_BYPSHAD_Pos (5U)
11747 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
11748 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11749 #define RTC_CR_REFCKON_Pos (4U)
11750 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
11751 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11752 #define RTC_CR_TSEDGE_Pos (3U)
11753 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
11754 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11755 #define RTC_CR_WUCKSEL_Pos (0U)
11756 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
11757 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11758 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
11759 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
11760 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
11761
11762 /* Legacy defines */
11763 #define RTC_CR_BCK RTC_CR_BKP
11764
11765 /******************** Bits definition for RTC_ISR register ******************/
11766 #define RTC_ISR_RECALPF_Pos (16U)
11767 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
11768 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11769 #define RTC_ISR_TAMP1F_Pos (13U)
11770 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
11771 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11772 #define RTC_ISR_TAMP2F_Pos (14U)
11773 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
11774 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11775 #define RTC_ISR_TSOVF_Pos (12U)
11776 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
11777 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11778 #define RTC_ISR_TSF_Pos (11U)
11779 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
11780 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
11781 #define RTC_ISR_WUTF_Pos (10U)
11782 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
11783 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11784 #define RTC_ISR_ALRBF_Pos (9U)
11785 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
11786 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11787 #define RTC_ISR_ALRAF_Pos (8U)
11788 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
11789 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11790 #define RTC_ISR_INIT_Pos (7U)
11791 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
11792 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
11793 #define RTC_ISR_INITF_Pos (6U)
11794 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
11795 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
11796 #define RTC_ISR_RSF_Pos (5U)
11797 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
11798 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
11799 #define RTC_ISR_INITS_Pos (4U)
11800 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
11801 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
11802 #define RTC_ISR_SHPF_Pos (3U)
11803 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
11804 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11805 #define RTC_ISR_WUTWF_Pos (2U)
11806 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
11807 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11808 #define RTC_ISR_ALRBWF_Pos (1U)
11809 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
11810 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11811 #define RTC_ISR_ALRAWF_Pos (0U)
11812 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
11813 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11814
11815 /******************** Bits definition for RTC_PRER register *****************/
11816 #define RTC_PRER_PREDIV_A_Pos (16U)
11817 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
11818 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11819 #define RTC_PRER_PREDIV_S_Pos (0U)
11820 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
11821 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11822
11823 /******************** Bits definition for RTC_WUTR register *****************/
11824 #define RTC_WUTR_WUT_Pos (0U)
11825 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
11826 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11827
11828 /******************** Bits definition for RTC_CALIBR register ***************/
11829 #define RTC_CALIBR_DCS_Pos (7U)
11830 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
11831 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
11832 #define RTC_CALIBR_DC_Pos (0U)
11833 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
11834 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
11835
11836 /******************** Bits definition for RTC_ALRMAR register ***************/
11837 #define RTC_ALRMAR_MSK4_Pos (31U)
11838 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
11839 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11840 #define RTC_ALRMAR_WDSEL_Pos (30U)
11841 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
11842 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11843 #define RTC_ALRMAR_DT_Pos (28U)
11844 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
11845 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11846 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
11847 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
11848 #define RTC_ALRMAR_DU_Pos (24U)
11849 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
11850 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11851 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
11852 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
11853 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
11854 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
11855 #define RTC_ALRMAR_MSK3_Pos (23U)
11856 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
11857 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11858 #define RTC_ALRMAR_PM_Pos (22U)
11859 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
11860 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11861 #define RTC_ALRMAR_HT_Pos (20U)
11862 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
11863 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11864 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
11865 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
11866 #define RTC_ALRMAR_HU_Pos (16U)
11867 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
11868 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11869 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
11870 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
11871 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
11872 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
11873 #define RTC_ALRMAR_MSK2_Pos (15U)
11874 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
11875 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11876 #define RTC_ALRMAR_MNT_Pos (12U)
11877 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
11878 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11879 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
11880 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
11881 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
11882 #define RTC_ALRMAR_MNU_Pos (8U)
11883 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
11884 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11885 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
11886 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
11887 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
11888 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
11889 #define RTC_ALRMAR_MSK1_Pos (7U)
11890 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
11891 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11892 #define RTC_ALRMAR_ST_Pos (4U)
11893 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
11894 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11895 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
11896 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
11897 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
11898 #define RTC_ALRMAR_SU_Pos (0U)
11899 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
11900 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11901 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
11902 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
11903 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
11904 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
11905
11906 /******************** Bits definition for RTC_ALRMBR register ***************/
11907 #define RTC_ALRMBR_MSK4_Pos (31U)
11908 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
11909 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11910 #define RTC_ALRMBR_WDSEL_Pos (30U)
11911 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
11912 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11913 #define RTC_ALRMBR_DT_Pos (28U)
11914 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
11915 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11916 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
11917 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
11918 #define RTC_ALRMBR_DU_Pos (24U)
11919 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
11920 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11921 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
11922 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
11923 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
11924 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
11925 #define RTC_ALRMBR_MSK3_Pos (23U)
11926 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
11927 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11928 #define RTC_ALRMBR_PM_Pos (22U)
11929 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
11930 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11931 #define RTC_ALRMBR_HT_Pos (20U)
11932 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
11933 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11934 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
11935 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
11936 #define RTC_ALRMBR_HU_Pos (16U)
11937 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
11938 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11939 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
11940 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
11941 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
11942 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
11943 #define RTC_ALRMBR_MSK2_Pos (15U)
11944 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
11945 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
11946 #define RTC_ALRMBR_MNT_Pos (12U)
11947 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
11948 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
11949 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
11950 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
11951 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
11952 #define RTC_ALRMBR_MNU_Pos (8U)
11953 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
11954 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
11955 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
11956 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
11957 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
11958 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
11959 #define RTC_ALRMBR_MSK1_Pos (7U)
11960 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
11961 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
11962 #define RTC_ALRMBR_ST_Pos (4U)
11963 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
11964 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
11965 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
11966 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
11967 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
11968 #define RTC_ALRMBR_SU_Pos (0U)
11969 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
11970 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
11971 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
11972 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
11973 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
11974 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
11975
11976 /******************** Bits definition for RTC_WPR register ******************/
11977 #define RTC_WPR_KEY_Pos (0U)
11978 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
11979 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
11980
11981 /******************** Bits definition for RTC_SSR register ******************/
11982 #define RTC_SSR_SS_Pos (0U)
11983 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
11984 #define RTC_SSR_SS RTC_SSR_SS_Msk
11985
11986 /******************** Bits definition for RTC_SHIFTR register ***************/
11987 #define RTC_SHIFTR_SUBFS_Pos (0U)
11988 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
11989 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11990 #define RTC_SHIFTR_ADD1S_Pos (31U)
11991 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
11992 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11993
11994 /******************** Bits definition for RTC_TSTR register *****************/
11995 #define RTC_TSTR_PM_Pos (22U)
11996 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
11997 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
11998 #define RTC_TSTR_HT_Pos (20U)
11999 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
12000 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
12001 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
12002 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
12003 #define RTC_TSTR_HU_Pos (16U)
12004 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
12005 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
12006 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
12007 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
12008 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
12009 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
12010 #define RTC_TSTR_MNT_Pos (12U)
12011 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
12012 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12013 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
12014 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
12015 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
12016 #define RTC_TSTR_MNU_Pos (8U)
12017 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
12018 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12019 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
12020 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
12021 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
12022 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
12023 #define RTC_TSTR_ST_Pos (4U)
12024 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
12025 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
12026 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
12027 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
12028 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
12029 #define RTC_TSTR_SU_Pos (0U)
12030 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
12031 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
12032 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
12033 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
12034 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
12035 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
12036
12037 /******************** Bits definition for RTC_TSDR register *****************/
12038 #define RTC_TSDR_WDU_Pos (13U)
12039 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
12040 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12041 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
12042 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
12043 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
12044 #define RTC_TSDR_MT_Pos (12U)
12045 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
12046 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
12047 #define RTC_TSDR_MU_Pos (8U)
12048 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
12049 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
12050 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
12051 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
12052 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
12053 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
12054 #define RTC_TSDR_DT_Pos (4U)
12055 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
12056 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
12057 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
12058 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
12059 #define RTC_TSDR_DU_Pos (0U)
12060 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
12061 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
12062 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
12063 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
12064 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
12065 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
12066
12067 /******************** Bits definition for RTC_TSSSR register ****************/
12068 #define RTC_TSSSR_SS_Pos (0U)
12069 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
12070 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12071
12072 /******************** Bits definition for RTC_CAL register *****************/
12073 #define RTC_CALR_CALP_Pos (15U)
12074 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
12075 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
12076 #define RTC_CALR_CALW8_Pos (14U)
12077 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
12078 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12079 #define RTC_CALR_CALW16_Pos (13U)
12080 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
12081 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12082 #define RTC_CALR_CALM_Pos (0U)
12083 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
12084 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
12085 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
12086 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
12087 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
12088 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
12089 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
12090 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
12091 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
12092 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
12093 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
12094
12095 /******************** Bits definition for RTC_TAFCR register ****************/
12096 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
12097 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
12098 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
12099 #define RTC_TAFCR_TSINSEL_Pos (17U)
12100 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
12101 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
12102 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
12103 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
12104 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
12105 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
12106 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
12107 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
12108 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
12109 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
12110 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
12111 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
12112 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
12113 #define RTC_TAFCR_TAMPFLT_Pos (11U)
12114 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
12115 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
12116 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
12117 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
12118 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
12119 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
12120 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
12121 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
12122 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
12123 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
12124 #define RTC_TAFCR_TAMPTS_Pos (7U)
12125 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
12126 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
12127 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
12128 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
12129 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
12130 #define RTC_TAFCR_TAMP2E_Pos (3U)
12131 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
12132 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
12133 #define RTC_TAFCR_TAMPIE_Pos (2U)
12134 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
12135 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
12136 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
12137 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
12138 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
12139 #define RTC_TAFCR_TAMP1E_Pos (0U)
12140 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
12141 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
12142
12143 /* Legacy defines */
12144 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
12145
12146 /******************** Bits definition for RTC_ALRMASSR register *************/
12147 #define RTC_ALRMASSR_MASKSS_Pos (24U)
12148 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
12149 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12150 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
12151 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
12152 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
12153 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
12154 #define RTC_ALRMASSR_SS_Pos (0U)
12155 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
12156 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12157
12158 /******************** Bits definition for RTC_ALRMBSSR register *************/
12159 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
12160 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
12161 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12162 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
12163 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
12164 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
12165 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
12166 #define RTC_ALRMBSSR_SS_Pos (0U)
12167 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
12168 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12169
12170 /******************** Bits definition for RTC_BKP0R register ****************/
12171 #define RTC_BKP0R_Pos (0U)
12172 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
12173 #define RTC_BKP0R RTC_BKP0R_Msk
12174
12175 /******************** Bits definition for RTC_BKP1R register ****************/
12176 #define RTC_BKP1R_Pos (0U)
12177 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
12178 #define RTC_BKP1R RTC_BKP1R_Msk
12179
12180 /******************** Bits definition for RTC_BKP2R register ****************/
12181 #define RTC_BKP2R_Pos (0U)
12182 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
12183 #define RTC_BKP2R RTC_BKP2R_Msk
12184
12185 /******************** Bits definition for RTC_BKP3R register ****************/
12186 #define RTC_BKP3R_Pos (0U)
12187 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
12188 #define RTC_BKP3R RTC_BKP3R_Msk
12189
12190 /******************** Bits definition for RTC_BKP4R register ****************/
12191 #define RTC_BKP4R_Pos (0U)
12192 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
12193 #define RTC_BKP4R RTC_BKP4R_Msk
12194
12195 /******************** Bits definition for RTC_BKP5R register ****************/
12196 #define RTC_BKP5R_Pos (0U)
12197 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
12198 #define RTC_BKP5R RTC_BKP5R_Msk
12199
12200 /******************** Bits definition for RTC_BKP6R register ****************/
12201 #define RTC_BKP6R_Pos (0U)
12202 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
12203 #define RTC_BKP6R RTC_BKP6R_Msk
12204
12205 /******************** Bits definition for RTC_BKP7R register ****************/
12206 #define RTC_BKP7R_Pos (0U)
12207 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
12208 #define RTC_BKP7R RTC_BKP7R_Msk
12209
12210 /******************** Bits definition for RTC_BKP8R register ****************/
12211 #define RTC_BKP8R_Pos (0U)
12212 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
12213 #define RTC_BKP8R RTC_BKP8R_Msk
12214
12215 /******************** Bits definition for RTC_BKP9R register ****************/
12216 #define RTC_BKP9R_Pos (0U)
12217 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
12218 #define RTC_BKP9R RTC_BKP9R_Msk
12219
12220 /******************** Bits definition for RTC_BKP10R register ***************/
12221 #define RTC_BKP10R_Pos (0U)
12222 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
12223 #define RTC_BKP10R RTC_BKP10R_Msk
12224
12225 /******************** Bits definition for RTC_BKP11R register ***************/
12226 #define RTC_BKP11R_Pos (0U)
12227 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
12228 #define RTC_BKP11R RTC_BKP11R_Msk
12229
12230 /******************** Bits definition for RTC_BKP12R register ***************/
12231 #define RTC_BKP12R_Pos (0U)
12232 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
12233 #define RTC_BKP12R RTC_BKP12R_Msk
12234
12235 /******************** Bits definition for RTC_BKP13R register ***************/
12236 #define RTC_BKP13R_Pos (0U)
12237 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
12238 #define RTC_BKP13R RTC_BKP13R_Msk
12239
12240 /******************** Bits definition for RTC_BKP14R register ***************/
12241 #define RTC_BKP14R_Pos (0U)
12242 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
12243 #define RTC_BKP14R RTC_BKP14R_Msk
12244
12245 /******************** Bits definition for RTC_BKP15R register ***************/
12246 #define RTC_BKP15R_Pos (0U)
12247 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
12248 #define RTC_BKP15R RTC_BKP15R_Msk
12249
12250 /******************** Bits definition for RTC_BKP16R register ***************/
12251 #define RTC_BKP16R_Pos (0U)
12252 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
12253 #define RTC_BKP16R RTC_BKP16R_Msk
12254
12255 /******************** Bits definition for RTC_BKP17R register ***************/
12256 #define RTC_BKP17R_Pos (0U)
12257 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
12258 #define RTC_BKP17R RTC_BKP17R_Msk
12259
12260 /******************** Bits definition for RTC_BKP18R register ***************/
12261 #define RTC_BKP18R_Pos (0U)
12262 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
12263 #define RTC_BKP18R RTC_BKP18R_Msk
12264
12265 /******************** Bits definition for RTC_BKP19R register ***************/
12266 #define RTC_BKP19R_Pos (0U)
12267 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
12268 #define RTC_BKP19R RTC_BKP19R_Msk
12269
12270 /******************** Number of backup registers ******************************/
12271 #define RTC_BKP_NUMBER 0x000000014U
12272
12273 /******************************************************************************/
12274 /* */
12275 /* Serial Audio Interface */
12276 /* */
12277 /******************************************************************************/
12278 /******************** Bit definition for SAI_GCR register *******************/
12279 #define SAI_GCR_SYNCIN_Pos (0U)
12280 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
12281 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
12282 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
12283 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
12284
12285 #define SAI_GCR_SYNCOUT_Pos (4U)
12286 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
12287 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
12288 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
12289 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
12290
12291 /******************* Bit definition for SAI_xCR1 register *******************/
12292 #define SAI_xCR1_MODE_Pos (0U)
12293 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
12294 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
12295 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
12296 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
12297
12298 #define SAI_xCR1_PRTCFG_Pos (2U)
12299 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
12300 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
12301 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
12302 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
12303
12304 #define SAI_xCR1_DS_Pos (5U)
12305 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
12306 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
12307 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
12308 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
12309 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
12310
12311 #define SAI_xCR1_LSBFIRST_Pos (8U)
12312 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
12313 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
12314 #define SAI_xCR1_CKSTR_Pos (9U)
12315 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
12316 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
12317
12318 #define SAI_xCR1_SYNCEN_Pos (10U)
12319 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
12320 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
12321 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
12322 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
12323
12324 #define SAI_xCR1_MONO_Pos (12U)
12325 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
12326 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
12327 #define SAI_xCR1_OUTDRIV_Pos (13U)
12328 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
12329 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
12330 #define SAI_xCR1_SAIEN_Pos (16U)
12331 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
12332 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
12333 #define SAI_xCR1_DMAEN_Pos (17U)
12334 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
12335 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
12336 #define SAI_xCR1_NODIV_Pos (19U)
12337 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
12338 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
12339
12340 #define SAI_xCR1_MCKDIV_Pos (20U)
12341 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
12342 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
12343 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
12344 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
12345 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
12346 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
12347
12348 /******************* Bit definition for SAI_xCR2 register *******************/
12349 #define SAI_xCR2_FTH_Pos (0U)
12350 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
12351 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
12352 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
12353 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
12354 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
12355
12356 #define SAI_xCR2_FFLUSH_Pos (3U)
12357 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
12358 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
12359 #define SAI_xCR2_TRIS_Pos (4U)
12360 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
12361 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
12362 #define SAI_xCR2_MUTE_Pos (5U)
12363 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
12364 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
12365 #define SAI_xCR2_MUTEVAL_Pos (6U)
12366 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
12367 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
12368
12369 #define SAI_xCR2_MUTECNT_Pos (7U)
12370 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
12371 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
12372 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
12373 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
12374 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
12375 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
12376 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
12377 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
12378
12379 #define SAI_xCR2_CPL_Pos (13U)
12380 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
12381 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
12382
12383 #define SAI_xCR2_COMP_Pos (14U)
12384 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
12385 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
12386 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
12387 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
12388
12389 /****************** Bit definition for SAI_xFRCR register *******************/
12390 #define SAI_xFRCR_FRL_Pos (0U)
12391 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
12392 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
12393 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
12394 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
12395 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
12396 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
12397 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
12398 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
12399 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
12400 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
12401
12402 #define SAI_xFRCR_FSALL_Pos (8U)
12403 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
12404 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
12405 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
12406 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
12407 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
12408 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
12409 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
12410 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
12411 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
12412
12413 #define SAI_xFRCR_FSDEF_Pos (16U)
12414 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
12415 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
12416 #define SAI_xFRCR_FSPOL_Pos (17U)
12417 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
12418 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
12419 #define SAI_xFRCR_FSOFF_Pos (18U)
12420 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
12421 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
12422 /* Legacy defines */
12423 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
12424
12425 /****************** Bit definition for SAI_xSLOTR register *******************/
12426 #define SAI_xSLOTR_FBOFF_Pos (0U)
12427 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
12428 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
12429 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
12430 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
12431 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
12432 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
12433 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
12434
12435 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
12436 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
12437 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
12438 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
12439 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
12440
12441 #define SAI_xSLOTR_NBSLOT_Pos (8U)
12442 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
12443 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
12444 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
12445 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
12446 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
12447 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
12448
12449 #define SAI_xSLOTR_SLOTEN_Pos (16U)
12450 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
12451 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
12452
12453 /******************* Bit definition for SAI_xIMR register *******************/
12454 #define SAI_xIMR_OVRUDRIE_Pos (0U)
12455 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
12456 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
12457 #define SAI_xIMR_MUTEDETIE_Pos (1U)
12458 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
12459 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
12460 #define SAI_xIMR_WCKCFGIE_Pos (2U)
12461 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
12462 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
12463 #define SAI_xIMR_FREQIE_Pos (3U)
12464 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
12465 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
12466 #define SAI_xIMR_CNRDYIE_Pos (4U)
12467 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
12468 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
12469 #define SAI_xIMR_AFSDETIE_Pos (5U)
12470 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
12471 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
12472 #define SAI_xIMR_LFSDETIE_Pos (6U)
12473 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
12474 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
12475
12476 /******************** Bit definition for SAI_xSR register *******************/
12477 #define SAI_xSR_OVRUDR_Pos (0U)
12478 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
12479 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
12480 #define SAI_xSR_MUTEDET_Pos (1U)
12481 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
12482 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
12483 #define SAI_xSR_WCKCFG_Pos (2U)
12484 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
12485 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
12486 #define SAI_xSR_FREQ_Pos (3U)
12487 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
12488 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
12489 #define SAI_xSR_CNRDY_Pos (4U)
12490 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
12491 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
12492 #define SAI_xSR_AFSDET_Pos (5U)
12493 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
12494 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
12495 #define SAI_xSR_LFSDET_Pos (6U)
12496 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
12497 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
12498
12499 #define SAI_xSR_FLVL_Pos (16U)
12500 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
12501 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
12502 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
12503 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
12504 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
12505
12506 /****************** Bit definition for SAI_xCLRFR register ******************/
12507 #define SAI_xCLRFR_COVRUDR_Pos (0U)
12508 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
12509 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
12510 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
12511 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
12512 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
12513 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
12514 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
12515 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
12516 #define SAI_xCLRFR_CFREQ_Pos (3U)
12517 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
12518 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
12519 #define SAI_xCLRFR_CCNRDY_Pos (4U)
12520 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
12521 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
12522 #define SAI_xCLRFR_CAFSDET_Pos (5U)
12523 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
12524 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
12525 #define SAI_xCLRFR_CLFSDET_Pos (6U)
12526 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
12527 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
12528
12529 /****************** Bit definition for SAI_xDR register ******************/
12530 #define SAI_xDR_DATA_Pos (0U)
12531 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
12532 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
12533
12534
12535 /******************************************************************************/
12536 /* */
12537 /* SD host Interface */
12538 /* */
12539 /******************************************************************************/
12540 /****************** Bit definition for SDIO_POWER register ******************/
12541 #define SDIO_POWER_PWRCTRL_Pos (0U)
12542 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
12543 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
12544 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
12545 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
12546
12547 /****************** Bit definition for SDIO_CLKCR register ******************/
12548 #define SDIO_CLKCR_CLKDIV_Pos (0U)
12549 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
12550 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
12551 #define SDIO_CLKCR_CLKEN_Pos (8U)
12552 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
12553 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
12554 #define SDIO_CLKCR_PWRSAV_Pos (9U)
12555 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
12556 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
12557 #define SDIO_CLKCR_BYPASS_Pos (10U)
12558 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
12559 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
12560
12561 #define SDIO_CLKCR_WIDBUS_Pos (11U)
12562 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
12563 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
12564 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
12565 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
12566
12567 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
12568 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
12569 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
12570 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
12571 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
12572 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
12573
12574 /******************* Bit definition for SDIO_ARG register *******************/
12575 #define SDIO_ARG_CMDARG_Pos (0U)
12576 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
12577 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
12578
12579 /******************* Bit definition for SDIO_CMD register *******************/
12580 #define SDIO_CMD_CMDINDEX_Pos (0U)
12581 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
12582 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
12583
12584 #define SDIO_CMD_WAITRESP_Pos (6U)
12585 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
12586 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
12587 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
12588 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
12589
12590 #define SDIO_CMD_WAITINT_Pos (8U)
12591 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
12592 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
12593 #define SDIO_CMD_WAITPEND_Pos (9U)
12594 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
12595 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
12596 #define SDIO_CMD_CPSMEN_Pos (10U)
12597 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
12598 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
12599 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
12600 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
12601 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
12602 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
12603 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
12604 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
12605 #define SDIO_CMD_NIEN_Pos (13U)
12606 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
12607 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
12608 #define SDIO_CMD_CEATACMD_Pos (14U)
12609 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
12610 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
12611
12612 /***************** Bit definition for SDIO_RESPCMD register *****************/
12613 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
12614 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
12615 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
12616
12617 /****************** Bit definition for SDIO_RESP0 register ******************/
12618 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
12619 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
12620 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
12621
12622 /****************** Bit definition for SDIO_RESP1 register ******************/
12623 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
12624 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
12625 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
12626
12627 /****************** Bit definition for SDIO_RESP2 register ******************/
12628 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
12629 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
12630 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
12631
12632 /****************** Bit definition for SDIO_RESP3 register ******************/
12633 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
12634 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
12635 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
12636
12637 /****************** Bit definition for SDIO_RESP4 register ******************/
12638 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
12639 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
12640 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
12641
12642 /****************** Bit definition for SDIO_DTIMER register *****************/
12643 #define SDIO_DTIMER_DATATIME_Pos (0U)
12644 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
12645 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
12646
12647 /****************** Bit definition for SDIO_DLEN register *******************/
12648 #define SDIO_DLEN_DATALENGTH_Pos (0U)
12649 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
12650 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
12651
12652 /****************** Bit definition for SDIO_DCTRL register ******************/
12653 #define SDIO_DCTRL_DTEN_Pos (0U)
12654 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
12655 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
12656 #define SDIO_DCTRL_DTDIR_Pos (1U)
12657 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
12658 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
12659 #define SDIO_DCTRL_DTMODE_Pos (2U)
12660 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
12661 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
12662 #define SDIO_DCTRL_DMAEN_Pos (3U)
12663 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
12664 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
12665
12666 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
12667 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
12668 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
12669 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
12670 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
12671 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
12672 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
12673
12674 #define SDIO_DCTRL_RWSTART_Pos (8U)
12675 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
12676 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
12677 #define SDIO_DCTRL_RWSTOP_Pos (9U)
12678 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
12679 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
12680 #define SDIO_DCTRL_RWMOD_Pos (10U)
12681 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
12682 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
12683 #define SDIO_DCTRL_SDIOEN_Pos (11U)
12684 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
12685 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
12686
12687 /****************** Bit definition for SDIO_DCOUNT register *****************/
12688 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
12689 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
12690 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
12691
12692 /****************** Bit definition for SDIO_STA register ********************/
12693 #define SDIO_STA_CCRCFAIL_Pos (0U)
12694 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
12695 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
12696 #define SDIO_STA_DCRCFAIL_Pos (1U)
12697 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
12698 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
12699 #define SDIO_STA_CTIMEOUT_Pos (2U)
12700 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
12701 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
12702 #define SDIO_STA_DTIMEOUT_Pos (3U)
12703 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
12704 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
12705 #define SDIO_STA_TXUNDERR_Pos (4U)
12706 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
12707 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
12708 #define SDIO_STA_RXOVERR_Pos (5U)
12709 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
12710 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
12711 #define SDIO_STA_CMDREND_Pos (6U)
12712 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
12713 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
12714 #define SDIO_STA_CMDSENT_Pos (7U)
12715 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
12716 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
12717 #define SDIO_STA_DATAEND_Pos (8U)
12718 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
12719 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
12720 #define SDIO_STA_STBITERR_Pos (9U)
12721 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
12722 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
12723 #define SDIO_STA_DBCKEND_Pos (10U)
12724 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
12725 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
12726 #define SDIO_STA_CMDACT_Pos (11U)
12727 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
12728 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
12729 #define SDIO_STA_TXACT_Pos (12U)
12730 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
12731 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
12732 #define SDIO_STA_RXACT_Pos (13U)
12733 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
12734 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
12735 #define SDIO_STA_TXFIFOHE_Pos (14U)
12736 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
12737 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
12738 #define SDIO_STA_RXFIFOHF_Pos (15U)
12739 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
12740 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
12741 #define SDIO_STA_TXFIFOF_Pos (16U)
12742 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
12743 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
12744 #define SDIO_STA_RXFIFOF_Pos (17U)
12745 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
12746 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
12747 #define SDIO_STA_TXFIFOE_Pos (18U)
12748 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
12749 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
12750 #define SDIO_STA_RXFIFOE_Pos (19U)
12751 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
12752 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
12753 #define SDIO_STA_TXDAVL_Pos (20U)
12754 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
12755 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
12756 #define SDIO_STA_RXDAVL_Pos (21U)
12757 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
12758 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
12759 #define SDIO_STA_SDIOIT_Pos (22U)
12760 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
12761 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
12762 #define SDIO_STA_CEATAEND_Pos (23U)
12763 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
12764 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
12765
12766 /******************* Bit definition for SDIO_ICR register *******************/
12767 #define SDIO_ICR_CCRCFAILC_Pos (0U)
12768 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
12769 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
12770 #define SDIO_ICR_DCRCFAILC_Pos (1U)
12771 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
12772 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
12773 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
12774 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
12775 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
12776 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
12777 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
12778 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
12779 #define SDIO_ICR_TXUNDERRC_Pos (4U)
12780 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
12781 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
12782 #define SDIO_ICR_RXOVERRC_Pos (5U)
12783 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
12784 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
12785 #define SDIO_ICR_CMDRENDC_Pos (6U)
12786 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
12787 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
12788 #define SDIO_ICR_CMDSENTC_Pos (7U)
12789 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
12790 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
12791 #define SDIO_ICR_DATAENDC_Pos (8U)
12792 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
12793 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
12794 #define SDIO_ICR_STBITERRC_Pos (9U)
12795 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
12796 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
12797 #define SDIO_ICR_DBCKENDC_Pos (10U)
12798 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
12799 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
12800 #define SDIO_ICR_SDIOITC_Pos (22U)
12801 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
12802 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
12803 #define SDIO_ICR_CEATAENDC_Pos (23U)
12804 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
12805 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
12806
12807 /****************** Bit definition for SDIO_MASK register *******************/
12808 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
12809 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
12810 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
12811 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
12812 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
12813 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
12814 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
12815 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
12816 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
12817 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
12818 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
12819 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
12820 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
12821 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
12822 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
12823 #define SDIO_MASK_RXOVERRIE_Pos (5U)
12824 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
12825 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
12826 #define SDIO_MASK_CMDRENDIE_Pos (6U)
12827 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
12828 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
12829 #define SDIO_MASK_CMDSENTIE_Pos (7U)
12830 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
12831 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
12832 #define SDIO_MASK_DATAENDIE_Pos (8U)
12833 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
12834 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
12835 #define SDIO_MASK_STBITERRIE_Pos (9U)
12836 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
12837 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
12838 #define SDIO_MASK_DBCKENDIE_Pos (10U)
12839 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
12840 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
12841 #define SDIO_MASK_CMDACTIE_Pos (11U)
12842 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
12843 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
12844 #define SDIO_MASK_TXACTIE_Pos (12U)
12845 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
12846 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
12847 #define SDIO_MASK_RXACTIE_Pos (13U)
12848 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
12849 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
12850 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
12851 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
12852 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
12853 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
12854 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
12855 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
12856 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
12857 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
12858 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
12859 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
12860 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
12861 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
12862 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
12863 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
12864 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
12865 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
12866 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
12867 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
12868 #define SDIO_MASK_TXDAVLIE_Pos (20U)
12869 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
12870 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
12871 #define SDIO_MASK_RXDAVLIE_Pos (21U)
12872 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
12873 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
12874 #define SDIO_MASK_SDIOITIE_Pos (22U)
12875 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
12876 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
12877 #define SDIO_MASK_CEATAENDIE_Pos (23U)
12878 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
12879 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
12880
12881 /***************** Bit definition for SDIO_FIFOCNT register *****************/
12882 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
12883 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
12884 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
12885
12886 /****************** Bit definition for SDIO_FIFO register *******************/
12887 #define SDIO_FIFO_FIFODATA_Pos (0U)
12888 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
12889 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
12890
12891 /******************************************************************************/
12892 /* */
12893 /* Serial Peripheral Interface */
12894 /* */
12895 /******************************************************************************/
12896 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
12897
12898 /******************* Bit definition for SPI_CR1 register ********************/
12899 #define SPI_CR1_CPHA_Pos (0U)
12900 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
12901 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
12902 #define SPI_CR1_CPOL_Pos (1U)
12903 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
12904 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
12905 #define SPI_CR1_MSTR_Pos (2U)
12906 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
12907 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
12908
12909 #define SPI_CR1_BR_Pos (3U)
12910 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
12911 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
12912 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
12913 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
12914 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
12915
12916 #define SPI_CR1_SPE_Pos (6U)
12917 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
12918 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
12919 #define SPI_CR1_LSBFIRST_Pos (7U)
12920 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
12921 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
12922 #define SPI_CR1_SSI_Pos (8U)
12923 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
12924 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
12925 #define SPI_CR1_SSM_Pos (9U)
12926 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
12927 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
12928 #define SPI_CR1_RXONLY_Pos (10U)
12929 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
12930 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
12931 #define SPI_CR1_DFF_Pos (11U)
12932 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
12933 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
12934 #define SPI_CR1_CRCNEXT_Pos (12U)
12935 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
12936 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
12937 #define SPI_CR1_CRCEN_Pos (13U)
12938 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
12939 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
12940 #define SPI_CR1_BIDIOE_Pos (14U)
12941 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
12942 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
12943 #define SPI_CR1_BIDIMODE_Pos (15U)
12944 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
12945 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
12946
12947 /******************* Bit definition for SPI_CR2 register ********************/
12948 #define SPI_CR2_RXDMAEN_Pos (0U)
12949 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
12950 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
12951 #define SPI_CR2_TXDMAEN_Pos (1U)
12952 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
12953 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
12954 #define SPI_CR2_SSOE_Pos (2U)
12955 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
12956 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
12957 #define SPI_CR2_FRF_Pos (4U)
12958 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
12959 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
12960 #define SPI_CR2_ERRIE_Pos (5U)
12961 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
12962 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
12963 #define SPI_CR2_RXNEIE_Pos (6U)
12964 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
12965 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
12966 #define SPI_CR2_TXEIE_Pos (7U)
12967 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
12968 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
12969
12970 /******************** Bit definition for SPI_SR register ********************/
12971 #define SPI_SR_RXNE_Pos (0U)
12972 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
12973 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
12974 #define SPI_SR_TXE_Pos (1U)
12975 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
12976 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
12977 #define SPI_SR_CHSIDE_Pos (2U)
12978 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
12979 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
12980 #define SPI_SR_UDR_Pos (3U)
12981 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
12982 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
12983 #define SPI_SR_CRCERR_Pos (4U)
12984 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
12985 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
12986 #define SPI_SR_MODF_Pos (5U)
12987 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
12988 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
12989 #define SPI_SR_OVR_Pos (6U)
12990 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
12991 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
12992 #define SPI_SR_BSY_Pos (7U)
12993 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
12994 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
12995 #define SPI_SR_FRE_Pos (8U)
12996 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
12997 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
12998
12999 /******************** Bit definition for SPI_DR register ********************/
13000 #define SPI_DR_DR_Pos (0U)
13001 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
13002 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
13003
13004 /******************* Bit definition for SPI_CRCPR register ******************/
13005 #define SPI_CRCPR_CRCPOLY_Pos (0U)
13006 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
13007 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
13008
13009 /****************** Bit definition for SPI_RXCRCR register ******************/
13010 #define SPI_RXCRCR_RXCRC_Pos (0U)
13011 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
13012 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
13013
13014 /****************** Bit definition for SPI_TXCRCR register ******************/
13015 #define SPI_TXCRCR_TXCRC_Pos (0U)
13016 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
13017 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
13018
13019 /****************** Bit definition for SPI_I2SCFGR register *****************/
13020 #define SPI_I2SCFGR_CHLEN_Pos (0U)
13021 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
13022 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
13023
13024 #define SPI_I2SCFGR_DATLEN_Pos (1U)
13025 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
13026 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
13027 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
13028 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
13029
13030 #define SPI_I2SCFGR_CKPOL_Pos (3U)
13031 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
13032 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
13033
13034 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
13035 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
13036 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
13037 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
13038 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
13039
13040 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
13041 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
13042 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
13043
13044 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
13045 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
13046 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
13047 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
13048 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
13049
13050 #define SPI_I2SCFGR_I2SE_Pos (10U)
13051 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
13052 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
13053 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
13054 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
13055 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
13056
13057 /****************** Bit definition for SPI_I2SPR register *******************/
13058 #define SPI_I2SPR_I2SDIV_Pos (0U)
13059 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
13060 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
13061 #define SPI_I2SPR_ODD_Pos (8U)
13062 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
13063 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
13064 #define SPI_I2SPR_MCKOE_Pos (9U)
13065 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
13066 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
13067
13068 /******************************************************************************/
13069 /* */
13070 /* SYSCFG */
13071 /* */
13072 /******************************************************************************/
13073 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
13074 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
13075 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
13076 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
13077 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
13078 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
13079 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
13080 #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
13081 #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
13082 #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
13083 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
13084 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
13085 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
13086 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
13087 /* Legacy Defines */
13088 #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
13089 /****************** Bit definition for SYSCFG_PMC register ******************/
13090 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
13091 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
13092 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
13093 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
13094 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
13095 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
13096 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
13097 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
13098 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
13099 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
13100 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
13101 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
13102 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
13103 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
13104 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
13105 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
13106 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
13107
13108 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13109 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13110 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
13111 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
13112 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13113 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
13114 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
13115 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13116 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
13117 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
13118 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13119 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
13120 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
13121 /**
13122 * @brief EXTI0 configuration
13123 */
13124 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
13125 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
13126 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
13127 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
13128 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
13129 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
13130 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
13131 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
13132 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
13133 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
13134 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
13135
13136 /**
13137 * @brief EXTI1 configuration
13138 */
13139 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
13140 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
13141 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
13142 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
13143 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
13144 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
13145 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
13146 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
13147 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
13148 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
13149 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
13150
13151 /**
13152 * @brief EXTI2 configuration
13153 */
13154 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
13155 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
13156 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
13157 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
13158 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
13159 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
13160 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
13161 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
13162 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
13163 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
13164 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
13165
13166 /**
13167 * @brief EXTI3 configuration
13168 */
13169 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
13170 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
13171 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
13172 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
13173 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
13174 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
13175 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
13176 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
13177 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
13178 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
13179 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
13180
13181 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13182 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13183 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
13184 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
13185 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13186 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
13187 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
13188 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13189 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
13190 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
13191 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13192 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
13193 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
13194
13195 /**
13196 * @brief EXTI4 configuration
13197 */
13198 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
13199 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
13200 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
13201 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
13202 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
13203 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
13204 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
13205 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
13206 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
13207 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
13208 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
13209
13210 /**
13211 * @brief EXTI5 configuration
13212 */
13213 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
13214 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
13215 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
13216 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
13217 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
13218 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
13219 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
13220 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
13221 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
13222 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
13223 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
13224
13225 /**
13226 * @brief EXTI6 configuration
13227 */
13228 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
13229 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
13230 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
13231 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
13232 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
13233 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
13234 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
13235 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
13236 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
13237 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
13238 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
13239
13240 /**
13241 * @brief EXTI7 configuration
13242 */
13243 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
13244 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
13245 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
13246 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
13247 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
13248 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
13249 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
13250 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
13251 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
13252 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
13253 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
13254
13255 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13256 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13257 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
13258 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
13259 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13260 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
13261 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
13262 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13263 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
13264 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
13265 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13266 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
13267 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
13268
13269 /**
13270 * @brief EXTI8 configuration
13271 */
13272 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
13273 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
13274 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
13275 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
13276 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
13277 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
13278 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
13279 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
13280 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
13281 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
13282
13283 /**
13284 * @brief EXTI9 configuration
13285 */
13286 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
13287 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
13288 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
13289 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
13290 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
13291 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
13292 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
13293 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
13294 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
13295 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
13296
13297 /**
13298 * @brief EXTI10 configuration
13299 */
13300 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
13301 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
13302 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
13303 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
13304 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
13305 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
13306 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
13307 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
13308 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
13309 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
13310
13311 /**
13312 * @brief EXTI11 configuration
13313 */
13314 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
13315 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
13316 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
13317 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
13318 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
13319 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
13320 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
13321 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
13322 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
13323 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
13324
13325
13326 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13327 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13328 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
13329 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
13330 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13331 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
13332 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
13333 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13334 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
13335 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
13336 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13337 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
13338 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
13339
13340 /**
13341 * @brief EXTI12 configuration
13342 */
13343 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
13344 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
13345 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
13346 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
13347 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
13348 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
13349 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
13350 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
13351 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
13352 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
13353
13354 /**
13355 * @brief EXTI13 configuration
13356 */
13357 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
13358 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
13359 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
13360 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
13361 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
13362 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
13363 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
13364 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
13365 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
13366 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
13367
13368 /**
13369 * @brief EXTI14 configuration
13370 */
13371 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
13372 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
13373 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
13374 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
13375 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
13376 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
13377 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
13378 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
13379 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
13380 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
13381
13382 /**
13383 * @brief EXTI15 configuration
13384 */
13385 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
13386 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
13387 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
13388 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
13389 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
13390 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
13391 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
13392 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
13393 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
13394 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
13395
13396 /****************** Bit definition for SYSCFG_CMPCR register ****************/
13397 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
13398 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
13399 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
13400 #define SYSCFG_CMPCR_READY_Pos (8U)
13401 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
13402 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
13403
13404 /******************************************************************************/
13405 /* */
13406 /* TIM */
13407 /* */
13408 /******************************************************************************/
13409 /******************* Bit definition for TIM_CR1 register ********************/
13410 #define TIM_CR1_CEN_Pos (0U)
13411 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
13412 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
13413 #define TIM_CR1_UDIS_Pos (1U)
13414 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
13415 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
13416 #define TIM_CR1_URS_Pos (2U)
13417 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
13418 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
13419 #define TIM_CR1_OPM_Pos (3U)
13420 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
13421 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
13422 #define TIM_CR1_DIR_Pos (4U)
13423 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
13424 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
13425
13426 #define TIM_CR1_CMS_Pos (5U)
13427 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
13428 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
13429 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
13430 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
13431
13432 #define TIM_CR1_ARPE_Pos (7U)
13433 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
13434 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
13435
13436 #define TIM_CR1_CKD_Pos (8U)
13437 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
13438 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
13439 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
13440 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
13441
13442 /******************* Bit definition for TIM_CR2 register ********************/
13443 #define TIM_CR2_CCPC_Pos (0U)
13444 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
13445 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
13446 #define TIM_CR2_CCUS_Pos (2U)
13447 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
13448 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
13449 #define TIM_CR2_CCDS_Pos (3U)
13450 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
13451 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
13452
13453 #define TIM_CR2_MMS_Pos (4U)
13454 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
13455 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
13456 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
13457 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
13458 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
13459
13460 #define TIM_CR2_TI1S_Pos (7U)
13461 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
13462 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
13463 #define TIM_CR2_OIS1_Pos (8U)
13464 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
13465 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
13466 #define TIM_CR2_OIS1N_Pos (9U)
13467 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
13468 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
13469 #define TIM_CR2_OIS2_Pos (10U)
13470 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
13471 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
13472 #define TIM_CR2_OIS2N_Pos (11U)
13473 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
13474 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
13475 #define TIM_CR2_OIS3_Pos (12U)
13476 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
13477 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
13478 #define TIM_CR2_OIS3N_Pos (13U)
13479 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
13480 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
13481 #define TIM_CR2_OIS4_Pos (14U)
13482 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
13483 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
13484
13485 /******************* Bit definition for TIM_SMCR register *******************/
13486 #define TIM_SMCR_SMS_Pos (0U)
13487 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
13488 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
13489 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
13490 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
13491 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
13492
13493 #define TIM_SMCR_TS_Pos (4U)
13494 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
13495 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
13496 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
13497 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
13498 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
13499
13500 #define TIM_SMCR_MSM_Pos (7U)
13501 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
13502 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
13503
13504 #define TIM_SMCR_ETF_Pos (8U)
13505 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
13506 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
13507 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
13508 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
13509 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
13510 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
13511
13512 #define TIM_SMCR_ETPS_Pos (12U)
13513 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
13514 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
13515 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
13516 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
13517
13518 #define TIM_SMCR_ECE_Pos (14U)
13519 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
13520 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
13521 #define TIM_SMCR_ETP_Pos (15U)
13522 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
13523 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
13524
13525 /******************* Bit definition for TIM_DIER register *******************/
13526 #define TIM_DIER_UIE_Pos (0U)
13527 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
13528 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
13529 #define TIM_DIER_CC1IE_Pos (1U)
13530 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
13531 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
13532 #define TIM_DIER_CC2IE_Pos (2U)
13533 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
13534 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
13535 #define TIM_DIER_CC3IE_Pos (3U)
13536 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
13537 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
13538 #define TIM_DIER_CC4IE_Pos (4U)
13539 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
13540 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
13541 #define TIM_DIER_COMIE_Pos (5U)
13542 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
13543 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
13544 #define TIM_DIER_TIE_Pos (6U)
13545 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
13546 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
13547 #define TIM_DIER_BIE_Pos (7U)
13548 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
13549 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
13550 #define TIM_DIER_UDE_Pos (8U)
13551 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
13552 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
13553 #define TIM_DIER_CC1DE_Pos (9U)
13554 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
13555 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
13556 #define TIM_DIER_CC2DE_Pos (10U)
13557 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
13558 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
13559 #define TIM_DIER_CC3DE_Pos (11U)
13560 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
13561 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
13562 #define TIM_DIER_CC4DE_Pos (12U)
13563 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
13564 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
13565 #define TIM_DIER_COMDE_Pos (13U)
13566 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
13567 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
13568 #define TIM_DIER_TDE_Pos (14U)
13569 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
13570 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
13571
13572 /******************** Bit definition for TIM_SR register ********************/
13573 #define TIM_SR_UIF_Pos (0U)
13574 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
13575 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
13576 #define TIM_SR_CC1IF_Pos (1U)
13577 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
13578 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
13579 #define TIM_SR_CC2IF_Pos (2U)
13580 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
13581 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
13582 #define TIM_SR_CC3IF_Pos (3U)
13583 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
13584 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
13585 #define TIM_SR_CC4IF_Pos (4U)
13586 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
13587 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
13588 #define TIM_SR_COMIF_Pos (5U)
13589 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
13590 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
13591 #define TIM_SR_TIF_Pos (6U)
13592 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
13593 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
13594 #define TIM_SR_BIF_Pos (7U)
13595 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
13596 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
13597 #define TIM_SR_CC1OF_Pos (9U)
13598 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
13599 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
13600 #define TIM_SR_CC2OF_Pos (10U)
13601 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
13602 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
13603 #define TIM_SR_CC3OF_Pos (11U)
13604 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
13605 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
13606 #define TIM_SR_CC4OF_Pos (12U)
13607 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
13608 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
13609
13610 /******************* Bit definition for TIM_EGR register ********************/
13611 #define TIM_EGR_UG_Pos (0U)
13612 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
13613 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
13614 #define TIM_EGR_CC1G_Pos (1U)
13615 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
13616 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
13617 #define TIM_EGR_CC2G_Pos (2U)
13618 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
13619 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
13620 #define TIM_EGR_CC3G_Pos (3U)
13621 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
13622 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
13623 #define TIM_EGR_CC4G_Pos (4U)
13624 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
13625 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
13626 #define TIM_EGR_COMG_Pos (5U)
13627 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
13628 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
13629 #define TIM_EGR_TG_Pos (6U)
13630 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
13631 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
13632 #define TIM_EGR_BG_Pos (7U)
13633 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
13634 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
13635
13636 /****************** Bit definition for TIM_CCMR1 register *******************/
13637 #define TIM_CCMR1_CC1S_Pos (0U)
13638 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
13639 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13640 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
13641 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
13642
13643 #define TIM_CCMR1_OC1FE_Pos (2U)
13644 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
13645 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
13646 #define TIM_CCMR1_OC1PE_Pos (3U)
13647 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
13648 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
13649
13650 #define TIM_CCMR1_OC1M_Pos (4U)
13651 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
13652 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
13653 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
13654 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
13655 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
13656
13657 #define TIM_CCMR1_OC1CE_Pos (7U)
13658 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
13659 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
13660
13661 #define TIM_CCMR1_CC2S_Pos (8U)
13662 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
13663 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
13664 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
13665 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
13666
13667 #define TIM_CCMR1_OC2FE_Pos (10U)
13668 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
13669 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
13670 #define TIM_CCMR1_OC2PE_Pos (11U)
13671 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
13672 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
13673
13674 #define TIM_CCMR1_OC2M_Pos (12U)
13675 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
13676 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
13677 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
13678 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
13679 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
13680
13681 #define TIM_CCMR1_OC2CE_Pos (15U)
13682 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
13683 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
13684
13685 /*----------------------------------------------------------------------------*/
13686
13687 #define TIM_CCMR1_IC1PSC_Pos (2U)
13688 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
13689 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
13690 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
13691 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
13692
13693 #define TIM_CCMR1_IC1F_Pos (4U)
13694 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
13695 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
13696 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
13697 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
13698 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
13699 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
13700
13701 #define TIM_CCMR1_IC2PSC_Pos (10U)
13702 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
13703 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
13704 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
13705 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
13706
13707 #define TIM_CCMR1_IC2F_Pos (12U)
13708 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
13709 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
13710 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
13711 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
13712 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
13713 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
13714
13715 /****************** Bit definition for TIM_CCMR2 register *******************/
13716 #define TIM_CCMR2_CC3S_Pos (0U)
13717 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
13718 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
13719 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
13720 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
13721
13722 #define TIM_CCMR2_OC3FE_Pos (2U)
13723 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
13724 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
13725 #define TIM_CCMR2_OC3PE_Pos (3U)
13726 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
13727 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
13728
13729 #define TIM_CCMR2_OC3M_Pos (4U)
13730 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
13731 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
13732 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
13733 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
13734 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
13735
13736 #define TIM_CCMR2_OC3CE_Pos (7U)
13737 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
13738 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
13739
13740 #define TIM_CCMR2_CC4S_Pos (8U)
13741 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
13742 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
13743 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
13744 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
13745
13746 #define TIM_CCMR2_OC4FE_Pos (10U)
13747 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
13748 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
13749 #define TIM_CCMR2_OC4PE_Pos (11U)
13750 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
13751 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
13752
13753 #define TIM_CCMR2_OC4M_Pos (12U)
13754 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
13755 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
13756 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
13757 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
13758 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
13759
13760 #define TIM_CCMR2_OC4CE_Pos (15U)
13761 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
13762 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
13763
13764 /*----------------------------------------------------------------------------*/
13765
13766 #define TIM_CCMR2_IC3PSC_Pos (2U)
13767 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
13768 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
13769 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
13770 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
13771
13772 #define TIM_CCMR2_IC3F_Pos (4U)
13773 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
13774 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
13775 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
13776 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
13777 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
13778 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
13779
13780 #define TIM_CCMR2_IC4PSC_Pos (10U)
13781 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
13782 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
13783 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
13784 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
13785
13786 #define TIM_CCMR2_IC4F_Pos (12U)
13787 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
13788 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
13789 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
13790 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
13791 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
13792 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
13793
13794 /******************* Bit definition for TIM_CCER register *******************/
13795 #define TIM_CCER_CC1E_Pos (0U)
13796 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
13797 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
13798 #define TIM_CCER_CC1P_Pos (1U)
13799 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
13800 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
13801 #define TIM_CCER_CC1NE_Pos (2U)
13802 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
13803 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
13804 #define TIM_CCER_CC1NP_Pos (3U)
13805 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
13806 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
13807 #define TIM_CCER_CC2E_Pos (4U)
13808 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
13809 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
13810 #define TIM_CCER_CC2P_Pos (5U)
13811 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
13812 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
13813 #define TIM_CCER_CC2NE_Pos (6U)
13814 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
13815 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
13816 #define TIM_CCER_CC2NP_Pos (7U)
13817 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
13818 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
13819 #define TIM_CCER_CC3E_Pos (8U)
13820 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
13821 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
13822 #define TIM_CCER_CC3P_Pos (9U)
13823 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
13824 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
13825 #define TIM_CCER_CC3NE_Pos (10U)
13826 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
13827 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
13828 #define TIM_CCER_CC3NP_Pos (11U)
13829 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
13830 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
13831 #define TIM_CCER_CC4E_Pos (12U)
13832 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
13833 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
13834 #define TIM_CCER_CC4P_Pos (13U)
13835 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
13836 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
13837 #define TIM_CCER_CC4NP_Pos (15U)
13838 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
13839 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
13840
13841 /******************* Bit definition for TIM_CNT register ********************/
13842 #define TIM_CNT_CNT_Pos (0U)
13843 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
13844 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
13845
13846 /******************* Bit definition for TIM_PSC register ********************/
13847 #define TIM_PSC_PSC_Pos (0U)
13848 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
13849 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
13850
13851 /******************* Bit definition for TIM_ARR register ********************/
13852 #define TIM_ARR_ARR_Pos (0U)
13853 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
13854 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
13855
13856 /******************* Bit definition for TIM_RCR register ********************/
13857 #define TIM_RCR_REP_Pos (0U)
13858 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
13859 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
13860
13861 /******************* Bit definition for TIM_CCR1 register *******************/
13862 #define TIM_CCR1_CCR1_Pos (0U)
13863 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
13864 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
13865
13866 /******************* Bit definition for TIM_CCR2 register *******************/
13867 #define TIM_CCR2_CCR2_Pos (0U)
13868 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
13869 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
13870
13871 /******************* Bit definition for TIM_CCR3 register *******************/
13872 #define TIM_CCR3_CCR3_Pos (0U)
13873 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
13874 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
13875
13876 /******************* Bit definition for TIM_CCR4 register *******************/
13877 #define TIM_CCR4_CCR4_Pos (0U)
13878 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
13879 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
13880
13881 /******************* Bit definition for TIM_BDTR register *******************/
13882 #define TIM_BDTR_DTG_Pos (0U)
13883 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
13884 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
13885 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
13886 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
13887 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
13888 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
13889 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
13890 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
13891 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
13892 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
13893
13894 #define TIM_BDTR_LOCK_Pos (8U)
13895 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
13896 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
13897 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
13898 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
13899
13900 #define TIM_BDTR_OSSI_Pos (10U)
13901 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
13902 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
13903 #define TIM_BDTR_OSSR_Pos (11U)
13904 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
13905 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
13906 #define TIM_BDTR_BKE_Pos (12U)
13907 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
13908 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
13909 #define TIM_BDTR_BKP_Pos (13U)
13910 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
13911 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
13912 #define TIM_BDTR_AOE_Pos (14U)
13913 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
13914 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
13915 #define TIM_BDTR_MOE_Pos (15U)
13916 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
13917 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
13918
13919 /******************* Bit definition for TIM_DCR register ********************/
13920 #define TIM_DCR_DBA_Pos (0U)
13921 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
13922 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
13923 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
13924 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
13925 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
13926 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
13927 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
13928
13929 #define TIM_DCR_DBL_Pos (8U)
13930 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
13931 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
13932 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
13933 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
13934 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
13935 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
13936 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
13937
13938 /******************* Bit definition for TIM_DMAR register *******************/
13939 #define TIM_DMAR_DMAB_Pos (0U)
13940 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
13941 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
13942
13943 /******************* Bit definition for TIM_OR register *********************/
13944 #define TIM_OR_TI1_RMP_Pos (0U)
13945 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
13946 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
13947 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
13948 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
13949
13950 #define TIM_OR_TI4_RMP_Pos (6U)
13951 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
13952 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
13953 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
13954 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
13955 #define TIM_OR_ITR1_RMP_Pos (10U)
13956 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
13957 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
13958 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
13959 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
13960
13961
13962 /******************************************************************************/
13963 /* */
13964 /* Universal Synchronous Asynchronous Receiver Transmitter */
13965 /* */
13966 /******************************************************************************/
13967 /******************* Bit definition for USART_SR register *******************/
13968 #define USART_SR_PE_Pos (0U)
13969 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
13970 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
13971 #define USART_SR_FE_Pos (1U)
13972 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
13973 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
13974 #define USART_SR_NE_Pos (2U)
13975 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
13976 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
13977 #define USART_SR_ORE_Pos (3U)
13978 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
13979 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
13980 #define USART_SR_IDLE_Pos (4U)
13981 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
13982 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
13983 #define USART_SR_RXNE_Pos (5U)
13984 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
13985 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
13986 #define USART_SR_TC_Pos (6U)
13987 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
13988 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
13989 #define USART_SR_TXE_Pos (7U)
13990 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
13991 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
13992 #define USART_SR_LBD_Pos (8U)
13993 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
13994 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
13995 #define USART_SR_CTS_Pos (9U)
13996 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
13997 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
13998
13999 /******************* Bit definition for USART_DR register *******************/
14000 #define USART_DR_DR_Pos (0U)
14001 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
14002 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
14003
14004 /****************** Bit definition for USART_BRR register *******************/
14005 #define USART_BRR_DIV_Fraction_Pos (0U)
14006 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
14007 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
14008 #define USART_BRR_DIV_Mantissa_Pos (4U)
14009 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
14010 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
14011
14012 /****************** Bit definition for USART_CR1 register *******************/
14013 #define USART_CR1_SBK_Pos (0U)
14014 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
14015 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
14016 #define USART_CR1_RWU_Pos (1U)
14017 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
14018 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
14019 #define USART_CR1_RE_Pos (2U)
14020 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
14021 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
14022 #define USART_CR1_TE_Pos (3U)
14023 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
14024 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
14025 #define USART_CR1_IDLEIE_Pos (4U)
14026 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
14027 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
14028 #define USART_CR1_RXNEIE_Pos (5U)
14029 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
14030 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
14031 #define USART_CR1_TCIE_Pos (6U)
14032 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
14033 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
14034 #define USART_CR1_TXEIE_Pos (7U)
14035 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
14036 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
14037 #define USART_CR1_PEIE_Pos (8U)
14038 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
14039 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
14040 #define USART_CR1_PS_Pos (9U)
14041 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
14042 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
14043 #define USART_CR1_PCE_Pos (10U)
14044 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
14045 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
14046 #define USART_CR1_WAKE_Pos (11U)
14047 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
14048 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
14049 #define USART_CR1_M_Pos (12U)
14050 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
14051 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
14052 #define USART_CR1_UE_Pos (13U)
14053 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
14054 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
14055 #define USART_CR1_OVER8_Pos (15U)
14056 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
14057 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
14058
14059 /****************** Bit definition for USART_CR2 register *******************/
14060 #define USART_CR2_ADD_Pos (0U)
14061 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
14062 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
14063 #define USART_CR2_LBDL_Pos (5U)
14064 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
14065 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
14066 #define USART_CR2_LBDIE_Pos (6U)
14067 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
14068 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
14069 #define USART_CR2_LBCL_Pos (8U)
14070 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
14071 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
14072 #define USART_CR2_CPHA_Pos (9U)
14073 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
14074 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
14075 #define USART_CR2_CPOL_Pos (10U)
14076 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
14077 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
14078 #define USART_CR2_CLKEN_Pos (11U)
14079 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
14080 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
14081
14082 #define USART_CR2_STOP_Pos (12U)
14083 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
14084 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
14085 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
14086 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
14087
14088 #define USART_CR2_LINEN_Pos (14U)
14089 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
14090 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
14091
14092 /****************** Bit definition for USART_CR3 register *******************/
14093 #define USART_CR3_EIE_Pos (0U)
14094 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
14095 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
14096 #define USART_CR3_IREN_Pos (1U)
14097 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
14098 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
14099 #define USART_CR3_IRLP_Pos (2U)
14100 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
14101 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
14102 #define USART_CR3_HDSEL_Pos (3U)
14103 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
14104 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
14105 #define USART_CR3_NACK_Pos (4U)
14106 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
14107 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
14108 #define USART_CR3_SCEN_Pos (5U)
14109 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
14110 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
14111 #define USART_CR3_DMAR_Pos (6U)
14112 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
14113 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
14114 #define USART_CR3_DMAT_Pos (7U)
14115 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
14116 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
14117 #define USART_CR3_RTSE_Pos (8U)
14118 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
14119 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
14120 #define USART_CR3_CTSE_Pos (9U)
14121 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
14122 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
14123 #define USART_CR3_CTSIE_Pos (10U)
14124 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
14125 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
14126 #define USART_CR3_ONEBIT_Pos (11U)
14127 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
14128 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
14129
14130 /****************** Bit definition for USART_GTPR register ******************/
14131 #define USART_GTPR_PSC_Pos (0U)
14132 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
14133 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
14134 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
14135 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
14136 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
14137 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
14138 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
14139 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
14140 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
14141 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
14142
14143 #define USART_GTPR_GT_Pos (8U)
14144 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
14145 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
14146
14147 /******************************************************************************/
14148 /* */
14149 /* Window WATCHDOG */
14150 /* */
14151 /******************************************************************************/
14152 /******************* Bit definition for WWDG_CR register ********************/
14153 #define WWDG_CR_T_Pos (0U)
14154 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
14155 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
14156 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
14157 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
14158 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
14159 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
14160 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
14161 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
14162 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
14163 /* Legacy defines */
14164 #define WWDG_CR_T0 WWDG_CR_T_0
14165 #define WWDG_CR_T1 WWDG_CR_T_1
14166 #define WWDG_CR_T2 WWDG_CR_T_2
14167 #define WWDG_CR_T3 WWDG_CR_T_3
14168 #define WWDG_CR_T4 WWDG_CR_T_4
14169 #define WWDG_CR_T5 WWDG_CR_T_5
14170 #define WWDG_CR_T6 WWDG_CR_T_6
14171
14172 #define WWDG_CR_WDGA_Pos (7U)
14173 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
14174 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
14175
14176 /******************* Bit definition for WWDG_CFR register *******************/
14177 #define WWDG_CFR_W_Pos (0U)
14178 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
14179 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
14180 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
14181 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
14182 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
14183 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
14184 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
14185 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
14186 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
14187 /* Legacy defines */
14188 #define WWDG_CFR_W0 WWDG_CFR_W_0
14189 #define WWDG_CFR_W1 WWDG_CFR_W_1
14190 #define WWDG_CFR_W2 WWDG_CFR_W_2
14191 #define WWDG_CFR_W3 WWDG_CFR_W_3
14192 #define WWDG_CFR_W4 WWDG_CFR_W_4
14193 #define WWDG_CFR_W5 WWDG_CFR_W_5
14194 #define WWDG_CFR_W6 WWDG_CFR_W_6
14195
14196 #define WWDG_CFR_WDGTB_Pos (7U)
14197 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
14198 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
14199 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
14200 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
14201 /* Legacy defines */
14202 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
14203 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
14204
14205 #define WWDG_CFR_EWI_Pos (9U)
14206 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
14207 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
14208
14209 /******************* Bit definition for WWDG_SR register ********************/
14210 #define WWDG_SR_EWIF_Pos (0U)
14211 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
14212 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
14213
14214
14215 /******************************************************************************/
14216 /* */
14217 /* DBG */
14218 /* */
14219 /******************************************************************************/
14220 /******************** Bit definition for DBGMCU_IDCODE register *************/
14221 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
14222 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
14223 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
14224 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
14225 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
14226 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
14227
14228 /******************** Bit definition for DBGMCU_CR register *****************/
14229 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
14230 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
14231 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
14232 #define DBGMCU_CR_DBG_STOP_Pos (1U)
14233 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
14234 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
14235 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
14236 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
14237 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
14238 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
14239 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
14240 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
14241
14242 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
14243 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
14244 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
14245 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
14246 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
14247
14248 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
14249 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
14250 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
14251 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
14252 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
14253 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
14254 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
14255 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
14256 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
14257 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
14258 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
14259 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
14260 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
14261 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
14262 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
14263 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
14264 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
14265 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
14266 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
14267 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
14268 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
14269 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
14270 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
14271 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
14272 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
14273 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
14274 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
14275 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
14276 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
14277 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
14278 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
14279 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
14280 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
14281 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
14282 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
14283 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
14284 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
14285 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
14286 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
14287 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
14288 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
14289 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
14290 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
14291 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
14292 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
14293 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
14294 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
14295 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
14296 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
14297 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
14298 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
14299 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
14300 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
14301 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
14302
14303 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
14304 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
14305 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
14306 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
14307 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
14308 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
14309 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
14310 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
14311 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
14312 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
14313 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
14314 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
14315 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14316 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
14317 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
14318 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14319
14320 /******************************************************************************/
14321 /* */
14322 /* Ethernet MAC Registers bits definitions */
14323 /* */
14324 /******************************************************************************/
14325 /* Bit definition for Ethernet MAC Control Register register */
14326 #define ETH_MACCR_WD_Pos (23U)
14327 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
14328 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
14329 #define ETH_MACCR_JD_Pos (22U)
14330 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
14331 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
14332 #define ETH_MACCR_IFG_Pos (17U)
14333 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
14334 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
14335 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
14336 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
14337 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
14338 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
14339 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
14340 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
14341 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
14342 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
14343 #define ETH_MACCR_CSD_Pos (16U)
14344 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
14345 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
14346 #define ETH_MACCR_FES_Pos (14U)
14347 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
14348 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
14349 #define ETH_MACCR_ROD_Pos (13U)
14350 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
14351 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
14352 #define ETH_MACCR_LM_Pos (12U)
14353 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
14354 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
14355 #define ETH_MACCR_DM_Pos (11U)
14356 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
14357 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
14358 #define ETH_MACCR_IPCO_Pos (10U)
14359 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
14360 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
14361 #define ETH_MACCR_RD_Pos (9U)
14362 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
14363 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
14364 #define ETH_MACCR_APCS_Pos (7U)
14365 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
14366 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
14367 #define ETH_MACCR_BL_Pos (5U)
14368 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
14369 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
14370 a transmission attempt during retries after a collision: 0 =< r <2^k */
14371 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
14372 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
14373 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
14374 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
14375 #define ETH_MACCR_DC_Pos (4U)
14376 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
14377 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
14378 #define ETH_MACCR_TE_Pos (3U)
14379 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
14380 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
14381 #define ETH_MACCR_RE_Pos (2U)
14382 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
14383 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
14384
14385 /* Bit definition for Ethernet MAC Frame Filter Register */
14386 #define ETH_MACFFR_RA_Pos (31U)
14387 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
14388 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
14389 #define ETH_MACFFR_HPF_Pos (10U)
14390 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
14391 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
14392 #define ETH_MACFFR_SAF_Pos (9U)
14393 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
14394 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
14395 #define ETH_MACFFR_SAIF_Pos (8U)
14396 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
14397 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
14398 #define ETH_MACFFR_PCF_Pos (6U)
14399 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
14400 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
14401 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
14402 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
14403 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
14404 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
14405 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
14406 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
14407 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
14408 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
14409 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
14410 #define ETH_MACFFR_BFD_Pos (5U)
14411 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
14412 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
14413 #define ETH_MACFFR_PAM_Pos (4U)
14414 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
14415 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
14416 #define ETH_MACFFR_DAIF_Pos (3U)
14417 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
14418 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
14419 #define ETH_MACFFR_HM_Pos (2U)
14420 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
14421 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
14422 #define ETH_MACFFR_HU_Pos (1U)
14423 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
14424 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
14425 #define ETH_MACFFR_PM_Pos (0U)
14426 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
14427 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
14428
14429 /* Bit definition for Ethernet MAC Hash Table High Register */
14430 #define ETH_MACHTHR_HTH_Pos (0U)
14431 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
14432 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
14433
14434 /* Bit definition for Ethernet MAC Hash Table Low Register */
14435 #define ETH_MACHTLR_HTL_Pos (0U)
14436 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
14437 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
14438
14439 /* Bit definition for Ethernet MAC MII Address Register */
14440 #define ETH_MACMIIAR_PA_Pos (11U)
14441 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
14442 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
14443 #define ETH_MACMIIAR_MR_Pos (6U)
14444 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
14445 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
14446 #define ETH_MACMIIAR_CR_Pos (2U)
14447 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
14448 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
14449 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
14450 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
14451 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
14452 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
14453 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
14454 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
14455 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
14456 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
14457 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
14458 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
14459 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
14460 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
14461 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
14462 #define ETH_MACMIIAR_MW_Pos (1U)
14463 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
14464 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
14465 #define ETH_MACMIIAR_MB_Pos (0U)
14466 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
14467 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
14468
14469 /* Bit definition for Ethernet MAC MII Data Register */
14470 #define ETH_MACMIIDR_MD_Pos (0U)
14471 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
14472 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
14473
14474 /* Bit definition for Ethernet MAC Flow Control Register */
14475 #define ETH_MACFCR_PT_Pos (16U)
14476 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
14477 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
14478 #define ETH_MACFCR_ZQPD_Pos (7U)
14479 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
14480 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
14481 #define ETH_MACFCR_PLT_Pos (4U)
14482 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
14483 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
14484 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
14485 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
14486 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
14487 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
14488 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
14489 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
14490 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
14491 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
14492 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
14493 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
14494 #define ETH_MACFCR_UPFD_Pos (3U)
14495 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
14496 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
14497 #define ETH_MACFCR_RFCE_Pos (2U)
14498 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
14499 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
14500 #define ETH_MACFCR_TFCE_Pos (1U)
14501 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
14502 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
14503 #define ETH_MACFCR_FCBBPA_Pos (0U)
14504 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
14505 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
14506
14507 /* Bit definition for Ethernet MAC VLAN Tag Register */
14508 #define ETH_MACVLANTR_VLANTC_Pos (16U)
14509 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
14510 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
14511 #define ETH_MACVLANTR_VLANTI_Pos (0U)
14512 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
14513 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
14514
14515 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
14516 #define ETH_MACRWUFFR_D_Pos (0U)
14517 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
14518 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
14519 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
14520 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
14521 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
14522 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
14523 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
14524 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
14525 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
14526 RSVD - Filter1 Command - RSVD - Filter0 Command
14527 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
14528 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
14529 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
14530
14531 /* Bit definition for Ethernet MAC PMT Control and Status Register */
14532 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
14533 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
14534 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
14535 #define ETH_MACPMTCSR_GU_Pos (9U)
14536 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
14537 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
14538 #define ETH_MACPMTCSR_WFR_Pos (6U)
14539 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
14540 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
14541 #define ETH_MACPMTCSR_MPR_Pos (5U)
14542 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
14543 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
14544 #define ETH_MACPMTCSR_WFE_Pos (2U)
14545 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
14546 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
14547 #define ETH_MACPMTCSR_MPE_Pos (1U)
14548 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
14549 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
14550 #define ETH_MACPMTCSR_PD_Pos (0U)
14551 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
14552 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
14553
14554 /* Bit definition for Ethernet MAC debug Register */
14555 #define ETH_MACDBGR_TFF_Pos (25U)
14556 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
14557 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
14558 #define ETH_MACDBGR_TFNE_Pos (24U)
14559 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
14560 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
14561 #define ETH_MACDBGR_TFWA_Pos (22U)
14562 #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
14563 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
14564 #define ETH_MACDBGR_TFRS_Pos (20U)
14565 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
14566 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
14567 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
14568 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
14569 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
14570 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
14571 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
14572 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
14573 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
14574 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
14575 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
14576 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
14577 #define ETH_MACDBGR_MTP_Pos (19U)
14578 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
14579 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
14580 #define ETH_MACDBGR_MTFCS_Pos (17U)
14581 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
14582 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
14583 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
14584 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
14585 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
14586 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
14587 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
14588 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
14589 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
14590 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
14591 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
14592 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
14593 #define ETH_MACDBGR_MMTEA_Pos (16U)
14594 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
14595 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
14596 #define ETH_MACDBGR_RFFL_Pos (8U)
14597 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
14598 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
14599 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
14600 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
14601 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
14602 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
14603 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
14604 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
14605 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
14606 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
14607 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
14608 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
14609 #define ETH_MACDBGR_RFRCS_Pos (5U)
14610 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
14611 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
14612 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
14613 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
14614 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
14615 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
14616 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
14617 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
14618 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
14619 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
14620 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
14621 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
14622 #define ETH_MACDBGR_RFWRA_Pos (4U)
14623 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
14624 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
14625 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
14626 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
14627 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
14628 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
14629 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
14630 #define ETH_MACDBGR_MMRPEA_Pos (0U)
14631 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
14632 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
14633
14634 /* Bit definition for Ethernet MAC Status Register */
14635 #define ETH_MACSR_TSTS_Pos (9U)
14636 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
14637 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
14638 #define ETH_MACSR_MMCTS_Pos (6U)
14639 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
14640 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
14641 #define ETH_MACSR_MMMCRS_Pos (5U)
14642 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
14643 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
14644 #define ETH_MACSR_MMCS_Pos (4U)
14645 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
14646 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
14647 #define ETH_MACSR_PMTS_Pos (3U)
14648 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
14649 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
14650
14651 /* Bit definition for Ethernet MAC Interrupt Mask Register */
14652 #define ETH_MACIMR_TSTIM_Pos (9U)
14653 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
14654 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
14655 #define ETH_MACIMR_PMTIM_Pos (3U)
14656 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
14657 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
14658
14659 /* Bit definition for Ethernet MAC Address0 High Register */
14660 #define ETH_MACA0HR_MACA0H_Pos (0U)
14661 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
14662 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
14663
14664 /* Bit definition for Ethernet MAC Address0 Low Register */
14665 #define ETH_MACA0LR_MACA0L_Pos (0U)
14666 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
14667 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
14668
14669 /* Bit definition for Ethernet MAC Address1 High Register */
14670 #define ETH_MACA1HR_AE_Pos (31U)
14671 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
14672 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
14673 #define ETH_MACA1HR_SA_Pos (30U)
14674 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
14675 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
14676 #define ETH_MACA1HR_MBC_Pos (24U)
14677 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
14678 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
14679 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14680 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14681 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14682 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14683 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14684 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
14685 #define ETH_MACA1HR_MACA1H_Pos (0U)
14686 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
14687 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
14688
14689 /* Bit definition for Ethernet MAC Address1 Low Register */
14690 #define ETH_MACA1LR_MACA1L_Pos (0U)
14691 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
14692 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
14693
14694 /* Bit definition for Ethernet MAC Address2 High Register */
14695 #define ETH_MACA2HR_AE_Pos (31U)
14696 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
14697 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
14698 #define ETH_MACA2HR_SA_Pos (30U)
14699 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
14700 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
14701 #define ETH_MACA2HR_MBC_Pos (24U)
14702 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
14703 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
14704 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14705 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14706 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14707 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14708 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14709 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
14710 #define ETH_MACA2HR_MACA2H_Pos (0U)
14711 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
14712 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
14713
14714 /* Bit definition for Ethernet MAC Address2 Low Register */
14715 #define ETH_MACA2LR_MACA2L_Pos (0U)
14716 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
14717 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
14718
14719 /* Bit definition for Ethernet MAC Address3 High Register */
14720 #define ETH_MACA3HR_AE_Pos (31U)
14721 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
14722 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
14723 #define ETH_MACA3HR_SA_Pos (30U)
14724 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
14725 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
14726 #define ETH_MACA3HR_MBC_Pos (24U)
14727 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
14728 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
14729 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14730 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14731 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14732 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14733 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14734 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
14735 #define ETH_MACA3HR_MACA3H_Pos (0U)
14736 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
14737 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
14738
14739 /* Bit definition for Ethernet MAC Address3 Low Register */
14740 #define ETH_MACA3LR_MACA3L_Pos (0U)
14741 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
14742 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
14743
14744 /******************************************************************************/
14745 /* Ethernet MMC Registers bits definition */
14746 /******************************************************************************/
14747
14748 /* Bit definition for Ethernet MMC Contol Register */
14749 #define ETH_MMCCR_MCFHP_Pos (5U)
14750 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
14751 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
14752 #define ETH_MMCCR_MCP_Pos (4U)
14753 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
14754 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
14755 #define ETH_MMCCR_MCF_Pos (3U)
14756 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
14757 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
14758 #define ETH_MMCCR_ROR_Pos (2U)
14759 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
14760 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
14761 #define ETH_MMCCR_CSR_Pos (1U)
14762 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
14763 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
14764 #define ETH_MMCCR_CR_Pos (0U)
14765 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
14766 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
14767
14768 /* Bit definition for Ethernet MMC Receive Interrupt Register */
14769 #define ETH_MMCRIR_RGUFS_Pos (17U)
14770 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
14771 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
14772 #define ETH_MMCRIR_RFAES_Pos (6U)
14773 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
14774 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
14775 #define ETH_MMCRIR_RFCES_Pos (5U)
14776 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
14777 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
14778
14779 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
14780 #define ETH_MMCTIR_TGFS_Pos (21U)
14781 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
14782 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
14783 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
14784 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
14785 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
14786 #define ETH_MMCTIR_TGFSCS_Pos (14U)
14787 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
14788 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
14789
14790 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
14791 #define ETH_MMCRIMR_RGUFM_Pos (17U)
14792 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
14793 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
14794 #define ETH_MMCRIMR_RFAEM_Pos (6U)
14795 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
14796 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
14797 #define ETH_MMCRIMR_RFCEM_Pos (5U)
14798 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
14799 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
14800
14801 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
14802 #define ETH_MMCTIMR_TGFM_Pos (21U)
14803 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
14804 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
14805 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
14806 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
14807 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
14808 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
14809 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
14810 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
14811
14812 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
14813 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
14814 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
14815 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
14816
14817 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
14818 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
14819 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
14820 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
14821
14822 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
14823 #define ETH_MMCTGFCR_TGFC_Pos (0U)
14824 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
14825 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
14826
14827 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
14828 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
14829 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
14830 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
14831
14832 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
14833 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
14834 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
14835 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
14836
14837 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
14838 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
14839 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
14840 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
14841
14842 /******************************************************************************/
14843 /* Ethernet PTP Registers bits definition */
14844 /******************************************************************************/
14845
14846 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
14847 #define ETH_PTPTSCR_TSCNT_Pos (16U)
14848 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
14849 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
14850 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
14851 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
14852 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
14853 #define ETH_PTPTSSR_TSSEME_Pos (14U)
14854 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
14855 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
14856 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
14857 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
14858 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
14859 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
14860 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
14861 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
14862 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
14863 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
14864 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
14865 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
14866 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
14867 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
14868 #define ETH_PTPTSSR_TSSSR_Pos (9U)
14869 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
14870 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
14871 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
14872 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
14873 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
14874
14875 #define ETH_PTPTSCR_TSARU_Pos (5U)
14876 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
14877 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
14878 #define ETH_PTPTSCR_TSITE_Pos (4U)
14879 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
14880 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
14881 #define ETH_PTPTSCR_TSSTU_Pos (3U)
14882 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
14883 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
14884 #define ETH_PTPTSCR_TSSTI_Pos (2U)
14885 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
14886 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
14887 #define ETH_PTPTSCR_TSFCU_Pos (1U)
14888 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
14889 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
14890 #define ETH_PTPTSCR_TSE_Pos (0U)
14891 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
14892 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
14893
14894 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
14895 #define ETH_PTPSSIR_STSSI_Pos (0U)
14896 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
14897 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
14898
14899 /* Bit definition for Ethernet PTP Time Stamp High Register */
14900 #define ETH_PTPTSHR_STS_Pos (0U)
14901 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
14902 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
14903
14904 /* Bit definition for Ethernet PTP Time Stamp Low Register */
14905 #define ETH_PTPTSLR_STPNS_Pos (31U)
14906 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
14907 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
14908 #define ETH_PTPTSLR_STSS_Pos (0U)
14909 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
14910 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
14911
14912 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
14913 #define ETH_PTPTSHUR_TSUS_Pos (0U)
14914 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
14915 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
14916
14917 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
14918 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
14919 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
14920 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
14921 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
14922 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
14923 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
14924
14925 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
14926 #define ETH_PTPTSAR_TSA_Pos (0U)
14927 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
14928 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
14929
14930 /* Bit definition for Ethernet PTP Target Time High Register */
14931 #define ETH_PTPTTHR_TTSH_Pos (0U)
14932 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
14933 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
14934
14935 /* Bit definition for Ethernet PTP Target Time Low Register */
14936 #define ETH_PTPTTLR_TTSL_Pos (0U)
14937 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
14938 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
14939
14940 /* Bit definition for Ethernet PTP Time Stamp Status Register */
14941 #define ETH_PTPTSSR_TSTTR_Pos (5U)
14942 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
14943 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
14944 #define ETH_PTPTSSR_TSSO_Pos (4U)
14945 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
14946 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
14947
14948 /******************************************************************************/
14949 /* Ethernet DMA Registers bits definition */
14950 /******************************************************************************/
14951
14952 /* Bit definition for Ethernet DMA Bus Mode Register */
14953 #define ETH_DMABMR_AAB_Pos (25U)
14954 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
14955 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
14956 #define ETH_DMABMR_FPM_Pos (24U)
14957 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
14958 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
14959 #define ETH_DMABMR_USP_Pos (23U)
14960 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
14961 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
14962 #define ETH_DMABMR_RDP_Pos (17U)
14963 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
14964 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
14965 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
14966 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
14967 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
14968 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
14969 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
14970 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
14971 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
14972 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
14973 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
14974 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
14975 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
14976 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
14977 #define ETH_DMABMR_FB_Pos (16U)
14978 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
14979 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
14980 #define ETH_DMABMR_RTPR_Pos (14U)
14981 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
14982 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
14983 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
14984 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
14985 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
14986 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
14987 #define ETH_DMABMR_PBL_Pos (8U)
14988 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
14989 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
14990 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
14991 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
14992 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
14993 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
14994 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
14995 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
14996 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
14997 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
14998 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
14999 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15000 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
15001 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
15002 #define ETH_DMABMR_EDE_Pos (7U)
15003 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
15004 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
15005 #define ETH_DMABMR_DSL_Pos (2U)
15006 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
15007 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
15008 #define ETH_DMABMR_DA_Pos (1U)
15009 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
15010 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
15011 #define ETH_DMABMR_SR_Pos (0U)
15012 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
15013 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
15014
15015 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
15016 #define ETH_DMATPDR_TPD_Pos (0U)
15017 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
15018 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
15019
15020 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
15021 #define ETH_DMARPDR_RPD_Pos (0U)
15022 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
15023 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
15024
15025 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
15026 #define ETH_DMARDLAR_SRL_Pos (0U)
15027 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
15028 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
15029
15030 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
15031 #define ETH_DMATDLAR_STL_Pos (0U)
15032 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
15033 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
15034
15035 /* Bit definition for Ethernet DMA Status Register */
15036 #define ETH_DMASR_TSTS_Pos (29U)
15037 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
15038 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
15039 #define ETH_DMASR_PMTS_Pos (28U)
15040 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
15041 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
15042 #define ETH_DMASR_MMCS_Pos (27U)
15043 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
15044 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
15045 #define ETH_DMASR_EBS_Pos (23U)
15046 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
15047 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
15048 /* combination with EBS[2:0] for GetFlagStatus function */
15049 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
15050 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
15051 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
15052 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
15053 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
15054 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
15055 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
15056 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
15057 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
15058 #define ETH_DMASR_TPS_Pos (20U)
15059 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
15060 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
15061 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
15062 #define ETH_DMASR_TPS_Fetching_Pos (20U)
15063 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
15064 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
15065 #define ETH_DMASR_TPS_Waiting_Pos (21U)
15066 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
15067 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
15068 #define ETH_DMASR_TPS_Reading_Pos (20U)
15069 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
15070 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
15071 #define ETH_DMASR_TPS_Suspended_Pos (21U)
15072 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
15073 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
15074 #define ETH_DMASR_TPS_Closing_Pos (20U)
15075 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
15076 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
15077 #define ETH_DMASR_RPS_Pos (17U)
15078 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
15079 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
15080 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
15081 #define ETH_DMASR_RPS_Fetching_Pos (17U)
15082 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
15083 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
15084 #define ETH_DMASR_RPS_Waiting_Pos (17U)
15085 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
15086 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
15087 #define ETH_DMASR_RPS_Suspended_Pos (19U)
15088 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
15089 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
15090 #define ETH_DMASR_RPS_Closing_Pos (17U)
15091 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
15092 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
15093 #define ETH_DMASR_RPS_Queuing_Pos (17U)
15094 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
15095 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
15096 #define ETH_DMASR_NIS_Pos (16U)
15097 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
15098 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
15099 #define ETH_DMASR_AIS_Pos (15U)
15100 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
15101 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
15102 #define ETH_DMASR_ERS_Pos (14U)
15103 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
15104 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
15105 #define ETH_DMASR_FBES_Pos (13U)
15106 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
15107 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
15108 #define ETH_DMASR_ETS_Pos (10U)
15109 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
15110 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
15111 #define ETH_DMASR_RWTS_Pos (9U)
15112 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
15113 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
15114 #define ETH_DMASR_RPSS_Pos (8U)
15115 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
15116 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
15117 #define ETH_DMASR_RBUS_Pos (7U)
15118 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
15119 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
15120 #define ETH_DMASR_RS_Pos (6U)
15121 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
15122 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
15123 #define ETH_DMASR_TUS_Pos (5U)
15124 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
15125 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
15126 #define ETH_DMASR_ROS_Pos (4U)
15127 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
15128 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
15129 #define ETH_DMASR_TJTS_Pos (3U)
15130 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
15131 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
15132 #define ETH_DMASR_TBUS_Pos (2U)
15133 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
15134 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
15135 #define ETH_DMASR_TPSS_Pos (1U)
15136 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
15137 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
15138 #define ETH_DMASR_TS_Pos (0U)
15139 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
15140 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
15141
15142 /* Bit definition for Ethernet DMA Operation Mode Register */
15143 #define ETH_DMAOMR_DTCEFD_Pos (26U)
15144 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
15145 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
15146 #define ETH_DMAOMR_RSF_Pos (25U)
15147 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
15148 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
15149 #define ETH_DMAOMR_DFRF_Pos (24U)
15150 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
15151 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
15152 #define ETH_DMAOMR_TSF_Pos (21U)
15153 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
15154 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
15155 #define ETH_DMAOMR_FTF_Pos (20U)
15156 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
15157 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
15158 #define ETH_DMAOMR_TTC_Pos (14U)
15159 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
15160 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
15161 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
15162 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
15163 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
15164 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
15165 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
15166 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
15167 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
15168 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
15169 #define ETH_DMAOMR_ST_Pos (13U)
15170 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
15171 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
15172 #define ETH_DMAOMR_FEF_Pos (7U)
15173 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
15174 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
15175 #define ETH_DMAOMR_FUGF_Pos (6U)
15176 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
15177 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
15178 #define ETH_DMAOMR_RTC_Pos (3U)
15179 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
15180 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
15181 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
15182 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
15183 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
15184 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
15185 #define ETH_DMAOMR_OSF_Pos (2U)
15186 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
15187 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
15188 #define ETH_DMAOMR_SR_Pos (1U)
15189 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
15190 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
15191
15192 /* Bit definition for Ethernet DMA Interrupt Enable Register */
15193 #define ETH_DMAIER_NISE_Pos (16U)
15194 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
15195 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
15196 #define ETH_DMAIER_AISE_Pos (15U)
15197 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
15198 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
15199 #define ETH_DMAIER_ERIE_Pos (14U)
15200 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
15201 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
15202 #define ETH_DMAIER_FBEIE_Pos (13U)
15203 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
15204 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
15205 #define ETH_DMAIER_ETIE_Pos (10U)
15206 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
15207 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
15208 #define ETH_DMAIER_RWTIE_Pos (9U)
15209 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
15210 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
15211 #define ETH_DMAIER_RPSIE_Pos (8U)
15212 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
15213 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
15214 #define ETH_DMAIER_RBUIE_Pos (7U)
15215 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
15216 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
15217 #define ETH_DMAIER_RIE_Pos (6U)
15218 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
15219 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
15220 #define ETH_DMAIER_TUIE_Pos (5U)
15221 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
15222 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
15223 #define ETH_DMAIER_ROIE_Pos (4U)
15224 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
15225 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
15226 #define ETH_DMAIER_TJTIE_Pos (3U)
15227 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
15228 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
15229 #define ETH_DMAIER_TBUIE_Pos (2U)
15230 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
15231 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
15232 #define ETH_DMAIER_TPSIE_Pos (1U)
15233 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
15234 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
15235 #define ETH_DMAIER_TIE_Pos (0U)
15236 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
15237 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
15238
15239 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
15240 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
15241 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
15242 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
15243 #define ETH_DMAMFBOCR_MFA_Pos (17U)
15244 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
15245 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
15246 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
15247 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
15248 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
15249 #define ETH_DMAMFBOCR_MFC_Pos (0U)
15250 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
15251 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
15252
15253 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
15254 #define ETH_DMACHTDR_HTDAP_Pos (0U)
15255 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
15256 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
15257
15258 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
15259 #define ETH_DMACHRDR_HRDAP_Pos (0U)
15260 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
15261 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
15262
15263 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
15264 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
15265 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
15266 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
15267
15268 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
15269 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
15270 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
15271 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
15272
15273 /******************************************************************************/
15274 /* */
15275 /* USB_OTG */
15276 /* */
15277 /******************************************************************************/
15278 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
15279 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
15280 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
15281 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
15282 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
15283 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
15284 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
15285 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
15286 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
15287 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
15288 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
15289 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
15290 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
15291 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
15292 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
15293 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
15294 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
15295 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
15296 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
15297 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
15298 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
15299 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
15300 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
15301 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
15302 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
15303 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
15304 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
15305 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
15306 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
15307 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
15308 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
15309
15310 /******************** Bit definition forUSB_OTG_HCFG register ********************/
15311
15312 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
15313 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
15314 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
15315 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
15316 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
15317 #define USB_OTG_HCFG_FSLSS_Pos (2U)
15318 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
15319 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
15320
15321 /******************** Bit definition for USB_OTG_DCFG register ********************/
15322
15323 #define USB_OTG_DCFG_DSPD_Pos (0U)
15324 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
15325 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
15326 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
15327 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
15328 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
15329 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
15330 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
15331
15332 #define USB_OTG_DCFG_DAD_Pos (4U)
15333 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
15334 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
15335 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
15336 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
15337 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
15338 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
15339 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
15340 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
15341 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
15342
15343 #define USB_OTG_DCFG_PFIVL_Pos (11U)
15344 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
15345 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
15346 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
15347 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
15348
15349 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
15350 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
15351 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
15352 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
15353 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
15354
15355 /******************** Bit definition for USB_OTG_PCGCR register ********************/
15356 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
15357 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
15358 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
15359 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
15360 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
15361 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
15362 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
15363 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
15364 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
15365
15366 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
15367 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
15368 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
15369 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
15370 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
15371 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
15372 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
15373 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
15374 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
15375 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
15376 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
15377 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
15378 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
15379 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
15380 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
15381 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
15382 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
15383 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
15384 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
15385
15386 /******************** Bit definition for USB_OTG_DCTL register ********************/
15387 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
15388 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
15389 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
15390 #define USB_OTG_DCTL_SDIS_Pos (1U)
15391 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
15392 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
15393 #define USB_OTG_DCTL_GINSTS_Pos (2U)
15394 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
15395 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
15396 #define USB_OTG_DCTL_GONSTS_Pos (3U)
15397 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
15398 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
15399
15400 #define USB_OTG_DCTL_TCTL_Pos (4U)
15401 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
15402 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
15403 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
15404 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
15405 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
15406 #define USB_OTG_DCTL_SGINAK_Pos (7U)
15407 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
15408 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
15409 #define USB_OTG_DCTL_CGINAK_Pos (8U)
15410 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
15411 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
15412 #define USB_OTG_DCTL_SGONAK_Pos (9U)
15413 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
15414 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
15415 #define USB_OTG_DCTL_CGONAK_Pos (10U)
15416 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
15417 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
15418 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
15419 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
15420 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
15421
15422 /******************** Bit definition for USB_OTG_HFIR register ********************/
15423 #define USB_OTG_HFIR_FRIVL_Pos (0U)
15424 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
15425 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
15426
15427 /******************** Bit definition for USB_OTG_HFNUM register ********************/
15428 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
15429 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
15430 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
15431 #define USB_OTG_HFNUM_FTREM_Pos (16U)
15432 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
15433 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
15434
15435 /******************** Bit definition for USB_OTG_DSTS register ********************/
15436 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
15437 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
15438 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
15439
15440 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
15441 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
15442 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
15443 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
15444 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
15445 #define USB_OTG_DSTS_EERR_Pos (3U)
15446 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
15447 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
15448 #define USB_OTG_DSTS_FNSOF_Pos (8U)
15449 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
15450 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
15451
15452 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
15453 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
15454 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
15455 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
15456 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
15457 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
15458 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
15459 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
15460 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
15461 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
15462 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
15463 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
15464 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
15465 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
15466 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
15467 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
15468 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
15469 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
15470 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
15471 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
15472 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
15473
15474 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
15475
15476 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
15477 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
15478 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
15479 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
15480 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
15481 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
15482 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
15483 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
15484 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
15485 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
15486 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
15487 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
15488 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
15489 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
15490 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
15491 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
15492 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
15493 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
15494 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
15495 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
15496 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
15497 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
15498 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
15499 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
15500 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
15501 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
15502 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
15503 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
15504 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
15505 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
15506 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
15507 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
15508 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
15509 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
15510 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
15511 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
15512 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
15513 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
15514 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
15515 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
15516 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
15517 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
15518 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
15519 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
15520 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
15521 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
15522 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
15523 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
15524 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
15525 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
15526 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
15527 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
15528 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
15529 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
15530 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
15531 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
15532 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
15533 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
15534 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
15535 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
15536 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
15537
15538 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
15539 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
15540 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
15541 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
15542 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
15543 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
15544 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
15545 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
15546 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
15547 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
15548 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
15549 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
15550 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
15551 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
15552 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
15553 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
15554
15555
15556 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
15557 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
15558 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
15559 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
15560 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
15561 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
15562 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
15563 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
15564 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
15565 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
15566 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
15567 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
15568 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
15569 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
15570
15571 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
15572 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
15573 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
15574 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
15575 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
15576 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
15577 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
15578 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
15579 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
15580 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
15581 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
15582 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
15583 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
15584 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
15585 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
15586 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
15587 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
15588 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
15589 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
15590 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
15591 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
15592 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
15593 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
15594 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
15595 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
15596
15597 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
15598 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
15599 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
15600 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
15601 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
15602 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
15603 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
15604 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
15605 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
15606 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
15607 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
15608 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
15609 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
15610 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
15611 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
15612
15613 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
15614 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
15615 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
15616 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
15617 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
15618 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
15619 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
15620 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
15621 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
15622 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
15623 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
15624
15625 /******************** Bit definition for USB_OTG_HAINT register ********************/
15626 #define USB_OTG_HAINT_HAINT_Pos (0U)
15627 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
15628 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
15629
15630 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
15631 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
15632 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
15633 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
15634 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
15635 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
15636 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
15637 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
15638 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
15639 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
15640 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
15641 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
15642 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
15643 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
15644 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
15645 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
15646 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
15647 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
15648 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
15649 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
15650 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
15651 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
15652
15653 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
15654 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
15655 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
15656 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
15657 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
15658 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
15659 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
15660 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
15661 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
15662 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
15663 #define USB_OTG_GINTSTS_SOF_Pos (3U)
15664 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
15665 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
15666 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
15667 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
15668 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
15669 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
15670 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
15671 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
15672 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
15673 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
15674 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
15675 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
15676 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
15677 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
15678 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
15679 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
15680 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
15681 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
15682 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
15683 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
15684 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
15685 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
15686 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
15687 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
15688 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
15689 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
15690 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
15691 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
15692 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
15693 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
15694 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
15695 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
15696 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
15697 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
15698 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
15699 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
15700 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
15701 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
15702 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
15703 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
15704 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
15705 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
15706 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
15707 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
15708 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
15709 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
15710 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
15711 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
15712 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
15713 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
15714 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
15715 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
15716 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
15717 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
15718 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
15719 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
15720 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
15721 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
15722 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
15723 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
15724 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
15725 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
15726 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
15727 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
15728 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
15729 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
15730 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
15731 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
15732
15733 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
15734 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
15735 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
15736 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
15737 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
15738 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
15739 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
15740 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
15741 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
15742 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
15743 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
15744 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
15745 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
15746 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
15747 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
15748 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
15749 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
15750 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
15751 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
15752 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
15753 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
15754 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
15755 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
15756 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
15757 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
15758 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
15759 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
15760 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
15761 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
15762 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
15763 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
15764 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
15765 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
15766 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
15767 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
15768 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
15769 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
15770 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
15771 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
15772 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
15773 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
15774 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
15775 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
15776 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
15777 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
15778 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
15779 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
15780 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
15781 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
15782 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
15783 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
15784 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
15785 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
15786 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
15787 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
15788 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
15789 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
15790 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
15791 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
15792 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
15793 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
15794 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
15795 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
15796 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
15797 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
15798 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
15799 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
15800 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
15801 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
15802 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
15803 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
15804 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
15805 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
15806 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
15807 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
15808 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
15809 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
15810 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
15811 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
15812
15813 /******************** Bit definition for USB_OTG_DAINT register ********************/
15814 #define USB_OTG_DAINT_IEPINT_Pos (0U)
15815 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
15816 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
15817 #define USB_OTG_DAINT_OEPINT_Pos (16U)
15818 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
15819 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
15820
15821 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
15822 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
15823 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
15824 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
15825
15826 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
15827 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
15828 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
15829 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
15830 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
15831 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
15832 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
15833 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
15834 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
15835 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
15836 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
15837 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
15838 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
15839
15840 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
15841 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
15842 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
15843 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
15844 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
15845 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
15846 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
15847
15848 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
15849 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
15850 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
15851 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
15852
15853 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
15854 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
15855 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
15856 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
15857
15858 /******************** Bit definition for OTG register ********************/
15859 #define USB_OTG_NPTXFSA_Pos (0U)
15860 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
15861 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
15862 #define USB_OTG_NPTXFD_Pos (16U)
15863 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
15864 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
15865 #define USB_OTG_TX0FSA_Pos (0U)
15866 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
15867 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
15868 #define USB_OTG_TX0FD_Pos (16U)
15869 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
15870 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
15871
15872 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
15873 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
15874 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
15875 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
15876
15877 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
15878 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
15879 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
15880 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
15881
15882 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
15883 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
15884 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
15885 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
15886 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
15887 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
15888 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
15889 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
15890 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
15891 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
15892 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
15893
15894 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
15895 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
15896 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
15897 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
15898 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
15899 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
15900 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
15901 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
15902 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
15903 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
15904
15905 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
15906 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
15907 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
15908 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
15909 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
15910 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
15911 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
15912
15913 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
15914 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
15915 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
15916 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
15917 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
15918 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
15919 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
15920 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
15921 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
15922 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
15923 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
15924 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
15925 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
15926 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
15927 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
15928
15929 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
15930 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
15931 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
15932 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
15933 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
15934 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
15935 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
15936 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
15937 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
15938 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
15939 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
15940 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
15941 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
15942 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
15943 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
15944
15945 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
15946 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
15947 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
15948 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
15949
15950 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
15951 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
15952 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
15953 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
15954 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
15955 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
15956 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
15957
15958 /******************** Bit definition for USB_OTG_GCCFG register ********************/
15959 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
15960 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
15961 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
15962 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
15963 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
15964 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
15965 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
15966 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
15967 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
15968 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
15969 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
15970 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
15971 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
15972 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
15973 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
15974 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
15975 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
15976 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
15977
15978 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
15979 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
15980 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
15981 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
15982 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
15983 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
15984 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
15985
15986 /******************** Bit definition for USB_OTG_CID register ********************/
15987 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
15988 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
15989 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
15990
15991 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
15992 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
15993 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
15994 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
15995 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
15996 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
15997 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
15998 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
15999 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
16000 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
16001 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
16002 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
16003 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
16004 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
16005 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
16006 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
16007 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
16008 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
16009 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
16010 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
16011 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
16012 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
16013 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
16014 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
16015 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
16016 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
16017 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
16018 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
16019
16020 /******************** Bit definition for USB_OTG_HPRT register ********************/
16021 #define USB_OTG_HPRT_PCSTS_Pos (0U)
16022 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
16023 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
16024 #define USB_OTG_HPRT_PCDET_Pos (1U)
16025 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
16026 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
16027 #define USB_OTG_HPRT_PENA_Pos (2U)
16028 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
16029 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
16030 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
16031 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
16032 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
16033 #define USB_OTG_HPRT_POCA_Pos (4U)
16034 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
16035 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
16036 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
16037 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
16038 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
16039 #define USB_OTG_HPRT_PRES_Pos (6U)
16040 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
16041 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
16042 #define USB_OTG_HPRT_PSUSP_Pos (7U)
16043 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
16044 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
16045 #define USB_OTG_HPRT_PRST_Pos (8U)
16046 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
16047 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
16048
16049 #define USB_OTG_HPRT_PLSTS_Pos (10U)
16050 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
16051 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
16052 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
16053 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
16054 #define USB_OTG_HPRT_PPWR_Pos (12U)
16055 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
16056 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
16057
16058 #define USB_OTG_HPRT_PTCTL_Pos (13U)
16059 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
16060 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
16061 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
16062 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
16063 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
16064 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
16065
16066 #define USB_OTG_HPRT_PSPD_Pos (17U)
16067 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
16068 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
16069 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
16070 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
16071
16072 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
16073 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
16074 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
16075 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
16076 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
16077 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
16078 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
16079 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
16080 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
16081 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
16082 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
16083 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
16084 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
16085 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
16086 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
16087 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
16088 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
16089 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
16090 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
16091 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
16092 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
16093 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
16094 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
16095 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
16096 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
16097 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
16098 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
16099 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
16100 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
16101 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
16102 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
16103 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
16104 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
16105 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
16106
16107 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
16108 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
16109 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
16110 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
16111 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
16112 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
16113 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
16114
16115 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
16116 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
16117 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
16118 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
16119 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
16120 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
16121 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
16122 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
16123 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
16124 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
16125 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
16126 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
16127 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
16128
16129 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
16130 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
16131 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
16132 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
16133 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
16134 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
16135 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
16136 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
16137
16138 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
16139 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
16140 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
16141 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
16142 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
16143 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
16144 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
16145 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
16146 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
16147 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
16148 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
16149 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
16150 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
16151 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
16152 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
16153 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
16154 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
16155 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
16156 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
16157 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
16158 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
16159 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
16160 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
16161 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
16162 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
16163
16164 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
16165 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
16166 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
16167 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
16168
16169 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
16170 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
16171 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
16172 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
16173 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
16174 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
16175 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
16176 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
16177 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
16178 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
16179 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
16180 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
16181 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
16182
16183 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
16184 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
16185 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
16186 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
16187 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
16188
16189 #define USB_OTG_HCCHAR_MC_Pos (20U)
16190 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
16191 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
16192 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
16193 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
16194
16195 #define USB_OTG_HCCHAR_DAD_Pos (22U)
16196 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
16197 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
16198 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
16199 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
16200 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
16201 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
16202 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
16203 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
16204 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
16205 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
16206 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
16207 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
16208 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
16209 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
16210 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
16211 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
16212 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
16213 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
16214
16215 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
16216
16217 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
16218 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
16219 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
16220 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
16221 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
16222 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
16223 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
16224 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
16225 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
16226 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
16227
16228 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
16229 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
16230 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
16231 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
16232 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
16233 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
16234 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
16235 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
16236 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
16237 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
16238
16239 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
16240 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
16241 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
16242 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
16243 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
16244 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
16245 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
16246 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
16247 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
16248 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
16249 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
16250
16251 /******************** Bit definition for USB_OTG_HCINT register ********************/
16252 #define USB_OTG_HCINT_XFRC_Pos (0U)
16253 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
16254 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
16255 #define USB_OTG_HCINT_CHH_Pos (1U)
16256 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
16257 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
16258 #define USB_OTG_HCINT_AHBERR_Pos (2U)
16259 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
16260 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
16261 #define USB_OTG_HCINT_STALL_Pos (3U)
16262 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
16263 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
16264 #define USB_OTG_HCINT_NAK_Pos (4U)
16265 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
16266 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
16267 #define USB_OTG_HCINT_ACK_Pos (5U)
16268 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
16269 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
16270 #define USB_OTG_HCINT_NYET_Pos (6U)
16271 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
16272 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
16273 #define USB_OTG_HCINT_TXERR_Pos (7U)
16274 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
16275 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
16276 #define USB_OTG_HCINT_BBERR_Pos (8U)
16277 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
16278 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
16279 #define USB_OTG_HCINT_FRMOR_Pos (9U)
16280 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
16281 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
16282 #define USB_OTG_HCINT_DTERR_Pos (10U)
16283 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
16284 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
16285
16286 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
16287 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
16288 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
16289 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
16290 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
16291 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
16292 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
16293 #define USB_OTG_DIEPINT_TOC_Pos (3U)
16294 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
16295 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
16296 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
16297 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
16298 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
16299 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
16300 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
16301 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
16302 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
16303 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
16304 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
16305 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
16306 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
16307 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
16308 #define USB_OTG_DIEPINT_BNA_Pos (9U)
16309 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
16310 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
16311 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
16312 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
16313 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
16314 #define USB_OTG_DIEPINT_BERR_Pos (12U)
16315 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
16316 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
16317 #define USB_OTG_DIEPINT_NAK_Pos (13U)
16318 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
16319 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
16320
16321 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
16322 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
16323 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
16324 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
16325 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
16326 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
16327 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
16328 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
16329 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
16330 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
16331 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
16332 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
16333 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
16334 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
16335 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
16336 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
16337 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
16338 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
16339 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
16340 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
16341 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
16342 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
16343 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
16344 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
16345 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
16346 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
16347 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
16348 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
16349 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
16350 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
16351 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
16352 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
16353 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
16354 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
16355
16356 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
16357
16358 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
16359 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16360 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
16361 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
16362 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16363 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
16364 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
16365 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
16366 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
16367 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
16368 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
16369 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16370 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
16371 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
16372 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16373 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
16374 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
16375 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
16376 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
16377 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
16378 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
16379 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
16380 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
16381 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
16382
16383 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
16384 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
16385 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
16386 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
16387
16388 /******************** Bit definition for USB_OTG_HCDMA register ********************/
16389 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
16390 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
16391 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
16392
16393 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
16394 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
16395 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
16396 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
16397
16398 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
16399 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
16400 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
16401 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
16402 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
16403 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
16404 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
16405
16406 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
16407
16408 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
16409 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
16410 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
16411 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
16412 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
16413 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
16414 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
16415 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
16416 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
16417 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
16418 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
16419 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
16420 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
16421 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
16422 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
16423 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
16424 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
16425 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
16426 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
16427 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
16428 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
16429 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
16430 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
16431 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
16432 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
16433 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
16434 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
16435 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
16436 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
16437 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
16438 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
16439 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
16440 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
16441 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
16442 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
16443 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
16444 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
16445 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
16446
16447 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
16448 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
16449 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
16450 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
16451 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
16452 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
16453 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
16454 #define USB_OTG_DOEPINT_STUP_Pos (3U)
16455 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
16456 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
16457 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
16458 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
16459 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
16460 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
16461 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
16462 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
16463 #define USB_OTG_DOEPINT_NYET_Pos (14U)
16464 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
16465 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
16466
16467 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
16468
16469 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
16470 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16471 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
16472 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
16473 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16474 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
16475
16476 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
16477 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
16478 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
16479 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
16480 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
16481
16482 /******************** Bit definition for PCGCCTL register ********************/
16483 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
16484 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
16485 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
16486 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
16487 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
16488 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
16489 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
16490 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
16491 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
16492
16493 /* Legacy define */
16494 /******************** Bit definition for OTG register ********************/
16495 #define USB_OTG_CHNUM_Pos (0U)
16496 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
16497 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
16498 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
16499 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
16500 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
16501 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
16502 #define USB_OTG_BCNT_Pos (4U)
16503 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
16504 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
16505
16506 #define USB_OTG_DPID_Pos (15U)
16507 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
16508 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
16509 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
16510 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
16511
16512 #define USB_OTG_PKTSTS_Pos (17U)
16513 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
16514 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
16515 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
16516 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
16517 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
16518 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
16519
16520 #define USB_OTG_EPNUM_Pos (0U)
16521 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
16522 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
16523 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
16524 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
16525 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
16526 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
16527
16528 #define USB_OTG_FRMNUM_Pos (21U)
16529 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
16530 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
16531 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
16532 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
16533 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
16534 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
16535 /**
16536 * @}
16537 */
16538
16539 /**
16540 * @}
16541 */
16542
16543 /** @addtogroup Exported_macros
16544 * @{
16545 */
16546
16547 /******************************* ADC Instances ********************************/
16548 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
16549 ((INSTANCE) == ADC2) || \
16550 ((INSTANCE) == ADC3))
16551
16552 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
16553
16554 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
16555
16556 /******************************* CAN Instances ********************************/
16557 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
16558 ((INSTANCE) == CAN2))
16559 /******************************* CRC Instances ********************************/
16560 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
16561
16562 /******************************* DAC Instances ********************************/
16563 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
16564
16565 /******************************* DCMI Instances *******************************/
16566 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
16567
16568 /******************************* DMA2D Instances *******************************/
16569 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
16570
16571 /******************************** DMA Instances *******************************/
16572 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
16573 ((INSTANCE) == DMA1_Stream1) || \
16574 ((INSTANCE) == DMA1_Stream2) || \
16575 ((INSTANCE) == DMA1_Stream3) || \
16576 ((INSTANCE) == DMA1_Stream4) || \
16577 ((INSTANCE) == DMA1_Stream5) || \
16578 ((INSTANCE) == DMA1_Stream6) || \
16579 ((INSTANCE) == DMA1_Stream7) || \
16580 ((INSTANCE) == DMA2_Stream0) || \
16581 ((INSTANCE) == DMA2_Stream1) || \
16582 ((INSTANCE) == DMA2_Stream2) || \
16583 ((INSTANCE) == DMA2_Stream3) || \
16584 ((INSTANCE) == DMA2_Stream4) || \
16585 ((INSTANCE) == DMA2_Stream5) || \
16586 ((INSTANCE) == DMA2_Stream6) || \
16587 ((INSTANCE) == DMA2_Stream7))
16588
16589 /******************************* GPIO Instances *******************************/
16590 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
16591 ((INSTANCE) == GPIOB) || \
16592 ((INSTANCE) == GPIOC) || \
16593 ((INSTANCE) == GPIOD) || \
16594 ((INSTANCE) == GPIOE) || \
16595 ((INSTANCE) == GPIOF) || \
16596 ((INSTANCE) == GPIOG) || \
16597 ((INSTANCE) == GPIOH) || \
16598 ((INSTANCE) == GPIOI) || \
16599 ((INSTANCE) == GPIOJ) || \
16600 ((INSTANCE) == GPIOK))
16601
16602 /******************************** I2C Instances *******************************/
16603 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
16604 ((INSTANCE) == I2C2) || \
16605 ((INSTANCE) == I2C3))
16606
16607 /******************************* SMBUS Instances ******************************/
16608 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
16609
16610 /******************************** I2S Instances *******************************/
16611
16612 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
16613 ((INSTANCE) == SPI3))
16614
16615 /*************************** I2S Extended Instances ***************************/
16616 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
16617 ((INSTANCE) == I2S3ext))
16618 /* Legacy Defines */
16619 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
16620
16621 /******************************* RNG Instances ********************************/
16622 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
16623
16624 /****************************** RTC Instances *********************************/
16625 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
16626
16627 /******************************* SAI Instances ********************************/
16628 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
16629 ((PERIPH) == SAI1_Block_B))
16630 /* Legacy define */
16631
16632 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
16633
16634 /******************************** SPI Instances *******************************/
16635 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
16636 ((INSTANCE) == SPI2) || \
16637 ((INSTANCE) == SPI3) || \
16638 ((INSTANCE) == SPI4) || \
16639 ((INSTANCE) == SPI5) || \
16640 ((INSTANCE) == SPI6))
16641
16642
16643 /****************** TIM Instances : All supported instances *******************/
16644 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16645 ((INSTANCE) == TIM2) || \
16646 ((INSTANCE) == TIM3) || \
16647 ((INSTANCE) == TIM4) || \
16648 ((INSTANCE) == TIM5) || \
16649 ((INSTANCE) == TIM6) || \
16650 ((INSTANCE) == TIM7) || \
16651 ((INSTANCE) == TIM8) || \
16652 ((INSTANCE) == TIM9) || \
16653 ((INSTANCE) == TIM10)|| \
16654 ((INSTANCE) == TIM11)|| \
16655 ((INSTANCE) == TIM12)|| \
16656 ((INSTANCE) == TIM13)|| \
16657 ((INSTANCE) == TIM14))
16658
16659 /************* TIM Instances : at least 1 capture/compare channel *************/
16660 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16661 ((INSTANCE) == TIM2) || \
16662 ((INSTANCE) == TIM3) || \
16663 ((INSTANCE) == TIM4) || \
16664 ((INSTANCE) == TIM5) || \
16665 ((INSTANCE) == TIM8) || \
16666 ((INSTANCE) == TIM9) || \
16667 ((INSTANCE) == TIM10) || \
16668 ((INSTANCE) == TIM11) || \
16669 ((INSTANCE) == TIM12) || \
16670 ((INSTANCE) == TIM13) || \
16671 ((INSTANCE) == TIM14))
16672
16673 /************ TIM Instances : at least 2 capture/compare channels *************/
16674 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16675 ((INSTANCE) == TIM2) || \
16676 ((INSTANCE) == TIM3) || \
16677 ((INSTANCE) == TIM4) || \
16678 ((INSTANCE) == TIM5) || \
16679 ((INSTANCE) == TIM8) || \
16680 ((INSTANCE) == TIM9) || \
16681 ((INSTANCE) == TIM12))
16682
16683 /************ TIM Instances : at least 3 capture/compare channels *************/
16684 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16685 ((INSTANCE) == TIM2) || \
16686 ((INSTANCE) == TIM3) || \
16687 ((INSTANCE) == TIM4) || \
16688 ((INSTANCE) == TIM5) || \
16689 ((INSTANCE) == TIM8))
16690
16691 /************ TIM Instances : at least 4 capture/compare channels *************/
16692 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16693 ((INSTANCE) == TIM2) || \
16694 ((INSTANCE) == TIM3) || \
16695 ((INSTANCE) == TIM4) || \
16696 ((INSTANCE) == TIM5) || \
16697 ((INSTANCE) == TIM8))
16698
16699 /******************** TIM Instances : Advanced-control timers *****************/
16700 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16701 ((INSTANCE) == TIM8))
16702
16703 /******************* TIM Instances : Timer input XOR function *****************/
16704 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16705 ((INSTANCE) == TIM2) || \
16706 ((INSTANCE) == TIM3) || \
16707 ((INSTANCE) == TIM4) || \
16708 ((INSTANCE) == TIM5) || \
16709 ((INSTANCE) == TIM8))
16710
16711 /****************** TIM Instances : DMA requests generation (UDE) *************/
16712 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16713 ((INSTANCE) == TIM2) || \
16714 ((INSTANCE) == TIM3) || \
16715 ((INSTANCE) == TIM4) || \
16716 ((INSTANCE) == TIM5) || \
16717 ((INSTANCE) == TIM6) || \
16718 ((INSTANCE) == TIM7) || \
16719 ((INSTANCE) == TIM8))
16720
16721 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
16722 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16723 ((INSTANCE) == TIM2) || \
16724 ((INSTANCE) == TIM3) || \
16725 ((INSTANCE) == TIM4) || \
16726 ((INSTANCE) == TIM5) || \
16727 ((INSTANCE) == TIM8))
16728
16729 /************ TIM Instances : DMA requests generation (COMDE) *****************/
16730 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16731 ((INSTANCE) == TIM2) || \
16732 ((INSTANCE) == TIM3) || \
16733 ((INSTANCE) == TIM4) || \
16734 ((INSTANCE) == TIM5) || \
16735 ((INSTANCE) == TIM8))
16736
16737 /******************** TIM Instances : DMA burst feature ***********************/
16738 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16739 ((INSTANCE) == TIM2) || \
16740 ((INSTANCE) == TIM3) || \
16741 ((INSTANCE) == TIM4) || \
16742 ((INSTANCE) == TIM5) || \
16743 ((INSTANCE) == TIM8))
16744
16745 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
16746 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16747 ((INSTANCE) == TIM2) || \
16748 ((INSTANCE) == TIM3) || \
16749 ((INSTANCE) == TIM4) || \
16750 ((INSTANCE) == TIM5) || \
16751 ((INSTANCE) == TIM6) || \
16752 ((INSTANCE) == TIM7) || \
16753 ((INSTANCE) == TIM8))
16754
16755 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
16756 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16757 ((INSTANCE) == TIM2) || \
16758 ((INSTANCE) == TIM3) || \
16759 ((INSTANCE) == TIM4) || \
16760 ((INSTANCE) == TIM5) || \
16761 ((INSTANCE) == TIM8) || \
16762 ((INSTANCE) == TIM9) || \
16763 ((INSTANCE) == TIM12))
16764
16765 /********************** TIM Instances : 32 bit Counter ************************/
16766 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
16767 ((INSTANCE) == TIM5))
16768
16769 /***************** TIM Instances : external trigger input availabe ************/
16770 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16771 ((INSTANCE) == TIM2) || \
16772 ((INSTANCE) == TIM3) || \
16773 ((INSTANCE) == TIM4) || \
16774 ((INSTANCE) == TIM5) || \
16775 ((INSTANCE) == TIM8))
16776
16777 /****************** TIM Instances : remapping capability **********************/
16778 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
16779 ((INSTANCE) == TIM5) || \
16780 ((INSTANCE) == TIM11))
16781
16782 /******************* TIM Instances : output(s) available **********************/
16783 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
16784 ((((INSTANCE) == TIM1) && \
16785 (((CHANNEL) == TIM_CHANNEL_1) || \
16786 ((CHANNEL) == TIM_CHANNEL_2) || \
16787 ((CHANNEL) == TIM_CHANNEL_3) || \
16788 ((CHANNEL) == TIM_CHANNEL_4))) \
16789 || \
16790 (((INSTANCE) == TIM2) && \
16791 (((CHANNEL) == TIM_CHANNEL_1) || \
16792 ((CHANNEL) == TIM_CHANNEL_2) || \
16793 ((CHANNEL) == TIM_CHANNEL_3) || \
16794 ((CHANNEL) == TIM_CHANNEL_4))) \
16795 || \
16796 (((INSTANCE) == TIM3) && \
16797 (((CHANNEL) == TIM_CHANNEL_1) || \
16798 ((CHANNEL) == TIM_CHANNEL_2) || \
16799 ((CHANNEL) == TIM_CHANNEL_3) || \
16800 ((CHANNEL) == TIM_CHANNEL_4))) \
16801 || \
16802 (((INSTANCE) == TIM4) && \
16803 (((CHANNEL) == TIM_CHANNEL_1) || \
16804 ((CHANNEL) == TIM_CHANNEL_2) || \
16805 ((CHANNEL) == TIM_CHANNEL_3) || \
16806 ((CHANNEL) == TIM_CHANNEL_4))) \
16807 || \
16808 (((INSTANCE) == TIM5) && \
16809 (((CHANNEL) == TIM_CHANNEL_1) || \
16810 ((CHANNEL) == TIM_CHANNEL_2) || \
16811 ((CHANNEL) == TIM_CHANNEL_3) || \
16812 ((CHANNEL) == TIM_CHANNEL_4))) \
16813 || \
16814 (((INSTANCE) == TIM8) && \
16815 (((CHANNEL) == TIM_CHANNEL_1) || \
16816 ((CHANNEL) == TIM_CHANNEL_2) || \
16817 ((CHANNEL) == TIM_CHANNEL_3) || \
16818 ((CHANNEL) == TIM_CHANNEL_4))) \
16819 || \
16820 (((INSTANCE) == TIM9) && \
16821 (((CHANNEL) == TIM_CHANNEL_1) || \
16822 ((CHANNEL) == TIM_CHANNEL_2))) \
16823 || \
16824 (((INSTANCE) == TIM10) && \
16825 (((CHANNEL) == TIM_CHANNEL_1))) \
16826 || \
16827 (((INSTANCE) == TIM11) && \
16828 (((CHANNEL) == TIM_CHANNEL_1))) \
16829 || \
16830 (((INSTANCE) == TIM12) && \
16831 (((CHANNEL) == TIM_CHANNEL_1) || \
16832 ((CHANNEL) == TIM_CHANNEL_2))) \
16833 || \
16834 (((INSTANCE) == TIM13) && \
16835 (((CHANNEL) == TIM_CHANNEL_1))) \
16836 || \
16837 (((INSTANCE) == TIM14) && \
16838 (((CHANNEL) == TIM_CHANNEL_1))))
16839
16840 /************ TIM Instances : complementary output(s) available ***************/
16841 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
16842 ((((INSTANCE) == TIM1) && \
16843 (((CHANNEL) == TIM_CHANNEL_1) || \
16844 ((CHANNEL) == TIM_CHANNEL_2) || \
16845 ((CHANNEL) == TIM_CHANNEL_3))) \
16846 || \
16847 (((INSTANCE) == TIM8) && \
16848 (((CHANNEL) == TIM_CHANNEL_1) || \
16849 ((CHANNEL) == TIM_CHANNEL_2) || \
16850 ((CHANNEL) == TIM_CHANNEL_3))))
16851
16852 /****************** TIM Instances : supporting counting mode selection ********/
16853 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16854 ((INSTANCE) == TIM2) || \
16855 ((INSTANCE) == TIM3) || \
16856 ((INSTANCE) == TIM4) || \
16857 ((INSTANCE) == TIM5) || \
16858 ((INSTANCE) == TIM8))
16859
16860 /****************** TIM Instances : supporting clock division *****************/
16861 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16862 ((INSTANCE) == TIM2) || \
16863 ((INSTANCE) == TIM3) || \
16864 ((INSTANCE) == TIM4) || \
16865 ((INSTANCE) == TIM5) || \
16866 ((INSTANCE) == TIM8) || \
16867 ((INSTANCE) == TIM9) || \
16868 ((INSTANCE) == TIM10)|| \
16869 ((INSTANCE) == TIM11)|| \
16870 ((INSTANCE) == TIM12)|| \
16871 ((INSTANCE) == TIM13)|| \
16872 ((INSTANCE) == TIM14))
16873
16874 /****************** TIM Instances : supporting commutation event generation ***/
16875 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
16876 ((INSTANCE) == TIM8))
16877
16878
16879 /****************** TIM Instances : supporting OCxREF clear *******************/
16880 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16881 ((INSTANCE) == TIM2) || \
16882 ((INSTANCE) == TIM3) || \
16883 ((INSTANCE) == TIM4) || \
16884 ((INSTANCE) == TIM5) || \
16885 ((INSTANCE) == TIM8))
16886
16887 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
16888 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16889 ((INSTANCE) == TIM2) || \
16890 ((INSTANCE) == TIM3) || \
16891 ((INSTANCE) == TIM4) || \
16892 ((INSTANCE) == TIM5) || \
16893 ((INSTANCE) == TIM8) || \
16894 ((INSTANCE) == TIM9) || \
16895 ((INSTANCE) == TIM12))
16896
16897 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
16898 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16899 ((INSTANCE) == TIM2) || \
16900 ((INSTANCE) == TIM3) || \
16901 ((INSTANCE) == TIM4) || \
16902 ((INSTANCE) == TIM5) || \
16903 ((INSTANCE) == TIM8))
16904
16905 /****************** TIM Instances : supporting repetition counter *************/
16906 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16907 ((INSTANCE) == TIM8))
16908
16909 /****************** TIM Instances : supporting encoder interface **************/
16910 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16911 ((INSTANCE) == TIM2) || \
16912 ((INSTANCE) == TIM3) || \
16913 ((INSTANCE) == TIM4) || \
16914 ((INSTANCE) == TIM5) || \
16915 ((INSTANCE) == TIM8) || \
16916 ((INSTANCE) == TIM9) || \
16917 ((INSTANCE) == TIM12))
16918 /****************** TIM Instances : supporting Hall sensor interface **********/
16919 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16920 ((INSTANCE) == TIM2) || \
16921 ((INSTANCE) == TIM3) || \
16922 ((INSTANCE) == TIM4) || \
16923 ((INSTANCE) == TIM5) || \
16924 ((INSTANCE) == TIM8))
16925 /****************** TIM Instances : supporting the break function *************/
16926 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16927 ((INSTANCE) == TIM8))
16928
16929 /******************** USART Instances : Synchronous mode **********************/
16930 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16931 ((INSTANCE) == USART2) || \
16932 ((INSTANCE) == USART3) || \
16933 ((INSTANCE) == USART6))
16934
16935 /******************** UART Instances : Half-Duplex mode **********************/
16936 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16937 ((INSTANCE) == USART2) || \
16938 ((INSTANCE) == USART3) || \
16939 ((INSTANCE) == UART4) || \
16940 ((INSTANCE) == UART5) || \
16941 ((INSTANCE) == USART6) || \
16942 ((INSTANCE) == UART7) || \
16943 ((INSTANCE) == UART8))
16944
16945 /* Legacy defines */
16946 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
16947
16948 /****************** UART Instances : Hardware Flow control ********************/
16949 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16950 ((INSTANCE) == USART2) || \
16951 ((INSTANCE) == USART3) || \
16952 ((INSTANCE) == USART6))
16953 /******************** UART Instances : LIN mode **********************/
16954 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
16955
16956 /********************* UART Instances : Smart card mode ***********************/
16957 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16958 ((INSTANCE) == USART2) || \
16959 ((INSTANCE) == USART3) || \
16960 ((INSTANCE) == USART6))
16961
16962 /*********************** UART Instances : IRDA mode ***************************/
16963 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16964 ((INSTANCE) == USART2) || \
16965 ((INSTANCE) == USART3) || \
16966 ((INSTANCE) == UART4) || \
16967 ((INSTANCE) == UART5) || \
16968 ((INSTANCE) == USART6) || \
16969 ((INSTANCE) == UART7) || \
16970 ((INSTANCE) == UART8))
16971
16972 /*********************** PCD Instances ****************************************/
16973 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
16974 ((INSTANCE) == USB_OTG_HS))
16975
16976 /*********************** HCD Instances ****************************************/
16977 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
16978 ((INSTANCE) == USB_OTG_HS))
16979
16980 /****************************** SDIO Instances ********************************/
16981 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
16982
16983 /****************************** IWDG Instances ********************************/
16984 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
16985
16986 /****************************** WWDG Instances ********************************/
16987 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
16988
16989 /****************************** USB Exported Constants ************************/
16990 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
16991 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
16992 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
16993 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
16994
16995 /*
16996 * @brief Specific devices reset values definitions
16997 */
16998 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
16999 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
17000 #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
17001
17002 #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
17003 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
17004 #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
17005 #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
17006 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
17007 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
17008 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
17009 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
17010
17011 #define RCC_PLLN_MIN_VALUE 50U
17012 #define RCC_PLLN_MAX_VALUE 432U
17013
17014 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
17015 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
17016 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
17017 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
17018 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
17019
17020 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
17021 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
17022 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
17023 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
17024 #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
17025
17026 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
17027 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
17028 #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
17029
17030 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
17031 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
17032 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
17033 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
17034 /******************************************************************************/
17035 /* For a painless codes migration between the STM32F4xx device product */
17036 /* lines, the aliases defined below are put in place to overcome the */
17037 /* differences in the interrupt handlers and IRQn definitions. */
17038 /* No need to update developed interrupt code when moving across */
17039 /* product lines within the same STM32F4 Family */
17040 /******************************************************************************/
17041 /* Aliases for __IRQn */
17042 #define FSMC_IRQn FMC_IRQn
17043
17044 /* Aliases for __IRQHandler */
17045 #define FSMC_IRQHandler FMC_IRQHandler
17046
17047 /**
17048 * @}
17049 */
17050
17051 /**
17052 * @}
17053 */
17054
17055 /**
17056 * @}
17057 */
17058
17059 #ifdef __cplusplus
17060 }
17061 #endif /* __cplusplus */
17062
17063 #endif /* __STM32F437xx_H */
17064
17065
17066
17067 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/