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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f429xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - peripherals registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f429xx
47 * @{
48 */
49
50 #ifndef __STM32F429xx_H
51 #define __STM32F429xx_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #define __FPU_PRESENT 1U /*!< FPU present */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78 /**
79 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
87 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
88 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
89 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
91 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
92 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
93 /****** STM32 specific Interrupt Numbers **********************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
99 RCC_IRQn = 5, /*!< RCC global Interrupt */
100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
112 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
113 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
114 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
115 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
116 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
133 USART3_IRQn = 39, /*!< USART3 global Interrupt */
134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
137 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
138 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
139 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
140 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
141 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
142 FMC_IRQn = 48, /*!< FMC global Interrupt */
143 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
144 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
149 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
150 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
151 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
152 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
153 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
154 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
155 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
156 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
157 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
158 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
159 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
160 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
162 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
163 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
164 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
165 USART6_IRQn = 71, /*!< USART6 global interrupt */
166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
168 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
169 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
170 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
171 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
172 DCMI_IRQn = 78, /*!< DCMI global interrupt */
173 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
174 FPU_IRQn = 81, /*!< FPU global interrupt */
175 UART7_IRQn = 82, /*!< UART7 global interrupt */
176 UART8_IRQn = 83, /*!< UART8 global interrupt */
177 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
178 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
179 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
180 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
181 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
182 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
183 DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
184 } IRQn_Type;
185
186 /**
187 * @}
188 */
189
190 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
191 #include "system_stm32f4xx.h"
192 #include <stdint.h>
193
194 /** @addtogroup Peripheral_registers_structures
195 * @{
196 */
197
198 /**
199 * @brief Analog to Digital Converter
200 */
201
202 typedef struct
203 {
204 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
205 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
206 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
207 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
208 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
209 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
210 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
211 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
212 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
213 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
214 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
215 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
216 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
217 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
218 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
219 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
220 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
221 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
222 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
223 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
224 } ADC_TypeDef;
225
226 typedef struct
227 {
228 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
229 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
230 __IO uint32_t CDR; /*!< ADC common regular data register for dual
231 AND triple modes, Address offset: ADC1 base address + 0x308 */
232 } ADC_Common_TypeDef;
233
234
235 /**
236 * @brief Controller Area Network TxMailBox
237 */
238
239 typedef struct
240 {
241 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
242 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
243 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
244 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
245 } CAN_TxMailBox_TypeDef;
246
247 /**
248 * @brief Controller Area Network FIFOMailBox
249 */
250
251 typedef struct
252 {
253 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
254 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
255 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
256 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
257 } CAN_FIFOMailBox_TypeDef;
258
259 /**
260 * @brief Controller Area Network FilterRegister
261 */
262
263 typedef struct
264 {
265 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
266 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
267 } CAN_FilterRegister_TypeDef;
268
269 /**
270 * @brief Controller Area Network
271 */
272
273 typedef struct
274 {
275 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
276 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
277 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
278 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
279 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
280 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
281 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
282 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
283 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
284 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
285 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
286 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
287 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
288 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
289 uint32_t RESERVED2; /*!< Reserved, 0x208 */
290 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
291 uint32_t RESERVED3; /*!< Reserved, 0x210 */
292 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
293 uint32_t RESERVED4; /*!< Reserved, 0x218 */
294 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
295 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
296 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
297 } CAN_TypeDef;
298
299 /**
300 * @brief CRC calculation unit
301 */
302
303 typedef struct
304 {
305 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
306 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
307 uint8_t RESERVED0; /*!< Reserved, 0x05 */
308 uint16_t RESERVED1; /*!< Reserved, 0x06 */
309 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
310 } CRC_TypeDef;
311
312 /**
313 * @brief Digital to Analog Converter
314 */
315
316 typedef struct
317 {
318 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
319 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
320 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
321 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
322 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
323 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
324 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
325 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
326 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
327 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
328 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
329 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
330 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
331 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
332 } DAC_TypeDef;
333
334 /**
335 * @brief Debug MCU
336 */
337
338 typedef struct
339 {
340 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
341 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
342 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
343 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
344 }DBGMCU_TypeDef;
345
346 /**
347 * @brief DCMI
348 */
349
350 typedef struct
351 {
352 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
353 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
354 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
355 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
356 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
357 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
358 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
359 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
360 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
361 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
362 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
363 } DCMI_TypeDef;
364
365 /**
366 * @brief DMA Controller
367 */
368
369 typedef struct
370 {
371 __IO uint32_t CR; /*!< DMA stream x configuration register */
372 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
373 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
374 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
375 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
376 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
377 } DMA_Stream_TypeDef;
378
379 typedef struct
380 {
381 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
382 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
383 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
384 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
385 } DMA_TypeDef;
386
387 /**
388 * @brief DMA2D Controller
389 */
390
391 typedef struct
392 {
393 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
394 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
395 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
396 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
397 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
398 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
399 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
400 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
401 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
402 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
403 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
404 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
405 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
406 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
407 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
408 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
409 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
410 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
411 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
412 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
413 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
414 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
415 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
416 } DMA2D_TypeDef;
417
418 /**
419 * @brief Ethernet MAC
420 */
421
422 typedef struct
423 {
424 __IO uint32_t MACCR;
425 __IO uint32_t MACFFR;
426 __IO uint32_t MACHTHR;
427 __IO uint32_t MACHTLR;
428 __IO uint32_t MACMIIAR;
429 __IO uint32_t MACMIIDR;
430 __IO uint32_t MACFCR;
431 __IO uint32_t MACVLANTR; /* 8 */
432 uint32_t RESERVED0[2];
433 __IO uint32_t MACRWUFFR; /* 11 */
434 __IO uint32_t MACPMTCSR;
435 uint32_t RESERVED1;
436 __IO uint32_t MACDBGR;
437 __IO uint32_t MACSR; /* 15 */
438 __IO uint32_t MACIMR;
439 __IO uint32_t MACA0HR;
440 __IO uint32_t MACA0LR;
441 __IO uint32_t MACA1HR;
442 __IO uint32_t MACA1LR;
443 __IO uint32_t MACA2HR;
444 __IO uint32_t MACA2LR;
445 __IO uint32_t MACA3HR;
446 __IO uint32_t MACA3LR; /* 24 */
447 uint32_t RESERVED2[40];
448 __IO uint32_t MMCCR; /* 65 */
449 __IO uint32_t MMCRIR;
450 __IO uint32_t MMCTIR;
451 __IO uint32_t MMCRIMR;
452 __IO uint32_t MMCTIMR; /* 69 */
453 uint32_t RESERVED3[14];
454 __IO uint32_t MMCTGFSCCR; /* 84 */
455 __IO uint32_t MMCTGFMSCCR;
456 uint32_t RESERVED4[5];
457 __IO uint32_t MMCTGFCR;
458 uint32_t RESERVED5[10];
459 __IO uint32_t MMCRFCECR;
460 __IO uint32_t MMCRFAECR;
461 uint32_t RESERVED6[10];
462 __IO uint32_t MMCRGUFCR;
463 uint32_t RESERVED7[334];
464 __IO uint32_t PTPTSCR;
465 __IO uint32_t PTPSSIR;
466 __IO uint32_t PTPTSHR;
467 __IO uint32_t PTPTSLR;
468 __IO uint32_t PTPTSHUR;
469 __IO uint32_t PTPTSLUR;
470 __IO uint32_t PTPTSAR;
471 __IO uint32_t PTPTTHR;
472 __IO uint32_t PTPTTLR;
473 __IO uint32_t RESERVED8;
474 __IO uint32_t PTPTSSR;
475 uint32_t RESERVED9[565];
476 __IO uint32_t DMABMR;
477 __IO uint32_t DMATPDR;
478 __IO uint32_t DMARPDR;
479 __IO uint32_t DMARDLAR;
480 __IO uint32_t DMATDLAR;
481 __IO uint32_t DMASR;
482 __IO uint32_t DMAOMR;
483 __IO uint32_t DMAIER;
484 __IO uint32_t DMAMFBOCR;
485 __IO uint32_t DMARSWTR;
486 uint32_t RESERVED10[8];
487 __IO uint32_t DMACHTDR;
488 __IO uint32_t DMACHRDR;
489 __IO uint32_t DMACHTBAR;
490 __IO uint32_t DMACHRBAR;
491 } ETH_TypeDef;
492
493 /**
494 * @brief External Interrupt/Event Controller
495 */
496
497 typedef struct
498 {
499 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
500 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
501 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
502 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
503 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
504 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
505 } EXTI_TypeDef;
506
507 /**
508 * @brief FLASH Registers
509 */
510
511 typedef struct
512 {
513 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
514 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
515 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
516 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
517 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
518 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
519 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
520 } FLASH_TypeDef;
521
522 /**
523 * @brief Flexible Memory Controller
524 */
525
526 typedef struct
527 {
528 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
529 } FMC_Bank1_TypeDef;
530
531 /**
532 * @brief Flexible Memory Controller Bank1E
533 */
534
535 typedef struct
536 {
537 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
538 } FMC_Bank1E_TypeDef;
539 /**
540 * @brief Flexible Memory Controller Bank2
541 */
542
543 typedef struct
544 {
545 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
546 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
547 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
548 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
549 uint32_t RESERVED0; /*!< Reserved, 0x70 */
550 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
551 uint32_t RESERVED1; /*!< Reserved, 0x78 */
552 uint32_t RESERVED2; /*!< Reserved, 0x7C */
553 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
554 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
555 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
556 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
557 uint32_t RESERVED3; /*!< Reserved, 0x90 */
558 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
559 } FMC_Bank2_3_TypeDef;
560
561 /**
562 * @brief Flexible Memory Controller Bank4
563 */
564
565 typedef struct
566 {
567 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
568 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
569 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
570 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
571 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
572 } FMC_Bank4_TypeDef;
573
574 /**
575 * @brief Flexible Memory Controller Bank5_6
576 */
577
578 typedef struct
579 {
580 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
581 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
582 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
583 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
584 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
585 } FMC_Bank5_6_TypeDef;
586
587 /**
588 * @brief General Purpose I/O
589 */
590
591 typedef struct
592 {
593 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
594 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
595 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
596 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
597 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
598 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
599 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
600 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
601 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
602 } GPIO_TypeDef;
603
604 /**
605 * @brief System configuration controller
606 */
607
608 typedef struct
609 {
610 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
611 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
612 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
613 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
614 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
615 } SYSCFG_TypeDef;
616
617 /**
618 * @brief Inter-integrated Circuit Interface
619 */
620
621 typedef struct
622 {
623 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
624 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
625 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
626 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
627 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
628 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
629 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
630 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
631 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
632 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
633 } I2C_TypeDef;
634
635 /**
636 * @brief Independent WATCHDOG
637 */
638
639 typedef struct
640 {
641 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
642 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
643 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
644 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
645 } IWDG_TypeDef;
646
647 /**
648 * @brief LCD-TFT Display Controller
649 */
650
651 typedef struct
652 {
653 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
654 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
655 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
656 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
657 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
658 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
659 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
660 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
661 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
662 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
663 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
664 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
665 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
666 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
667 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
668 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
669 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
670 } LTDC_TypeDef;
671
672 /**
673 * @brief LCD-TFT Display layer x Controller
674 */
675
676 typedef struct
677 {
678 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
679 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
680 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
681 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
682 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
683 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
684 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
685 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
686 uint32_t RESERVED0[2]; /*!< Reserved */
687 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
688 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
689 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
690 uint32_t RESERVED1[3]; /*!< Reserved */
691 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
692 } LTDC_Layer_TypeDef;
693
694 /**
695 * @brief Power Control
696 */
697
698 typedef struct
699 {
700 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
701 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
702 } PWR_TypeDef;
703
704 /**
705 * @brief Reset and Clock Control
706 */
707
708 typedef struct
709 {
710 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
711 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
712 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
713 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
714 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
715 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
716 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
717 uint32_t RESERVED0; /*!< Reserved, 0x1C */
718 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
719 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
720 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
721 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
722 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
723 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
724 uint32_t RESERVED2; /*!< Reserved, 0x3C */
725 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
726 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
727 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
728 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
729 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
730 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
731 uint32_t RESERVED4; /*!< Reserved, 0x5C */
732 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
733 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
734 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
735 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
736 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
737 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
738 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
739 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
740 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
741 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
742 } RCC_TypeDef;
743
744 /**
745 * @brief Real-Time Clock
746 */
747
748 typedef struct
749 {
750 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
751 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
752 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
753 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
754 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
755 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
756 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
757 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
758 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
759 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
760 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
761 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
762 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
763 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
764 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
765 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
766 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
767 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
768 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
769 uint32_t RESERVED7; /*!< Reserved, 0x4C */
770 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
771 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
772 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
773 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
774 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
775 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
776 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
777 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
778 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
779 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
780 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
781 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
782 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
783 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
784 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
785 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
786 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
787 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
788 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
789 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
790 } RTC_TypeDef;
791
792 /**
793 * @brief Serial Audio Interface
794 */
795
796 typedef struct
797 {
798 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
799 } SAI_TypeDef;
800
801 typedef struct
802 {
803 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
804 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
805 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
806 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
807 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
808 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
809 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
810 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
811 } SAI_Block_TypeDef;
812
813 /**
814 * @brief SD host Interface
815 */
816
817 typedef struct
818 {
819 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
820 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
821 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
822 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
823 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
824 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
825 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
826 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
827 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
828 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
829 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
830 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
831 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
832 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
833 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
834 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
835 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
836 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
837 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
838 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
839 } SDIO_TypeDef;
840
841 /**
842 * @brief Serial Peripheral Interface
843 */
844
845 typedef struct
846 {
847 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
848 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
849 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
850 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
851 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
852 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
853 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
854 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
855 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
856 } SPI_TypeDef;
857
858
859 /**
860 * @brief TIM
861 */
862
863 typedef struct
864 {
865 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
866 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
867 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
868 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
869 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
870 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
871 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
872 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
873 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
874 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
875 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
876 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
877 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
878 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
879 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
880 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
881 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
882 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
883 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
884 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
885 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
886 } TIM_TypeDef;
887
888 /**
889 * @brief Universal Synchronous Asynchronous Receiver Transmitter
890 */
891
892 typedef struct
893 {
894 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
895 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
896 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
897 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
898 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
899 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
900 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
901 } USART_TypeDef;
902
903 /**
904 * @brief Window WATCHDOG
905 */
906
907 typedef struct
908 {
909 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
910 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
911 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
912 } WWDG_TypeDef;
913
914 /**
915 * @brief RNG
916 */
917
918 typedef struct
919 {
920 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
921 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
922 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
923 } RNG_TypeDef;
924
925 /**
926 * @brief USB_OTG_Core_Registers
927 */
928 typedef struct
929 {
930 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
931 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
932 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
933 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
934 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
935 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
936 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
937 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
938 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
939 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
940 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
941 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
942 uint32_t Reserved30[2]; /*!< Reserved 030h */
943 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
944 __IO uint32_t CID; /*!< User ID Register 03Ch */
945 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
946 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
947 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
948 } USB_OTG_GlobalTypeDef;
949
950 /**
951 * @brief USB_OTG_device_Registers
952 */
953 typedef struct
954 {
955 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
956 __IO uint32_t DCTL; /*!< dev Control Register 804h */
957 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
958 uint32_t Reserved0C; /*!< Reserved 80Ch */
959 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
960 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
961 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
962 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
963 uint32_t Reserved20; /*!< Reserved 820h */
964 uint32_t Reserved9; /*!< Reserved 824h */
965 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
966 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
967 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
968 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
969 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
970 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
971 uint32_t Reserved40; /*!< dedicated EP mask 840h */
972 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
973 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
974 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
975 } USB_OTG_DeviceTypeDef;
976
977 /**
978 * @brief USB_OTG_IN_Endpoint-Specific_Register
979 */
980 typedef struct
981 {
982 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
983 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
984 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
985 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
986 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
987 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
988 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
989 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
990 } USB_OTG_INEndpointTypeDef;
991
992 /**
993 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
994 */
995 typedef struct
996 {
997 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
998 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
999 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1000 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1001 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1002 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1003 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1004 } USB_OTG_OUTEndpointTypeDef;
1005
1006 /**
1007 * @brief USB_OTG_Host_Mode_Register_Structures
1008 */
1009 typedef struct
1010 {
1011 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1012 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1013 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1014 uint32_t Reserved40C; /*!< Reserved 40Ch */
1015 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1016 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1017 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1018 } USB_OTG_HostTypeDef;
1019
1020 /**
1021 * @brief USB_OTG_Host_Channel_Specific_Registers
1022 */
1023 typedef struct
1024 {
1025 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1026 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1027 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1028 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1029 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1030 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1031 uint32_t Reserved[2]; /*!< Reserved */
1032 } USB_OTG_HostChannelTypeDef;
1033
1034 /**
1035 * @}
1036 */
1037
1038 /** @addtogroup Peripheral_memory_map
1039 * @{
1040 */
1041 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
1042 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
1043 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
1044 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
1045 #define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
1046 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
1047 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
1048 #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
1049 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
1050 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
1051 #define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
1052 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
1053 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
1054 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
1055 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
1056 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
1057 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
1058
1059 /* Legacy defines */
1060 #define SRAM_BASE SRAM1_BASE
1061 #define SRAM_BB_BASE SRAM1_BB_BASE
1062
1063 /*!< Peripheral memory map */
1064 #define APB1PERIPH_BASE PERIPH_BASE
1065 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1066 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1067 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1068
1069 /*!< APB1 peripherals */
1070 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1071 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1072 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1073 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1074 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1075 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1076 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1077 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1078 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1079 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1080 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1081 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1082 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1083 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1084 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1085 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1086 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1087 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1088 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1089 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1090 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1091 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1092 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1093 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1094 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1095 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1096 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1097 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1098 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1099
1100 /*!< APB2 peripherals */
1101 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1102 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1103 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1104 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1105 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1106 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1107 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1108 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
1109 /* Legacy define */
1110 #define ADC_BASE ADC123_COMMON_BASE
1111 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1112 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1113 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1114 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1115 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1116 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1117 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1118 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1119 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1120 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1121 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1122 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1123 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1124 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1125 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1126 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1127
1128 /*!< AHB1 peripherals */
1129 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1130 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1131 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1132 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1133 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1134 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1135 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1136 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1137 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1138 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1139 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1140 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1141 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1142 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1143 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1144 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1145 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1146 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1147 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1148 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1149 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1150 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1151 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1152 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1153 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1154 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1155 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1156 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1157 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1158 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1159 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1160 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1161 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1162 #define ETH_MAC_BASE (ETH_BASE)
1163 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1164 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1165 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1166 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1167
1168 /*!< AHB2 peripherals */
1169 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1170 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1171
1172 /*!< FMC Bankx registers base address */
1173 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1174 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1175 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
1176 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
1177 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1178
1179
1180 /*!< Debug MCU registers base address */
1181 #define DBGMCU_BASE 0xE0042000U
1182 /*!< USB registers base address */
1183 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1184 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1185
1186 #define USB_OTG_GLOBAL_BASE 0x000U
1187 #define USB_OTG_DEVICE_BASE 0x800U
1188 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1189 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1190 #define USB_OTG_EP_REG_SIZE 0x20U
1191 #define USB_OTG_HOST_BASE 0x400U
1192 #define USB_OTG_HOST_PORT_BASE 0x440U
1193 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1194 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1195 #define USB_OTG_PCGCCTL_BASE 0xE00U
1196 #define USB_OTG_FIFO_BASE 0x1000U
1197 #define USB_OTG_FIFO_SIZE 0x1000U
1198
1199 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
1200 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
1201 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1202 /**
1203 * @}
1204 */
1205
1206 /** @addtogroup Peripheral_declaration
1207 * @{
1208 */
1209 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1210 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1211 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1212 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1213 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1214 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1215 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1216 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1217 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1218 #define RTC ((RTC_TypeDef *) RTC_BASE)
1219 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1220 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1221 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1222 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1223 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1224 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1225 #define USART2 ((USART_TypeDef *) USART2_BASE)
1226 #define USART3 ((USART_TypeDef *) USART3_BASE)
1227 #define UART4 ((USART_TypeDef *) UART4_BASE)
1228 #define UART5 ((USART_TypeDef *) UART5_BASE)
1229 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1230 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1231 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1232 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1233 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1234 #define PWR ((PWR_TypeDef *) PWR_BASE)
1235 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1236 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1237 #define UART7 ((USART_TypeDef *) UART7_BASE)
1238 #define UART8 ((USART_TypeDef *) UART8_BASE)
1239 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1240 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1241 #define USART1 ((USART_TypeDef *) USART1_BASE)
1242 #define USART6 ((USART_TypeDef *) USART6_BASE)
1243 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1244 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1245 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1246 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1247 /* Legacy define */
1248 #define ADC ADC123_COMMON
1249 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1250 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1251 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1252 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1253 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1254 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1255 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1256 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1257 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1258 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1259 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1260 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1261 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1262 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1263 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1264 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1265 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1266 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1267 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1268 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1269 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1270 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1271 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1272 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1273 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1274 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1275 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1276 #define CRC ((CRC_TypeDef *) CRC_BASE)
1277 #define RCC ((RCC_TypeDef *) RCC_BASE)
1278 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1279 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1280 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1281 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1282 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1283 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1284 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1285 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1286 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1287 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1288 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1289 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1290 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1291 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1292 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1293 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1294 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1295 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1296 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1297 #define ETH ((ETH_TypeDef *) ETH_BASE)
1298 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1299 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1300 #define RNG ((RNG_TypeDef *) RNG_BASE)
1301 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1302 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1303 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1304 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1305 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1306 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1307 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1308 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1309
1310 /**
1311 * @}
1312 */
1313
1314 /** @addtogroup Exported_constants
1315 * @{
1316 */
1317
1318 /** @addtogroup Peripheral_Registers_Bits_Definition
1319 * @{
1320 */
1321
1322 /******************************************************************************/
1323 /* Peripheral Registers_Bits_Definition */
1324 /******************************************************************************/
1325
1326 /******************************************************************************/
1327 /* */
1328 /* Analog to Digital Converter */
1329 /* */
1330 /******************************************************************************/
1331 /*
1332 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1333 */
1334 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
1335
1336 /******************** Bit definition for ADC_SR register ********************/
1337 #define ADC_SR_AWD_Pos (0U)
1338 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1339 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1340 #define ADC_SR_EOC_Pos (1U)
1341 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1342 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1343 #define ADC_SR_JEOC_Pos (2U)
1344 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1345 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1346 #define ADC_SR_JSTRT_Pos (3U)
1347 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1348 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1349 #define ADC_SR_STRT_Pos (4U)
1350 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1351 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1352 #define ADC_SR_OVR_Pos (5U)
1353 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1354 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1355
1356 /******************* Bit definition for ADC_CR1 register ********************/
1357 #define ADC_CR1_AWDCH_Pos (0U)
1358 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1359 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1360 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1361 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1362 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1363 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1364 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1365 #define ADC_CR1_EOCIE_Pos (5U)
1366 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1367 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1368 #define ADC_CR1_AWDIE_Pos (6U)
1369 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1370 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1371 #define ADC_CR1_JEOCIE_Pos (7U)
1372 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1373 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1374 #define ADC_CR1_SCAN_Pos (8U)
1375 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1376 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1377 #define ADC_CR1_AWDSGL_Pos (9U)
1378 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1379 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1380 #define ADC_CR1_JAUTO_Pos (10U)
1381 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1382 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1383 #define ADC_CR1_DISCEN_Pos (11U)
1384 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1385 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1386 #define ADC_CR1_JDISCEN_Pos (12U)
1387 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1388 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1389 #define ADC_CR1_DISCNUM_Pos (13U)
1390 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1391 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1392 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1393 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1394 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1395 #define ADC_CR1_JAWDEN_Pos (22U)
1396 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1397 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1398 #define ADC_CR1_AWDEN_Pos (23U)
1399 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1400 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1401 #define ADC_CR1_RES_Pos (24U)
1402 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1403 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1404 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1405 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1406 #define ADC_CR1_OVRIE_Pos (26U)
1407 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1408 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1409
1410 /******************* Bit definition for ADC_CR2 register ********************/
1411 #define ADC_CR2_ADON_Pos (0U)
1412 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1413 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1414 #define ADC_CR2_CONT_Pos (1U)
1415 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1416 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1417 #define ADC_CR2_DMA_Pos (8U)
1418 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1419 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1420 #define ADC_CR2_DDS_Pos (9U)
1421 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1422 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1423 #define ADC_CR2_EOCS_Pos (10U)
1424 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1425 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1426 #define ADC_CR2_ALIGN_Pos (11U)
1427 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1428 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1429 #define ADC_CR2_JEXTSEL_Pos (16U)
1430 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1431 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1432 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1433 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1434 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1435 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1436 #define ADC_CR2_JEXTEN_Pos (20U)
1437 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1438 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1439 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1440 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1441 #define ADC_CR2_JSWSTART_Pos (22U)
1442 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1443 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1444 #define ADC_CR2_EXTSEL_Pos (24U)
1445 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1446 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1447 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1448 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1449 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1450 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1451 #define ADC_CR2_EXTEN_Pos (28U)
1452 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1453 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1454 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1455 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1456 #define ADC_CR2_SWSTART_Pos (30U)
1457 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1458 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1459
1460 /****************** Bit definition for ADC_SMPR1 register *******************/
1461 #define ADC_SMPR1_SMP10_Pos (0U)
1462 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1463 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1464 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1465 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1466 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1467 #define ADC_SMPR1_SMP11_Pos (3U)
1468 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1469 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1470 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1471 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1472 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1473 #define ADC_SMPR1_SMP12_Pos (6U)
1474 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1475 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1476 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1477 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1478 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1479 #define ADC_SMPR1_SMP13_Pos (9U)
1480 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1481 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1482 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1483 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1484 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1485 #define ADC_SMPR1_SMP14_Pos (12U)
1486 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1487 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1488 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1489 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1490 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1491 #define ADC_SMPR1_SMP15_Pos (15U)
1492 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1493 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1494 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1495 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1496 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1497 #define ADC_SMPR1_SMP16_Pos (18U)
1498 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1499 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1500 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1501 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1502 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1503 #define ADC_SMPR1_SMP17_Pos (21U)
1504 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1505 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1506 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1507 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1508 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1509 #define ADC_SMPR1_SMP18_Pos (24U)
1510 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1511 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1512 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1513 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1514 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1515
1516 /****************** Bit definition for ADC_SMPR2 register *******************/
1517 #define ADC_SMPR2_SMP0_Pos (0U)
1518 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1519 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1520 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1521 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1522 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1523 #define ADC_SMPR2_SMP1_Pos (3U)
1524 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1525 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1526 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1527 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1528 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1529 #define ADC_SMPR2_SMP2_Pos (6U)
1530 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1531 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1532 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1533 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1534 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1535 #define ADC_SMPR2_SMP3_Pos (9U)
1536 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1537 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1538 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1539 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1540 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1541 #define ADC_SMPR2_SMP4_Pos (12U)
1542 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1543 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1544 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1545 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1546 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1547 #define ADC_SMPR2_SMP5_Pos (15U)
1548 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1549 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1550 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1551 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1552 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1553 #define ADC_SMPR2_SMP6_Pos (18U)
1554 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1555 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1556 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1557 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1558 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1559 #define ADC_SMPR2_SMP7_Pos (21U)
1560 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1561 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1562 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1563 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1564 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1565 #define ADC_SMPR2_SMP8_Pos (24U)
1566 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1567 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1568 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1569 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1570 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1571 #define ADC_SMPR2_SMP9_Pos (27U)
1572 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1573 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1574 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1575 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1576 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1577
1578 /****************** Bit definition for ADC_JOFR1 register *******************/
1579 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1580 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1581 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1582
1583 /****************** Bit definition for ADC_JOFR2 register *******************/
1584 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1585 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1586 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1587
1588 /****************** Bit definition for ADC_JOFR3 register *******************/
1589 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1590 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1591 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1592
1593 /****************** Bit definition for ADC_JOFR4 register *******************/
1594 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1595 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1596 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1597
1598 /******************* Bit definition for ADC_HTR register ********************/
1599 #define ADC_HTR_HT_Pos (0U)
1600 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1601 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1602
1603 /******************* Bit definition for ADC_LTR register ********************/
1604 #define ADC_LTR_LT_Pos (0U)
1605 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1606 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1607
1608 /******************* Bit definition for ADC_SQR1 register *******************/
1609 #define ADC_SQR1_SQ13_Pos (0U)
1610 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1611 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1612 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1613 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1614 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1615 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1616 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1617 #define ADC_SQR1_SQ14_Pos (5U)
1618 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1619 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1620 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1621 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1622 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1623 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1624 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1625 #define ADC_SQR1_SQ15_Pos (10U)
1626 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1627 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1628 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1629 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1630 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1631 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1632 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1633 #define ADC_SQR1_SQ16_Pos (15U)
1634 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1635 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1636 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1637 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1638 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1639 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1640 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1641 #define ADC_SQR1_L_Pos (20U)
1642 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1643 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1644 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1645 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1646 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1647 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1648
1649 /******************* Bit definition for ADC_SQR2 register *******************/
1650 #define ADC_SQR2_SQ7_Pos (0U)
1651 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1652 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1653 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1654 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1655 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1656 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1657 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1658 #define ADC_SQR2_SQ8_Pos (5U)
1659 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1660 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1661 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1662 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1663 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1664 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1665 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1666 #define ADC_SQR2_SQ9_Pos (10U)
1667 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1668 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1669 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1670 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1671 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1672 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1673 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1674 #define ADC_SQR2_SQ10_Pos (15U)
1675 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1676 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1677 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1678 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1679 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1680 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1681 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1682 #define ADC_SQR2_SQ11_Pos (20U)
1683 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1684 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1685 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1686 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1687 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1688 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1689 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1690 #define ADC_SQR2_SQ12_Pos (25U)
1691 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1692 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1693 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1694 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1695 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1696 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1697 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1698
1699 /******************* Bit definition for ADC_SQR3 register *******************/
1700 #define ADC_SQR3_SQ1_Pos (0U)
1701 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1702 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1703 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1704 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1705 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1706 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1707 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1708 #define ADC_SQR3_SQ2_Pos (5U)
1709 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1710 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1711 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1712 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1713 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1714 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1715 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1716 #define ADC_SQR3_SQ3_Pos (10U)
1717 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1718 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1719 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1720 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1721 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1722 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1723 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1724 #define ADC_SQR3_SQ4_Pos (15U)
1725 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1726 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1727 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1728 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1729 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1730 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1731 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1732 #define ADC_SQR3_SQ5_Pos (20U)
1733 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1734 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1735 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1736 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1737 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1738 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1739 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1740 #define ADC_SQR3_SQ6_Pos (25U)
1741 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1742 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1743 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1744 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1745 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1746 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1747 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1748
1749 /******************* Bit definition for ADC_JSQR register *******************/
1750 #define ADC_JSQR_JSQ1_Pos (0U)
1751 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1752 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1753 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1754 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1755 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1756 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1757 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1758 #define ADC_JSQR_JSQ2_Pos (5U)
1759 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1760 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1761 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1762 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1763 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1764 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1765 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1766 #define ADC_JSQR_JSQ3_Pos (10U)
1767 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1768 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1769 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1770 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1771 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1772 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1773 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1774 #define ADC_JSQR_JSQ4_Pos (15U)
1775 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1776 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1777 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1778 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1779 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1780 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1781 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1782 #define ADC_JSQR_JL_Pos (20U)
1783 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1784 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1785 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1786 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1787
1788 /******************* Bit definition for ADC_JDR1 register *******************/
1789 #define ADC_JDR1_JDATA_Pos (0U)
1790 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1791 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1792
1793 /******************* Bit definition for ADC_JDR2 register *******************/
1794 #define ADC_JDR2_JDATA_Pos (0U)
1795 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1796 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1797
1798 /******************* Bit definition for ADC_JDR3 register *******************/
1799 #define ADC_JDR3_JDATA_Pos (0U)
1800 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1801 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1802
1803 /******************* Bit definition for ADC_JDR4 register *******************/
1804 #define ADC_JDR4_JDATA_Pos (0U)
1805 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1806 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1807
1808 /******************** Bit definition for ADC_DR register ********************/
1809 #define ADC_DR_DATA_Pos (0U)
1810 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1811 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1812 #define ADC_DR_ADC2DATA_Pos (16U)
1813 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1814 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1815
1816 /******************* Bit definition for ADC_CSR register ********************/
1817 #define ADC_CSR_AWD1_Pos (0U)
1818 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1819 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1820 #define ADC_CSR_EOC1_Pos (1U)
1821 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1822 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1823 #define ADC_CSR_JEOC1_Pos (2U)
1824 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1825 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1826 #define ADC_CSR_JSTRT1_Pos (3U)
1827 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1828 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1829 #define ADC_CSR_STRT1_Pos (4U)
1830 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1831 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1832 #define ADC_CSR_OVR1_Pos (5U)
1833 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1834 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1835 #define ADC_CSR_AWD2_Pos (8U)
1836 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
1837 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
1838 #define ADC_CSR_EOC2_Pos (9U)
1839 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
1840 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
1841 #define ADC_CSR_JEOC2_Pos (10U)
1842 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
1843 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
1844 #define ADC_CSR_JSTRT2_Pos (11U)
1845 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
1846 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
1847 #define ADC_CSR_STRT2_Pos (12U)
1848 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
1849 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
1850 #define ADC_CSR_OVR2_Pos (13U)
1851 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
1852 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
1853 #define ADC_CSR_AWD3_Pos (16U)
1854 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
1855 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
1856 #define ADC_CSR_EOC3_Pos (17U)
1857 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
1858 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
1859 #define ADC_CSR_JEOC3_Pos (18U)
1860 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
1861 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
1862 #define ADC_CSR_JSTRT3_Pos (19U)
1863 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
1864 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
1865 #define ADC_CSR_STRT3_Pos (20U)
1866 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
1867 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
1868 #define ADC_CSR_OVR3_Pos (21U)
1869 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
1870 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
1871
1872 /* Legacy defines */
1873 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1874 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1875 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1876
1877 /******************* Bit definition for ADC_CCR register ********************/
1878 #define ADC_CCR_MULTI_Pos (0U)
1879 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1880 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1881 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1882 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1883 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1884 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1885 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1886 #define ADC_CCR_DELAY_Pos (8U)
1887 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1888 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1889 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1890 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1891 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1892 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1893 #define ADC_CCR_DDS_Pos (13U)
1894 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1895 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1896 #define ADC_CCR_DMA_Pos (14U)
1897 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1898 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1899 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1900 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1901 #define ADC_CCR_ADCPRE_Pos (16U)
1902 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1903 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1904 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1905 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1906 #define ADC_CCR_VBATE_Pos (22U)
1907 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1908 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1909 #define ADC_CCR_TSVREFE_Pos (23U)
1910 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1911 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1912
1913 /******************* Bit definition for ADC_CDR register ********************/
1914 #define ADC_CDR_DATA1_Pos (0U)
1915 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1916 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1917 #define ADC_CDR_DATA2_Pos (16U)
1918 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1919 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1920
1921 /* Legacy defines */
1922 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1923 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1924
1925 /******************************************************************************/
1926 /* */
1927 /* Controller Area Network */
1928 /* */
1929 /******************************************************************************/
1930 /*!<CAN control and status registers */
1931 /******************* Bit definition for CAN_MCR register ********************/
1932 #define CAN_MCR_INRQ_Pos (0U)
1933 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
1934 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
1935 #define CAN_MCR_SLEEP_Pos (1U)
1936 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
1937 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
1938 #define CAN_MCR_TXFP_Pos (2U)
1939 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
1940 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
1941 #define CAN_MCR_RFLM_Pos (3U)
1942 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
1943 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
1944 #define CAN_MCR_NART_Pos (4U)
1945 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
1946 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
1947 #define CAN_MCR_AWUM_Pos (5U)
1948 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
1949 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
1950 #define CAN_MCR_ABOM_Pos (6U)
1951 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
1952 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
1953 #define CAN_MCR_TTCM_Pos (7U)
1954 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
1955 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
1956 #define CAN_MCR_RESET_Pos (15U)
1957 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
1958 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
1959 #define CAN_MCR_DBF_Pos (16U)
1960 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
1961 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
1962 /******************* Bit definition for CAN_MSR register ********************/
1963 #define CAN_MSR_INAK_Pos (0U)
1964 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
1965 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
1966 #define CAN_MSR_SLAK_Pos (1U)
1967 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
1968 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
1969 #define CAN_MSR_ERRI_Pos (2U)
1970 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
1971 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
1972 #define CAN_MSR_WKUI_Pos (3U)
1973 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
1974 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
1975 #define CAN_MSR_SLAKI_Pos (4U)
1976 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
1977 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
1978 #define CAN_MSR_TXM_Pos (8U)
1979 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
1980 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
1981 #define CAN_MSR_RXM_Pos (9U)
1982 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
1983 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
1984 #define CAN_MSR_SAMP_Pos (10U)
1985 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
1986 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
1987 #define CAN_MSR_RX_Pos (11U)
1988 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
1989 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
1990
1991 /******************* Bit definition for CAN_TSR register ********************/
1992 #define CAN_TSR_RQCP0_Pos (0U)
1993 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
1994 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
1995 #define CAN_TSR_TXOK0_Pos (1U)
1996 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
1997 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
1998 #define CAN_TSR_ALST0_Pos (2U)
1999 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2000 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2001 #define CAN_TSR_TERR0_Pos (3U)
2002 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2003 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2004 #define CAN_TSR_ABRQ0_Pos (7U)
2005 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2006 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2007 #define CAN_TSR_RQCP1_Pos (8U)
2008 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2009 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2010 #define CAN_TSR_TXOK1_Pos (9U)
2011 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2012 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2013 #define CAN_TSR_ALST1_Pos (10U)
2014 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2015 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2016 #define CAN_TSR_TERR1_Pos (11U)
2017 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2018 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2019 #define CAN_TSR_ABRQ1_Pos (15U)
2020 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2021 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2022 #define CAN_TSR_RQCP2_Pos (16U)
2023 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2024 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2025 #define CAN_TSR_TXOK2_Pos (17U)
2026 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2027 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2028 #define CAN_TSR_ALST2_Pos (18U)
2029 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2030 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2031 #define CAN_TSR_TERR2_Pos (19U)
2032 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2033 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2034 #define CAN_TSR_ABRQ2_Pos (23U)
2035 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2036 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2037 #define CAN_TSR_CODE_Pos (24U)
2038 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2039 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2040
2041 #define CAN_TSR_TME_Pos (26U)
2042 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2043 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2044 #define CAN_TSR_TME0_Pos (26U)
2045 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2046 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2047 #define CAN_TSR_TME1_Pos (27U)
2048 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2049 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2050 #define CAN_TSR_TME2_Pos (28U)
2051 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2052 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2053
2054 #define CAN_TSR_LOW_Pos (29U)
2055 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2056 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2057 #define CAN_TSR_LOW0_Pos (29U)
2058 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2059 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2060 #define CAN_TSR_LOW1_Pos (30U)
2061 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2062 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2063 #define CAN_TSR_LOW2_Pos (31U)
2064 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2065 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2066
2067 /******************* Bit definition for CAN_RF0R register *******************/
2068 #define CAN_RF0R_FMP0_Pos (0U)
2069 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2070 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2071 #define CAN_RF0R_FULL0_Pos (3U)
2072 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2073 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2074 #define CAN_RF0R_FOVR0_Pos (4U)
2075 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2076 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2077 #define CAN_RF0R_RFOM0_Pos (5U)
2078 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2079 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2080
2081 /******************* Bit definition for CAN_RF1R register *******************/
2082 #define CAN_RF1R_FMP1_Pos (0U)
2083 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2084 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2085 #define CAN_RF1R_FULL1_Pos (3U)
2086 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2087 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2088 #define CAN_RF1R_FOVR1_Pos (4U)
2089 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2090 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2091 #define CAN_RF1R_RFOM1_Pos (5U)
2092 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2093 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2094
2095 /******************** Bit definition for CAN_IER register *******************/
2096 #define CAN_IER_TMEIE_Pos (0U)
2097 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2098 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2099 #define CAN_IER_FMPIE0_Pos (1U)
2100 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2101 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2102 #define CAN_IER_FFIE0_Pos (2U)
2103 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2104 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2105 #define CAN_IER_FOVIE0_Pos (3U)
2106 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2107 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2108 #define CAN_IER_FMPIE1_Pos (4U)
2109 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2110 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2111 #define CAN_IER_FFIE1_Pos (5U)
2112 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2113 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2114 #define CAN_IER_FOVIE1_Pos (6U)
2115 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2116 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2117 #define CAN_IER_EWGIE_Pos (8U)
2118 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2119 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2120 #define CAN_IER_EPVIE_Pos (9U)
2121 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2122 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2123 #define CAN_IER_BOFIE_Pos (10U)
2124 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2125 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2126 #define CAN_IER_LECIE_Pos (11U)
2127 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2128 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2129 #define CAN_IER_ERRIE_Pos (15U)
2130 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2131 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2132 #define CAN_IER_WKUIE_Pos (16U)
2133 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2134 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2135 #define CAN_IER_SLKIE_Pos (17U)
2136 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2137 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2138 #define CAN_IER_EWGIE_Pos (8U)
2139
2140 /******************** Bit definition for CAN_ESR register *******************/
2141 #define CAN_ESR_EWGF_Pos (0U)
2142 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2143 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2144 #define CAN_ESR_EPVF_Pos (1U)
2145 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2146 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2147 #define CAN_ESR_BOFF_Pos (2U)
2148 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2149 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2150
2151 #define CAN_ESR_LEC_Pos (4U)
2152 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2153 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2154 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2155 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2156 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2157
2158 #define CAN_ESR_TEC_Pos (16U)
2159 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2160 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2161 #define CAN_ESR_REC_Pos (24U)
2162 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2163 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2164
2165 /******************* Bit definition for CAN_BTR register ********************/
2166 #define CAN_BTR_BRP_Pos (0U)
2167 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2168 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2169 #define CAN_BTR_TS1_Pos (16U)
2170 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2171 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2172 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2173 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2174 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2175 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2176 #define CAN_BTR_TS2_Pos (20U)
2177 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2178 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2179 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2180 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2181 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2182 #define CAN_BTR_SJW_Pos (24U)
2183 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2184 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2185 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2186 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2187 #define CAN_BTR_LBKM_Pos (30U)
2188 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2189 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2190 #define CAN_BTR_SILM_Pos (31U)
2191 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2192 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2193
2194
2195 /*!<Mailbox registers */
2196 /****************** Bit definition for CAN_TI0R register ********************/
2197 #define CAN_TI0R_TXRQ_Pos (0U)
2198 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2199 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2200 #define CAN_TI0R_RTR_Pos (1U)
2201 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2202 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2203 #define CAN_TI0R_IDE_Pos (2U)
2204 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2205 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2206 #define CAN_TI0R_EXID_Pos (3U)
2207 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2208 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2209 #define CAN_TI0R_STID_Pos (21U)
2210 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2211 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2212
2213 /****************** Bit definition for CAN_TDT0R register *******************/
2214 #define CAN_TDT0R_DLC_Pos (0U)
2215 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2216 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2217 #define CAN_TDT0R_TGT_Pos (8U)
2218 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2219 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2220 #define CAN_TDT0R_TIME_Pos (16U)
2221 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2222 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2223
2224 /****************** Bit definition for CAN_TDL0R register *******************/
2225 #define CAN_TDL0R_DATA0_Pos (0U)
2226 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2227 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2228 #define CAN_TDL0R_DATA1_Pos (8U)
2229 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2230 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2231 #define CAN_TDL0R_DATA2_Pos (16U)
2232 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2233 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2234 #define CAN_TDL0R_DATA3_Pos (24U)
2235 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2236 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2237
2238 /****************** Bit definition for CAN_TDH0R register *******************/
2239 #define CAN_TDH0R_DATA4_Pos (0U)
2240 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2241 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2242 #define CAN_TDH0R_DATA5_Pos (8U)
2243 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2244 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2245 #define CAN_TDH0R_DATA6_Pos (16U)
2246 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2247 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2248 #define CAN_TDH0R_DATA7_Pos (24U)
2249 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2250 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2251
2252 /******************* Bit definition for CAN_TI1R register *******************/
2253 #define CAN_TI1R_TXRQ_Pos (0U)
2254 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2255 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2256 #define CAN_TI1R_RTR_Pos (1U)
2257 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2258 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2259 #define CAN_TI1R_IDE_Pos (2U)
2260 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2261 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2262 #define CAN_TI1R_EXID_Pos (3U)
2263 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2264 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2265 #define CAN_TI1R_STID_Pos (21U)
2266 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2267 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2268
2269 /******************* Bit definition for CAN_TDT1R register ******************/
2270 #define CAN_TDT1R_DLC_Pos (0U)
2271 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2272 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2273 #define CAN_TDT1R_TGT_Pos (8U)
2274 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2275 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2276 #define CAN_TDT1R_TIME_Pos (16U)
2277 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2278 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2279
2280 /******************* Bit definition for CAN_TDL1R register ******************/
2281 #define CAN_TDL1R_DATA0_Pos (0U)
2282 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2283 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2284 #define CAN_TDL1R_DATA1_Pos (8U)
2285 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2286 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2287 #define CAN_TDL1R_DATA2_Pos (16U)
2288 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2289 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2290 #define CAN_TDL1R_DATA3_Pos (24U)
2291 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2292 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2293
2294 /******************* Bit definition for CAN_TDH1R register ******************/
2295 #define CAN_TDH1R_DATA4_Pos (0U)
2296 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2297 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2298 #define CAN_TDH1R_DATA5_Pos (8U)
2299 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2300 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2301 #define CAN_TDH1R_DATA6_Pos (16U)
2302 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2303 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2304 #define CAN_TDH1R_DATA7_Pos (24U)
2305 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2306 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2307
2308 /******************* Bit definition for CAN_TI2R register *******************/
2309 #define CAN_TI2R_TXRQ_Pos (0U)
2310 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2311 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2312 #define CAN_TI2R_RTR_Pos (1U)
2313 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2314 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2315 #define CAN_TI2R_IDE_Pos (2U)
2316 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2317 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2318 #define CAN_TI2R_EXID_Pos (3U)
2319 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2320 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2321 #define CAN_TI2R_STID_Pos (21U)
2322 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2323 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2324
2325 /******************* Bit definition for CAN_TDT2R register ******************/
2326 #define CAN_TDT2R_DLC_Pos (0U)
2327 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2328 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2329 #define CAN_TDT2R_TGT_Pos (8U)
2330 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2331 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2332 #define CAN_TDT2R_TIME_Pos (16U)
2333 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2334 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2335
2336 /******************* Bit definition for CAN_TDL2R register ******************/
2337 #define CAN_TDL2R_DATA0_Pos (0U)
2338 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2339 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2340 #define CAN_TDL2R_DATA1_Pos (8U)
2341 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2342 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2343 #define CAN_TDL2R_DATA2_Pos (16U)
2344 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2345 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2346 #define CAN_TDL2R_DATA3_Pos (24U)
2347 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2348 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2349
2350 /******************* Bit definition for CAN_TDH2R register ******************/
2351 #define CAN_TDH2R_DATA4_Pos (0U)
2352 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2353 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2354 #define CAN_TDH2R_DATA5_Pos (8U)
2355 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2356 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2357 #define CAN_TDH2R_DATA6_Pos (16U)
2358 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2359 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2360 #define CAN_TDH2R_DATA7_Pos (24U)
2361 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2362 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2363
2364 /******************* Bit definition for CAN_RI0R register *******************/
2365 #define CAN_RI0R_RTR_Pos (1U)
2366 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2367 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2368 #define CAN_RI0R_IDE_Pos (2U)
2369 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2370 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2371 #define CAN_RI0R_EXID_Pos (3U)
2372 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2373 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2374 #define CAN_RI0R_STID_Pos (21U)
2375 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2376 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2377
2378 /******************* Bit definition for CAN_RDT0R register ******************/
2379 #define CAN_RDT0R_DLC_Pos (0U)
2380 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2381 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2382 #define CAN_RDT0R_FMI_Pos (8U)
2383 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2384 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2385 #define CAN_RDT0R_TIME_Pos (16U)
2386 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2387 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2388
2389 /******************* Bit definition for CAN_RDL0R register ******************/
2390 #define CAN_RDL0R_DATA0_Pos (0U)
2391 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2392 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2393 #define CAN_RDL0R_DATA1_Pos (8U)
2394 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2395 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2396 #define CAN_RDL0R_DATA2_Pos (16U)
2397 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2398 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2399 #define CAN_RDL0R_DATA3_Pos (24U)
2400 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2401 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2402
2403 /******************* Bit definition for CAN_RDH0R register ******************/
2404 #define CAN_RDH0R_DATA4_Pos (0U)
2405 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2406 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2407 #define CAN_RDH0R_DATA5_Pos (8U)
2408 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2409 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2410 #define CAN_RDH0R_DATA6_Pos (16U)
2411 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2412 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2413 #define CAN_RDH0R_DATA7_Pos (24U)
2414 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2415 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2416
2417 /******************* Bit definition for CAN_RI1R register *******************/
2418 #define CAN_RI1R_RTR_Pos (1U)
2419 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2420 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2421 #define CAN_RI1R_IDE_Pos (2U)
2422 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2423 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2424 #define CAN_RI1R_EXID_Pos (3U)
2425 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2426 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2427 #define CAN_RI1R_STID_Pos (21U)
2428 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2429 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2430
2431 /******************* Bit definition for CAN_RDT1R register ******************/
2432 #define CAN_RDT1R_DLC_Pos (0U)
2433 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2434 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2435 #define CAN_RDT1R_FMI_Pos (8U)
2436 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2437 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2438 #define CAN_RDT1R_TIME_Pos (16U)
2439 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2440 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2441
2442 /******************* Bit definition for CAN_RDL1R register ******************/
2443 #define CAN_RDL1R_DATA0_Pos (0U)
2444 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2445 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2446 #define CAN_RDL1R_DATA1_Pos (8U)
2447 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2448 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2449 #define CAN_RDL1R_DATA2_Pos (16U)
2450 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2451 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2452 #define CAN_RDL1R_DATA3_Pos (24U)
2453 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2454 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2455
2456 /******************* Bit definition for CAN_RDH1R register ******************/
2457 #define CAN_RDH1R_DATA4_Pos (0U)
2458 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2459 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2460 #define CAN_RDH1R_DATA5_Pos (8U)
2461 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2462 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2463 #define CAN_RDH1R_DATA6_Pos (16U)
2464 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2465 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2466 #define CAN_RDH1R_DATA7_Pos (24U)
2467 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2468 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2469
2470 /*!<CAN filter registers */
2471 /******************* Bit definition for CAN_FMR register ********************/
2472 #define CAN_FMR_FINIT_Pos (0U)
2473 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2474 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2475 #define CAN_FMR_CAN2SB_Pos (8U)
2476 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2477 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2478
2479 /******************* Bit definition for CAN_FM1R register *******************/
2480 #define CAN_FM1R_FBM_Pos (0U)
2481 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2482 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2483 #define CAN_FM1R_FBM0_Pos (0U)
2484 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2485 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2486 #define CAN_FM1R_FBM1_Pos (1U)
2487 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2488 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2489 #define CAN_FM1R_FBM2_Pos (2U)
2490 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2491 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2492 #define CAN_FM1R_FBM3_Pos (3U)
2493 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2494 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2495 #define CAN_FM1R_FBM4_Pos (4U)
2496 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2497 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2498 #define CAN_FM1R_FBM5_Pos (5U)
2499 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2500 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2501 #define CAN_FM1R_FBM6_Pos (6U)
2502 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2503 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2504 #define CAN_FM1R_FBM7_Pos (7U)
2505 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2506 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2507 #define CAN_FM1R_FBM8_Pos (8U)
2508 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2509 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2510 #define CAN_FM1R_FBM9_Pos (9U)
2511 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2512 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2513 #define CAN_FM1R_FBM10_Pos (10U)
2514 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2515 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2516 #define CAN_FM1R_FBM11_Pos (11U)
2517 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2518 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2519 #define CAN_FM1R_FBM12_Pos (12U)
2520 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2521 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2522 #define CAN_FM1R_FBM13_Pos (13U)
2523 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2524 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2525 #define CAN_FM1R_FBM14_Pos (14U)
2526 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2527 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2528 #define CAN_FM1R_FBM15_Pos (15U)
2529 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2530 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2531 #define CAN_FM1R_FBM16_Pos (16U)
2532 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2533 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2534 #define CAN_FM1R_FBM17_Pos (17U)
2535 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2536 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2537 #define CAN_FM1R_FBM18_Pos (18U)
2538 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2539 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2540 #define CAN_FM1R_FBM19_Pos (19U)
2541 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2542 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2543 #define CAN_FM1R_FBM20_Pos (20U)
2544 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2545 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2546 #define CAN_FM1R_FBM21_Pos (21U)
2547 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2548 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2549 #define CAN_FM1R_FBM22_Pos (22U)
2550 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2551 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2552 #define CAN_FM1R_FBM23_Pos (23U)
2553 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2554 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2555 #define CAN_FM1R_FBM24_Pos (24U)
2556 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2557 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2558 #define CAN_FM1R_FBM25_Pos (25U)
2559 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2560 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2561 #define CAN_FM1R_FBM26_Pos (26U)
2562 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2563 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2564 #define CAN_FM1R_FBM27_Pos (27U)
2565 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2566 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2567
2568 /******************* Bit definition for CAN_FS1R register *******************/
2569 #define CAN_FS1R_FSC_Pos (0U)
2570 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2571 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2572 #define CAN_FS1R_FSC0_Pos (0U)
2573 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2574 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2575 #define CAN_FS1R_FSC1_Pos (1U)
2576 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2577 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2578 #define CAN_FS1R_FSC2_Pos (2U)
2579 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2580 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2581 #define CAN_FS1R_FSC3_Pos (3U)
2582 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2583 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2584 #define CAN_FS1R_FSC4_Pos (4U)
2585 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2586 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2587 #define CAN_FS1R_FSC5_Pos (5U)
2588 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2589 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2590 #define CAN_FS1R_FSC6_Pos (6U)
2591 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2592 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2593 #define CAN_FS1R_FSC7_Pos (7U)
2594 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2595 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2596 #define CAN_FS1R_FSC8_Pos (8U)
2597 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2598 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2599 #define CAN_FS1R_FSC9_Pos (9U)
2600 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2601 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2602 #define CAN_FS1R_FSC10_Pos (10U)
2603 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2604 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2605 #define CAN_FS1R_FSC11_Pos (11U)
2606 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2607 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2608 #define CAN_FS1R_FSC12_Pos (12U)
2609 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2610 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2611 #define CAN_FS1R_FSC13_Pos (13U)
2612 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2613 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2614 #define CAN_FS1R_FSC14_Pos (14U)
2615 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2616 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2617 #define CAN_FS1R_FSC15_Pos (15U)
2618 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2619 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2620 #define CAN_FS1R_FSC16_Pos (16U)
2621 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2622 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2623 #define CAN_FS1R_FSC17_Pos (17U)
2624 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2625 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2626 #define CAN_FS1R_FSC18_Pos (18U)
2627 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2628 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2629 #define CAN_FS1R_FSC19_Pos (19U)
2630 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2631 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2632 #define CAN_FS1R_FSC20_Pos (20U)
2633 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2634 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2635 #define CAN_FS1R_FSC21_Pos (21U)
2636 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2637 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2638 #define CAN_FS1R_FSC22_Pos (22U)
2639 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2640 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2641 #define CAN_FS1R_FSC23_Pos (23U)
2642 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2643 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2644 #define CAN_FS1R_FSC24_Pos (24U)
2645 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2646 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2647 #define CAN_FS1R_FSC25_Pos (25U)
2648 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2649 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2650 #define CAN_FS1R_FSC26_Pos (26U)
2651 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2652 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2653 #define CAN_FS1R_FSC27_Pos (27U)
2654 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2655 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2656
2657 /****************** Bit definition for CAN_FFA1R register *******************/
2658 #define CAN_FFA1R_FFA_Pos (0U)
2659 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2660 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2661 #define CAN_FFA1R_FFA0_Pos (0U)
2662 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2663 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2664 #define CAN_FFA1R_FFA1_Pos (1U)
2665 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2666 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2667 #define CAN_FFA1R_FFA2_Pos (2U)
2668 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2669 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2670 #define CAN_FFA1R_FFA3_Pos (3U)
2671 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2672 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2673 #define CAN_FFA1R_FFA4_Pos (4U)
2674 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2675 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2676 #define CAN_FFA1R_FFA5_Pos (5U)
2677 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2678 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2679 #define CAN_FFA1R_FFA6_Pos (6U)
2680 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2681 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2682 #define CAN_FFA1R_FFA7_Pos (7U)
2683 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2684 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2685 #define CAN_FFA1R_FFA8_Pos (8U)
2686 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2687 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2688 #define CAN_FFA1R_FFA9_Pos (9U)
2689 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2690 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2691 #define CAN_FFA1R_FFA10_Pos (10U)
2692 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2693 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2694 #define CAN_FFA1R_FFA11_Pos (11U)
2695 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2696 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2697 #define CAN_FFA1R_FFA12_Pos (12U)
2698 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2699 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2700 #define CAN_FFA1R_FFA13_Pos (13U)
2701 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2702 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2703 #define CAN_FFA1R_FFA14_Pos (14U)
2704 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2705 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2706 #define CAN_FFA1R_FFA15_Pos (15U)
2707 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2708 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2709 #define CAN_FFA1R_FFA16_Pos (16U)
2710 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2711 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2712 #define CAN_FFA1R_FFA17_Pos (17U)
2713 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2714 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2715 #define CAN_FFA1R_FFA18_Pos (18U)
2716 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2717 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2718 #define CAN_FFA1R_FFA19_Pos (19U)
2719 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2720 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2721 #define CAN_FFA1R_FFA20_Pos (20U)
2722 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2723 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2724 #define CAN_FFA1R_FFA21_Pos (21U)
2725 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2726 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2727 #define CAN_FFA1R_FFA22_Pos (22U)
2728 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2729 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2730 #define CAN_FFA1R_FFA23_Pos (23U)
2731 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2732 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2733 #define CAN_FFA1R_FFA24_Pos (24U)
2734 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2735 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2736 #define CAN_FFA1R_FFA25_Pos (25U)
2737 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2738 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2739 #define CAN_FFA1R_FFA26_Pos (26U)
2740 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2741 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2742 #define CAN_FFA1R_FFA27_Pos (27U)
2743 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2744 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2745
2746 /******************* Bit definition for CAN_FA1R register *******************/
2747 #define CAN_FA1R_FACT_Pos (0U)
2748 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2749 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2750 #define CAN_FA1R_FACT0_Pos (0U)
2751 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2752 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2753 #define CAN_FA1R_FACT1_Pos (1U)
2754 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2755 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2756 #define CAN_FA1R_FACT2_Pos (2U)
2757 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2758 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2759 #define CAN_FA1R_FACT3_Pos (3U)
2760 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2761 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2762 #define CAN_FA1R_FACT4_Pos (4U)
2763 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2764 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2765 #define CAN_FA1R_FACT5_Pos (5U)
2766 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2767 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2768 #define CAN_FA1R_FACT6_Pos (6U)
2769 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2770 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2771 #define CAN_FA1R_FACT7_Pos (7U)
2772 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2773 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2774 #define CAN_FA1R_FACT8_Pos (8U)
2775 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2776 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2777 #define CAN_FA1R_FACT9_Pos (9U)
2778 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2779 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2780 #define CAN_FA1R_FACT10_Pos (10U)
2781 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2782 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2783 #define CAN_FA1R_FACT11_Pos (11U)
2784 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2785 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2786 #define CAN_FA1R_FACT12_Pos (12U)
2787 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2788 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2789 #define CAN_FA1R_FACT13_Pos (13U)
2790 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2791 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2792 #define CAN_FA1R_FACT14_Pos (14U)
2793 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2794 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2795 #define CAN_FA1R_FACT15_Pos (15U)
2796 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2797 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2798 #define CAN_FA1R_FACT16_Pos (16U)
2799 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2800 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2801 #define CAN_FA1R_FACT17_Pos (17U)
2802 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2803 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2804 #define CAN_FA1R_FACT18_Pos (18U)
2805 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2806 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2807 #define CAN_FA1R_FACT19_Pos (19U)
2808 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2809 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2810 #define CAN_FA1R_FACT20_Pos (20U)
2811 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2812 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2813 #define CAN_FA1R_FACT21_Pos (21U)
2814 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2815 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2816 #define CAN_FA1R_FACT22_Pos (22U)
2817 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2818 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2819 #define CAN_FA1R_FACT23_Pos (23U)
2820 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2821 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2822 #define CAN_FA1R_FACT24_Pos (24U)
2823 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2824 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2825 #define CAN_FA1R_FACT25_Pos (25U)
2826 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2827 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2828 #define CAN_FA1R_FACT26_Pos (26U)
2829 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2830 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
2831 #define CAN_FA1R_FACT27_Pos (27U)
2832 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
2833 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
2834
2835
2836 /******************* Bit definition for CAN_F0R1 register *******************/
2837 #define CAN_F0R1_FB0_Pos (0U)
2838 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2839 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2840 #define CAN_F0R1_FB1_Pos (1U)
2841 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2842 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2843 #define CAN_F0R1_FB2_Pos (2U)
2844 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2845 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2846 #define CAN_F0R1_FB3_Pos (3U)
2847 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2848 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2849 #define CAN_F0R1_FB4_Pos (4U)
2850 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2851 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2852 #define CAN_F0R1_FB5_Pos (5U)
2853 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2854 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2855 #define CAN_F0R1_FB6_Pos (6U)
2856 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2857 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2858 #define CAN_F0R1_FB7_Pos (7U)
2859 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2860 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2861 #define CAN_F0R1_FB8_Pos (8U)
2862 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2863 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2864 #define CAN_F0R1_FB9_Pos (9U)
2865 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2866 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2867 #define CAN_F0R1_FB10_Pos (10U)
2868 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2869 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2870 #define CAN_F0R1_FB11_Pos (11U)
2871 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2872 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2873 #define CAN_F0R1_FB12_Pos (12U)
2874 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2875 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2876 #define CAN_F0R1_FB13_Pos (13U)
2877 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2878 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2879 #define CAN_F0R1_FB14_Pos (14U)
2880 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2881 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2882 #define CAN_F0R1_FB15_Pos (15U)
2883 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2884 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2885 #define CAN_F0R1_FB16_Pos (16U)
2886 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2887 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2888 #define CAN_F0R1_FB17_Pos (17U)
2889 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2890 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2891 #define CAN_F0R1_FB18_Pos (18U)
2892 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2893 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2894 #define CAN_F0R1_FB19_Pos (19U)
2895 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2896 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2897 #define CAN_F0R1_FB20_Pos (20U)
2898 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2899 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2900 #define CAN_F0R1_FB21_Pos (21U)
2901 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2902 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2903 #define CAN_F0R1_FB22_Pos (22U)
2904 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2905 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2906 #define CAN_F0R1_FB23_Pos (23U)
2907 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2908 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
2909 #define CAN_F0R1_FB24_Pos (24U)
2910 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
2911 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
2912 #define CAN_F0R1_FB25_Pos (25U)
2913 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
2914 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
2915 #define CAN_F0R1_FB26_Pos (26U)
2916 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
2917 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
2918 #define CAN_F0R1_FB27_Pos (27U)
2919 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
2920 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
2921 #define CAN_F0R1_FB28_Pos (28U)
2922 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
2923 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
2924 #define CAN_F0R1_FB29_Pos (29U)
2925 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
2926 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
2927 #define CAN_F0R1_FB30_Pos (30U)
2928 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
2929 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
2930 #define CAN_F0R1_FB31_Pos (31U)
2931 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
2932 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
2933
2934 /******************* Bit definition for CAN_F1R1 register *******************/
2935 #define CAN_F1R1_FB0_Pos (0U)
2936 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
2937 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
2938 #define CAN_F1R1_FB1_Pos (1U)
2939 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
2940 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
2941 #define CAN_F1R1_FB2_Pos (2U)
2942 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
2943 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
2944 #define CAN_F1R1_FB3_Pos (3U)
2945 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
2946 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
2947 #define CAN_F1R1_FB4_Pos (4U)
2948 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
2949 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
2950 #define CAN_F1R1_FB5_Pos (5U)
2951 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
2952 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
2953 #define CAN_F1R1_FB6_Pos (6U)
2954 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
2955 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
2956 #define CAN_F1R1_FB7_Pos (7U)
2957 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
2958 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
2959 #define CAN_F1R1_FB8_Pos (8U)
2960 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
2961 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
2962 #define CAN_F1R1_FB9_Pos (9U)
2963 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
2964 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
2965 #define CAN_F1R1_FB10_Pos (10U)
2966 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
2967 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
2968 #define CAN_F1R1_FB11_Pos (11U)
2969 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
2970 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
2971 #define CAN_F1R1_FB12_Pos (12U)
2972 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
2973 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
2974 #define CAN_F1R1_FB13_Pos (13U)
2975 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
2976 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
2977 #define CAN_F1R1_FB14_Pos (14U)
2978 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
2979 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
2980 #define CAN_F1R1_FB15_Pos (15U)
2981 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
2982 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
2983 #define CAN_F1R1_FB16_Pos (16U)
2984 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
2985 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
2986 #define CAN_F1R1_FB17_Pos (17U)
2987 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
2988 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
2989 #define CAN_F1R1_FB18_Pos (18U)
2990 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
2991 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
2992 #define CAN_F1R1_FB19_Pos (19U)
2993 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
2994 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
2995 #define CAN_F1R1_FB20_Pos (20U)
2996 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
2997 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
2998 #define CAN_F1R1_FB21_Pos (21U)
2999 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3000 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3001 #define CAN_F1R1_FB22_Pos (22U)
3002 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3003 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3004 #define CAN_F1R1_FB23_Pos (23U)
3005 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3006 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3007 #define CAN_F1R1_FB24_Pos (24U)
3008 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3009 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3010 #define CAN_F1R1_FB25_Pos (25U)
3011 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3012 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3013 #define CAN_F1R1_FB26_Pos (26U)
3014 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3015 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3016 #define CAN_F1R1_FB27_Pos (27U)
3017 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3018 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3019 #define CAN_F1R1_FB28_Pos (28U)
3020 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3021 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3022 #define CAN_F1R1_FB29_Pos (29U)
3023 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3024 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3025 #define CAN_F1R1_FB30_Pos (30U)
3026 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3027 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3028 #define CAN_F1R1_FB31_Pos (31U)
3029 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3030 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3031
3032 /******************* Bit definition for CAN_F2R1 register *******************/
3033 #define CAN_F2R1_FB0_Pos (0U)
3034 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3035 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3036 #define CAN_F2R1_FB1_Pos (1U)
3037 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3038 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3039 #define CAN_F2R1_FB2_Pos (2U)
3040 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3041 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3042 #define CAN_F2R1_FB3_Pos (3U)
3043 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3044 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3045 #define CAN_F2R1_FB4_Pos (4U)
3046 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3047 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3048 #define CAN_F2R1_FB5_Pos (5U)
3049 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3050 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3051 #define CAN_F2R1_FB6_Pos (6U)
3052 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3053 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3054 #define CAN_F2R1_FB7_Pos (7U)
3055 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3056 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3057 #define CAN_F2R1_FB8_Pos (8U)
3058 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3059 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3060 #define CAN_F2R1_FB9_Pos (9U)
3061 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3062 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3063 #define CAN_F2R1_FB10_Pos (10U)
3064 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3065 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3066 #define CAN_F2R1_FB11_Pos (11U)
3067 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3068 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3069 #define CAN_F2R1_FB12_Pos (12U)
3070 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3071 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3072 #define CAN_F2R1_FB13_Pos (13U)
3073 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3074 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3075 #define CAN_F2R1_FB14_Pos (14U)
3076 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3077 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3078 #define CAN_F2R1_FB15_Pos (15U)
3079 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3080 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3081 #define CAN_F2R1_FB16_Pos (16U)
3082 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3083 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3084 #define CAN_F2R1_FB17_Pos (17U)
3085 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3086 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3087 #define CAN_F2R1_FB18_Pos (18U)
3088 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3089 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3090 #define CAN_F2R1_FB19_Pos (19U)
3091 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3092 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3093 #define CAN_F2R1_FB20_Pos (20U)
3094 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3095 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3096 #define CAN_F2R1_FB21_Pos (21U)
3097 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3098 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3099 #define CAN_F2R1_FB22_Pos (22U)
3100 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3101 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3102 #define CAN_F2R1_FB23_Pos (23U)
3103 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3104 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3105 #define CAN_F2R1_FB24_Pos (24U)
3106 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3107 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3108 #define CAN_F2R1_FB25_Pos (25U)
3109 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3110 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3111 #define CAN_F2R1_FB26_Pos (26U)
3112 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3113 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3114 #define CAN_F2R1_FB27_Pos (27U)
3115 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3116 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3117 #define CAN_F2R1_FB28_Pos (28U)
3118 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3119 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3120 #define CAN_F2R1_FB29_Pos (29U)
3121 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3122 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3123 #define CAN_F2R1_FB30_Pos (30U)
3124 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3125 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3126 #define CAN_F2R1_FB31_Pos (31U)
3127 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3128 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3129
3130 /******************* Bit definition for CAN_F3R1 register *******************/
3131 #define CAN_F3R1_FB0_Pos (0U)
3132 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3133 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3134 #define CAN_F3R1_FB1_Pos (1U)
3135 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3136 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3137 #define CAN_F3R1_FB2_Pos (2U)
3138 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3139 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3140 #define CAN_F3R1_FB3_Pos (3U)
3141 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3142 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3143 #define CAN_F3R1_FB4_Pos (4U)
3144 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3145 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3146 #define CAN_F3R1_FB5_Pos (5U)
3147 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3148 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3149 #define CAN_F3R1_FB6_Pos (6U)
3150 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3151 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3152 #define CAN_F3R1_FB7_Pos (7U)
3153 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3154 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3155 #define CAN_F3R1_FB8_Pos (8U)
3156 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3157 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3158 #define CAN_F3R1_FB9_Pos (9U)
3159 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3160 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3161 #define CAN_F3R1_FB10_Pos (10U)
3162 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3163 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3164 #define CAN_F3R1_FB11_Pos (11U)
3165 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3166 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3167 #define CAN_F3R1_FB12_Pos (12U)
3168 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3169 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3170 #define CAN_F3R1_FB13_Pos (13U)
3171 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3172 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3173 #define CAN_F3R1_FB14_Pos (14U)
3174 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3175 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3176 #define CAN_F3R1_FB15_Pos (15U)
3177 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3178 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3179 #define CAN_F3R1_FB16_Pos (16U)
3180 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3181 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3182 #define CAN_F3R1_FB17_Pos (17U)
3183 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3184 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3185 #define CAN_F3R1_FB18_Pos (18U)
3186 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3187 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3188 #define CAN_F3R1_FB19_Pos (19U)
3189 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3190 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3191 #define CAN_F3R1_FB20_Pos (20U)
3192 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3193 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3194 #define CAN_F3R1_FB21_Pos (21U)
3195 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3196 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3197 #define CAN_F3R1_FB22_Pos (22U)
3198 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3199 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3200 #define CAN_F3R1_FB23_Pos (23U)
3201 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3202 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3203 #define CAN_F3R1_FB24_Pos (24U)
3204 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3205 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3206 #define CAN_F3R1_FB25_Pos (25U)
3207 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3208 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3209 #define CAN_F3R1_FB26_Pos (26U)
3210 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3211 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3212 #define CAN_F3R1_FB27_Pos (27U)
3213 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3214 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3215 #define CAN_F3R1_FB28_Pos (28U)
3216 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3217 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3218 #define CAN_F3R1_FB29_Pos (29U)
3219 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3220 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3221 #define CAN_F3R1_FB30_Pos (30U)
3222 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3223 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3224 #define CAN_F3R1_FB31_Pos (31U)
3225 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3226 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3227
3228 /******************* Bit definition for CAN_F4R1 register *******************/
3229 #define CAN_F4R1_FB0_Pos (0U)
3230 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3231 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3232 #define CAN_F4R1_FB1_Pos (1U)
3233 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3234 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3235 #define CAN_F4R1_FB2_Pos (2U)
3236 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3237 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3238 #define CAN_F4R1_FB3_Pos (3U)
3239 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3240 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3241 #define CAN_F4R1_FB4_Pos (4U)
3242 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3243 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3244 #define CAN_F4R1_FB5_Pos (5U)
3245 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3246 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3247 #define CAN_F4R1_FB6_Pos (6U)
3248 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3249 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3250 #define CAN_F4R1_FB7_Pos (7U)
3251 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3252 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3253 #define CAN_F4R1_FB8_Pos (8U)
3254 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3255 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3256 #define CAN_F4R1_FB9_Pos (9U)
3257 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3258 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3259 #define CAN_F4R1_FB10_Pos (10U)
3260 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3261 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3262 #define CAN_F4R1_FB11_Pos (11U)
3263 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3264 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3265 #define CAN_F4R1_FB12_Pos (12U)
3266 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3267 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3268 #define CAN_F4R1_FB13_Pos (13U)
3269 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3270 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3271 #define CAN_F4R1_FB14_Pos (14U)
3272 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3273 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3274 #define CAN_F4R1_FB15_Pos (15U)
3275 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3276 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3277 #define CAN_F4R1_FB16_Pos (16U)
3278 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3279 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3280 #define CAN_F4R1_FB17_Pos (17U)
3281 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3282 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3283 #define CAN_F4R1_FB18_Pos (18U)
3284 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3285 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3286 #define CAN_F4R1_FB19_Pos (19U)
3287 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3288 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3289 #define CAN_F4R1_FB20_Pos (20U)
3290 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3291 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3292 #define CAN_F4R1_FB21_Pos (21U)
3293 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3294 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3295 #define CAN_F4R1_FB22_Pos (22U)
3296 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3297 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3298 #define CAN_F4R1_FB23_Pos (23U)
3299 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3300 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3301 #define CAN_F4R1_FB24_Pos (24U)
3302 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3303 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3304 #define CAN_F4R1_FB25_Pos (25U)
3305 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3306 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3307 #define CAN_F4R1_FB26_Pos (26U)
3308 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3309 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3310 #define CAN_F4R1_FB27_Pos (27U)
3311 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3312 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3313 #define CAN_F4R1_FB28_Pos (28U)
3314 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3315 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3316 #define CAN_F4R1_FB29_Pos (29U)
3317 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3318 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3319 #define CAN_F4R1_FB30_Pos (30U)
3320 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3321 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3322 #define CAN_F4R1_FB31_Pos (31U)
3323 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3324 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3325
3326 /******************* Bit definition for CAN_F5R1 register *******************/
3327 #define CAN_F5R1_FB0_Pos (0U)
3328 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3329 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3330 #define CAN_F5R1_FB1_Pos (1U)
3331 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3332 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3333 #define CAN_F5R1_FB2_Pos (2U)
3334 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3335 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3336 #define CAN_F5R1_FB3_Pos (3U)
3337 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3338 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3339 #define CAN_F5R1_FB4_Pos (4U)
3340 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3341 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3342 #define CAN_F5R1_FB5_Pos (5U)
3343 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3344 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3345 #define CAN_F5R1_FB6_Pos (6U)
3346 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3347 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3348 #define CAN_F5R1_FB7_Pos (7U)
3349 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3350 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3351 #define CAN_F5R1_FB8_Pos (8U)
3352 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3353 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3354 #define CAN_F5R1_FB9_Pos (9U)
3355 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3356 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3357 #define CAN_F5R1_FB10_Pos (10U)
3358 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3359 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3360 #define CAN_F5R1_FB11_Pos (11U)
3361 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3362 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3363 #define CAN_F5R1_FB12_Pos (12U)
3364 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3365 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3366 #define CAN_F5R1_FB13_Pos (13U)
3367 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3368 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3369 #define CAN_F5R1_FB14_Pos (14U)
3370 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3371 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3372 #define CAN_F5R1_FB15_Pos (15U)
3373 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3374 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3375 #define CAN_F5R1_FB16_Pos (16U)
3376 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3377 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3378 #define CAN_F5R1_FB17_Pos (17U)
3379 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3380 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3381 #define CAN_F5R1_FB18_Pos (18U)
3382 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3383 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3384 #define CAN_F5R1_FB19_Pos (19U)
3385 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3386 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3387 #define CAN_F5R1_FB20_Pos (20U)
3388 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3389 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3390 #define CAN_F5R1_FB21_Pos (21U)
3391 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3392 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3393 #define CAN_F5R1_FB22_Pos (22U)
3394 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3395 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3396 #define CAN_F5R1_FB23_Pos (23U)
3397 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3398 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3399 #define CAN_F5R1_FB24_Pos (24U)
3400 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3401 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3402 #define CAN_F5R1_FB25_Pos (25U)
3403 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3404 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3405 #define CAN_F5R1_FB26_Pos (26U)
3406 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3407 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3408 #define CAN_F5R1_FB27_Pos (27U)
3409 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3410 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3411 #define CAN_F5R1_FB28_Pos (28U)
3412 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3413 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3414 #define CAN_F5R1_FB29_Pos (29U)
3415 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3416 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3417 #define CAN_F5R1_FB30_Pos (30U)
3418 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3419 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3420 #define CAN_F5R1_FB31_Pos (31U)
3421 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3422 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3423
3424 /******************* Bit definition for CAN_F6R1 register *******************/
3425 #define CAN_F6R1_FB0_Pos (0U)
3426 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3427 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3428 #define CAN_F6R1_FB1_Pos (1U)
3429 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3430 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3431 #define CAN_F6R1_FB2_Pos (2U)
3432 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3433 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3434 #define CAN_F6R1_FB3_Pos (3U)
3435 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3436 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3437 #define CAN_F6R1_FB4_Pos (4U)
3438 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3439 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3440 #define CAN_F6R1_FB5_Pos (5U)
3441 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3442 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3443 #define CAN_F6R1_FB6_Pos (6U)
3444 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3445 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3446 #define CAN_F6R1_FB7_Pos (7U)
3447 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3448 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3449 #define CAN_F6R1_FB8_Pos (8U)
3450 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3451 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3452 #define CAN_F6R1_FB9_Pos (9U)
3453 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3454 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3455 #define CAN_F6R1_FB10_Pos (10U)
3456 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3457 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3458 #define CAN_F6R1_FB11_Pos (11U)
3459 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3460 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3461 #define CAN_F6R1_FB12_Pos (12U)
3462 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3463 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3464 #define CAN_F6R1_FB13_Pos (13U)
3465 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3466 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3467 #define CAN_F6R1_FB14_Pos (14U)
3468 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3469 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3470 #define CAN_F6R1_FB15_Pos (15U)
3471 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3472 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3473 #define CAN_F6R1_FB16_Pos (16U)
3474 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3475 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3476 #define CAN_F6R1_FB17_Pos (17U)
3477 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3478 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3479 #define CAN_F6R1_FB18_Pos (18U)
3480 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3481 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3482 #define CAN_F6R1_FB19_Pos (19U)
3483 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3484 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3485 #define CAN_F6R1_FB20_Pos (20U)
3486 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3487 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3488 #define CAN_F6R1_FB21_Pos (21U)
3489 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3490 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3491 #define CAN_F6R1_FB22_Pos (22U)
3492 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3493 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3494 #define CAN_F6R1_FB23_Pos (23U)
3495 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3496 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3497 #define CAN_F6R1_FB24_Pos (24U)
3498 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3499 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3500 #define CAN_F6R1_FB25_Pos (25U)
3501 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3502 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3503 #define CAN_F6R1_FB26_Pos (26U)
3504 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3505 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3506 #define CAN_F6R1_FB27_Pos (27U)
3507 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3508 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3509 #define CAN_F6R1_FB28_Pos (28U)
3510 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3511 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3512 #define CAN_F6R1_FB29_Pos (29U)
3513 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3514 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3515 #define CAN_F6R1_FB30_Pos (30U)
3516 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3517 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3518 #define CAN_F6R1_FB31_Pos (31U)
3519 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3520 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3521
3522 /******************* Bit definition for CAN_F7R1 register *******************/
3523 #define CAN_F7R1_FB0_Pos (0U)
3524 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3525 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3526 #define CAN_F7R1_FB1_Pos (1U)
3527 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3528 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3529 #define CAN_F7R1_FB2_Pos (2U)
3530 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3531 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3532 #define CAN_F7R1_FB3_Pos (3U)
3533 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3534 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3535 #define CAN_F7R1_FB4_Pos (4U)
3536 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3537 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3538 #define CAN_F7R1_FB5_Pos (5U)
3539 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3540 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3541 #define CAN_F7R1_FB6_Pos (6U)
3542 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3543 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3544 #define CAN_F7R1_FB7_Pos (7U)
3545 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3546 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3547 #define CAN_F7R1_FB8_Pos (8U)
3548 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3549 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3550 #define CAN_F7R1_FB9_Pos (9U)
3551 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3552 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3553 #define CAN_F7R1_FB10_Pos (10U)
3554 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3555 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3556 #define CAN_F7R1_FB11_Pos (11U)
3557 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3558 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3559 #define CAN_F7R1_FB12_Pos (12U)
3560 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3561 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3562 #define CAN_F7R1_FB13_Pos (13U)
3563 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3564 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3565 #define CAN_F7R1_FB14_Pos (14U)
3566 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3567 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3568 #define CAN_F7R1_FB15_Pos (15U)
3569 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3570 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3571 #define CAN_F7R1_FB16_Pos (16U)
3572 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3573 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3574 #define CAN_F7R1_FB17_Pos (17U)
3575 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3576 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3577 #define CAN_F7R1_FB18_Pos (18U)
3578 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3579 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3580 #define CAN_F7R1_FB19_Pos (19U)
3581 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3582 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3583 #define CAN_F7R1_FB20_Pos (20U)
3584 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3585 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3586 #define CAN_F7R1_FB21_Pos (21U)
3587 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3588 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3589 #define CAN_F7R1_FB22_Pos (22U)
3590 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3591 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3592 #define CAN_F7R1_FB23_Pos (23U)
3593 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3594 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3595 #define CAN_F7R1_FB24_Pos (24U)
3596 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3597 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3598 #define CAN_F7R1_FB25_Pos (25U)
3599 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3600 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3601 #define CAN_F7R1_FB26_Pos (26U)
3602 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3603 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3604 #define CAN_F7R1_FB27_Pos (27U)
3605 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3606 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3607 #define CAN_F7R1_FB28_Pos (28U)
3608 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3609 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3610 #define CAN_F7R1_FB29_Pos (29U)
3611 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3612 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3613 #define CAN_F7R1_FB30_Pos (30U)
3614 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3615 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3616 #define CAN_F7R1_FB31_Pos (31U)
3617 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3618 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3619
3620 /******************* Bit definition for CAN_F8R1 register *******************/
3621 #define CAN_F8R1_FB0_Pos (0U)
3622 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3623 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3624 #define CAN_F8R1_FB1_Pos (1U)
3625 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3626 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3627 #define CAN_F8R1_FB2_Pos (2U)
3628 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3629 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3630 #define CAN_F8R1_FB3_Pos (3U)
3631 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3632 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3633 #define CAN_F8R1_FB4_Pos (4U)
3634 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3635 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3636 #define CAN_F8R1_FB5_Pos (5U)
3637 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3638 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3639 #define CAN_F8R1_FB6_Pos (6U)
3640 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3641 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3642 #define CAN_F8R1_FB7_Pos (7U)
3643 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3644 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3645 #define CAN_F8R1_FB8_Pos (8U)
3646 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3647 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3648 #define CAN_F8R1_FB9_Pos (9U)
3649 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3650 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3651 #define CAN_F8R1_FB10_Pos (10U)
3652 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3653 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3654 #define CAN_F8R1_FB11_Pos (11U)
3655 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3656 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3657 #define CAN_F8R1_FB12_Pos (12U)
3658 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3659 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3660 #define CAN_F8R1_FB13_Pos (13U)
3661 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3662 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3663 #define CAN_F8R1_FB14_Pos (14U)
3664 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3665 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3666 #define CAN_F8R1_FB15_Pos (15U)
3667 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3668 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3669 #define CAN_F8R1_FB16_Pos (16U)
3670 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3671 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3672 #define CAN_F8R1_FB17_Pos (17U)
3673 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3674 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3675 #define CAN_F8R1_FB18_Pos (18U)
3676 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3677 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3678 #define CAN_F8R1_FB19_Pos (19U)
3679 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3680 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3681 #define CAN_F8R1_FB20_Pos (20U)
3682 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3683 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3684 #define CAN_F8R1_FB21_Pos (21U)
3685 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3686 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3687 #define CAN_F8R1_FB22_Pos (22U)
3688 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3689 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3690 #define CAN_F8R1_FB23_Pos (23U)
3691 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3692 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3693 #define CAN_F8R1_FB24_Pos (24U)
3694 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3695 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3696 #define CAN_F8R1_FB25_Pos (25U)
3697 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3698 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3699 #define CAN_F8R1_FB26_Pos (26U)
3700 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3701 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3702 #define CAN_F8R1_FB27_Pos (27U)
3703 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3704 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3705 #define CAN_F8R1_FB28_Pos (28U)
3706 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3707 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3708 #define CAN_F8R1_FB29_Pos (29U)
3709 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3710 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3711 #define CAN_F8R1_FB30_Pos (30U)
3712 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3713 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3714 #define CAN_F8R1_FB31_Pos (31U)
3715 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3716 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3717
3718 /******************* Bit definition for CAN_F9R1 register *******************/
3719 #define CAN_F9R1_FB0_Pos (0U)
3720 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3721 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3722 #define CAN_F9R1_FB1_Pos (1U)
3723 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3724 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3725 #define CAN_F9R1_FB2_Pos (2U)
3726 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3727 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3728 #define CAN_F9R1_FB3_Pos (3U)
3729 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3730 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3731 #define CAN_F9R1_FB4_Pos (4U)
3732 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3733 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3734 #define CAN_F9R1_FB5_Pos (5U)
3735 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3736 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3737 #define CAN_F9R1_FB6_Pos (6U)
3738 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3739 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3740 #define CAN_F9R1_FB7_Pos (7U)
3741 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3742 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3743 #define CAN_F9R1_FB8_Pos (8U)
3744 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3745 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3746 #define CAN_F9R1_FB9_Pos (9U)
3747 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3748 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3749 #define CAN_F9R1_FB10_Pos (10U)
3750 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3751 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3752 #define CAN_F9R1_FB11_Pos (11U)
3753 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3754 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3755 #define CAN_F9R1_FB12_Pos (12U)
3756 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3757 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3758 #define CAN_F9R1_FB13_Pos (13U)
3759 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3760 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3761 #define CAN_F9R1_FB14_Pos (14U)
3762 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3763 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3764 #define CAN_F9R1_FB15_Pos (15U)
3765 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3766 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3767 #define CAN_F9R1_FB16_Pos (16U)
3768 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3769 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3770 #define CAN_F9R1_FB17_Pos (17U)
3771 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3772 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3773 #define CAN_F9R1_FB18_Pos (18U)
3774 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3775 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3776 #define CAN_F9R1_FB19_Pos (19U)
3777 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3778 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3779 #define CAN_F9R1_FB20_Pos (20U)
3780 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3781 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3782 #define CAN_F9R1_FB21_Pos (21U)
3783 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3784 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3785 #define CAN_F9R1_FB22_Pos (22U)
3786 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3787 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3788 #define CAN_F9R1_FB23_Pos (23U)
3789 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3790 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3791 #define CAN_F9R1_FB24_Pos (24U)
3792 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3793 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3794 #define CAN_F9R1_FB25_Pos (25U)
3795 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3796 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3797 #define CAN_F9R1_FB26_Pos (26U)
3798 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3799 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3800 #define CAN_F9R1_FB27_Pos (27U)
3801 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3802 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3803 #define CAN_F9R1_FB28_Pos (28U)
3804 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3805 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3806 #define CAN_F9R1_FB29_Pos (29U)
3807 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3808 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3809 #define CAN_F9R1_FB30_Pos (30U)
3810 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3811 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3812 #define CAN_F9R1_FB31_Pos (31U)
3813 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3814 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3815
3816 /******************* Bit definition for CAN_F10R1 register ******************/
3817 #define CAN_F10R1_FB0_Pos (0U)
3818 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3819 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3820 #define CAN_F10R1_FB1_Pos (1U)
3821 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3822 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3823 #define CAN_F10R1_FB2_Pos (2U)
3824 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3825 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3826 #define CAN_F10R1_FB3_Pos (3U)
3827 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3828 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3829 #define CAN_F10R1_FB4_Pos (4U)
3830 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3831 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3832 #define CAN_F10R1_FB5_Pos (5U)
3833 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3834 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3835 #define CAN_F10R1_FB6_Pos (6U)
3836 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3837 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3838 #define CAN_F10R1_FB7_Pos (7U)
3839 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3840 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3841 #define CAN_F10R1_FB8_Pos (8U)
3842 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3843 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3844 #define CAN_F10R1_FB9_Pos (9U)
3845 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3846 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3847 #define CAN_F10R1_FB10_Pos (10U)
3848 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3849 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3850 #define CAN_F10R1_FB11_Pos (11U)
3851 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3852 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3853 #define CAN_F10R1_FB12_Pos (12U)
3854 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3855 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3856 #define CAN_F10R1_FB13_Pos (13U)
3857 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3858 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3859 #define CAN_F10R1_FB14_Pos (14U)
3860 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3861 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3862 #define CAN_F10R1_FB15_Pos (15U)
3863 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3864 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3865 #define CAN_F10R1_FB16_Pos (16U)
3866 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3867 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3868 #define CAN_F10R1_FB17_Pos (17U)
3869 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3870 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3871 #define CAN_F10R1_FB18_Pos (18U)
3872 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3873 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3874 #define CAN_F10R1_FB19_Pos (19U)
3875 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3876 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3877 #define CAN_F10R1_FB20_Pos (20U)
3878 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3879 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3880 #define CAN_F10R1_FB21_Pos (21U)
3881 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3882 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
3883 #define CAN_F10R1_FB22_Pos (22U)
3884 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
3885 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
3886 #define CAN_F10R1_FB23_Pos (23U)
3887 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
3888 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
3889 #define CAN_F10R1_FB24_Pos (24U)
3890 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
3891 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
3892 #define CAN_F10R1_FB25_Pos (25U)
3893 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
3894 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
3895 #define CAN_F10R1_FB26_Pos (26U)
3896 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
3897 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
3898 #define CAN_F10R1_FB27_Pos (27U)
3899 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
3900 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
3901 #define CAN_F10R1_FB28_Pos (28U)
3902 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
3903 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
3904 #define CAN_F10R1_FB29_Pos (29U)
3905 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
3906 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
3907 #define CAN_F10R1_FB30_Pos (30U)
3908 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
3909 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
3910 #define CAN_F10R1_FB31_Pos (31U)
3911 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
3912 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
3913
3914 /******************* Bit definition for CAN_F11R1 register ******************/
3915 #define CAN_F11R1_FB0_Pos (0U)
3916 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
3917 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
3918 #define CAN_F11R1_FB1_Pos (1U)
3919 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
3920 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
3921 #define CAN_F11R1_FB2_Pos (2U)
3922 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
3923 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
3924 #define CAN_F11R1_FB3_Pos (3U)
3925 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
3926 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
3927 #define CAN_F11R1_FB4_Pos (4U)
3928 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
3929 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
3930 #define CAN_F11R1_FB5_Pos (5U)
3931 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
3932 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
3933 #define CAN_F11R1_FB6_Pos (6U)
3934 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
3935 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
3936 #define CAN_F11R1_FB7_Pos (7U)
3937 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
3938 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
3939 #define CAN_F11R1_FB8_Pos (8U)
3940 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
3941 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
3942 #define CAN_F11R1_FB9_Pos (9U)
3943 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
3944 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
3945 #define CAN_F11R1_FB10_Pos (10U)
3946 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
3947 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
3948 #define CAN_F11R1_FB11_Pos (11U)
3949 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
3950 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
3951 #define CAN_F11R1_FB12_Pos (12U)
3952 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
3953 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
3954 #define CAN_F11R1_FB13_Pos (13U)
3955 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
3956 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
3957 #define CAN_F11R1_FB14_Pos (14U)
3958 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
3959 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
3960 #define CAN_F11R1_FB15_Pos (15U)
3961 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
3962 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
3963 #define CAN_F11R1_FB16_Pos (16U)
3964 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
3965 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
3966 #define CAN_F11R1_FB17_Pos (17U)
3967 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
3968 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
3969 #define CAN_F11R1_FB18_Pos (18U)
3970 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
3971 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
3972 #define CAN_F11R1_FB19_Pos (19U)
3973 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
3974 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
3975 #define CAN_F11R1_FB20_Pos (20U)
3976 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
3977 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
3978 #define CAN_F11R1_FB21_Pos (21U)
3979 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
3980 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
3981 #define CAN_F11R1_FB22_Pos (22U)
3982 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
3983 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
3984 #define CAN_F11R1_FB23_Pos (23U)
3985 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
3986 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
3987 #define CAN_F11R1_FB24_Pos (24U)
3988 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
3989 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
3990 #define CAN_F11R1_FB25_Pos (25U)
3991 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
3992 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
3993 #define CAN_F11R1_FB26_Pos (26U)
3994 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
3995 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
3996 #define CAN_F11R1_FB27_Pos (27U)
3997 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
3998 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
3999 #define CAN_F11R1_FB28_Pos (28U)
4000 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4001 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4002 #define CAN_F11R1_FB29_Pos (29U)
4003 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4004 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4005 #define CAN_F11R1_FB30_Pos (30U)
4006 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4007 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4008 #define CAN_F11R1_FB31_Pos (31U)
4009 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4010 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4011
4012 /******************* Bit definition for CAN_F12R1 register ******************/
4013 #define CAN_F12R1_FB0_Pos (0U)
4014 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4015 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4016 #define CAN_F12R1_FB1_Pos (1U)
4017 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4018 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4019 #define CAN_F12R1_FB2_Pos (2U)
4020 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4021 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4022 #define CAN_F12R1_FB3_Pos (3U)
4023 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4024 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4025 #define CAN_F12R1_FB4_Pos (4U)
4026 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4027 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4028 #define CAN_F12R1_FB5_Pos (5U)
4029 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4030 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4031 #define CAN_F12R1_FB6_Pos (6U)
4032 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4033 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4034 #define CAN_F12R1_FB7_Pos (7U)
4035 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4036 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4037 #define CAN_F12R1_FB8_Pos (8U)
4038 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4039 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4040 #define CAN_F12R1_FB9_Pos (9U)
4041 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4042 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4043 #define CAN_F12R1_FB10_Pos (10U)
4044 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4045 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4046 #define CAN_F12R1_FB11_Pos (11U)
4047 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4048 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4049 #define CAN_F12R1_FB12_Pos (12U)
4050 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4051 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4052 #define CAN_F12R1_FB13_Pos (13U)
4053 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4054 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4055 #define CAN_F12R1_FB14_Pos (14U)
4056 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4057 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4058 #define CAN_F12R1_FB15_Pos (15U)
4059 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4060 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4061 #define CAN_F12R1_FB16_Pos (16U)
4062 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4063 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4064 #define CAN_F12R1_FB17_Pos (17U)
4065 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4066 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4067 #define CAN_F12R1_FB18_Pos (18U)
4068 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4069 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4070 #define CAN_F12R1_FB19_Pos (19U)
4071 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4072 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4073 #define CAN_F12R1_FB20_Pos (20U)
4074 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4075 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4076 #define CAN_F12R1_FB21_Pos (21U)
4077 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4078 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4079 #define CAN_F12R1_FB22_Pos (22U)
4080 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4081 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4082 #define CAN_F12R1_FB23_Pos (23U)
4083 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4084 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4085 #define CAN_F12R1_FB24_Pos (24U)
4086 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4087 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4088 #define CAN_F12R1_FB25_Pos (25U)
4089 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4090 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4091 #define CAN_F12R1_FB26_Pos (26U)
4092 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4093 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4094 #define CAN_F12R1_FB27_Pos (27U)
4095 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4096 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4097 #define CAN_F12R1_FB28_Pos (28U)
4098 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4099 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4100 #define CAN_F12R1_FB29_Pos (29U)
4101 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4102 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4103 #define CAN_F12R1_FB30_Pos (30U)
4104 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4105 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4106 #define CAN_F12R1_FB31_Pos (31U)
4107 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4108 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4109
4110 /******************* Bit definition for CAN_F13R1 register ******************/
4111 #define CAN_F13R1_FB0_Pos (0U)
4112 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4113 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4114 #define CAN_F13R1_FB1_Pos (1U)
4115 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4116 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4117 #define CAN_F13R1_FB2_Pos (2U)
4118 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4119 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4120 #define CAN_F13R1_FB3_Pos (3U)
4121 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4122 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4123 #define CAN_F13R1_FB4_Pos (4U)
4124 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4125 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4126 #define CAN_F13R1_FB5_Pos (5U)
4127 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4128 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4129 #define CAN_F13R1_FB6_Pos (6U)
4130 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4131 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4132 #define CAN_F13R1_FB7_Pos (7U)
4133 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4134 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4135 #define CAN_F13R1_FB8_Pos (8U)
4136 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4137 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4138 #define CAN_F13R1_FB9_Pos (9U)
4139 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4140 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4141 #define CAN_F13R1_FB10_Pos (10U)
4142 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4143 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4144 #define CAN_F13R1_FB11_Pos (11U)
4145 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4146 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4147 #define CAN_F13R1_FB12_Pos (12U)
4148 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4149 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4150 #define CAN_F13R1_FB13_Pos (13U)
4151 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4152 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4153 #define CAN_F13R1_FB14_Pos (14U)
4154 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4155 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4156 #define CAN_F13R1_FB15_Pos (15U)
4157 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4158 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4159 #define CAN_F13R1_FB16_Pos (16U)
4160 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4161 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4162 #define CAN_F13R1_FB17_Pos (17U)
4163 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4164 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4165 #define CAN_F13R1_FB18_Pos (18U)
4166 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4167 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4168 #define CAN_F13R1_FB19_Pos (19U)
4169 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4170 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4171 #define CAN_F13R1_FB20_Pos (20U)
4172 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4173 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4174 #define CAN_F13R1_FB21_Pos (21U)
4175 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4176 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4177 #define CAN_F13R1_FB22_Pos (22U)
4178 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4179 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4180 #define CAN_F13R1_FB23_Pos (23U)
4181 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4182 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4183 #define CAN_F13R1_FB24_Pos (24U)
4184 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4185 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4186 #define CAN_F13R1_FB25_Pos (25U)
4187 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4188 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4189 #define CAN_F13R1_FB26_Pos (26U)
4190 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4191 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4192 #define CAN_F13R1_FB27_Pos (27U)
4193 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4194 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4195 #define CAN_F13R1_FB28_Pos (28U)
4196 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4197 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4198 #define CAN_F13R1_FB29_Pos (29U)
4199 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4200 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4201 #define CAN_F13R1_FB30_Pos (30U)
4202 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4203 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4204 #define CAN_F13R1_FB31_Pos (31U)
4205 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4206 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4207
4208 /******************* Bit definition for CAN_F0R2 register *******************/
4209 #define CAN_F0R2_FB0_Pos (0U)
4210 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4211 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4212 #define CAN_F0R2_FB1_Pos (1U)
4213 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4214 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4215 #define CAN_F0R2_FB2_Pos (2U)
4216 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4217 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4218 #define CAN_F0R2_FB3_Pos (3U)
4219 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4220 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4221 #define CAN_F0R2_FB4_Pos (4U)
4222 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4223 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4224 #define CAN_F0R2_FB5_Pos (5U)
4225 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4226 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4227 #define CAN_F0R2_FB6_Pos (6U)
4228 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4229 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4230 #define CAN_F0R2_FB7_Pos (7U)
4231 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4232 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4233 #define CAN_F0R2_FB8_Pos (8U)
4234 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4235 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4236 #define CAN_F0R2_FB9_Pos (9U)
4237 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4238 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4239 #define CAN_F0R2_FB10_Pos (10U)
4240 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4241 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4242 #define CAN_F0R2_FB11_Pos (11U)
4243 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4244 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4245 #define CAN_F0R2_FB12_Pos (12U)
4246 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4247 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4248 #define CAN_F0R2_FB13_Pos (13U)
4249 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4250 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4251 #define CAN_F0R2_FB14_Pos (14U)
4252 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4253 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4254 #define CAN_F0R2_FB15_Pos (15U)
4255 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4256 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4257 #define CAN_F0R2_FB16_Pos (16U)
4258 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4259 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4260 #define CAN_F0R2_FB17_Pos (17U)
4261 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4262 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4263 #define CAN_F0R2_FB18_Pos (18U)
4264 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4265 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4266 #define CAN_F0R2_FB19_Pos (19U)
4267 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4268 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4269 #define CAN_F0R2_FB20_Pos (20U)
4270 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4271 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4272 #define CAN_F0R2_FB21_Pos (21U)
4273 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4274 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4275 #define CAN_F0R2_FB22_Pos (22U)
4276 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4277 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4278 #define CAN_F0R2_FB23_Pos (23U)
4279 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4280 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4281 #define CAN_F0R2_FB24_Pos (24U)
4282 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4283 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4284 #define CAN_F0R2_FB25_Pos (25U)
4285 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4286 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4287 #define CAN_F0R2_FB26_Pos (26U)
4288 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4289 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4290 #define CAN_F0R2_FB27_Pos (27U)
4291 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4292 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4293 #define CAN_F0R2_FB28_Pos (28U)
4294 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4295 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4296 #define CAN_F0R2_FB29_Pos (29U)
4297 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4298 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4299 #define CAN_F0R2_FB30_Pos (30U)
4300 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4301 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4302 #define CAN_F0R2_FB31_Pos (31U)
4303 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4304 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4305
4306 /******************* Bit definition for CAN_F1R2 register *******************/
4307 #define CAN_F1R2_FB0_Pos (0U)
4308 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4309 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4310 #define CAN_F1R2_FB1_Pos (1U)
4311 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4312 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4313 #define CAN_F1R2_FB2_Pos (2U)
4314 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4315 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4316 #define CAN_F1R2_FB3_Pos (3U)
4317 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4318 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4319 #define CAN_F1R2_FB4_Pos (4U)
4320 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4321 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4322 #define CAN_F1R2_FB5_Pos (5U)
4323 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4324 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4325 #define CAN_F1R2_FB6_Pos (6U)
4326 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4327 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4328 #define CAN_F1R2_FB7_Pos (7U)
4329 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4330 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4331 #define CAN_F1R2_FB8_Pos (8U)
4332 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4333 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4334 #define CAN_F1R2_FB9_Pos (9U)
4335 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4336 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4337 #define CAN_F1R2_FB10_Pos (10U)
4338 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4339 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4340 #define CAN_F1R2_FB11_Pos (11U)
4341 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4342 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4343 #define CAN_F1R2_FB12_Pos (12U)
4344 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4345 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4346 #define CAN_F1R2_FB13_Pos (13U)
4347 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4348 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4349 #define CAN_F1R2_FB14_Pos (14U)
4350 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4351 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4352 #define CAN_F1R2_FB15_Pos (15U)
4353 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4354 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4355 #define CAN_F1R2_FB16_Pos (16U)
4356 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4357 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4358 #define CAN_F1R2_FB17_Pos (17U)
4359 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4360 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4361 #define CAN_F1R2_FB18_Pos (18U)
4362 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4363 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4364 #define CAN_F1R2_FB19_Pos (19U)
4365 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4366 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4367 #define CAN_F1R2_FB20_Pos (20U)
4368 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4369 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4370 #define CAN_F1R2_FB21_Pos (21U)
4371 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4372 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4373 #define CAN_F1R2_FB22_Pos (22U)
4374 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4375 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4376 #define CAN_F1R2_FB23_Pos (23U)
4377 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4378 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4379 #define CAN_F1R2_FB24_Pos (24U)
4380 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4381 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4382 #define CAN_F1R2_FB25_Pos (25U)
4383 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4384 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4385 #define CAN_F1R2_FB26_Pos (26U)
4386 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4387 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4388 #define CAN_F1R2_FB27_Pos (27U)
4389 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4390 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4391 #define CAN_F1R2_FB28_Pos (28U)
4392 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4393 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4394 #define CAN_F1R2_FB29_Pos (29U)
4395 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4396 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4397 #define CAN_F1R2_FB30_Pos (30U)
4398 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4399 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4400 #define CAN_F1R2_FB31_Pos (31U)
4401 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4402 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4403
4404 /******************* Bit definition for CAN_F2R2 register *******************/
4405 #define CAN_F2R2_FB0_Pos (0U)
4406 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4407 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4408 #define CAN_F2R2_FB1_Pos (1U)
4409 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4410 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4411 #define CAN_F2R2_FB2_Pos (2U)
4412 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4413 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4414 #define CAN_F2R2_FB3_Pos (3U)
4415 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4416 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4417 #define CAN_F2R2_FB4_Pos (4U)
4418 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4419 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4420 #define CAN_F2R2_FB5_Pos (5U)
4421 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4422 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4423 #define CAN_F2R2_FB6_Pos (6U)
4424 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4425 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4426 #define CAN_F2R2_FB7_Pos (7U)
4427 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4428 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4429 #define CAN_F2R2_FB8_Pos (8U)
4430 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4431 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4432 #define CAN_F2R2_FB9_Pos (9U)
4433 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4434 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4435 #define CAN_F2R2_FB10_Pos (10U)
4436 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4437 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4438 #define CAN_F2R2_FB11_Pos (11U)
4439 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4440 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4441 #define CAN_F2R2_FB12_Pos (12U)
4442 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4443 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4444 #define CAN_F2R2_FB13_Pos (13U)
4445 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4446 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4447 #define CAN_F2R2_FB14_Pos (14U)
4448 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4449 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4450 #define CAN_F2R2_FB15_Pos (15U)
4451 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4452 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4453 #define CAN_F2R2_FB16_Pos (16U)
4454 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4455 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4456 #define CAN_F2R2_FB17_Pos (17U)
4457 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4458 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4459 #define CAN_F2R2_FB18_Pos (18U)
4460 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4461 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4462 #define CAN_F2R2_FB19_Pos (19U)
4463 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4464 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4465 #define CAN_F2R2_FB20_Pos (20U)
4466 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4467 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4468 #define CAN_F2R2_FB21_Pos (21U)
4469 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4470 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4471 #define CAN_F2R2_FB22_Pos (22U)
4472 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4473 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4474 #define CAN_F2R2_FB23_Pos (23U)
4475 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4476 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4477 #define CAN_F2R2_FB24_Pos (24U)
4478 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4479 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4480 #define CAN_F2R2_FB25_Pos (25U)
4481 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4482 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4483 #define CAN_F2R2_FB26_Pos (26U)
4484 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4485 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4486 #define CAN_F2R2_FB27_Pos (27U)
4487 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4488 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4489 #define CAN_F2R2_FB28_Pos (28U)
4490 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4491 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4492 #define CAN_F2R2_FB29_Pos (29U)
4493 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4494 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4495 #define CAN_F2R2_FB30_Pos (30U)
4496 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4497 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4498 #define CAN_F2R2_FB31_Pos (31U)
4499 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4500 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4501
4502 /******************* Bit definition for CAN_F3R2 register *******************/
4503 #define CAN_F3R2_FB0_Pos (0U)
4504 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4505 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4506 #define CAN_F3R2_FB1_Pos (1U)
4507 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4508 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4509 #define CAN_F3R2_FB2_Pos (2U)
4510 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4511 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4512 #define CAN_F3R2_FB3_Pos (3U)
4513 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4514 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4515 #define CAN_F3R2_FB4_Pos (4U)
4516 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4517 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4518 #define CAN_F3R2_FB5_Pos (5U)
4519 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4520 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4521 #define CAN_F3R2_FB6_Pos (6U)
4522 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4523 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4524 #define CAN_F3R2_FB7_Pos (7U)
4525 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4526 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4527 #define CAN_F3R2_FB8_Pos (8U)
4528 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4529 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4530 #define CAN_F3R2_FB9_Pos (9U)
4531 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4532 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4533 #define CAN_F3R2_FB10_Pos (10U)
4534 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4535 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4536 #define CAN_F3R2_FB11_Pos (11U)
4537 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4538 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4539 #define CAN_F3R2_FB12_Pos (12U)
4540 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4541 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4542 #define CAN_F3R2_FB13_Pos (13U)
4543 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4544 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4545 #define CAN_F3R2_FB14_Pos (14U)
4546 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4547 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4548 #define CAN_F3R2_FB15_Pos (15U)
4549 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4550 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4551 #define CAN_F3R2_FB16_Pos (16U)
4552 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4553 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4554 #define CAN_F3R2_FB17_Pos (17U)
4555 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4556 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4557 #define CAN_F3R2_FB18_Pos (18U)
4558 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4559 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4560 #define CAN_F3R2_FB19_Pos (19U)
4561 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4562 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4563 #define CAN_F3R2_FB20_Pos (20U)
4564 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4565 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4566 #define CAN_F3R2_FB21_Pos (21U)
4567 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4568 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4569 #define CAN_F3R2_FB22_Pos (22U)
4570 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4571 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4572 #define CAN_F3R2_FB23_Pos (23U)
4573 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4574 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4575 #define CAN_F3R2_FB24_Pos (24U)
4576 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4577 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4578 #define CAN_F3R2_FB25_Pos (25U)
4579 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4580 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4581 #define CAN_F3R2_FB26_Pos (26U)
4582 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4583 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4584 #define CAN_F3R2_FB27_Pos (27U)
4585 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4586 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4587 #define CAN_F3R2_FB28_Pos (28U)
4588 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4589 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4590 #define CAN_F3R2_FB29_Pos (29U)
4591 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4592 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4593 #define CAN_F3R2_FB30_Pos (30U)
4594 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4595 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4596 #define CAN_F3R2_FB31_Pos (31U)
4597 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4598 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4599
4600 /******************* Bit definition for CAN_F4R2 register *******************/
4601 #define CAN_F4R2_FB0_Pos (0U)
4602 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4603 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4604 #define CAN_F4R2_FB1_Pos (1U)
4605 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4606 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4607 #define CAN_F4R2_FB2_Pos (2U)
4608 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4609 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4610 #define CAN_F4R2_FB3_Pos (3U)
4611 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4612 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4613 #define CAN_F4R2_FB4_Pos (4U)
4614 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4615 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4616 #define CAN_F4R2_FB5_Pos (5U)
4617 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4618 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4619 #define CAN_F4R2_FB6_Pos (6U)
4620 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4621 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4622 #define CAN_F4R2_FB7_Pos (7U)
4623 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4624 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4625 #define CAN_F4R2_FB8_Pos (8U)
4626 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4627 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4628 #define CAN_F4R2_FB9_Pos (9U)
4629 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4630 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4631 #define CAN_F4R2_FB10_Pos (10U)
4632 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4633 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4634 #define CAN_F4R2_FB11_Pos (11U)
4635 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4636 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4637 #define CAN_F4R2_FB12_Pos (12U)
4638 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4639 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4640 #define CAN_F4R2_FB13_Pos (13U)
4641 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4642 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4643 #define CAN_F4R2_FB14_Pos (14U)
4644 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4645 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4646 #define CAN_F4R2_FB15_Pos (15U)
4647 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4648 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4649 #define CAN_F4R2_FB16_Pos (16U)
4650 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4651 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4652 #define CAN_F4R2_FB17_Pos (17U)
4653 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4654 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4655 #define CAN_F4R2_FB18_Pos (18U)
4656 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4657 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4658 #define CAN_F4R2_FB19_Pos (19U)
4659 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4660 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4661 #define CAN_F4R2_FB20_Pos (20U)
4662 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4663 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4664 #define CAN_F4R2_FB21_Pos (21U)
4665 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4666 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4667 #define CAN_F4R2_FB22_Pos (22U)
4668 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4669 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4670 #define CAN_F4R2_FB23_Pos (23U)
4671 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4672 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4673 #define CAN_F4R2_FB24_Pos (24U)
4674 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4675 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4676 #define CAN_F4R2_FB25_Pos (25U)
4677 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4678 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4679 #define CAN_F4R2_FB26_Pos (26U)
4680 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4681 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4682 #define CAN_F4R2_FB27_Pos (27U)
4683 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4684 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4685 #define CAN_F4R2_FB28_Pos (28U)
4686 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4687 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4688 #define CAN_F4R2_FB29_Pos (29U)
4689 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4690 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4691 #define CAN_F4R2_FB30_Pos (30U)
4692 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4693 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4694 #define CAN_F4R2_FB31_Pos (31U)
4695 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4696 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4697
4698 /******************* Bit definition for CAN_F5R2 register *******************/
4699 #define CAN_F5R2_FB0_Pos (0U)
4700 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4701 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4702 #define CAN_F5R2_FB1_Pos (1U)
4703 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4704 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4705 #define CAN_F5R2_FB2_Pos (2U)
4706 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4707 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4708 #define CAN_F5R2_FB3_Pos (3U)
4709 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4710 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4711 #define CAN_F5R2_FB4_Pos (4U)
4712 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4713 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4714 #define CAN_F5R2_FB5_Pos (5U)
4715 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4716 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4717 #define CAN_F5R2_FB6_Pos (6U)
4718 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4719 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4720 #define CAN_F5R2_FB7_Pos (7U)
4721 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4722 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4723 #define CAN_F5R2_FB8_Pos (8U)
4724 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4725 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4726 #define CAN_F5R2_FB9_Pos (9U)
4727 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4728 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4729 #define CAN_F5R2_FB10_Pos (10U)
4730 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4731 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4732 #define CAN_F5R2_FB11_Pos (11U)
4733 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4734 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4735 #define CAN_F5R2_FB12_Pos (12U)
4736 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4737 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4738 #define CAN_F5R2_FB13_Pos (13U)
4739 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4740 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4741 #define CAN_F5R2_FB14_Pos (14U)
4742 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4743 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4744 #define CAN_F5R2_FB15_Pos (15U)
4745 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4746 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4747 #define CAN_F5R2_FB16_Pos (16U)
4748 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4749 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4750 #define CAN_F5R2_FB17_Pos (17U)
4751 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4752 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4753 #define CAN_F5R2_FB18_Pos (18U)
4754 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4755 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4756 #define CAN_F5R2_FB19_Pos (19U)
4757 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4758 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4759 #define CAN_F5R2_FB20_Pos (20U)
4760 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4761 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4762 #define CAN_F5R2_FB21_Pos (21U)
4763 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4764 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4765 #define CAN_F5R2_FB22_Pos (22U)
4766 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4767 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4768 #define CAN_F5R2_FB23_Pos (23U)
4769 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4770 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4771 #define CAN_F5R2_FB24_Pos (24U)
4772 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4773 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4774 #define CAN_F5R2_FB25_Pos (25U)
4775 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4776 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4777 #define CAN_F5R2_FB26_Pos (26U)
4778 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4779 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4780 #define CAN_F5R2_FB27_Pos (27U)
4781 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4782 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4783 #define CAN_F5R2_FB28_Pos (28U)
4784 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4785 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4786 #define CAN_F5R2_FB29_Pos (29U)
4787 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4788 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4789 #define CAN_F5R2_FB30_Pos (30U)
4790 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4791 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4792 #define CAN_F5R2_FB31_Pos (31U)
4793 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4794 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4795
4796 /******************* Bit definition for CAN_F6R2 register *******************/
4797 #define CAN_F6R2_FB0_Pos (0U)
4798 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4799 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4800 #define CAN_F6R2_FB1_Pos (1U)
4801 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4802 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4803 #define CAN_F6R2_FB2_Pos (2U)
4804 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4805 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4806 #define CAN_F6R2_FB3_Pos (3U)
4807 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4808 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4809 #define CAN_F6R2_FB4_Pos (4U)
4810 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4811 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4812 #define CAN_F6R2_FB5_Pos (5U)
4813 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4814 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4815 #define CAN_F6R2_FB6_Pos (6U)
4816 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4817 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4818 #define CAN_F6R2_FB7_Pos (7U)
4819 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4820 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4821 #define CAN_F6R2_FB8_Pos (8U)
4822 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4823 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4824 #define CAN_F6R2_FB9_Pos (9U)
4825 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4826 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4827 #define CAN_F6R2_FB10_Pos (10U)
4828 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4829 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4830 #define CAN_F6R2_FB11_Pos (11U)
4831 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4832 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4833 #define CAN_F6R2_FB12_Pos (12U)
4834 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4835 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4836 #define CAN_F6R2_FB13_Pos (13U)
4837 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4838 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4839 #define CAN_F6R2_FB14_Pos (14U)
4840 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4841 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4842 #define CAN_F6R2_FB15_Pos (15U)
4843 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4844 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4845 #define CAN_F6R2_FB16_Pos (16U)
4846 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4847 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4848 #define CAN_F6R2_FB17_Pos (17U)
4849 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4850 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4851 #define CAN_F6R2_FB18_Pos (18U)
4852 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4853 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4854 #define CAN_F6R2_FB19_Pos (19U)
4855 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4856 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4857 #define CAN_F6R2_FB20_Pos (20U)
4858 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4859 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4860 #define CAN_F6R2_FB21_Pos (21U)
4861 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4862 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4863 #define CAN_F6R2_FB22_Pos (22U)
4864 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4865 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4866 #define CAN_F6R2_FB23_Pos (23U)
4867 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4868 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4869 #define CAN_F6R2_FB24_Pos (24U)
4870 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4871 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4872 #define CAN_F6R2_FB25_Pos (25U)
4873 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4874 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4875 #define CAN_F6R2_FB26_Pos (26U)
4876 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4877 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4878 #define CAN_F6R2_FB27_Pos (27U)
4879 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4880 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4881 #define CAN_F6R2_FB28_Pos (28U)
4882 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
4883 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
4884 #define CAN_F6R2_FB29_Pos (29U)
4885 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
4886 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
4887 #define CAN_F6R2_FB30_Pos (30U)
4888 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
4889 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
4890 #define CAN_F6R2_FB31_Pos (31U)
4891 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
4892 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
4893
4894 /******************* Bit definition for CAN_F7R2 register *******************/
4895 #define CAN_F7R2_FB0_Pos (0U)
4896 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
4897 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
4898 #define CAN_F7R2_FB1_Pos (1U)
4899 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
4900 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
4901 #define CAN_F7R2_FB2_Pos (2U)
4902 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
4903 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
4904 #define CAN_F7R2_FB3_Pos (3U)
4905 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
4906 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
4907 #define CAN_F7R2_FB4_Pos (4U)
4908 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
4909 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
4910 #define CAN_F7R2_FB5_Pos (5U)
4911 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
4912 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
4913 #define CAN_F7R2_FB6_Pos (6U)
4914 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
4915 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
4916 #define CAN_F7R2_FB7_Pos (7U)
4917 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
4918 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
4919 #define CAN_F7R2_FB8_Pos (8U)
4920 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
4921 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
4922 #define CAN_F7R2_FB9_Pos (9U)
4923 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
4924 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
4925 #define CAN_F7R2_FB10_Pos (10U)
4926 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
4927 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
4928 #define CAN_F7R2_FB11_Pos (11U)
4929 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
4930 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
4931 #define CAN_F7R2_FB12_Pos (12U)
4932 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
4933 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
4934 #define CAN_F7R2_FB13_Pos (13U)
4935 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
4936 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
4937 #define CAN_F7R2_FB14_Pos (14U)
4938 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
4939 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
4940 #define CAN_F7R2_FB15_Pos (15U)
4941 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
4942 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
4943 #define CAN_F7R2_FB16_Pos (16U)
4944 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
4945 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
4946 #define CAN_F7R2_FB17_Pos (17U)
4947 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
4948 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
4949 #define CAN_F7R2_FB18_Pos (18U)
4950 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
4951 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
4952 #define CAN_F7R2_FB19_Pos (19U)
4953 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
4954 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
4955 #define CAN_F7R2_FB20_Pos (20U)
4956 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
4957 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
4958 #define CAN_F7R2_FB21_Pos (21U)
4959 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
4960 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
4961 #define CAN_F7R2_FB22_Pos (22U)
4962 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
4963 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
4964 #define CAN_F7R2_FB23_Pos (23U)
4965 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
4966 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
4967 #define CAN_F7R2_FB24_Pos (24U)
4968 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
4969 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
4970 #define CAN_F7R2_FB25_Pos (25U)
4971 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
4972 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
4973 #define CAN_F7R2_FB26_Pos (26U)
4974 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
4975 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
4976 #define CAN_F7R2_FB27_Pos (27U)
4977 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
4978 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
4979 #define CAN_F7R2_FB28_Pos (28U)
4980 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
4981 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
4982 #define CAN_F7R2_FB29_Pos (29U)
4983 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
4984 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
4985 #define CAN_F7R2_FB30_Pos (30U)
4986 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
4987 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
4988 #define CAN_F7R2_FB31_Pos (31U)
4989 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
4990 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
4991
4992 /******************* Bit definition for CAN_F8R2 register *******************/
4993 #define CAN_F8R2_FB0_Pos (0U)
4994 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
4995 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
4996 #define CAN_F8R2_FB1_Pos (1U)
4997 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
4998 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
4999 #define CAN_F8R2_FB2_Pos (2U)
5000 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5001 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5002 #define CAN_F8R2_FB3_Pos (3U)
5003 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5004 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5005 #define CAN_F8R2_FB4_Pos (4U)
5006 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5007 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5008 #define CAN_F8R2_FB5_Pos (5U)
5009 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5010 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5011 #define CAN_F8R2_FB6_Pos (6U)
5012 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5013 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5014 #define CAN_F8R2_FB7_Pos (7U)
5015 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5016 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5017 #define CAN_F8R2_FB8_Pos (8U)
5018 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5019 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5020 #define CAN_F8R2_FB9_Pos (9U)
5021 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5022 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5023 #define CAN_F8R2_FB10_Pos (10U)
5024 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5025 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5026 #define CAN_F8R2_FB11_Pos (11U)
5027 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5028 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5029 #define CAN_F8R2_FB12_Pos (12U)
5030 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5031 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5032 #define CAN_F8R2_FB13_Pos (13U)
5033 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5034 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5035 #define CAN_F8R2_FB14_Pos (14U)
5036 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5037 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5038 #define CAN_F8R2_FB15_Pos (15U)
5039 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5040 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5041 #define CAN_F8R2_FB16_Pos (16U)
5042 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5043 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5044 #define CAN_F8R2_FB17_Pos (17U)
5045 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5046 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5047 #define CAN_F8R2_FB18_Pos (18U)
5048 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5049 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5050 #define CAN_F8R2_FB19_Pos (19U)
5051 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5052 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5053 #define CAN_F8R2_FB20_Pos (20U)
5054 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5055 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5056 #define CAN_F8R2_FB21_Pos (21U)
5057 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5058 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5059 #define CAN_F8R2_FB22_Pos (22U)
5060 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5061 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5062 #define CAN_F8R2_FB23_Pos (23U)
5063 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5064 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5065 #define CAN_F8R2_FB24_Pos (24U)
5066 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5067 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5068 #define CAN_F8R2_FB25_Pos (25U)
5069 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5070 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5071 #define CAN_F8R2_FB26_Pos (26U)
5072 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5073 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5074 #define CAN_F8R2_FB27_Pos (27U)
5075 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5076 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5077 #define CAN_F8R2_FB28_Pos (28U)
5078 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5079 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5080 #define CAN_F8R2_FB29_Pos (29U)
5081 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5082 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5083 #define CAN_F8R2_FB30_Pos (30U)
5084 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5085 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5086 #define CAN_F8R2_FB31_Pos (31U)
5087 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5088 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5089
5090 /******************* Bit definition for CAN_F9R2 register *******************/
5091 #define CAN_F9R2_FB0_Pos (0U)
5092 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5093 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5094 #define CAN_F9R2_FB1_Pos (1U)
5095 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5096 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5097 #define CAN_F9R2_FB2_Pos (2U)
5098 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5099 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5100 #define CAN_F9R2_FB3_Pos (3U)
5101 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5102 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5103 #define CAN_F9R2_FB4_Pos (4U)
5104 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5105 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5106 #define CAN_F9R2_FB5_Pos (5U)
5107 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5108 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5109 #define CAN_F9R2_FB6_Pos (6U)
5110 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5111 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5112 #define CAN_F9R2_FB7_Pos (7U)
5113 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5114 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5115 #define CAN_F9R2_FB8_Pos (8U)
5116 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5117 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5118 #define CAN_F9R2_FB9_Pos (9U)
5119 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5120 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5121 #define CAN_F9R2_FB10_Pos (10U)
5122 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5123 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5124 #define CAN_F9R2_FB11_Pos (11U)
5125 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5126 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5127 #define CAN_F9R2_FB12_Pos (12U)
5128 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5129 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5130 #define CAN_F9R2_FB13_Pos (13U)
5131 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5132 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5133 #define CAN_F9R2_FB14_Pos (14U)
5134 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5135 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5136 #define CAN_F9R2_FB15_Pos (15U)
5137 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5138 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5139 #define CAN_F9R2_FB16_Pos (16U)
5140 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5141 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5142 #define CAN_F9R2_FB17_Pos (17U)
5143 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5144 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5145 #define CAN_F9R2_FB18_Pos (18U)
5146 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5147 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5148 #define CAN_F9R2_FB19_Pos (19U)
5149 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5150 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5151 #define CAN_F9R2_FB20_Pos (20U)
5152 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5153 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5154 #define CAN_F9R2_FB21_Pos (21U)
5155 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5156 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5157 #define CAN_F9R2_FB22_Pos (22U)
5158 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5159 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5160 #define CAN_F9R2_FB23_Pos (23U)
5161 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5162 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5163 #define CAN_F9R2_FB24_Pos (24U)
5164 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5165 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5166 #define CAN_F9R2_FB25_Pos (25U)
5167 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5168 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5169 #define CAN_F9R2_FB26_Pos (26U)
5170 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5171 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5172 #define CAN_F9R2_FB27_Pos (27U)
5173 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5174 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5175 #define CAN_F9R2_FB28_Pos (28U)
5176 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5177 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5178 #define CAN_F9R2_FB29_Pos (29U)
5179 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5180 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5181 #define CAN_F9R2_FB30_Pos (30U)
5182 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5183 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5184 #define CAN_F9R2_FB31_Pos (31U)
5185 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5186 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5187
5188 /******************* Bit definition for CAN_F10R2 register ******************/
5189 #define CAN_F10R2_FB0_Pos (0U)
5190 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5191 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5192 #define CAN_F10R2_FB1_Pos (1U)
5193 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5194 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5195 #define CAN_F10R2_FB2_Pos (2U)
5196 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5197 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5198 #define CAN_F10R2_FB3_Pos (3U)
5199 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5200 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5201 #define CAN_F10R2_FB4_Pos (4U)
5202 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5203 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5204 #define CAN_F10R2_FB5_Pos (5U)
5205 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5206 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5207 #define CAN_F10R2_FB6_Pos (6U)
5208 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5209 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5210 #define CAN_F10R2_FB7_Pos (7U)
5211 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5212 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5213 #define CAN_F10R2_FB8_Pos (8U)
5214 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5215 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5216 #define CAN_F10R2_FB9_Pos (9U)
5217 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5218 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5219 #define CAN_F10R2_FB10_Pos (10U)
5220 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5221 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5222 #define CAN_F10R2_FB11_Pos (11U)
5223 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5224 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5225 #define CAN_F10R2_FB12_Pos (12U)
5226 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5227 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5228 #define CAN_F10R2_FB13_Pos (13U)
5229 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5230 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5231 #define CAN_F10R2_FB14_Pos (14U)
5232 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5233 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5234 #define CAN_F10R2_FB15_Pos (15U)
5235 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5236 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5237 #define CAN_F10R2_FB16_Pos (16U)
5238 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5239 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5240 #define CAN_F10R2_FB17_Pos (17U)
5241 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5242 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5243 #define CAN_F10R2_FB18_Pos (18U)
5244 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5245 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5246 #define CAN_F10R2_FB19_Pos (19U)
5247 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5248 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5249 #define CAN_F10R2_FB20_Pos (20U)
5250 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5251 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5252 #define CAN_F10R2_FB21_Pos (21U)
5253 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5254 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5255 #define CAN_F10R2_FB22_Pos (22U)
5256 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5257 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5258 #define CAN_F10R2_FB23_Pos (23U)
5259 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5260 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5261 #define CAN_F10R2_FB24_Pos (24U)
5262 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5263 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5264 #define CAN_F10R2_FB25_Pos (25U)
5265 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5266 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5267 #define CAN_F10R2_FB26_Pos (26U)
5268 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5269 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5270 #define CAN_F10R2_FB27_Pos (27U)
5271 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5272 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5273 #define CAN_F10R2_FB28_Pos (28U)
5274 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5275 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5276 #define CAN_F10R2_FB29_Pos (29U)
5277 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5278 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5279 #define CAN_F10R2_FB30_Pos (30U)
5280 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5281 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5282 #define CAN_F10R2_FB31_Pos (31U)
5283 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5284 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5285
5286 /******************* Bit definition for CAN_F11R2 register ******************/
5287 #define CAN_F11R2_FB0_Pos (0U)
5288 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5289 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5290 #define CAN_F11R2_FB1_Pos (1U)
5291 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5292 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5293 #define CAN_F11R2_FB2_Pos (2U)
5294 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5295 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5296 #define CAN_F11R2_FB3_Pos (3U)
5297 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5298 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5299 #define CAN_F11R2_FB4_Pos (4U)
5300 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5301 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5302 #define CAN_F11R2_FB5_Pos (5U)
5303 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5304 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5305 #define CAN_F11R2_FB6_Pos (6U)
5306 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5307 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5308 #define CAN_F11R2_FB7_Pos (7U)
5309 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5310 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5311 #define CAN_F11R2_FB8_Pos (8U)
5312 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5313 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5314 #define CAN_F11R2_FB9_Pos (9U)
5315 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5316 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5317 #define CAN_F11R2_FB10_Pos (10U)
5318 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5319 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5320 #define CAN_F11R2_FB11_Pos (11U)
5321 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5322 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5323 #define CAN_F11R2_FB12_Pos (12U)
5324 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5325 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5326 #define CAN_F11R2_FB13_Pos (13U)
5327 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5328 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5329 #define CAN_F11R2_FB14_Pos (14U)
5330 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5331 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5332 #define CAN_F11R2_FB15_Pos (15U)
5333 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5334 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5335 #define CAN_F11R2_FB16_Pos (16U)
5336 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5337 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5338 #define CAN_F11R2_FB17_Pos (17U)
5339 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5340 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5341 #define CAN_F11R2_FB18_Pos (18U)
5342 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5343 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5344 #define CAN_F11R2_FB19_Pos (19U)
5345 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5346 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5347 #define CAN_F11R2_FB20_Pos (20U)
5348 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5349 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5350 #define CAN_F11R2_FB21_Pos (21U)
5351 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5352 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5353 #define CAN_F11R2_FB22_Pos (22U)
5354 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5355 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5356 #define CAN_F11R2_FB23_Pos (23U)
5357 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5358 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5359 #define CAN_F11R2_FB24_Pos (24U)
5360 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5361 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5362 #define CAN_F11R2_FB25_Pos (25U)
5363 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5364 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5365 #define CAN_F11R2_FB26_Pos (26U)
5366 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5367 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5368 #define CAN_F11R2_FB27_Pos (27U)
5369 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5370 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5371 #define CAN_F11R2_FB28_Pos (28U)
5372 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5373 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5374 #define CAN_F11R2_FB29_Pos (29U)
5375 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5376 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5377 #define CAN_F11R2_FB30_Pos (30U)
5378 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5379 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5380 #define CAN_F11R2_FB31_Pos (31U)
5381 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5382 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5383
5384 /******************* Bit definition for CAN_F12R2 register ******************/
5385 #define CAN_F12R2_FB0_Pos (0U)
5386 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5387 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5388 #define CAN_F12R2_FB1_Pos (1U)
5389 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5390 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5391 #define CAN_F12R2_FB2_Pos (2U)
5392 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5393 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5394 #define CAN_F12R2_FB3_Pos (3U)
5395 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5396 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5397 #define CAN_F12R2_FB4_Pos (4U)
5398 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5399 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5400 #define CAN_F12R2_FB5_Pos (5U)
5401 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5402 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5403 #define CAN_F12R2_FB6_Pos (6U)
5404 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5405 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5406 #define CAN_F12R2_FB7_Pos (7U)
5407 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5408 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5409 #define CAN_F12R2_FB8_Pos (8U)
5410 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5411 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5412 #define CAN_F12R2_FB9_Pos (9U)
5413 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5414 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5415 #define CAN_F12R2_FB10_Pos (10U)
5416 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5417 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5418 #define CAN_F12R2_FB11_Pos (11U)
5419 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5420 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5421 #define CAN_F12R2_FB12_Pos (12U)
5422 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5423 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5424 #define CAN_F12R2_FB13_Pos (13U)
5425 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5426 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5427 #define CAN_F12R2_FB14_Pos (14U)
5428 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5429 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5430 #define CAN_F12R2_FB15_Pos (15U)
5431 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5432 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5433 #define CAN_F12R2_FB16_Pos (16U)
5434 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5435 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5436 #define CAN_F12R2_FB17_Pos (17U)
5437 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5438 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5439 #define CAN_F12R2_FB18_Pos (18U)
5440 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5441 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5442 #define CAN_F12R2_FB19_Pos (19U)
5443 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5444 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5445 #define CAN_F12R2_FB20_Pos (20U)
5446 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5447 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5448 #define CAN_F12R2_FB21_Pos (21U)
5449 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5450 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5451 #define CAN_F12R2_FB22_Pos (22U)
5452 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5453 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5454 #define CAN_F12R2_FB23_Pos (23U)
5455 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5456 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5457 #define CAN_F12R2_FB24_Pos (24U)
5458 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5459 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5460 #define CAN_F12R2_FB25_Pos (25U)
5461 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5462 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5463 #define CAN_F12R2_FB26_Pos (26U)
5464 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5465 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5466 #define CAN_F12R2_FB27_Pos (27U)
5467 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5468 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5469 #define CAN_F12R2_FB28_Pos (28U)
5470 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5471 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5472 #define CAN_F12R2_FB29_Pos (29U)
5473 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5474 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5475 #define CAN_F12R2_FB30_Pos (30U)
5476 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5477 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5478 #define CAN_F12R2_FB31_Pos (31U)
5479 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5480 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5481
5482 /******************* Bit definition for CAN_F13R2 register ******************/
5483 #define CAN_F13R2_FB0_Pos (0U)
5484 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5485 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5486 #define CAN_F13R2_FB1_Pos (1U)
5487 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5488 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5489 #define CAN_F13R2_FB2_Pos (2U)
5490 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5491 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5492 #define CAN_F13R2_FB3_Pos (3U)
5493 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5494 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5495 #define CAN_F13R2_FB4_Pos (4U)
5496 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5497 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5498 #define CAN_F13R2_FB5_Pos (5U)
5499 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5500 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5501 #define CAN_F13R2_FB6_Pos (6U)
5502 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5503 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5504 #define CAN_F13R2_FB7_Pos (7U)
5505 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5506 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5507 #define CAN_F13R2_FB8_Pos (8U)
5508 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5509 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5510 #define CAN_F13R2_FB9_Pos (9U)
5511 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5512 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5513 #define CAN_F13R2_FB10_Pos (10U)
5514 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5515 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5516 #define CAN_F13R2_FB11_Pos (11U)
5517 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5518 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5519 #define CAN_F13R2_FB12_Pos (12U)
5520 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5521 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5522 #define CAN_F13R2_FB13_Pos (13U)
5523 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5524 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5525 #define CAN_F13R2_FB14_Pos (14U)
5526 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5527 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5528 #define CAN_F13R2_FB15_Pos (15U)
5529 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5530 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5531 #define CAN_F13R2_FB16_Pos (16U)
5532 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5533 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5534 #define CAN_F13R2_FB17_Pos (17U)
5535 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5536 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5537 #define CAN_F13R2_FB18_Pos (18U)
5538 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5539 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5540 #define CAN_F13R2_FB19_Pos (19U)
5541 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5542 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5543 #define CAN_F13R2_FB20_Pos (20U)
5544 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5545 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5546 #define CAN_F13R2_FB21_Pos (21U)
5547 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5548 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5549 #define CAN_F13R2_FB22_Pos (22U)
5550 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5551 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5552 #define CAN_F13R2_FB23_Pos (23U)
5553 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5554 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5555 #define CAN_F13R2_FB24_Pos (24U)
5556 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5557 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5558 #define CAN_F13R2_FB25_Pos (25U)
5559 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5560 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5561 #define CAN_F13R2_FB26_Pos (26U)
5562 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5563 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5564 #define CAN_F13R2_FB27_Pos (27U)
5565 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5566 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5567 #define CAN_F13R2_FB28_Pos (28U)
5568 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5569 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5570 #define CAN_F13R2_FB29_Pos (29U)
5571 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5572 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5573 #define CAN_F13R2_FB30_Pos (30U)
5574 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5575 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5576 #define CAN_F13R2_FB31_Pos (31U)
5577 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5578 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5579
5580 /******************************************************************************/
5581 /* */
5582 /* CRC calculation unit */
5583 /* */
5584 /******************************************************************************/
5585 /******************* Bit definition for CRC_DR register *********************/
5586 #define CRC_DR_DR_Pos (0U)
5587 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5588 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5589
5590
5591 /******************* Bit definition for CRC_IDR register ********************/
5592 #define CRC_IDR_IDR_Pos (0U)
5593 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5594 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5595
5596
5597 /******************** Bit definition for CRC_CR register ********************/
5598 #define CRC_CR_RESET_Pos (0U)
5599 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5600 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5601
5602 /******************************************************************************/
5603 /* */
5604 /* Digital to Analog Converter */
5605 /* */
5606 /******************************************************************************/
5607 /*
5608 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5609 */
5610 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5611 /******************** Bit definition for DAC_CR register ********************/
5612 #define DAC_CR_EN1_Pos (0U)
5613 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5614 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5615 #define DAC_CR_BOFF1_Pos (1U)
5616 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5617 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5618 #define DAC_CR_TEN1_Pos (2U)
5619 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5620 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5621
5622 #define DAC_CR_TSEL1_Pos (3U)
5623 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5624 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5625 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5626 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5627 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5628
5629 #define DAC_CR_WAVE1_Pos (6U)
5630 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5631 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5632 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5633 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5634
5635 #define DAC_CR_MAMP1_Pos (8U)
5636 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5637 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5638 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5639 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5640 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5641 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5642
5643 #define DAC_CR_DMAEN1_Pos (12U)
5644 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5645 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5646 #define DAC_CR_DMAUDRIE1_Pos (13U)
5647 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5648 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5649 #define DAC_CR_EN2_Pos (16U)
5650 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5651 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5652 #define DAC_CR_BOFF2_Pos (17U)
5653 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5654 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5655 #define DAC_CR_TEN2_Pos (18U)
5656 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5657 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5658
5659 #define DAC_CR_TSEL2_Pos (19U)
5660 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5661 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5662 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5663 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5664 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5665
5666 #define DAC_CR_WAVE2_Pos (22U)
5667 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5668 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5669 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5670 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5671
5672 #define DAC_CR_MAMP2_Pos (24U)
5673 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5674 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5675 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5676 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5677 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5678 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5679
5680 #define DAC_CR_DMAEN2_Pos (28U)
5681 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5682 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5683 #define DAC_CR_DMAUDRIE2_Pos (29U)
5684 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5685 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5686
5687 /***************** Bit definition for DAC_SWTRIGR register ******************/
5688 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5689 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5690 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5691 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5692 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5693 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5694
5695 /***************** Bit definition for DAC_DHR12R1 register ******************/
5696 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5697 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5698 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5699
5700 /***************** Bit definition for DAC_DHR12L1 register ******************/
5701 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5702 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5703 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5704
5705 /****************** Bit definition for DAC_DHR8R1 register ******************/
5706 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5707 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5708 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5709
5710 /***************** Bit definition for DAC_DHR12R2 register ******************/
5711 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5712 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5713 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5714
5715 /***************** Bit definition for DAC_DHR12L2 register ******************/
5716 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5717 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5718 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5719
5720 /****************** Bit definition for DAC_DHR8R2 register ******************/
5721 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5722 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5723 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5724
5725 /***************** Bit definition for DAC_DHR12RD register ******************/
5726 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5727 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5728 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5729 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5730 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5731 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5732
5733 /***************** Bit definition for DAC_DHR12LD register ******************/
5734 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5735 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5736 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5737 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5738 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5739 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5740
5741 /****************** Bit definition for DAC_DHR8RD register ******************/
5742 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5743 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5744 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5745 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5746 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5747 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5748
5749 /******************* Bit definition for DAC_DOR1 register *******************/
5750 #define DAC_DOR1_DACC1DOR_Pos (0U)
5751 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5752 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5753
5754 /******************* Bit definition for DAC_DOR2 register *******************/
5755 #define DAC_DOR2_DACC2DOR_Pos (0U)
5756 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5757 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5758
5759 /******************** Bit definition for DAC_SR register ********************/
5760 #define DAC_SR_DMAUDR1_Pos (13U)
5761 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5762 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5763 #define DAC_SR_DMAUDR2_Pos (29U)
5764 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5765 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5766
5767 /******************************************************************************/
5768 /* */
5769 /* DCMI */
5770 /* */
5771 /******************************************************************************/
5772 /******************** Bits definition for DCMI_CR register ******************/
5773 #define DCMI_CR_CAPTURE_Pos (0U)
5774 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5775 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5776 #define DCMI_CR_CM_Pos (1U)
5777 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5778 #define DCMI_CR_CM DCMI_CR_CM_Msk
5779 #define DCMI_CR_CROP_Pos (2U)
5780 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5781 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
5782 #define DCMI_CR_JPEG_Pos (3U)
5783 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5784 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5785 #define DCMI_CR_ESS_Pos (4U)
5786 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5787 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
5788 #define DCMI_CR_PCKPOL_Pos (5U)
5789 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5790 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5791 #define DCMI_CR_HSPOL_Pos (6U)
5792 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5793 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5794 #define DCMI_CR_VSPOL_Pos (7U)
5795 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5796 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5797 #define DCMI_CR_FCRC_0 0x00000100U
5798 #define DCMI_CR_FCRC_1 0x00000200U
5799 #define DCMI_CR_EDM_0 0x00000400U
5800 #define DCMI_CR_EDM_1 0x00000800U
5801 #define DCMI_CR_CRE_Pos (12U)
5802 #define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
5803 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
5804 #define DCMI_CR_ENABLE_Pos (14U)
5805 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5806 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5807
5808 /******************** Bits definition for DCMI_SR register ******************/
5809 #define DCMI_SR_HSYNC_Pos (0U)
5810 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
5811 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5812 #define DCMI_SR_VSYNC_Pos (1U)
5813 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
5814 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5815 #define DCMI_SR_FNE_Pos (2U)
5816 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
5817 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
5818
5819 /******************** Bits definition for DCMI_RIS register *****************/
5820 #define DCMI_RIS_FRAME_RIS_Pos (0U)
5821 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
5822 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5823 #define DCMI_RIS_OVR_RIS_Pos (1U)
5824 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
5825 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5826 #define DCMI_RIS_ERR_RIS_Pos (2U)
5827 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
5828 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5829 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
5830 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
5831 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5832 #define DCMI_RIS_LINE_RIS_Pos (4U)
5833 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
5834 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5835 /* Legacy defines */
5836 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5837 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5838 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5839 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5840 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5841 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5842
5843 /******************** Bits definition for DCMI_IER register *****************/
5844 #define DCMI_IER_FRAME_IE_Pos (0U)
5845 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
5846 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5847 #define DCMI_IER_OVR_IE_Pos (1U)
5848 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
5849 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5850 #define DCMI_IER_ERR_IE_Pos (2U)
5851 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
5852 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5853 #define DCMI_IER_VSYNC_IE_Pos (3U)
5854 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
5855 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5856 #define DCMI_IER_LINE_IE_Pos (4U)
5857 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
5858 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5859 /* Legacy defines */
5860 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5861
5862 /******************** Bits definition for DCMI_MIS register *****************/
5863 #define DCMI_MIS_FRAME_MIS_Pos (0U)
5864 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
5865 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5866 #define DCMI_MIS_OVR_MIS_Pos (1U)
5867 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
5868 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5869 #define DCMI_MIS_ERR_MIS_Pos (2U)
5870 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
5871 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5872 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
5873 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
5874 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5875 #define DCMI_MIS_LINE_MIS_Pos (4U)
5876 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
5877 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5878
5879 /* Legacy defines */
5880 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5881 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5882 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5883 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5884 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5885
5886 /******************** Bits definition for DCMI_ICR register *****************/
5887 #define DCMI_ICR_FRAME_ISC_Pos (0U)
5888 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
5889 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5890 #define DCMI_ICR_OVR_ISC_Pos (1U)
5891 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
5892 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5893 #define DCMI_ICR_ERR_ISC_Pos (2U)
5894 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
5895 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5896 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
5897 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
5898 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5899 #define DCMI_ICR_LINE_ISC_Pos (4U)
5900 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
5901 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5902
5903 /* Legacy defines */
5904 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5905
5906 /******************** Bits definition for DCMI_ESCR register ******************/
5907 #define DCMI_ESCR_FSC_Pos (0U)
5908 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
5909 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5910 #define DCMI_ESCR_LSC_Pos (8U)
5911 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
5912 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5913 #define DCMI_ESCR_LEC_Pos (16U)
5914 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
5915 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5916 #define DCMI_ESCR_FEC_Pos (24U)
5917 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
5918 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5919
5920 /******************** Bits definition for DCMI_ESUR register ******************/
5921 #define DCMI_ESUR_FSU_Pos (0U)
5922 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
5923 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5924 #define DCMI_ESUR_LSU_Pos (8U)
5925 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
5926 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5927 #define DCMI_ESUR_LEU_Pos (16U)
5928 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
5929 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5930 #define DCMI_ESUR_FEU_Pos (24U)
5931 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
5932 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5933
5934 /******************** Bits definition for DCMI_CWSTRT register ******************/
5935 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5936 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
5937 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5938 #define DCMI_CWSTRT_VST_Pos (16U)
5939 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
5940 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5941
5942 /******************** Bits definition for DCMI_CWSIZE register ******************/
5943 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
5944 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
5945 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5946 #define DCMI_CWSIZE_VLINE_Pos (16U)
5947 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
5948 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5949
5950 /******************** Bits definition for DCMI_DR register *********************/
5951 #define DCMI_DR_BYTE0_Pos (0U)
5952 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
5953 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5954 #define DCMI_DR_BYTE1_Pos (8U)
5955 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
5956 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5957 #define DCMI_DR_BYTE2_Pos (16U)
5958 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
5959 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5960 #define DCMI_DR_BYTE3_Pos (24U)
5961 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
5962 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5963
5964 /******************************************************************************/
5965 /* */
5966 /* DMA Controller */
5967 /* */
5968 /******************************************************************************/
5969 /******************** Bits definition for DMA_SxCR register *****************/
5970 #define DMA_SxCR_CHSEL_Pos (25U)
5971 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
5972 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5973 #define DMA_SxCR_CHSEL_0 0x02000000U
5974 #define DMA_SxCR_CHSEL_1 0x04000000U
5975 #define DMA_SxCR_CHSEL_2 0x08000000U
5976 #define DMA_SxCR_MBURST_Pos (23U)
5977 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
5978 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5979 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
5980 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
5981 #define DMA_SxCR_PBURST_Pos (21U)
5982 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
5983 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5984 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
5985 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
5986 #define DMA_SxCR_CT_Pos (19U)
5987 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
5988 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
5989 #define DMA_SxCR_DBM_Pos (18U)
5990 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
5991 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5992 #define DMA_SxCR_PL_Pos (16U)
5993 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
5994 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
5995 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
5996 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
5997 #define DMA_SxCR_PINCOS_Pos (15U)
5998 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
5999 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6000 #define DMA_SxCR_MSIZE_Pos (13U)
6001 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6002 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6003 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6004 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6005 #define DMA_SxCR_PSIZE_Pos (11U)
6006 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6007 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6008 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6009 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6010 #define DMA_SxCR_MINC_Pos (10U)
6011 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6012 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6013 #define DMA_SxCR_PINC_Pos (9U)
6014 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6015 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6016 #define DMA_SxCR_CIRC_Pos (8U)
6017 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6018 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6019 #define DMA_SxCR_DIR_Pos (6U)
6020 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6021 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6022 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6023 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6024 #define DMA_SxCR_PFCTRL_Pos (5U)
6025 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6026 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6027 #define DMA_SxCR_TCIE_Pos (4U)
6028 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6029 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6030 #define DMA_SxCR_HTIE_Pos (3U)
6031 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6032 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6033 #define DMA_SxCR_TEIE_Pos (2U)
6034 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6035 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6036 #define DMA_SxCR_DMEIE_Pos (1U)
6037 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6038 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6039 #define DMA_SxCR_EN_Pos (0U)
6040 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6041 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
6042
6043 /* Legacy defines */
6044 #define DMA_SxCR_ACK_Pos (20U)
6045 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
6046 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6047
6048 /******************** Bits definition for DMA_SxCNDTR register **************/
6049 #define DMA_SxNDT_Pos (0U)
6050 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6051 #define DMA_SxNDT DMA_SxNDT_Msk
6052 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
6053 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
6054 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
6055 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
6056 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
6057 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
6058 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
6059 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
6060 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
6061 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
6062 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
6063 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
6064 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
6065 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
6066 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
6067 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
6068
6069 /******************** Bits definition for DMA_SxFCR register ****************/
6070 #define DMA_SxFCR_FEIE_Pos (7U)
6071 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6072 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6073 #define DMA_SxFCR_FS_Pos (3U)
6074 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6075 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6076 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6077 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6078 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6079 #define DMA_SxFCR_DMDIS_Pos (2U)
6080 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6081 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6082 #define DMA_SxFCR_FTH_Pos (0U)
6083 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6084 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6085 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6086 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6087
6088 /******************** Bits definition for DMA_LISR register *****************/
6089 #define DMA_LISR_TCIF3_Pos (27U)
6090 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6091 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6092 #define DMA_LISR_HTIF3_Pos (26U)
6093 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6094 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6095 #define DMA_LISR_TEIF3_Pos (25U)
6096 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6097 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6098 #define DMA_LISR_DMEIF3_Pos (24U)
6099 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6100 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6101 #define DMA_LISR_FEIF3_Pos (22U)
6102 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6103 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6104 #define DMA_LISR_TCIF2_Pos (21U)
6105 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6106 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6107 #define DMA_LISR_HTIF2_Pos (20U)
6108 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6109 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6110 #define DMA_LISR_TEIF2_Pos (19U)
6111 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6112 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6113 #define DMA_LISR_DMEIF2_Pos (18U)
6114 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6115 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6116 #define DMA_LISR_FEIF2_Pos (16U)
6117 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6118 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6119 #define DMA_LISR_TCIF1_Pos (11U)
6120 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6121 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6122 #define DMA_LISR_HTIF1_Pos (10U)
6123 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6124 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6125 #define DMA_LISR_TEIF1_Pos (9U)
6126 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6127 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6128 #define DMA_LISR_DMEIF1_Pos (8U)
6129 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6130 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6131 #define DMA_LISR_FEIF1_Pos (6U)
6132 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6133 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6134 #define DMA_LISR_TCIF0_Pos (5U)
6135 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6136 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6137 #define DMA_LISR_HTIF0_Pos (4U)
6138 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6139 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6140 #define DMA_LISR_TEIF0_Pos (3U)
6141 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6142 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6143 #define DMA_LISR_DMEIF0_Pos (2U)
6144 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6145 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6146 #define DMA_LISR_FEIF0_Pos (0U)
6147 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6148 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6149
6150 /******************** Bits definition for DMA_HISR register *****************/
6151 #define DMA_HISR_TCIF7_Pos (27U)
6152 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6153 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6154 #define DMA_HISR_HTIF7_Pos (26U)
6155 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6156 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6157 #define DMA_HISR_TEIF7_Pos (25U)
6158 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6159 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6160 #define DMA_HISR_DMEIF7_Pos (24U)
6161 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6162 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6163 #define DMA_HISR_FEIF7_Pos (22U)
6164 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6165 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6166 #define DMA_HISR_TCIF6_Pos (21U)
6167 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6168 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6169 #define DMA_HISR_HTIF6_Pos (20U)
6170 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6171 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6172 #define DMA_HISR_TEIF6_Pos (19U)
6173 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6174 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6175 #define DMA_HISR_DMEIF6_Pos (18U)
6176 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6177 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6178 #define DMA_HISR_FEIF6_Pos (16U)
6179 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6180 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6181 #define DMA_HISR_TCIF5_Pos (11U)
6182 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6183 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6184 #define DMA_HISR_HTIF5_Pos (10U)
6185 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6186 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6187 #define DMA_HISR_TEIF5_Pos (9U)
6188 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6189 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6190 #define DMA_HISR_DMEIF5_Pos (8U)
6191 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6192 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6193 #define DMA_HISR_FEIF5_Pos (6U)
6194 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6195 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6196 #define DMA_HISR_TCIF4_Pos (5U)
6197 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6198 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6199 #define DMA_HISR_HTIF4_Pos (4U)
6200 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6201 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6202 #define DMA_HISR_TEIF4_Pos (3U)
6203 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6204 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6205 #define DMA_HISR_DMEIF4_Pos (2U)
6206 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6207 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6208 #define DMA_HISR_FEIF4_Pos (0U)
6209 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6210 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6211
6212 /******************** Bits definition for DMA_LIFCR register ****************/
6213 #define DMA_LIFCR_CTCIF3_Pos (27U)
6214 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6215 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6216 #define DMA_LIFCR_CHTIF3_Pos (26U)
6217 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6218 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6219 #define DMA_LIFCR_CTEIF3_Pos (25U)
6220 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6221 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6222 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6223 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6224 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6225 #define DMA_LIFCR_CFEIF3_Pos (22U)
6226 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6227 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6228 #define DMA_LIFCR_CTCIF2_Pos (21U)
6229 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6230 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6231 #define DMA_LIFCR_CHTIF2_Pos (20U)
6232 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6233 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6234 #define DMA_LIFCR_CTEIF2_Pos (19U)
6235 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6236 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6237 #define DMA_LIFCR_CDMEIF2_Pos (18U)
6238 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6239 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6240 #define DMA_LIFCR_CFEIF2_Pos (16U)
6241 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6242 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6243 #define DMA_LIFCR_CTCIF1_Pos (11U)
6244 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6245 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6246 #define DMA_LIFCR_CHTIF1_Pos (10U)
6247 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6248 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6249 #define DMA_LIFCR_CTEIF1_Pos (9U)
6250 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6251 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6252 #define DMA_LIFCR_CDMEIF1_Pos (8U)
6253 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6254 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6255 #define DMA_LIFCR_CFEIF1_Pos (6U)
6256 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6257 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6258 #define DMA_LIFCR_CTCIF0_Pos (5U)
6259 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6260 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6261 #define DMA_LIFCR_CHTIF0_Pos (4U)
6262 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6263 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6264 #define DMA_LIFCR_CTEIF0_Pos (3U)
6265 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6266 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6267 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6268 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6269 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6270 #define DMA_LIFCR_CFEIF0_Pos (0U)
6271 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6272 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6273
6274 /******************** Bits definition for DMA_HIFCR register ****************/
6275 #define DMA_HIFCR_CTCIF7_Pos (27U)
6276 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6277 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6278 #define DMA_HIFCR_CHTIF7_Pos (26U)
6279 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6280 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6281 #define DMA_HIFCR_CTEIF7_Pos (25U)
6282 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6283 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6284 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6285 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6286 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6287 #define DMA_HIFCR_CFEIF7_Pos (22U)
6288 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6289 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6290 #define DMA_HIFCR_CTCIF6_Pos (21U)
6291 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6292 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6293 #define DMA_HIFCR_CHTIF6_Pos (20U)
6294 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6295 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6296 #define DMA_HIFCR_CTEIF6_Pos (19U)
6297 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6298 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6299 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6300 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6301 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6302 #define DMA_HIFCR_CFEIF6_Pos (16U)
6303 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6304 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6305 #define DMA_HIFCR_CTCIF5_Pos (11U)
6306 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6307 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6308 #define DMA_HIFCR_CHTIF5_Pos (10U)
6309 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6310 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6311 #define DMA_HIFCR_CTEIF5_Pos (9U)
6312 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6313 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6314 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6315 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6316 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6317 #define DMA_HIFCR_CFEIF5_Pos (6U)
6318 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6319 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6320 #define DMA_HIFCR_CTCIF4_Pos (5U)
6321 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6322 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6323 #define DMA_HIFCR_CHTIF4_Pos (4U)
6324 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6325 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6326 #define DMA_HIFCR_CTEIF4_Pos (3U)
6327 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6328 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6329 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6330 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6331 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6332 #define DMA_HIFCR_CFEIF4_Pos (0U)
6333 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6334 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6335
6336 /****************** Bit definition for DMA_SxPAR register ********************/
6337 #define DMA_SxPAR_PA_Pos (0U)
6338 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6339 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6340
6341 /****************** Bit definition for DMA_SxM0AR register ********************/
6342 #define DMA_SxM0AR_M0A_Pos (0U)
6343 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6344 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6345
6346 /****************** Bit definition for DMA_SxM1AR register ********************/
6347 #define DMA_SxM1AR_M1A_Pos (0U)
6348 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6349 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6350
6351
6352 /******************************************************************************/
6353 /* */
6354 /* AHB Master DMA2D Controller (DMA2D) */
6355 /* */
6356 /******************************************************************************/
6357
6358 /******************** Bit definition for DMA2D_CR register ******************/
6359
6360 #define DMA2D_CR_START_Pos (0U)
6361 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
6362 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
6363 #define DMA2D_CR_SUSP_Pos (1U)
6364 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
6365 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
6366 #define DMA2D_CR_ABORT_Pos (2U)
6367 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
6368 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
6369 #define DMA2D_CR_TEIE_Pos (8U)
6370 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
6371 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
6372 #define DMA2D_CR_TCIE_Pos (9U)
6373 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
6374 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
6375 #define DMA2D_CR_TWIE_Pos (10U)
6376 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
6377 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
6378 #define DMA2D_CR_CAEIE_Pos (11U)
6379 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
6380 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
6381 #define DMA2D_CR_CTCIE_Pos (12U)
6382 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
6383 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
6384 #define DMA2D_CR_CEIE_Pos (13U)
6385 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
6386 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
6387 #define DMA2D_CR_MODE_Pos (16U)
6388 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
6389 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
6390 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
6391 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
6392
6393 /******************** Bit definition for DMA2D_ISR register *****************/
6394
6395 #define DMA2D_ISR_TEIF_Pos (0U)
6396 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
6397 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
6398 #define DMA2D_ISR_TCIF_Pos (1U)
6399 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
6400 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
6401 #define DMA2D_ISR_TWIF_Pos (2U)
6402 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
6403 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
6404 #define DMA2D_ISR_CAEIF_Pos (3U)
6405 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
6406 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
6407 #define DMA2D_ISR_CTCIF_Pos (4U)
6408 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
6409 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
6410 #define DMA2D_ISR_CEIF_Pos (5U)
6411 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
6412 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
6413
6414 /******************** Bit definition for DMA2D_IFCR register ****************/
6415
6416 #define DMA2D_IFCR_CTEIF_Pos (0U)
6417 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
6418 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
6419 #define DMA2D_IFCR_CTCIF_Pos (1U)
6420 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
6421 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
6422 #define DMA2D_IFCR_CTWIF_Pos (2U)
6423 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
6424 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
6425 #define DMA2D_IFCR_CAECIF_Pos (3U)
6426 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
6427 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
6428 #define DMA2D_IFCR_CCTCIF_Pos (4U)
6429 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
6430 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
6431 #define DMA2D_IFCR_CCEIF_Pos (5U)
6432 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
6433 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
6434
6435 /* Legacy defines */
6436 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
6437 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
6438 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
6439 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
6440 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
6441 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
6442
6443 /******************** Bit definition for DMA2D_FGMAR register ***************/
6444
6445 #define DMA2D_FGMAR_MA_Pos (0U)
6446 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6447 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
6448
6449 /******************** Bit definition for DMA2D_FGOR register ****************/
6450
6451 #define DMA2D_FGOR_LO_Pos (0U)
6452 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
6453 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
6454
6455 /******************** Bit definition for DMA2D_BGMAR register ***************/
6456
6457 #define DMA2D_BGMAR_MA_Pos (0U)
6458 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6459 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
6460
6461 /******************** Bit definition for DMA2D_BGOR register ****************/
6462
6463 #define DMA2D_BGOR_LO_Pos (0U)
6464 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
6465 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
6466
6467 /******************** Bit definition for DMA2D_FGPFCCR register *************/
6468
6469 #define DMA2D_FGPFCCR_CM_Pos (0U)
6470 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
6471 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6472 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
6473 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
6474 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
6475 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
6476 #define DMA2D_FGPFCCR_CCM_Pos (4U)
6477 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
6478 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
6479 #define DMA2D_FGPFCCR_START_Pos (5U)
6480 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
6481 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
6482 #define DMA2D_FGPFCCR_CS_Pos (8U)
6483 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6484 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
6485 #define DMA2D_FGPFCCR_AM_Pos (16U)
6486 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
6487 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6488 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
6489 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
6490 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6491 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6492 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
6493
6494 /******************** Bit definition for DMA2D_FGCOLR register **************/
6495
6496 #define DMA2D_FGCOLR_BLUE_Pos (0U)
6497 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
6498 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
6499 #define DMA2D_FGCOLR_GREEN_Pos (8U)
6500 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6501 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
6502 #define DMA2D_FGCOLR_RED_Pos (16U)
6503 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
6504 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
6505
6506 /******************** Bit definition for DMA2D_BGPFCCR register *************/
6507
6508 #define DMA2D_BGPFCCR_CM_Pos (0U)
6509 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
6510 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6511 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
6512 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
6513 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
6514 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
6515 #define DMA2D_BGPFCCR_CCM_Pos (4U)
6516 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
6517 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
6518 #define DMA2D_BGPFCCR_START_Pos (5U)
6519 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
6520 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
6521 #define DMA2D_BGPFCCR_CS_Pos (8U)
6522 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6523 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
6524 #define DMA2D_BGPFCCR_AM_Pos (16U)
6525 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
6526 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6527 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
6528 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
6529 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6530 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6531 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
6532
6533 /******************** Bit definition for DMA2D_BGCOLR register **************/
6534
6535 #define DMA2D_BGCOLR_BLUE_Pos (0U)
6536 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
6537 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
6538 #define DMA2D_BGCOLR_GREEN_Pos (8U)
6539 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6540 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
6541 #define DMA2D_BGCOLR_RED_Pos (16U)
6542 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
6543 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
6544
6545 /******************** Bit definition for DMA2D_FGCMAR register **************/
6546
6547 #define DMA2D_FGCMAR_MA_Pos (0U)
6548 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6549 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
6550
6551 /******************** Bit definition for DMA2D_BGCMAR register **************/
6552
6553 #define DMA2D_BGCMAR_MA_Pos (0U)
6554 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6555 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
6556
6557 /******************** Bit definition for DMA2D_OPFCCR register **************/
6558
6559 #define DMA2D_OPFCCR_CM_Pos (0U)
6560 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
6561 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
6562 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
6563 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
6564 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
6565
6566 /******************** Bit definition for DMA2D_OCOLR register ***************/
6567
6568 /*!<Mode_ARGB8888/RGB888 */
6569
6570 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
6571 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
6572 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
6573 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
6574
6575 /*!<Mode_RGB565 */
6576 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
6577 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
6578 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
6579
6580 /*!<Mode_ARGB1555 */
6581 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
6582 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
6583 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
6584 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
6585
6586 /*!<Mode_ARGB4444 */
6587 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
6588 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
6589 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
6590 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
6591
6592 /******************** Bit definition for DMA2D_OMAR register ****************/
6593
6594 #define DMA2D_OMAR_MA_Pos (0U)
6595 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
6596 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
6597
6598 /******************** Bit definition for DMA2D_OOR register *****************/
6599
6600 #define DMA2D_OOR_LO_Pos (0U)
6601 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
6602 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
6603
6604 /******************** Bit definition for DMA2D_NLR register *****************/
6605
6606 #define DMA2D_NLR_NL_Pos (0U)
6607 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
6608 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
6609 #define DMA2D_NLR_PL_Pos (16U)
6610 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
6611 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
6612
6613 /******************** Bit definition for DMA2D_LWR register *****************/
6614
6615 #define DMA2D_LWR_LW_Pos (0U)
6616 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
6617 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
6618
6619 /******************** Bit definition for DMA2D_AMTCR register ***************/
6620
6621 #define DMA2D_AMTCR_EN_Pos (0U)
6622 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
6623 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
6624 #define DMA2D_AMTCR_DT_Pos (8U)
6625 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
6626 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
6627
6628 /******************** Bit definition for DMA2D_FGCLUT register **************/
6629
6630 /******************** Bit definition for DMA2D_BGCLUT register **************/
6631
6632
6633 /******************************************************************************/
6634 /* */
6635 /* External Interrupt/Event Controller */
6636 /* */
6637 /******************************************************************************/
6638 /******************* Bit definition for EXTI_IMR register *******************/
6639 #define EXTI_IMR_MR0_Pos (0U)
6640 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
6641 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
6642 #define EXTI_IMR_MR1_Pos (1U)
6643 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
6644 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
6645 #define EXTI_IMR_MR2_Pos (2U)
6646 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
6647 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
6648 #define EXTI_IMR_MR3_Pos (3U)
6649 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
6650 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
6651 #define EXTI_IMR_MR4_Pos (4U)
6652 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
6653 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
6654 #define EXTI_IMR_MR5_Pos (5U)
6655 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
6656 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
6657 #define EXTI_IMR_MR6_Pos (6U)
6658 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
6659 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
6660 #define EXTI_IMR_MR7_Pos (7U)
6661 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
6662 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
6663 #define EXTI_IMR_MR8_Pos (8U)
6664 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
6665 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
6666 #define EXTI_IMR_MR9_Pos (9U)
6667 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
6668 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
6669 #define EXTI_IMR_MR10_Pos (10U)
6670 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
6671 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
6672 #define EXTI_IMR_MR11_Pos (11U)
6673 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
6674 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
6675 #define EXTI_IMR_MR12_Pos (12U)
6676 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
6677 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
6678 #define EXTI_IMR_MR13_Pos (13U)
6679 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
6680 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
6681 #define EXTI_IMR_MR14_Pos (14U)
6682 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
6683 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
6684 #define EXTI_IMR_MR15_Pos (15U)
6685 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
6686 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
6687 #define EXTI_IMR_MR16_Pos (16U)
6688 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
6689 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
6690 #define EXTI_IMR_MR17_Pos (17U)
6691 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
6692 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
6693 #define EXTI_IMR_MR18_Pos (18U)
6694 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
6695 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
6696 #define EXTI_IMR_MR19_Pos (19U)
6697 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
6698 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
6699 #define EXTI_IMR_MR20_Pos (20U)
6700 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
6701 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
6702 #define EXTI_IMR_MR21_Pos (21U)
6703 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
6704 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
6705 #define EXTI_IMR_MR22_Pos (22U)
6706 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
6707 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
6708
6709 /* Reference Defines */
6710 #define EXTI_IMR_IM0 EXTI_IMR_MR0
6711 #define EXTI_IMR_IM1 EXTI_IMR_MR1
6712 #define EXTI_IMR_IM2 EXTI_IMR_MR2
6713 #define EXTI_IMR_IM3 EXTI_IMR_MR3
6714 #define EXTI_IMR_IM4 EXTI_IMR_MR4
6715 #define EXTI_IMR_IM5 EXTI_IMR_MR5
6716 #define EXTI_IMR_IM6 EXTI_IMR_MR6
6717 #define EXTI_IMR_IM7 EXTI_IMR_MR7
6718 #define EXTI_IMR_IM8 EXTI_IMR_MR8
6719 #define EXTI_IMR_IM9 EXTI_IMR_MR9
6720 #define EXTI_IMR_IM10 EXTI_IMR_MR10
6721 #define EXTI_IMR_IM11 EXTI_IMR_MR11
6722 #define EXTI_IMR_IM12 EXTI_IMR_MR12
6723 #define EXTI_IMR_IM13 EXTI_IMR_MR13
6724 #define EXTI_IMR_IM14 EXTI_IMR_MR14
6725 #define EXTI_IMR_IM15 EXTI_IMR_MR15
6726 #define EXTI_IMR_IM16 EXTI_IMR_MR16
6727 #define EXTI_IMR_IM17 EXTI_IMR_MR17
6728 #define EXTI_IMR_IM18 EXTI_IMR_MR18
6729 #define EXTI_IMR_IM19 EXTI_IMR_MR19
6730 #define EXTI_IMR_IM20 EXTI_IMR_MR20
6731 #define EXTI_IMR_IM21 EXTI_IMR_MR21
6732 #define EXTI_IMR_IM22 EXTI_IMR_MR22
6733 #define EXTI_IMR_IM_Pos (0U)
6734 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
6735 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
6736
6737 /******************* Bit definition for EXTI_EMR register *******************/
6738 #define EXTI_EMR_MR0_Pos (0U)
6739 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
6740 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
6741 #define EXTI_EMR_MR1_Pos (1U)
6742 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
6743 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
6744 #define EXTI_EMR_MR2_Pos (2U)
6745 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
6746 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
6747 #define EXTI_EMR_MR3_Pos (3U)
6748 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
6749 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
6750 #define EXTI_EMR_MR4_Pos (4U)
6751 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
6752 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
6753 #define EXTI_EMR_MR5_Pos (5U)
6754 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
6755 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
6756 #define EXTI_EMR_MR6_Pos (6U)
6757 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
6758 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
6759 #define EXTI_EMR_MR7_Pos (7U)
6760 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
6761 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
6762 #define EXTI_EMR_MR8_Pos (8U)
6763 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
6764 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
6765 #define EXTI_EMR_MR9_Pos (9U)
6766 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
6767 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
6768 #define EXTI_EMR_MR10_Pos (10U)
6769 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
6770 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
6771 #define EXTI_EMR_MR11_Pos (11U)
6772 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
6773 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
6774 #define EXTI_EMR_MR12_Pos (12U)
6775 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
6776 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
6777 #define EXTI_EMR_MR13_Pos (13U)
6778 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
6779 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
6780 #define EXTI_EMR_MR14_Pos (14U)
6781 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
6782 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
6783 #define EXTI_EMR_MR15_Pos (15U)
6784 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
6785 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
6786 #define EXTI_EMR_MR16_Pos (16U)
6787 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
6788 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
6789 #define EXTI_EMR_MR17_Pos (17U)
6790 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
6791 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
6792 #define EXTI_EMR_MR18_Pos (18U)
6793 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
6794 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
6795 #define EXTI_EMR_MR19_Pos (19U)
6796 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
6797 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
6798 #define EXTI_EMR_MR20_Pos (20U)
6799 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
6800 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
6801 #define EXTI_EMR_MR21_Pos (21U)
6802 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
6803 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
6804 #define EXTI_EMR_MR22_Pos (22U)
6805 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
6806 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
6807
6808 /* Reference Defines */
6809 #define EXTI_EMR_EM0 EXTI_EMR_MR0
6810 #define EXTI_EMR_EM1 EXTI_EMR_MR1
6811 #define EXTI_EMR_EM2 EXTI_EMR_MR2
6812 #define EXTI_EMR_EM3 EXTI_EMR_MR3
6813 #define EXTI_EMR_EM4 EXTI_EMR_MR4
6814 #define EXTI_EMR_EM5 EXTI_EMR_MR5
6815 #define EXTI_EMR_EM6 EXTI_EMR_MR6
6816 #define EXTI_EMR_EM7 EXTI_EMR_MR7
6817 #define EXTI_EMR_EM8 EXTI_EMR_MR8
6818 #define EXTI_EMR_EM9 EXTI_EMR_MR9
6819 #define EXTI_EMR_EM10 EXTI_EMR_MR10
6820 #define EXTI_EMR_EM11 EXTI_EMR_MR11
6821 #define EXTI_EMR_EM12 EXTI_EMR_MR12
6822 #define EXTI_EMR_EM13 EXTI_EMR_MR13
6823 #define EXTI_EMR_EM14 EXTI_EMR_MR14
6824 #define EXTI_EMR_EM15 EXTI_EMR_MR15
6825 #define EXTI_EMR_EM16 EXTI_EMR_MR16
6826 #define EXTI_EMR_EM17 EXTI_EMR_MR17
6827 #define EXTI_EMR_EM18 EXTI_EMR_MR18
6828 #define EXTI_EMR_EM19 EXTI_EMR_MR19
6829 #define EXTI_EMR_EM20 EXTI_EMR_MR20
6830 #define EXTI_EMR_EM21 EXTI_EMR_MR21
6831 #define EXTI_EMR_EM22 EXTI_EMR_MR22
6832
6833 /****************** Bit definition for EXTI_RTSR register *******************/
6834 #define EXTI_RTSR_TR0_Pos (0U)
6835 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
6836 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
6837 #define EXTI_RTSR_TR1_Pos (1U)
6838 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
6839 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
6840 #define EXTI_RTSR_TR2_Pos (2U)
6841 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
6842 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
6843 #define EXTI_RTSR_TR3_Pos (3U)
6844 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
6845 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
6846 #define EXTI_RTSR_TR4_Pos (4U)
6847 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
6848 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
6849 #define EXTI_RTSR_TR5_Pos (5U)
6850 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
6851 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
6852 #define EXTI_RTSR_TR6_Pos (6U)
6853 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
6854 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
6855 #define EXTI_RTSR_TR7_Pos (7U)
6856 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
6857 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
6858 #define EXTI_RTSR_TR8_Pos (8U)
6859 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
6860 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
6861 #define EXTI_RTSR_TR9_Pos (9U)
6862 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
6863 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
6864 #define EXTI_RTSR_TR10_Pos (10U)
6865 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
6866 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
6867 #define EXTI_RTSR_TR11_Pos (11U)
6868 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
6869 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
6870 #define EXTI_RTSR_TR12_Pos (12U)
6871 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
6872 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
6873 #define EXTI_RTSR_TR13_Pos (13U)
6874 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
6875 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
6876 #define EXTI_RTSR_TR14_Pos (14U)
6877 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
6878 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
6879 #define EXTI_RTSR_TR15_Pos (15U)
6880 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
6881 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
6882 #define EXTI_RTSR_TR16_Pos (16U)
6883 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
6884 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
6885 #define EXTI_RTSR_TR17_Pos (17U)
6886 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
6887 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
6888 #define EXTI_RTSR_TR18_Pos (18U)
6889 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
6890 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
6891 #define EXTI_RTSR_TR19_Pos (19U)
6892 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
6893 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
6894 #define EXTI_RTSR_TR20_Pos (20U)
6895 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
6896 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
6897 #define EXTI_RTSR_TR21_Pos (21U)
6898 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
6899 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
6900 #define EXTI_RTSR_TR22_Pos (22U)
6901 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
6902 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
6903
6904 /****************** Bit definition for EXTI_FTSR register *******************/
6905 #define EXTI_FTSR_TR0_Pos (0U)
6906 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
6907 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
6908 #define EXTI_FTSR_TR1_Pos (1U)
6909 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
6910 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
6911 #define EXTI_FTSR_TR2_Pos (2U)
6912 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
6913 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
6914 #define EXTI_FTSR_TR3_Pos (3U)
6915 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
6916 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
6917 #define EXTI_FTSR_TR4_Pos (4U)
6918 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
6919 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
6920 #define EXTI_FTSR_TR5_Pos (5U)
6921 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
6922 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
6923 #define EXTI_FTSR_TR6_Pos (6U)
6924 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
6925 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
6926 #define EXTI_FTSR_TR7_Pos (7U)
6927 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
6928 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
6929 #define EXTI_FTSR_TR8_Pos (8U)
6930 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
6931 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
6932 #define EXTI_FTSR_TR9_Pos (9U)
6933 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
6934 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
6935 #define EXTI_FTSR_TR10_Pos (10U)
6936 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
6937 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
6938 #define EXTI_FTSR_TR11_Pos (11U)
6939 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
6940 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
6941 #define EXTI_FTSR_TR12_Pos (12U)
6942 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
6943 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
6944 #define EXTI_FTSR_TR13_Pos (13U)
6945 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
6946 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
6947 #define EXTI_FTSR_TR14_Pos (14U)
6948 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
6949 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
6950 #define EXTI_FTSR_TR15_Pos (15U)
6951 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
6952 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
6953 #define EXTI_FTSR_TR16_Pos (16U)
6954 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
6955 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
6956 #define EXTI_FTSR_TR17_Pos (17U)
6957 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
6958 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
6959 #define EXTI_FTSR_TR18_Pos (18U)
6960 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
6961 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
6962 #define EXTI_FTSR_TR19_Pos (19U)
6963 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
6964 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
6965 #define EXTI_FTSR_TR20_Pos (20U)
6966 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
6967 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
6968 #define EXTI_FTSR_TR21_Pos (21U)
6969 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
6970 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
6971 #define EXTI_FTSR_TR22_Pos (22U)
6972 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
6973 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
6974
6975 /****************** Bit definition for EXTI_SWIER register ******************/
6976 #define EXTI_SWIER_SWIER0_Pos (0U)
6977 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
6978 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
6979 #define EXTI_SWIER_SWIER1_Pos (1U)
6980 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
6981 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
6982 #define EXTI_SWIER_SWIER2_Pos (2U)
6983 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
6984 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
6985 #define EXTI_SWIER_SWIER3_Pos (3U)
6986 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
6987 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
6988 #define EXTI_SWIER_SWIER4_Pos (4U)
6989 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
6990 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
6991 #define EXTI_SWIER_SWIER5_Pos (5U)
6992 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
6993 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
6994 #define EXTI_SWIER_SWIER6_Pos (6U)
6995 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
6996 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
6997 #define EXTI_SWIER_SWIER7_Pos (7U)
6998 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
6999 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
7000 #define EXTI_SWIER_SWIER8_Pos (8U)
7001 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
7002 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
7003 #define EXTI_SWIER_SWIER9_Pos (9U)
7004 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
7005 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
7006 #define EXTI_SWIER_SWIER10_Pos (10U)
7007 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
7008 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
7009 #define EXTI_SWIER_SWIER11_Pos (11U)
7010 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
7011 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
7012 #define EXTI_SWIER_SWIER12_Pos (12U)
7013 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
7014 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
7015 #define EXTI_SWIER_SWIER13_Pos (13U)
7016 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
7017 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
7018 #define EXTI_SWIER_SWIER14_Pos (14U)
7019 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
7020 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
7021 #define EXTI_SWIER_SWIER15_Pos (15U)
7022 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
7023 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
7024 #define EXTI_SWIER_SWIER16_Pos (16U)
7025 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
7026 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
7027 #define EXTI_SWIER_SWIER17_Pos (17U)
7028 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
7029 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
7030 #define EXTI_SWIER_SWIER18_Pos (18U)
7031 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
7032 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
7033 #define EXTI_SWIER_SWIER19_Pos (19U)
7034 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
7035 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
7036 #define EXTI_SWIER_SWIER20_Pos (20U)
7037 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
7038 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
7039 #define EXTI_SWIER_SWIER21_Pos (21U)
7040 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
7041 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
7042 #define EXTI_SWIER_SWIER22_Pos (22U)
7043 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
7044 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
7045
7046 /******************* Bit definition for EXTI_PR register ********************/
7047 #define EXTI_PR_PR0_Pos (0U)
7048 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
7049 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
7050 #define EXTI_PR_PR1_Pos (1U)
7051 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
7052 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
7053 #define EXTI_PR_PR2_Pos (2U)
7054 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
7055 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
7056 #define EXTI_PR_PR3_Pos (3U)
7057 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
7058 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
7059 #define EXTI_PR_PR4_Pos (4U)
7060 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
7061 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
7062 #define EXTI_PR_PR5_Pos (5U)
7063 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
7064 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
7065 #define EXTI_PR_PR6_Pos (6U)
7066 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
7067 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
7068 #define EXTI_PR_PR7_Pos (7U)
7069 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
7070 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
7071 #define EXTI_PR_PR8_Pos (8U)
7072 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
7073 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
7074 #define EXTI_PR_PR9_Pos (9U)
7075 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
7076 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
7077 #define EXTI_PR_PR10_Pos (10U)
7078 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
7079 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
7080 #define EXTI_PR_PR11_Pos (11U)
7081 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
7082 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
7083 #define EXTI_PR_PR12_Pos (12U)
7084 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
7085 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
7086 #define EXTI_PR_PR13_Pos (13U)
7087 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
7088 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
7089 #define EXTI_PR_PR14_Pos (14U)
7090 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
7091 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
7092 #define EXTI_PR_PR15_Pos (15U)
7093 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
7094 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
7095 #define EXTI_PR_PR16_Pos (16U)
7096 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
7097 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
7098 #define EXTI_PR_PR17_Pos (17U)
7099 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
7100 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
7101 #define EXTI_PR_PR18_Pos (18U)
7102 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
7103 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
7104 #define EXTI_PR_PR19_Pos (19U)
7105 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
7106 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
7107 #define EXTI_PR_PR20_Pos (20U)
7108 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
7109 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
7110 #define EXTI_PR_PR21_Pos (21U)
7111 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
7112 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
7113 #define EXTI_PR_PR22_Pos (22U)
7114 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
7115 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
7116
7117 /******************************************************************************/
7118 /* */
7119 /* FLASH */
7120 /* */
7121 /******************************************************************************/
7122 /******************* Bits definition for FLASH_ACR register *****************/
7123 #define FLASH_ACR_LATENCY_Pos (0U)
7124 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
7125 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7126 #define FLASH_ACR_LATENCY_0WS 0x00000000U
7127 #define FLASH_ACR_LATENCY_1WS 0x00000001U
7128 #define FLASH_ACR_LATENCY_2WS 0x00000002U
7129 #define FLASH_ACR_LATENCY_3WS 0x00000003U
7130 #define FLASH_ACR_LATENCY_4WS 0x00000004U
7131 #define FLASH_ACR_LATENCY_5WS 0x00000005U
7132 #define FLASH_ACR_LATENCY_6WS 0x00000006U
7133 #define FLASH_ACR_LATENCY_7WS 0x00000007U
7134
7135 #define FLASH_ACR_LATENCY_8WS 0x00000008U
7136 #define FLASH_ACR_LATENCY_9WS 0x00000009U
7137 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
7138 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
7139 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
7140 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
7141 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
7142 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
7143 #define FLASH_ACR_PRFTEN_Pos (8U)
7144 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
7145 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7146 #define FLASH_ACR_ICEN_Pos (9U)
7147 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
7148 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
7149 #define FLASH_ACR_DCEN_Pos (10U)
7150 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
7151 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
7152 #define FLASH_ACR_ICRST_Pos (11U)
7153 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
7154 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
7155 #define FLASH_ACR_DCRST_Pos (12U)
7156 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
7157 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
7158 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
7159 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
7160 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
7161 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
7162 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
7163 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
7164
7165 /******************* Bits definition for FLASH_SR register ******************/
7166 #define FLASH_SR_EOP_Pos (0U)
7167 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
7168 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
7169 #define FLASH_SR_SOP_Pos (1U)
7170 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
7171 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
7172 #define FLASH_SR_WRPERR_Pos (4U)
7173 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
7174 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7175 #define FLASH_SR_PGAERR_Pos (5U)
7176 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
7177 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7178 #define FLASH_SR_PGPERR_Pos (6U)
7179 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
7180 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
7181 #define FLASH_SR_PGSERR_Pos (7U)
7182 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
7183 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
7184 #define FLASH_SR_RDERR_Pos (8U)
7185 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
7186 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
7187 #define FLASH_SR_BSY_Pos (16U)
7188 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
7189 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
7190
7191 /******************* Bits definition for FLASH_CR register ******************/
7192 #define FLASH_CR_PG_Pos (0U)
7193 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
7194 #define FLASH_CR_PG FLASH_CR_PG_Msk
7195 #define FLASH_CR_SER_Pos (1U)
7196 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
7197 #define FLASH_CR_SER FLASH_CR_SER_Msk
7198 #define FLASH_CR_MER_Pos (2U)
7199 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
7200 #define FLASH_CR_MER FLASH_CR_MER_Msk
7201 #define FLASH_CR_MER1 FLASH_CR_MER
7202 #define FLASH_CR_SNB_Pos (3U)
7203 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
7204 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
7205 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
7206 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
7207 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
7208 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
7209 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
7210 #define FLASH_CR_PSIZE_Pos (8U)
7211 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
7212 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
7213 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
7214 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
7215 #define FLASH_CR_MER2_Pos (15U)
7216 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
7217 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
7218 #define FLASH_CR_STRT_Pos (16U)
7219 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
7220 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
7221 #define FLASH_CR_EOPIE_Pos (24U)
7222 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
7223 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7224 #define FLASH_CR_LOCK_Pos (31U)
7225 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
7226 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7227
7228 /******************* Bits definition for FLASH_OPTCR register ***************/
7229 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
7230 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
7231 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
7232 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
7233 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
7234 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
7235
7236 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
7237 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
7238 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
7239 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
7240 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
7241 #define FLASH_OPTCR_BFB2_Pos (4U)
7242 #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
7243 #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
7244 #define FLASH_OPTCR_WDG_SW_Pos (5U)
7245 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
7246 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
7247 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
7248 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
7249 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
7250 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
7251 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
7252 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
7253 #define FLASH_OPTCR_RDP_Pos (8U)
7254 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
7255 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
7256 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
7257 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
7258 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
7259 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
7260 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
7261 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
7262 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
7263 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
7264 #define FLASH_OPTCR_nWRP_Pos (16U)
7265 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
7266 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
7267 #define FLASH_OPTCR_nWRP_0 0x00010000U
7268 #define FLASH_OPTCR_nWRP_1 0x00020000U
7269 #define FLASH_OPTCR_nWRP_2 0x00040000U
7270 #define FLASH_OPTCR_nWRP_3 0x00080000U
7271 #define FLASH_OPTCR_nWRP_4 0x00100000U
7272 #define FLASH_OPTCR_nWRP_5 0x00200000U
7273 #define FLASH_OPTCR_nWRP_6 0x00400000U
7274 #define FLASH_OPTCR_nWRP_7 0x00800000U
7275 #define FLASH_OPTCR_nWRP_8 0x01000000U
7276 #define FLASH_OPTCR_nWRP_9 0x02000000U
7277 #define FLASH_OPTCR_nWRP_10 0x04000000U
7278 #define FLASH_OPTCR_nWRP_11 0x08000000U
7279 #define FLASH_OPTCR_DB1M_Pos (30U)
7280 #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
7281 #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
7282 #define FLASH_OPTCR_SPRMOD_Pos (31U)
7283 #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
7284 #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
7285
7286 /****************** Bits definition for FLASH_OPTCR1 register ***************/
7287 #define FLASH_OPTCR1_nWRP_Pos (16U)
7288 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
7289 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
7290 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
7291 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
7292 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
7293 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
7294 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
7295 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
7296 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
7297 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
7298 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
7299 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
7300 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
7301 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
7302
7303 /******************************************************************************/
7304 /* */
7305 /* Flexible Memory Controller */
7306 /* */
7307 /******************************************************************************/
7308 /****************** Bit definition for FMC_BCR1 register *******************/
7309 #define FMC_BCR1_MBKEN_Pos (0U)
7310 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
7311 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
7312 #define FMC_BCR1_MUXEN_Pos (1U)
7313 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
7314 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7315
7316 #define FMC_BCR1_MTYP_Pos (2U)
7317 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
7318 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7319 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
7320 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
7321
7322 #define FMC_BCR1_MWID_Pos (4U)
7323 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
7324 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7325 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
7326 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
7327
7328 #define FMC_BCR1_FACCEN_Pos (6U)
7329 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
7330 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
7331 #define FMC_BCR1_BURSTEN_Pos (8U)
7332 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
7333 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
7334 #define FMC_BCR1_WAITPOL_Pos (9U)
7335 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
7336 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
7337 #define FMC_BCR1_WRAPMOD_Pos (10U)
7338 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
7339 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
7340 #define FMC_BCR1_WAITCFG_Pos (11U)
7341 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
7342 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
7343 #define FMC_BCR1_WREN_Pos (12U)
7344 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
7345 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
7346 #define FMC_BCR1_WAITEN_Pos (13U)
7347 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
7348 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
7349 #define FMC_BCR1_EXTMOD_Pos (14U)
7350 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
7351 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
7352 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
7353 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
7354 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
7355 #define FMC_BCR1_CPSIZE_Pos (16U)
7356 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
7357 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
7358 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
7359 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
7360 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
7361 #define FMC_BCR1_CBURSTRW_Pos (19U)
7362 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
7363 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
7364 #define FMC_BCR1_CCLKEN_Pos (20U)
7365 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
7366 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
7367
7368 /****************** Bit definition for FMC_BCR2 register *******************/
7369 #define FMC_BCR2_MBKEN_Pos (0U)
7370 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
7371 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
7372 #define FMC_BCR2_MUXEN_Pos (1U)
7373 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
7374 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7375
7376 #define FMC_BCR2_MTYP_Pos (2U)
7377 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
7378 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7379 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
7380 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
7381
7382 #define FMC_BCR2_MWID_Pos (4U)
7383 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
7384 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7385 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
7386 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
7387
7388 #define FMC_BCR2_FACCEN_Pos (6U)
7389 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
7390 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
7391 #define FMC_BCR2_BURSTEN_Pos (8U)
7392 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
7393 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
7394 #define FMC_BCR2_WAITPOL_Pos (9U)
7395 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
7396 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
7397 #define FMC_BCR2_WRAPMOD_Pos (10U)
7398 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
7399 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
7400 #define FMC_BCR2_WAITCFG_Pos (11U)
7401 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
7402 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
7403 #define FMC_BCR2_WREN_Pos (12U)
7404 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
7405 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
7406 #define FMC_BCR2_WAITEN_Pos (13U)
7407 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
7408 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
7409 #define FMC_BCR2_EXTMOD_Pos (14U)
7410 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
7411 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
7412 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
7413 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
7414 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
7415 #define FMC_BCR2_CPSIZE_Pos (16U)
7416 #define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
7417 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
7418 #define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
7419 #define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
7420 #define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
7421 #define FMC_BCR2_CBURSTRW_Pos (19U)
7422 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
7423 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
7424
7425 /****************** Bit definition for FMC_BCR3 register *******************/
7426 #define FMC_BCR3_MBKEN_Pos (0U)
7427 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
7428 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
7429 #define FMC_BCR3_MUXEN_Pos (1U)
7430 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
7431 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7432
7433 #define FMC_BCR3_MTYP_Pos (2U)
7434 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
7435 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7436 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
7437 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
7438
7439 #define FMC_BCR3_MWID_Pos (4U)
7440 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
7441 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7442 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
7443 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
7444
7445 #define FMC_BCR3_FACCEN_Pos (6U)
7446 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
7447 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
7448 #define FMC_BCR3_BURSTEN_Pos (8U)
7449 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
7450 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
7451 #define FMC_BCR3_WAITPOL_Pos (9U)
7452 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
7453 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
7454 #define FMC_BCR3_WRAPMOD_Pos (10U)
7455 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
7456 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
7457 #define FMC_BCR3_WAITCFG_Pos (11U)
7458 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
7459 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
7460 #define FMC_BCR3_WREN_Pos (12U)
7461 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
7462 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
7463 #define FMC_BCR3_WAITEN_Pos (13U)
7464 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
7465 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
7466 #define FMC_BCR3_EXTMOD_Pos (14U)
7467 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
7468 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
7469 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
7470 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
7471 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
7472 #define FMC_BCR3_CPSIZE_Pos (16U)
7473 #define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
7474 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
7475 #define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
7476 #define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
7477 #define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
7478 #define FMC_BCR3_CBURSTRW_Pos (19U)
7479 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
7480 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
7481
7482 /****************** Bit definition for FMC_BCR4 register *******************/
7483 #define FMC_BCR4_MBKEN_Pos (0U)
7484 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
7485 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
7486 #define FMC_BCR4_MUXEN_Pos (1U)
7487 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
7488 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7489
7490 #define FMC_BCR4_MTYP_Pos (2U)
7491 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
7492 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7493 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
7494 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
7495
7496 #define FMC_BCR4_MWID_Pos (4U)
7497 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
7498 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7499 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
7500 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
7501
7502 #define FMC_BCR4_FACCEN_Pos (6U)
7503 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
7504 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
7505 #define FMC_BCR4_BURSTEN_Pos (8U)
7506 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
7507 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
7508 #define FMC_BCR4_WAITPOL_Pos (9U)
7509 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
7510 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
7511 #define FMC_BCR4_WRAPMOD_Pos (10U)
7512 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
7513 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
7514 #define FMC_BCR4_WAITCFG_Pos (11U)
7515 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
7516 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
7517 #define FMC_BCR4_WREN_Pos (12U)
7518 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
7519 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
7520 #define FMC_BCR4_WAITEN_Pos (13U)
7521 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
7522 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
7523 #define FMC_BCR4_EXTMOD_Pos (14U)
7524 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
7525 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
7526 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
7527 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
7528 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
7529 #define FMC_BCR4_CPSIZE_Pos (16U)
7530 #define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
7531 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
7532 #define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
7533 #define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
7534 #define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
7535 #define FMC_BCR4_CBURSTRW_Pos (19U)
7536 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
7537 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
7538
7539 /****************** Bit definition for FMC_BTR1 register ******************/
7540 #define FMC_BTR1_ADDSET_Pos (0U)
7541 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7542 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7543 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7544 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7545 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7546 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
7547
7548 #define FMC_BTR1_ADDHLD_Pos (4U)
7549 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7550 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7551 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
7552 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
7553 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
7554 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
7555
7556 #define FMC_BTR1_DATAST_Pos (8U)
7557 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
7558 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7559 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
7560 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
7561 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
7562 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
7563 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
7564 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
7565 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
7566 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
7567
7568 #define FMC_BTR1_BUSTURN_Pos (16U)
7569 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7570 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7571 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
7572 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
7573 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
7574 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
7575
7576 #define FMC_BTR1_CLKDIV_Pos (20U)
7577 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
7578 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7579 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
7580 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
7581 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
7582 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
7583
7584 #define FMC_BTR1_DATLAT_Pos (24U)
7585 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
7586 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7587 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
7588 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
7589 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
7590 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
7591
7592 #define FMC_BTR1_ACCMOD_Pos (28U)
7593 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
7594 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7595 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
7596 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
7597
7598 /****************** Bit definition for FMC_BTR2 register *******************/
7599 #define FMC_BTR2_ADDSET_Pos (0U)
7600 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
7601 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7602 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
7603 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
7604 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
7605 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
7606
7607 #define FMC_BTR2_ADDHLD_Pos (4U)
7608 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7609 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7610 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
7611 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
7612 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
7613 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7614
7615 #define FMC_BTR2_DATAST_Pos (8U)
7616 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
7617 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7618 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
7619 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
7620 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
7621 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
7622 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
7623 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
7624 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
7625 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
7626
7627 #define FMC_BTR2_BUSTURN_Pos (16U)
7628 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7629 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7630 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
7631 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
7632 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
7633 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
7634
7635 #define FMC_BTR2_CLKDIV_Pos (20U)
7636 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
7637 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7638 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
7639 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
7640 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
7641 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
7642
7643 #define FMC_BTR2_DATLAT_Pos (24U)
7644 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
7645 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7646 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
7647 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
7648 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
7649 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
7650
7651 #define FMC_BTR2_ACCMOD_Pos (28U)
7652 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
7653 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7654 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
7655 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
7656
7657 /******************* Bit definition for FMC_BTR3 register *******************/
7658 #define FMC_BTR3_ADDSET_Pos (0U)
7659 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7660 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7661 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7662 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7663 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7664 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7665
7666 #define FMC_BTR3_ADDHLD_Pos (4U)
7667 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7668 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7669 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7670 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7671 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7672 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
7673
7674 #define FMC_BTR3_DATAST_Pos (8U)
7675 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
7676 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7677 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
7678 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
7679 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
7680 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
7681 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
7682 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
7683 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
7684 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
7685
7686 #define FMC_BTR3_BUSTURN_Pos (16U)
7687 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7688 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7689 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
7690 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
7691 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
7692 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
7693
7694 #define FMC_BTR3_CLKDIV_Pos (20U)
7695 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
7696 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7697 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
7698 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
7699 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
7700 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
7701
7702 #define FMC_BTR3_DATLAT_Pos (24U)
7703 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
7704 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7705 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
7706 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
7707 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
7708 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
7709
7710 #define FMC_BTR3_ACCMOD_Pos (28U)
7711 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
7712 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7713 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
7714 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
7715
7716 /****************** Bit definition for FMC_BTR4 register *******************/
7717 #define FMC_BTR4_ADDSET_Pos (0U)
7718 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
7719 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7720 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
7721 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
7722 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
7723 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7724
7725 #define FMC_BTR4_ADDHLD_Pos (4U)
7726 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7727 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7728 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
7729 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
7730 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
7731 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
7732
7733 #define FMC_BTR4_DATAST_Pos (8U)
7734 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
7735 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7736 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
7737 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
7738 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
7739 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
7740 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
7741 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
7742 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
7743 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
7744
7745 #define FMC_BTR4_BUSTURN_Pos (16U)
7746 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7747 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7748 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
7749 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
7750 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
7751 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
7752
7753 #define FMC_BTR4_CLKDIV_Pos (20U)
7754 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
7755 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7756 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
7757 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
7758 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
7759 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
7760
7761 #define FMC_BTR4_DATLAT_Pos (24U)
7762 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
7763 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7764 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
7765 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
7766 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
7767 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
7768
7769 #define FMC_BTR4_ACCMOD_Pos (28U)
7770 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
7771 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7772 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
7773 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
7774
7775 /****************** Bit definition for FMC_BWTR1 register ******************/
7776 #define FMC_BWTR1_ADDSET_Pos (0U)
7777 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
7778 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7779 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
7780 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
7781 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
7782 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
7783
7784 #define FMC_BWTR1_ADDHLD_Pos (4U)
7785 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7786 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7787 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
7788 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
7789 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
7790 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
7791
7792 #define FMC_BWTR1_DATAST_Pos (8U)
7793 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
7794 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7795 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
7796 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
7797 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
7798 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
7799 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
7800 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
7801 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
7802 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
7803
7804 #define FMC_BWTR1_BUSTURN_Pos (16U)
7805 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7806 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7807 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
7808 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
7809 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
7810 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
7811
7812 #define FMC_BWTR1_ACCMOD_Pos (28U)
7813 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
7814 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7815 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
7816 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
7817
7818 /****************** Bit definition for FMC_BWTR2 register ******************/
7819 #define FMC_BWTR2_ADDSET_Pos (0U)
7820 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7821 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7822 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7823 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7824 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7825 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7826
7827 #define FMC_BWTR2_ADDHLD_Pos (4U)
7828 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7829 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7830 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
7831 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
7832 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
7833 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
7834
7835 #define FMC_BWTR2_DATAST_Pos (8U)
7836 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
7837 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7838 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
7839 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
7840 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
7841 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
7842 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
7843 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
7844 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
7845 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
7846
7847 #define FMC_BWTR2_BUSTURN_Pos (16U)
7848 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7849 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7850 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
7851 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
7852 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
7853 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
7854
7855 #define FMC_BWTR2_ACCMOD_Pos (28U)
7856 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
7857 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7858 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
7859 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
7860
7861 /****************** Bit definition for FMC_BWTR3 register ******************/
7862 #define FMC_BWTR3_ADDSET_Pos (0U)
7863 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
7864 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7865 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
7866 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
7867 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
7868 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7869
7870 #define FMC_BWTR3_ADDHLD_Pos (4U)
7871 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7872 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7873 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
7874 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
7875 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
7876 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
7877
7878 #define FMC_BWTR3_DATAST_Pos (8U)
7879 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
7880 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7881 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
7882 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
7883 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
7884 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
7885 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
7886 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
7887 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
7888 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
7889
7890 #define FMC_BWTR3_BUSTURN_Pos (16U)
7891 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7892 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7893 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
7894 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
7895 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
7896 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
7897
7898 #define FMC_BWTR3_ACCMOD_Pos (28U)
7899 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
7900 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7901 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
7902 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
7903
7904 /****************** Bit definition for FMC_BWTR4 register ******************/
7905 #define FMC_BWTR4_ADDSET_Pos (0U)
7906 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
7907 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7908 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
7909 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
7910 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
7911 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
7912
7913 #define FMC_BWTR4_ADDHLD_Pos (4U)
7914 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7915 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7916 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
7917 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
7918 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
7919 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
7920
7921 #define FMC_BWTR4_DATAST_Pos (8U)
7922 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
7923 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7924 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
7925 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
7926 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
7927 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
7928 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
7929 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
7930 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
7931 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
7932
7933 #define FMC_BWTR4_BUSTURN_Pos (16U)
7934 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7935 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7936 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
7937 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
7938 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
7939 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
7940
7941 #define FMC_BWTR4_ACCMOD_Pos (28U)
7942 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
7943 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7944 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
7945 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
7946
7947 /****************** Bit definition for FMC_PCR2 register *******************/
7948
7949 #define FMC_PCR2_PWAITEN_Pos (1U)
7950 #define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
7951 #define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
7952 #define FMC_PCR2_PBKEN_Pos (2U)
7953 #define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
7954 #define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7955 #define FMC_PCR2_PTYP_Pos (3U)
7956 #define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
7957 #define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
7958
7959 #define FMC_PCR2_PWID_Pos (4U)
7960 #define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
7961 #define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7962 #define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
7963 #define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
7964
7965 #define FMC_PCR2_ECCEN_Pos (6U)
7966 #define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
7967 #define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
7968
7969 #define FMC_PCR2_TCLR_Pos (9U)
7970 #define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
7971 #define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7972 #define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
7973 #define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
7974 #define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
7975 #define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
7976
7977 #define FMC_PCR2_TAR_Pos (13U)
7978 #define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
7979 #define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7980 #define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
7981 #define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
7982 #define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
7983 #define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
7984
7985 #define FMC_PCR2_ECCPS_Pos (17U)
7986 #define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
7987 #define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
7988 #define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
7989 #define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
7990 #define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
7991
7992 /****************** Bit definition for FMC_PCR3 register *******************/
7993 #define FMC_PCR3_PWAITEN_Pos (1U)
7994 #define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
7995 #define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
7996 #define FMC_PCR3_PBKEN_Pos (2U)
7997 #define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
7998 #define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7999 #define FMC_PCR3_PTYP_Pos (3U)
8000 #define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
8001 #define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
8002
8003 #define FMC_PCR3_PWID_Pos (4U)
8004 #define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
8005 #define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
8006 #define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
8007 #define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
8008
8009 #define FMC_PCR3_ECCEN_Pos (6U)
8010 #define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
8011 #define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
8012
8013 #define FMC_PCR3_TCLR_Pos (9U)
8014 #define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
8015 #define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
8016 #define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
8017 #define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
8018 #define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
8019 #define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
8020
8021 #define FMC_PCR3_TAR_Pos (13U)
8022 #define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
8023 #define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
8024 #define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
8025 #define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
8026 #define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
8027 #define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
8028
8029 #define FMC_PCR3_ECCPS_Pos (17U)
8030 #define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
8031 #define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
8032 #define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
8033 #define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
8034 #define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
8035
8036 /****************** Bit definition for FMC_PCR4 register *******************/
8037 #define FMC_PCR4_PWAITEN_Pos (1U)
8038 #define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
8039 #define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
8040 #define FMC_PCR4_PBKEN_Pos (2U)
8041 #define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
8042 #define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
8043 #define FMC_PCR4_PTYP_Pos (3U)
8044 #define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
8045 #define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
8046
8047 #define FMC_PCR4_PWID_Pos (4U)
8048 #define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
8049 #define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
8050 #define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
8051 #define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
8052
8053 #define FMC_PCR4_ECCEN_Pos (6U)
8054 #define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
8055 #define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
8056
8057 #define FMC_PCR4_TCLR_Pos (9U)
8058 #define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
8059 #define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
8060 #define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
8061 #define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
8062 #define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
8063 #define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
8064
8065 #define FMC_PCR4_TAR_Pos (13U)
8066 #define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
8067 #define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
8068 #define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
8069 #define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
8070 #define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
8071 #define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
8072
8073 #define FMC_PCR4_ECCPS_Pos (17U)
8074 #define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
8075 #define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
8076 #define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
8077 #define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
8078 #define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
8079
8080 /******************* Bit definition for FMC_SR2 register *******************/
8081 #define FMC_SR2_IRS_Pos (0U)
8082 #define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
8083 #define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
8084 #define FMC_SR2_ILS_Pos (1U)
8085 #define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
8086 #define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
8087 #define FMC_SR2_IFS_Pos (2U)
8088 #define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
8089 #define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
8090 #define FMC_SR2_IREN_Pos (3U)
8091 #define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
8092 #define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8093 #define FMC_SR2_ILEN_Pos (4U)
8094 #define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
8095 #define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8096 #define FMC_SR2_IFEN_Pos (5U)
8097 #define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
8098 #define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8099 #define FMC_SR2_FEMPT_Pos (6U)
8100 #define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
8101 #define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
8102
8103 /******************* Bit definition for FMC_SR3 register *******************/
8104 #define FMC_SR3_IRS_Pos (0U)
8105 #define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
8106 #define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
8107 #define FMC_SR3_ILS_Pos (1U)
8108 #define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
8109 #define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
8110 #define FMC_SR3_IFS_Pos (2U)
8111 #define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
8112 #define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
8113 #define FMC_SR3_IREN_Pos (3U)
8114 #define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
8115 #define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8116 #define FMC_SR3_ILEN_Pos (4U)
8117 #define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
8118 #define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8119 #define FMC_SR3_IFEN_Pos (5U)
8120 #define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
8121 #define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8122 #define FMC_SR3_FEMPT_Pos (6U)
8123 #define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
8124 #define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
8125
8126 /******************* Bit definition for FMC_SR4 register *******************/
8127 #define FMC_SR4_IRS_Pos (0U)
8128 #define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
8129 #define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
8130 #define FMC_SR4_ILS_Pos (1U)
8131 #define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
8132 #define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
8133 #define FMC_SR4_IFS_Pos (2U)
8134 #define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
8135 #define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
8136 #define FMC_SR4_IREN_Pos (3U)
8137 #define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
8138 #define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8139 #define FMC_SR4_ILEN_Pos (4U)
8140 #define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
8141 #define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8142 #define FMC_SR4_IFEN_Pos (5U)
8143 #define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
8144 #define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8145 #define FMC_SR4_FEMPT_Pos (6U)
8146 #define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
8147 #define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
8148
8149 /****************** Bit definition for FMC_PMEM2 register ******************/
8150 #define FMC_PMEM2_MEMSET2_Pos (0U)
8151 #define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
8152 #define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
8153 #define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
8154 #define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
8155 #define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
8156 #define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
8157 #define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
8158 #define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
8159 #define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
8160 #define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
8161
8162 #define FMC_PMEM2_MEMWAIT2_Pos (8U)
8163 #define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
8164 #define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
8165 #define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
8166 #define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
8167 #define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
8168 #define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
8169 #define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
8170 #define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
8171 #define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
8172 #define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
8173
8174 #define FMC_PMEM2_MEMHOLD2_Pos (16U)
8175 #define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
8176 #define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
8177 #define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
8178 #define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
8179 #define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
8180 #define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
8181 #define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
8182 #define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
8183 #define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
8184 #define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
8185
8186 #define FMC_PMEM2_MEMHIZ2_Pos (24U)
8187 #define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
8188 #define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
8189 #define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
8190 #define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
8191 #define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
8192 #define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
8193 #define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
8194 #define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
8195 #define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
8196 #define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
8197
8198 /****************** Bit definition for FMC_PMEM3 register ******************/
8199 #define FMC_PMEM3_MEMSET3_Pos (0U)
8200 #define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
8201 #define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
8202 #define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
8203 #define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
8204 #define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
8205 #define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
8206 #define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
8207 #define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
8208 #define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
8209 #define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
8210
8211 #define FMC_PMEM3_MEMWAIT3_Pos (8U)
8212 #define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
8213 #define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
8214 #define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
8215 #define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
8216 #define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
8217 #define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
8218 #define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
8219 #define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
8220 #define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
8221 #define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
8222
8223 #define FMC_PMEM3_MEMHOLD3_Pos (16U)
8224 #define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
8225 #define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
8226 #define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
8227 #define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
8228 #define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
8229 #define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
8230 #define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
8231 #define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
8232 #define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
8233 #define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
8234
8235 #define FMC_PMEM3_MEMHIZ3_Pos (24U)
8236 #define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
8237 #define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
8238 #define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
8239 #define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
8240 #define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
8241 #define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
8242 #define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
8243 #define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
8244 #define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
8245 #define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
8246
8247 /****************** Bit definition for FMC_PMEM4 register ******************/
8248 #define FMC_PMEM4_MEMSET4_Pos (0U)
8249 #define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
8250 #define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
8251 #define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
8252 #define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
8253 #define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
8254 #define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
8255 #define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
8256 #define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
8257 #define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
8258 #define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
8259
8260 #define FMC_PMEM4_MEMWAIT4_Pos (8U)
8261 #define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
8262 #define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
8263 #define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
8264 #define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
8265 #define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
8266 #define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
8267 #define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
8268 #define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
8269 #define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
8270 #define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
8271
8272 #define FMC_PMEM4_MEMHOLD4_Pos (16U)
8273 #define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
8274 #define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
8275 #define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
8276 #define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
8277 #define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
8278 #define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
8279 #define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
8280 #define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
8281 #define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
8282 #define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
8283
8284 #define FMC_PMEM4_MEMHIZ4_Pos (24U)
8285 #define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
8286 #define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
8287 #define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
8288 #define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
8289 #define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
8290 #define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
8291 #define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
8292 #define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
8293 #define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
8294 #define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
8295
8296 /****************** Bit definition for FMC_PATT2 register ******************/
8297 #define FMC_PATT2_ATTSET2_Pos (0U)
8298 #define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
8299 #define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
8300 #define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
8301 #define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
8302 #define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
8303 #define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
8304 #define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
8305 #define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
8306 #define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
8307 #define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
8308
8309 #define FMC_PATT2_ATTWAIT2_Pos (8U)
8310 #define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
8311 #define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
8312 #define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
8313 #define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
8314 #define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
8315 #define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
8316 #define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
8317 #define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
8318 #define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
8319 #define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
8320
8321 #define FMC_PATT2_ATTHOLD2_Pos (16U)
8322 #define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
8323 #define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
8324 #define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
8325 #define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
8326 #define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
8327 #define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
8328 #define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
8329 #define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
8330 #define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
8331 #define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
8332
8333 #define FMC_PATT2_ATTHIZ2_Pos (24U)
8334 #define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
8335 #define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
8336 #define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
8337 #define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
8338 #define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
8339 #define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
8340 #define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
8341 #define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
8342 #define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
8343 #define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
8344
8345 /****************** Bit definition for FMC_PATT3 register ******************/
8346 #define FMC_PATT3_ATTSET3_Pos (0U)
8347 #define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
8348 #define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
8349 #define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
8350 #define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
8351 #define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
8352 #define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
8353 #define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
8354 #define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
8355 #define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
8356 #define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
8357
8358 #define FMC_PATT3_ATTWAIT3_Pos (8U)
8359 #define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
8360 #define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
8361 #define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
8362 #define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
8363 #define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
8364 #define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
8365 #define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
8366 #define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
8367 #define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
8368 #define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
8369
8370 #define FMC_PATT3_ATTHOLD3_Pos (16U)
8371 #define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
8372 #define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
8373 #define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
8374 #define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
8375 #define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
8376 #define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
8377 #define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
8378 #define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
8379 #define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
8380 #define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
8381
8382 #define FMC_PATT3_ATTHIZ3_Pos (24U)
8383 #define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
8384 #define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
8385 #define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
8386 #define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
8387 #define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
8388 #define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
8389 #define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
8390 #define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
8391 #define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
8392 #define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
8393
8394 /****************** Bit definition for FMC_PATT4 register ******************/
8395 #define FMC_PATT4_ATTSET4_Pos (0U)
8396 #define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
8397 #define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
8398 #define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
8399 #define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
8400 #define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
8401 #define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
8402 #define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
8403 #define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
8404 #define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
8405 #define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
8406
8407 #define FMC_PATT4_ATTWAIT4_Pos (8U)
8408 #define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
8409 #define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
8410 #define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
8411 #define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
8412 #define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
8413 #define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
8414 #define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
8415 #define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
8416 #define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
8417 #define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
8418
8419 #define FMC_PATT4_ATTHOLD4_Pos (16U)
8420 #define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
8421 #define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
8422 #define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
8423 #define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
8424 #define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
8425 #define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
8426 #define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
8427 #define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
8428 #define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
8429 #define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
8430
8431 #define FMC_PATT4_ATTHIZ4_Pos (24U)
8432 #define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
8433 #define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
8434 #define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
8435 #define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
8436 #define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
8437 #define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
8438 #define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
8439 #define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
8440 #define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
8441 #define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
8442
8443 /****************** Bit definition for FMC_PIO4 register *******************/
8444 #define FMC_PIO4_IOSET4_Pos (0U)
8445 #define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
8446 #define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
8447 #define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
8448 #define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
8449 #define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
8450 #define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
8451 #define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
8452 #define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
8453 #define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
8454 #define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
8455
8456 #define FMC_PIO4_IOWAIT4_Pos (8U)
8457 #define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
8458 #define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
8459 #define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
8460 #define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
8461 #define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
8462 #define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
8463 #define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
8464 #define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
8465 #define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
8466 #define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
8467
8468 #define FMC_PIO4_IOHOLD4_Pos (16U)
8469 #define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
8470 #define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
8471 #define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
8472 #define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
8473 #define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
8474 #define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
8475 #define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
8476 #define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
8477 #define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
8478 #define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
8479
8480 #define FMC_PIO4_IOHIZ4_Pos (24U)
8481 #define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
8482 #define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
8483 #define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
8484 #define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
8485 #define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
8486 #define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
8487 #define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
8488 #define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
8489 #define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
8490 #define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
8491
8492
8493 /****************** Bit definition for FMC_ECCR2 register ******************/
8494 #define FMC_ECCR2_ECC2_Pos (0U)
8495 #define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
8496 #define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
8497
8498 /****************** Bit definition for FMC_ECCR3 register ******************/
8499 #define FMC_ECCR3_ECC3_Pos (0U)
8500 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
8501 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
8502
8503 /****************** Bit definition for FMC_SDCR1 register ******************/
8504 #define FMC_SDCR1_NC_Pos (0U)
8505 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
8506 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
8507 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
8508 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
8509
8510 #define FMC_SDCR1_NR_Pos (2U)
8511 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
8512 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
8513 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
8514 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
8515
8516 #define FMC_SDCR1_MWID_Pos (4U)
8517 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
8518 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
8519 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
8520 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
8521
8522 #define FMC_SDCR1_NB_Pos (6U)
8523 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
8524 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
8525
8526 #define FMC_SDCR1_CAS_Pos (7U)
8527 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
8528 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
8529 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
8530 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
8531
8532 #define FMC_SDCR1_WP_Pos (9U)
8533 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
8534 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
8535
8536 #define FMC_SDCR1_SDCLK_Pos (10U)
8537 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8538 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
8539 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8540 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
8541
8542 #define FMC_SDCR1_RBURST_Pos (12U)
8543 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
8544 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
8545
8546 #define FMC_SDCR1_RPIPE_Pos (13U)
8547 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
8548 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
8549 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
8550 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
8551
8552 /****************** Bit definition for FMC_SDCR2 register ******************/
8553 #define FMC_SDCR2_NC_Pos (0U)
8554 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
8555 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
8556 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
8557 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
8558
8559 #define FMC_SDCR2_NR_Pos (2U)
8560 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
8561 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
8562 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
8563 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
8564
8565 #define FMC_SDCR2_MWID_Pos (4U)
8566 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
8567 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
8568 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
8569 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
8570
8571 #define FMC_SDCR2_NB_Pos (6U)
8572 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
8573 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
8574
8575 #define FMC_SDCR2_CAS_Pos (7U)
8576 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
8577 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
8578 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
8579 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
8580
8581 #define FMC_SDCR2_WP_Pos (9U)
8582 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
8583 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
8584
8585 #define FMC_SDCR2_SDCLK_Pos (10U)
8586 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
8587 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
8588 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
8589 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
8590
8591 #define FMC_SDCR2_RBURST_Pos (12U)
8592 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
8593 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
8594
8595 #define FMC_SDCR2_RPIPE_Pos (13U)
8596 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
8597 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
8598 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
8599 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
8600
8601 /****************** Bit definition for FMC_SDTR1 register ******************/
8602 #define FMC_SDTR1_TMRD_Pos (0U)
8603 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
8604 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
8605 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
8606 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
8607 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
8608 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
8609
8610 #define FMC_SDTR1_TXSR_Pos (4U)
8611 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
8612 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
8613 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
8614 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
8615 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
8616 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
8617
8618 #define FMC_SDTR1_TRAS_Pos (8U)
8619 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
8620 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
8621 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
8622 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
8623 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
8624 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
8625
8626 #define FMC_SDTR1_TRC_Pos (12U)
8627 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
8628 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
8629 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
8630 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
8631 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
8632
8633 #define FMC_SDTR1_TWR_Pos (16U)
8634 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8635 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
8636 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8637 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8638 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
8639
8640 #define FMC_SDTR1_TRP_Pos (20U)
8641 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
8642 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
8643 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
8644 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
8645 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
8646
8647 #define FMC_SDTR1_TRCD_Pos (24U)
8648 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8649 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
8650 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8651 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8652 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
8653
8654 /****************** Bit definition for FMC_SDTR2 register ******************/
8655 #define FMC_SDTR2_TMRD_Pos (0U)
8656 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
8657 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
8658 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
8659 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
8660 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
8661 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
8662
8663 #define FMC_SDTR2_TXSR_Pos (4U)
8664 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
8665 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
8666 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
8667 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
8668 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
8669 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
8670
8671 #define FMC_SDTR2_TRAS_Pos (8U)
8672 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8673 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
8674 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8675 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8676 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8677 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
8678
8679 #define FMC_SDTR2_TRC_Pos (12U)
8680 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8681 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
8682 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8683 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8684 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
8685
8686 #define FMC_SDTR2_TWR_Pos (16U)
8687 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8688 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
8689 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8690 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8691 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
8692
8693 #define FMC_SDTR2_TRP_Pos (20U)
8694 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
8695 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
8696 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
8697 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
8698 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
8699
8700 #define FMC_SDTR2_TRCD_Pos (24U)
8701 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
8702 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
8703 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
8704 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
8705 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
8706
8707 /****************** Bit definition for FMC_SDCMR register ******************/
8708 #define FMC_SDCMR_MODE_Pos (0U)
8709 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
8710 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
8711 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
8712 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
8713 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
8714
8715 #define FMC_SDCMR_CTB2_Pos (3U)
8716 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
8717 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
8718
8719 #define FMC_SDCMR_CTB1_Pos (4U)
8720 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
8721 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
8722
8723 #define FMC_SDCMR_NRFS_Pos (5U)
8724 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
8725 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
8726 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
8727 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
8728 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
8729 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
8730
8731 #define FMC_SDCMR_MRD_Pos (9U)
8732 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
8733 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
8734
8735 /****************** Bit definition for FMC_SDRTR register ******************/
8736 #define FMC_SDRTR_CRE_Pos (0U)
8737 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
8738 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
8739
8740 #define FMC_SDRTR_COUNT_Pos (1U)
8741 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
8742 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
8743
8744 #define FMC_SDRTR_REIE_Pos (14U)
8745 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
8746 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
8747
8748 /****************** Bit definition for FMC_SDSR register ******************/
8749 #define FMC_SDSR_RE_Pos (0U)
8750 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
8751 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
8752
8753 #define FMC_SDSR_MODES1_Pos (1U)
8754 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
8755 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
8756 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
8757 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
8758
8759 #define FMC_SDSR_MODES2_Pos (3U)
8760 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
8761 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
8762 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
8763 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
8764 #define FMC_SDSR_BUSY_Pos (5U)
8765 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
8766 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
8767
8768 /******************************************************************************/
8769 /* */
8770 /* General Purpose I/O */
8771 /* */
8772 /******************************************************************************/
8773 /****************** Bits definition for GPIO_MODER register *****************/
8774 #define GPIO_MODER_MODE0_Pos (0U)
8775 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
8776 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
8777 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
8778 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
8779 #define GPIO_MODER_MODE1_Pos (2U)
8780 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
8781 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
8782 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
8783 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
8784 #define GPIO_MODER_MODE2_Pos (4U)
8785 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
8786 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
8787 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
8788 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
8789 #define GPIO_MODER_MODE3_Pos (6U)
8790 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
8791 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
8792 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
8793 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
8794 #define GPIO_MODER_MODE4_Pos (8U)
8795 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
8796 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
8797 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
8798 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
8799 #define GPIO_MODER_MODE5_Pos (10U)
8800 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
8801 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
8802 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
8803 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
8804 #define GPIO_MODER_MODE6_Pos (12U)
8805 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
8806 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
8807 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
8808 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
8809 #define GPIO_MODER_MODE7_Pos (14U)
8810 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
8811 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
8812 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
8813 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
8814 #define GPIO_MODER_MODE8_Pos (16U)
8815 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
8816 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
8817 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
8818 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
8819 #define GPIO_MODER_MODE9_Pos (18U)
8820 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
8821 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
8822 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
8823 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
8824 #define GPIO_MODER_MODE10_Pos (20U)
8825 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
8826 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
8827 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
8828 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
8829 #define GPIO_MODER_MODE11_Pos (22U)
8830 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
8831 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
8832 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
8833 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
8834 #define GPIO_MODER_MODE12_Pos (24U)
8835 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
8836 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
8837 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
8838 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
8839 #define GPIO_MODER_MODE13_Pos (26U)
8840 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
8841 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
8842 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
8843 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
8844 #define GPIO_MODER_MODE14_Pos (28U)
8845 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
8846 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8847 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
8848 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
8849 #define GPIO_MODER_MODE15_Pos (30U)
8850 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
8851 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8852 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
8853 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
8854
8855 /* Legacy defines */
8856 #define GPIO_MODER_MODER0_Pos (0U)
8857 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
8858 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8859 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
8860 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
8861 #define GPIO_MODER_MODER1_Pos (2U)
8862 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
8863 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8864 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
8865 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
8866 #define GPIO_MODER_MODER2_Pos (4U)
8867 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
8868 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8869 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
8870 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
8871 #define GPIO_MODER_MODER3_Pos (6U)
8872 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
8873 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8874 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
8875 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
8876 #define GPIO_MODER_MODER4_Pos (8U)
8877 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
8878 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8879 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
8880 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
8881 #define GPIO_MODER_MODER5_Pos (10U)
8882 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
8883 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8884 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
8885 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
8886 #define GPIO_MODER_MODER6_Pos (12U)
8887 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
8888 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8889 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
8890 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
8891 #define GPIO_MODER_MODER7_Pos (14U)
8892 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
8893 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8894 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
8895 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
8896 #define GPIO_MODER_MODER8_Pos (16U)
8897 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
8898 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8899 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
8900 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
8901 #define GPIO_MODER_MODER9_Pos (18U)
8902 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
8903 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8904 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
8905 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
8906 #define GPIO_MODER_MODER10_Pos (20U)
8907 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
8908 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8909 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
8910 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
8911 #define GPIO_MODER_MODER11_Pos (22U)
8912 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
8913 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8914 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
8915 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
8916 #define GPIO_MODER_MODER12_Pos (24U)
8917 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
8918 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8919 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
8920 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
8921 #define GPIO_MODER_MODER13_Pos (26U)
8922 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
8923 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8924 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
8925 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
8926 #define GPIO_MODER_MODER14_Pos (28U)
8927 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
8928 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8929 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
8930 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
8931 #define GPIO_MODER_MODER15_Pos (30U)
8932 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
8933 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8934 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
8935 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
8936
8937 /****************** Bits definition for GPIO_OTYPER register ****************/
8938 #define GPIO_OTYPER_OT0_Pos (0U)
8939 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
8940 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8941 #define GPIO_OTYPER_OT1_Pos (1U)
8942 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
8943 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8944 #define GPIO_OTYPER_OT2_Pos (2U)
8945 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
8946 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8947 #define GPIO_OTYPER_OT3_Pos (3U)
8948 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
8949 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8950 #define GPIO_OTYPER_OT4_Pos (4U)
8951 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
8952 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8953 #define GPIO_OTYPER_OT5_Pos (5U)
8954 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
8955 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8956 #define GPIO_OTYPER_OT6_Pos (6U)
8957 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
8958 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8959 #define GPIO_OTYPER_OT7_Pos (7U)
8960 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
8961 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8962 #define GPIO_OTYPER_OT8_Pos (8U)
8963 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
8964 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8965 #define GPIO_OTYPER_OT9_Pos (9U)
8966 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
8967 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8968 #define GPIO_OTYPER_OT10_Pos (10U)
8969 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
8970 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8971 #define GPIO_OTYPER_OT11_Pos (11U)
8972 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
8973 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8974 #define GPIO_OTYPER_OT12_Pos (12U)
8975 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
8976 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8977 #define GPIO_OTYPER_OT13_Pos (13U)
8978 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
8979 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8980 #define GPIO_OTYPER_OT14_Pos (14U)
8981 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
8982 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8983 #define GPIO_OTYPER_OT15_Pos (15U)
8984 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
8985 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8986
8987 /* Legacy defines */
8988 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8989 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8990 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8991 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8992 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8993 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8994 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8995 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8996 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8997 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8998 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8999 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
9000 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
9001 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
9002 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
9003 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
9004
9005 /****************** Bits definition for GPIO_OSPEEDR register ***************/
9006 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
9007 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
9008 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
9009 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
9010 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
9011 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
9012 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
9013 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
9014 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
9015 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
9016 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
9017 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
9018 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
9019 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
9020 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
9021 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
9022 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
9023 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
9024 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
9025 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
9026 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
9027 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
9028 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
9029 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
9030 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
9031 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
9032 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
9033 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
9034 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
9035 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
9036 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
9037 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
9038 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
9039 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
9040 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
9041 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
9042 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
9043 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
9044 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
9045 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
9046 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
9047 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
9048 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
9049 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
9050 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
9051 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
9052 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
9053 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
9054 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
9055 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
9056 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
9057 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
9058 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
9059 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
9060 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
9061 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
9062 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
9063 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
9064 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
9065 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
9066 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
9067 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
9068 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
9069 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
9070 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
9071 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
9072 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
9073 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
9074 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
9075 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
9076 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
9077 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
9078 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
9079 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
9080 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
9081 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
9082 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
9083 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
9084 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
9085 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
9086
9087 /* Legacy defines */
9088 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
9089 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
9090 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
9091 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
9092 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
9093 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
9094 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
9095 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
9096 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
9097 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
9098 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
9099 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
9100 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
9101 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
9102 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
9103 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
9104 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
9105 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
9106 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
9107 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
9108 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
9109 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
9110 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
9111 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
9112 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
9113 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
9114 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
9115 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
9116 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
9117 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
9118 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
9119 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
9120 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
9121 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
9122 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
9123 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
9124 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
9125 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
9126 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
9127 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
9128 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
9129 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
9130 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
9131 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
9132 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
9133 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
9134 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
9135 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
9136
9137 /****************** Bits definition for GPIO_PUPDR register *****************/
9138 #define GPIO_PUPDR_PUPD0_Pos (0U)
9139 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
9140 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
9141 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
9142 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
9143 #define GPIO_PUPDR_PUPD1_Pos (2U)
9144 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
9145 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
9146 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
9147 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
9148 #define GPIO_PUPDR_PUPD2_Pos (4U)
9149 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
9150 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
9151 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
9152 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
9153 #define GPIO_PUPDR_PUPD3_Pos (6U)
9154 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
9155 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
9156 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
9157 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
9158 #define GPIO_PUPDR_PUPD4_Pos (8U)
9159 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
9160 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
9161 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
9162 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
9163 #define GPIO_PUPDR_PUPD5_Pos (10U)
9164 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
9165 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
9166 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
9167 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
9168 #define GPIO_PUPDR_PUPD6_Pos (12U)
9169 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
9170 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
9171 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
9172 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
9173 #define GPIO_PUPDR_PUPD7_Pos (14U)
9174 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
9175 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
9176 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
9177 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
9178 #define GPIO_PUPDR_PUPD8_Pos (16U)
9179 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
9180 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
9181 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
9182 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
9183 #define GPIO_PUPDR_PUPD9_Pos (18U)
9184 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
9185 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
9186 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
9187 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
9188 #define GPIO_PUPDR_PUPD10_Pos (20U)
9189 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
9190 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
9191 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
9192 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
9193 #define GPIO_PUPDR_PUPD11_Pos (22U)
9194 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
9195 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
9196 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
9197 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
9198 #define GPIO_PUPDR_PUPD12_Pos (24U)
9199 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
9200 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
9201 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
9202 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
9203 #define GPIO_PUPDR_PUPD13_Pos (26U)
9204 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
9205 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
9206 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
9207 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
9208 #define GPIO_PUPDR_PUPD14_Pos (28U)
9209 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
9210 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
9211 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
9212 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
9213 #define GPIO_PUPDR_PUPD15_Pos (30U)
9214 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
9215 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
9216 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
9217 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
9218
9219 /* Legacy defines */
9220 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
9221 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
9222 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
9223 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
9224 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
9225 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
9226 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
9227 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
9228 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
9229 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
9230 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
9231 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
9232 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
9233 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
9234 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
9235 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
9236 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
9237 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
9238 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
9239 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
9240 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
9241 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
9242 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
9243 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
9244 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
9245 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
9246 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
9247 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
9248 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
9249 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
9250 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
9251 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
9252 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
9253 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
9254 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
9255 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
9256 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
9257 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
9258 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
9259 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
9260 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
9261 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
9262 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
9263 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
9264 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
9265 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
9266 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
9267 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
9268
9269 /****************** Bits definition for GPIO_IDR register *******************/
9270 #define GPIO_IDR_ID0_Pos (0U)
9271 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
9272 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
9273 #define GPIO_IDR_ID1_Pos (1U)
9274 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
9275 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
9276 #define GPIO_IDR_ID2_Pos (2U)
9277 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
9278 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
9279 #define GPIO_IDR_ID3_Pos (3U)
9280 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
9281 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
9282 #define GPIO_IDR_ID4_Pos (4U)
9283 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
9284 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
9285 #define GPIO_IDR_ID5_Pos (5U)
9286 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
9287 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
9288 #define GPIO_IDR_ID6_Pos (6U)
9289 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
9290 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
9291 #define GPIO_IDR_ID7_Pos (7U)
9292 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
9293 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
9294 #define GPIO_IDR_ID8_Pos (8U)
9295 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
9296 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
9297 #define GPIO_IDR_ID9_Pos (9U)
9298 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
9299 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
9300 #define GPIO_IDR_ID10_Pos (10U)
9301 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
9302 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
9303 #define GPIO_IDR_ID11_Pos (11U)
9304 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
9305 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
9306 #define GPIO_IDR_ID12_Pos (12U)
9307 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
9308 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
9309 #define GPIO_IDR_ID13_Pos (13U)
9310 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
9311 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
9312 #define GPIO_IDR_ID14_Pos (14U)
9313 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
9314 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
9315 #define GPIO_IDR_ID15_Pos (15U)
9316 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
9317 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
9318
9319 /* Legacy defines */
9320 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
9321 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
9322 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
9323 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
9324 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
9325 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
9326 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
9327 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
9328 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
9329 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
9330 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
9331 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
9332 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
9333 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
9334 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
9335 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
9336
9337 /****************** Bits definition for GPIO_ODR register *******************/
9338 #define GPIO_ODR_OD0_Pos (0U)
9339 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
9340 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
9341 #define GPIO_ODR_OD1_Pos (1U)
9342 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
9343 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
9344 #define GPIO_ODR_OD2_Pos (2U)
9345 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
9346 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
9347 #define GPIO_ODR_OD3_Pos (3U)
9348 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
9349 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
9350 #define GPIO_ODR_OD4_Pos (4U)
9351 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
9352 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
9353 #define GPIO_ODR_OD5_Pos (5U)
9354 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
9355 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
9356 #define GPIO_ODR_OD6_Pos (6U)
9357 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
9358 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
9359 #define GPIO_ODR_OD7_Pos (7U)
9360 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
9361 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
9362 #define GPIO_ODR_OD8_Pos (8U)
9363 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
9364 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
9365 #define GPIO_ODR_OD9_Pos (9U)
9366 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
9367 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
9368 #define GPIO_ODR_OD10_Pos (10U)
9369 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
9370 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
9371 #define GPIO_ODR_OD11_Pos (11U)
9372 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
9373 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
9374 #define GPIO_ODR_OD12_Pos (12U)
9375 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
9376 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
9377 #define GPIO_ODR_OD13_Pos (13U)
9378 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
9379 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
9380 #define GPIO_ODR_OD14_Pos (14U)
9381 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
9382 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
9383 #define GPIO_ODR_OD15_Pos (15U)
9384 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
9385 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
9386 /* Legacy defines */
9387 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
9388 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
9389 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
9390 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
9391 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
9392 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
9393 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
9394 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
9395 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
9396 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
9397 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
9398 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
9399 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
9400 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
9401 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
9402 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
9403
9404 /****************** Bits definition for GPIO_BSRR register ******************/
9405 #define GPIO_BSRR_BS0_Pos (0U)
9406 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
9407 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
9408 #define GPIO_BSRR_BS1_Pos (1U)
9409 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
9410 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
9411 #define GPIO_BSRR_BS2_Pos (2U)
9412 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
9413 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
9414 #define GPIO_BSRR_BS3_Pos (3U)
9415 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
9416 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
9417 #define GPIO_BSRR_BS4_Pos (4U)
9418 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
9419 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
9420 #define GPIO_BSRR_BS5_Pos (5U)
9421 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
9422 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
9423 #define GPIO_BSRR_BS6_Pos (6U)
9424 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
9425 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
9426 #define GPIO_BSRR_BS7_Pos (7U)
9427 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
9428 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
9429 #define GPIO_BSRR_BS8_Pos (8U)
9430 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
9431 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
9432 #define GPIO_BSRR_BS9_Pos (9U)
9433 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
9434 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
9435 #define GPIO_BSRR_BS10_Pos (10U)
9436 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
9437 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
9438 #define GPIO_BSRR_BS11_Pos (11U)
9439 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
9440 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
9441 #define GPIO_BSRR_BS12_Pos (12U)
9442 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
9443 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
9444 #define GPIO_BSRR_BS13_Pos (13U)
9445 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
9446 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
9447 #define GPIO_BSRR_BS14_Pos (14U)
9448 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
9449 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
9450 #define GPIO_BSRR_BS15_Pos (15U)
9451 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
9452 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
9453 #define GPIO_BSRR_BR0_Pos (16U)
9454 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
9455 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
9456 #define GPIO_BSRR_BR1_Pos (17U)
9457 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
9458 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
9459 #define GPIO_BSRR_BR2_Pos (18U)
9460 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
9461 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
9462 #define GPIO_BSRR_BR3_Pos (19U)
9463 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
9464 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
9465 #define GPIO_BSRR_BR4_Pos (20U)
9466 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
9467 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
9468 #define GPIO_BSRR_BR5_Pos (21U)
9469 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
9470 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
9471 #define GPIO_BSRR_BR6_Pos (22U)
9472 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
9473 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
9474 #define GPIO_BSRR_BR7_Pos (23U)
9475 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
9476 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
9477 #define GPIO_BSRR_BR8_Pos (24U)
9478 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
9479 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
9480 #define GPIO_BSRR_BR9_Pos (25U)
9481 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
9482 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
9483 #define GPIO_BSRR_BR10_Pos (26U)
9484 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
9485 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
9486 #define GPIO_BSRR_BR11_Pos (27U)
9487 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
9488 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
9489 #define GPIO_BSRR_BR12_Pos (28U)
9490 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
9491 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
9492 #define GPIO_BSRR_BR13_Pos (29U)
9493 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
9494 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
9495 #define GPIO_BSRR_BR14_Pos (30U)
9496 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
9497 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
9498 #define GPIO_BSRR_BR15_Pos (31U)
9499 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
9500 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
9501
9502 /* Legacy defines */
9503 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
9504 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
9505 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
9506 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
9507 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
9508 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
9509 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
9510 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
9511 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
9512 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
9513 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
9514 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
9515 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
9516 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
9517 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
9518 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
9519 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
9520 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
9521 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
9522 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
9523 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
9524 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
9525 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
9526 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
9527 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
9528 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
9529 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
9530 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
9531 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
9532 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
9533 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
9534 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
9535 /****************** Bit definition for GPIO_LCKR register *********************/
9536 #define GPIO_LCKR_LCK0_Pos (0U)
9537 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
9538 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
9539 #define GPIO_LCKR_LCK1_Pos (1U)
9540 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
9541 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
9542 #define GPIO_LCKR_LCK2_Pos (2U)
9543 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
9544 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
9545 #define GPIO_LCKR_LCK3_Pos (3U)
9546 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
9547 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
9548 #define GPIO_LCKR_LCK4_Pos (4U)
9549 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
9550 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
9551 #define GPIO_LCKR_LCK5_Pos (5U)
9552 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
9553 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
9554 #define GPIO_LCKR_LCK6_Pos (6U)
9555 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
9556 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
9557 #define GPIO_LCKR_LCK7_Pos (7U)
9558 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
9559 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
9560 #define GPIO_LCKR_LCK8_Pos (8U)
9561 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
9562 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
9563 #define GPIO_LCKR_LCK9_Pos (9U)
9564 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
9565 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
9566 #define GPIO_LCKR_LCK10_Pos (10U)
9567 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
9568 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
9569 #define GPIO_LCKR_LCK11_Pos (11U)
9570 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
9571 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
9572 #define GPIO_LCKR_LCK12_Pos (12U)
9573 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
9574 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
9575 #define GPIO_LCKR_LCK13_Pos (13U)
9576 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
9577 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
9578 #define GPIO_LCKR_LCK14_Pos (14U)
9579 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
9580 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
9581 #define GPIO_LCKR_LCK15_Pos (15U)
9582 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
9583 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
9584 #define GPIO_LCKR_LCKK_Pos (16U)
9585 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
9586 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
9587 /****************** Bit definition for GPIO_AFRL register *********************/
9588 #define GPIO_AFRL_AFSEL0_Pos (0U)
9589 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
9590 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
9591 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
9592 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
9593 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
9594 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
9595 #define GPIO_AFRL_AFSEL1_Pos (4U)
9596 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
9597 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
9598 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
9599 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
9600 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
9601 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
9602 #define GPIO_AFRL_AFSEL2_Pos (8U)
9603 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
9604 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
9605 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
9606 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
9607 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
9608 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
9609 #define GPIO_AFRL_AFSEL3_Pos (12U)
9610 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
9611 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
9612 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
9613 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
9614 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
9615 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
9616 #define GPIO_AFRL_AFSEL4_Pos (16U)
9617 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
9618 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
9619 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
9620 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
9621 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
9622 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
9623 #define GPIO_AFRL_AFSEL5_Pos (20U)
9624 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
9625 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
9626 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
9627 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
9628 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
9629 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
9630 #define GPIO_AFRL_AFSEL6_Pos (24U)
9631 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
9632 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
9633 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
9634 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
9635 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
9636 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
9637 #define GPIO_AFRL_AFSEL7_Pos (28U)
9638 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
9639 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
9640 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
9641 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
9642 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
9643 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
9644
9645 /* Legacy defines */
9646 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
9647 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
9648 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
9649 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
9650 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
9651 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
9652 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
9653 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
9654 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
9655 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
9656 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
9657 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
9658 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
9659 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
9660 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
9661 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
9662 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
9663 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
9664 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
9665 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
9666 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
9667 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
9668 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
9669 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
9670 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
9671 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
9672 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
9673 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
9674 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
9675 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
9676 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
9677 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
9678 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
9679 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
9680 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
9681 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9682 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
9683 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
9684 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
9685 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
9686
9687 /****************** Bit definition for GPIO_AFRH register *********************/
9688 #define GPIO_AFRH_AFSEL8_Pos (0U)
9689 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
9690 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9691 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
9692 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
9693 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
9694 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
9695 #define GPIO_AFRH_AFSEL9_Pos (4U)
9696 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
9697 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9698 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
9699 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
9700 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
9701 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
9702 #define GPIO_AFRH_AFSEL10_Pos (8U)
9703 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
9704 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9705 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
9706 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
9707 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
9708 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
9709 #define GPIO_AFRH_AFSEL11_Pos (12U)
9710 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
9711 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9712 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
9713 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
9714 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
9715 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
9716 #define GPIO_AFRH_AFSEL12_Pos (16U)
9717 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
9718 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9719 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
9720 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
9721 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
9722 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
9723 #define GPIO_AFRH_AFSEL13_Pos (20U)
9724 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
9725 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9726 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
9727 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
9728 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
9729 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
9730 #define GPIO_AFRH_AFSEL14_Pos (24U)
9731 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
9732 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9733 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
9734 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
9735 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
9736 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
9737 #define GPIO_AFRH_AFSEL15_Pos (28U)
9738 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
9739 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9740 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
9741 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
9742 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
9743 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
9744
9745 /* Legacy defines */
9746 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9747 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
9748 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
9749 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
9750 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
9751 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9752 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
9753 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
9754 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
9755 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
9756 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9757 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
9758 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
9759 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
9760 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
9761 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9762 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
9763 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
9764 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
9765 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
9766 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9767 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
9768 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
9769 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
9770 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
9771 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9772 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
9773 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
9774 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
9775 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
9776 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9777 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
9778 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
9779 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
9780 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
9781 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9782 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
9783 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
9784 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
9785 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
9786
9787 /****************** Bits definition for GPIO_BRR register ******************/
9788 #define GPIO_BRR_BR0_Pos (0U)
9789 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
9790 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
9791 #define GPIO_BRR_BR1_Pos (1U)
9792 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
9793 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
9794 #define GPIO_BRR_BR2_Pos (2U)
9795 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
9796 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
9797 #define GPIO_BRR_BR3_Pos (3U)
9798 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
9799 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
9800 #define GPIO_BRR_BR4_Pos (4U)
9801 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
9802 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
9803 #define GPIO_BRR_BR5_Pos (5U)
9804 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
9805 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
9806 #define GPIO_BRR_BR6_Pos (6U)
9807 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
9808 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
9809 #define GPIO_BRR_BR7_Pos (7U)
9810 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
9811 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
9812 #define GPIO_BRR_BR8_Pos (8U)
9813 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
9814 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
9815 #define GPIO_BRR_BR9_Pos (9U)
9816 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
9817 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
9818 #define GPIO_BRR_BR10_Pos (10U)
9819 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
9820 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
9821 #define GPIO_BRR_BR11_Pos (11U)
9822 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
9823 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
9824 #define GPIO_BRR_BR12_Pos (12U)
9825 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
9826 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
9827 #define GPIO_BRR_BR13_Pos (13U)
9828 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
9829 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
9830 #define GPIO_BRR_BR14_Pos (14U)
9831 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
9832 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
9833 #define GPIO_BRR_BR15_Pos (15U)
9834 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
9835 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
9836
9837
9838 /******************************************************************************/
9839 /* */
9840 /* Inter-integrated Circuit Interface */
9841 /* */
9842 /******************************************************************************/
9843 /******************* Bit definition for I2C_CR1 register ********************/
9844 #define I2C_CR1_PE_Pos (0U)
9845 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
9846 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
9847 #define I2C_CR1_SMBUS_Pos (1U)
9848 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
9849 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
9850 #define I2C_CR1_SMBTYPE_Pos (3U)
9851 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
9852 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
9853 #define I2C_CR1_ENARP_Pos (4U)
9854 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
9855 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
9856 #define I2C_CR1_ENPEC_Pos (5U)
9857 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
9858 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
9859 #define I2C_CR1_ENGC_Pos (6U)
9860 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
9861 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
9862 #define I2C_CR1_NOSTRETCH_Pos (7U)
9863 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
9864 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
9865 #define I2C_CR1_START_Pos (8U)
9866 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
9867 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
9868 #define I2C_CR1_STOP_Pos (9U)
9869 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
9870 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
9871 #define I2C_CR1_ACK_Pos (10U)
9872 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
9873 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
9874 #define I2C_CR1_POS_Pos (11U)
9875 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
9876 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
9877 #define I2C_CR1_PEC_Pos (12U)
9878 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
9879 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
9880 #define I2C_CR1_ALERT_Pos (13U)
9881 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
9882 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
9883 #define I2C_CR1_SWRST_Pos (15U)
9884 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
9885 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
9886
9887 /******************* Bit definition for I2C_CR2 register ********************/
9888 #define I2C_CR2_FREQ_Pos (0U)
9889 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
9890 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
9891 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
9892 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
9893 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
9894 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
9895 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
9896 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
9897
9898 #define I2C_CR2_ITERREN_Pos (8U)
9899 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
9900 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
9901 #define I2C_CR2_ITEVTEN_Pos (9U)
9902 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
9903 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
9904 #define I2C_CR2_ITBUFEN_Pos (10U)
9905 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
9906 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
9907 #define I2C_CR2_DMAEN_Pos (11U)
9908 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
9909 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
9910 #define I2C_CR2_LAST_Pos (12U)
9911 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
9912 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
9913
9914 /******************* Bit definition for I2C_OAR1 register *******************/
9915 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
9916 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
9917
9918 #define I2C_OAR1_ADD0_Pos (0U)
9919 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
9920 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
9921 #define I2C_OAR1_ADD1_Pos (1U)
9922 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
9923 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
9924 #define I2C_OAR1_ADD2_Pos (2U)
9925 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
9926 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
9927 #define I2C_OAR1_ADD3_Pos (3U)
9928 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
9929 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
9930 #define I2C_OAR1_ADD4_Pos (4U)
9931 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
9932 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
9933 #define I2C_OAR1_ADD5_Pos (5U)
9934 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
9935 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
9936 #define I2C_OAR1_ADD6_Pos (6U)
9937 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
9938 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
9939 #define I2C_OAR1_ADD7_Pos (7U)
9940 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
9941 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
9942 #define I2C_OAR1_ADD8_Pos (8U)
9943 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
9944 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
9945 #define I2C_OAR1_ADD9_Pos (9U)
9946 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
9947 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
9948
9949 #define I2C_OAR1_ADDMODE_Pos (15U)
9950 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
9951 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
9952
9953 /******************* Bit definition for I2C_OAR2 register *******************/
9954 #define I2C_OAR2_ENDUAL_Pos (0U)
9955 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
9956 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
9957 #define I2C_OAR2_ADD2_Pos (1U)
9958 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
9959 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
9960
9961 /******************** Bit definition for I2C_DR register ********************/
9962 #define I2C_DR_DR_Pos (0U)
9963 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
9964 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
9965
9966 /******************* Bit definition for I2C_SR1 register ********************/
9967 #define I2C_SR1_SB_Pos (0U)
9968 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
9969 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
9970 #define I2C_SR1_ADDR_Pos (1U)
9971 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
9972 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
9973 #define I2C_SR1_BTF_Pos (2U)
9974 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
9975 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
9976 #define I2C_SR1_ADD10_Pos (3U)
9977 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
9978 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
9979 #define I2C_SR1_STOPF_Pos (4U)
9980 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
9981 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
9982 #define I2C_SR1_RXNE_Pos (6U)
9983 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
9984 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
9985 #define I2C_SR1_TXE_Pos (7U)
9986 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
9987 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
9988 #define I2C_SR1_BERR_Pos (8U)
9989 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
9990 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
9991 #define I2C_SR1_ARLO_Pos (9U)
9992 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
9993 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
9994 #define I2C_SR1_AF_Pos (10U)
9995 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
9996 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
9997 #define I2C_SR1_OVR_Pos (11U)
9998 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
9999 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
10000 #define I2C_SR1_PECERR_Pos (12U)
10001 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
10002 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
10003 #define I2C_SR1_TIMEOUT_Pos (14U)
10004 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
10005 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
10006 #define I2C_SR1_SMBALERT_Pos (15U)
10007 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
10008 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
10009
10010 /******************* Bit definition for I2C_SR2 register ********************/
10011 #define I2C_SR2_MSL_Pos (0U)
10012 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
10013 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
10014 #define I2C_SR2_BUSY_Pos (1U)
10015 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
10016 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
10017 #define I2C_SR2_TRA_Pos (2U)
10018 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
10019 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
10020 #define I2C_SR2_GENCALL_Pos (4U)
10021 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
10022 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
10023 #define I2C_SR2_SMBDEFAULT_Pos (5U)
10024 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
10025 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
10026 #define I2C_SR2_SMBHOST_Pos (6U)
10027 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
10028 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
10029 #define I2C_SR2_DUALF_Pos (7U)
10030 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
10031 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
10032 #define I2C_SR2_PEC_Pos (8U)
10033 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
10034 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
10035
10036 /******************* Bit definition for I2C_CCR register ********************/
10037 #define I2C_CCR_CCR_Pos (0U)
10038 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
10039 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
10040 #define I2C_CCR_DUTY_Pos (14U)
10041 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
10042 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
10043 #define I2C_CCR_FS_Pos (15U)
10044 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
10045 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
10046
10047 /****************** Bit definition for I2C_TRISE register *******************/
10048 #define I2C_TRISE_TRISE_Pos (0U)
10049 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
10050 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
10051
10052 /****************** Bit definition for I2C_FLTR register *******************/
10053 #define I2C_FLTR_DNF_Pos (0U)
10054 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
10055 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
10056 #define I2C_FLTR_ANOFF_Pos (4U)
10057 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
10058 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
10059
10060 /******************************************************************************/
10061 /* */
10062 /* Independent WATCHDOG */
10063 /* */
10064 /******************************************************************************/
10065 /******************* Bit definition for IWDG_KR register ********************/
10066 #define IWDG_KR_KEY_Pos (0U)
10067 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
10068 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
10069
10070 /******************* Bit definition for IWDG_PR register ********************/
10071 #define IWDG_PR_PR_Pos (0U)
10072 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
10073 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
10074 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
10075 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
10076 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
10077
10078 /******************* Bit definition for IWDG_RLR register *******************/
10079 #define IWDG_RLR_RL_Pos (0U)
10080 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
10081 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
10082
10083 /******************* Bit definition for IWDG_SR register ********************/
10084 #define IWDG_SR_PVU_Pos (0U)
10085 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
10086 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
10087 #define IWDG_SR_RVU_Pos (1U)
10088 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
10089 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
10090
10091
10092 /******************************************************************************/
10093 /* */
10094 /* LCD-TFT Display Controller (LTDC) */
10095 /* */
10096 /******************************************************************************/
10097
10098 /******************** Bit definition for LTDC_SSCR register *****************/
10099
10100 #define LTDC_SSCR_VSH_Pos (0U)
10101 #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
10102 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
10103 #define LTDC_SSCR_HSW_Pos (16U)
10104 #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
10105 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
10106
10107 /******************** Bit definition for LTDC_BPCR register *****************/
10108
10109 #define LTDC_BPCR_AVBP_Pos (0U)
10110 #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
10111 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
10112 #define LTDC_BPCR_AHBP_Pos (16U)
10113 #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
10114 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
10115
10116 /******************** Bit definition for LTDC_AWCR register *****************/
10117
10118 #define LTDC_AWCR_AAH_Pos (0U)
10119 #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
10120 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
10121 #define LTDC_AWCR_AAW_Pos (16U)
10122 #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
10123 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
10124
10125 /******************** Bit definition for LTDC_TWCR register *****************/
10126
10127 #define LTDC_TWCR_TOTALH_Pos (0U)
10128 #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
10129 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
10130 #define LTDC_TWCR_TOTALW_Pos (16U)
10131 #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
10132 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
10133
10134 /******************** Bit definition for LTDC_GCR register ******************/
10135
10136 #define LTDC_GCR_LTDCEN_Pos (0U)
10137 #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
10138 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
10139 #define LTDC_GCR_DBW_Pos (4U)
10140 #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
10141 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
10142 #define LTDC_GCR_DGW_Pos (8U)
10143 #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
10144 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
10145 #define LTDC_GCR_DRW_Pos (12U)
10146 #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
10147 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
10148 #define LTDC_GCR_DEN_Pos (16U)
10149 #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
10150 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
10151 #define LTDC_GCR_PCPOL_Pos (28U)
10152 #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
10153 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
10154 #define LTDC_GCR_DEPOL_Pos (29U)
10155 #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
10156 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
10157 #define LTDC_GCR_VSPOL_Pos (30U)
10158 #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
10159 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
10160 #define LTDC_GCR_HSPOL_Pos (31U)
10161 #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
10162 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
10163
10164 /* Legacy defines */
10165 #define LTDC_GCR_DTEN LTDC_GCR_DEN
10166
10167 /******************** Bit definition for LTDC_SRCR register *****************/
10168
10169 #define LTDC_SRCR_IMR_Pos (0U)
10170 #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
10171 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
10172 #define LTDC_SRCR_VBR_Pos (1U)
10173 #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
10174 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
10175
10176 /******************** Bit definition for LTDC_BCCR register *****************/
10177
10178 #define LTDC_BCCR_BCBLUE_Pos (0U)
10179 #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
10180 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
10181 #define LTDC_BCCR_BCGREEN_Pos (8U)
10182 #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
10183 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
10184 #define LTDC_BCCR_BCRED_Pos (16U)
10185 #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
10186 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
10187
10188 /******************** Bit definition for LTDC_IER register ******************/
10189
10190 #define LTDC_IER_LIE_Pos (0U)
10191 #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
10192 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
10193 #define LTDC_IER_FUIE_Pos (1U)
10194 #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
10195 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
10196 #define LTDC_IER_TERRIE_Pos (2U)
10197 #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
10198 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
10199 #define LTDC_IER_RRIE_Pos (3U)
10200 #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
10201 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
10202
10203 /******************** Bit definition for LTDC_ISR register ******************/
10204
10205 #define LTDC_ISR_LIF_Pos (0U)
10206 #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
10207 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
10208 #define LTDC_ISR_FUIF_Pos (1U)
10209 #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
10210 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
10211 #define LTDC_ISR_TERRIF_Pos (2U)
10212 #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
10213 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
10214 #define LTDC_ISR_RRIF_Pos (3U)
10215 #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
10216 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
10217
10218 /******************** Bit definition for LTDC_ICR register ******************/
10219
10220 #define LTDC_ICR_CLIF_Pos (0U)
10221 #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
10222 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
10223 #define LTDC_ICR_CFUIF_Pos (1U)
10224 #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
10225 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
10226 #define LTDC_ICR_CTERRIF_Pos (2U)
10227 #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
10228 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
10229 #define LTDC_ICR_CRRIF_Pos (3U)
10230 #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
10231 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
10232
10233 /******************** Bit definition for LTDC_LIPCR register ****************/
10234
10235 #define LTDC_LIPCR_LIPOS_Pos (0U)
10236 #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
10237 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
10238
10239 /******************** Bit definition for LTDC_CPSR register *****************/
10240
10241 #define LTDC_CPSR_CYPOS_Pos (0U)
10242 #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
10243 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
10244 #define LTDC_CPSR_CXPOS_Pos (16U)
10245 #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
10246 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
10247
10248 /******************** Bit definition for LTDC_CDSR register *****************/
10249
10250 #define LTDC_CDSR_VDES_Pos (0U)
10251 #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
10252 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
10253 #define LTDC_CDSR_HDES_Pos (1U)
10254 #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
10255 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
10256 #define LTDC_CDSR_VSYNCS_Pos (2U)
10257 #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
10258 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
10259 #define LTDC_CDSR_HSYNCS_Pos (3U)
10260 #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
10261 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
10262
10263 /******************** Bit definition for LTDC_LxCR register *****************/
10264
10265 #define LTDC_LxCR_LEN_Pos (0U)
10266 #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
10267 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
10268 #define LTDC_LxCR_COLKEN_Pos (1U)
10269 #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
10270 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
10271 #define LTDC_LxCR_CLUTEN_Pos (4U)
10272 #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
10273 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
10274
10275 /******************** Bit definition for LTDC_LxWHPCR register **************/
10276
10277 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
10278 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
10279 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
10280 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
10281 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
10282 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
10283
10284 /******************** Bit definition for LTDC_LxWVPCR register **************/
10285
10286 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
10287 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
10288 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
10289 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
10290 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
10291 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
10292
10293 /******************** Bit definition for LTDC_LxCKCR register ***************/
10294
10295 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
10296 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
10297 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
10298 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
10299 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
10300 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
10301 #define LTDC_LxCKCR_CKRED_Pos (16U)
10302 #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
10303 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
10304
10305 /******************** Bit definition for LTDC_LxPFCR register ***************/
10306
10307 #define LTDC_LxPFCR_PF_Pos (0U)
10308 #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
10309 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
10310
10311 /******************** Bit definition for LTDC_LxCACR register ***************/
10312
10313 #define LTDC_LxCACR_CONSTA_Pos (0U)
10314 #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
10315 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
10316
10317 /******************** Bit definition for LTDC_LxDCCR register ***************/
10318
10319 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
10320 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
10321 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
10322 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
10323 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
10324 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
10325 #define LTDC_LxDCCR_DCRED_Pos (16U)
10326 #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
10327 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
10328 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
10329 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
10330 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
10331
10332 /******************** Bit definition for LTDC_LxBFCR register ***************/
10333
10334 #define LTDC_LxBFCR_BF2_Pos (0U)
10335 #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
10336 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
10337 #define LTDC_LxBFCR_BF1_Pos (8U)
10338 #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
10339 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
10340
10341 /******************** Bit definition for LTDC_LxCFBAR register **************/
10342
10343 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
10344 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
10345 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
10346
10347 /******************** Bit definition for LTDC_LxCFBLR register **************/
10348
10349 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
10350 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
10351 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
10352 #define LTDC_LxCFBLR_CFBP_Pos (16U)
10353 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
10354 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
10355
10356 /******************** Bit definition for LTDC_LxCFBLNR register *************/
10357
10358 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
10359 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
10360 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
10361
10362 /******************** Bit definition for LTDC_LxCLUTWR register *************/
10363
10364 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
10365 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
10366 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
10367 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
10368 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
10369 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
10370 #define LTDC_LxCLUTWR_RED_Pos (16U)
10371 #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
10372 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
10373 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
10374 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
10375 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
10376
10377
10378 /******************************************************************************/
10379 /* */
10380 /* Power Control */
10381 /* */
10382 /******************************************************************************/
10383 /******************** Bit definition for PWR_CR register ********************/
10384 #define PWR_CR_LPDS_Pos (0U)
10385 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
10386 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
10387 #define PWR_CR_PDDS_Pos (1U)
10388 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
10389 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
10390 #define PWR_CR_CWUF_Pos (2U)
10391 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
10392 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
10393 #define PWR_CR_CSBF_Pos (3U)
10394 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
10395 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
10396 #define PWR_CR_PVDE_Pos (4U)
10397 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
10398 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
10399
10400 #define PWR_CR_PLS_Pos (5U)
10401 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
10402 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
10403 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
10404 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
10405 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
10406
10407 /*!< PVD level configuration */
10408 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
10409 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
10410 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
10411 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
10412 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
10413 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
10414 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
10415 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
10416 #define PWR_CR_DBP_Pos (8U)
10417 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
10418 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
10419 #define PWR_CR_FPDS_Pos (9U)
10420 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
10421 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
10422 #define PWR_CR_LPLVDS_Pos (10U)
10423 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
10424 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
10425 #define PWR_CR_MRLVDS_Pos (11U)
10426 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
10427 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
10428 #define PWR_CR_ADCDC1_Pos (13U)
10429 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
10430 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
10431 #define PWR_CR_VOS_Pos (14U)
10432 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
10433 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10434 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
10435 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
10436 #define PWR_CR_ODEN_Pos (16U)
10437 #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
10438 #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
10439 #define PWR_CR_ODSWEN_Pos (17U)
10440 #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
10441 #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
10442 #define PWR_CR_UDEN_Pos (18U)
10443 #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
10444 #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
10445 #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
10446 #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
10447
10448 /* Legacy define */
10449 #define PWR_CR_PMODE PWR_CR_VOS
10450 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
10451 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
10452
10453 /******************* Bit definition for PWR_CSR register ********************/
10454 #define PWR_CSR_WUF_Pos (0U)
10455 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
10456 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
10457 #define PWR_CSR_SBF_Pos (1U)
10458 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
10459 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
10460 #define PWR_CSR_PVDO_Pos (2U)
10461 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
10462 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
10463 #define PWR_CSR_BRR_Pos (3U)
10464 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
10465 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
10466 #define PWR_CSR_EWUP_Pos (8U)
10467 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
10468 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
10469 #define PWR_CSR_BRE_Pos (9U)
10470 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
10471 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
10472 #define PWR_CSR_VOSRDY_Pos (14U)
10473 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
10474 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
10475 #define PWR_CSR_ODRDY_Pos (16U)
10476 #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
10477 #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
10478 #define PWR_CSR_ODSWRDY_Pos (17U)
10479 #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
10480 #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
10481 #define PWR_CSR_UDRDY_Pos (18U)
10482 #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
10483 #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
10484 /* Legacy define */
10485 #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
10486
10487 /* Legacy define */
10488 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
10489
10490 /******************************************************************************/
10491 /* */
10492 /* Reset and Clock Control */
10493 /* */
10494 /******************************************************************************/
10495 /******************** Bit definition for RCC_CR register ********************/
10496 #define RCC_CR_HSION_Pos (0U)
10497 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
10498 #define RCC_CR_HSION RCC_CR_HSION_Msk
10499 #define RCC_CR_HSIRDY_Pos (1U)
10500 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
10501 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10502
10503 #define RCC_CR_HSITRIM_Pos (3U)
10504 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
10505 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10506 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
10507 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
10508 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
10509 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
10510 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
10511
10512 #define RCC_CR_HSICAL_Pos (8U)
10513 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
10514 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10515 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
10516 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
10517 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
10518 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
10519 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
10520 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
10521 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
10522 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
10523
10524 #define RCC_CR_HSEON_Pos (16U)
10525 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
10526 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
10527 #define RCC_CR_HSERDY_Pos (17U)
10528 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
10529 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10530 #define RCC_CR_HSEBYP_Pos (18U)
10531 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
10532 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10533 #define RCC_CR_CSSON_Pos (19U)
10534 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
10535 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
10536 #define RCC_CR_PLLON_Pos (24U)
10537 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
10538 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
10539 #define RCC_CR_PLLRDY_Pos (25U)
10540 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
10541 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10542 /*
10543 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10544 */
10545 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
10546
10547 #define RCC_CR_PLLI2SON_Pos (26U)
10548 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
10549 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
10550 #define RCC_CR_PLLI2SRDY_Pos (27U)
10551 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
10552 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
10553 /*
10554 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10555 */
10556 #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
10557
10558 #define RCC_CR_PLLSAION_Pos (28U)
10559 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
10560 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
10561 #define RCC_CR_PLLSAIRDY_Pos (29U)
10562 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
10563 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
10564
10565 /******************** Bit definition for RCC_PLLCFGR register ***************/
10566 #define RCC_PLLCFGR_PLLM_Pos (0U)
10567 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
10568 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10569 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
10570 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
10571 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
10572 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
10573 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
10574 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
10575
10576 #define RCC_PLLCFGR_PLLN_Pos (6U)
10577 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
10578 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10579 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
10580 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
10581 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
10582 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
10583 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
10584 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
10585 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
10586 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
10587 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
10588
10589 #define RCC_PLLCFGR_PLLP_Pos (16U)
10590 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
10591 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10592 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
10593 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
10594
10595 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
10596 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
10597 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10598 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
10599 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
10600 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10601 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
10602
10603 #define RCC_PLLCFGR_PLLQ_Pos (24U)
10604 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
10605 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10606 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
10607 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
10608 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
10609 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
10610
10611
10612 /******************** Bit definition for RCC_CFGR register ******************/
10613 /*!< SW configuration */
10614 #define RCC_CFGR_SW_Pos (0U)
10615 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
10616 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
10617 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
10618 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
10619
10620 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
10621 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
10622 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
10623
10624 /*!< SWS configuration */
10625 #define RCC_CFGR_SWS_Pos (2U)
10626 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
10627 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
10628 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
10629 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
10630
10631 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
10632 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
10633 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
10634
10635 /*!< HPRE configuration */
10636 #define RCC_CFGR_HPRE_Pos (4U)
10637 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
10638 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
10639 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
10640 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
10641 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
10642 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
10643
10644 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
10645 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
10646 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
10647 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
10648 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
10649 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
10650 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
10651 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
10652 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
10653
10654 /*!< PPRE1 configuration */
10655 #define RCC_CFGR_PPRE1_Pos (10U)
10656 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
10657 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
10658 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
10659 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
10660 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
10661
10662 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
10663 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
10664 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
10665 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
10666 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
10667
10668 /*!< PPRE2 configuration */
10669 #define RCC_CFGR_PPRE2_Pos (13U)
10670 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
10671 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
10672 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
10673 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
10674 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
10675
10676 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
10677 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
10678 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
10679 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
10680 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
10681
10682 /*!< RTCPRE configuration */
10683 #define RCC_CFGR_RTCPRE_Pos (16U)
10684 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
10685 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
10686 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
10687 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
10688 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
10689 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
10690 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
10691
10692 /*!< MCO1 configuration */
10693 #define RCC_CFGR_MCO1_Pos (21U)
10694 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
10695 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
10696 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
10697 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
10698
10699 #define RCC_CFGR_I2SSRC_Pos (23U)
10700 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
10701 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
10702
10703 #define RCC_CFGR_MCO1PRE_Pos (24U)
10704 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
10705 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
10706 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
10707 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
10708 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
10709
10710 #define RCC_CFGR_MCO2PRE_Pos (27U)
10711 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
10712 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
10713 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
10714 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
10715 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
10716
10717 #define RCC_CFGR_MCO2_Pos (30U)
10718 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
10719 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
10720 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
10721 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
10722
10723 /******************** Bit definition for RCC_CIR register *******************/
10724 #define RCC_CIR_LSIRDYF_Pos (0U)
10725 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
10726 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
10727 #define RCC_CIR_LSERDYF_Pos (1U)
10728 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
10729 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
10730 #define RCC_CIR_HSIRDYF_Pos (2U)
10731 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
10732 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
10733 #define RCC_CIR_HSERDYF_Pos (3U)
10734 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
10735 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
10736 #define RCC_CIR_PLLRDYF_Pos (4U)
10737 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
10738 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
10739 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
10740 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
10741 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
10742
10743 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
10744 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
10745 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
10746 #define RCC_CIR_CSSF_Pos (7U)
10747 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
10748 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
10749 #define RCC_CIR_LSIRDYIE_Pos (8U)
10750 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
10751 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
10752 #define RCC_CIR_LSERDYIE_Pos (9U)
10753 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
10754 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
10755 #define RCC_CIR_HSIRDYIE_Pos (10U)
10756 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
10757 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
10758 #define RCC_CIR_HSERDYIE_Pos (11U)
10759 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
10760 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
10761 #define RCC_CIR_PLLRDYIE_Pos (12U)
10762 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
10763 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
10764 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
10765 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
10766 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
10767
10768 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
10769 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
10770 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
10771 #define RCC_CIR_LSIRDYC_Pos (16U)
10772 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
10773 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
10774 #define RCC_CIR_LSERDYC_Pos (17U)
10775 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
10776 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
10777 #define RCC_CIR_HSIRDYC_Pos (18U)
10778 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
10779 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
10780 #define RCC_CIR_HSERDYC_Pos (19U)
10781 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
10782 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
10783 #define RCC_CIR_PLLRDYC_Pos (20U)
10784 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
10785 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
10786 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
10787 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
10788 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
10789 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
10790 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
10791 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
10792
10793 #define RCC_CIR_CSSC_Pos (23U)
10794 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
10795 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
10796
10797 /******************** Bit definition for RCC_AHB1RSTR register **************/
10798 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
10799 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
10800 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
10801 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
10802 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
10803 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
10804 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
10805 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
10806 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
10807 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
10808 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
10809 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
10810 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
10811 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
10812 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
10813 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
10814 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
10815 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
10816 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
10817 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
10818 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
10819 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
10820 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
10821 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
10822 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
10823 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
10824 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
10825 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
10826 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
10827 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
10828 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
10829 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
10830 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
10831 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
10832 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
10833 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10834 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
10835 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
10836 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10837 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
10838 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
10839 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10840 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
10841 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
10842 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
10843 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
10844 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
10845 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
10846 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
10847 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
10848 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
10849
10850 /******************** Bit definition for RCC_AHB2RSTR register **************/
10851 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
10852 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
10853 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
10854 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
10855 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
10856 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
10857 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
10858 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
10859 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
10860 /******************** Bit definition for RCC_AHB3RSTR register **************/
10861 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
10862 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
10863 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
10864
10865
10866 /******************** Bit definition for RCC_APB1RSTR register **************/
10867 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
10868 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
10869 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
10870 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
10871 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
10872 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
10873 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
10874 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
10875 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
10876 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
10877 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
10878 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
10879 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
10880 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
10881 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
10882 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
10883 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
10884 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
10885 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
10886 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
10887 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
10888 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
10889 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
10890 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
10891 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
10892 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
10893 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
10894 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
10895 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
10896 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
10897 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
10898 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
10899 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
10900 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
10901 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
10902 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
10903 #define RCC_APB1RSTR_USART2RST_Pos (17U)
10904 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
10905 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
10906 #define RCC_APB1RSTR_USART3RST_Pos (18U)
10907 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
10908 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
10909 #define RCC_APB1RSTR_UART4RST_Pos (19U)
10910 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
10911 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
10912 #define RCC_APB1RSTR_UART5RST_Pos (20U)
10913 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
10914 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
10915 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
10916 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
10917 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
10918 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
10919 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
10920 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
10921 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
10922 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
10923 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
10924 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
10925 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
10926 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
10927 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
10928 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
10929 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
10930 #define RCC_APB1RSTR_PWRRST_Pos (28U)
10931 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
10932 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
10933 #define RCC_APB1RSTR_DACRST_Pos (29U)
10934 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
10935 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
10936 #define RCC_APB1RSTR_UART7RST_Pos (30U)
10937 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
10938 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
10939 #define RCC_APB1RSTR_UART8RST_Pos (31U)
10940 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
10941 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
10942
10943 /******************** Bit definition for RCC_APB2RSTR register **************/
10944 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
10945 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
10946 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10947 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
10948 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
10949 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
10950 #define RCC_APB2RSTR_USART1RST_Pos (4U)
10951 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
10952 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10953 #define RCC_APB2RSTR_USART6RST_Pos (5U)
10954 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
10955 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
10956 #define RCC_APB2RSTR_ADCRST_Pos (8U)
10957 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
10958 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
10959 #define RCC_APB2RSTR_SDIORST_Pos (11U)
10960 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
10961 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
10962 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
10963 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
10964 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10965 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
10966 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
10967 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
10968 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
10969 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
10970 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10971 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
10972 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
10973 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
10974 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
10975 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
10976 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
10977 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
10978 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
10979 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
10980 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
10981 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
10982 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
10983 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
10984 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
10985 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
10986 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
10987 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
10988 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
10989 #define RCC_APB2RSTR_LTDCRST_Pos (26U)
10990 #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
10991 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
10992
10993 /* Old SPI1RST bit definition, maintained for legacy purpose */
10994 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
10995
10996 /******************** Bit definition for RCC_AHB1ENR register ***************/
10997 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
10998 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
10999 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
11000 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
11001 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
11002 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
11003 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
11004 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
11005 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
11006 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
11007 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
11008 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
11009 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
11010 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
11011 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
11012 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
11013 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
11014 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
11015 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
11016 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
11017 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
11018 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
11019 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
11020 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
11021 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
11022 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
11023 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
11024 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
11025 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
11026 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
11027 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
11028 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
11029 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
11030 #define RCC_AHB1ENR_CRCEN_Pos (12U)
11031 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
11032 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
11033 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
11034 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
11035 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
11036 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
11037 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
11038 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
11039 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
11040 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
11041 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
11042 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
11043 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
11044 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
11045 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
11046 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
11047 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
11048 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
11049 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
11050 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
11051 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
11052 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
11053 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
11054 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
11055 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
11056 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
11057 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
11058 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
11059 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
11060 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
11061 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
11062 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
11063 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
11064 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
11065 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
11066 /******************** Bit definition for RCC_AHB2ENR register ***************/
11067 /*
11068 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11069 */
11070 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
11071
11072 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
11073 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
11074 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
11075 #define RCC_AHB2ENR_RNGEN_Pos (6U)
11076 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
11077 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11078 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
11079 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
11080 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11081
11082 /******************** Bit definition for RCC_AHB3ENR register ***************/
11083 /*
11084 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11085 */
11086 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
11087
11088 #define RCC_AHB3ENR_FMCEN_Pos (0U)
11089 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
11090 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11091
11092 /******************** Bit definition for RCC_APB1ENR register ***************/
11093 #define RCC_APB1ENR_TIM2EN_Pos (0U)
11094 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
11095 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
11096 #define RCC_APB1ENR_TIM3EN_Pos (1U)
11097 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
11098 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
11099 #define RCC_APB1ENR_TIM4EN_Pos (2U)
11100 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
11101 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
11102 #define RCC_APB1ENR_TIM5EN_Pos (3U)
11103 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
11104 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
11105 #define RCC_APB1ENR_TIM6EN_Pos (4U)
11106 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
11107 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
11108 #define RCC_APB1ENR_TIM7EN_Pos (5U)
11109 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
11110 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
11111 #define RCC_APB1ENR_TIM12EN_Pos (6U)
11112 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
11113 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
11114 #define RCC_APB1ENR_TIM13EN_Pos (7U)
11115 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
11116 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
11117 #define RCC_APB1ENR_TIM14EN_Pos (8U)
11118 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
11119 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
11120 #define RCC_APB1ENR_WWDGEN_Pos (11U)
11121 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
11122 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
11123 #define RCC_APB1ENR_SPI2EN_Pos (14U)
11124 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
11125 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
11126 #define RCC_APB1ENR_SPI3EN_Pos (15U)
11127 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
11128 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
11129 #define RCC_APB1ENR_USART2EN_Pos (17U)
11130 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
11131 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
11132 #define RCC_APB1ENR_USART3EN_Pos (18U)
11133 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
11134 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
11135 #define RCC_APB1ENR_UART4EN_Pos (19U)
11136 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
11137 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
11138 #define RCC_APB1ENR_UART5EN_Pos (20U)
11139 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
11140 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
11141 #define RCC_APB1ENR_I2C1EN_Pos (21U)
11142 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
11143 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
11144 #define RCC_APB1ENR_I2C2EN_Pos (22U)
11145 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
11146 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
11147 #define RCC_APB1ENR_I2C3EN_Pos (23U)
11148 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
11149 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
11150 #define RCC_APB1ENR_CAN1EN_Pos (25U)
11151 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
11152 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
11153 #define RCC_APB1ENR_CAN2EN_Pos (26U)
11154 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
11155 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
11156 #define RCC_APB1ENR_PWREN_Pos (28U)
11157 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
11158 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
11159 #define RCC_APB1ENR_DACEN_Pos (29U)
11160 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
11161 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
11162 #define RCC_APB1ENR_UART7EN_Pos (30U)
11163 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
11164 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
11165 #define RCC_APB1ENR_UART8EN_Pos (31U)
11166 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
11167 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
11168
11169 /******************** Bit definition for RCC_APB2ENR register ***************/
11170 #define RCC_APB2ENR_TIM1EN_Pos (0U)
11171 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
11172 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11173 #define RCC_APB2ENR_TIM8EN_Pos (1U)
11174 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
11175 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11176 #define RCC_APB2ENR_USART1EN_Pos (4U)
11177 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
11178 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11179 #define RCC_APB2ENR_USART6EN_Pos (5U)
11180 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
11181 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
11182 #define RCC_APB2ENR_ADC1EN_Pos (8U)
11183 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
11184 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
11185 #define RCC_APB2ENR_ADC2EN_Pos (9U)
11186 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
11187 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
11188 #define RCC_APB2ENR_ADC3EN_Pos (10U)
11189 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
11190 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
11191 #define RCC_APB2ENR_SDIOEN_Pos (11U)
11192 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
11193 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
11194 #define RCC_APB2ENR_SPI1EN_Pos (12U)
11195 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
11196 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11197 #define RCC_APB2ENR_SPI4EN_Pos (13U)
11198 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
11199 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
11200 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
11201 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
11202 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11203 #define RCC_APB2ENR_TIM9EN_Pos (16U)
11204 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
11205 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
11206 #define RCC_APB2ENR_TIM10EN_Pos (17U)
11207 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
11208 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
11209 #define RCC_APB2ENR_TIM11EN_Pos (18U)
11210 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
11211 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
11212 #define RCC_APB2ENR_SPI5EN_Pos (20U)
11213 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
11214 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
11215 #define RCC_APB2ENR_SPI6EN_Pos (21U)
11216 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
11217 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
11218 #define RCC_APB2ENR_SAI1EN_Pos (22U)
11219 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
11220 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11221 #define RCC_APB2ENR_LTDCEN_Pos (26U)
11222 #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
11223 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
11224
11225 /******************** Bit definition for RCC_AHB1LPENR register *************/
11226 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
11227 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
11228 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
11229 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
11230 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
11231 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
11232 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
11233 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
11234 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
11235 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
11236 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
11237 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
11238 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
11239 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
11240 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
11241 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
11242 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
11243 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
11244 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
11245 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
11246 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
11247 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
11248 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
11249 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
11250 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
11251 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
11252 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
11253 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
11254 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
11255 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
11256 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
11257 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
11258 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
11259 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
11260 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
11261 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
11262 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
11263 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
11264 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
11265 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
11266 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
11267 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
11268 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
11269 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
11270 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
11271 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
11272 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
11273 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
11274 #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
11275 #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
11276 #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
11277 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
11278 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
11279 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
11280 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
11281 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
11282 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
11283 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
11284 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
11285 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
11286
11287 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
11288 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
11289 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
11290 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
11291 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
11292 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
11293 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
11294 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
11295 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
11296 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
11297 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
11298 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
11299 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
11300 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
11301 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
11302 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
11303 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
11304 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
11305
11306 /******************** Bit definition for RCC_AHB2LPENR register *************/
11307 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
11308 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
11309 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
11310 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
11311 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
11312 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
11313 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
11314 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
11315 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
11316
11317 /******************** Bit definition for RCC_AHB3LPENR register *************/
11318 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
11319 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
11320 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
11321
11322 /******************** Bit definition for RCC_APB1LPENR register *************/
11323 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
11324 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
11325 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
11326 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
11327 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
11328 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
11329 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
11330 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
11331 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
11332 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
11333 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
11334 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
11335 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
11336 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
11337 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
11338 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
11339 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
11340 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
11341 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
11342 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
11343 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
11344 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
11345 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
11346 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
11347 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
11348 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
11349 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
11350 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
11351 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
11352 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
11353 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
11354 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
11355 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
11356 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
11357 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
11358 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
11359 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
11360 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
11361 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
11362 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
11363 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
11364 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
11365 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
11366 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
11367 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
11368 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
11369 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
11370 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
11371 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
11372 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
11373 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
11374 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
11375 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
11376 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
11377 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
11378 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
11379 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
11380 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
11381 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
11382 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
11383 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
11384 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
11385 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
11386 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
11387 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
11388 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
11389 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
11390 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
11391 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
11392 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
11393 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
11394 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
11395 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
11396 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
11397 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
11398
11399 /******************** Bit definition for RCC_APB2LPENR register *************/
11400 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
11401 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
11402 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
11403 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
11404 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
11405 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
11406 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
11407 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
11408 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
11409 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
11410 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
11411 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
11412 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
11413 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
11414 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
11415 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
11416 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
11417 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
11418 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
11419 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
11420 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
11421 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
11422 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
11423 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
11424 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
11425 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
11426 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
11427 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
11428 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
11429 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
11430 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
11431 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
11432 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
11433 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
11434 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
11435 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
11436 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
11437 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
11438 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
11439 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
11440 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
11441 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
11442 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
11443 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
11444 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
11445 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
11446 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
11447 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
11448 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
11449 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
11450 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
11451 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
11452 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
11453 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
11454
11455 /******************** Bit definition for RCC_BDCR register ******************/
11456 #define RCC_BDCR_LSEON_Pos (0U)
11457 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
11458 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11459 #define RCC_BDCR_LSERDY_Pos (1U)
11460 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
11461 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11462 #define RCC_BDCR_LSEBYP_Pos (2U)
11463 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
11464 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11465
11466 #define RCC_BDCR_RTCSEL_Pos (8U)
11467 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
11468 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11469 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
11470 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
11471
11472 #define RCC_BDCR_RTCEN_Pos (15U)
11473 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
11474 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11475 #define RCC_BDCR_BDRST_Pos (16U)
11476 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
11477 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11478
11479 /******************** Bit definition for RCC_CSR register *******************/
11480 #define RCC_CSR_LSION_Pos (0U)
11481 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
11482 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
11483 #define RCC_CSR_LSIRDY_Pos (1U)
11484 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
11485 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11486 #define RCC_CSR_RMVF_Pos (24U)
11487 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
11488 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11489 #define RCC_CSR_BORRSTF_Pos (25U)
11490 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
11491 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11492 #define RCC_CSR_PINRSTF_Pos (26U)
11493 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
11494 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11495 #define RCC_CSR_PORRSTF_Pos (27U)
11496 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
11497 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
11498 #define RCC_CSR_SFTRSTF_Pos (28U)
11499 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
11500 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11501 #define RCC_CSR_IWDGRSTF_Pos (29U)
11502 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
11503 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11504 #define RCC_CSR_WWDGRSTF_Pos (30U)
11505 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
11506 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11507 #define RCC_CSR_LPWRRSTF_Pos (31U)
11508 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
11509 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11510 /* Legacy defines */
11511 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
11512 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
11513
11514 /******************** Bit definition for RCC_SSCGR register *****************/
11515 #define RCC_SSCGR_MODPER_Pos (0U)
11516 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
11517 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
11518 #define RCC_SSCGR_INCSTEP_Pos (13U)
11519 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
11520 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
11521 #define RCC_SSCGR_SPREADSEL_Pos (30U)
11522 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
11523 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
11524 #define RCC_SSCGR_SSCGEN_Pos (31U)
11525 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
11526 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
11527
11528 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
11529 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
11530 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
11531 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
11532 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
11533 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
11534 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
11535 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
11536 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
11537 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
11538 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
11539 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
11540 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
11541
11542 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
11543 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
11544 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
11545 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
11546 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
11547 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
11548 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
11549 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
11550 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
11551 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
11552 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
11553 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
11554 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
11555
11556 /******************** Bit definition for RCC_PLLSAICFGR register ************/
11557 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
11558 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
11559 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
11560 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
11561 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
11562 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
11563 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
11564 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
11565 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
11566 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
11567 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
11568 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
11569
11570
11571 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
11572 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
11573 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
11574 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
11575 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
11576 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
11577 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
11578
11579 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
11580 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
11581 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
11582 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
11583 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
11584 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
11585
11586 /******************** Bit definition for RCC_DCKCFGR register ***************/
11587 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
11588 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
11589 #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
11590 #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
11591 #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
11592 #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
11593 #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
11594 #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
11595
11596 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
11597 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
11598 #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
11599 #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
11600 #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
11601 #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
11602 #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
11603 #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
11604 #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
11605 #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11606 #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
11607 #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11608 #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
11609
11610 #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
11611 #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
11612 #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
11613 #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
11614 #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
11615 #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
11616 #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
11617 #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
11618 #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
11619 #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
11620 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
11621 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
11622 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
11623
11624
11625 /******************************************************************************/
11626 /* */
11627 /* RNG */
11628 /* */
11629 /******************************************************************************/
11630 /******************** Bits definition for RNG_CR register *******************/
11631 #define RNG_CR_RNGEN_Pos (2U)
11632 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
11633 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11634 #define RNG_CR_IE_Pos (3U)
11635 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
11636 #define RNG_CR_IE RNG_CR_IE_Msk
11637
11638 /******************** Bits definition for RNG_SR register *******************/
11639 #define RNG_SR_DRDY_Pos (0U)
11640 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
11641 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
11642 #define RNG_SR_CECS_Pos (1U)
11643 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
11644 #define RNG_SR_CECS RNG_SR_CECS_Msk
11645 #define RNG_SR_SECS_Pos (2U)
11646 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
11647 #define RNG_SR_SECS RNG_SR_SECS_Msk
11648 #define RNG_SR_CEIS_Pos (5U)
11649 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
11650 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
11651 #define RNG_SR_SEIS_Pos (6U)
11652 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
11653 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
11654
11655 /******************************************************************************/
11656 /* */
11657 /* Real-Time Clock (RTC) */
11658 /* */
11659 /******************************************************************************/
11660 /*
11661 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11662 */
11663 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
11664 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
11665 /******************** Bits definition for RTC_TR register *******************/
11666 #define RTC_TR_PM_Pos (22U)
11667 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
11668 #define RTC_TR_PM RTC_TR_PM_Msk
11669 #define RTC_TR_HT_Pos (20U)
11670 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
11671 #define RTC_TR_HT RTC_TR_HT_Msk
11672 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
11673 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
11674 #define RTC_TR_HU_Pos (16U)
11675 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
11676 #define RTC_TR_HU RTC_TR_HU_Msk
11677 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
11678 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
11679 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
11680 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
11681 #define RTC_TR_MNT_Pos (12U)
11682 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
11683 #define RTC_TR_MNT RTC_TR_MNT_Msk
11684 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
11685 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
11686 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
11687 #define RTC_TR_MNU_Pos (8U)
11688 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
11689 #define RTC_TR_MNU RTC_TR_MNU_Msk
11690 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
11691 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
11692 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
11693 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
11694 #define RTC_TR_ST_Pos (4U)
11695 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
11696 #define RTC_TR_ST RTC_TR_ST_Msk
11697 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
11698 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
11699 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
11700 #define RTC_TR_SU_Pos (0U)
11701 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
11702 #define RTC_TR_SU RTC_TR_SU_Msk
11703 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
11704 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
11705 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
11706 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
11707
11708 /******************** Bits definition for RTC_DR register *******************/
11709 #define RTC_DR_YT_Pos (20U)
11710 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
11711 #define RTC_DR_YT RTC_DR_YT_Msk
11712 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
11713 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
11714 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
11715 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
11716 #define RTC_DR_YU_Pos (16U)
11717 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
11718 #define RTC_DR_YU RTC_DR_YU_Msk
11719 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
11720 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
11721 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
11722 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
11723 #define RTC_DR_WDU_Pos (13U)
11724 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
11725 #define RTC_DR_WDU RTC_DR_WDU_Msk
11726 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
11727 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
11728 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
11729 #define RTC_DR_MT_Pos (12U)
11730 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
11731 #define RTC_DR_MT RTC_DR_MT_Msk
11732 #define RTC_DR_MU_Pos (8U)
11733 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
11734 #define RTC_DR_MU RTC_DR_MU_Msk
11735 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
11736 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
11737 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
11738 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
11739 #define RTC_DR_DT_Pos (4U)
11740 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
11741 #define RTC_DR_DT RTC_DR_DT_Msk
11742 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
11743 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
11744 #define RTC_DR_DU_Pos (0U)
11745 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
11746 #define RTC_DR_DU RTC_DR_DU_Msk
11747 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
11748 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
11749 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
11750 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
11751
11752 /******************** Bits definition for RTC_CR register *******************/
11753 #define RTC_CR_COE_Pos (23U)
11754 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
11755 #define RTC_CR_COE RTC_CR_COE_Msk
11756 #define RTC_CR_OSEL_Pos (21U)
11757 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
11758 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
11759 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
11760 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
11761 #define RTC_CR_POL_Pos (20U)
11762 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
11763 #define RTC_CR_POL RTC_CR_POL_Msk
11764 #define RTC_CR_COSEL_Pos (19U)
11765 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
11766 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
11767 #define RTC_CR_BKP_Pos (18U)
11768 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
11769 #define RTC_CR_BKP RTC_CR_BKP_Msk
11770 #define RTC_CR_SUB1H_Pos (17U)
11771 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
11772 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11773 #define RTC_CR_ADD1H_Pos (16U)
11774 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
11775 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11776 #define RTC_CR_TSIE_Pos (15U)
11777 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
11778 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
11779 #define RTC_CR_WUTIE_Pos (14U)
11780 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
11781 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11782 #define RTC_CR_ALRBIE_Pos (13U)
11783 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
11784 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11785 #define RTC_CR_ALRAIE_Pos (12U)
11786 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
11787 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11788 #define RTC_CR_TSE_Pos (11U)
11789 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
11790 #define RTC_CR_TSE RTC_CR_TSE_Msk
11791 #define RTC_CR_WUTE_Pos (10U)
11792 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
11793 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
11794 #define RTC_CR_ALRBE_Pos (9U)
11795 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
11796 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11797 #define RTC_CR_ALRAE_Pos (8U)
11798 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
11799 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11800 #define RTC_CR_DCE_Pos (7U)
11801 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
11802 #define RTC_CR_DCE RTC_CR_DCE_Msk
11803 #define RTC_CR_FMT_Pos (6U)
11804 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
11805 #define RTC_CR_FMT RTC_CR_FMT_Msk
11806 #define RTC_CR_BYPSHAD_Pos (5U)
11807 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
11808 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11809 #define RTC_CR_REFCKON_Pos (4U)
11810 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
11811 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11812 #define RTC_CR_TSEDGE_Pos (3U)
11813 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
11814 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11815 #define RTC_CR_WUCKSEL_Pos (0U)
11816 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
11817 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11818 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
11819 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
11820 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
11821
11822 /* Legacy defines */
11823 #define RTC_CR_BCK RTC_CR_BKP
11824
11825 /******************** Bits definition for RTC_ISR register ******************/
11826 #define RTC_ISR_RECALPF_Pos (16U)
11827 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
11828 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11829 #define RTC_ISR_TAMP1F_Pos (13U)
11830 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
11831 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11832 #define RTC_ISR_TAMP2F_Pos (14U)
11833 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
11834 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11835 #define RTC_ISR_TSOVF_Pos (12U)
11836 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
11837 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11838 #define RTC_ISR_TSF_Pos (11U)
11839 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
11840 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
11841 #define RTC_ISR_WUTF_Pos (10U)
11842 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
11843 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11844 #define RTC_ISR_ALRBF_Pos (9U)
11845 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
11846 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11847 #define RTC_ISR_ALRAF_Pos (8U)
11848 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
11849 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11850 #define RTC_ISR_INIT_Pos (7U)
11851 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
11852 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
11853 #define RTC_ISR_INITF_Pos (6U)
11854 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
11855 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
11856 #define RTC_ISR_RSF_Pos (5U)
11857 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
11858 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
11859 #define RTC_ISR_INITS_Pos (4U)
11860 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
11861 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
11862 #define RTC_ISR_SHPF_Pos (3U)
11863 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
11864 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11865 #define RTC_ISR_WUTWF_Pos (2U)
11866 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
11867 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11868 #define RTC_ISR_ALRBWF_Pos (1U)
11869 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
11870 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11871 #define RTC_ISR_ALRAWF_Pos (0U)
11872 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
11873 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11874
11875 /******************** Bits definition for RTC_PRER register *****************/
11876 #define RTC_PRER_PREDIV_A_Pos (16U)
11877 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
11878 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11879 #define RTC_PRER_PREDIV_S_Pos (0U)
11880 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
11881 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11882
11883 /******************** Bits definition for RTC_WUTR register *****************/
11884 #define RTC_WUTR_WUT_Pos (0U)
11885 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
11886 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11887
11888 /******************** Bits definition for RTC_CALIBR register ***************/
11889 #define RTC_CALIBR_DCS_Pos (7U)
11890 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
11891 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
11892 #define RTC_CALIBR_DC_Pos (0U)
11893 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
11894 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
11895
11896 /******************** Bits definition for RTC_ALRMAR register ***************/
11897 #define RTC_ALRMAR_MSK4_Pos (31U)
11898 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
11899 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11900 #define RTC_ALRMAR_WDSEL_Pos (30U)
11901 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
11902 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11903 #define RTC_ALRMAR_DT_Pos (28U)
11904 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
11905 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11906 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
11907 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
11908 #define RTC_ALRMAR_DU_Pos (24U)
11909 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
11910 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11911 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
11912 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
11913 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
11914 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
11915 #define RTC_ALRMAR_MSK3_Pos (23U)
11916 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
11917 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11918 #define RTC_ALRMAR_PM_Pos (22U)
11919 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
11920 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11921 #define RTC_ALRMAR_HT_Pos (20U)
11922 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
11923 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11924 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
11925 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
11926 #define RTC_ALRMAR_HU_Pos (16U)
11927 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
11928 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11929 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
11930 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
11931 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
11932 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
11933 #define RTC_ALRMAR_MSK2_Pos (15U)
11934 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
11935 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11936 #define RTC_ALRMAR_MNT_Pos (12U)
11937 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
11938 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11939 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
11940 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
11941 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
11942 #define RTC_ALRMAR_MNU_Pos (8U)
11943 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
11944 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11945 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
11946 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
11947 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
11948 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
11949 #define RTC_ALRMAR_MSK1_Pos (7U)
11950 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
11951 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11952 #define RTC_ALRMAR_ST_Pos (4U)
11953 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
11954 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11955 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
11956 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
11957 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
11958 #define RTC_ALRMAR_SU_Pos (0U)
11959 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
11960 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11961 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
11962 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
11963 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
11964 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
11965
11966 /******************** Bits definition for RTC_ALRMBR register ***************/
11967 #define RTC_ALRMBR_MSK4_Pos (31U)
11968 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
11969 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11970 #define RTC_ALRMBR_WDSEL_Pos (30U)
11971 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
11972 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11973 #define RTC_ALRMBR_DT_Pos (28U)
11974 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
11975 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11976 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
11977 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
11978 #define RTC_ALRMBR_DU_Pos (24U)
11979 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
11980 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11981 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
11982 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
11983 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
11984 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
11985 #define RTC_ALRMBR_MSK3_Pos (23U)
11986 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
11987 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11988 #define RTC_ALRMBR_PM_Pos (22U)
11989 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
11990 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11991 #define RTC_ALRMBR_HT_Pos (20U)
11992 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
11993 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11994 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
11995 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
11996 #define RTC_ALRMBR_HU_Pos (16U)
11997 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
11998 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11999 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
12000 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
12001 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
12002 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
12003 #define RTC_ALRMBR_MSK2_Pos (15U)
12004 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
12005 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
12006 #define RTC_ALRMBR_MNT_Pos (12U)
12007 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
12008 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
12009 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
12010 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
12011 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
12012 #define RTC_ALRMBR_MNU_Pos (8U)
12013 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
12014 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
12015 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
12016 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
12017 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
12018 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
12019 #define RTC_ALRMBR_MSK1_Pos (7U)
12020 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
12021 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
12022 #define RTC_ALRMBR_ST_Pos (4U)
12023 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
12024 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
12025 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
12026 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
12027 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
12028 #define RTC_ALRMBR_SU_Pos (0U)
12029 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
12030 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
12031 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
12032 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
12033 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
12034 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
12035
12036 /******************** Bits definition for RTC_WPR register ******************/
12037 #define RTC_WPR_KEY_Pos (0U)
12038 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
12039 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
12040
12041 /******************** Bits definition for RTC_SSR register ******************/
12042 #define RTC_SSR_SS_Pos (0U)
12043 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
12044 #define RTC_SSR_SS RTC_SSR_SS_Msk
12045
12046 /******************** Bits definition for RTC_SHIFTR register ***************/
12047 #define RTC_SHIFTR_SUBFS_Pos (0U)
12048 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
12049 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12050 #define RTC_SHIFTR_ADD1S_Pos (31U)
12051 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
12052 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12053
12054 /******************** Bits definition for RTC_TSTR register *****************/
12055 #define RTC_TSTR_PM_Pos (22U)
12056 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
12057 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
12058 #define RTC_TSTR_HT_Pos (20U)
12059 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
12060 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
12061 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
12062 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
12063 #define RTC_TSTR_HU_Pos (16U)
12064 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
12065 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
12066 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
12067 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
12068 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
12069 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
12070 #define RTC_TSTR_MNT_Pos (12U)
12071 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
12072 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12073 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
12074 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
12075 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
12076 #define RTC_TSTR_MNU_Pos (8U)
12077 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
12078 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12079 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
12080 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
12081 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
12082 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
12083 #define RTC_TSTR_ST_Pos (4U)
12084 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
12085 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
12086 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
12087 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
12088 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
12089 #define RTC_TSTR_SU_Pos (0U)
12090 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
12091 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
12092 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
12093 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
12094 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
12095 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
12096
12097 /******************** Bits definition for RTC_TSDR register *****************/
12098 #define RTC_TSDR_WDU_Pos (13U)
12099 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
12100 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12101 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
12102 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
12103 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
12104 #define RTC_TSDR_MT_Pos (12U)
12105 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
12106 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
12107 #define RTC_TSDR_MU_Pos (8U)
12108 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
12109 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
12110 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
12111 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
12112 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
12113 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
12114 #define RTC_TSDR_DT_Pos (4U)
12115 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
12116 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
12117 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
12118 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
12119 #define RTC_TSDR_DU_Pos (0U)
12120 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
12121 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
12122 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
12123 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
12124 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
12125 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
12126
12127 /******************** Bits definition for RTC_TSSSR register ****************/
12128 #define RTC_TSSSR_SS_Pos (0U)
12129 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
12130 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12131
12132 /******************** Bits definition for RTC_CAL register *****************/
12133 #define RTC_CALR_CALP_Pos (15U)
12134 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
12135 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
12136 #define RTC_CALR_CALW8_Pos (14U)
12137 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
12138 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12139 #define RTC_CALR_CALW16_Pos (13U)
12140 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
12141 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12142 #define RTC_CALR_CALM_Pos (0U)
12143 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
12144 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
12145 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
12146 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
12147 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
12148 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
12149 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
12150 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
12151 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
12152 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
12153 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
12154
12155 /******************** Bits definition for RTC_TAFCR register ****************/
12156 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
12157 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
12158 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
12159 #define RTC_TAFCR_TSINSEL_Pos (17U)
12160 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
12161 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
12162 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
12163 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
12164 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
12165 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
12166 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
12167 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
12168 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
12169 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
12170 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
12171 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
12172 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
12173 #define RTC_TAFCR_TAMPFLT_Pos (11U)
12174 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
12175 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
12176 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
12177 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
12178 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
12179 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
12180 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
12181 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
12182 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
12183 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
12184 #define RTC_TAFCR_TAMPTS_Pos (7U)
12185 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
12186 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
12187 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
12188 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
12189 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
12190 #define RTC_TAFCR_TAMP2E_Pos (3U)
12191 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
12192 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
12193 #define RTC_TAFCR_TAMPIE_Pos (2U)
12194 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
12195 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
12196 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
12197 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
12198 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
12199 #define RTC_TAFCR_TAMP1E_Pos (0U)
12200 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
12201 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
12202
12203 /* Legacy defines */
12204 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
12205
12206 /******************** Bits definition for RTC_ALRMASSR register *************/
12207 #define RTC_ALRMASSR_MASKSS_Pos (24U)
12208 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
12209 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12210 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
12211 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
12212 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
12213 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
12214 #define RTC_ALRMASSR_SS_Pos (0U)
12215 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
12216 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12217
12218 /******************** Bits definition for RTC_ALRMBSSR register *************/
12219 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
12220 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
12221 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12222 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
12223 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
12224 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
12225 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
12226 #define RTC_ALRMBSSR_SS_Pos (0U)
12227 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
12228 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12229
12230 /******************** Bits definition for RTC_BKP0R register ****************/
12231 #define RTC_BKP0R_Pos (0U)
12232 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
12233 #define RTC_BKP0R RTC_BKP0R_Msk
12234
12235 /******************** Bits definition for RTC_BKP1R register ****************/
12236 #define RTC_BKP1R_Pos (0U)
12237 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
12238 #define RTC_BKP1R RTC_BKP1R_Msk
12239
12240 /******************** Bits definition for RTC_BKP2R register ****************/
12241 #define RTC_BKP2R_Pos (0U)
12242 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
12243 #define RTC_BKP2R RTC_BKP2R_Msk
12244
12245 /******************** Bits definition for RTC_BKP3R register ****************/
12246 #define RTC_BKP3R_Pos (0U)
12247 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
12248 #define RTC_BKP3R RTC_BKP3R_Msk
12249
12250 /******************** Bits definition for RTC_BKP4R register ****************/
12251 #define RTC_BKP4R_Pos (0U)
12252 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
12253 #define RTC_BKP4R RTC_BKP4R_Msk
12254
12255 /******************** Bits definition for RTC_BKP5R register ****************/
12256 #define RTC_BKP5R_Pos (0U)
12257 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
12258 #define RTC_BKP5R RTC_BKP5R_Msk
12259
12260 /******************** Bits definition for RTC_BKP6R register ****************/
12261 #define RTC_BKP6R_Pos (0U)
12262 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
12263 #define RTC_BKP6R RTC_BKP6R_Msk
12264
12265 /******************** Bits definition for RTC_BKP7R register ****************/
12266 #define RTC_BKP7R_Pos (0U)
12267 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
12268 #define RTC_BKP7R RTC_BKP7R_Msk
12269
12270 /******************** Bits definition for RTC_BKP8R register ****************/
12271 #define RTC_BKP8R_Pos (0U)
12272 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
12273 #define RTC_BKP8R RTC_BKP8R_Msk
12274
12275 /******************** Bits definition for RTC_BKP9R register ****************/
12276 #define RTC_BKP9R_Pos (0U)
12277 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
12278 #define RTC_BKP9R RTC_BKP9R_Msk
12279
12280 /******************** Bits definition for RTC_BKP10R register ***************/
12281 #define RTC_BKP10R_Pos (0U)
12282 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
12283 #define RTC_BKP10R RTC_BKP10R_Msk
12284
12285 /******************** Bits definition for RTC_BKP11R register ***************/
12286 #define RTC_BKP11R_Pos (0U)
12287 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
12288 #define RTC_BKP11R RTC_BKP11R_Msk
12289
12290 /******************** Bits definition for RTC_BKP12R register ***************/
12291 #define RTC_BKP12R_Pos (0U)
12292 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
12293 #define RTC_BKP12R RTC_BKP12R_Msk
12294
12295 /******************** Bits definition for RTC_BKP13R register ***************/
12296 #define RTC_BKP13R_Pos (0U)
12297 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
12298 #define RTC_BKP13R RTC_BKP13R_Msk
12299
12300 /******************** Bits definition for RTC_BKP14R register ***************/
12301 #define RTC_BKP14R_Pos (0U)
12302 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
12303 #define RTC_BKP14R RTC_BKP14R_Msk
12304
12305 /******************** Bits definition for RTC_BKP15R register ***************/
12306 #define RTC_BKP15R_Pos (0U)
12307 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
12308 #define RTC_BKP15R RTC_BKP15R_Msk
12309
12310 /******************** Bits definition for RTC_BKP16R register ***************/
12311 #define RTC_BKP16R_Pos (0U)
12312 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
12313 #define RTC_BKP16R RTC_BKP16R_Msk
12314
12315 /******************** Bits definition for RTC_BKP17R register ***************/
12316 #define RTC_BKP17R_Pos (0U)
12317 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
12318 #define RTC_BKP17R RTC_BKP17R_Msk
12319
12320 /******************** Bits definition for RTC_BKP18R register ***************/
12321 #define RTC_BKP18R_Pos (0U)
12322 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
12323 #define RTC_BKP18R RTC_BKP18R_Msk
12324
12325 /******************** Bits definition for RTC_BKP19R register ***************/
12326 #define RTC_BKP19R_Pos (0U)
12327 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
12328 #define RTC_BKP19R RTC_BKP19R_Msk
12329
12330 /******************** Number of backup registers ******************************/
12331 #define RTC_BKP_NUMBER 0x000000014U
12332
12333 /******************************************************************************/
12334 /* */
12335 /* Serial Audio Interface */
12336 /* */
12337 /******************************************************************************/
12338 /******************** Bit definition for SAI_GCR register *******************/
12339 #define SAI_GCR_SYNCIN_Pos (0U)
12340 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
12341 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
12342 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
12343 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
12344
12345 #define SAI_GCR_SYNCOUT_Pos (4U)
12346 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
12347 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
12348 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
12349 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
12350
12351 /******************* Bit definition for SAI_xCR1 register *******************/
12352 #define SAI_xCR1_MODE_Pos (0U)
12353 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
12354 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
12355 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
12356 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
12357
12358 #define SAI_xCR1_PRTCFG_Pos (2U)
12359 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
12360 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
12361 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
12362 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
12363
12364 #define SAI_xCR1_DS_Pos (5U)
12365 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
12366 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
12367 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
12368 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
12369 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
12370
12371 #define SAI_xCR1_LSBFIRST_Pos (8U)
12372 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
12373 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
12374 #define SAI_xCR1_CKSTR_Pos (9U)
12375 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
12376 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
12377
12378 #define SAI_xCR1_SYNCEN_Pos (10U)
12379 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
12380 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
12381 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
12382 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
12383
12384 #define SAI_xCR1_MONO_Pos (12U)
12385 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
12386 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
12387 #define SAI_xCR1_OUTDRIV_Pos (13U)
12388 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
12389 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
12390 #define SAI_xCR1_SAIEN_Pos (16U)
12391 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
12392 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
12393 #define SAI_xCR1_DMAEN_Pos (17U)
12394 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
12395 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
12396 #define SAI_xCR1_NODIV_Pos (19U)
12397 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
12398 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
12399
12400 #define SAI_xCR1_MCKDIV_Pos (20U)
12401 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
12402 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
12403 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
12404 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
12405 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
12406 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
12407
12408 /******************* Bit definition for SAI_xCR2 register *******************/
12409 #define SAI_xCR2_FTH_Pos (0U)
12410 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
12411 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
12412 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
12413 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
12414 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
12415
12416 #define SAI_xCR2_FFLUSH_Pos (3U)
12417 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
12418 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
12419 #define SAI_xCR2_TRIS_Pos (4U)
12420 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
12421 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
12422 #define SAI_xCR2_MUTE_Pos (5U)
12423 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
12424 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
12425 #define SAI_xCR2_MUTEVAL_Pos (6U)
12426 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
12427 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
12428
12429 #define SAI_xCR2_MUTECNT_Pos (7U)
12430 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
12431 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
12432 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
12433 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
12434 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
12435 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
12436 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
12437 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
12438
12439 #define SAI_xCR2_CPL_Pos (13U)
12440 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
12441 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
12442
12443 #define SAI_xCR2_COMP_Pos (14U)
12444 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
12445 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
12446 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
12447 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
12448
12449 /****************** Bit definition for SAI_xFRCR register *******************/
12450 #define SAI_xFRCR_FRL_Pos (0U)
12451 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
12452 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
12453 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
12454 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
12455 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
12456 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
12457 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
12458 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
12459 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
12460 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
12461
12462 #define SAI_xFRCR_FSALL_Pos (8U)
12463 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
12464 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
12465 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
12466 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
12467 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
12468 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
12469 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
12470 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
12471 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
12472
12473 #define SAI_xFRCR_FSDEF_Pos (16U)
12474 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
12475 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
12476 #define SAI_xFRCR_FSPOL_Pos (17U)
12477 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
12478 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
12479 #define SAI_xFRCR_FSOFF_Pos (18U)
12480 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
12481 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
12482 /* Legacy defines */
12483 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
12484
12485 /****************** Bit definition for SAI_xSLOTR register *******************/
12486 #define SAI_xSLOTR_FBOFF_Pos (0U)
12487 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
12488 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
12489 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
12490 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
12491 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
12492 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
12493 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
12494
12495 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
12496 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
12497 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
12498 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
12499 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
12500
12501 #define SAI_xSLOTR_NBSLOT_Pos (8U)
12502 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
12503 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
12504 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
12505 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
12506 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
12507 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
12508
12509 #define SAI_xSLOTR_SLOTEN_Pos (16U)
12510 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
12511 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
12512
12513 /******************* Bit definition for SAI_xIMR register *******************/
12514 #define SAI_xIMR_OVRUDRIE_Pos (0U)
12515 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
12516 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
12517 #define SAI_xIMR_MUTEDETIE_Pos (1U)
12518 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
12519 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
12520 #define SAI_xIMR_WCKCFGIE_Pos (2U)
12521 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
12522 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
12523 #define SAI_xIMR_FREQIE_Pos (3U)
12524 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
12525 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
12526 #define SAI_xIMR_CNRDYIE_Pos (4U)
12527 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
12528 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
12529 #define SAI_xIMR_AFSDETIE_Pos (5U)
12530 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
12531 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
12532 #define SAI_xIMR_LFSDETIE_Pos (6U)
12533 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
12534 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
12535
12536 /******************** Bit definition for SAI_xSR register *******************/
12537 #define SAI_xSR_OVRUDR_Pos (0U)
12538 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
12539 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
12540 #define SAI_xSR_MUTEDET_Pos (1U)
12541 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
12542 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
12543 #define SAI_xSR_WCKCFG_Pos (2U)
12544 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
12545 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
12546 #define SAI_xSR_FREQ_Pos (3U)
12547 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
12548 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
12549 #define SAI_xSR_CNRDY_Pos (4U)
12550 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
12551 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
12552 #define SAI_xSR_AFSDET_Pos (5U)
12553 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
12554 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
12555 #define SAI_xSR_LFSDET_Pos (6U)
12556 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
12557 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
12558
12559 #define SAI_xSR_FLVL_Pos (16U)
12560 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
12561 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
12562 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
12563 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
12564 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
12565
12566 /****************** Bit definition for SAI_xCLRFR register ******************/
12567 #define SAI_xCLRFR_COVRUDR_Pos (0U)
12568 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
12569 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
12570 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
12571 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
12572 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
12573 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
12574 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
12575 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
12576 #define SAI_xCLRFR_CFREQ_Pos (3U)
12577 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
12578 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
12579 #define SAI_xCLRFR_CCNRDY_Pos (4U)
12580 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
12581 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
12582 #define SAI_xCLRFR_CAFSDET_Pos (5U)
12583 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
12584 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
12585 #define SAI_xCLRFR_CLFSDET_Pos (6U)
12586 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
12587 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
12588
12589 /****************** Bit definition for SAI_xDR register ******************/
12590 #define SAI_xDR_DATA_Pos (0U)
12591 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
12592 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
12593
12594
12595 /******************************************************************************/
12596 /* */
12597 /* SD host Interface */
12598 /* */
12599 /******************************************************************************/
12600 /****************** Bit definition for SDIO_POWER register ******************/
12601 #define SDIO_POWER_PWRCTRL_Pos (0U)
12602 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
12603 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
12604 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
12605 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
12606
12607 /****************** Bit definition for SDIO_CLKCR register ******************/
12608 #define SDIO_CLKCR_CLKDIV_Pos (0U)
12609 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
12610 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
12611 #define SDIO_CLKCR_CLKEN_Pos (8U)
12612 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
12613 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
12614 #define SDIO_CLKCR_PWRSAV_Pos (9U)
12615 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
12616 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
12617 #define SDIO_CLKCR_BYPASS_Pos (10U)
12618 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
12619 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
12620
12621 #define SDIO_CLKCR_WIDBUS_Pos (11U)
12622 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
12623 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
12624 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
12625 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
12626
12627 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
12628 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
12629 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
12630 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
12631 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
12632 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
12633
12634 /******************* Bit definition for SDIO_ARG register *******************/
12635 #define SDIO_ARG_CMDARG_Pos (0U)
12636 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
12637 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
12638
12639 /******************* Bit definition for SDIO_CMD register *******************/
12640 #define SDIO_CMD_CMDINDEX_Pos (0U)
12641 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
12642 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
12643
12644 #define SDIO_CMD_WAITRESP_Pos (6U)
12645 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
12646 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
12647 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
12648 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
12649
12650 #define SDIO_CMD_WAITINT_Pos (8U)
12651 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
12652 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
12653 #define SDIO_CMD_WAITPEND_Pos (9U)
12654 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
12655 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
12656 #define SDIO_CMD_CPSMEN_Pos (10U)
12657 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
12658 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
12659 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
12660 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
12661 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
12662 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
12663 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
12664 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
12665 #define SDIO_CMD_NIEN_Pos (13U)
12666 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
12667 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
12668 #define SDIO_CMD_CEATACMD_Pos (14U)
12669 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
12670 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
12671
12672 /***************** Bit definition for SDIO_RESPCMD register *****************/
12673 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
12674 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
12675 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
12676
12677 /****************** Bit definition for SDIO_RESP0 register ******************/
12678 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
12679 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
12680 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
12681
12682 /****************** Bit definition for SDIO_RESP1 register ******************/
12683 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
12684 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
12685 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
12686
12687 /****************** Bit definition for SDIO_RESP2 register ******************/
12688 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
12689 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
12690 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
12691
12692 /****************** Bit definition for SDIO_RESP3 register ******************/
12693 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
12694 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
12695 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
12696
12697 /****************** Bit definition for SDIO_RESP4 register ******************/
12698 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
12699 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
12700 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
12701
12702 /****************** Bit definition for SDIO_DTIMER register *****************/
12703 #define SDIO_DTIMER_DATATIME_Pos (0U)
12704 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
12705 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
12706
12707 /****************** Bit definition for SDIO_DLEN register *******************/
12708 #define SDIO_DLEN_DATALENGTH_Pos (0U)
12709 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
12710 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
12711
12712 /****************** Bit definition for SDIO_DCTRL register ******************/
12713 #define SDIO_DCTRL_DTEN_Pos (0U)
12714 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
12715 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
12716 #define SDIO_DCTRL_DTDIR_Pos (1U)
12717 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
12718 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
12719 #define SDIO_DCTRL_DTMODE_Pos (2U)
12720 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
12721 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
12722 #define SDIO_DCTRL_DMAEN_Pos (3U)
12723 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
12724 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
12725
12726 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
12727 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
12728 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
12729 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
12730 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
12731 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
12732 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
12733
12734 #define SDIO_DCTRL_RWSTART_Pos (8U)
12735 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
12736 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
12737 #define SDIO_DCTRL_RWSTOP_Pos (9U)
12738 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
12739 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
12740 #define SDIO_DCTRL_RWMOD_Pos (10U)
12741 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
12742 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
12743 #define SDIO_DCTRL_SDIOEN_Pos (11U)
12744 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
12745 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
12746
12747 /****************** Bit definition for SDIO_DCOUNT register *****************/
12748 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
12749 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
12750 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
12751
12752 /****************** Bit definition for SDIO_STA register ********************/
12753 #define SDIO_STA_CCRCFAIL_Pos (0U)
12754 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
12755 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
12756 #define SDIO_STA_DCRCFAIL_Pos (1U)
12757 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
12758 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
12759 #define SDIO_STA_CTIMEOUT_Pos (2U)
12760 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
12761 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
12762 #define SDIO_STA_DTIMEOUT_Pos (3U)
12763 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
12764 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
12765 #define SDIO_STA_TXUNDERR_Pos (4U)
12766 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
12767 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
12768 #define SDIO_STA_RXOVERR_Pos (5U)
12769 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
12770 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
12771 #define SDIO_STA_CMDREND_Pos (6U)
12772 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
12773 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
12774 #define SDIO_STA_CMDSENT_Pos (7U)
12775 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
12776 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
12777 #define SDIO_STA_DATAEND_Pos (8U)
12778 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
12779 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
12780 #define SDIO_STA_STBITERR_Pos (9U)
12781 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
12782 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
12783 #define SDIO_STA_DBCKEND_Pos (10U)
12784 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
12785 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
12786 #define SDIO_STA_CMDACT_Pos (11U)
12787 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
12788 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
12789 #define SDIO_STA_TXACT_Pos (12U)
12790 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
12791 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
12792 #define SDIO_STA_RXACT_Pos (13U)
12793 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
12794 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
12795 #define SDIO_STA_TXFIFOHE_Pos (14U)
12796 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
12797 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
12798 #define SDIO_STA_RXFIFOHF_Pos (15U)
12799 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
12800 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
12801 #define SDIO_STA_TXFIFOF_Pos (16U)
12802 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
12803 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
12804 #define SDIO_STA_RXFIFOF_Pos (17U)
12805 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
12806 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
12807 #define SDIO_STA_TXFIFOE_Pos (18U)
12808 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
12809 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
12810 #define SDIO_STA_RXFIFOE_Pos (19U)
12811 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
12812 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
12813 #define SDIO_STA_TXDAVL_Pos (20U)
12814 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
12815 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
12816 #define SDIO_STA_RXDAVL_Pos (21U)
12817 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
12818 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
12819 #define SDIO_STA_SDIOIT_Pos (22U)
12820 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
12821 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
12822 #define SDIO_STA_CEATAEND_Pos (23U)
12823 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
12824 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
12825
12826 /******************* Bit definition for SDIO_ICR register *******************/
12827 #define SDIO_ICR_CCRCFAILC_Pos (0U)
12828 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
12829 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
12830 #define SDIO_ICR_DCRCFAILC_Pos (1U)
12831 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
12832 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
12833 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
12834 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
12835 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
12836 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
12837 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
12838 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
12839 #define SDIO_ICR_TXUNDERRC_Pos (4U)
12840 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
12841 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
12842 #define SDIO_ICR_RXOVERRC_Pos (5U)
12843 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
12844 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
12845 #define SDIO_ICR_CMDRENDC_Pos (6U)
12846 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
12847 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
12848 #define SDIO_ICR_CMDSENTC_Pos (7U)
12849 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
12850 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
12851 #define SDIO_ICR_DATAENDC_Pos (8U)
12852 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
12853 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
12854 #define SDIO_ICR_STBITERRC_Pos (9U)
12855 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
12856 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
12857 #define SDIO_ICR_DBCKENDC_Pos (10U)
12858 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
12859 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
12860 #define SDIO_ICR_SDIOITC_Pos (22U)
12861 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
12862 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
12863 #define SDIO_ICR_CEATAENDC_Pos (23U)
12864 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
12865 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
12866
12867 /****************** Bit definition for SDIO_MASK register *******************/
12868 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
12869 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
12870 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
12871 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
12872 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
12873 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
12874 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
12875 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
12876 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
12877 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
12878 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
12879 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
12880 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
12881 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
12882 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
12883 #define SDIO_MASK_RXOVERRIE_Pos (5U)
12884 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
12885 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
12886 #define SDIO_MASK_CMDRENDIE_Pos (6U)
12887 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
12888 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
12889 #define SDIO_MASK_CMDSENTIE_Pos (7U)
12890 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
12891 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
12892 #define SDIO_MASK_DATAENDIE_Pos (8U)
12893 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
12894 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
12895 #define SDIO_MASK_STBITERRIE_Pos (9U)
12896 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
12897 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
12898 #define SDIO_MASK_DBCKENDIE_Pos (10U)
12899 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
12900 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
12901 #define SDIO_MASK_CMDACTIE_Pos (11U)
12902 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
12903 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
12904 #define SDIO_MASK_TXACTIE_Pos (12U)
12905 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
12906 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
12907 #define SDIO_MASK_RXACTIE_Pos (13U)
12908 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
12909 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
12910 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
12911 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
12912 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
12913 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
12914 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
12915 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
12916 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
12917 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
12918 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
12919 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
12920 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
12921 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
12922 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
12923 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
12924 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
12925 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
12926 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
12927 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
12928 #define SDIO_MASK_TXDAVLIE_Pos (20U)
12929 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
12930 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
12931 #define SDIO_MASK_RXDAVLIE_Pos (21U)
12932 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
12933 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
12934 #define SDIO_MASK_SDIOITIE_Pos (22U)
12935 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
12936 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
12937 #define SDIO_MASK_CEATAENDIE_Pos (23U)
12938 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
12939 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
12940
12941 /***************** Bit definition for SDIO_FIFOCNT register *****************/
12942 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
12943 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
12944 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
12945
12946 /****************** Bit definition for SDIO_FIFO register *******************/
12947 #define SDIO_FIFO_FIFODATA_Pos (0U)
12948 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
12949 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
12950
12951 /******************************************************************************/
12952 /* */
12953 /* Serial Peripheral Interface */
12954 /* */
12955 /******************************************************************************/
12956 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
12957
12958 /******************* Bit definition for SPI_CR1 register ********************/
12959 #define SPI_CR1_CPHA_Pos (0U)
12960 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
12961 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
12962 #define SPI_CR1_CPOL_Pos (1U)
12963 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
12964 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
12965 #define SPI_CR1_MSTR_Pos (2U)
12966 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
12967 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
12968
12969 #define SPI_CR1_BR_Pos (3U)
12970 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
12971 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
12972 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
12973 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
12974 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
12975
12976 #define SPI_CR1_SPE_Pos (6U)
12977 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
12978 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
12979 #define SPI_CR1_LSBFIRST_Pos (7U)
12980 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
12981 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
12982 #define SPI_CR1_SSI_Pos (8U)
12983 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
12984 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
12985 #define SPI_CR1_SSM_Pos (9U)
12986 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
12987 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
12988 #define SPI_CR1_RXONLY_Pos (10U)
12989 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
12990 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
12991 #define SPI_CR1_DFF_Pos (11U)
12992 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
12993 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
12994 #define SPI_CR1_CRCNEXT_Pos (12U)
12995 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
12996 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
12997 #define SPI_CR1_CRCEN_Pos (13U)
12998 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
12999 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
13000 #define SPI_CR1_BIDIOE_Pos (14U)
13001 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
13002 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
13003 #define SPI_CR1_BIDIMODE_Pos (15U)
13004 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
13005 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
13006
13007 /******************* Bit definition for SPI_CR2 register ********************/
13008 #define SPI_CR2_RXDMAEN_Pos (0U)
13009 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
13010 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
13011 #define SPI_CR2_TXDMAEN_Pos (1U)
13012 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
13013 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
13014 #define SPI_CR2_SSOE_Pos (2U)
13015 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
13016 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
13017 #define SPI_CR2_FRF_Pos (4U)
13018 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
13019 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
13020 #define SPI_CR2_ERRIE_Pos (5U)
13021 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
13022 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
13023 #define SPI_CR2_RXNEIE_Pos (6U)
13024 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
13025 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
13026 #define SPI_CR2_TXEIE_Pos (7U)
13027 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
13028 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
13029
13030 /******************** Bit definition for SPI_SR register ********************/
13031 #define SPI_SR_RXNE_Pos (0U)
13032 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
13033 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
13034 #define SPI_SR_TXE_Pos (1U)
13035 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
13036 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
13037 #define SPI_SR_CHSIDE_Pos (2U)
13038 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
13039 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
13040 #define SPI_SR_UDR_Pos (3U)
13041 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
13042 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
13043 #define SPI_SR_CRCERR_Pos (4U)
13044 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
13045 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
13046 #define SPI_SR_MODF_Pos (5U)
13047 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
13048 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
13049 #define SPI_SR_OVR_Pos (6U)
13050 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
13051 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
13052 #define SPI_SR_BSY_Pos (7U)
13053 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
13054 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
13055 #define SPI_SR_FRE_Pos (8U)
13056 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
13057 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
13058
13059 /******************** Bit definition for SPI_DR register ********************/
13060 #define SPI_DR_DR_Pos (0U)
13061 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
13062 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
13063
13064 /******************* Bit definition for SPI_CRCPR register ******************/
13065 #define SPI_CRCPR_CRCPOLY_Pos (0U)
13066 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
13067 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
13068
13069 /****************** Bit definition for SPI_RXCRCR register ******************/
13070 #define SPI_RXCRCR_RXCRC_Pos (0U)
13071 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
13072 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
13073
13074 /****************** Bit definition for SPI_TXCRCR register ******************/
13075 #define SPI_TXCRCR_TXCRC_Pos (0U)
13076 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
13077 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
13078
13079 /****************** Bit definition for SPI_I2SCFGR register *****************/
13080 #define SPI_I2SCFGR_CHLEN_Pos (0U)
13081 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
13082 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
13083
13084 #define SPI_I2SCFGR_DATLEN_Pos (1U)
13085 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
13086 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
13087 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
13088 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
13089
13090 #define SPI_I2SCFGR_CKPOL_Pos (3U)
13091 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
13092 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
13093
13094 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
13095 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
13096 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
13097 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
13098 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
13099
13100 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
13101 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
13102 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
13103
13104 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
13105 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
13106 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
13107 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
13108 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
13109
13110 #define SPI_I2SCFGR_I2SE_Pos (10U)
13111 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
13112 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
13113 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
13114 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
13115 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
13116
13117 /****************** Bit definition for SPI_I2SPR register *******************/
13118 #define SPI_I2SPR_I2SDIV_Pos (0U)
13119 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
13120 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
13121 #define SPI_I2SPR_ODD_Pos (8U)
13122 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
13123 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
13124 #define SPI_I2SPR_MCKOE_Pos (9U)
13125 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
13126 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
13127
13128 /******************************************************************************/
13129 /* */
13130 /* SYSCFG */
13131 /* */
13132 /******************************************************************************/
13133 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
13134 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
13135 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
13136 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
13137 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
13138 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
13139 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
13140 #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
13141 #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
13142 #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
13143 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
13144 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
13145 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
13146 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
13147 /* Legacy Defines */
13148 #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
13149 /****************** Bit definition for SYSCFG_PMC register ******************/
13150 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
13151 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
13152 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
13153 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
13154 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
13155 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
13156 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
13157 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
13158 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
13159 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
13160 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
13161 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
13162 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
13163 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
13164 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
13165 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
13166 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
13167
13168 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13169 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13170 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
13171 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
13172 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13173 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
13174 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
13175 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13176 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
13177 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
13178 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13179 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
13180 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
13181 /**
13182 * @brief EXTI0 configuration
13183 */
13184 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
13185 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
13186 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
13187 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
13188 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
13189 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
13190 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
13191 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
13192 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
13193 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
13194 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
13195
13196 /**
13197 * @brief EXTI1 configuration
13198 */
13199 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
13200 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
13201 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
13202 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
13203 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
13204 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
13205 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
13206 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
13207 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
13208 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
13209 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
13210
13211 /**
13212 * @brief EXTI2 configuration
13213 */
13214 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
13215 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
13216 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
13217 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
13218 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
13219 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
13220 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
13221 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
13222 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
13223 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
13224 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
13225
13226 /**
13227 * @brief EXTI3 configuration
13228 */
13229 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
13230 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
13231 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
13232 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
13233 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
13234 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
13235 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
13236 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
13237 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
13238 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
13239 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
13240
13241 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13242 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13243 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
13244 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
13245 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13246 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
13247 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
13248 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13249 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
13250 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
13251 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13252 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
13253 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
13254
13255 /**
13256 * @brief EXTI4 configuration
13257 */
13258 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
13259 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
13260 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
13261 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
13262 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
13263 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
13264 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
13265 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
13266 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
13267 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
13268 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
13269
13270 /**
13271 * @brief EXTI5 configuration
13272 */
13273 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
13274 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
13275 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
13276 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
13277 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
13278 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
13279 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
13280 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
13281 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
13282 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
13283 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
13284
13285 /**
13286 * @brief EXTI6 configuration
13287 */
13288 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
13289 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
13290 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
13291 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
13292 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
13293 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
13294 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
13295 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
13296 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
13297 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
13298 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
13299
13300 /**
13301 * @brief EXTI7 configuration
13302 */
13303 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
13304 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
13305 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
13306 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
13307 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
13308 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
13309 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
13310 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
13311 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
13312 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
13313 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
13314
13315 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13316 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13317 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
13318 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
13319 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13320 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
13321 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
13322 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13323 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
13324 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
13325 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13326 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
13327 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
13328
13329 /**
13330 * @brief EXTI8 configuration
13331 */
13332 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
13333 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
13334 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
13335 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
13336 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
13337 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
13338 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
13339 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
13340 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
13341 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
13342
13343 /**
13344 * @brief EXTI9 configuration
13345 */
13346 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
13347 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
13348 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
13349 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
13350 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
13351 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
13352 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
13353 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
13354 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
13355 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
13356
13357 /**
13358 * @brief EXTI10 configuration
13359 */
13360 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
13361 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
13362 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
13363 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
13364 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
13365 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
13366 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
13367 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
13368 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
13369 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
13370
13371 /**
13372 * @brief EXTI11 configuration
13373 */
13374 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
13375 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
13376 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
13377 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
13378 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
13379 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
13380 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
13381 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
13382 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
13383 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
13384
13385
13386 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13387 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13388 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
13389 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
13390 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13391 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
13392 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
13393 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13394 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
13395 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
13396 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13397 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
13398 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
13399
13400 /**
13401 * @brief EXTI12 configuration
13402 */
13403 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
13404 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
13405 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
13406 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
13407 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
13408 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
13409 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
13410 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
13411 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
13412 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
13413
13414 /**
13415 * @brief EXTI13 configuration
13416 */
13417 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
13418 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
13419 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
13420 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
13421 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
13422 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
13423 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
13424 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
13425 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
13426 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
13427
13428 /**
13429 * @brief EXTI14 configuration
13430 */
13431 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
13432 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
13433 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
13434 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
13435 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
13436 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
13437 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
13438 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
13439 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
13440 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
13441
13442 /**
13443 * @brief EXTI15 configuration
13444 */
13445 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
13446 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
13447 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
13448 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
13449 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
13450 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
13451 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
13452 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
13453 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
13454 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
13455
13456 /****************** Bit definition for SYSCFG_CMPCR register ****************/
13457 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
13458 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
13459 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
13460 #define SYSCFG_CMPCR_READY_Pos (8U)
13461 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
13462 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
13463
13464 /******************************************************************************/
13465 /* */
13466 /* TIM */
13467 /* */
13468 /******************************************************************************/
13469 /******************* Bit definition for TIM_CR1 register ********************/
13470 #define TIM_CR1_CEN_Pos (0U)
13471 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
13472 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
13473 #define TIM_CR1_UDIS_Pos (1U)
13474 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
13475 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
13476 #define TIM_CR1_URS_Pos (2U)
13477 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
13478 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
13479 #define TIM_CR1_OPM_Pos (3U)
13480 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
13481 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
13482 #define TIM_CR1_DIR_Pos (4U)
13483 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
13484 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
13485
13486 #define TIM_CR1_CMS_Pos (5U)
13487 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
13488 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
13489 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
13490 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
13491
13492 #define TIM_CR1_ARPE_Pos (7U)
13493 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
13494 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
13495
13496 #define TIM_CR1_CKD_Pos (8U)
13497 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
13498 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
13499 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
13500 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
13501
13502 /******************* Bit definition for TIM_CR2 register ********************/
13503 #define TIM_CR2_CCPC_Pos (0U)
13504 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
13505 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
13506 #define TIM_CR2_CCUS_Pos (2U)
13507 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
13508 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
13509 #define TIM_CR2_CCDS_Pos (3U)
13510 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
13511 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
13512
13513 #define TIM_CR2_MMS_Pos (4U)
13514 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
13515 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
13516 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
13517 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
13518 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
13519
13520 #define TIM_CR2_TI1S_Pos (7U)
13521 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
13522 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
13523 #define TIM_CR2_OIS1_Pos (8U)
13524 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
13525 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
13526 #define TIM_CR2_OIS1N_Pos (9U)
13527 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
13528 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
13529 #define TIM_CR2_OIS2_Pos (10U)
13530 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
13531 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
13532 #define TIM_CR2_OIS2N_Pos (11U)
13533 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
13534 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
13535 #define TIM_CR2_OIS3_Pos (12U)
13536 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
13537 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
13538 #define TIM_CR2_OIS3N_Pos (13U)
13539 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
13540 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
13541 #define TIM_CR2_OIS4_Pos (14U)
13542 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
13543 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
13544
13545 /******************* Bit definition for TIM_SMCR register *******************/
13546 #define TIM_SMCR_SMS_Pos (0U)
13547 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
13548 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
13549 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
13550 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
13551 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
13552
13553 #define TIM_SMCR_TS_Pos (4U)
13554 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
13555 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
13556 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
13557 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
13558 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
13559
13560 #define TIM_SMCR_MSM_Pos (7U)
13561 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
13562 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
13563
13564 #define TIM_SMCR_ETF_Pos (8U)
13565 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
13566 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
13567 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
13568 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
13569 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
13570 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
13571
13572 #define TIM_SMCR_ETPS_Pos (12U)
13573 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
13574 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
13575 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
13576 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
13577
13578 #define TIM_SMCR_ECE_Pos (14U)
13579 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
13580 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
13581 #define TIM_SMCR_ETP_Pos (15U)
13582 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
13583 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
13584
13585 /******************* Bit definition for TIM_DIER register *******************/
13586 #define TIM_DIER_UIE_Pos (0U)
13587 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
13588 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
13589 #define TIM_DIER_CC1IE_Pos (1U)
13590 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
13591 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
13592 #define TIM_DIER_CC2IE_Pos (2U)
13593 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
13594 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
13595 #define TIM_DIER_CC3IE_Pos (3U)
13596 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
13597 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
13598 #define TIM_DIER_CC4IE_Pos (4U)
13599 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
13600 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
13601 #define TIM_DIER_COMIE_Pos (5U)
13602 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
13603 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
13604 #define TIM_DIER_TIE_Pos (6U)
13605 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
13606 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
13607 #define TIM_DIER_BIE_Pos (7U)
13608 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
13609 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
13610 #define TIM_DIER_UDE_Pos (8U)
13611 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
13612 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
13613 #define TIM_DIER_CC1DE_Pos (9U)
13614 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
13615 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
13616 #define TIM_DIER_CC2DE_Pos (10U)
13617 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
13618 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
13619 #define TIM_DIER_CC3DE_Pos (11U)
13620 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
13621 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
13622 #define TIM_DIER_CC4DE_Pos (12U)
13623 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
13624 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
13625 #define TIM_DIER_COMDE_Pos (13U)
13626 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
13627 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
13628 #define TIM_DIER_TDE_Pos (14U)
13629 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
13630 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
13631
13632 /******************** Bit definition for TIM_SR register ********************/
13633 #define TIM_SR_UIF_Pos (0U)
13634 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
13635 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
13636 #define TIM_SR_CC1IF_Pos (1U)
13637 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
13638 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
13639 #define TIM_SR_CC2IF_Pos (2U)
13640 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
13641 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
13642 #define TIM_SR_CC3IF_Pos (3U)
13643 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
13644 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
13645 #define TIM_SR_CC4IF_Pos (4U)
13646 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
13647 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
13648 #define TIM_SR_COMIF_Pos (5U)
13649 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
13650 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
13651 #define TIM_SR_TIF_Pos (6U)
13652 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
13653 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
13654 #define TIM_SR_BIF_Pos (7U)
13655 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
13656 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
13657 #define TIM_SR_CC1OF_Pos (9U)
13658 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
13659 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
13660 #define TIM_SR_CC2OF_Pos (10U)
13661 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
13662 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
13663 #define TIM_SR_CC3OF_Pos (11U)
13664 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
13665 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
13666 #define TIM_SR_CC4OF_Pos (12U)
13667 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
13668 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
13669
13670 /******************* Bit definition for TIM_EGR register ********************/
13671 #define TIM_EGR_UG_Pos (0U)
13672 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
13673 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
13674 #define TIM_EGR_CC1G_Pos (1U)
13675 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
13676 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
13677 #define TIM_EGR_CC2G_Pos (2U)
13678 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
13679 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
13680 #define TIM_EGR_CC3G_Pos (3U)
13681 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
13682 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
13683 #define TIM_EGR_CC4G_Pos (4U)
13684 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
13685 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
13686 #define TIM_EGR_COMG_Pos (5U)
13687 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
13688 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
13689 #define TIM_EGR_TG_Pos (6U)
13690 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
13691 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
13692 #define TIM_EGR_BG_Pos (7U)
13693 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
13694 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
13695
13696 /****************** Bit definition for TIM_CCMR1 register *******************/
13697 #define TIM_CCMR1_CC1S_Pos (0U)
13698 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
13699 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13700 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
13701 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
13702
13703 #define TIM_CCMR1_OC1FE_Pos (2U)
13704 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
13705 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
13706 #define TIM_CCMR1_OC1PE_Pos (3U)
13707 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
13708 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
13709
13710 #define TIM_CCMR1_OC1M_Pos (4U)
13711 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
13712 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
13713 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
13714 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
13715 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
13716
13717 #define TIM_CCMR1_OC1CE_Pos (7U)
13718 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
13719 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
13720
13721 #define TIM_CCMR1_CC2S_Pos (8U)
13722 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
13723 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
13724 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
13725 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
13726
13727 #define TIM_CCMR1_OC2FE_Pos (10U)
13728 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
13729 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
13730 #define TIM_CCMR1_OC2PE_Pos (11U)
13731 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
13732 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
13733
13734 #define TIM_CCMR1_OC2M_Pos (12U)
13735 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
13736 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
13737 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
13738 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
13739 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
13740
13741 #define TIM_CCMR1_OC2CE_Pos (15U)
13742 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
13743 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
13744
13745 /*----------------------------------------------------------------------------*/
13746
13747 #define TIM_CCMR1_IC1PSC_Pos (2U)
13748 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
13749 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
13750 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
13751 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
13752
13753 #define TIM_CCMR1_IC1F_Pos (4U)
13754 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
13755 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
13756 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
13757 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
13758 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
13759 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
13760
13761 #define TIM_CCMR1_IC2PSC_Pos (10U)
13762 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
13763 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
13764 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
13765 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
13766
13767 #define TIM_CCMR1_IC2F_Pos (12U)
13768 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
13769 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
13770 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
13771 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
13772 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
13773 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
13774
13775 /****************** Bit definition for TIM_CCMR2 register *******************/
13776 #define TIM_CCMR2_CC3S_Pos (0U)
13777 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
13778 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
13779 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
13780 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
13781
13782 #define TIM_CCMR2_OC3FE_Pos (2U)
13783 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
13784 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
13785 #define TIM_CCMR2_OC3PE_Pos (3U)
13786 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
13787 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
13788
13789 #define TIM_CCMR2_OC3M_Pos (4U)
13790 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
13791 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
13792 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
13793 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
13794 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
13795
13796 #define TIM_CCMR2_OC3CE_Pos (7U)
13797 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
13798 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
13799
13800 #define TIM_CCMR2_CC4S_Pos (8U)
13801 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
13802 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
13803 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
13804 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
13805
13806 #define TIM_CCMR2_OC4FE_Pos (10U)
13807 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
13808 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
13809 #define TIM_CCMR2_OC4PE_Pos (11U)
13810 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
13811 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
13812
13813 #define TIM_CCMR2_OC4M_Pos (12U)
13814 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
13815 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
13816 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
13817 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
13818 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
13819
13820 #define TIM_CCMR2_OC4CE_Pos (15U)
13821 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
13822 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
13823
13824 /*----------------------------------------------------------------------------*/
13825
13826 #define TIM_CCMR2_IC3PSC_Pos (2U)
13827 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
13828 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
13829 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
13830 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
13831
13832 #define TIM_CCMR2_IC3F_Pos (4U)
13833 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
13834 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
13835 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
13836 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
13837 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
13838 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
13839
13840 #define TIM_CCMR2_IC4PSC_Pos (10U)
13841 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
13842 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
13843 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
13844 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
13845
13846 #define TIM_CCMR2_IC4F_Pos (12U)
13847 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
13848 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
13849 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
13850 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
13851 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
13852 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
13853
13854 /******************* Bit definition for TIM_CCER register *******************/
13855 #define TIM_CCER_CC1E_Pos (0U)
13856 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
13857 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
13858 #define TIM_CCER_CC1P_Pos (1U)
13859 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
13860 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
13861 #define TIM_CCER_CC1NE_Pos (2U)
13862 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
13863 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
13864 #define TIM_CCER_CC1NP_Pos (3U)
13865 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
13866 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
13867 #define TIM_CCER_CC2E_Pos (4U)
13868 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
13869 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
13870 #define TIM_CCER_CC2P_Pos (5U)
13871 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
13872 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
13873 #define TIM_CCER_CC2NE_Pos (6U)
13874 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
13875 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
13876 #define TIM_CCER_CC2NP_Pos (7U)
13877 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
13878 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
13879 #define TIM_CCER_CC3E_Pos (8U)
13880 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
13881 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
13882 #define TIM_CCER_CC3P_Pos (9U)
13883 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
13884 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
13885 #define TIM_CCER_CC3NE_Pos (10U)
13886 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
13887 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
13888 #define TIM_CCER_CC3NP_Pos (11U)
13889 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
13890 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
13891 #define TIM_CCER_CC4E_Pos (12U)
13892 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
13893 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
13894 #define TIM_CCER_CC4P_Pos (13U)
13895 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
13896 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
13897 #define TIM_CCER_CC4NP_Pos (15U)
13898 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
13899 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
13900
13901 /******************* Bit definition for TIM_CNT register ********************/
13902 #define TIM_CNT_CNT_Pos (0U)
13903 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
13904 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
13905
13906 /******************* Bit definition for TIM_PSC register ********************/
13907 #define TIM_PSC_PSC_Pos (0U)
13908 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
13909 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
13910
13911 /******************* Bit definition for TIM_ARR register ********************/
13912 #define TIM_ARR_ARR_Pos (0U)
13913 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
13914 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
13915
13916 /******************* Bit definition for TIM_RCR register ********************/
13917 #define TIM_RCR_REP_Pos (0U)
13918 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
13919 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
13920
13921 /******************* Bit definition for TIM_CCR1 register *******************/
13922 #define TIM_CCR1_CCR1_Pos (0U)
13923 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
13924 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
13925
13926 /******************* Bit definition for TIM_CCR2 register *******************/
13927 #define TIM_CCR2_CCR2_Pos (0U)
13928 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
13929 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
13930
13931 /******************* Bit definition for TIM_CCR3 register *******************/
13932 #define TIM_CCR3_CCR3_Pos (0U)
13933 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
13934 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
13935
13936 /******************* Bit definition for TIM_CCR4 register *******************/
13937 #define TIM_CCR4_CCR4_Pos (0U)
13938 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
13939 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
13940
13941 /******************* Bit definition for TIM_BDTR register *******************/
13942 #define TIM_BDTR_DTG_Pos (0U)
13943 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
13944 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
13945 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
13946 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
13947 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
13948 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
13949 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
13950 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
13951 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
13952 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
13953
13954 #define TIM_BDTR_LOCK_Pos (8U)
13955 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
13956 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
13957 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
13958 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
13959
13960 #define TIM_BDTR_OSSI_Pos (10U)
13961 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
13962 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
13963 #define TIM_BDTR_OSSR_Pos (11U)
13964 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
13965 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
13966 #define TIM_BDTR_BKE_Pos (12U)
13967 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
13968 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
13969 #define TIM_BDTR_BKP_Pos (13U)
13970 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
13971 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
13972 #define TIM_BDTR_AOE_Pos (14U)
13973 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
13974 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
13975 #define TIM_BDTR_MOE_Pos (15U)
13976 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
13977 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
13978
13979 /******************* Bit definition for TIM_DCR register ********************/
13980 #define TIM_DCR_DBA_Pos (0U)
13981 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
13982 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
13983 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
13984 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
13985 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
13986 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
13987 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
13988
13989 #define TIM_DCR_DBL_Pos (8U)
13990 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
13991 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
13992 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
13993 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
13994 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
13995 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
13996 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
13997
13998 /******************* Bit definition for TIM_DMAR register *******************/
13999 #define TIM_DMAR_DMAB_Pos (0U)
14000 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
14001 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
14002
14003 /******************* Bit definition for TIM_OR register *********************/
14004 #define TIM_OR_TI1_RMP_Pos (0U)
14005 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
14006 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
14007 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
14008 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
14009
14010 #define TIM_OR_TI4_RMP_Pos (6U)
14011 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
14012 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
14013 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
14014 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
14015 #define TIM_OR_ITR1_RMP_Pos (10U)
14016 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
14017 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
14018 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
14019 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
14020
14021
14022 /******************************************************************************/
14023 /* */
14024 /* Universal Synchronous Asynchronous Receiver Transmitter */
14025 /* */
14026 /******************************************************************************/
14027 /******************* Bit definition for USART_SR register *******************/
14028 #define USART_SR_PE_Pos (0U)
14029 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
14030 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
14031 #define USART_SR_FE_Pos (1U)
14032 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
14033 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
14034 #define USART_SR_NE_Pos (2U)
14035 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
14036 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
14037 #define USART_SR_ORE_Pos (3U)
14038 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
14039 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
14040 #define USART_SR_IDLE_Pos (4U)
14041 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
14042 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
14043 #define USART_SR_RXNE_Pos (5U)
14044 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
14045 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
14046 #define USART_SR_TC_Pos (6U)
14047 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
14048 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
14049 #define USART_SR_TXE_Pos (7U)
14050 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
14051 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
14052 #define USART_SR_LBD_Pos (8U)
14053 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
14054 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
14055 #define USART_SR_CTS_Pos (9U)
14056 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
14057 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
14058
14059 /******************* Bit definition for USART_DR register *******************/
14060 #define USART_DR_DR_Pos (0U)
14061 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
14062 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
14063
14064 /****************** Bit definition for USART_BRR register *******************/
14065 #define USART_BRR_DIV_Fraction_Pos (0U)
14066 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
14067 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
14068 #define USART_BRR_DIV_Mantissa_Pos (4U)
14069 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
14070 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
14071
14072 /****************** Bit definition for USART_CR1 register *******************/
14073 #define USART_CR1_SBK_Pos (0U)
14074 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
14075 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
14076 #define USART_CR1_RWU_Pos (1U)
14077 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
14078 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
14079 #define USART_CR1_RE_Pos (2U)
14080 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
14081 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
14082 #define USART_CR1_TE_Pos (3U)
14083 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
14084 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
14085 #define USART_CR1_IDLEIE_Pos (4U)
14086 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
14087 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
14088 #define USART_CR1_RXNEIE_Pos (5U)
14089 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
14090 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
14091 #define USART_CR1_TCIE_Pos (6U)
14092 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
14093 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
14094 #define USART_CR1_TXEIE_Pos (7U)
14095 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
14096 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
14097 #define USART_CR1_PEIE_Pos (8U)
14098 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
14099 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
14100 #define USART_CR1_PS_Pos (9U)
14101 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
14102 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
14103 #define USART_CR1_PCE_Pos (10U)
14104 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
14105 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
14106 #define USART_CR1_WAKE_Pos (11U)
14107 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
14108 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
14109 #define USART_CR1_M_Pos (12U)
14110 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
14111 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
14112 #define USART_CR1_UE_Pos (13U)
14113 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
14114 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
14115 #define USART_CR1_OVER8_Pos (15U)
14116 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
14117 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
14118
14119 /****************** Bit definition for USART_CR2 register *******************/
14120 #define USART_CR2_ADD_Pos (0U)
14121 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
14122 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
14123 #define USART_CR2_LBDL_Pos (5U)
14124 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
14125 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
14126 #define USART_CR2_LBDIE_Pos (6U)
14127 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
14128 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
14129 #define USART_CR2_LBCL_Pos (8U)
14130 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
14131 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
14132 #define USART_CR2_CPHA_Pos (9U)
14133 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
14134 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
14135 #define USART_CR2_CPOL_Pos (10U)
14136 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
14137 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
14138 #define USART_CR2_CLKEN_Pos (11U)
14139 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
14140 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
14141
14142 #define USART_CR2_STOP_Pos (12U)
14143 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
14144 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
14145 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
14146 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
14147
14148 #define USART_CR2_LINEN_Pos (14U)
14149 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
14150 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
14151
14152 /****************** Bit definition for USART_CR3 register *******************/
14153 #define USART_CR3_EIE_Pos (0U)
14154 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
14155 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
14156 #define USART_CR3_IREN_Pos (1U)
14157 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
14158 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
14159 #define USART_CR3_IRLP_Pos (2U)
14160 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
14161 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
14162 #define USART_CR3_HDSEL_Pos (3U)
14163 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
14164 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
14165 #define USART_CR3_NACK_Pos (4U)
14166 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
14167 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
14168 #define USART_CR3_SCEN_Pos (5U)
14169 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
14170 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
14171 #define USART_CR3_DMAR_Pos (6U)
14172 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
14173 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
14174 #define USART_CR3_DMAT_Pos (7U)
14175 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
14176 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
14177 #define USART_CR3_RTSE_Pos (8U)
14178 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
14179 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
14180 #define USART_CR3_CTSE_Pos (9U)
14181 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
14182 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
14183 #define USART_CR3_CTSIE_Pos (10U)
14184 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
14185 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
14186 #define USART_CR3_ONEBIT_Pos (11U)
14187 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
14188 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
14189
14190 /****************** Bit definition for USART_GTPR register ******************/
14191 #define USART_GTPR_PSC_Pos (0U)
14192 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
14193 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
14194 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
14195 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
14196 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
14197 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
14198 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
14199 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
14200 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
14201 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
14202
14203 #define USART_GTPR_GT_Pos (8U)
14204 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
14205 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
14206
14207 /******************************************************************************/
14208 /* */
14209 /* Window WATCHDOG */
14210 /* */
14211 /******************************************************************************/
14212 /******************* Bit definition for WWDG_CR register ********************/
14213 #define WWDG_CR_T_Pos (0U)
14214 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
14215 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
14216 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
14217 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
14218 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
14219 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
14220 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
14221 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
14222 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
14223 /* Legacy defines */
14224 #define WWDG_CR_T0 WWDG_CR_T_0
14225 #define WWDG_CR_T1 WWDG_CR_T_1
14226 #define WWDG_CR_T2 WWDG_CR_T_2
14227 #define WWDG_CR_T3 WWDG_CR_T_3
14228 #define WWDG_CR_T4 WWDG_CR_T_4
14229 #define WWDG_CR_T5 WWDG_CR_T_5
14230 #define WWDG_CR_T6 WWDG_CR_T_6
14231
14232 #define WWDG_CR_WDGA_Pos (7U)
14233 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
14234 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
14235
14236 /******************* Bit definition for WWDG_CFR register *******************/
14237 #define WWDG_CFR_W_Pos (0U)
14238 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
14239 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
14240 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
14241 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
14242 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
14243 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
14244 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
14245 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
14246 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
14247 /* Legacy defines */
14248 #define WWDG_CFR_W0 WWDG_CFR_W_0
14249 #define WWDG_CFR_W1 WWDG_CFR_W_1
14250 #define WWDG_CFR_W2 WWDG_CFR_W_2
14251 #define WWDG_CFR_W3 WWDG_CFR_W_3
14252 #define WWDG_CFR_W4 WWDG_CFR_W_4
14253 #define WWDG_CFR_W5 WWDG_CFR_W_5
14254 #define WWDG_CFR_W6 WWDG_CFR_W_6
14255
14256 #define WWDG_CFR_WDGTB_Pos (7U)
14257 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
14258 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
14259 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
14260 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
14261 /* Legacy defines */
14262 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
14263 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
14264
14265 #define WWDG_CFR_EWI_Pos (9U)
14266 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
14267 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
14268
14269 /******************* Bit definition for WWDG_SR register ********************/
14270 #define WWDG_SR_EWIF_Pos (0U)
14271 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
14272 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
14273
14274
14275 /******************************************************************************/
14276 /* */
14277 /* DBG */
14278 /* */
14279 /******************************************************************************/
14280 /******************** Bit definition for DBGMCU_IDCODE register *************/
14281 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
14282 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
14283 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
14284 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
14285 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
14286 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
14287
14288 /******************** Bit definition for DBGMCU_CR register *****************/
14289 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
14290 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
14291 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
14292 #define DBGMCU_CR_DBG_STOP_Pos (1U)
14293 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
14294 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
14295 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
14296 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
14297 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
14298 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
14299 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
14300 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
14301
14302 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
14303 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
14304 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
14305 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
14306 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
14307
14308 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
14309 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
14310 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
14311 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
14312 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
14313 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
14314 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
14315 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
14316 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
14317 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
14318 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
14319 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
14320 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
14321 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
14322 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
14323 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
14324 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
14325 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
14326 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
14327 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
14328 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
14329 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
14330 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
14331 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
14332 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
14333 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
14334 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
14335 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
14336 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
14337 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
14338 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
14339 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
14340 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
14341 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
14342 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
14343 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
14344 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
14345 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
14346 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
14347 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
14348 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
14349 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
14350 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
14351 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
14352 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
14353 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
14354 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
14355 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
14356 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
14357 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
14358 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
14359 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
14360 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
14361 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
14362
14363 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
14364 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
14365 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
14366 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
14367 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
14368 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
14369 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
14370 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
14371 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
14372 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
14373 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
14374 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
14375 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14376 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
14377 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
14378 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14379
14380 /******************************************************************************/
14381 /* */
14382 /* Ethernet MAC Registers bits definitions */
14383 /* */
14384 /******************************************************************************/
14385 /* Bit definition for Ethernet MAC Control Register register */
14386 #define ETH_MACCR_WD_Pos (23U)
14387 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
14388 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
14389 #define ETH_MACCR_JD_Pos (22U)
14390 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
14391 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
14392 #define ETH_MACCR_IFG_Pos (17U)
14393 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
14394 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
14395 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
14396 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
14397 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
14398 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
14399 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
14400 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
14401 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
14402 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
14403 #define ETH_MACCR_CSD_Pos (16U)
14404 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
14405 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
14406 #define ETH_MACCR_FES_Pos (14U)
14407 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
14408 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
14409 #define ETH_MACCR_ROD_Pos (13U)
14410 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
14411 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
14412 #define ETH_MACCR_LM_Pos (12U)
14413 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
14414 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
14415 #define ETH_MACCR_DM_Pos (11U)
14416 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
14417 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
14418 #define ETH_MACCR_IPCO_Pos (10U)
14419 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
14420 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
14421 #define ETH_MACCR_RD_Pos (9U)
14422 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
14423 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
14424 #define ETH_MACCR_APCS_Pos (7U)
14425 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
14426 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
14427 #define ETH_MACCR_BL_Pos (5U)
14428 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
14429 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
14430 a transmission attempt during retries after a collision: 0 =< r <2^k */
14431 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
14432 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
14433 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
14434 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
14435 #define ETH_MACCR_DC_Pos (4U)
14436 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
14437 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
14438 #define ETH_MACCR_TE_Pos (3U)
14439 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
14440 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
14441 #define ETH_MACCR_RE_Pos (2U)
14442 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
14443 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
14444
14445 /* Bit definition for Ethernet MAC Frame Filter Register */
14446 #define ETH_MACFFR_RA_Pos (31U)
14447 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
14448 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
14449 #define ETH_MACFFR_HPF_Pos (10U)
14450 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
14451 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
14452 #define ETH_MACFFR_SAF_Pos (9U)
14453 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
14454 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
14455 #define ETH_MACFFR_SAIF_Pos (8U)
14456 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
14457 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
14458 #define ETH_MACFFR_PCF_Pos (6U)
14459 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
14460 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
14461 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
14462 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
14463 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
14464 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
14465 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
14466 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
14467 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
14468 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
14469 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
14470 #define ETH_MACFFR_BFD_Pos (5U)
14471 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
14472 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
14473 #define ETH_MACFFR_PAM_Pos (4U)
14474 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
14475 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
14476 #define ETH_MACFFR_DAIF_Pos (3U)
14477 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
14478 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
14479 #define ETH_MACFFR_HM_Pos (2U)
14480 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
14481 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
14482 #define ETH_MACFFR_HU_Pos (1U)
14483 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
14484 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
14485 #define ETH_MACFFR_PM_Pos (0U)
14486 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
14487 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
14488
14489 /* Bit definition for Ethernet MAC Hash Table High Register */
14490 #define ETH_MACHTHR_HTH_Pos (0U)
14491 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
14492 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
14493
14494 /* Bit definition for Ethernet MAC Hash Table Low Register */
14495 #define ETH_MACHTLR_HTL_Pos (0U)
14496 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
14497 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
14498
14499 /* Bit definition for Ethernet MAC MII Address Register */
14500 #define ETH_MACMIIAR_PA_Pos (11U)
14501 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
14502 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
14503 #define ETH_MACMIIAR_MR_Pos (6U)
14504 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
14505 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
14506 #define ETH_MACMIIAR_CR_Pos (2U)
14507 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
14508 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
14509 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
14510 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
14511 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
14512 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
14513 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
14514 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
14515 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
14516 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
14517 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
14518 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
14519 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
14520 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
14521 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
14522 #define ETH_MACMIIAR_MW_Pos (1U)
14523 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
14524 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
14525 #define ETH_MACMIIAR_MB_Pos (0U)
14526 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
14527 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
14528
14529 /* Bit definition for Ethernet MAC MII Data Register */
14530 #define ETH_MACMIIDR_MD_Pos (0U)
14531 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
14532 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
14533
14534 /* Bit definition for Ethernet MAC Flow Control Register */
14535 #define ETH_MACFCR_PT_Pos (16U)
14536 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
14537 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
14538 #define ETH_MACFCR_ZQPD_Pos (7U)
14539 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
14540 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
14541 #define ETH_MACFCR_PLT_Pos (4U)
14542 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
14543 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
14544 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
14545 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
14546 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
14547 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
14548 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
14549 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
14550 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
14551 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
14552 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
14553 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
14554 #define ETH_MACFCR_UPFD_Pos (3U)
14555 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
14556 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
14557 #define ETH_MACFCR_RFCE_Pos (2U)
14558 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
14559 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
14560 #define ETH_MACFCR_TFCE_Pos (1U)
14561 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
14562 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
14563 #define ETH_MACFCR_FCBBPA_Pos (0U)
14564 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
14565 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
14566
14567 /* Bit definition for Ethernet MAC VLAN Tag Register */
14568 #define ETH_MACVLANTR_VLANTC_Pos (16U)
14569 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
14570 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
14571 #define ETH_MACVLANTR_VLANTI_Pos (0U)
14572 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
14573 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
14574
14575 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
14576 #define ETH_MACRWUFFR_D_Pos (0U)
14577 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
14578 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
14579 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
14580 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
14581 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
14582 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
14583 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
14584 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
14585 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
14586 RSVD - Filter1 Command - RSVD - Filter0 Command
14587 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
14588 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
14589 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
14590
14591 /* Bit definition for Ethernet MAC PMT Control and Status Register */
14592 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
14593 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
14594 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
14595 #define ETH_MACPMTCSR_GU_Pos (9U)
14596 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
14597 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
14598 #define ETH_MACPMTCSR_WFR_Pos (6U)
14599 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
14600 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
14601 #define ETH_MACPMTCSR_MPR_Pos (5U)
14602 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
14603 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
14604 #define ETH_MACPMTCSR_WFE_Pos (2U)
14605 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
14606 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
14607 #define ETH_MACPMTCSR_MPE_Pos (1U)
14608 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
14609 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
14610 #define ETH_MACPMTCSR_PD_Pos (0U)
14611 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
14612 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
14613
14614 /* Bit definition for Ethernet MAC debug Register */
14615 #define ETH_MACDBGR_TFF_Pos (25U)
14616 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
14617 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
14618 #define ETH_MACDBGR_TFNE_Pos (24U)
14619 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
14620 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
14621 #define ETH_MACDBGR_TFWA_Pos (22U)
14622 #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
14623 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
14624 #define ETH_MACDBGR_TFRS_Pos (20U)
14625 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
14626 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
14627 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
14628 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
14629 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
14630 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
14631 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
14632 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
14633 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
14634 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
14635 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
14636 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
14637 #define ETH_MACDBGR_MTP_Pos (19U)
14638 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
14639 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
14640 #define ETH_MACDBGR_MTFCS_Pos (17U)
14641 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
14642 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
14643 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
14644 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
14645 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
14646 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
14647 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
14648 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
14649 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
14650 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
14651 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
14652 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
14653 #define ETH_MACDBGR_MMTEA_Pos (16U)
14654 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
14655 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
14656 #define ETH_MACDBGR_RFFL_Pos (8U)
14657 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
14658 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
14659 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
14660 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
14661 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
14662 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
14663 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
14664 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
14665 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
14666 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
14667 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
14668 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
14669 #define ETH_MACDBGR_RFRCS_Pos (5U)
14670 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
14671 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
14672 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
14673 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
14674 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
14675 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
14676 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
14677 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
14678 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
14679 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
14680 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
14681 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
14682 #define ETH_MACDBGR_RFWRA_Pos (4U)
14683 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
14684 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
14685 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
14686 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
14687 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
14688 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
14689 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
14690 #define ETH_MACDBGR_MMRPEA_Pos (0U)
14691 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
14692 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
14693
14694 /* Bit definition for Ethernet MAC Status Register */
14695 #define ETH_MACSR_TSTS_Pos (9U)
14696 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
14697 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
14698 #define ETH_MACSR_MMCTS_Pos (6U)
14699 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
14700 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
14701 #define ETH_MACSR_MMMCRS_Pos (5U)
14702 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
14703 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
14704 #define ETH_MACSR_MMCS_Pos (4U)
14705 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
14706 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
14707 #define ETH_MACSR_PMTS_Pos (3U)
14708 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
14709 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
14710
14711 /* Bit definition for Ethernet MAC Interrupt Mask Register */
14712 #define ETH_MACIMR_TSTIM_Pos (9U)
14713 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
14714 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
14715 #define ETH_MACIMR_PMTIM_Pos (3U)
14716 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
14717 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
14718
14719 /* Bit definition for Ethernet MAC Address0 High Register */
14720 #define ETH_MACA0HR_MACA0H_Pos (0U)
14721 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
14722 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
14723
14724 /* Bit definition for Ethernet MAC Address0 Low Register */
14725 #define ETH_MACA0LR_MACA0L_Pos (0U)
14726 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
14727 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
14728
14729 /* Bit definition for Ethernet MAC Address1 High Register */
14730 #define ETH_MACA1HR_AE_Pos (31U)
14731 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
14732 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
14733 #define ETH_MACA1HR_SA_Pos (30U)
14734 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
14735 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
14736 #define ETH_MACA1HR_MBC_Pos (24U)
14737 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
14738 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
14739 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14740 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14741 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14742 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14743 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14744 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
14745 #define ETH_MACA1HR_MACA1H_Pos (0U)
14746 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
14747 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
14748
14749 /* Bit definition for Ethernet MAC Address1 Low Register */
14750 #define ETH_MACA1LR_MACA1L_Pos (0U)
14751 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
14752 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
14753
14754 /* Bit definition for Ethernet MAC Address2 High Register */
14755 #define ETH_MACA2HR_AE_Pos (31U)
14756 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
14757 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
14758 #define ETH_MACA2HR_SA_Pos (30U)
14759 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
14760 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
14761 #define ETH_MACA2HR_MBC_Pos (24U)
14762 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
14763 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
14764 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14765 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14766 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14767 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14768 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14769 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
14770 #define ETH_MACA2HR_MACA2H_Pos (0U)
14771 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
14772 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
14773
14774 /* Bit definition for Ethernet MAC Address2 Low Register */
14775 #define ETH_MACA2LR_MACA2L_Pos (0U)
14776 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
14777 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
14778
14779 /* Bit definition for Ethernet MAC Address3 High Register */
14780 #define ETH_MACA3HR_AE_Pos (31U)
14781 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
14782 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
14783 #define ETH_MACA3HR_SA_Pos (30U)
14784 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
14785 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
14786 #define ETH_MACA3HR_MBC_Pos (24U)
14787 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
14788 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
14789 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14790 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14791 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14792 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14793 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14794 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
14795 #define ETH_MACA3HR_MACA3H_Pos (0U)
14796 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
14797 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
14798
14799 /* Bit definition for Ethernet MAC Address3 Low Register */
14800 #define ETH_MACA3LR_MACA3L_Pos (0U)
14801 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
14802 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
14803
14804 /******************************************************************************/
14805 /* Ethernet MMC Registers bits definition */
14806 /******************************************************************************/
14807
14808 /* Bit definition for Ethernet MMC Contol Register */
14809 #define ETH_MMCCR_MCFHP_Pos (5U)
14810 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
14811 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
14812 #define ETH_MMCCR_MCP_Pos (4U)
14813 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
14814 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
14815 #define ETH_MMCCR_MCF_Pos (3U)
14816 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
14817 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
14818 #define ETH_MMCCR_ROR_Pos (2U)
14819 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
14820 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
14821 #define ETH_MMCCR_CSR_Pos (1U)
14822 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
14823 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
14824 #define ETH_MMCCR_CR_Pos (0U)
14825 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
14826 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
14827
14828 /* Bit definition for Ethernet MMC Receive Interrupt Register */
14829 #define ETH_MMCRIR_RGUFS_Pos (17U)
14830 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
14831 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
14832 #define ETH_MMCRIR_RFAES_Pos (6U)
14833 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
14834 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
14835 #define ETH_MMCRIR_RFCES_Pos (5U)
14836 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
14837 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
14838
14839 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
14840 #define ETH_MMCTIR_TGFS_Pos (21U)
14841 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
14842 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
14843 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
14844 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
14845 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
14846 #define ETH_MMCTIR_TGFSCS_Pos (14U)
14847 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
14848 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
14849
14850 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
14851 #define ETH_MMCRIMR_RGUFM_Pos (17U)
14852 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
14853 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
14854 #define ETH_MMCRIMR_RFAEM_Pos (6U)
14855 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
14856 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
14857 #define ETH_MMCRIMR_RFCEM_Pos (5U)
14858 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
14859 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
14860
14861 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
14862 #define ETH_MMCTIMR_TGFM_Pos (21U)
14863 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
14864 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
14865 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
14866 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
14867 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
14868 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
14869 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
14870 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
14871
14872 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
14873 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
14874 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
14875 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
14876
14877 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
14878 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
14879 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
14880 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
14881
14882 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
14883 #define ETH_MMCTGFCR_TGFC_Pos (0U)
14884 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
14885 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
14886
14887 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
14888 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
14889 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
14890 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
14891
14892 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
14893 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
14894 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
14895 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
14896
14897 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
14898 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
14899 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
14900 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
14901
14902 /******************************************************************************/
14903 /* Ethernet PTP Registers bits definition */
14904 /******************************************************************************/
14905
14906 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
14907 #define ETH_PTPTSCR_TSCNT_Pos (16U)
14908 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
14909 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
14910 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
14911 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
14912 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
14913 #define ETH_PTPTSSR_TSSEME_Pos (14U)
14914 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
14915 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
14916 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
14917 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
14918 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
14919 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
14920 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
14921 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
14922 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
14923 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
14924 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
14925 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
14926 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
14927 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
14928 #define ETH_PTPTSSR_TSSSR_Pos (9U)
14929 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
14930 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
14931 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
14932 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
14933 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
14934
14935 #define ETH_PTPTSCR_TSARU_Pos (5U)
14936 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
14937 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
14938 #define ETH_PTPTSCR_TSITE_Pos (4U)
14939 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
14940 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
14941 #define ETH_PTPTSCR_TSSTU_Pos (3U)
14942 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
14943 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
14944 #define ETH_PTPTSCR_TSSTI_Pos (2U)
14945 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
14946 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
14947 #define ETH_PTPTSCR_TSFCU_Pos (1U)
14948 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
14949 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
14950 #define ETH_PTPTSCR_TSE_Pos (0U)
14951 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
14952 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
14953
14954 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
14955 #define ETH_PTPSSIR_STSSI_Pos (0U)
14956 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
14957 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
14958
14959 /* Bit definition for Ethernet PTP Time Stamp High Register */
14960 #define ETH_PTPTSHR_STS_Pos (0U)
14961 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
14962 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
14963
14964 /* Bit definition for Ethernet PTP Time Stamp Low Register */
14965 #define ETH_PTPTSLR_STPNS_Pos (31U)
14966 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
14967 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
14968 #define ETH_PTPTSLR_STSS_Pos (0U)
14969 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
14970 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
14971
14972 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
14973 #define ETH_PTPTSHUR_TSUS_Pos (0U)
14974 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
14975 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
14976
14977 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
14978 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
14979 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
14980 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
14981 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
14982 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
14983 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
14984
14985 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
14986 #define ETH_PTPTSAR_TSA_Pos (0U)
14987 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
14988 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
14989
14990 /* Bit definition for Ethernet PTP Target Time High Register */
14991 #define ETH_PTPTTHR_TTSH_Pos (0U)
14992 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
14993 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
14994
14995 /* Bit definition for Ethernet PTP Target Time Low Register */
14996 #define ETH_PTPTTLR_TTSL_Pos (0U)
14997 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
14998 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
14999
15000 /* Bit definition for Ethernet PTP Time Stamp Status Register */
15001 #define ETH_PTPTSSR_TSTTR_Pos (5U)
15002 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
15003 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
15004 #define ETH_PTPTSSR_TSSO_Pos (4U)
15005 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
15006 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
15007
15008 /******************************************************************************/
15009 /* Ethernet DMA Registers bits definition */
15010 /******************************************************************************/
15011
15012 /* Bit definition for Ethernet DMA Bus Mode Register */
15013 #define ETH_DMABMR_AAB_Pos (25U)
15014 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
15015 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
15016 #define ETH_DMABMR_FPM_Pos (24U)
15017 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
15018 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
15019 #define ETH_DMABMR_USP_Pos (23U)
15020 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
15021 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
15022 #define ETH_DMABMR_RDP_Pos (17U)
15023 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
15024 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
15025 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
15026 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
15027 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15028 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15029 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15030 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15031 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15032 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15033 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15034 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15035 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
15036 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
15037 #define ETH_DMABMR_FB_Pos (16U)
15038 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
15039 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
15040 #define ETH_DMABMR_RTPR_Pos (14U)
15041 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
15042 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
15043 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
15044 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
15045 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
15046 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
15047 #define ETH_DMABMR_PBL_Pos (8U)
15048 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
15049 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
15050 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
15051 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
15052 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15053 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15054 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15055 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15056 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15057 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15058 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15059 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15060 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
15061 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
15062 #define ETH_DMABMR_EDE_Pos (7U)
15063 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
15064 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
15065 #define ETH_DMABMR_DSL_Pos (2U)
15066 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
15067 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
15068 #define ETH_DMABMR_DA_Pos (1U)
15069 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
15070 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
15071 #define ETH_DMABMR_SR_Pos (0U)
15072 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
15073 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
15074
15075 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
15076 #define ETH_DMATPDR_TPD_Pos (0U)
15077 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
15078 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
15079
15080 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
15081 #define ETH_DMARPDR_RPD_Pos (0U)
15082 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
15083 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
15084
15085 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
15086 #define ETH_DMARDLAR_SRL_Pos (0U)
15087 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
15088 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
15089
15090 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
15091 #define ETH_DMATDLAR_STL_Pos (0U)
15092 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
15093 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
15094
15095 /* Bit definition for Ethernet DMA Status Register */
15096 #define ETH_DMASR_TSTS_Pos (29U)
15097 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
15098 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
15099 #define ETH_DMASR_PMTS_Pos (28U)
15100 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
15101 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
15102 #define ETH_DMASR_MMCS_Pos (27U)
15103 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
15104 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
15105 #define ETH_DMASR_EBS_Pos (23U)
15106 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
15107 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
15108 /* combination with EBS[2:0] for GetFlagStatus function */
15109 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
15110 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
15111 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
15112 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
15113 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
15114 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
15115 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
15116 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
15117 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
15118 #define ETH_DMASR_TPS_Pos (20U)
15119 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
15120 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
15121 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
15122 #define ETH_DMASR_TPS_Fetching_Pos (20U)
15123 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
15124 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
15125 #define ETH_DMASR_TPS_Waiting_Pos (21U)
15126 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
15127 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
15128 #define ETH_DMASR_TPS_Reading_Pos (20U)
15129 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
15130 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
15131 #define ETH_DMASR_TPS_Suspended_Pos (21U)
15132 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
15133 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
15134 #define ETH_DMASR_TPS_Closing_Pos (20U)
15135 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
15136 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
15137 #define ETH_DMASR_RPS_Pos (17U)
15138 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
15139 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
15140 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
15141 #define ETH_DMASR_RPS_Fetching_Pos (17U)
15142 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
15143 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
15144 #define ETH_DMASR_RPS_Waiting_Pos (17U)
15145 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
15146 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
15147 #define ETH_DMASR_RPS_Suspended_Pos (19U)
15148 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
15149 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
15150 #define ETH_DMASR_RPS_Closing_Pos (17U)
15151 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
15152 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
15153 #define ETH_DMASR_RPS_Queuing_Pos (17U)
15154 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
15155 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
15156 #define ETH_DMASR_NIS_Pos (16U)
15157 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
15158 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
15159 #define ETH_DMASR_AIS_Pos (15U)
15160 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
15161 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
15162 #define ETH_DMASR_ERS_Pos (14U)
15163 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
15164 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
15165 #define ETH_DMASR_FBES_Pos (13U)
15166 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
15167 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
15168 #define ETH_DMASR_ETS_Pos (10U)
15169 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
15170 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
15171 #define ETH_DMASR_RWTS_Pos (9U)
15172 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
15173 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
15174 #define ETH_DMASR_RPSS_Pos (8U)
15175 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
15176 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
15177 #define ETH_DMASR_RBUS_Pos (7U)
15178 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
15179 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
15180 #define ETH_DMASR_RS_Pos (6U)
15181 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
15182 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
15183 #define ETH_DMASR_TUS_Pos (5U)
15184 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
15185 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
15186 #define ETH_DMASR_ROS_Pos (4U)
15187 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
15188 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
15189 #define ETH_DMASR_TJTS_Pos (3U)
15190 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
15191 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
15192 #define ETH_DMASR_TBUS_Pos (2U)
15193 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
15194 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
15195 #define ETH_DMASR_TPSS_Pos (1U)
15196 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
15197 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
15198 #define ETH_DMASR_TS_Pos (0U)
15199 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
15200 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
15201
15202 /* Bit definition for Ethernet DMA Operation Mode Register */
15203 #define ETH_DMAOMR_DTCEFD_Pos (26U)
15204 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
15205 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
15206 #define ETH_DMAOMR_RSF_Pos (25U)
15207 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
15208 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
15209 #define ETH_DMAOMR_DFRF_Pos (24U)
15210 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
15211 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
15212 #define ETH_DMAOMR_TSF_Pos (21U)
15213 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
15214 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
15215 #define ETH_DMAOMR_FTF_Pos (20U)
15216 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
15217 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
15218 #define ETH_DMAOMR_TTC_Pos (14U)
15219 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
15220 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
15221 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
15222 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
15223 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
15224 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
15225 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
15226 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
15227 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
15228 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
15229 #define ETH_DMAOMR_ST_Pos (13U)
15230 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
15231 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
15232 #define ETH_DMAOMR_FEF_Pos (7U)
15233 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
15234 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
15235 #define ETH_DMAOMR_FUGF_Pos (6U)
15236 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
15237 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
15238 #define ETH_DMAOMR_RTC_Pos (3U)
15239 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
15240 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
15241 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
15242 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
15243 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
15244 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
15245 #define ETH_DMAOMR_OSF_Pos (2U)
15246 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
15247 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
15248 #define ETH_DMAOMR_SR_Pos (1U)
15249 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
15250 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
15251
15252 /* Bit definition for Ethernet DMA Interrupt Enable Register */
15253 #define ETH_DMAIER_NISE_Pos (16U)
15254 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
15255 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
15256 #define ETH_DMAIER_AISE_Pos (15U)
15257 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
15258 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
15259 #define ETH_DMAIER_ERIE_Pos (14U)
15260 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
15261 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
15262 #define ETH_DMAIER_FBEIE_Pos (13U)
15263 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
15264 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
15265 #define ETH_DMAIER_ETIE_Pos (10U)
15266 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
15267 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
15268 #define ETH_DMAIER_RWTIE_Pos (9U)
15269 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
15270 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
15271 #define ETH_DMAIER_RPSIE_Pos (8U)
15272 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
15273 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
15274 #define ETH_DMAIER_RBUIE_Pos (7U)
15275 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
15276 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
15277 #define ETH_DMAIER_RIE_Pos (6U)
15278 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
15279 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
15280 #define ETH_DMAIER_TUIE_Pos (5U)
15281 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
15282 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
15283 #define ETH_DMAIER_ROIE_Pos (4U)
15284 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
15285 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
15286 #define ETH_DMAIER_TJTIE_Pos (3U)
15287 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
15288 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
15289 #define ETH_DMAIER_TBUIE_Pos (2U)
15290 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
15291 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
15292 #define ETH_DMAIER_TPSIE_Pos (1U)
15293 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
15294 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
15295 #define ETH_DMAIER_TIE_Pos (0U)
15296 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
15297 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
15298
15299 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
15300 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
15301 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
15302 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
15303 #define ETH_DMAMFBOCR_MFA_Pos (17U)
15304 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
15305 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
15306 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
15307 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
15308 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
15309 #define ETH_DMAMFBOCR_MFC_Pos (0U)
15310 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
15311 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
15312
15313 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
15314 #define ETH_DMACHTDR_HTDAP_Pos (0U)
15315 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
15316 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
15317
15318 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
15319 #define ETH_DMACHRDR_HRDAP_Pos (0U)
15320 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
15321 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
15322
15323 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
15324 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
15325 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
15326 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
15327
15328 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
15329 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
15330 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
15331 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
15332
15333 /******************************************************************************/
15334 /* */
15335 /* USB_OTG */
15336 /* */
15337 /******************************************************************************/
15338 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
15339 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
15340 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
15341 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
15342 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
15343 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
15344 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
15345 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
15346 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
15347 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
15348 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
15349 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
15350 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
15351 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
15352 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
15353 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
15354 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
15355 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
15356 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
15357 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
15358 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
15359 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
15360 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
15361 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
15362 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
15363 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
15364 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
15365 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
15366 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
15367 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
15368 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
15369
15370 /******************** Bit definition forUSB_OTG_HCFG register ********************/
15371
15372 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
15373 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
15374 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
15375 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
15376 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
15377 #define USB_OTG_HCFG_FSLSS_Pos (2U)
15378 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
15379 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
15380
15381 /******************** Bit definition for USB_OTG_DCFG register ********************/
15382
15383 #define USB_OTG_DCFG_DSPD_Pos (0U)
15384 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
15385 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
15386 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
15387 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
15388 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
15389 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
15390 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
15391
15392 #define USB_OTG_DCFG_DAD_Pos (4U)
15393 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
15394 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
15395 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
15396 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
15397 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
15398 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
15399 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
15400 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
15401 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
15402
15403 #define USB_OTG_DCFG_PFIVL_Pos (11U)
15404 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
15405 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
15406 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
15407 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
15408
15409 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
15410 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
15411 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
15412 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
15413 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
15414
15415 /******************** Bit definition for USB_OTG_PCGCR register ********************/
15416 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
15417 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
15418 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
15419 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
15420 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
15421 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
15422 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
15423 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
15424 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
15425
15426 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
15427 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
15428 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
15429 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
15430 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
15431 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
15432 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
15433 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
15434 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
15435 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
15436 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
15437 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
15438 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
15439 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
15440 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
15441 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
15442 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
15443 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
15444 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
15445
15446 /******************** Bit definition for USB_OTG_DCTL register ********************/
15447 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
15448 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
15449 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
15450 #define USB_OTG_DCTL_SDIS_Pos (1U)
15451 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
15452 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
15453 #define USB_OTG_DCTL_GINSTS_Pos (2U)
15454 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
15455 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
15456 #define USB_OTG_DCTL_GONSTS_Pos (3U)
15457 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
15458 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
15459
15460 #define USB_OTG_DCTL_TCTL_Pos (4U)
15461 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
15462 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
15463 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
15464 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
15465 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
15466 #define USB_OTG_DCTL_SGINAK_Pos (7U)
15467 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
15468 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
15469 #define USB_OTG_DCTL_CGINAK_Pos (8U)
15470 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
15471 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
15472 #define USB_OTG_DCTL_SGONAK_Pos (9U)
15473 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
15474 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
15475 #define USB_OTG_DCTL_CGONAK_Pos (10U)
15476 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
15477 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
15478 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
15479 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
15480 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
15481
15482 /******************** Bit definition for USB_OTG_HFIR register ********************/
15483 #define USB_OTG_HFIR_FRIVL_Pos (0U)
15484 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
15485 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
15486
15487 /******************** Bit definition for USB_OTG_HFNUM register ********************/
15488 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
15489 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
15490 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
15491 #define USB_OTG_HFNUM_FTREM_Pos (16U)
15492 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
15493 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
15494
15495 /******************** Bit definition for USB_OTG_DSTS register ********************/
15496 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
15497 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
15498 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
15499
15500 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
15501 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
15502 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
15503 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
15504 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
15505 #define USB_OTG_DSTS_EERR_Pos (3U)
15506 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
15507 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
15508 #define USB_OTG_DSTS_FNSOF_Pos (8U)
15509 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
15510 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
15511
15512 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
15513 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
15514 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
15515 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
15516 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
15517 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
15518 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
15519 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
15520 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
15521 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
15522 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
15523 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
15524 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
15525 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
15526 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
15527 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
15528 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
15529 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
15530 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
15531 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
15532 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
15533
15534 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
15535
15536 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
15537 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
15538 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
15539 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
15540 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
15541 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
15542 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
15543 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
15544 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
15545 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
15546 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
15547 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
15548 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
15549 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
15550 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
15551 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
15552 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
15553 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
15554 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
15555 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
15556 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
15557 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
15558 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
15559 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
15560 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
15561 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
15562 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
15563 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
15564 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
15565 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
15566 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
15567 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
15568 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
15569 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
15570 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
15571 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
15572 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
15573 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
15574 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
15575 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
15576 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
15577 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
15578 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
15579 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
15580 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
15581 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
15582 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
15583 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
15584 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
15585 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
15586 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
15587 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
15588 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
15589 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
15590 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
15591 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
15592 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
15593 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
15594 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
15595 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
15596 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
15597
15598 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
15599 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
15600 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
15601 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
15602 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
15603 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
15604 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
15605 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
15606 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
15607 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
15608 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
15609 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
15610 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
15611 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
15612 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
15613 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
15614
15615
15616 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
15617 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
15618 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
15619 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
15620 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
15621 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
15622 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
15623 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
15624 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
15625 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
15626 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
15627 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
15628 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
15629 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
15630
15631 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
15632 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
15633 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
15634 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
15635 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
15636 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
15637 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
15638 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
15639 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
15640 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
15641 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
15642 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
15643 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
15644 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
15645 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
15646 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
15647 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
15648 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
15649 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
15650 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
15651 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
15652 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
15653 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
15654 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
15655 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
15656
15657 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
15658 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
15659 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
15660 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
15661 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
15662 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
15663 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
15664 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
15665 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
15666 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
15667 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
15668 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
15669 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
15670 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
15671 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
15672
15673 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
15674 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
15675 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
15676 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
15677 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
15678 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
15679 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
15680 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
15681 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
15682 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
15683 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
15684
15685 /******************** Bit definition for USB_OTG_HAINT register ********************/
15686 #define USB_OTG_HAINT_HAINT_Pos (0U)
15687 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
15688 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
15689
15690 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
15691 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
15692 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
15693 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
15694 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
15695 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
15696 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
15697 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
15698 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
15699 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
15700 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
15701 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
15702 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
15703 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
15704 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
15705 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
15706 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
15707 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
15708 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
15709 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
15710 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
15711 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
15712
15713 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
15714 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
15715 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
15716 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
15717 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
15718 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
15719 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
15720 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
15721 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
15722 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
15723 #define USB_OTG_GINTSTS_SOF_Pos (3U)
15724 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
15725 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
15726 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
15727 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
15728 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
15729 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
15730 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
15731 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
15732 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
15733 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
15734 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
15735 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
15736 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
15737 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
15738 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
15739 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
15740 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
15741 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
15742 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
15743 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
15744 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
15745 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
15746 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
15747 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
15748 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
15749 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
15750 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
15751 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
15752 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
15753 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
15754 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
15755 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
15756 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
15757 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
15758 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
15759 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
15760 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
15761 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
15762 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
15763 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
15764 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
15765 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
15766 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
15767 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
15768 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
15769 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
15770 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
15771 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
15772 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
15773 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
15774 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
15775 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
15776 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
15777 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
15778 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
15779 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
15780 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
15781 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
15782 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
15783 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
15784 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
15785 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
15786 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
15787 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
15788 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
15789 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
15790 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
15791 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
15792
15793 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
15794 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
15795 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
15796 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
15797 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
15798 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
15799 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
15800 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
15801 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
15802 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
15803 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
15804 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
15805 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
15806 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
15807 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
15808 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
15809 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
15810 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
15811 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
15812 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
15813 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
15814 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
15815 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
15816 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
15817 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
15818 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
15819 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
15820 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
15821 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
15822 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
15823 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
15824 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
15825 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
15826 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
15827 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
15828 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
15829 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
15830 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
15831 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
15832 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
15833 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
15834 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
15835 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
15836 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
15837 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
15838 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
15839 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
15840 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
15841 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
15842 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
15843 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
15844 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
15845 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
15846 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
15847 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
15848 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
15849 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
15850 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
15851 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
15852 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
15853 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
15854 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
15855 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
15856 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
15857 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
15858 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
15859 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
15860 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
15861 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
15862 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
15863 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
15864 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
15865 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
15866 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
15867 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
15868 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
15869 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
15870 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
15871 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
15872
15873 /******************** Bit definition for USB_OTG_DAINT register ********************/
15874 #define USB_OTG_DAINT_IEPINT_Pos (0U)
15875 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
15876 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
15877 #define USB_OTG_DAINT_OEPINT_Pos (16U)
15878 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
15879 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
15880
15881 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
15882 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
15883 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
15884 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
15885
15886 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
15887 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
15888 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
15889 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
15890 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
15891 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
15892 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
15893 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
15894 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
15895 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
15896 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
15897 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
15898 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
15899
15900 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
15901 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
15902 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
15903 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
15904 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
15905 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
15906 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
15907
15908 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
15909 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
15910 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
15911 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
15912
15913 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
15914 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
15915 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
15916 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
15917
15918 /******************** Bit definition for OTG register ********************/
15919 #define USB_OTG_NPTXFSA_Pos (0U)
15920 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
15921 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
15922 #define USB_OTG_NPTXFD_Pos (16U)
15923 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
15924 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
15925 #define USB_OTG_TX0FSA_Pos (0U)
15926 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
15927 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
15928 #define USB_OTG_TX0FD_Pos (16U)
15929 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
15930 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
15931
15932 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
15933 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
15934 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
15935 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
15936
15937 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
15938 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
15939 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
15940 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
15941
15942 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
15943 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
15944 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
15945 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
15946 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
15947 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
15948 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
15949 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
15950 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
15951 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
15952 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
15953
15954 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
15955 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
15956 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
15957 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
15958 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
15959 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
15960 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
15961 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
15962 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
15963 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
15964
15965 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
15966 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
15967 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
15968 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
15969 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
15970 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
15971 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
15972
15973 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
15974 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
15975 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
15976 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
15977 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
15978 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
15979 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
15980 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
15981 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
15982 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
15983 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
15984 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
15985 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
15986 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
15987 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
15988
15989 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
15990 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
15991 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
15992 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
15993 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
15994 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
15995 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
15996 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
15997 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
15998 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
15999 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
16000 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
16001 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
16002 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
16003 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
16004
16005 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
16006 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
16007 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
16008 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
16009
16010 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
16011 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
16012 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
16013 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
16014 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
16015 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
16016 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
16017
16018 /******************** Bit definition for USB_OTG_GCCFG register ********************/
16019 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
16020 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
16021 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
16022 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
16023 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
16024 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
16025 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
16026 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
16027 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
16028 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
16029 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
16030 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
16031 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
16032 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
16033 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
16034 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
16035 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
16036 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
16037
16038 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
16039 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
16040 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
16041 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
16042 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
16043 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
16044 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
16045
16046 /******************** Bit definition for USB_OTG_CID register ********************/
16047 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
16048 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
16049 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
16050
16051 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
16052 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
16053 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
16054 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
16055 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
16056 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
16057 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
16058 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
16059 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
16060 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
16061 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
16062 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
16063 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
16064 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
16065 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
16066 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
16067 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
16068 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
16069 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
16070 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
16071 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
16072 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
16073 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
16074 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
16075 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
16076 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
16077 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
16078 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
16079
16080 /******************** Bit definition for USB_OTG_HPRT register ********************/
16081 #define USB_OTG_HPRT_PCSTS_Pos (0U)
16082 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
16083 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
16084 #define USB_OTG_HPRT_PCDET_Pos (1U)
16085 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
16086 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
16087 #define USB_OTG_HPRT_PENA_Pos (2U)
16088 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
16089 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
16090 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
16091 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
16092 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
16093 #define USB_OTG_HPRT_POCA_Pos (4U)
16094 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
16095 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
16096 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
16097 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
16098 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
16099 #define USB_OTG_HPRT_PRES_Pos (6U)
16100 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
16101 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
16102 #define USB_OTG_HPRT_PSUSP_Pos (7U)
16103 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
16104 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
16105 #define USB_OTG_HPRT_PRST_Pos (8U)
16106 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
16107 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
16108
16109 #define USB_OTG_HPRT_PLSTS_Pos (10U)
16110 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
16111 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
16112 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
16113 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
16114 #define USB_OTG_HPRT_PPWR_Pos (12U)
16115 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
16116 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
16117
16118 #define USB_OTG_HPRT_PTCTL_Pos (13U)
16119 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
16120 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
16121 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
16122 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
16123 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
16124 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
16125
16126 #define USB_OTG_HPRT_PSPD_Pos (17U)
16127 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
16128 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
16129 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
16130 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
16131
16132 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
16133 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
16134 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
16135 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
16136 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
16137 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
16138 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
16139 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
16140 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
16141 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
16142 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
16143 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
16144 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
16145 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
16146 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
16147 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
16148 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
16149 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
16150 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
16151 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
16152 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
16153 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
16154 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
16155 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
16156 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
16157 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
16158 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
16159 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
16160 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
16161 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
16162 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
16163 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
16164 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
16165 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
16166
16167 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
16168 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
16169 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
16170 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
16171 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
16172 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
16173 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
16174
16175 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
16176 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
16177 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
16178 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
16179 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
16180 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
16181 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
16182 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
16183 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
16184 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
16185 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
16186 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
16187 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
16188
16189 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
16190 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
16191 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
16192 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
16193 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
16194 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
16195 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
16196 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
16197
16198 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
16199 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
16200 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
16201 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
16202 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
16203 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
16204 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
16205 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
16206 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
16207 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
16208 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
16209 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
16210 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
16211 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
16212 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
16213 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
16214 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
16215 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
16216 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
16217 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
16218 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
16219 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
16220 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
16221 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
16222 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
16223
16224 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
16225 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
16226 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
16227 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
16228
16229 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
16230 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
16231 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
16232 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
16233 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
16234 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
16235 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
16236 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
16237 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
16238 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
16239 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
16240 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
16241 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
16242
16243 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
16244 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
16245 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
16246 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
16247 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
16248
16249 #define USB_OTG_HCCHAR_MC_Pos (20U)
16250 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
16251 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
16252 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
16253 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
16254
16255 #define USB_OTG_HCCHAR_DAD_Pos (22U)
16256 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
16257 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
16258 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
16259 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
16260 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
16261 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
16262 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
16263 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
16264 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
16265 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
16266 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
16267 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
16268 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
16269 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
16270 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
16271 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
16272 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
16273 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
16274
16275 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
16276
16277 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
16278 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
16279 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
16280 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
16281 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
16282 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
16283 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
16284 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
16285 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
16286 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
16287
16288 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
16289 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
16290 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
16291 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
16292 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
16293 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
16294 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
16295 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
16296 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
16297 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
16298
16299 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
16300 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
16301 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
16302 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
16303 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
16304 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
16305 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
16306 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
16307 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
16308 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
16309 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
16310
16311 /******************** Bit definition for USB_OTG_HCINT register ********************/
16312 #define USB_OTG_HCINT_XFRC_Pos (0U)
16313 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
16314 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
16315 #define USB_OTG_HCINT_CHH_Pos (1U)
16316 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
16317 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
16318 #define USB_OTG_HCINT_AHBERR_Pos (2U)
16319 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
16320 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
16321 #define USB_OTG_HCINT_STALL_Pos (3U)
16322 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
16323 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
16324 #define USB_OTG_HCINT_NAK_Pos (4U)
16325 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
16326 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
16327 #define USB_OTG_HCINT_ACK_Pos (5U)
16328 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
16329 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
16330 #define USB_OTG_HCINT_NYET_Pos (6U)
16331 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
16332 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
16333 #define USB_OTG_HCINT_TXERR_Pos (7U)
16334 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
16335 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
16336 #define USB_OTG_HCINT_BBERR_Pos (8U)
16337 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
16338 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
16339 #define USB_OTG_HCINT_FRMOR_Pos (9U)
16340 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
16341 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
16342 #define USB_OTG_HCINT_DTERR_Pos (10U)
16343 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
16344 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
16345
16346 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
16347 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
16348 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
16349 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
16350 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
16351 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
16352 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
16353 #define USB_OTG_DIEPINT_TOC_Pos (3U)
16354 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
16355 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
16356 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
16357 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
16358 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
16359 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
16360 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
16361 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
16362 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
16363 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
16364 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
16365 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
16366 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
16367 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
16368 #define USB_OTG_DIEPINT_BNA_Pos (9U)
16369 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
16370 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
16371 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
16372 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
16373 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
16374 #define USB_OTG_DIEPINT_BERR_Pos (12U)
16375 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
16376 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
16377 #define USB_OTG_DIEPINT_NAK_Pos (13U)
16378 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
16379 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
16380
16381 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
16382 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
16383 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
16384 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
16385 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
16386 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
16387 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
16388 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
16389 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
16390 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
16391 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
16392 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
16393 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
16394 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
16395 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
16396 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
16397 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
16398 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
16399 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
16400 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
16401 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
16402 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
16403 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
16404 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
16405 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
16406 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
16407 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
16408 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
16409 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
16410 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
16411 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
16412 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
16413 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
16414 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
16415
16416 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
16417
16418 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
16419 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16420 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
16421 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
16422 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16423 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
16424 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
16425 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
16426 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
16427 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
16428 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
16429 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16430 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
16431 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
16432 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16433 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
16434 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
16435 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
16436 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
16437 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
16438 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
16439 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
16440 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
16441 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
16442
16443 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
16444 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
16445 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
16446 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
16447
16448 /******************** Bit definition for USB_OTG_HCDMA register ********************/
16449 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
16450 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
16451 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
16452
16453 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
16454 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
16455 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
16456 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
16457
16458 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
16459 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
16460 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
16461 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
16462 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
16463 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
16464 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
16465
16466 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
16467
16468 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
16469 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
16470 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
16471 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
16472 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
16473 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
16474 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
16475 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
16476 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
16477 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
16478 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
16479 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
16480 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
16481 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
16482 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
16483 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
16484 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
16485 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
16486 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
16487 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
16488 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
16489 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
16490 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
16491 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
16492 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
16493 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
16494 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
16495 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
16496 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
16497 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
16498 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
16499 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
16500 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
16501 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
16502 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
16503 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
16504 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
16505 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
16506
16507 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
16508 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
16509 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
16510 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
16511 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
16512 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
16513 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
16514 #define USB_OTG_DOEPINT_STUP_Pos (3U)
16515 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
16516 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
16517 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
16518 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
16519 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
16520 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
16521 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
16522 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
16523 #define USB_OTG_DOEPINT_NYET_Pos (14U)
16524 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
16525 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
16526
16527 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
16528
16529 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
16530 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16531 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
16532 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
16533 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16534 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
16535
16536 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
16537 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
16538 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
16539 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
16540 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
16541
16542 /******************** Bit definition for PCGCCTL register ********************/
16543 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
16544 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
16545 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
16546 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
16547 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
16548 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
16549 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
16550 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
16551 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
16552
16553 /* Legacy define */
16554 /******************** Bit definition for OTG register ********************/
16555 #define USB_OTG_CHNUM_Pos (0U)
16556 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
16557 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
16558 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
16559 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
16560 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
16561 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
16562 #define USB_OTG_BCNT_Pos (4U)
16563 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
16564 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
16565
16566 #define USB_OTG_DPID_Pos (15U)
16567 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
16568 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
16569 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
16570 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
16571
16572 #define USB_OTG_PKTSTS_Pos (17U)
16573 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
16574 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
16575 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
16576 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
16577 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
16578 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
16579
16580 #define USB_OTG_EPNUM_Pos (0U)
16581 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
16582 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
16583 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
16584 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
16585 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
16586 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
16587
16588 #define USB_OTG_FRMNUM_Pos (21U)
16589 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
16590 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
16591 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
16592 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
16593 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
16594 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
16595 /**
16596 * @}
16597 */
16598
16599 /**
16600 * @}
16601 */
16602
16603 /** @addtogroup Exported_macros
16604 * @{
16605 */
16606
16607 /******************************* ADC Instances ********************************/
16608 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
16609 ((INSTANCE) == ADC2) || \
16610 ((INSTANCE) == ADC3))
16611
16612 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
16613
16614 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
16615
16616 /******************************* CAN Instances ********************************/
16617 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
16618 ((INSTANCE) == CAN2))
16619 /******************************* CRC Instances ********************************/
16620 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
16621
16622 /******************************* DAC Instances ********************************/
16623 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
16624
16625 /******************************* DCMI Instances *******************************/
16626 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
16627
16628 /******************************* DMA2D Instances *******************************/
16629 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
16630
16631 /******************************** DMA Instances *******************************/
16632 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
16633 ((INSTANCE) == DMA1_Stream1) || \
16634 ((INSTANCE) == DMA1_Stream2) || \
16635 ((INSTANCE) == DMA1_Stream3) || \
16636 ((INSTANCE) == DMA1_Stream4) || \
16637 ((INSTANCE) == DMA1_Stream5) || \
16638 ((INSTANCE) == DMA1_Stream6) || \
16639 ((INSTANCE) == DMA1_Stream7) || \
16640 ((INSTANCE) == DMA2_Stream0) || \
16641 ((INSTANCE) == DMA2_Stream1) || \
16642 ((INSTANCE) == DMA2_Stream2) || \
16643 ((INSTANCE) == DMA2_Stream3) || \
16644 ((INSTANCE) == DMA2_Stream4) || \
16645 ((INSTANCE) == DMA2_Stream5) || \
16646 ((INSTANCE) == DMA2_Stream6) || \
16647 ((INSTANCE) == DMA2_Stream7))
16648
16649 /******************************* GPIO Instances *******************************/
16650 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
16651 ((INSTANCE) == GPIOB) || \
16652 ((INSTANCE) == GPIOC) || \
16653 ((INSTANCE) == GPIOD) || \
16654 ((INSTANCE) == GPIOE) || \
16655 ((INSTANCE) == GPIOF) || \
16656 ((INSTANCE) == GPIOG) || \
16657 ((INSTANCE) == GPIOH) || \
16658 ((INSTANCE) == GPIOI) || \
16659 ((INSTANCE) == GPIOJ) || \
16660 ((INSTANCE) == GPIOK))
16661
16662 /******************************** I2C Instances *******************************/
16663 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
16664 ((INSTANCE) == I2C2) || \
16665 ((INSTANCE) == I2C3))
16666
16667 /******************************* SMBUS Instances ******************************/
16668 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
16669
16670 /******************************** I2S Instances *******************************/
16671
16672 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
16673 ((INSTANCE) == SPI3))
16674
16675 /*************************** I2S Extended Instances ***************************/
16676 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
16677 ((INSTANCE) == I2S3ext))
16678 /* Legacy Defines */
16679 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
16680
16681 /****************************** LTDC Instances ********************************/
16682 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
16683 /******************************* RNG Instances ********************************/
16684 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
16685
16686 /****************************** RTC Instances *********************************/
16687 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
16688
16689 /******************************* SAI Instances ********************************/
16690 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
16691 ((PERIPH) == SAI1_Block_B))
16692 /* Legacy define */
16693
16694 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
16695
16696 /******************************** SPI Instances *******************************/
16697 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
16698 ((INSTANCE) == SPI2) || \
16699 ((INSTANCE) == SPI3) || \
16700 ((INSTANCE) == SPI4) || \
16701 ((INSTANCE) == SPI5) || \
16702 ((INSTANCE) == SPI6))
16703
16704
16705 /****************** TIM Instances : All supported instances *******************/
16706 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16707 ((INSTANCE) == TIM2) || \
16708 ((INSTANCE) == TIM3) || \
16709 ((INSTANCE) == TIM4) || \
16710 ((INSTANCE) == TIM5) || \
16711 ((INSTANCE) == TIM6) || \
16712 ((INSTANCE) == TIM7) || \
16713 ((INSTANCE) == TIM8) || \
16714 ((INSTANCE) == TIM9) || \
16715 ((INSTANCE) == TIM10)|| \
16716 ((INSTANCE) == TIM11)|| \
16717 ((INSTANCE) == TIM12)|| \
16718 ((INSTANCE) == TIM13)|| \
16719 ((INSTANCE) == TIM14))
16720
16721 /************* TIM Instances : at least 1 capture/compare channel *************/
16722 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16723 ((INSTANCE) == TIM2) || \
16724 ((INSTANCE) == TIM3) || \
16725 ((INSTANCE) == TIM4) || \
16726 ((INSTANCE) == TIM5) || \
16727 ((INSTANCE) == TIM8) || \
16728 ((INSTANCE) == TIM9) || \
16729 ((INSTANCE) == TIM10) || \
16730 ((INSTANCE) == TIM11) || \
16731 ((INSTANCE) == TIM12) || \
16732 ((INSTANCE) == TIM13) || \
16733 ((INSTANCE) == TIM14))
16734
16735 /************ TIM Instances : at least 2 capture/compare channels *************/
16736 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16737 ((INSTANCE) == TIM2) || \
16738 ((INSTANCE) == TIM3) || \
16739 ((INSTANCE) == TIM4) || \
16740 ((INSTANCE) == TIM5) || \
16741 ((INSTANCE) == TIM8) || \
16742 ((INSTANCE) == TIM9) || \
16743 ((INSTANCE) == TIM12))
16744
16745 /************ TIM Instances : at least 3 capture/compare channels *************/
16746 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16747 ((INSTANCE) == TIM2) || \
16748 ((INSTANCE) == TIM3) || \
16749 ((INSTANCE) == TIM4) || \
16750 ((INSTANCE) == TIM5) || \
16751 ((INSTANCE) == TIM8))
16752
16753 /************ TIM Instances : at least 4 capture/compare channels *************/
16754 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16755 ((INSTANCE) == TIM2) || \
16756 ((INSTANCE) == TIM3) || \
16757 ((INSTANCE) == TIM4) || \
16758 ((INSTANCE) == TIM5) || \
16759 ((INSTANCE) == TIM8))
16760
16761 /******************** TIM Instances : Advanced-control timers *****************/
16762 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16763 ((INSTANCE) == TIM8))
16764
16765 /******************* TIM Instances : Timer input XOR function *****************/
16766 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16767 ((INSTANCE) == TIM2) || \
16768 ((INSTANCE) == TIM3) || \
16769 ((INSTANCE) == TIM4) || \
16770 ((INSTANCE) == TIM5) || \
16771 ((INSTANCE) == TIM8))
16772
16773 /****************** TIM Instances : DMA requests generation (UDE) *************/
16774 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16775 ((INSTANCE) == TIM2) || \
16776 ((INSTANCE) == TIM3) || \
16777 ((INSTANCE) == TIM4) || \
16778 ((INSTANCE) == TIM5) || \
16779 ((INSTANCE) == TIM6) || \
16780 ((INSTANCE) == TIM7) || \
16781 ((INSTANCE) == TIM8))
16782
16783 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
16784 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16785 ((INSTANCE) == TIM2) || \
16786 ((INSTANCE) == TIM3) || \
16787 ((INSTANCE) == TIM4) || \
16788 ((INSTANCE) == TIM5) || \
16789 ((INSTANCE) == TIM8))
16790
16791 /************ TIM Instances : DMA requests generation (COMDE) *****************/
16792 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16793 ((INSTANCE) == TIM2) || \
16794 ((INSTANCE) == TIM3) || \
16795 ((INSTANCE) == TIM4) || \
16796 ((INSTANCE) == TIM5) || \
16797 ((INSTANCE) == TIM8))
16798
16799 /******************** TIM Instances : DMA burst feature ***********************/
16800 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16801 ((INSTANCE) == TIM2) || \
16802 ((INSTANCE) == TIM3) || \
16803 ((INSTANCE) == TIM4) || \
16804 ((INSTANCE) == TIM5) || \
16805 ((INSTANCE) == TIM8))
16806
16807 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
16808 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16809 ((INSTANCE) == TIM2) || \
16810 ((INSTANCE) == TIM3) || \
16811 ((INSTANCE) == TIM4) || \
16812 ((INSTANCE) == TIM5) || \
16813 ((INSTANCE) == TIM6) || \
16814 ((INSTANCE) == TIM7) || \
16815 ((INSTANCE) == TIM8))
16816
16817 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
16818 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16819 ((INSTANCE) == TIM2) || \
16820 ((INSTANCE) == TIM3) || \
16821 ((INSTANCE) == TIM4) || \
16822 ((INSTANCE) == TIM5) || \
16823 ((INSTANCE) == TIM8) || \
16824 ((INSTANCE) == TIM9) || \
16825 ((INSTANCE) == TIM12))
16826
16827 /********************** TIM Instances : 32 bit Counter ************************/
16828 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
16829 ((INSTANCE) == TIM5))
16830
16831 /***************** TIM Instances : external trigger input availabe ************/
16832 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16833 ((INSTANCE) == TIM2) || \
16834 ((INSTANCE) == TIM3) || \
16835 ((INSTANCE) == TIM4) || \
16836 ((INSTANCE) == TIM5) || \
16837 ((INSTANCE) == TIM8))
16838
16839 /****************** TIM Instances : remapping capability **********************/
16840 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
16841 ((INSTANCE) == TIM5) || \
16842 ((INSTANCE) == TIM11))
16843
16844 /******************* TIM Instances : output(s) available **********************/
16845 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
16846 ((((INSTANCE) == TIM1) && \
16847 (((CHANNEL) == TIM_CHANNEL_1) || \
16848 ((CHANNEL) == TIM_CHANNEL_2) || \
16849 ((CHANNEL) == TIM_CHANNEL_3) || \
16850 ((CHANNEL) == TIM_CHANNEL_4))) \
16851 || \
16852 (((INSTANCE) == TIM2) && \
16853 (((CHANNEL) == TIM_CHANNEL_1) || \
16854 ((CHANNEL) == TIM_CHANNEL_2) || \
16855 ((CHANNEL) == TIM_CHANNEL_3) || \
16856 ((CHANNEL) == TIM_CHANNEL_4))) \
16857 || \
16858 (((INSTANCE) == TIM3) && \
16859 (((CHANNEL) == TIM_CHANNEL_1) || \
16860 ((CHANNEL) == TIM_CHANNEL_2) || \
16861 ((CHANNEL) == TIM_CHANNEL_3) || \
16862 ((CHANNEL) == TIM_CHANNEL_4))) \
16863 || \
16864 (((INSTANCE) == TIM4) && \
16865 (((CHANNEL) == TIM_CHANNEL_1) || \
16866 ((CHANNEL) == TIM_CHANNEL_2) || \
16867 ((CHANNEL) == TIM_CHANNEL_3) || \
16868 ((CHANNEL) == TIM_CHANNEL_4))) \
16869 || \
16870 (((INSTANCE) == TIM5) && \
16871 (((CHANNEL) == TIM_CHANNEL_1) || \
16872 ((CHANNEL) == TIM_CHANNEL_2) || \
16873 ((CHANNEL) == TIM_CHANNEL_3) || \
16874 ((CHANNEL) == TIM_CHANNEL_4))) \
16875 || \
16876 (((INSTANCE) == TIM8) && \
16877 (((CHANNEL) == TIM_CHANNEL_1) || \
16878 ((CHANNEL) == TIM_CHANNEL_2) || \
16879 ((CHANNEL) == TIM_CHANNEL_3) || \
16880 ((CHANNEL) == TIM_CHANNEL_4))) \
16881 || \
16882 (((INSTANCE) == TIM9) && \
16883 (((CHANNEL) == TIM_CHANNEL_1) || \
16884 ((CHANNEL) == TIM_CHANNEL_2))) \
16885 || \
16886 (((INSTANCE) == TIM10) && \
16887 (((CHANNEL) == TIM_CHANNEL_1))) \
16888 || \
16889 (((INSTANCE) == TIM11) && \
16890 (((CHANNEL) == TIM_CHANNEL_1))) \
16891 || \
16892 (((INSTANCE) == TIM12) && \
16893 (((CHANNEL) == TIM_CHANNEL_1) || \
16894 ((CHANNEL) == TIM_CHANNEL_2))) \
16895 || \
16896 (((INSTANCE) == TIM13) && \
16897 (((CHANNEL) == TIM_CHANNEL_1))) \
16898 || \
16899 (((INSTANCE) == TIM14) && \
16900 (((CHANNEL) == TIM_CHANNEL_1))))
16901
16902 /************ TIM Instances : complementary output(s) available ***************/
16903 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
16904 ((((INSTANCE) == TIM1) && \
16905 (((CHANNEL) == TIM_CHANNEL_1) || \
16906 ((CHANNEL) == TIM_CHANNEL_2) || \
16907 ((CHANNEL) == TIM_CHANNEL_3))) \
16908 || \
16909 (((INSTANCE) == TIM8) && \
16910 (((CHANNEL) == TIM_CHANNEL_1) || \
16911 ((CHANNEL) == TIM_CHANNEL_2) || \
16912 ((CHANNEL) == TIM_CHANNEL_3))))
16913
16914 /****************** TIM Instances : supporting counting mode selection ********/
16915 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16916 ((INSTANCE) == TIM2) || \
16917 ((INSTANCE) == TIM3) || \
16918 ((INSTANCE) == TIM4) || \
16919 ((INSTANCE) == TIM5) || \
16920 ((INSTANCE) == TIM8))
16921
16922 /****************** TIM Instances : supporting clock division *****************/
16923 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16924 ((INSTANCE) == TIM2) || \
16925 ((INSTANCE) == TIM3) || \
16926 ((INSTANCE) == TIM4) || \
16927 ((INSTANCE) == TIM5) || \
16928 ((INSTANCE) == TIM8) || \
16929 ((INSTANCE) == TIM9) || \
16930 ((INSTANCE) == TIM10)|| \
16931 ((INSTANCE) == TIM11)|| \
16932 ((INSTANCE) == TIM12)|| \
16933 ((INSTANCE) == TIM13)|| \
16934 ((INSTANCE) == TIM14))
16935
16936 /****************** TIM Instances : supporting commutation event generation ***/
16937 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
16938 ((INSTANCE) == TIM8))
16939
16940
16941 /****************** TIM Instances : supporting OCxREF clear *******************/
16942 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16943 ((INSTANCE) == TIM2) || \
16944 ((INSTANCE) == TIM3) || \
16945 ((INSTANCE) == TIM4) || \
16946 ((INSTANCE) == TIM5) || \
16947 ((INSTANCE) == TIM8))
16948
16949 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
16950 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16951 ((INSTANCE) == TIM2) || \
16952 ((INSTANCE) == TIM3) || \
16953 ((INSTANCE) == TIM4) || \
16954 ((INSTANCE) == TIM5) || \
16955 ((INSTANCE) == TIM8) || \
16956 ((INSTANCE) == TIM9) || \
16957 ((INSTANCE) == TIM12))
16958
16959 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
16960 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16961 ((INSTANCE) == TIM2) || \
16962 ((INSTANCE) == TIM3) || \
16963 ((INSTANCE) == TIM4) || \
16964 ((INSTANCE) == TIM5) || \
16965 ((INSTANCE) == TIM8))
16966
16967 /****************** TIM Instances : supporting repetition counter *************/
16968 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16969 ((INSTANCE) == TIM8))
16970
16971 /****************** TIM Instances : supporting encoder interface **************/
16972 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16973 ((INSTANCE) == TIM2) || \
16974 ((INSTANCE) == TIM3) || \
16975 ((INSTANCE) == TIM4) || \
16976 ((INSTANCE) == TIM5) || \
16977 ((INSTANCE) == TIM8) || \
16978 ((INSTANCE) == TIM9) || \
16979 ((INSTANCE) == TIM12))
16980 /****************** TIM Instances : supporting Hall sensor interface **********/
16981 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16982 ((INSTANCE) == TIM2) || \
16983 ((INSTANCE) == TIM3) || \
16984 ((INSTANCE) == TIM4) || \
16985 ((INSTANCE) == TIM5) || \
16986 ((INSTANCE) == TIM8))
16987 /****************** TIM Instances : supporting the break function *************/
16988 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16989 ((INSTANCE) == TIM8))
16990
16991 /******************** USART Instances : Synchronous mode **********************/
16992 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16993 ((INSTANCE) == USART2) || \
16994 ((INSTANCE) == USART3) || \
16995 ((INSTANCE) == USART6))
16996
16997 /******************** UART Instances : Half-Duplex mode **********************/
16998 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16999 ((INSTANCE) == USART2) || \
17000 ((INSTANCE) == USART3) || \
17001 ((INSTANCE) == UART4) || \
17002 ((INSTANCE) == UART5) || \
17003 ((INSTANCE) == USART6) || \
17004 ((INSTANCE) == UART7) || \
17005 ((INSTANCE) == UART8))
17006
17007 /* Legacy defines */
17008 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
17009
17010 /****************** UART Instances : Hardware Flow control ********************/
17011 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17012 ((INSTANCE) == USART2) || \
17013 ((INSTANCE) == USART3) || \
17014 ((INSTANCE) == USART6))
17015 /******************** UART Instances : LIN mode **********************/
17016 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
17017
17018 /********************* UART Instances : Smart card mode ***********************/
17019 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17020 ((INSTANCE) == USART2) || \
17021 ((INSTANCE) == USART3) || \
17022 ((INSTANCE) == USART6))
17023
17024 /*********************** UART Instances : IRDA mode ***************************/
17025 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17026 ((INSTANCE) == USART2) || \
17027 ((INSTANCE) == USART3) || \
17028 ((INSTANCE) == UART4) || \
17029 ((INSTANCE) == UART5) || \
17030 ((INSTANCE) == USART6) || \
17031 ((INSTANCE) == UART7) || \
17032 ((INSTANCE) == UART8))
17033
17034 /*********************** PCD Instances ****************************************/
17035 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17036 ((INSTANCE) == USB_OTG_HS))
17037
17038 /*********************** HCD Instances ****************************************/
17039 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17040 ((INSTANCE) == USB_OTG_HS))
17041
17042 /****************************** SDIO Instances ********************************/
17043 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
17044
17045 /****************************** IWDG Instances ********************************/
17046 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
17047
17048 /****************************** WWDG Instances ********************************/
17049 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
17050
17051 /****************************** USB Exported Constants ************************/
17052 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
17053 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
17054 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
17055 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
17056
17057 /*
17058 * @brief Specific devices reset values definitions
17059 */
17060 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
17061 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
17062 #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
17063
17064 #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
17065 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
17066 #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
17067 #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
17068 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
17069 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
17070 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
17071 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
17072
17073 #define RCC_PLLN_MIN_VALUE 50U
17074 #define RCC_PLLN_MAX_VALUE 432U
17075
17076 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
17077 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
17078 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
17079 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
17080 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
17081
17082 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
17083 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
17084 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
17085 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
17086 #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
17087
17088 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
17089 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
17090 #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
17091
17092 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
17093 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
17094 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
17095 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
17096 /******************************************************************************/
17097 /* For a painless codes migration between the STM32F4xx device product */
17098 /* lines, the aliases defined below are put in place to overcome the */
17099 /* differences in the interrupt handlers and IRQn definitions. */
17100 /* No need to update developed interrupt code when moving across */
17101 /* product lines within the same STM32F4 Family */
17102 /******************************************************************************/
17103 /* Aliases for __IRQn */
17104 #define FSMC_IRQn FMC_IRQn
17105
17106 /* Aliases for __IRQHandler */
17107 #define FSMC_IRQHandler FMC_IRQHandler
17108
17109 /**
17110 * @}
17111 */
17112
17113 /**
17114 * @}
17115 */
17116
17117 /**
17118 * @}
17119 */
17120
17121 #ifdef __cplusplus
17122 }
17123 #endif /* __cplusplus */
17124
17125 #endif /* __STM32F429xx_H */
17126
17127
17128
17129 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/