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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f423xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F423xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - peripherals registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f423xx
47 * @{
48 */
49
50 #ifndef __STM32F423xx_H
51 #define __STM32F423xx_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #define __FPU_PRESENT 1U /*!< FPU present */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78 /**
79 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
87 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
88 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
89 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
91 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
92 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
93 /****** STM32 specific Interrupt Numbers **********************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
99 RCC_IRQn = 5, /*!< RCC global Interrupt */
100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
112 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
113 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
114 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
115 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
116 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
133 USART3_IRQn = 39, /*!< USART3 global Interrupt */
134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
137 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
138 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
139 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
140 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
141 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
142 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
143 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
144 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
145 UART4_IRQn = 52, /*!< UART4 global Interrupt */
146 UART5_IRQn = 53, /*!< UART5 global Interrupt */
147 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
148 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
149 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
150 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
151 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
152 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
153 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
154 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
155 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
156 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
157 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
158 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
159 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
160 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
161 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
162 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
163 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
164 USART6_IRQn = 71, /*!< USART6 global interrupt */
165 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
166 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
167 CAN3_TX_IRQn = 74, /*!< CAN3 TX Interrupt */
168 CAN3_RX0_IRQn = 75, /*!< CAN3 RX0 Interrupt */
169 CAN3_RX1_IRQn = 76, /*!< CAN3 RX1 Interrupt */
170 CAN3_SCE_IRQn = 77, /*!< CAN3 SCE Interrupt */
171 AES_IRQn = 79, /*!< AES global Interrupt */
172 RNG_IRQn = 80, /*!< RNG global Interrupt */
173 FPU_IRQn = 81, /*!< FPU global interrupt */
174 UART7_IRQn = 82, /*!< UART7 global interrupt */
175 UART8_IRQn = 83, /*!< UART8 global interrupt */
176 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
177 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
178 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
179 UART9_IRQn = 88, /*!< UART9 global Interrupt */
180 UART10_IRQn = 89, /*!< UART10 global Interrupt */
181 QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
182 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
183 FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
184 LPTIM1_IRQn = 97, /*!< LP TIM1 interrupt */
185 DFSDM2_FLT0_IRQn = 98, /*!< DFSDM2 Filter 0 global Interrupt */
186 DFSDM2_FLT1_IRQn = 99, /*!< DFSDM2 Filter 1 global Interrupt */
187 DFSDM2_FLT2_IRQn = 100, /*!< DFSDM2 Filter 2 global Interrupt */
188 DFSDM2_FLT3_IRQn = 101 /*!< DFSDM2 Filter 3 global Interrupt */
189 } IRQn_Type;
190
191 /**
192 * @}
193 */
194
195 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
196 #include "system_stm32f4xx.h"
197 #include <stdint.h>
198
199 /** @addtogroup Peripheral_registers_structures
200 * @{
201 */
202
203 /**
204 * @brief Analog to Digital Converter
205 */
206
207 typedef struct
208 {
209 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
210 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
211 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
212 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
213 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
214 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
215 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
216 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
217 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
218 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
219 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
220 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
221 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
222 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
223 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
224 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
225 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
226 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
227 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
228 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
229 } ADC_TypeDef;
230
231 typedef struct
232 {
233 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
234 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
235 __IO uint32_t CDR; /*!< ADC common regular data register for dual
236 AND triple modes, Address offset: ADC1 base address + 0x308 */
237 } ADC_Common_TypeDef;
238
239
240 /**
241 * @brief Controller Area Network TxMailBox
242 */
243
244 typedef struct
245 {
246 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
247 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
248 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
249 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
250 } CAN_TxMailBox_TypeDef;
251
252 /**
253 * @brief Controller Area Network FIFOMailBox
254 */
255
256 typedef struct
257 {
258 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
259 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
260 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
261 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
262 } CAN_FIFOMailBox_TypeDef;
263
264 /**
265 * @brief Controller Area Network FilterRegister
266 */
267
268 typedef struct
269 {
270 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
271 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
272 } CAN_FilterRegister_TypeDef;
273
274 /**
275 * @brief Controller Area Network
276 */
277
278 typedef struct
279 {
280 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
281 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
282 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
283 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
284 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
285 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
286 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
287 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
288 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
289 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
290 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
291 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
292 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
293 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
294 uint32_t RESERVED2; /*!< Reserved, 0x208 */
295 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
296 uint32_t RESERVED3; /*!< Reserved, 0x210 */
297 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
298 uint32_t RESERVED4; /*!< Reserved, 0x218 */
299 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
300 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
301 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
302 } CAN_TypeDef;
303
304 /**
305 * @brief CRC calculation unit
306 */
307
308 typedef struct
309 {
310 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
311 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
312 uint8_t RESERVED0; /*!< Reserved, 0x05 */
313 uint16_t RESERVED1; /*!< Reserved, 0x06 */
314 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
315 } CRC_TypeDef;
316
317 /**
318 * @brief DFSDM module registers
319 */
320 typedef struct
321 {
322 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
323 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
324 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
325 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
326 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
327 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
328 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
329 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
330 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
331 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
332 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
333 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
334 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
335 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
336 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
337 } DFSDM_Filter_TypeDef;
338
339 /**
340 * @brief DFSDM channel configuration registers
341 */
342 typedef struct
343 {
344 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
345 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
346 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
347 short circuit detector register, Address offset: 0x08 */
348 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
349 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
350 } DFSDM_Channel_TypeDef;
351
352 /**
353 * @brief Digital to Analog Converter
354 */
355
356 typedef struct
357 {
358 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
359 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
360 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
361 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
362 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
363 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
364 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
365 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
366 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
367 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
368 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
369 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
370 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
371 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
372 } DAC_TypeDef;
373
374 /**
375 * @brief Debug MCU
376 */
377
378 typedef struct
379 {
380 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
381 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
382 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
383 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
384 }DBGMCU_TypeDef;
385
386
387 /**
388 * @brief DMA Controller
389 */
390
391 typedef struct
392 {
393 __IO uint32_t CR; /*!< DMA stream x configuration register */
394 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
395 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
396 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
397 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
398 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
399 } DMA_Stream_TypeDef;
400
401 typedef struct
402 {
403 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
404 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
405 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
406 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
407 } DMA_TypeDef;
408
409 /**
410 * @brief External Interrupt/Event Controller
411 */
412
413 typedef struct
414 {
415 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
416 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
417 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
418 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
419 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
420 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
421 } EXTI_TypeDef;
422
423 /**
424 * @brief FLASH Registers
425 */
426
427 typedef struct
428 {
429 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
430 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
431 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
432 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
433 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
434 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
435 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
436 } FLASH_TypeDef;
437
438
439
440 /**
441 * @brief Flexible Static Memory Controller
442 */
443
444 typedef struct
445 {
446 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
447 } FSMC_Bank1_TypeDef;
448
449 /**
450 * @brief Flexible Static Memory Controller Bank1E
451 */
452
453 typedef struct
454 {
455 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
456 } FSMC_Bank1E_TypeDef;
457 /**
458 * @brief General Purpose I/O
459 */
460
461 typedef struct
462 {
463 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
464 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
465 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
466 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
467 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
468 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
469 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
470 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
471 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
472 } GPIO_TypeDef;
473
474 /**
475 * @brief System configuration controller
476 */
477
478 typedef struct
479 {
480 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
481 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
482 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
483 uint32_t RESERVED; /*!< Reserved, 0x18 */
484 __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
485 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
486 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
487 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
488 __IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset: 0x30 */
489 } SYSCFG_TypeDef;
490
491 /**
492 * @brief Inter-integrated Circuit Interface
493 */
494
495 typedef struct
496 {
497 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
498 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
499 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
500 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
501 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
502 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
503 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
504 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
505 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
506 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
507 } I2C_TypeDef;
508
509 /**
510 * @brief Inter-integrated Circuit Interface
511 */
512
513 typedef struct
514 {
515 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
516 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
517 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
518 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
519 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
520 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
521 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
522 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
523 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
524 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
525 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
526 } FMPI2C_TypeDef;
527
528 /**
529 * @brief Independent WATCHDOG
530 */
531
532 typedef struct
533 {
534 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
535 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
536 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
537 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
538 } IWDG_TypeDef;
539
540
541 /**
542 * @brief Power Control
543 */
544
545 typedef struct
546 {
547 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
548 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
549 } PWR_TypeDef;
550
551 /**
552 * @brief Reset and Clock Control
553 */
554
555 typedef struct
556 {
557 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
558 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
559 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
560 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
561 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
562 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
563 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
564 uint32_t RESERVED0; /*!< Reserved, 0x1C */
565 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
566 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
567 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
568 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
569 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
570 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
571 uint32_t RESERVED2; /*!< Reserved, 0x3C */
572 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
573 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
574 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
575 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
576 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
577 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
578 uint32_t RESERVED4; /*!< Reserved, 0x5C */
579 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
580 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
581 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
582 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
583 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
584 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
585 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
586 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
587 uint32_t RESERVED7; /*!< Reserved, 0x84 */
588 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
589 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
590 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
591 } RCC_TypeDef;
592
593 /**
594 * @brief Real-Time Clock
595 */
596
597 typedef struct
598 {
599 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
600 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
601 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
602 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
603 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
604 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
605 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
606 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
607 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
608 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
609 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
610 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
611 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
612 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
613 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
614 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
615 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
616 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
617 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
618 uint32_t RESERVED7; /*!< Reserved, 0x4C */
619 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
620 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
621 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
622 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
623 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
624 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
625 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
626 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
627 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
628 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
629 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
630 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
631 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
632 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
633 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
634 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
635 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
636 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
637 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
638 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
639 } RTC_TypeDef;
640
641 /**
642 * @brief Serial Audio Interface
643 */
644
645 typedef struct
646 {
647 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
648 } SAI_TypeDef;
649
650 typedef struct
651 {
652 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
653 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
654 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
655 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
656 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
657 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
658 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
659 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
660 } SAI_Block_TypeDef;
661
662 /**
663 * @brief SD host Interface
664 */
665
666 typedef struct
667 {
668 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
669 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
670 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
671 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
672 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
673 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
674 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
675 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
676 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
677 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
678 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
679 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
680 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
681 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
682 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
683 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
684 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
685 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
686 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
687 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
688 } SDIO_TypeDef;
689
690 /**
691 * @brief Serial Peripheral Interface
692 */
693
694 typedef struct
695 {
696 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
697 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
698 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
699 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
700 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
701 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
702 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
703 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
704 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
705 } SPI_TypeDef;
706
707 /**
708 * @brief QUAD Serial Peripheral Interface
709 */
710
711 typedef struct
712 {
713 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
714 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
715 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
716 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
717 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
718 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
719 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
720 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
721 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
722 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
723 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
724 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
725 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
726 } QUADSPI_TypeDef;
727
728 /**
729 * @brief TIM
730 */
731
732 typedef struct
733 {
734 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
735 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
736 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
737 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
738 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
739 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
740 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
741 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
742 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
743 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
744 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
745 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
746 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
747 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
748 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
749 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
750 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
751 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
752 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
753 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
754 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
755 } TIM_TypeDef;
756
757 /**
758 * @brief Universal Synchronous Asynchronous Receiver Transmitter
759 */
760
761 typedef struct
762 {
763 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
764 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
765 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
766 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
767 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
768 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
769 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
770 } USART_TypeDef;
771
772 /**
773 * @brief Window WATCHDOG
774 */
775
776 typedef struct
777 {
778 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
779 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
780 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
781 } WWDG_TypeDef;
782
783 /**
784 * @brief AES hardware accelerator
785 */
786
787 typedef struct
788 {
789 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
790 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
791 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
792 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
793 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
794 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
795 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
796 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
797 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
798 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
799 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
800 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
801 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
802 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
803 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
804 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
805 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
806 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
807 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
808 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
809 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
810 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
811 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
812 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
813 } AES_TypeDef;
814
815
816 /**
817 * @brief RNG
818 */
819
820 typedef struct
821 {
822 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
823 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
824 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
825 } RNG_TypeDef;
826
827 /**
828 * @brief USB_OTG_Core_Registers
829 */
830 typedef struct
831 {
832 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
833 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
834 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
835 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
836 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
837 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
838 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
839 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
840 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
841 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
842 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
843 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
844 uint32_t Reserved30[2]; /*!< Reserved 030h */
845 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
846 __IO uint32_t CID; /*!< User ID Register 03Ch */
847 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
848 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
849 uint32_t Reserved6; /*!< Reserved 050h */
850 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
851 uint32_t Reserved; /*!< Reserved 058h */
852 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
853 uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
854 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
855 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
856 } USB_OTG_GlobalTypeDef;
857
858 /**
859 * @brief USB_OTG_device_Registers
860 */
861 typedef struct
862 {
863 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
864 __IO uint32_t DCTL; /*!< dev Control Register 804h */
865 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
866 uint32_t Reserved0C; /*!< Reserved 80Ch */
867 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
868 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
869 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
870 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
871 uint32_t Reserved20; /*!< Reserved 820h */
872 uint32_t Reserved9; /*!< Reserved 824h */
873 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
874 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
875 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
876 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
877 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
878 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
879 uint32_t Reserved40; /*!< dedicated EP mask 840h */
880 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
881 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
882 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
883 } USB_OTG_DeviceTypeDef;
884
885 /**
886 * @brief USB_OTG_IN_Endpoint-Specific_Register
887 */
888 typedef struct
889 {
890 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
891 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
892 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
893 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
894 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
895 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
896 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
897 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
898 } USB_OTG_INEndpointTypeDef;
899
900 /**
901 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
902 */
903 typedef struct
904 {
905 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
906 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
907 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
908 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
909 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
910 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
911 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
912 } USB_OTG_OUTEndpointTypeDef;
913
914 /**
915 * @brief USB_OTG_Host_Mode_Register_Structures
916 */
917 typedef struct
918 {
919 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
920 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
921 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
922 uint32_t Reserved40C; /*!< Reserved 40Ch */
923 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
924 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
925 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
926 } USB_OTG_HostTypeDef;
927
928 /**
929 * @brief USB_OTG_Host_Channel_Specific_Registers
930 */
931 typedef struct
932 {
933 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
934 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
935 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
936 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
937 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
938 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
939 uint32_t Reserved[2]; /*!< Reserved */
940 } USB_OTG_HostChannelTypeDef;
941
942 /**
943 * @brief LPTIMER
944 */
945 typedef struct
946 {
947 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
948 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
949 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
950 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
951 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
952 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
953 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
954 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
955 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
956 } LPTIM_TypeDef;
957
958 /**
959 * @}
960 */
961
962 /** @addtogroup Peripheral_memory_map
963 * @{
964 */
965 #define FLASH_BASE 0x08000000U /*!< FLASH (up to 1.5 MB) base address in the alias region */
966 #define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */
967 #define SRAM2_BASE 0x20040000U /*!< SRAM2(64 KB) base address in the alias region */
968 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
969 #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
970 #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
971 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */
972 #define SRAM2_BB_BASE 0x22800000U /*!< SRAM2(64 KB) base address in the bit-band region */
973 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
974 #define FLASH_END 0x0817FFFFU /*!< FLASH end address */
975 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
976 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
977
978 /* Legacy defines */
979 #define SRAM_BASE SRAM1_BASE
980 #define SRAM_BB_BASE SRAM1_BB_BASE
981
982 /*!< Peripheral memory map */
983 #define APB1PERIPH_BASE PERIPH_BASE
984 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
985 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
986 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
987
988 /*!< APB1 peripherals */
989 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
990 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
991 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
992 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
993 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
994 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
995 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
996 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
997 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
998 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
999 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1000 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1001 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1002 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1003 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1004 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1005 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1006 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1007 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1008 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1009 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1010 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1011 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1012 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1013 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
1014 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1015 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1016 #define CAN3_BASE (APB1PERIPH_BASE + 0x6C00U)
1017 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1018 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1019 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1020 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1021
1022 /*!< APB2 peripherals */
1023 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1024 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1025 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1026 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1027 #define UART9_BASE (APB2PERIPH_BASE + 0x1800U)
1028 #define UART10_BASE (APB2PERIPH_BASE + 0x1C00U)
1029 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1030 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
1031 /* Legacy define */
1032 #define ADC_BASE ADC1_COMMON_BASE
1033 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1034 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1035 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1036 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1037 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1038 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1039 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1040 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1041 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1042 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
1043 #define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400U)
1044 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
1045 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
1046 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
1047 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
1048 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
1049 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
1050 #define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00U)
1051 #define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20U)
1052 #define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40U)
1053 #define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60U)
1054 #define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80U)
1055 #define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0U)
1056 #define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0U)
1057 #define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0U)
1058 #define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100U)
1059 #define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180U)
1060 #define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200U)
1061 #define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280U)
1062 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1063 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1064 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1065
1066 /*!< AHB1 peripherals */
1067 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1068 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1069 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1070 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1071 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1072 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1073 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1074 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1075 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1076 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1077 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1078 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1079 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1080 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1081 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1082 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1083 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1084 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1085 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1086 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1087 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1088 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1089 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1090 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1091 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1092 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1093 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1094 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1095 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1096
1097 /*!< AHB2 peripherals */
1098 #define AES_BASE (AHB2PERIPH_BASE + 0x60000U)
1099 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1100
1101
1102 /*!< FSMC Bankx registers base address */
1103 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
1104 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
1105
1106 /*!< Debug MCU registers base address */
1107 #define DBGMCU_BASE 0xE0042000U
1108 /*!< USB registers base address */
1109 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1110
1111 #define USB_OTG_GLOBAL_BASE 0x000U
1112 #define USB_OTG_DEVICE_BASE 0x800U
1113 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1114 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1115 #define USB_OTG_EP_REG_SIZE 0x20U
1116 #define USB_OTG_HOST_BASE 0x400U
1117 #define USB_OTG_HOST_PORT_BASE 0x440U
1118 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1119 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1120 #define USB_OTG_PCGCCTL_BASE 0xE00U
1121 #define USB_OTG_FIFO_BASE 0x1000U
1122 #define USB_OTG_FIFO_SIZE 0x1000U
1123
1124 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
1125 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
1126 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1127 /**
1128 * @}
1129 */
1130
1131 /** @addtogroup Peripheral_declaration
1132 * @{
1133 */
1134 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1135 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1136 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1137 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1138 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1139 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1140 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1141 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1142 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1143 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1144 #define RTC ((RTC_TypeDef *) RTC_BASE)
1145 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1146 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1147 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1148 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1149 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1150 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1151 #define USART2 ((USART_TypeDef *) USART2_BASE)
1152 #define USART3 ((USART_TypeDef *) USART3_BASE)
1153 #define UART4 ((USART_TypeDef *) UART4_BASE)
1154 #define UART5 ((USART_TypeDef *) UART5_BASE)
1155 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1156 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1157 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1158 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
1159 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1160 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1161 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
1162 #define PWR ((PWR_TypeDef *) PWR_BASE)
1163 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1164 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1165 #define UART7 ((USART_TypeDef *) UART7_BASE)
1166 #define UART8 ((USART_TypeDef *) UART8_BASE)
1167 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1168 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1169 #define USART1 ((USART_TypeDef *) USART1_BASE)
1170 #define USART6 ((USART_TypeDef *) USART6_BASE)
1171 #define UART9 ((USART_TypeDef *) UART9_BASE)
1172 #define UART10 ((USART_TypeDef *) UART10_BASE)
1173 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1174 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1175 /* Legacy define */
1176 #define ADC ADC1_COMMON
1177 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1178 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1179 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1180 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1181 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1182 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1183 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1184 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1185 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1186 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1187 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1188 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1189 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1190 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1191 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1192 #define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
1193 #define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
1194 #define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
1195 #define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
1196 #define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
1197 #define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
1198 #define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
1199 #define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
1200 #define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
1201 #define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
1202 #define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
1203 #define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
1204 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1205 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1206 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1207 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1208 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1209 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1210 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1211 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1212 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1213 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1214 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1215 #define CRC ((CRC_TypeDef *) CRC_BASE)
1216 #define RCC ((RCC_TypeDef *) RCC_BASE)
1217 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1218 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1219 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1220 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1221 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1222 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1223 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1224 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1225 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1226 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1227 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1228 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1229 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1230 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1231 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1232 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1233 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1234 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1235 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1236 #define AES ((AES_TypeDef *) AES_BASE)
1237 #define RNG ((RNG_TypeDef *) RNG_BASE)
1238 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1239 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1240 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1241 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1242 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1243
1244 /**
1245 * @}
1246 */
1247
1248 /** @addtogroup Exported_constants
1249 * @{
1250 */
1251
1252 /** @addtogroup Peripheral_Registers_Bits_Definition
1253 * @{
1254 */
1255
1256 /******************************************************************************/
1257 /* Peripheral Registers_Bits_Definition */
1258 /******************************************************************************/
1259
1260 /******************************************************************************/
1261 /* */
1262 /* Analog to Digital Converter */
1263 /* */
1264 /******************************************************************************/
1265
1266 /******************** Bit definition for ADC_SR register ********************/
1267 #define ADC_SR_AWD_Pos (0U)
1268 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1269 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1270 #define ADC_SR_EOC_Pos (1U)
1271 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1272 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1273 #define ADC_SR_JEOC_Pos (2U)
1274 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1275 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1276 #define ADC_SR_JSTRT_Pos (3U)
1277 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1278 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1279 #define ADC_SR_STRT_Pos (4U)
1280 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1281 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1282 #define ADC_SR_OVR_Pos (5U)
1283 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1284 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1285
1286 /******************* Bit definition for ADC_CR1 register ********************/
1287 #define ADC_CR1_AWDCH_Pos (0U)
1288 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1289 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1290 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1291 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1292 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1293 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1294 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1295 #define ADC_CR1_EOCIE_Pos (5U)
1296 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1297 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1298 #define ADC_CR1_AWDIE_Pos (6U)
1299 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1300 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1301 #define ADC_CR1_JEOCIE_Pos (7U)
1302 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1303 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1304 #define ADC_CR1_SCAN_Pos (8U)
1305 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1306 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1307 #define ADC_CR1_AWDSGL_Pos (9U)
1308 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1309 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1310 #define ADC_CR1_JAUTO_Pos (10U)
1311 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1312 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1313 #define ADC_CR1_DISCEN_Pos (11U)
1314 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1315 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1316 #define ADC_CR1_JDISCEN_Pos (12U)
1317 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1318 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1319 #define ADC_CR1_DISCNUM_Pos (13U)
1320 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1321 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1322 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1323 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1324 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1325 #define ADC_CR1_JAWDEN_Pos (22U)
1326 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1327 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1328 #define ADC_CR1_AWDEN_Pos (23U)
1329 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1330 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1331 #define ADC_CR1_RES_Pos (24U)
1332 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1333 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1334 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1335 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1336 #define ADC_CR1_OVRIE_Pos (26U)
1337 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1338 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1339
1340 /******************* Bit definition for ADC_CR2 register ********************/
1341 #define ADC_CR2_ADON_Pos (0U)
1342 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1343 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1344 #define ADC_CR2_CONT_Pos (1U)
1345 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1346 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1347 #define ADC_CR2_DMA_Pos (8U)
1348 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1349 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1350 #define ADC_CR2_DDS_Pos (9U)
1351 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1352 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1353 #define ADC_CR2_EOCS_Pos (10U)
1354 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1355 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1356 #define ADC_CR2_ALIGN_Pos (11U)
1357 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1358 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1359 #define ADC_CR2_JEXTSEL_Pos (16U)
1360 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1361 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1362 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1363 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1364 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1365 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1366 #define ADC_CR2_JEXTEN_Pos (20U)
1367 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1368 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1369 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1370 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1371 #define ADC_CR2_JSWSTART_Pos (22U)
1372 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1373 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1374 #define ADC_CR2_EXTSEL_Pos (24U)
1375 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1376 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1377 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1378 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1379 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1380 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1381 #define ADC_CR2_EXTEN_Pos (28U)
1382 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1383 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1384 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1385 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1386 #define ADC_CR2_SWSTART_Pos (30U)
1387 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1388 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1389
1390 /****************** Bit definition for ADC_SMPR1 register *******************/
1391 #define ADC_SMPR1_SMP10_Pos (0U)
1392 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1393 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1394 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1395 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1396 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1397 #define ADC_SMPR1_SMP11_Pos (3U)
1398 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1399 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1400 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1401 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1402 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1403 #define ADC_SMPR1_SMP12_Pos (6U)
1404 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1405 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1406 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1407 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1408 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1409 #define ADC_SMPR1_SMP13_Pos (9U)
1410 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1411 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1412 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1413 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1414 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1415 #define ADC_SMPR1_SMP14_Pos (12U)
1416 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1417 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1418 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1419 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1420 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1421 #define ADC_SMPR1_SMP15_Pos (15U)
1422 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1423 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1424 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1425 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1426 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1427 #define ADC_SMPR1_SMP16_Pos (18U)
1428 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1429 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1430 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1431 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1432 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1433 #define ADC_SMPR1_SMP17_Pos (21U)
1434 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1435 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1436 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1437 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1438 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1439 #define ADC_SMPR1_SMP18_Pos (24U)
1440 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1441 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1442 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1443 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1444 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1445
1446 /****************** Bit definition for ADC_SMPR2 register *******************/
1447 #define ADC_SMPR2_SMP0_Pos (0U)
1448 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1449 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1450 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1451 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1452 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1453 #define ADC_SMPR2_SMP1_Pos (3U)
1454 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1455 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1456 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1457 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1458 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1459 #define ADC_SMPR2_SMP2_Pos (6U)
1460 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1461 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1462 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1463 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1464 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1465 #define ADC_SMPR2_SMP3_Pos (9U)
1466 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1467 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1468 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1469 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1470 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1471 #define ADC_SMPR2_SMP4_Pos (12U)
1472 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1473 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1474 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1475 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1476 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1477 #define ADC_SMPR2_SMP5_Pos (15U)
1478 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1479 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1480 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1481 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1482 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1483 #define ADC_SMPR2_SMP6_Pos (18U)
1484 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1485 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1486 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1487 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1488 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1489 #define ADC_SMPR2_SMP7_Pos (21U)
1490 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1491 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1492 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1493 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1494 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1495 #define ADC_SMPR2_SMP8_Pos (24U)
1496 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1497 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1498 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1499 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1500 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1501 #define ADC_SMPR2_SMP9_Pos (27U)
1502 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1503 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1504 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1505 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1506 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1507
1508 /****************** Bit definition for ADC_JOFR1 register *******************/
1509 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1510 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1511 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1512
1513 /****************** Bit definition for ADC_JOFR2 register *******************/
1514 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1515 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1516 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1517
1518 /****************** Bit definition for ADC_JOFR3 register *******************/
1519 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1520 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1521 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1522
1523 /****************** Bit definition for ADC_JOFR4 register *******************/
1524 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1525 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1526 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1527
1528 /******************* Bit definition for ADC_HTR register ********************/
1529 #define ADC_HTR_HT_Pos (0U)
1530 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1531 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1532
1533 /******************* Bit definition for ADC_LTR register ********************/
1534 #define ADC_LTR_LT_Pos (0U)
1535 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1536 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1537
1538 /******************* Bit definition for ADC_SQR1 register *******************/
1539 #define ADC_SQR1_SQ13_Pos (0U)
1540 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1541 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1542 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1543 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1544 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1545 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1546 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1547 #define ADC_SQR1_SQ14_Pos (5U)
1548 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1549 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1550 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1551 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1552 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1553 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1554 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1555 #define ADC_SQR1_SQ15_Pos (10U)
1556 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1557 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1558 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1559 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1560 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1561 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1562 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1563 #define ADC_SQR1_SQ16_Pos (15U)
1564 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1565 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1566 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1567 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1568 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1569 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1570 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1571 #define ADC_SQR1_L_Pos (20U)
1572 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1573 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1574 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1575 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1576 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1577 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1578
1579 /******************* Bit definition for ADC_SQR2 register *******************/
1580 #define ADC_SQR2_SQ7_Pos (0U)
1581 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1582 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1583 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1584 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1585 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1586 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1587 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1588 #define ADC_SQR2_SQ8_Pos (5U)
1589 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1590 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1591 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1592 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1593 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1594 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1595 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1596 #define ADC_SQR2_SQ9_Pos (10U)
1597 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1598 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1599 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1600 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1601 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1602 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1603 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1604 #define ADC_SQR2_SQ10_Pos (15U)
1605 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1606 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1607 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1608 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1609 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1610 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1611 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1612 #define ADC_SQR2_SQ11_Pos (20U)
1613 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1614 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1615 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1616 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1617 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1618 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1619 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1620 #define ADC_SQR2_SQ12_Pos (25U)
1621 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1622 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1623 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1624 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1625 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1626 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1627 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1628
1629 /******************* Bit definition for ADC_SQR3 register *******************/
1630 #define ADC_SQR3_SQ1_Pos (0U)
1631 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1632 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1633 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1634 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1635 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1636 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1637 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1638 #define ADC_SQR3_SQ2_Pos (5U)
1639 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1640 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1641 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1642 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1643 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1644 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1645 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1646 #define ADC_SQR3_SQ3_Pos (10U)
1647 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1648 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1649 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1650 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1651 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1652 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1653 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1654 #define ADC_SQR3_SQ4_Pos (15U)
1655 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1656 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1657 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1658 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1659 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1660 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1661 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1662 #define ADC_SQR3_SQ5_Pos (20U)
1663 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1664 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1665 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1666 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1667 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1668 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1669 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1670 #define ADC_SQR3_SQ6_Pos (25U)
1671 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1672 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1673 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1674 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1675 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1676 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1677 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1678
1679 /******************* Bit definition for ADC_JSQR register *******************/
1680 #define ADC_JSQR_JSQ1_Pos (0U)
1681 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1682 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1683 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1684 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1685 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1686 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1687 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1688 #define ADC_JSQR_JSQ2_Pos (5U)
1689 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1690 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1691 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1692 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1693 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1694 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1695 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1696 #define ADC_JSQR_JSQ3_Pos (10U)
1697 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1698 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1699 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1700 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1701 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1702 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1703 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1704 #define ADC_JSQR_JSQ4_Pos (15U)
1705 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1706 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1707 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1708 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1709 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1710 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1711 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1712 #define ADC_JSQR_JL_Pos (20U)
1713 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1714 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1715 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1716 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1717
1718 /******************* Bit definition for ADC_JDR1 register *******************/
1719 #define ADC_JDR1_JDATA_Pos (0U)
1720 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1721 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1722
1723 /******************* Bit definition for ADC_JDR2 register *******************/
1724 #define ADC_JDR2_JDATA_Pos (0U)
1725 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1726 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1727
1728 /******************* Bit definition for ADC_JDR3 register *******************/
1729 #define ADC_JDR3_JDATA_Pos (0U)
1730 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1731 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1732
1733 /******************* Bit definition for ADC_JDR4 register *******************/
1734 #define ADC_JDR4_JDATA_Pos (0U)
1735 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1736 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1737
1738 /******************** Bit definition for ADC_DR register ********************/
1739 #define ADC_DR_DATA_Pos (0U)
1740 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1741 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1742 #define ADC_DR_ADC2DATA_Pos (16U)
1743 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1744 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1745
1746 /******************* Bit definition for ADC_CSR register ********************/
1747 #define ADC_CSR_AWD1_Pos (0U)
1748 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1749 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1750 #define ADC_CSR_EOC1_Pos (1U)
1751 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1752 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1753 #define ADC_CSR_JEOC1_Pos (2U)
1754 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1755 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1756 #define ADC_CSR_JSTRT1_Pos (3U)
1757 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1758 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1759 #define ADC_CSR_STRT1_Pos (4U)
1760 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1761 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1762 #define ADC_CSR_OVR1_Pos (5U)
1763 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1764 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1765
1766 /* Legacy defines */
1767 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1768
1769 /******************* Bit definition for ADC_CCR register ********************/
1770 #define ADC_CCR_MULTI_Pos (0U)
1771 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1772 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1773 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1774 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1775 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1776 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1777 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1778 #define ADC_CCR_DELAY_Pos (8U)
1779 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1780 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1781 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1782 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1783 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1784 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1785 #define ADC_CCR_DDS_Pos (13U)
1786 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1787 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1788 #define ADC_CCR_DMA_Pos (14U)
1789 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1790 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1791 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1792 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1793 #define ADC_CCR_ADCPRE_Pos (16U)
1794 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1795 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1796 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1797 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1798 #define ADC_CCR_VBATE_Pos (22U)
1799 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1800 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1801 #define ADC_CCR_TSVREFE_Pos (23U)
1802 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1803 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1804
1805 /******************* Bit definition for ADC_CDR register ********************/
1806 #define ADC_CDR_DATA1_Pos (0U)
1807 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1808 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1809 #define ADC_CDR_DATA2_Pos (16U)
1810 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1811 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1812
1813 /* Legacy defines */
1814 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1815 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1816
1817 /******************************************************************************/
1818 /* */
1819 /* Controller Area Network */
1820 /* */
1821 /******************************************************************************/
1822 /*!<CAN control and status registers */
1823 /******************* Bit definition for CAN_MCR register ********************/
1824 #define CAN_MCR_INRQ_Pos (0U)
1825 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
1826 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
1827 #define CAN_MCR_SLEEP_Pos (1U)
1828 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
1829 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
1830 #define CAN_MCR_TXFP_Pos (2U)
1831 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
1832 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
1833 #define CAN_MCR_RFLM_Pos (3U)
1834 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
1835 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
1836 #define CAN_MCR_NART_Pos (4U)
1837 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
1838 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
1839 #define CAN_MCR_AWUM_Pos (5U)
1840 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
1841 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
1842 #define CAN_MCR_ABOM_Pos (6U)
1843 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
1844 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
1845 #define CAN_MCR_TTCM_Pos (7U)
1846 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
1847 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
1848 #define CAN_MCR_RESET_Pos (15U)
1849 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
1850 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
1851 #define CAN_MCR_DBF_Pos (16U)
1852 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
1853 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
1854 /******************* Bit definition for CAN_MSR register ********************/
1855 #define CAN_MSR_INAK_Pos (0U)
1856 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
1857 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
1858 #define CAN_MSR_SLAK_Pos (1U)
1859 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
1860 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
1861 #define CAN_MSR_ERRI_Pos (2U)
1862 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
1863 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
1864 #define CAN_MSR_WKUI_Pos (3U)
1865 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
1866 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
1867 #define CAN_MSR_SLAKI_Pos (4U)
1868 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
1869 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
1870 #define CAN_MSR_TXM_Pos (8U)
1871 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
1872 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
1873 #define CAN_MSR_RXM_Pos (9U)
1874 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
1875 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
1876 #define CAN_MSR_SAMP_Pos (10U)
1877 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
1878 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
1879 #define CAN_MSR_RX_Pos (11U)
1880 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
1881 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
1882
1883 /******************* Bit definition for CAN_TSR register ********************/
1884 #define CAN_TSR_RQCP0_Pos (0U)
1885 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
1886 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
1887 #define CAN_TSR_TXOK0_Pos (1U)
1888 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
1889 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
1890 #define CAN_TSR_ALST0_Pos (2U)
1891 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
1892 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
1893 #define CAN_TSR_TERR0_Pos (3U)
1894 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
1895 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
1896 #define CAN_TSR_ABRQ0_Pos (7U)
1897 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
1898 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
1899 #define CAN_TSR_RQCP1_Pos (8U)
1900 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
1901 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
1902 #define CAN_TSR_TXOK1_Pos (9U)
1903 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
1904 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
1905 #define CAN_TSR_ALST1_Pos (10U)
1906 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
1907 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
1908 #define CAN_TSR_TERR1_Pos (11U)
1909 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
1910 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
1911 #define CAN_TSR_ABRQ1_Pos (15U)
1912 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
1913 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
1914 #define CAN_TSR_RQCP2_Pos (16U)
1915 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
1916 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
1917 #define CAN_TSR_TXOK2_Pos (17U)
1918 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
1919 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
1920 #define CAN_TSR_ALST2_Pos (18U)
1921 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
1922 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
1923 #define CAN_TSR_TERR2_Pos (19U)
1924 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
1925 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
1926 #define CAN_TSR_ABRQ2_Pos (23U)
1927 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
1928 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
1929 #define CAN_TSR_CODE_Pos (24U)
1930 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
1931 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
1932
1933 #define CAN_TSR_TME_Pos (26U)
1934 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
1935 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
1936 #define CAN_TSR_TME0_Pos (26U)
1937 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
1938 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
1939 #define CAN_TSR_TME1_Pos (27U)
1940 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
1941 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
1942 #define CAN_TSR_TME2_Pos (28U)
1943 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
1944 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
1945
1946 #define CAN_TSR_LOW_Pos (29U)
1947 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
1948 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
1949 #define CAN_TSR_LOW0_Pos (29U)
1950 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
1951 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
1952 #define CAN_TSR_LOW1_Pos (30U)
1953 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
1954 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
1955 #define CAN_TSR_LOW2_Pos (31U)
1956 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
1957 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
1958
1959 /******************* Bit definition for CAN_RF0R register *******************/
1960 #define CAN_RF0R_FMP0_Pos (0U)
1961 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
1962 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
1963 #define CAN_RF0R_FULL0_Pos (3U)
1964 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
1965 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
1966 #define CAN_RF0R_FOVR0_Pos (4U)
1967 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
1968 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
1969 #define CAN_RF0R_RFOM0_Pos (5U)
1970 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
1971 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
1972
1973 /******************* Bit definition for CAN_RF1R register *******************/
1974 #define CAN_RF1R_FMP1_Pos (0U)
1975 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
1976 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
1977 #define CAN_RF1R_FULL1_Pos (3U)
1978 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
1979 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
1980 #define CAN_RF1R_FOVR1_Pos (4U)
1981 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
1982 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
1983 #define CAN_RF1R_RFOM1_Pos (5U)
1984 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
1985 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
1986
1987 /******************** Bit definition for CAN_IER register *******************/
1988 #define CAN_IER_TMEIE_Pos (0U)
1989 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
1990 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
1991 #define CAN_IER_FMPIE0_Pos (1U)
1992 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
1993 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
1994 #define CAN_IER_FFIE0_Pos (2U)
1995 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
1996 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
1997 #define CAN_IER_FOVIE0_Pos (3U)
1998 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
1999 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2000 #define CAN_IER_FMPIE1_Pos (4U)
2001 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2002 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2003 #define CAN_IER_FFIE1_Pos (5U)
2004 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2005 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2006 #define CAN_IER_FOVIE1_Pos (6U)
2007 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2008 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2009 #define CAN_IER_EWGIE_Pos (8U)
2010 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2011 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2012 #define CAN_IER_EPVIE_Pos (9U)
2013 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2014 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2015 #define CAN_IER_BOFIE_Pos (10U)
2016 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2017 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2018 #define CAN_IER_LECIE_Pos (11U)
2019 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2020 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2021 #define CAN_IER_ERRIE_Pos (15U)
2022 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2023 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2024 #define CAN_IER_WKUIE_Pos (16U)
2025 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2026 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2027 #define CAN_IER_SLKIE_Pos (17U)
2028 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2029 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2030 #define CAN_IER_EWGIE_Pos (8U)
2031
2032 /******************** Bit definition for CAN_ESR register *******************/
2033 #define CAN_ESR_EWGF_Pos (0U)
2034 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2035 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2036 #define CAN_ESR_EPVF_Pos (1U)
2037 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2038 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2039 #define CAN_ESR_BOFF_Pos (2U)
2040 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2041 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2042
2043 #define CAN_ESR_LEC_Pos (4U)
2044 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2045 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2046 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2047 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2048 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2049
2050 #define CAN_ESR_TEC_Pos (16U)
2051 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2052 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2053 #define CAN_ESR_REC_Pos (24U)
2054 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2055 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2056
2057 /******************* Bit definition for CAN_BTR register ********************/
2058 #define CAN_BTR_BRP_Pos (0U)
2059 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2060 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2061 #define CAN_BTR_TS1_Pos (16U)
2062 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2063 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2064 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2065 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2066 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2067 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2068 #define CAN_BTR_TS2_Pos (20U)
2069 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2070 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2071 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2072 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2073 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2074 #define CAN_BTR_SJW_Pos (24U)
2075 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2076 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2077 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2078 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2079 #define CAN_BTR_LBKM_Pos (30U)
2080 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2081 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2082 #define CAN_BTR_SILM_Pos (31U)
2083 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2084 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2085
2086
2087 /*!<Mailbox registers */
2088 /****************** Bit definition for CAN_TI0R register ********************/
2089 #define CAN_TI0R_TXRQ_Pos (0U)
2090 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2091 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2092 #define CAN_TI0R_RTR_Pos (1U)
2093 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2094 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2095 #define CAN_TI0R_IDE_Pos (2U)
2096 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2097 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2098 #define CAN_TI0R_EXID_Pos (3U)
2099 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2100 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2101 #define CAN_TI0R_STID_Pos (21U)
2102 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2103 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2104
2105 /****************** Bit definition for CAN_TDT0R register *******************/
2106 #define CAN_TDT0R_DLC_Pos (0U)
2107 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2108 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2109 #define CAN_TDT0R_TGT_Pos (8U)
2110 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2111 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2112 #define CAN_TDT0R_TIME_Pos (16U)
2113 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2114 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2115
2116 /****************** Bit definition for CAN_TDL0R register *******************/
2117 #define CAN_TDL0R_DATA0_Pos (0U)
2118 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2119 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2120 #define CAN_TDL0R_DATA1_Pos (8U)
2121 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2122 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2123 #define CAN_TDL0R_DATA2_Pos (16U)
2124 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2125 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2126 #define CAN_TDL0R_DATA3_Pos (24U)
2127 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2128 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2129
2130 /****************** Bit definition for CAN_TDH0R register *******************/
2131 #define CAN_TDH0R_DATA4_Pos (0U)
2132 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2133 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2134 #define CAN_TDH0R_DATA5_Pos (8U)
2135 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2136 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2137 #define CAN_TDH0R_DATA6_Pos (16U)
2138 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2139 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2140 #define CAN_TDH0R_DATA7_Pos (24U)
2141 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2142 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2143
2144 /******************* Bit definition for CAN_TI1R register *******************/
2145 #define CAN_TI1R_TXRQ_Pos (0U)
2146 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2147 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2148 #define CAN_TI1R_RTR_Pos (1U)
2149 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2150 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2151 #define CAN_TI1R_IDE_Pos (2U)
2152 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2153 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2154 #define CAN_TI1R_EXID_Pos (3U)
2155 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2156 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2157 #define CAN_TI1R_STID_Pos (21U)
2158 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2159 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2160
2161 /******************* Bit definition for CAN_TDT1R register ******************/
2162 #define CAN_TDT1R_DLC_Pos (0U)
2163 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2164 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2165 #define CAN_TDT1R_TGT_Pos (8U)
2166 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2167 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2168 #define CAN_TDT1R_TIME_Pos (16U)
2169 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2170 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2171
2172 /******************* Bit definition for CAN_TDL1R register ******************/
2173 #define CAN_TDL1R_DATA0_Pos (0U)
2174 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2175 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2176 #define CAN_TDL1R_DATA1_Pos (8U)
2177 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2178 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2179 #define CAN_TDL1R_DATA2_Pos (16U)
2180 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2181 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2182 #define CAN_TDL1R_DATA3_Pos (24U)
2183 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2184 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2185
2186 /******************* Bit definition for CAN_TDH1R register ******************/
2187 #define CAN_TDH1R_DATA4_Pos (0U)
2188 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2189 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2190 #define CAN_TDH1R_DATA5_Pos (8U)
2191 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2192 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2193 #define CAN_TDH1R_DATA6_Pos (16U)
2194 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2195 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2196 #define CAN_TDH1R_DATA7_Pos (24U)
2197 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2198 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2199
2200 /******************* Bit definition for CAN_TI2R register *******************/
2201 #define CAN_TI2R_TXRQ_Pos (0U)
2202 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2203 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2204 #define CAN_TI2R_RTR_Pos (1U)
2205 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2206 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2207 #define CAN_TI2R_IDE_Pos (2U)
2208 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2209 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2210 #define CAN_TI2R_EXID_Pos (3U)
2211 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2212 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2213 #define CAN_TI2R_STID_Pos (21U)
2214 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2215 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2216
2217 /******************* Bit definition for CAN_TDT2R register ******************/
2218 #define CAN_TDT2R_DLC_Pos (0U)
2219 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2220 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2221 #define CAN_TDT2R_TGT_Pos (8U)
2222 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2223 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2224 #define CAN_TDT2R_TIME_Pos (16U)
2225 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2226 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2227
2228 /******************* Bit definition for CAN_TDL2R register ******************/
2229 #define CAN_TDL2R_DATA0_Pos (0U)
2230 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2231 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2232 #define CAN_TDL2R_DATA1_Pos (8U)
2233 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2234 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2235 #define CAN_TDL2R_DATA2_Pos (16U)
2236 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2237 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2238 #define CAN_TDL2R_DATA3_Pos (24U)
2239 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2240 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2241
2242 /******************* Bit definition for CAN_TDH2R register ******************/
2243 #define CAN_TDH2R_DATA4_Pos (0U)
2244 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2245 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2246 #define CAN_TDH2R_DATA5_Pos (8U)
2247 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2248 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2249 #define CAN_TDH2R_DATA6_Pos (16U)
2250 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2251 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2252 #define CAN_TDH2R_DATA7_Pos (24U)
2253 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2254 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2255
2256 /******************* Bit definition for CAN_RI0R register *******************/
2257 #define CAN_RI0R_RTR_Pos (1U)
2258 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2259 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2260 #define CAN_RI0R_IDE_Pos (2U)
2261 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2262 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2263 #define CAN_RI0R_EXID_Pos (3U)
2264 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2265 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2266 #define CAN_RI0R_STID_Pos (21U)
2267 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2268 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2269
2270 /******************* Bit definition for CAN_RDT0R register ******************/
2271 #define CAN_RDT0R_DLC_Pos (0U)
2272 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2273 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2274 #define CAN_RDT0R_FMI_Pos (8U)
2275 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2276 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2277 #define CAN_RDT0R_TIME_Pos (16U)
2278 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2279 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2280
2281 /******************* Bit definition for CAN_RDL0R register ******************/
2282 #define CAN_RDL0R_DATA0_Pos (0U)
2283 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2284 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2285 #define CAN_RDL0R_DATA1_Pos (8U)
2286 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2287 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2288 #define CAN_RDL0R_DATA2_Pos (16U)
2289 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2290 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2291 #define CAN_RDL0R_DATA3_Pos (24U)
2292 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2293 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2294
2295 /******************* Bit definition for CAN_RDH0R register ******************/
2296 #define CAN_RDH0R_DATA4_Pos (0U)
2297 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2298 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2299 #define CAN_RDH0R_DATA5_Pos (8U)
2300 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2301 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2302 #define CAN_RDH0R_DATA6_Pos (16U)
2303 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2304 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2305 #define CAN_RDH0R_DATA7_Pos (24U)
2306 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2307 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2308
2309 /******************* Bit definition for CAN_RI1R register *******************/
2310 #define CAN_RI1R_RTR_Pos (1U)
2311 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2312 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2313 #define CAN_RI1R_IDE_Pos (2U)
2314 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2315 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2316 #define CAN_RI1R_EXID_Pos (3U)
2317 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2318 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2319 #define CAN_RI1R_STID_Pos (21U)
2320 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2321 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2322
2323 /******************* Bit definition for CAN_RDT1R register ******************/
2324 #define CAN_RDT1R_DLC_Pos (0U)
2325 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2326 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2327 #define CAN_RDT1R_FMI_Pos (8U)
2328 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2329 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2330 #define CAN_RDT1R_TIME_Pos (16U)
2331 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2332 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2333
2334 /******************* Bit definition for CAN_RDL1R register ******************/
2335 #define CAN_RDL1R_DATA0_Pos (0U)
2336 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2337 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2338 #define CAN_RDL1R_DATA1_Pos (8U)
2339 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2340 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2341 #define CAN_RDL1R_DATA2_Pos (16U)
2342 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2343 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2344 #define CAN_RDL1R_DATA3_Pos (24U)
2345 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2346 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2347
2348 /******************* Bit definition for CAN_RDH1R register ******************/
2349 #define CAN_RDH1R_DATA4_Pos (0U)
2350 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2351 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2352 #define CAN_RDH1R_DATA5_Pos (8U)
2353 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2354 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2355 #define CAN_RDH1R_DATA6_Pos (16U)
2356 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2357 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2358 #define CAN_RDH1R_DATA7_Pos (24U)
2359 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2360 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2361
2362 /*!<CAN filter registers */
2363 /******************* Bit definition for CAN_FMR register ********************/
2364 #define CAN_FMR_FINIT_Pos (0U)
2365 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2366 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2367 #define CAN_FMR_CAN2SB_Pos (8U)
2368 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2369 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2370
2371 /******************* Bit definition for CAN_FM1R register *******************/
2372 #define CAN_FM1R_FBM_Pos (0U)
2373 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2374 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2375 #define CAN_FM1R_FBM0_Pos (0U)
2376 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2377 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2378 #define CAN_FM1R_FBM1_Pos (1U)
2379 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2380 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2381 #define CAN_FM1R_FBM2_Pos (2U)
2382 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2383 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2384 #define CAN_FM1R_FBM3_Pos (3U)
2385 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2386 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2387 #define CAN_FM1R_FBM4_Pos (4U)
2388 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2389 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2390 #define CAN_FM1R_FBM5_Pos (5U)
2391 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2392 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2393 #define CAN_FM1R_FBM6_Pos (6U)
2394 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2395 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2396 #define CAN_FM1R_FBM7_Pos (7U)
2397 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2398 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2399 #define CAN_FM1R_FBM8_Pos (8U)
2400 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2401 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2402 #define CAN_FM1R_FBM9_Pos (9U)
2403 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2404 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2405 #define CAN_FM1R_FBM10_Pos (10U)
2406 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2407 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2408 #define CAN_FM1R_FBM11_Pos (11U)
2409 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2410 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2411 #define CAN_FM1R_FBM12_Pos (12U)
2412 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2413 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2414 #define CAN_FM1R_FBM13_Pos (13U)
2415 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2416 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2417 #define CAN_FM1R_FBM14_Pos (14U)
2418 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2419 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2420 #define CAN_FM1R_FBM15_Pos (15U)
2421 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2422 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2423 #define CAN_FM1R_FBM16_Pos (16U)
2424 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2425 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2426 #define CAN_FM1R_FBM17_Pos (17U)
2427 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2428 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2429 #define CAN_FM1R_FBM18_Pos (18U)
2430 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2431 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2432 #define CAN_FM1R_FBM19_Pos (19U)
2433 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2434 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2435 #define CAN_FM1R_FBM20_Pos (20U)
2436 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2437 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2438 #define CAN_FM1R_FBM21_Pos (21U)
2439 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2440 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2441 #define CAN_FM1R_FBM22_Pos (22U)
2442 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2443 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2444 #define CAN_FM1R_FBM23_Pos (23U)
2445 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2446 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2447 #define CAN_FM1R_FBM24_Pos (24U)
2448 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2449 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2450 #define CAN_FM1R_FBM25_Pos (25U)
2451 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2452 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2453 #define CAN_FM1R_FBM26_Pos (26U)
2454 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2455 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2456 #define CAN_FM1R_FBM27_Pos (27U)
2457 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2458 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2459
2460 /******************* Bit definition for CAN_FS1R register *******************/
2461 #define CAN_FS1R_FSC_Pos (0U)
2462 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2463 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2464 #define CAN_FS1R_FSC0_Pos (0U)
2465 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2466 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2467 #define CAN_FS1R_FSC1_Pos (1U)
2468 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2469 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2470 #define CAN_FS1R_FSC2_Pos (2U)
2471 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2472 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2473 #define CAN_FS1R_FSC3_Pos (3U)
2474 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2475 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2476 #define CAN_FS1R_FSC4_Pos (4U)
2477 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2478 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2479 #define CAN_FS1R_FSC5_Pos (5U)
2480 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2481 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2482 #define CAN_FS1R_FSC6_Pos (6U)
2483 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2484 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2485 #define CAN_FS1R_FSC7_Pos (7U)
2486 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2487 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2488 #define CAN_FS1R_FSC8_Pos (8U)
2489 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2490 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2491 #define CAN_FS1R_FSC9_Pos (9U)
2492 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2493 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2494 #define CAN_FS1R_FSC10_Pos (10U)
2495 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2496 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2497 #define CAN_FS1R_FSC11_Pos (11U)
2498 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2499 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2500 #define CAN_FS1R_FSC12_Pos (12U)
2501 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2502 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2503 #define CAN_FS1R_FSC13_Pos (13U)
2504 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2505 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2506 #define CAN_FS1R_FSC14_Pos (14U)
2507 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2508 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2509 #define CAN_FS1R_FSC15_Pos (15U)
2510 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2511 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2512 #define CAN_FS1R_FSC16_Pos (16U)
2513 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2514 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2515 #define CAN_FS1R_FSC17_Pos (17U)
2516 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2517 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2518 #define CAN_FS1R_FSC18_Pos (18U)
2519 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2520 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2521 #define CAN_FS1R_FSC19_Pos (19U)
2522 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2523 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2524 #define CAN_FS1R_FSC20_Pos (20U)
2525 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2526 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2527 #define CAN_FS1R_FSC21_Pos (21U)
2528 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2529 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2530 #define CAN_FS1R_FSC22_Pos (22U)
2531 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2532 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2533 #define CAN_FS1R_FSC23_Pos (23U)
2534 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2535 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2536 #define CAN_FS1R_FSC24_Pos (24U)
2537 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2538 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2539 #define CAN_FS1R_FSC25_Pos (25U)
2540 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2541 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2542 #define CAN_FS1R_FSC26_Pos (26U)
2543 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2544 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2545 #define CAN_FS1R_FSC27_Pos (27U)
2546 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2547 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2548
2549 /****************** Bit definition for CAN_FFA1R register *******************/
2550 #define CAN_FFA1R_FFA_Pos (0U)
2551 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2552 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2553 #define CAN_FFA1R_FFA0_Pos (0U)
2554 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2555 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2556 #define CAN_FFA1R_FFA1_Pos (1U)
2557 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2558 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2559 #define CAN_FFA1R_FFA2_Pos (2U)
2560 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2561 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2562 #define CAN_FFA1R_FFA3_Pos (3U)
2563 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2564 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2565 #define CAN_FFA1R_FFA4_Pos (4U)
2566 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2567 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2568 #define CAN_FFA1R_FFA5_Pos (5U)
2569 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2570 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2571 #define CAN_FFA1R_FFA6_Pos (6U)
2572 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2573 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2574 #define CAN_FFA1R_FFA7_Pos (7U)
2575 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2576 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2577 #define CAN_FFA1R_FFA8_Pos (8U)
2578 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2579 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2580 #define CAN_FFA1R_FFA9_Pos (9U)
2581 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2582 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2583 #define CAN_FFA1R_FFA10_Pos (10U)
2584 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2585 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2586 #define CAN_FFA1R_FFA11_Pos (11U)
2587 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2588 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2589 #define CAN_FFA1R_FFA12_Pos (12U)
2590 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2591 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2592 #define CAN_FFA1R_FFA13_Pos (13U)
2593 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2594 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2595 #define CAN_FFA1R_FFA14_Pos (14U)
2596 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2597 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2598 #define CAN_FFA1R_FFA15_Pos (15U)
2599 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2600 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2601 #define CAN_FFA1R_FFA16_Pos (16U)
2602 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2603 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2604 #define CAN_FFA1R_FFA17_Pos (17U)
2605 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2606 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2607 #define CAN_FFA1R_FFA18_Pos (18U)
2608 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2609 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2610 #define CAN_FFA1R_FFA19_Pos (19U)
2611 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2612 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2613 #define CAN_FFA1R_FFA20_Pos (20U)
2614 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2615 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2616 #define CAN_FFA1R_FFA21_Pos (21U)
2617 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2618 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2619 #define CAN_FFA1R_FFA22_Pos (22U)
2620 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2621 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2622 #define CAN_FFA1R_FFA23_Pos (23U)
2623 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2624 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2625 #define CAN_FFA1R_FFA24_Pos (24U)
2626 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2627 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2628 #define CAN_FFA1R_FFA25_Pos (25U)
2629 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2630 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2631 #define CAN_FFA1R_FFA26_Pos (26U)
2632 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2633 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2634 #define CAN_FFA1R_FFA27_Pos (27U)
2635 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2636 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2637
2638 /******************* Bit definition for CAN_FA1R register *******************/
2639 #define CAN_FA1R_FACT_Pos (0U)
2640 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2641 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2642 #define CAN_FA1R_FACT0_Pos (0U)
2643 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2644 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2645 #define CAN_FA1R_FACT1_Pos (1U)
2646 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2647 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2648 #define CAN_FA1R_FACT2_Pos (2U)
2649 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2650 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2651 #define CAN_FA1R_FACT3_Pos (3U)
2652 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2653 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2654 #define CAN_FA1R_FACT4_Pos (4U)
2655 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2656 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2657 #define CAN_FA1R_FACT5_Pos (5U)
2658 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2659 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2660 #define CAN_FA1R_FACT6_Pos (6U)
2661 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2662 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2663 #define CAN_FA1R_FACT7_Pos (7U)
2664 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2665 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2666 #define CAN_FA1R_FACT8_Pos (8U)
2667 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2668 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2669 #define CAN_FA1R_FACT9_Pos (9U)
2670 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2671 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2672 #define CAN_FA1R_FACT10_Pos (10U)
2673 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2674 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2675 #define CAN_FA1R_FACT11_Pos (11U)
2676 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2677 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2678 #define CAN_FA1R_FACT12_Pos (12U)
2679 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2680 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2681 #define CAN_FA1R_FACT13_Pos (13U)
2682 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2683 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2684 #define CAN_FA1R_FACT14_Pos (14U)
2685 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2686 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2687 #define CAN_FA1R_FACT15_Pos (15U)
2688 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2689 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2690 #define CAN_FA1R_FACT16_Pos (16U)
2691 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2692 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2693 #define CAN_FA1R_FACT17_Pos (17U)
2694 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2695 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2696 #define CAN_FA1R_FACT18_Pos (18U)
2697 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2698 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2699 #define CAN_FA1R_FACT19_Pos (19U)
2700 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2701 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2702 #define CAN_FA1R_FACT20_Pos (20U)
2703 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2704 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2705 #define CAN_FA1R_FACT21_Pos (21U)
2706 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2707 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2708 #define CAN_FA1R_FACT22_Pos (22U)
2709 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2710 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2711 #define CAN_FA1R_FACT23_Pos (23U)
2712 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2713 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2714 #define CAN_FA1R_FACT24_Pos (24U)
2715 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2716 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2717 #define CAN_FA1R_FACT25_Pos (25U)
2718 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2719 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2720 #define CAN_FA1R_FACT26_Pos (26U)
2721 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2722 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
2723 #define CAN_FA1R_FACT27_Pos (27U)
2724 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
2725 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
2726
2727
2728 /******************* Bit definition for CAN_F0R1 register *******************/
2729 #define CAN_F0R1_FB0_Pos (0U)
2730 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2731 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2732 #define CAN_F0R1_FB1_Pos (1U)
2733 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2734 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2735 #define CAN_F0R1_FB2_Pos (2U)
2736 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2737 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2738 #define CAN_F0R1_FB3_Pos (3U)
2739 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2740 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2741 #define CAN_F0R1_FB4_Pos (4U)
2742 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2743 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2744 #define CAN_F0R1_FB5_Pos (5U)
2745 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2746 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2747 #define CAN_F0R1_FB6_Pos (6U)
2748 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2749 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2750 #define CAN_F0R1_FB7_Pos (7U)
2751 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2752 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2753 #define CAN_F0R1_FB8_Pos (8U)
2754 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2755 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2756 #define CAN_F0R1_FB9_Pos (9U)
2757 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2758 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2759 #define CAN_F0R1_FB10_Pos (10U)
2760 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2761 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2762 #define CAN_F0R1_FB11_Pos (11U)
2763 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2764 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2765 #define CAN_F0R1_FB12_Pos (12U)
2766 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2767 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2768 #define CAN_F0R1_FB13_Pos (13U)
2769 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2770 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2771 #define CAN_F0R1_FB14_Pos (14U)
2772 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2773 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2774 #define CAN_F0R1_FB15_Pos (15U)
2775 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2776 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2777 #define CAN_F0R1_FB16_Pos (16U)
2778 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2779 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2780 #define CAN_F0R1_FB17_Pos (17U)
2781 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2782 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2783 #define CAN_F0R1_FB18_Pos (18U)
2784 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2785 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2786 #define CAN_F0R1_FB19_Pos (19U)
2787 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2788 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2789 #define CAN_F0R1_FB20_Pos (20U)
2790 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2791 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2792 #define CAN_F0R1_FB21_Pos (21U)
2793 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2794 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2795 #define CAN_F0R1_FB22_Pos (22U)
2796 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2797 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2798 #define CAN_F0R1_FB23_Pos (23U)
2799 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2800 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
2801 #define CAN_F0R1_FB24_Pos (24U)
2802 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
2803 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
2804 #define CAN_F0R1_FB25_Pos (25U)
2805 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
2806 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
2807 #define CAN_F0R1_FB26_Pos (26U)
2808 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
2809 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
2810 #define CAN_F0R1_FB27_Pos (27U)
2811 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
2812 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
2813 #define CAN_F0R1_FB28_Pos (28U)
2814 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
2815 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
2816 #define CAN_F0R1_FB29_Pos (29U)
2817 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
2818 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
2819 #define CAN_F0R1_FB30_Pos (30U)
2820 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
2821 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
2822 #define CAN_F0R1_FB31_Pos (31U)
2823 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
2824 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
2825
2826 /******************* Bit definition for CAN_F1R1 register *******************/
2827 #define CAN_F1R1_FB0_Pos (0U)
2828 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
2829 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
2830 #define CAN_F1R1_FB1_Pos (1U)
2831 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
2832 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
2833 #define CAN_F1R1_FB2_Pos (2U)
2834 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
2835 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
2836 #define CAN_F1R1_FB3_Pos (3U)
2837 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
2838 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
2839 #define CAN_F1R1_FB4_Pos (4U)
2840 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
2841 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
2842 #define CAN_F1R1_FB5_Pos (5U)
2843 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
2844 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
2845 #define CAN_F1R1_FB6_Pos (6U)
2846 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
2847 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
2848 #define CAN_F1R1_FB7_Pos (7U)
2849 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
2850 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
2851 #define CAN_F1R1_FB8_Pos (8U)
2852 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
2853 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
2854 #define CAN_F1R1_FB9_Pos (9U)
2855 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
2856 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
2857 #define CAN_F1R1_FB10_Pos (10U)
2858 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
2859 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
2860 #define CAN_F1R1_FB11_Pos (11U)
2861 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
2862 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
2863 #define CAN_F1R1_FB12_Pos (12U)
2864 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
2865 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
2866 #define CAN_F1R1_FB13_Pos (13U)
2867 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
2868 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
2869 #define CAN_F1R1_FB14_Pos (14U)
2870 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
2871 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
2872 #define CAN_F1R1_FB15_Pos (15U)
2873 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
2874 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
2875 #define CAN_F1R1_FB16_Pos (16U)
2876 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
2877 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
2878 #define CAN_F1R1_FB17_Pos (17U)
2879 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
2880 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
2881 #define CAN_F1R1_FB18_Pos (18U)
2882 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
2883 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
2884 #define CAN_F1R1_FB19_Pos (19U)
2885 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
2886 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
2887 #define CAN_F1R1_FB20_Pos (20U)
2888 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
2889 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
2890 #define CAN_F1R1_FB21_Pos (21U)
2891 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
2892 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
2893 #define CAN_F1R1_FB22_Pos (22U)
2894 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
2895 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
2896 #define CAN_F1R1_FB23_Pos (23U)
2897 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
2898 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
2899 #define CAN_F1R1_FB24_Pos (24U)
2900 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
2901 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
2902 #define CAN_F1R1_FB25_Pos (25U)
2903 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
2904 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
2905 #define CAN_F1R1_FB26_Pos (26U)
2906 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
2907 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
2908 #define CAN_F1R1_FB27_Pos (27U)
2909 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
2910 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
2911 #define CAN_F1R1_FB28_Pos (28U)
2912 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
2913 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
2914 #define CAN_F1R1_FB29_Pos (29U)
2915 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
2916 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
2917 #define CAN_F1R1_FB30_Pos (30U)
2918 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
2919 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
2920 #define CAN_F1R1_FB31_Pos (31U)
2921 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
2922 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
2923
2924 /******************* Bit definition for CAN_F2R1 register *******************/
2925 #define CAN_F2R1_FB0_Pos (0U)
2926 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
2927 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
2928 #define CAN_F2R1_FB1_Pos (1U)
2929 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
2930 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
2931 #define CAN_F2R1_FB2_Pos (2U)
2932 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
2933 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
2934 #define CAN_F2R1_FB3_Pos (3U)
2935 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
2936 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
2937 #define CAN_F2R1_FB4_Pos (4U)
2938 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
2939 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
2940 #define CAN_F2R1_FB5_Pos (5U)
2941 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
2942 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
2943 #define CAN_F2R1_FB6_Pos (6U)
2944 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
2945 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
2946 #define CAN_F2R1_FB7_Pos (7U)
2947 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
2948 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
2949 #define CAN_F2R1_FB8_Pos (8U)
2950 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
2951 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
2952 #define CAN_F2R1_FB9_Pos (9U)
2953 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
2954 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
2955 #define CAN_F2R1_FB10_Pos (10U)
2956 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
2957 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
2958 #define CAN_F2R1_FB11_Pos (11U)
2959 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
2960 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
2961 #define CAN_F2R1_FB12_Pos (12U)
2962 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
2963 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
2964 #define CAN_F2R1_FB13_Pos (13U)
2965 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
2966 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
2967 #define CAN_F2R1_FB14_Pos (14U)
2968 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
2969 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
2970 #define CAN_F2R1_FB15_Pos (15U)
2971 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
2972 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
2973 #define CAN_F2R1_FB16_Pos (16U)
2974 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
2975 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
2976 #define CAN_F2R1_FB17_Pos (17U)
2977 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
2978 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
2979 #define CAN_F2R1_FB18_Pos (18U)
2980 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
2981 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
2982 #define CAN_F2R1_FB19_Pos (19U)
2983 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
2984 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
2985 #define CAN_F2R1_FB20_Pos (20U)
2986 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
2987 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
2988 #define CAN_F2R1_FB21_Pos (21U)
2989 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
2990 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
2991 #define CAN_F2R1_FB22_Pos (22U)
2992 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
2993 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
2994 #define CAN_F2R1_FB23_Pos (23U)
2995 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
2996 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
2997 #define CAN_F2R1_FB24_Pos (24U)
2998 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
2999 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3000 #define CAN_F2R1_FB25_Pos (25U)
3001 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3002 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3003 #define CAN_F2R1_FB26_Pos (26U)
3004 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3005 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3006 #define CAN_F2R1_FB27_Pos (27U)
3007 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3008 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3009 #define CAN_F2R1_FB28_Pos (28U)
3010 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3011 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3012 #define CAN_F2R1_FB29_Pos (29U)
3013 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3014 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3015 #define CAN_F2R1_FB30_Pos (30U)
3016 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3017 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3018 #define CAN_F2R1_FB31_Pos (31U)
3019 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3020 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3021
3022 /******************* Bit definition for CAN_F3R1 register *******************/
3023 #define CAN_F3R1_FB0_Pos (0U)
3024 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3025 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3026 #define CAN_F3R1_FB1_Pos (1U)
3027 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3028 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3029 #define CAN_F3R1_FB2_Pos (2U)
3030 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3031 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3032 #define CAN_F3R1_FB3_Pos (3U)
3033 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3034 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3035 #define CAN_F3R1_FB4_Pos (4U)
3036 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3037 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3038 #define CAN_F3R1_FB5_Pos (5U)
3039 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3040 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3041 #define CAN_F3R1_FB6_Pos (6U)
3042 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3043 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3044 #define CAN_F3R1_FB7_Pos (7U)
3045 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3046 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3047 #define CAN_F3R1_FB8_Pos (8U)
3048 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3049 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3050 #define CAN_F3R1_FB9_Pos (9U)
3051 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3052 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3053 #define CAN_F3R1_FB10_Pos (10U)
3054 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3055 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3056 #define CAN_F3R1_FB11_Pos (11U)
3057 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3058 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3059 #define CAN_F3R1_FB12_Pos (12U)
3060 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3061 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3062 #define CAN_F3R1_FB13_Pos (13U)
3063 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3064 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3065 #define CAN_F3R1_FB14_Pos (14U)
3066 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3067 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3068 #define CAN_F3R1_FB15_Pos (15U)
3069 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3070 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3071 #define CAN_F3R1_FB16_Pos (16U)
3072 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3073 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3074 #define CAN_F3R1_FB17_Pos (17U)
3075 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3076 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3077 #define CAN_F3R1_FB18_Pos (18U)
3078 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3079 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3080 #define CAN_F3R1_FB19_Pos (19U)
3081 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3082 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3083 #define CAN_F3R1_FB20_Pos (20U)
3084 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3085 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3086 #define CAN_F3R1_FB21_Pos (21U)
3087 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3088 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3089 #define CAN_F3R1_FB22_Pos (22U)
3090 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3091 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3092 #define CAN_F3R1_FB23_Pos (23U)
3093 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3094 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3095 #define CAN_F3R1_FB24_Pos (24U)
3096 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3097 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3098 #define CAN_F3R1_FB25_Pos (25U)
3099 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3100 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3101 #define CAN_F3R1_FB26_Pos (26U)
3102 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3103 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3104 #define CAN_F3R1_FB27_Pos (27U)
3105 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3106 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3107 #define CAN_F3R1_FB28_Pos (28U)
3108 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3109 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3110 #define CAN_F3R1_FB29_Pos (29U)
3111 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3112 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3113 #define CAN_F3R1_FB30_Pos (30U)
3114 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3115 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3116 #define CAN_F3R1_FB31_Pos (31U)
3117 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3118 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3119
3120 /******************* Bit definition for CAN_F4R1 register *******************/
3121 #define CAN_F4R1_FB0_Pos (0U)
3122 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3123 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3124 #define CAN_F4R1_FB1_Pos (1U)
3125 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3126 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3127 #define CAN_F4R1_FB2_Pos (2U)
3128 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3129 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3130 #define CAN_F4R1_FB3_Pos (3U)
3131 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3132 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3133 #define CAN_F4R1_FB4_Pos (4U)
3134 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3135 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3136 #define CAN_F4R1_FB5_Pos (5U)
3137 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3138 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3139 #define CAN_F4R1_FB6_Pos (6U)
3140 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3141 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3142 #define CAN_F4R1_FB7_Pos (7U)
3143 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3144 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3145 #define CAN_F4R1_FB8_Pos (8U)
3146 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3147 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3148 #define CAN_F4R1_FB9_Pos (9U)
3149 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3150 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3151 #define CAN_F4R1_FB10_Pos (10U)
3152 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3153 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3154 #define CAN_F4R1_FB11_Pos (11U)
3155 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3156 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3157 #define CAN_F4R1_FB12_Pos (12U)
3158 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3159 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3160 #define CAN_F4R1_FB13_Pos (13U)
3161 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3162 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3163 #define CAN_F4R1_FB14_Pos (14U)
3164 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3165 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3166 #define CAN_F4R1_FB15_Pos (15U)
3167 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3168 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3169 #define CAN_F4R1_FB16_Pos (16U)
3170 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3171 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3172 #define CAN_F4R1_FB17_Pos (17U)
3173 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3174 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3175 #define CAN_F4R1_FB18_Pos (18U)
3176 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3177 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3178 #define CAN_F4R1_FB19_Pos (19U)
3179 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3180 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3181 #define CAN_F4R1_FB20_Pos (20U)
3182 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3183 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3184 #define CAN_F4R1_FB21_Pos (21U)
3185 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3186 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3187 #define CAN_F4R1_FB22_Pos (22U)
3188 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3189 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3190 #define CAN_F4R1_FB23_Pos (23U)
3191 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3192 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3193 #define CAN_F4R1_FB24_Pos (24U)
3194 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3195 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3196 #define CAN_F4R1_FB25_Pos (25U)
3197 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3198 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3199 #define CAN_F4R1_FB26_Pos (26U)
3200 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3201 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3202 #define CAN_F4R1_FB27_Pos (27U)
3203 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3204 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3205 #define CAN_F4R1_FB28_Pos (28U)
3206 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3207 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3208 #define CAN_F4R1_FB29_Pos (29U)
3209 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3210 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3211 #define CAN_F4R1_FB30_Pos (30U)
3212 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3213 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3214 #define CAN_F4R1_FB31_Pos (31U)
3215 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3216 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3217
3218 /******************* Bit definition for CAN_F5R1 register *******************/
3219 #define CAN_F5R1_FB0_Pos (0U)
3220 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3221 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3222 #define CAN_F5R1_FB1_Pos (1U)
3223 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3224 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3225 #define CAN_F5R1_FB2_Pos (2U)
3226 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3227 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3228 #define CAN_F5R1_FB3_Pos (3U)
3229 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3230 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3231 #define CAN_F5R1_FB4_Pos (4U)
3232 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3233 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3234 #define CAN_F5R1_FB5_Pos (5U)
3235 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3236 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3237 #define CAN_F5R1_FB6_Pos (6U)
3238 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3239 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3240 #define CAN_F5R1_FB7_Pos (7U)
3241 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3242 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3243 #define CAN_F5R1_FB8_Pos (8U)
3244 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3245 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3246 #define CAN_F5R1_FB9_Pos (9U)
3247 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3248 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3249 #define CAN_F5R1_FB10_Pos (10U)
3250 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3251 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3252 #define CAN_F5R1_FB11_Pos (11U)
3253 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3254 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3255 #define CAN_F5R1_FB12_Pos (12U)
3256 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3257 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3258 #define CAN_F5R1_FB13_Pos (13U)
3259 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3260 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3261 #define CAN_F5R1_FB14_Pos (14U)
3262 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3263 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3264 #define CAN_F5R1_FB15_Pos (15U)
3265 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3266 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3267 #define CAN_F5R1_FB16_Pos (16U)
3268 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3269 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3270 #define CAN_F5R1_FB17_Pos (17U)
3271 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3272 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3273 #define CAN_F5R1_FB18_Pos (18U)
3274 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3275 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3276 #define CAN_F5R1_FB19_Pos (19U)
3277 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3278 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3279 #define CAN_F5R1_FB20_Pos (20U)
3280 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3281 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3282 #define CAN_F5R1_FB21_Pos (21U)
3283 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3284 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3285 #define CAN_F5R1_FB22_Pos (22U)
3286 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3287 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3288 #define CAN_F5R1_FB23_Pos (23U)
3289 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3290 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3291 #define CAN_F5R1_FB24_Pos (24U)
3292 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3293 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3294 #define CAN_F5R1_FB25_Pos (25U)
3295 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3296 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3297 #define CAN_F5R1_FB26_Pos (26U)
3298 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3299 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3300 #define CAN_F5R1_FB27_Pos (27U)
3301 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3302 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3303 #define CAN_F5R1_FB28_Pos (28U)
3304 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3305 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3306 #define CAN_F5R1_FB29_Pos (29U)
3307 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3308 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3309 #define CAN_F5R1_FB30_Pos (30U)
3310 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3311 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3312 #define CAN_F5R1_FB31_Pos (31U)
3313 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3314 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3315
3316 /******************* Bit definition for CAN_F6R1 register *******************/
3317 #define CAN_F6R1_FB0_Pos (0U)
3318 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3319 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3320 #define CAN_F6R1_FB1_Pos (1U)
3321 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3322 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3323 #define CAN_F6R1_FB2_Pos (2U)
3324 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3325 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3326 #define CAN_F6R1_FB3_Pos (3U)
3327 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3328 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3329 #define CAN_F6R1_FB4_Pos (4U)
3330 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3331 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3332 #define CAN_F6R1_FB5_Pos (5U)
3333 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3334 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3335 #define CAN_F6R1_FB6_Pos (6U)
3336 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3337 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3338 #define CAN_F6R1_FB7_Pos (7U)
3339 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3340 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3341 #define CAN_F6R1_FB8_Pos (8U)
3342 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3343 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3344 #define CAN_F6R1_FB9_Pos (9U)
3345 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3346 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3347 #define CAN_F6R1_FB10_Pos (10U)
3348 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3349 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3350 #define CAN_F6R1_FB11_Pos (11U)
3351 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3352 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3353 #define CAN_F6R1_FB12_Pos (12U)
3354 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3355 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3356 #define CAN_F6R1_FB13_Pos (13U)
3357 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3358 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3359 #define CAN_F6R1_FB14_Pos (14U)
3360 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3361 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3362 #define CAN_F6R1_FB15_Pos (15U)
3363 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3364 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3365 #define CAN_F6R1_FB16_Pos (16U)
3366 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3367 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3368 #define CAN_F6R1_FB17_Pos (17U)
3369 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3370 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3371 #define CAN_F6R1_FB18_Pos (18U)
3372 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3373 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3374 #define CAN_F6R1_FB19_Pos (19U)
3375 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3376 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3377 #define CAN_F6R1_FB20_Pos (20U)
3378 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3379 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3380 #define CAN_F6R1_FB21_Pos (21U)
3381 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3382 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3383 #define CAN_F6R1_FB22_Pos (22U)
3384 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3385 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3386 #define CAN_F6R1_FB23_Pos (23U)
3387 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3388 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3389 #define CAN_F6R1_FB24_Pos (24U)
3390 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3391 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3392 #define CAN_F6R1_FB25_Pos (25U)
3393 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3394 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3395 #define CAN_F6R1_FB26_Pos (26U)
3396 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3397 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3398 #define CAN_F6R1_FB27_Pos (27U)
3399 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3400 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3401 #define CAN_F6R1_FB28_Pos (28U)
3402 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3403 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3404 #define CAN_F6R1_FB29_Pos (29U)
3405 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3406 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3407 #define CAN_F6R1_FB30_Pos (30U)
3408 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3409 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3410 #define CAN_F6R1_FB31_Pos (31U)
3411 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3412 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3413
3414 /******************* Bit definition for CAN_F7R1 register *******************/
3415 #define CAN_F7R1_FB0_Pos (0U)
3416 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3417 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3418 #define CAN_F7R1_FB1_Pos (1U)
3419 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3420 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3421 #define CAN_F7R1_FB2_Pos (2U)
3422 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3423 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3424 #define CAN_F7R1_FB3_Pos (3U)
3425 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3426 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3427 #define CAN_F7R1_FB4_Pos (4U)
3428 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3429 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3430 #define CAN_F7R1_FB5_Pos (5U)
3431 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3432 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3433 #define CAN_F7R1_FB6_Pos (6U)
3434 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3435 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3436 #define CAN_F7R1_FB7_Pos (7U)
3437 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3438 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3439 #define CAN_F7R1_FB8_Pos (8U)
3440 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3441 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3442 #define CAN_F7R1_FB9_Pos (9U)
3443 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3444 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3445 #define CAN_F7R1_FB10_Pos (10U)
3446 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3447 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3448 #define CAN_F7R1_FB11_Pos (11U)
3449 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3450 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3451 #define CAN_F7R1_FB12_Pos (12U)
3452 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3453 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3454 #define CAN_F7R1_FB13_Pos (13U)
3455 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3456 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3457 #define CAN_F7R1_FB14_Pos (14U)
3458 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3459 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3460 #define CAN_F7R1_FB15_Pos (15U)
3461 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3462 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3463 #define CAN_F7R1_FB16_Pos (16U)
3464 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3465 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3466 #define CAN_F7R1_FB17_Pos (17U)
3467 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3468 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3469 #define CAN_F7R1_FB18_Pos (18U)
3470 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3471 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3472 #define CAN_F7R1_FB19_Pos (19U)
3473 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3474 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3475 #define CAN_F7R1_FB20_Pos (20U)
3476 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3477 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3478 #define CAN_F7R1_FB21_Pos (21U)
3479 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3480 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3481 #define CAN_F7R1_FB22_Pos (22U)
3482 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3483 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3484 #define CAN_F7R1_FB23_Pos (23U)
3485 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3486 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3487 #define CAN_F7R1_FB24_Pos (24U)
3488 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3489 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3490 #define CAN_F7R1_FB25_Pos (25U)
3491 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3492 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3493 #define CAN_F7R1_FB26_Pos (26U)
3494 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3495 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3496 #define CAN_F7R1_FB27_Pos (27U)
3497 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3498 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3499 #define CAN_F7R1_FB28_Pos (28U)
3500 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3501 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3502 #define CAN_F7R1_FB29_Pos (29U)
3503 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3504 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3505 #define CAN_F7R1_FB30_Pos (30U)
3506 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3507 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3508 #define CAN_F7R1_FB31_Pos (31U)
3509 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3510 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3511
3512 /******************* Bit definition for CAN_F8R1 register *******************/
3513 #define CAN_F8R1_FB0_Pos (0U)
3514 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3515 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3516 #define CAN_F8R1_FB1_Pos (1U)
3517 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3518 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3519 #define CAN_F8R1_FB2_Pos (2U)
3520 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3521 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3522 #define CAN_F8R1_FB3_Pos (3U)
3523 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3524 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3525 #define CAN_F8R1_FB4_Pos (4U)
3526 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3527 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3528 #define CAN_F8R1_FB5_Pos (5U)
3529 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3530 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3531 #define CAN_F8R1_FB6_Pos (6U)
3532 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3533 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3534 #define CAN_F8R1_FB7_Pos (7U)
3535 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3536 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3537 #define CAN_F8R1_FB8_Pos (8U)
3538 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3539 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3540 #define CAN_F8R1_FB9_Pos (9U)
3541 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3542 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3543 #define CAN_F8R1_FB10_Pos (10U)
3544 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3545 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3546 #define CAN_F8R1_FB11_Pos (11U)
3547 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3548 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3549 #define CAN_F8R1_FB12_Pos (12U)
3550 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3551 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3552 #define CAN_F8R1_FB13_Pos (13U)
3553 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3554 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3555 #define CAN_F8R1_FB14_Pos (14U)
3556 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3557 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3558 #define CAN_F8R1_FB15_Pos (15U)
3559 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3560 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3561 #define CAN_F8R1_FB16_Pos (16U)
3562 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3563 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3564 #define CAN_F8R1_FB17_Pos (17U)
3565 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3566 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3567 #define CAN_F8R1_FB18_Pos (18U)
3568 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3569 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3570 #define CAN_F8R1_FB19_Pos (19U)
3571 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3572 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3573 #define CAN_F8R1_FB20_Pos (20U)
3574 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3575 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3576 #define CAN_F8R1_FB21_Pos (21U)
3577 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3578 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3579 #define CAN_F8R1_FB22_Pos (22U)
3580 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3581 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3582 #define CAN_F8R1_FB23_Pos (23U)
3583 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3584 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3585 #define CAN_F8R1_FB24_Pos (24U)
3586 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3587 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3588 #define CAN_F8R1_FB25_Pos (25U)
3589 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3590 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3591 #define CAN_F8R1_FB26_Pos (26U)
3592 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3593 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3594 #define CAN_F8R1_FB27_Pos (27U)
3595 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3596 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3597 #define CAN_F8R1_FB28_Pos (28U)
3598 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3599 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3600 #define CAN_F8R1_FB29_Pos (29U)
3601 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3602 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3603 #define CAN_F8R1_FB30_Pos (30U)
3604 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3605 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3606 #define CAN_F8R1_FB31_Pos (31U)
3607 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3608 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3609
3610 /******************* Bit definition for CAN_F9R1 register *******************/
3611 #define CAN_F9R1_FB0_Pos (0U)
3612 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3613 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3614 #define CAN_F9R1_FB1_Pos (1U)
3615 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3616 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3617 #define CAN_F9R1_FB2_Pos (2U)
3618 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3619 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3620 #define CAN_F9R1_FB3_Pos (3U)
3621 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3622 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3623 #define CAN_F9R1_FB4_Pos (4U)
3624 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3625 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3626 #define CAN_F9R1_FB5_Pos (5U)
3627 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3628 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3629 #define CAN_F9R1_FB6_Pos (6U)
3630 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3631 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3632 #define CAN_F9R1_FB7_Pos (7U)
3633 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3634 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3635 #define CAN_F9R1_FB8_Pos (8U)
3636 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3637 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3638 #define CAN_F9R1_FB9_Pos (9U)
3639 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3640 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3641 #define CAN_F9R1_FB10_Pos (10U)
3642 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3643 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3644 #define CAN_F9R1_FB11_Pos (11U)
3645 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3646 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3647 #define CAN_F9R1_FB12_Pos (12U)
3648 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3649 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3650 #define CAN_F9R1_FB13_Pos (13U)
3651 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3652 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3653 #define CAN_F9R1_FB14_Pos (14U)
3654 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3655 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3656 #define CAN_F9R1_FB15_Pos (15U)
3657 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3658 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3659 #define CAN_F9R1_FB16_Pos (16U)
3660 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3661 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3662 #define CAN_F9R1_FB17_Pos (17U)
3663 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3664 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3665 #define CAN_F9R1_FB18_Pos (18U)
3666 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3667 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3668 #define CAN_F9R1_FB19_Pos (19U)
3669 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3670 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3671 #define CAN_F9R1_FB20_Pos (20U)
3672 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3673 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3674 #define CAN_F9R1_FB21_Pos (21U)
3675 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3676 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3677 #define CAN_F9R1_FB22_Pos (22U)
3678 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3679 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3680 #define CAN_F9R1_FB23_Pos (23U)
3681 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3682 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3683 #define CAN_F9R1_FB24_Pos (24U)
3684 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3685 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3686 #define CAN_F9R1_FB25_Pos (25U)
3687 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3688 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3689 #define CAN_F9R1_FB26_Pos (26U)
3690 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3691 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3692 #define CAN_F9R1_FB27_Pos (27U)
3693 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3694 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3695 #define CAN_F9R1_FB28_Pos (28U)
3696 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3697 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3698 #define CAN_F9R1_FB29_Pos (29U)
3699 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3700 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3701 #define CAN_F9R1_FB30_Pos (30U)
3702 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3703 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3704 #define CAN_F9R1_FB31_Pos (31U)
3705 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3706 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3707
3708 /******************* Bit definition for CAN_F10R1 register ******************/
3709 #define CAN_F10R1_FB0_Pos (0U)
3710 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3711 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3712 #define CAN_F10R1_FB1_Pos (1U)
3713 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3714 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3715 #define CAN_F10R1_FB2_Pos (2U)
3716 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3717 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3718 #define CAN_F10R1_FB3_Pos (3U)
3719 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3720 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3721 #define CAN_F10R1_FB4_Pos (4U)
3722 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3723 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3724 #define CAN_F10R1_FB5_Pos (5U)
3725 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3726 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3727 #define CAN_F10R1_FB6_Pos (6U)
3728 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3729 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3730 #define CAN_F10R1_FB7_Pos (7U)
3731 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3732 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3733 #define CAN_F10R1_FB8_Pos (8U)
3734 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3735 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3736 #define CAN_F10R1_FB9_Pos (9U)
3737 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3738 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3739 #define CAN_F10R1_FB10_Pos (10U)
3740 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3741 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3742 #define CAN_F10R1_FB11_Pos (11U)
3743 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3744 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3745 #define CAN_F10R1_FB12_Pos (12U)
3746 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3747 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3748 #define CAN_F10R1_FB13_Pos (13U)
3749 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3750 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3751 #define CAN_F10R1_FB14_Pos (14U)
3752 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3753 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3754 #define CAN_F10R1_FB15_Pos (15U)
3755 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3756 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3757 #define CAN_F10R1_FB16_Pos (16U)
3758 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3759 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3760 #define CAN_F10R1_FB17_Pos (17U)
3761 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3762 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3763 #define CAN_F10R1_FB18_Pos (18U)
3764 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3765 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3766 #define CAN_F10R1_FB19_Pos (19U)
3767 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3768 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3769 #define CAN_F10R1_FB20_Pos (20U)
3770 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3771 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3772 #define CAN_F10R1_FB21_Pos (21U)
3773 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3774 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
3775 #define CAN_F10R1_FB22_Pos (22U)
3776 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
3777 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
3778 #define CAN_F10R1_FB23_Pos (23U)
3779 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
3780 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
3781 #define CAN_F10R1_FB24_Pos (24U)
3782 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
3783 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
3784 #define CAN_F10R1_FB25_Pos (25U)
3785 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
3786 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
3787 #define CAN_F10R1_FB26_Pos (26U)
3788 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
3789 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
3790 #define CAN_F10R1_FB27_Pos (27U)
3791 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
3792 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
3793 #define CAN_F10R1_FB28_Pos (28U)
3794 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
3795 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
3796 #define CAN_F10R1_FB29_Pos (29U)
3797 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
3798 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
3799 #define CAN_F10R1_FB30_Pos (30U)
3800 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
3801 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
3802 #define CAN_F10R1_FB31_Pos (31U)
3803 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
3804 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
3805
3806 /******************* Bit definition for CAN_F11R1 register ******************/
3807 #define CAN_F11R1_FB0_Pos (0U)
3808 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
3809 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
3810 #define CAN_F11R1_FB1_Pos (1U)
3811 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
3812 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
3813 #define CAN_F11R1_FB2_Pos (2U)
3814 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
3815 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
3816 #define CAN_F11R1_FB3_Pos (3U)
3817 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
3818 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
3819 #define CAN_F11R1_FB4_Pos (4U)
3820 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
3821 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
3822 #define CAN_F11R1_FB5_Pos (5U)
3823 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
3824 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
3825 #define CAN_F11R1_FB6_Pos (6U)
3826 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
3827 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
3828 #define CAN_F11R1_FB7_Pos (7U)
3829 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
3830 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
3831 #define CAN_F11R1_FB8_Pos (8U)
3832 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
3833 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
3834 #define CAN_F11R1_FB9_Pos (9U)
3835 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
3836 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
3837 #define CAN_F11R1_FB10_Pos (10U)
3838 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
3839 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
3840 #define CAN_F11R1_FB11_Pos (11U)
3841 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
3842 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
3843 #define CAN_F11R1_FB12_Pos (12U)
3844 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
3845 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
3846 #define CAN_F11R1_FB13_Pos (13U)
3847 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
3848 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
3849 #define CAN_F11R1_FB14_Pos (14U)
3850 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
3851 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
3852 #define CAN_F11R1_FB15_Pos (15U)
3853 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
3854 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
3855 #define CAN_F11R1_FB16_Pos (16U)
3856 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
3857 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
3858 #define CAN_F11R1_FB17_Pos (17U)
3859 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
3860 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
3861 #define CAN_F11R1_FB18_Pos (18U)
3862 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
3863 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
3864 #define CAN_F11R1_FB19_Pos (19U)
3865 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
3866 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
3867 #define CAN_F11R1_FB20_Pos (20U)
3868 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
3869 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
3870 #define CAN_F11R1_FB21_Pos (21U)
3871 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
3872 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
3873 #define CAN_F11R1_FB22_Pos (22U)
3874 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
3875 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
3876 #define CAN_F11R1_FB23_Pos (23U)
3877 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
3878 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
3879 #define CAN_F11R1_FB24_Pos (24U)
3880 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
3881 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
3882 #define CAN_F11R1_FB25_Pos (25U)
3883 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
3884 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
3885 #define CAN_F11R1_FB26_Pos (26U)
3886 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
3887 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
3888 #define CAN_F11R1_FB27_Pos (27U)
3889 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
3890 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
3891 #define CAN_F11R1_FB28_Pos (28U)
3892 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
3893 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
3894 #define CAN_F11R1_FB29_Pos (29U)
3895 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
3896 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
3897 #define CAN_F11R1_FB30_Pos (30U)
3898 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
3899 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
3900 #define CAN_F11R1_FB31_Pos (31U)
3901 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
3902 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
3903
3904 /******************* Bit definition for CAN_F12R1 register ******************/
3905 #define CAN_F12R1_FB0_Pos (0U)
3906 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
3907 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
3908 #define CAN_F12R1_FB1_Pos (1U)
3909 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
3910 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
3911 #define CAN_F12R1_FB2_Pos (2U)
3912 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
3913 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
3914 #define CAN_F12R1_FB3_Pos (3U)
3915 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
3916 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
3917 #define CAN_F12R1_FB4_Pos (4U)
3918 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
3919 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
3920 #define CAN_F12R1_FB5_Pos (5U)
3921 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
3922 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
3923 #define CAN_F12R1_FB6_Pos (6U)
3924 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
3925 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
3926 #define CAN_F12R1_FB7_Pos (7U)
3927 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
3928 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
3929 #define CAN_F12R1_FB8_Pos (8U)
3930 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
3931 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
3932 #define CAN_F12R1_FB9_Pos (9U)
3933 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
3934 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
3935 #define CAN_F12R1_FB10_Pos (10U)
3936 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
3937 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
3938 #define CAN_F12R1_FB11_Pos (11U)
3939 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
3940 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
3941 #define CAN_F12R1_FB12_Pos (12U)
3942 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
3943 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
3944 #define CAN_F12R1_FB13_Pos (13U)
3945 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
3946 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
3947 #define CAN_F12R1_FB14_Pos (14U)
3948 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
3949 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
3950 #define CAN_F12R1_FB15_Pos (15U)
3951 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
3952 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
3953 #define CAN_F12R1_FB16_Pos (16U)
3954 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
3955 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
3956 #define CAN_F12R1_FB17_Pos (17U)
3957 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
3958 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
3959 #define CAN_F12R1_FB18_Pos (18U)
3960 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
3961 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
3962 #define CAN_F12R1_FB19_Pos (19U)
3963 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
3964 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
3965 #define CAN_F12R1_FB20_Pos (20U)
3966 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
3967 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
3968 #define CAN_F12R1_FB21_Pos (21U)
3969 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
3970 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
3971 #define CAN_F12R1_FB22_Pos (22U)
3972 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
3973 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
3974 #define CAN_F12R1_FB23_Pos (23U)
3975 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
3976 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
3977 #define CAN_F12R1_FB24_Pos (24U)
3978 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
3979 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
3980 #define CAN_F12R1_FB25_Pos (25U)
3981 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
3982 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
3983 #define CAN_F12R1_FB26_Pos (26U)
3984 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
3985 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
3986 #define CAN_F12R1_FB27_Pos (27U)
3987 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
3988 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
3989 #define CAN_F12R1_FB28_Pos (28U)
3990 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
3991 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
3992 #define CAN_F12R1_FB29_Pos (29U)
3993 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
3994 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
3995 #define CAN_F12R1_FB30_Pos (30U)
3996 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
3997 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
3998 #define CAN_F12R1_FB31_Pos (31U)
3999 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4000 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4001
4002 /******************* Bit definition for CAN_F13R1 register ******************/
4003 #define CAN_F13R1_FB0_Pos (0U)
4004 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4005 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4006 #define CAN_F13R1_FB1_Pos (1U)
4007 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4008 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4009 #define CAN_F13R1_FB2_Pos (2U)
4010 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4011 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4012 #define CAN_F13R1_FB3_Pos (3U)
4013 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4014 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4015 #define CAN_F13R1_FB4_Pos (4U)
4016 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4017 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4018 #define CAN_F13R1_FB5_Pos (5U)
4019 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4020 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4021 #define CAN_F13R1_FB6_Pos (6U)
4022 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4023 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4024 #define CAN_F13R1_FB7_Pos (7U)
4025 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4026 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4027 #define CAN_F13R1_FB8_Pos (8U)
4028 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4029 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4030 #define CAN_F13R1_FB9_Pos (9U)
4031 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4032 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4033 #define CAN_F13R1_FB10_Pos (10U)
4034 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4035 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4036 #define CAN_F13R1_FB11_Pos (11U)
4037 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4038 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4039 #define CAN_F13R1_FB12_Pos (12U)
4040 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4041 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4042 #define CAN_F13R1_FB13_Pos (13U)
4043 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4044 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4045 #define CAN_F13R1_FB14_Pos (14U)
4046 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4047 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4048 #define CAN_F13R1_FB15_Pos (15U)
4049 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4050 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4051 #define CAN_F13R1_FB16_Pos (16U)
4052 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4053 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4054 #define CAN_F13R1_FB17_Pos (17U)
4055 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4056 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4057 #define CAN_F13R1_FB18_Pos (18U)
4058 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4059 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4060 #define CAN_F13R1_FB19_Pos (19U)
4061 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4062 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4063 #define CAN_F13R1_FB20_Pos (20U)
4064 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4065 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4066 #define CAN_F13R1_FB21_Pos (21U)
4067 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4068 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4069 #define CAN_F13R1_FB22_Pos (22U)
4070 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4071 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4072 #define CAN_F13R1_FB23_Pos (23U)
4073 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4074 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4075 #define CAN_F13R1_FB24_Pos (24U)
4076 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4077 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4078 #define CAN_F13R1_FB25_Pos (25U)
4079 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4080 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4081 #define CAN_F13R1_FB26_Pos (26U)
4082 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4083 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4084 #define CAN_F13R1_FB27_Pos (27U)
4085 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4086 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4087 #define CAN_F13R1_FB28_Pos (28U)
4088 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4089 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4090 #define CAN_F13R1_FB29_Pos (29U)
4091 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4092 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4093 #define CAN_F13R1_FB30_Pos (30U)
4094 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4095 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4096 #define CAN_F13R1_FB31_Pos (31U)
4097 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4098 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4099
4100 /******************* Bit definition for CAN_F0R2 register *******************/
4101 #define CAN_F0R2_FB0_Pos (0U)
4102 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4103 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4104 #define CAN_F0R2_FB1_Pos (1U)
4105 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4106 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4107 #define CAN_F0R2_FB2_Pos (2U)
4108 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4109 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4110 #define CAN_F0R2_FB3_Pos (3U)
4111 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4112 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4113 #define CAN_F0R2_FB4_Pos (4U)
4114 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4115 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4116 #define CAN_F0R2_FB5_Pos (5U)
4117 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4118 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4119 #define CAN_F0R2_FB6_Pos (6U)
4120 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4121 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4122 #define CAN_F0R2_FB7_Pos (7U)
4123 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4124 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4125 #define CAN_F0R2_FB8_Pos (8U)
4126 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4127 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4128 #define CAN_F0R2_FB9_Pos (9U)
4129 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4130 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4131 #define CAN_F0R2_FB10_Pos (10U)
4132 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4133 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4134 #define CAN_F0R2_FB11_Pos (11U)
4135 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4136 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4137 #define CAN_F0R2_FB12_Pos (12U)
4138 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4139 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4140 #define CAN_F0R2_FB13_Pos (13U)
4141 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4142 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4143 #define CAN_F0R2_FB14_Pos (14U)
4144 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4145 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4146 #define CAN_F0R2_FB15_Pos (15U)
4147 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4148 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4149 #define CAN_F0R2_FB16_Pos (16U)
4150 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4151 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4152 #define CAN_F0R2_FB17_Pos (17U)
4153 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4154 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4155 #define CAN_F0R2_FB18_Pos (18U)
4156 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4157 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4158 #define CAN_F0R2_FB19_Pos (19U)
4159 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4160 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4161 #define CAN_F0R2_FB20_Pos (20U)
4162 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4163 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4164 #define CAN_F0R2_FB21_Pos (21U)
4165 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4166 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4167 #define CAN_F0R2_FB22_Pos (22U)
4168 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4169 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4170 #define CAN_F0R2_FB23_Pos (23U)
4171 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4172 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4173 #define CAN_F0R2_FB24_Pos (24U)
4174 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4175 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4176 #define CAN_F0R2_FB25_Pos (25U)
4177 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4178 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4179 #define CAN_F0R2_FB26_Pos (26U)
4180 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4181 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4182 #define CAN_F0R2_FB27_Pos (27U)
4183 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4184 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4185 #define CAN_F0R2_FB28_Pos (28U)
4186 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4187 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4188 #define CAN_F0R2_FB29_Pos (29U)
4189 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4190 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4191 #define CAN_F0R2_FB30_Pos (30U)
4192 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4193 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4194 #define CAN_F0R2_FB31_Pos (31U)
4195 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4196 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4197
4198 /******************* Bit definition for CAN_F1R2 register *******************/
4199 #define CAN_F1R2_FB0_Pos (0U)
4200 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4201 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4202 #define CAN_F1R2_FB1_Pos (1U)
4203 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4204 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4205 #define CAN_F1R2_FB2_Pos (2U)
4206 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4207 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4208 #define CAN_F1R2_FB3_Pos (3U)
4209 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4210 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4211 #define CAN_F1R2_FB4_Pos (4U)
4212 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4213 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4214 #define CAN_F1R2_FB5_Pos (5U)
4215 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4216 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4217 #define CAN_F1R2_FB6_Pos (6U)
4218 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4219 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4220 #define CAN_F1R2_FB7_Pos (7U)
4221 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4222 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4223 #define CAN_F1R2_FB8_Pos (8U)
4224 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4225 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4226 #define CAN_F1R2_FB9_Pos (9U)
4227 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4228 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4229 #define CAN_F1R2_FB10_Pos (10U)
4230 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4231 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4232 #define CAN_F1R2_FB11_Pos (11U)
4233 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4234 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4235 #define CAN_F1R2_FB12_Pos (12U)
4236 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4237 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4238 #define CAN_F1R2_FB13_Pos (13U)
4239 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4240 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4241 #define CAN_F1R2_FB14_Pos (14U)
4242 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4243 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4244 #define CAN_F1R2_FB15_Pos (15U)
4245 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4246 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4247 #define CAN_F1R2_FB16_Pos (16U)
4248 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4249 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4250 #define CAN_F1R2_FB17_Pos (17U)
4251 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4252 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4253 #define CAN_F1R2_FB18_Pos (18U)
4254 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4255 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4256 #define CAN_F1R2_FB19_Pos (19U)
4257 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4258 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4259 #define CAN_F1R2_FB20_Pos (20U)
4260 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4261 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4262 #define CAN_F1R2_FB21_Pos (21U)
4263 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4264 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4265 #define CAN_F1R2_FB22_Pos (22U)
4266 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4267 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4268 #define CAN_F1R2_FB23_Pos (23U)
4269 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4270 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4271 #define CAN_F1R2_FB24_Pos (24U)
4272 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4273 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4274 #define CAN_F1R2_FB25_Pos (25U)
4275 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4276 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4277 #define CAN_F1R2_FB26_Pos (26U)
4278 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4279 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4280 #define CAN_F1R2_FB27_Pos (27U)
4281 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4282 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4283 #define CAN_F1R2_FB28_Pos (28U)
4284 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4285 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4286 #define CAN_F1R2_FB29_Pos (29U)
4287 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4288 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4289 #define CAN_F1R2_FB30_Pos (30U)
4290 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4291 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4292 #define CAN_F1R2_FB31_Pos (31U)
4293 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4294 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4295
4296 /******************* Bit definition for CAN_F2R2 register *******************/
4297 #define CAN_F2R2_FB0_Pos (0U)
4298 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4299 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4300 #define CAN_F2R2_FB1_Pos (1U)
4301 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4302 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4303 #define CAN_F2R2_FB2_Pos (2U)
4304 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4305 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4306 #define CAN_F2R2_FB3_Pos (3U)
4307 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4308 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4309 #define CAN_F2R2_FB4_Pos (4U)
4310 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4311 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4312 #define CAN_F2R2_FB5_Pos (5U)
4313 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4314 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4315 #define CAN_F2R2_FB6_Pos (6U)
4316 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4317 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4318 #define CAN_F2R2_FB7_Pos (7U)
4319 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4320 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4321 #define CAN_F2R2_FB8_Pos (8U)
4322 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4323 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4324 #define CAN_F2R2_FB9_Pos (9U)
4325 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4326 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4327 #define CAN_F2R2_FB10_Pos (10U)
4328 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4329 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4330 #define CAN_F2R2_FB11_Pos (11U)
4331 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4332 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4333 #define CAN_F2R2_FB12_Pos (12U)
4334 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4335 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4336 #define CAN_F2R2_FB13_Pos (13U)
4337 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4338 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4339 #define CAN_F2R2_FB14_Pos (14U)
4340 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4341 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4342 #define CAN_F2R2_FB15_Pos (15U)
4343 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4344 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4345 #define CAN_F2R2_FB16_Pos (16U)
4346 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4347 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4348 #define CAN_F2R2_FB17_Pos (17U)
4349 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4350 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4351 #define CAN_F2R2_FB18_Pos (18U)
4352 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4353 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4354 #define CAN_F2R2_FB19_Pos (19U)
4355 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4356 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4357 #define CAN_F2R2_FB20_Pos (20U)
4358 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4359 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4360 #define CAN_F2R2_FB21_Pos (21U)
4361 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4362 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4363 #define CAN_F2R2_FB22_Pos (22U)
4364 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4365 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4366 #define CAN_F2R2_FB23_Pos (23U)
4367 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4368 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4369 #define CAN_F2R2_FB24_Pos (24U)
4370 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4371 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4372 #define CAN_F2R2_FB25_Pos (25U)
4373 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4374 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4375 #define CAN_F2R2_FB26_Pos (26U)
4376 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4377 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4378 #define CAN_F2R2_FB27_Pos (27U)
4379 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4380 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4381 #define CAN_F2R2_FB28_Pos (28U)
4382 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4383 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4384 #define CAN_F2R2_FB29_Pos (29U)
4385 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4386 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4387 #define CAN_F2R2_FB30_Pos (30U)
4388 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4389 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4390 #define CAN_F2R2_FB31_Pos (31U)
4391 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4392 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4393
4394 /******************* Bit definition for CAN_F3R2 register *******************/
4395 #define CAN_F3R2_FB0_Pos (0U)
4396 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4397 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4398 #define CAN_F3R2_FB1_Pos (1U)
4399 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4400 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4401 #define CAN_F3R2_FB2_Pos (2U)
4402 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4403 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4404 #define CAN_F3R2_FB3_Pos (3U)
4405 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4406 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4407 #define CAN_F3R2_FB4_Pos (4U)
4408 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4409 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4410 #define CAN_F3R2_FB5_Pos (5U)
4411 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4412 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4413 #define CAN_F3R2_FB6_Pos (6U)
4414 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4415 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4416 #define CAN_F3R2_FB7_Pos (7U)
4417 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4418 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4419 #define CAN_F3R2_FB8_Pos (8U)
4420 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4421 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4422 #define CAN_F3R2_FB9_Pos (9U)
4423 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4424 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4425 #define CAN_F3R2_FB10_Pos (10U)
4426 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4427 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4428 #define CAN_F3R2_FB11_Pos (11U)
4429 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4430 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4431 #define CAN_F3R2_FB12_Pos (12U)
4432 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4433 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4434 #define CAN_F3R2_FB13_Pos (13U)
4435 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4436 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4437 #define CAN_F3R2_FB14_Pos (14U)
4438 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4439 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4440 #define CAN_F3R2_FB15_Pos (15U)
4441 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4442 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4443 #define CAN_F3R2_FB16_Pos (16U)
4444 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4445 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4446 #define CAN_F3R2_FB17_Pos (17U)
4447 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4448 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4449 #define CAN_F3R2_FB18_Pos (18U)
4450 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4451 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4452 #define CAN_F3R2_FB19_Pos (19U)
4453 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4454 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4455 #define CAN_F3R2_FB20_Pos (20U)
4456 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4457 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4458 #define CAN_F3R2_FB21_Pos (21U)
4459 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4460 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4461 #define CAN_F3R2_FB22_Pos (22U)
4462 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4463 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4464 #define CAN_F3R2_FB23_Pos (23U)
4465 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4466 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4467 #define CAN_F3R2_FB24_Pos (24U)
4468 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4469 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4470 #define CAN_F3R2_FB25_Pos (25U)
4471 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4472 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4473 #define CAN_F3R2_FB26_Pos (26U)
4474 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4475 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4476 #define CAN_F3R2_FB27_Pos (27U)
4477 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4478 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4479 #define CAN_F3R2_FB28_Pos (28U)
4480 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4481 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4482 #define CAN_F3R2_FB29_Pos (29U)
4483 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4484 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4485 #define CAN_F3R2_FB30_Pos (30U)
4486 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4487 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4488 #define CAN_F3R2_FB31_Pos (31U)
4489 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4490 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4491
4492 /******************* Bit definition for CAN_F4R2 register *******************/
4493 #define CAN_F4R2_FB0_Pos (0U)
4494 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4495 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4496 #define CAN_F4R2_FB1_Pos (1U)
4497 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4498 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4499 #define CAN_F4R2_FB2_Pos (2U)
4500 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4501 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4502 #define CAN_F4R2_FB3_Pos (3U)
4503 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4504 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4505 #define CAN_F4R2_FB4_Pos (4U)
4506 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4507 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4508 #define CAN_F4R2_FB5_Pos (5U)
4509 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4510 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4511 #define CAN_F4R2_FB6_Pos (6U)
4512 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4513 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4514 #define CAN_F4R2_FB7_Pos (7U)
4515 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4516 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4517 #define CAN_F4R2_FB8_Pos (8U)
4518 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4519 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4520 #define CAN_F4R2_FB9_Pos (9U)
4521 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4522 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4523 #define CAN_F4R2_FB10_Pos (10U)
4524 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4525 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4526 #define CAN_F4R2_FB11_Pos (11U)
4527 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4528 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4529 #define CAN_F4R2_FB12_Pos (12U)
4530 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4531 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4532 #define CAN_F4R2_FB13_Pos (13U)
4533 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4534 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4535 #define CAN_F4R2_FB14_Pos (14U)
4536 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4537 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4538 #define CAN_F4R2_FB15_Pos (15U)
4539 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4540 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4541 #define CAN_F4R2_FB16_Pos (16U)
4542 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4543 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4544 #define CAN_F4R2_FB17_Pos (17U)
4545 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4546 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4547 #define CAN_F4R2_FB18_Pos (18U)
4548 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4549 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4550 #define CAN_F4R2_FB19_Pos (19U)
4551 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4552 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4553 #define CAN_F4R2_FB20_Pos (20U)
4554 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4555 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4556 #define CAN_F4R2_FB21_Pos (21U)
4557 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4558 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4559 #define CAN_F4R2_FB22_Pos (22U)
4560 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4561 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4562 #define CAN_F4R2_FB23_Pos (23U)
4563 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4564 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4565 #define CAN_F4R2_FB24_Pos (24U)
4566 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4567 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4568 #define CAN_F4R2_FB25_Pos (25U)
4569 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4570 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4571 #define CAN_F4R2_FB26_Pos (26U)
4572 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4573 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4574 #define CAN_F4R2_FB27_Pos (27U)
4575 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4576 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4577 #define CAN_F4R2_FB28_Pos (28U)
4578 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4579 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4580 #define CAN_F4R2_FB29_Pos (29U)
4581 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4582 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4583 #define CAN_F4R2_FB30_Pos (30U)
4584 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4585 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4586 #define CAN_F4R2_FB31_Pos (31U)
4587 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4588 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4589
4590 /******************* Bit definition for CAN_F5R2 register *******************/
4591 #define CAN_F5R2_FB0_Pos (0U)
4592 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4593 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4594 #define CAN_F5R2_FB1_Pos (1U)
4595 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4596 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4597 #define CAN_F5R2_FB2_Pos (2U)
4598 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4599 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4600 #define CAN_F5R2_FB3_Pos (3U)
4601 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4602 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4603 #define CAN_F5R2_FB4_Pos (4U)
4604 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4605 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4606 #define CAN_F5R2_FB5_Pos (5U)
4607 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4608 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4609 #define CAN_F5R2_FB6_Pos (6U)
4610 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4611 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4612 #define CAN_F5R2_FB7_Pos (7U)
4613 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4614 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4615 #define CAN_F5R2_FB8_Pos (8U)
4616 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4617 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4618 #define CAN_F5R2_FB9_Pos (9U)
4619 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4620 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4621 #define CAN_F5R2_FB10_Pos (10U)
4622 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4623 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4624 #define CAN_F5R2_FB11_Pos (11U)
4625 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4626 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4627 #define CAN_F5R2_FB12_Pos (12U)
4628 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4629 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4630 #define CAN_F5R2_FB13_Pos (13U)
4631 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4632 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4633 #define CAN_F5R2_FB14_Pos (14U)
4634 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4635 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4636 #define CAN_F5R2_FB15_Pos (15U)
4637 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4638 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4639 #define CAN_F5R2_FB16_Pos (16U)
4640 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4641 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4642 #define CAN_F5R2_FB17_Pos (17U)
4643 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4644 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4645 #define CAN_F5R2_FB18_Pos (18U)
4646 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4647 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4648 #define CAN_F5R2_FB19_Pos (19U)
4649 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4650 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4651 #define CAN_F5R2_FB20_Pos (20U)
4652 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4653 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4654 #define CAN_F5R2_FB21_Pos (21U)
4655 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4656 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4657 #define CAN_F5R2_FB22_Pos (22U)
4658 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4659 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4660 #define CAN_F5R2_FB23_Pos (23U)
4661 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4662 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4663 #define CAN_F5R2_FB24_Pos (24U)
4664 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4665 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4666 #define CAN_F5R2_FB25_Pos (25U)
4667 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4668 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4669 #define CAN_F5R2_FB26_Pos (26U)
4670 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4671 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4672 #define CAN_F5R2_FB27_Pos (27U)
4673 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4674 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4675 #define CAN_F5R2_FB28_Pos (28U)
4676 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4677 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4678 #define CAN_F5R2_FB29_Pos (29U)
4679 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4680 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4681 #define CAN_F5R2_FB30_Pos (30U)
4682 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4683 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4684 #define CAN_F5R2_FB31_Pos (31U)
4685 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4686 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4687
4688 /******************* Bit definition for CAN_F6R2 register *******************/
4689 #define CAN_F6R2_FB0_Pos (0U)
4690 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4691 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4692 #define CAN_F6R2_FB1_Pos (1U)
4693 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4694 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4695 #define CAN_F6R2_FB2_Pos (2U)
4696 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4697 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4698 #define CAN_F6R2_FB3_Pos (3U)
4699 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4700 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4701 #define CAN_F6R2_FB4_Pos (4U)
4702 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4703 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4704 #define CAN_F6R2_FB5_Pos (5U)
4705 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4706 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4707 #define CAN_F6R2_FB6_Pos (6U)
4708 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4709 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4710 #define CAN_F6R2_FB7_Pos (7U)
4711 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4712 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4713 #define CAN_F6R2_FB8_Pos (8U)
4714 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4715 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4716 #define CAN_F6R2_FB9_Pos (9U)
4717 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4718 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4719 #define CAN_F6R2_FB10_Pos (10U)
4720 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4721 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4722 #define CAN_F6R2_FB11_Pos (11U)
4723 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4724 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4725 #define CAN_F6R2_FB12_Pos (12U)
4726 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4727 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4728 #define CAN_F6R2_FB13_Pos (13U)
4729 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4730 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4731 #define CAN_F6R2_FB14_Pos (14U)
4732 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4733 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4734 #define CAN_F6R2_FB15_Pos (15U)
4735 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4736 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4737 #define CAN_F6R2_FB16_Pos (16U)
4738 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4739 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4740 #define CAN_F6R2_FB17_Pos (17U)
4741 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4742 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4743 #define CAN_F6R2_FB18_Pos (18U)
4744 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4745 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4746 #define CAN_F6R2_FB19_Pos (19U)
4747 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4748 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4749 #define CAN_F6R2_FB20_Pos (20U)
4750 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4751 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4752 #define CAN_F6R2_FB21_Pos (21U)
4753 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4754 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4755 #define CAN_F6R2_FB22_Pos (22U)
4756 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4757 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4758 #define CAN_F6R2_FB23_Pos (23U)
4759 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4760 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4761 #define CAN_F6R2_FB24_Pos (24U)
4762 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4763 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4764 #define CAN_F6R2_FB25_Pos (25U)
4765 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4766 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4767 #define CAN_F6R2_FB26_Pos (26U)
4768 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4769 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4770 #define CAN_F6R2_FB27_Pos (27U)
4771 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4772 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4773 #define CAN_F6R2_FB28_Pos (28U)
4774 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
4775 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
4776 #define CAN_F6R2_FB29_Pos (29U)
4777 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
4778 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
4779 #define CAN_F6R2_FB30_Pos (30U)
4780 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
4781 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
4782 #define CAN_F6R2_FB31_Pos (31U)
4783 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
4784 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
4785
4786 /******************* Bit definition for CAN_F7R2 register *******************/
4787 #define CAN_F7R2_FB0_Pos (0U)
4788 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
4789 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
4790 #define CAN_F7R2_FB1_Pos (1U)
4791 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
4792 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
4793 #define CAN_F7R2_FB2_Pos (2U)
4794 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
4795 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
4796 #define CAN_F7R2_FB3_Pos (3U)
4797 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
4798 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
4799 #define CAN_F7R2_FB4_Pos (4U)
4800 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
4801 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
4802 #define CAN_F7R2_FB5_Pos (5U)
4803 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
4804 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
4805 #define CAN_F7R2_FB6_Pos (6U)
4806 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
4807 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
4808 #define CAN_F7R2_FB7_Pos (7U)
4809 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
4810 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
4811 #define CAN_F7R2_FB8_Pos (8U)
4812 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
4813 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
4814 #define CAN_F7R2_FB9_Pos (9U)
4815 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
4816 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
4817 #define CAN_F7R2_FB10_Pos (10U)
4818 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
4819 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
4820 #define CAN_F7R2_FB11_Pos (11U)
4821 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
4822 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
4823 #define CAN_F7R2_FB12_Pos (12U)
4824 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
4825 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
4826 #define CAN_F7R2_FB13_Pos (13U)
4827 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
4828 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
4829 #define CAN_F7R2_FB14_Pos (14U)
4830 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
4831 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
4832 #define CAN_F7R2_FB15_Pos (15U)
4833 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
4834 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
4835 #define CAN_F7R2_FB16_Pos (16U)
4836 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
4837 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
4838 #define CAN_F7R2_FB17_Pos (17U)
4839 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
4840 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
4841 #define CAN_F7R2_FB18_Pos (18U)
4842 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
4843 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
4844 #define CAN_F7R2_FB19_Pos (19U)
4845 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
4846 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
4847 #define CAN_F7R2_FB20_Pos (20U)
4848 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
4849 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
4850 #define CAN_F7R2_FB21_Pos (21U)
4851 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
4852 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
4853 #define CAN_F7R2_FB22_Pos (22U)
4854 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
4855 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
4856 #define CAN_F7R2_FB23_Pos (23U)
4857 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
4858 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
4859 #define CAN_F7R2_FB24_Pos (24U)
4860 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
4861 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
4862 #define CAN_F7R2_FB25_Pos (25U)
4863 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
4864 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
4865 #define CAN_F7R2_FB26_Pos (26U)
4866 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
4867 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
4868 #define CAN_F7R2_FB27_Pos (27U)
4869 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
4870 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
4871 #define CAN_F7R2_FB28_Pos (28U)
4872 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
4873 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
4874 #define CAN_F7R2_FB29_Pos (29U)
4875 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
4876 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
4877 #define CAN_F7R2_FB30_Pos (30U)
4878 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
4879 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
4880 #define CAN_F7R2_FB31_Pos (31U)
4881 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
4882 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
4883
4884 /******************* Bit definition for CAN_F8R2 register *******************/
4885 #define CAN_F8R2_FB0_Pos (0U)
4886 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
4887 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
4888 #define CAN_F8R2_FB1_Pos (1U)
4889 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
4890 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
4891 #define CAN_F8R2_FB2_Pos (2U)
4892 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
4893 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
4894 #define CAN_F8R2_FB3_Pos (3U)
4895 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
4896 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
4897 #define CAN_F8R2_FB4_Pos (4U)
4898 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
4899 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
4900 #define CAN_F8R2_FB5_Pos (5U)
4901 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
4902 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
4903 #define CAN_F8R2_FB6_Pos (6U)
4904 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
4905 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
4906 #define CAN_F8R2_FB7_Pos (7U)
4907 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
4908 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
4909 #define CAN_F8R2_FB8_Pos (8U)
4910 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
4911 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
4912 #define CAN_F8R2_FB9_Pos (9U)
4913 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
4914 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
4915 #define CAN_F8R2_FB10_Pos (10U)
4916 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
4917 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
4918 #define CAN_F8R2_FB11_Pos (11U)
4919 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
4920 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
4921 #define CAN_F8R2_FB12_Pos (12U)
4922 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
4923 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
4924 #define CAN_F8R2_FB13_Pos (13U)
4925 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
4926 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
4927 #define CAN_F8R2_FB14_Pos (14U)
4928 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
4929 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
4930 #define CAN_F8R2_FB15_Pos (15U)
4931 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
4932 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
4933 #define CAN_F8R2_FB16_Pos (16U)
4934 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
4935 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
4936 #define CAN_F8R2_FB17_Pos (17U)
4937 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
4938 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
4939 #define CAN_F8R2_FB18_Pos (18U)
4940 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
4941 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
4942 #define CAN_F8R2_FB19_Pos (19U)
4943 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
4944 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
4945 #define CAN_F8R2_FB20_Pos (20U)
4946 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
4947 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
4948 #define CAN_F8R2_FB21_Pos (21U)
4949 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
4950 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
4951 #define CAN_F8R2_FB22_Pos (22U)
4952 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
4953 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
4954 #define CAN_F8R2_FB23_Pos (23U)
4955 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
4956 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
4957 #define CAN_F8R2_FB24_Pos (24U)
4958 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
4959 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
4960 #define CAN_F8R2_FB25_Pos (25U)
4961 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
4962 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
4963 #define CAN_F8R2_FB26_Pos (26U)
4964 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
4965 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
4966 #define CAN_F8R2_FB27_Pos (27U)
4967 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
4968 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
4969 #define CAN_F8R2_FB28_Pos (28U)
4970 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
4971 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
4972 #define CAN_F8R2_FB29_Pos (29U)
4973 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
4974 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
4975 #define CAN_F8R2_FB30_Pos (30U)
4976 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
4977 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
4978 #define CAN_F8R2_FB31_Pos (31U)
4979 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
4980 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
4981
4982 /******************* Bit definition for CAN_F9R2 register *******************/
4983 #define CAN_F9R2_FB0_Pos (0U)
4984 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
4985 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
4986 #define CAN_F9R2_FB1_Pos (1U)
4987 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
4988 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
4989 #define CAN_F9R2_FB2_Pos (2U)
4990 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
4991 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
4992 #define CAN_F9R2_FB3_Pos (3U)
4993 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
4994 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
4995 #define CAN_F9R2_FB4_Pos (4U)
4996 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
4997 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
4998 #define CAN_F9R2_FB5_Pos (5U)
4999 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5000 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5001 #define CAN_F9R2_FB6_Pos (6U)
5002 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5003 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5004 #define CAN_F9R2_FB7_Pos (7U)
5005 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5006 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5007 #define CAN_F9R2_FB8_Pos (8U)
5008 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5009 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5010 #define CAN_F9R2_FB9_Pos (9U)
5011 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5012 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5013 #define CAN_F9R2_FB10_Pos (10U)
5014 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5015 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5016 #define CAN_F9R2_FB11_Pos (11U)
5017 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5018 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5019 #define CAN_F9R2_FB12_Pos (12U)
5020 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5021 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5022 #define CAN_F9R2_FB13_Pos (13U)
5023 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5024 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5025 #define CAN_F9R2_FB14_Pos (14U)
5026 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5027 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5028 #define CAN_F9R2_FB15_Pos (15U)
5029 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5030 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5031 #define CAN_F9R2_FB16_Pos (16U)
5032 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5033 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5034 #define CAN_F9R2_FB17_Pos (17U)
5035 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5036 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5037 #define CAN_F9R2_FB18_Pos (18U)
5038 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5039 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5040 #define CAN_F9R2_FB19_Pos (19U)
5041 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5042 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5043 #define CAN_F9R2_FB20_Pos (20U)
5044 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5045 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5046 #define CAN_F9R2_FB21_Pos (21U)
5047 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5048 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5049 #define CAN_F9R2_FB22_Pos (22U)
5050 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5051 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5052 #define CAN_F9R2_FB23_Pos (23U)
5053 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5054 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5055 #define CAN_F9R2_FB24_Pos (24U)
5056 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5057 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5058 #define CAN_F9R2_FB25_Pos (25U)
5059 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5060 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5061 #define CAN_F9R2_FB26_Pos (26U)
5062 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5063 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5064 #define CAN_F9R2_FB27_Pos (27U)
5065 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5066 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5067 #define CAN_F9R2_FB28_Pos (28U)
5068 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5069 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5070 #define CAN_F9R2_FB29_Pos (29U)
5071 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5072 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5073 #define CAN_F9R2_FB30_Pos (30U)
5074 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5075 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5076 #define CAN_F9R2_FB31_Pos (31U)
5077 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5078 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5079
5080 /******************* Bit definition for CAN_F10R2 register ******************/
5081 #define CAN_F10R2_FB0_Pos (0U)
5082 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5083 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5084 #define CAN_F10R2_FB1_Pos (1U)
5085 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5086 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5087 #define CAN_F10R2_FB2_Pos (2U)
5088 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5089 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5090 #define CAN_F10R2_FB3_Pos (3U)
5091 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5092 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5093 #define CAN_F10R2_FB4_Pos (4U)
5094 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5095 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5096 #define CAN_F10R2_FB5_Pos (5U)
5097 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5098 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5099 #define CAN_F10R2_FB6_Pos (6U)
5100 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5101 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5102 #define CAN_F10R2_FB7_Pos (7U)
5103 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5104 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5105 #define CAN_F10R2_FB8_Pos (8U)
5106 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5107 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5108 #define CAN_F10R2_FB9_Pos (9U)
5109 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5110 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5111 #define CAN_F10R2_FB10_Pos (10U)
5112 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5113 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5114 #define CAN_F10R2_FB11_Pos (11U)
5115 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5116 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5117 #define CAN_F10R2_FB12_Pos (12U)
5118 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5119 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5120 #define CAN_F10R2_FB13_Pos (13U)
5121 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5122 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5123 #define CAN_F10R2_FB14_Pos (14U)
5124 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5125 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5126 #define CAN_F10R2_FB15_Pos (15U)
5127 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5128 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5129 #define CAN_F10R2_FB16_Pos (16U)
5130 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5131 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5132 #define CAN_F10R2_FB17_Pos (17U)
5133 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5134 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5135 #define CAN_F10R2_FB18_Pos (18U)
5136 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5137 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5138 #define CAN_F10R2_FB19_Pos (19U)
5139 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5140 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5141 #define CAN_F10R2_FB20_Pos (20U)
5142 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5143 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5144 #define CAN_F10R2_FB21_Pos (21U)
5145 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5146 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5147 #define CAN_F10R2_FB22_Pos (22U)
5148 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5149 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5150 #define CAN_F10R2_FB23_Pos (23U)
5151 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5152 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5153 #define CAN_F10R2_FB24_Pos (24U)
5154 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5155 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5156 #define CAN_F10R2_FB25_Pos (25U)
5157 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5158 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5159 #define CAN_F10R2_FB26_Pos (26U)
5160 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5161 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5162 #define CAN_F10R2_FB27_Pos (27U)
5163 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5164 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5165 #define CAN_F10R2_FB28_Pos (28U)
5166 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5167 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5168 #define CAN_F10R2_FB29_Pos (29U)
5169 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5170 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5171 #define CAN_F10R2_FB30_Pos (30U)
5172 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5173 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5174 #define CAN_F10R2_FB31_Pos (31U)
5175 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5176 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5177
5178 /******************* Bit definition for CAN_F11R2 register ******************/
5179 #define CAN_F11R2_FB0_Pos (0U)
5180 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5181 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5182 #define CAN_F11R2_FB1_Pos (1U)
5183 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5184 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5185 #define CAN_F11R2_FB2_Pos (2U)
5186 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5187 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5188 #define CAN_F11R2_FB3_Pos (3U)
5189 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5190 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5191 #define CAN_F11R2_FB4_Pos (4U)
5192 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5193 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5194 #define CAN_F11R2_FB5_Pos (5U)
5195 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5196 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5197 #define CAN_F11R2_FB6_Pos (6U)
5198 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5199 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5200 #define CAN_F11R2_FB7_Pos (7U)
5201 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5202 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5203 #define CAN_F11R2_FB8_Pos (8U)
5204 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5205 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5206 #define CAN_F11R2_FB9_Pos (9U)
5207 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5208 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5209 #define CAN_F11R2_FB10_Pos (10U)
5210 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5211 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5212 #define CAN_F11R2_FB11_Pos (11U)
5213 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5214 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5215 #define CAN_F11R2_FB12_Pos (12U)
5216 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5217 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5218 #define CAN_F11R2_FB13_Pos (13U)
5219 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5220 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5221 #define CAN_F11R2_FB14_Pos (14U)
5222 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5223 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5224 #define CAN_F11R2_FB15_Pos (15U)
5225 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5226 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5227 #define CAN_F11R2_FB16_Pos (16U)
5228 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5229 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5230 #define CAN_F11R2_FB17_Pos (17U)
5231 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5232 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5233 #define CAN_F11R2_FB18_Pos (18U)
5234 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5235 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5236 #define CAN_F11R2_FB19_Pos (19U)
5237 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5238 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5239 #define CAN_F11R2_FB20_Pos (20U)
5240 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5241 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5242 #define CAN_F11R2_FB21_Pos (21U)
5243 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5244 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5245 #define CAN_F11R2_FB22_Pos (22U)
5246 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5247 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5248 #define CAN_F11R2_FB23_Pos (23U)
5249 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5250 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5251 #define CAN_F11R2_FB24_Pos (24U)
5252 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5253 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5254 #define CAN_F11R2_FB25_Pos (25U)
5255 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5256 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5257 #define CAN_F11R2_FB26_Pos (26U)
5258 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5259 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5260 #define CAN_F11R2_FB27_Pos (27U)
5261 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5262 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5263 #define CAN_F11R2_FB28_Pos (28U)
5264 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5265 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5266 #define CAN_F11R2_FB29_Pos (29U)
5267 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5268 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5269 #define CAN_F11R2_FB30_Pos (30U)
5270 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5271 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5272 #define CAN_F11R2_FB31_Pos (31U)
5273 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5274 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5275
5276 /******************* Bit definition for CAN_F12R2 register ******************/
5277 #define CAN_F12R2_FB0_Pos (0U)
5278 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5279 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5280 #define CAN_F12R2_FB1_Pos (1U)
5281 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5282 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5283 #define CAN_F12R2_FB2_Pos (2U)
5284 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5285 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5286 #define CAN_F12R2_FB3_Pos (3U)
5287 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5288 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5289 #define CAN_F12R2_FB4_Pos (4U)
5290 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5291 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5292 #define CAN_F12R2_FB5_Pos (5U)
5293 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5294 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5295 #define CAN_F12R2_FB6_Pos (6U)
5296 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5297 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5298 #define CAN_F12R2_FB7_Pos (7U)
5299 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5300 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5301 #define CAN_F12R2_FB8_Pos (8U)
5302 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5303 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5304 #define CAN_F12R2_FB9_Pos (9U)
5305 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5306 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5307 #define CAN_F12R2_FB10_Pos (10U)
5308 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5309 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5310 #define CAN_F12R2_FB11_Pos (11U)
5311 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5312 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5313 #define CAN_F12R2_FB12_Pos (12U)
5314 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5315 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5316 #define CAN_F12R2_FB13_Pos (13U)
5317 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5318 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5319 #define CAN_F12R2_FB14_Pos (14U)
5320 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5321 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5322 #define CAN_F12R2_FB15_Pos (15U)
5323 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5324 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5325 #define CAN_F12R2_FB16_Pos (16U)
5326 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5327 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5328 #define CAN_F12R2_FB17_Pos (17U)
5329 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5330 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5331 #define CAN_F12R2_FB18_Pos (18U)
5332 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5333 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5334 #define CAN_F12R2_FB19_Pos (19U)
5335 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5336 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5337 #define CAN_F12R2_FB20_Pos (20U)
5338 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5339 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5340 #define CAN_F12R2_FB21_Pos (21U)
5341 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5342 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5343 #define CAN_F12R2_FB22_Pos (22U)
5344 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5345 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5346 #define CAN_F12R2_FB23_Pos (23U)
5347 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5348 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5349 #define CAN_F12R2_FB24_Pos (24U)
5350 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5351 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5352 #define CAN_F12R2_FB25_Pos (25U)
5353 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5354 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5355 #define CAN_F12R2_FB26_Pos (26U)
5356 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5357 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5358 #define CAN_F12R2_FB27_Pos (27U)
5359 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5360 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5361 #define CAN_F12R2_FB28_Pos (28U)
5362 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5363 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5364 #define CAN_F12R2_FB29_Pos (29U)
5365 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5366 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5367 #define CAN_F12R2_FB30_Pos (30U)
5368 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5369 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5370 #define CAN_F12R2_FB31_Pos (31U)
5371 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5372 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5373
5374 /******************* Bit definition for CAN_F13R2 register ******************/
5375 #define CAN_F13R2_FB0_Pos (0U)
5376 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5377 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5378 #define CAN_F13R2_FB1_Pos (1U)
5379 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5380 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5381 #define CAN_F13R2_FB2_Pos (2U)
5382 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5383 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5384 #define CAN_F13R2_FB3_Pos (3U)
5385 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5386 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5387 #define CAN_F13R2_FB4_Pos (4U)
5388 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5389 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5390 #define CAN_F13R2_FB5_Pos (5U)
5391 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5392 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5393 #define CAN_F13R2_FB6_Pos (6U)
5394 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5395 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5396 #define CAN_F13R2_FB7_Pos (7U)
5397 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5398 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5399 #define CAN_F13R2_FB8_Pos (8U)
5400 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5401 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5402 #define CAN_F13R2_FB9_Pos (9U)
5403 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5404 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5405 #define CAN_F13R2_FB10_Pos (10U)
5406 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5407 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5408 #define CAN_F13R2_FB11_Pos (11U)
5409 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5410 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5411 #define CAN_F13R2_FB12_Pos (12U)
5412 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5413 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5414 #define CAN_F13R2_FB13_Pos (13U)
5415 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5416 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5417 #define CAN_F13R2_FB14_Pos (14U)
5418 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5419 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5420 #define CAN_F13R2_FB15_Pos (15U)
5421 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5422 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5423 #define CAN_F13R2_FB16_Pos (16U)
5424 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5425 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5426 #define CAN_F13R2_FB17_Pos (17U)
5427 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5428 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5429 #define CAN_F13R2_FB18_Pos (18U)
5430 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5431 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5432 #define CAN_F13R2_FB19_Pos (19U)
5433 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5434 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5435 #define CAN_F13R2_FB20_Pos (20U)
5436 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5437 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5438 #define CAN_F13R2_FB21_Pos (21U)
5439 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5440 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5441 #define CAN_F13R2_FB22_Pos (22U)
5442 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5443 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5444 #define CAN_F13R2_FB23_Pos (23U)
5445 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5446 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5447 #define CAN_F13R2_FB24_Pos (24U)
5448 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5449 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5450 #define CAN_F13R2_FB25_Pos (25U)
5451 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5452 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5453 #define CAN_F13R2_FB26_Pos (26U)
5454 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5455 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5456 #define CAN_F13R2_FB27_Pos (27U)
5457 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5458 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5459 #define CAN_F13R2_FB28_Pos (28U)
5460 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5461 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5462 #define CAN_F13R2_FB29_Pos (29U)
5463 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5464 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5465 #define CAN_F13R2_FB30_Pos (30U)
5466 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5467 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5468 #define CAN_F13R2_FB31_Pos (31U)
5469 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5470 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5471
5472 /******************************************************************************/
5473 /* */
5474 /* CRC calculation unit */
5475 /* */
5476 /******************************************************************************/
5477 /******************* Bit definition for CRC_DR register *********************/
5478 #define CRC_DR_DR_Pos (0U)
5479 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5480 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5481
5482
5483 /******************* Bit definition for CRC_IDR register ********************/
5484 #define CRC_IDR_IDR_Pos (0U)
5485 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5486 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5487
5488
5489 /******************** Bit definition for CRC_CR register ********************/
5490 #define CRC_CR_RESET_Pos (0U)
5491 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5492 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5493
5494 /******************************************************************************/
5495 /* */
5496 /* Digital to Analog Converter */
5497 /* */
5498 /******************************************************************************/
5499 /*
5500 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5501 */
5502 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5503 /******************** Bit definition for DAC_CR register ********************/
5504 #define DAC_CR_EN1_Pos (0U)
5505 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5506 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5507 #define DAC_CR_BOFF1_Pos (1U)
5508 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5509 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5510 #define DAC_CR_TEN1_Pos (2U)
5511 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5512 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5513
5514 #define DAC_CR_TSEL1_Pos (3U)
5515 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5516 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5517 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5518 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5519 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5520
5521 #define DAC_CR_WAVE1_Pos (6U)
5522 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5523 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5524 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5525 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5526
5527 #define DAC_CR_MAMP1_Pos (8U)
5528 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5529 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5530 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5531 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5532 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5533 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5534
5535 #define DAC_CR_DMAEN1_Pos (12U)
5536 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5537 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5538 #define DAC_CR_DMAUDRIE1_Pos (13U)
5539 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5540 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5541 #define DAC_CR_EN2_Pos (16U)
5542 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5543 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5544 #define DAC_CR_BOFF2_Pos (17U)
5545 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5546 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5547 #define DAC_CR_TEN2_Pos (18U)
5548 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5549 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5550
5551 #define DAC_CR_TSEL2_Pos (19U)
5552 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5553 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5554 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5555 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5556 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5557
5558 #define DAC_CR_WAVE2_Pos (22U)
5559 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5560 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5561 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5562 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5563
5564 #define DAC_CR_MAMP2_Pos (24U)
5565 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5566 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5567 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5568 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5569 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5570 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5571
5572 #define DAC_CR_DMAEN2_Pos (28U)
5573 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5574 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5575 #define DAC_CR_DMAUDRIE2_Pos (29U)
5576 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5577 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5578
5579 /***************** Bit definition for DAC_SWTRIGR register ******************/
5580 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5581 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5582 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5583 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5584 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5585 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5586
5587 /***************** Bit definition for DAC_DHR12R1 register ******************/
5588 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5589 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5590 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5591
5592 /***************** Bit definition for DAC_DHR12L1 register ******************/
5593 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5594 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5595 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5596
5597 /****************** Bit definition for DAC_DHR8R1 register ******************/
5598 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5599 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5600 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5601
5602 /***************** Bit definition for DAC_DHR12R2 register ******************/
5603 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5604 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5605 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5606
5607 /***************** Bit definition for DAC_DHR12L2 register ******************/
5608 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5609 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5610 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5611
5612 /****************** Bit definition for DAC_DHR8R2 register ******************/
5613 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5614 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5615 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5616
5617 /***************** Bit definition for DAC_DHR12RD register ******************/
5618 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5619 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5620 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5621 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5622 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5623 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5624
5625 /***************** Bit definition for DAC_DHR12LD register ******************/
5626 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5627 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5628 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5629 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5630 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5631 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5632
5633 /****************** Bit definition for DAC_DHR8RD register ******************/
5634 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5635 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5636 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5637 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5638 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5639 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5640
5641 /******************* Bit definition for DAC_DOR1 register *******************/
5642 #define DAC_DOR1_DACC1DOR_Pos (0U)
5643 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5644 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5645
5646 /******************* Bit definition for DAC_DOR2 register *******************/
5647 #define DAC_DOR2_DACC2DOR_Pos (0U)
5648 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5649 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5650
5651 /******************** Bit definition for DAC_SR register ********************/
5652 #define DAC_SR_DMAUDR1_Pos (13U)
5653 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5654 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5655 #define DAC_SR_DMAUDR2_Pos (29U)
5656 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5657 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5658
5659 /******************************************************************************/
5660 /* */
5661 /* Digital Filter for Sigma Delta Modulators */
5662 /* */
5663 /******************************************************************************/
5664
5665 /**************** DFSDM channel configuration registers ********************/
5666
5667 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
5668 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
5669 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
5670 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
5671 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
5672 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
5673 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
5674 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
5675 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
5676 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
5677 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
5678 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
5679 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
5680 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
5681 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
5682 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
5683 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
5684 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
5685 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
5686 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
5687 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
5688 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
5689 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
5690 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
5691 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
5692 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
5693 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
5694 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
5695 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
5696 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
5697 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
5698 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
5699 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
5700 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
5701 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
5702 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
5703 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
5704 #define DFSDM_CHCFGR1_SITP_Pos (0U)
5705 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
5706 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
5707 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
5708 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
5709
5710 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
5711 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
5712 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
5713 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
5714 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
5715 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
5716 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
5717
5718 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
5719 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
5720 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
5721 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
5722 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
5723 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
5724 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
5725 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
5726 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
5727 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
5728 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
5729 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
5730 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
5731 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
5732 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
5733
5734 /**************** Bit definition for DFSDM_CHWDATR register *******************/
5735 #define DFSDM_CHWDATR_WDATA_Pos (0U)
5736 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
5737 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
5738
5739 /**************** Bit definition for DFSDM_CHDATINR register *****************/
5740 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
5741 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
5742 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
5743 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
5744 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
5745 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
5746
5747 /************************ DFSDM module registers ****************************/
5748
5749 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
5750 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
5751 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
5752 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
5753 #define DFSDM_FLTCR1_FAST_Pos (29U)
5754 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
5755 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
5756 #define DFSDM_FLTCR1_RCH_Pos (24U)
5757 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
5758 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
5759 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
5760 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
5761 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
5762 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
5763 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
5764 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
5765 #define DFSDM_FLTCR1_RCONT_Pos (18U)
5766 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
5767 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
5768 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
5769 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
5770 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
5771 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
5772 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
5773 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
5774 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
5775 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
5776 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
5777 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
5778 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
5779 #define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
5780 #define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
5781 #define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
5782 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
5783 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
5784 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
5785 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
5786 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
5787 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
5788 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
5789 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
5790 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
5791 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
5792 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
5793 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
5794 #define DFSDM_FLTCR1_DFEN_Pos (0U)
5795 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
5796 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
5797
5798 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
5799 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
5800 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
5801 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
5802 #define DFSDM_FLTCR2_EXCH_Pos (8U)
5803 #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
5804 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
5805 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
5806 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
5807 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
5808 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
5809 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
5810 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
5811 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
5812 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
5813 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
5814 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
5815 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
5816 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
5817 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
5818 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
5819 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
5820 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
5821 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
5822 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
5823 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
5824 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
5825 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
5826
5827 /***************** Bit definition for DFSDM_FLTISR register *******************/
5828 #define DFSDM_FLTISR_SCDF_Pos (24U)
5829 #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
5830 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
5831 #define DFSDM_FLTISR_CKABF_Pos (16U)
5832 #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
5833 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
5834 #define DFSDM_FLTISR_RCIP_Pos (14U)
5835 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
5836 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
5837 #define DFSDM_FLTISR_JCIP_Pos (13U)
5838 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
5839 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
5840 #define DFSDM_FLTISR_AWDF_Pos (4U)
5841 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
5842 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
5843 #define DFSDM_FLTISR_ROVRF_Pos (3U)
5844 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
5845 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
5846 #define DFSDM_FLTISR_JOVRF_Pos (2U)
5847 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
5848 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
5849 #define DFSDM_FLTISR_REOCF_Pos (1U)
5850 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
5851 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
5852 #define DFSDM_FLTISR_JEOCF_Pos (0U)
5853 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
5854 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
5855
5856 /***************** Bit definition for DFSDM_FLTICR register *******************/
5857 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
5858 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
5859 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
5860 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
5861 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
5862 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
5863 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
5864 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
5865 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
5866 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
5867 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
5868 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
5869
5870 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
5871 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
5872 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
5873 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
5874
5875 /***************** Bit definition for DFSDM_FLTFCR register *******************/
5876 #define DFSDM_FLTFCR_FORD_Pos (29U)
5877 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
5878 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
5879 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
5880 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
5881 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
5882 #define DFSDM_FLTFCR_FOSR_Pos (16U)
5883 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
5884 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
5885 #define DFSDM_FLTFCR_IOSR_Pos (0U)
5886 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
5887 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
5888
5889 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
5890 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
5891 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
5892 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
5893 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
5894 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
5895 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
5896
5897 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
5898 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
5899 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
5900 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
5901 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
5902 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
5903 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
5904 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
5905 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
5906 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
5907
5908 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
5909 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
5910 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
5911 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
5912 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
5913 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
5914 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
5915
5916 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
5917 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
5918 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
5919 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
5920 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
5921 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
5922 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
5923
5924 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
5925 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
5926 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
5927 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
5928 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
5929 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
5930 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
5931
5932
5933 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
5934 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
5935 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
5936 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
5937 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
5938 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
5939 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
5940
5941 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
5942 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
5943 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
5944 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
5945 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
5946 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
5947 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
5948
5949 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
5950 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
5951 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
5952 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
5953 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
5954 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
5955 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
5956
5957 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
5958 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
5959 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
5960 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
5961
5962 /******************************************************************************/
5963 /* */
5964 /* DMA Controller */
5965 /* */
5966 /******************************************************************************/
5967 /******************** Bits definition for DMA_SxCR register *****************/
5968 #define DMA_SxCR_CHSEL_Pos (25U)
5969 #define DMA_SxCR_CHSEL_Msk (0xFU << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
5970 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5971 #define DMA_SxCR_CHSEL_0 0x02000000U
5972 #define DMA_SxCR_CHSEL_1 0x04000000U
5973 #define DMA_SxCR_CHSEL_2 0x08000000U
5974 #define DMA_SxCR_CHSEL_3 0x10000000U
5975 #define DMA_SxCR_MBURST_Pos (23U)
5976 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
5977 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5978 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
5979 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
5980 #define DMA_SxCR_PBURST_Pos (21U)
5981 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
5982 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5983 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
5984 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
5985 #define DMA_SxCR_CT_Pos (19U)
5986 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
5987 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
5988 #define DMA_SxCR_DBM_Pos (18U)
5989 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
5990 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5991 #define DMA_SxCR_PL_Pos (16U)
5992 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
5993 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
5994 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
5995 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
5996 #define DMA_SxCR_PINCOS_Pos (15U)
5997 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
5998 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5999 #define DMA_SxCR_MSIZE_Pos (13U)
6000 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6001 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6002 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6003 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6004 #define DMA_SxCR_PSIZE_Pos (11U)
6005 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6006 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6007 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6008 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6009 #define DMA_SxCR_MINC_Pos (10U)
6010 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6011 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6012 #define DMA_SxCR_PINC_Pos (9U)
6013 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6014 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6015 #define DMA_SxCR_CIRC_Pos (8U)
6016 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6017 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6018 #define DMA_SxCR_DIR_Pos (6U)
6019 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6020 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6021 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6022 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6023 #define DMA_SxCR_PFCTRL_Pos (5U)
6024 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6025 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6026 #define DMA_SxCR_TCIE_Pos (4U)
6027 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6028 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6029 #define DMA_SxCR_HTIE_Pos (3U)
6030 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6031 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6032 #define DMA_SxCR_TEIE_Pos (2U)
6033 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6034 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6035 #define DMA_SxCR_DMEIE_Pos (1U)
6036 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6037 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6038 #define DMA_SxCR_EN_Pos (0U)
6039 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6040 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
6041
6042 /* Legacy defines */
6043 #define DMA_SxCR_ACK_Pos (20U)
6044 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
6045 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6046
6047 /******************** Bits definition for DMA_SxCNDTR register **************/
6048 #define DMA_SxNDT_Pos (0U)
6049 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6050 #define DMA_SxNDT DMA_SxNDT_Msk
6051 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
6052 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
6053 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
6054 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
6055 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
6056 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
6057 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
6058 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
6059 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
6060 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
6061 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
6062 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
6063 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
6064 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
6065 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
6066 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
6067
6068 /******************** Bits definition for DMA_SxFCR register ****************/
6069 #define DMA_SxFCR_FEIE_Pos (7U)
6070 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6071 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6072 #define DMA_SxFCR_FS_Pos (3U)
6073 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6074 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6075 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6076 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6077 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6078 #define DMA_SxFCR_DMDIS_Pos (2U)
6079 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6080 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6081 #define DMA_SxFCR_FTH_Pos (0U)
6082 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6083 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6084 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6085 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6086
6087 /******************** Bits definition for DMA_LISR register *****************/
6088 #define DMA_LISR_TCIF3_Pos (27U)
6089 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6090 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6091 #define DMA_LISR_HTIF3_Pos (26U)
6092 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6093 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6094 #define DMA_LISR_TEIF3_Pos (25U)
6095 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6096 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6097 #define DMA_LISR_DMEIF3_Pos (24U)
6098 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6099 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6100 #define DMA_LISR_FEIF3_Pos (22U)
6101 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6102 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6103 #define DMA_LISR_TCIF2_Pos (21U)
6104 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6105 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6106 #define DMA_LISR_HTIF2_Pos (20U)
6107 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6108 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6109 #define DMA_LISR_TEIF2_Pos (19U)
6110 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6111 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6112 #define DMA_LISR_DMEIF2_Pos (18U)
6113 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6114 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6115 #define DMA_LISR_FEIF2_Pos (16U)
6116 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6117 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6118 #define DMA_LISR_TCIF1_Pos (11U)
6119 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6120 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6121 #define DMA_LISR_HTIF1_Pos (10U)
6122 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6123 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6124 #define DMA_LISR_TEIF1_Pos (9U)
6125 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6126 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6127 #define DMA_LISR_DMEIF1_Pos (8U)
6128 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6129 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6130 #define DMA_LISR_FEIF1_Pos (6U)
6131 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6132 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6133 #define DMA_LISR_TCIF0_Pos (5U)
6134 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6135 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6136 #define DMA_LISR_HTIF0_Pos (4U)
6137 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6138 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6139 #define DMA_LISR_TEIF0_Pos (3U)
6140 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6141 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6142 #define DMA_LISR_DMEIF0_Pos (2U)
6143 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6144 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6145 #define DMA_LISR_FEIF0_Pos (0U)
6146 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6147 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6148
6149 /******************** Bits definition for DMA_HISR register *****************/
6150 #define DMA_HISR_TCIF7_Pos (27U)
6151 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6152 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6153 #define DMA_HISR_HTIF7_Pos (26U)
6154 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6155 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6156 #define DMA_HISR_TEIF7_Pos (25U)
6157 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6158 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6159 #define DMA_HISR_DMEIF7_Pos (24U)
6160 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6161 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6162 #define DMA_HISR_FEIF7_Pos (22U)
6163 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6164 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6165 #define DMA_HISR_TCIF6_Pos (21U)
6166 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6167 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6168 #define DMA_HISR_HTIF6_Pos (20U)
6169 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6170 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6171 #define DMA_HISR_TEIF6_Pos (19U)
6172 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6173 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6174 #define DMA_HISR_DMEIF6_Pos (18U)
6175 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6176 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6177 #define DMA_HISR_FEIF6_Pos (16U)
6178 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6179 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6180 #define DMA_HISR_TCIF5_Pos (11U)
6181 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6182 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6183 #define DMA_HISR_HTIF5_Pos (10U)
6184 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6185 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6186 #define DMA_HISR_TEIF5_Pos (9U)
6187 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6188 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6189 #define DMA_HISR_DMEIF5_Pos (8U)
6190 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6191 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6192 #define DMA_HISR_FEIF5_Pos (6U)
6193 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6194 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6195 #define DMA_HISR_TCIF4_Pos (5U)
6196 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6197 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6198 #define DMA_HISR_HTIF4_Pos (4U)
6199 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6200 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6201 #define DMA_HISR_TEIF4_Pos (3U)
6202 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6203 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6204 #define DMA_HISR_DMEIF4_Pos (2U)
6205 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6206 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6207 #define DMA_HISR_FEIF4_Pos (0U)
6208 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6209 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6210
6211 /******************** Bits definition for DMA_LIFCR register ****************/
6212 #define DMA_LIFCR_CTCIF3_Pos (27U)
6213 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6214 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6215 #define DMA_LIFCR_CHTIF3_Pos (26U)
6216 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6217 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6218 #define DMA_LIFCR_CTEIF3_Pos (25U)
6219 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6220 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6221 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6222 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6223 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6224 #define DMA_LIFCR_CFEIF3_Pos (22U)
6225 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6226 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6227 #define DMA_LIFCR_CTCIF2_Pos (21U)
6228 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6229 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6230 #define DMA_LIFCR_CHTIF2_Pos (20U)
6231 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6232 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6233 #define DMA_LIFCR_CTEIF2_Pos (19U)
6234 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6235 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6236 #define DMA_LIFCR_CDMEIF2_Pos (18U)
6237 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6238 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6239 #define DMA_LIFCR_CFEIF2_Pos (16U)
6240 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6241 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6242 #define DMA_LIFCR_CTCIF1_Pos (11U)
6243 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6244 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6245 #define DMA_LIFCR_CHTIF1_Pos (10U)
6246 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6247 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6248 #define DMA_LIFCR_CTEIF1_Pos (9U)
6249 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6250 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6251 #define DMA_LIFCR_CDMEIF1_Pos (8U)
6252 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6253 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6254 #define DMA_LIFCR_CFEIF1_Pos (6U)
6255 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6256 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6257 #define DMA_LIFCR_CTCIF0_Pos (5U)
6258 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6259 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6260 #define DMA_LIFCR_CHTIF0_Pos (4U)
6261 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6262 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6263 #define DMA_LIFCR_CTEIF0_Pos (3U)
6264 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6265 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6266 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6267 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6268 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6269 #define DMA_LIFCR_CFEIF0_Pos (0U)
6270 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6271 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6272
6273 /******************** Bits definition for DMA_HIFCR register ****************/
6274 #define DMA_HIFCR_CTCIF7_Pos (27U)
6275 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6276 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6277 #define DMA_HIFCR_CHTIF7_Pos (26U)
6278 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6279 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6280 #define DMA_HIFCR_CTEIF7_Pos (25U)
6281 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6282 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6283 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6284 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6285 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6286 #define DMA_HIFCR_CFEIF7_Pos (22U)
6287 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6288 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6289 #define DMA_HIFCR_CTCIF6_Pos (21U)
6290 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6291 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6292 #define DMA_HIFCR_CHTIF6_Pos (20U)
6293 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6294 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6295 #define DMA_HIFCR_CTEIF6_Pos (19U)
6296 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6297 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6298 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6299 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6300 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6301 #define DMA_HIFCR_CFEIF6_Pos (16U)
6302 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6303 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6304 #define DMA_HIFCR_CTCIF5_Pos (11U)
6305 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6306 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6307 #define DMA_HIFCR_CHTIF5_Pos (10U)
6308 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6309 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6310 #define DMA_HIFCR_CTEIF5_Pos (9U)
6311 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6312 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6313 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6314 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6315 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6316 #define DMA_HIFCR_CFEIF5_Pos (6U)
6317 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6318 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6319 #define DMA_HIFCR_CTCIF4_Pos (5U)
6320 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6321 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6322 #define DMA_HIFCR_CHTIF4_Pos (4U)
6323 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6324 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6325 #define DMA_HIFCR_CTEIF4_Pos (3U)
6326 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6327 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6328 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6329 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6330 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6331 #define DMA_HIFCR_CFEIF4_Pos (0U)
6332 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6333 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6334
6335 /****************** Bit definition for DMA_SxPAR register ********************/
6336 #define DMA_SxPAR_PA_Pos (0U)
6337 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6338 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6339
6340 /****************** Bit definition for DMA_SxM0AR register ********************/
6341 #define DMA_SxM0AR_M0A_Pos (0U)
6342 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6343 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6344
6345 /****************** Bit definition for DMA_SxM1AR register ********************/
6346 #define DMA_SxM1AR_M1A_Pos (0U)
6347 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6348 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6349
6350
6351 /******************************************************************************/
6352 /* */
6353 /* External Interrupt/Event Controller */
6354 /* */
6355 /******************************************************************************/
6356 /******************* Bit definition for EXTI_IMR register *******************/
6357 #define EXTI_IMR_MR0_Pos (0U)
6358 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
6359 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
6360 #define EXTI_IMR_MR1_Pos (1U)
6361 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
6362 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
6363 #define EXTI_IMR_MR2_Pos (2U)
6364 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
6365 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
6366 #define EXTI_IMR_MR3_Pos (3U)
6367 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
6368 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
6369 #define EXTI_IMR_MR4_Pos (4U)
6370 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
6371 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
6372 #define EXTI_IMR_MR5_Pos (5U)
6373 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
6374 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
6375 #define EXTI_IMR_MR6_Pos (6U)
6376 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
6377 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
6378 #define EXTI_IMR_MR7_Pos (7U)
6379 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
6380 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
6381 #define EXTI_IMR_MR8_Pos (8U)
6382 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
6383 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
6384 #define EXTI_IMR_MR9_Pos (9U)
6385 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
6386 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
6387 #define EXTI_IMR_MR10_Pos (10U)
6388 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
6389 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
6390 #define EXTI_IMR_MR11_Pos (11U)
6391 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
6392 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
6393 #define EXTI_IMR_MR12_Pos (12U)
6394 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
6395 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
6396 #define EXTI_IMR_MR13_Pos (13U)
6397 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
6398 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
6399 #define EXTI_IMR_MR14_Pos (14U)
6400 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
6401 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
6402 #define EXTI_IMR_MR15_Pos (15U)
6403 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
6404 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
6405 #define EXTI_IMR_MR16_Pos (16U)
6406 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
6407 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
6408 #define EXTI_IMR_MR17_Pos (17U)
6409 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
6410 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
6411 #define EXTI_IMR_MR18_Pos (18U)
6412 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
6413 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
6414 #define EXTI_IMR_MR19_Pos (19U)
6415 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
6416 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
6417 #define EXTI_IMR_MR20_Pos (20U)
6418 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
6419 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
6420 #define EXTI_IMR_MR21_Pos (21U)
6421 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
6422 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
6423 #define EXTI_IMR_MR22_Pos (22U)
6424 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
6425 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
6426 #define EXTI_IMR_MR23_Pos (23U)
6427 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
6428 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
6429
6430 /* Reference Defines */
6431 #define EXTI_IMR_IM0 EXTI_IMR_MR0
6432 #define EXTI_IMR_IM1 EXTI_IMR_MR1
6433 #define EXTI_IMR_IM2 EXTI_IMR_MR2
6434 #define EXTI_IMR_IM3 EXTI_IMR_MR3
6435 #define EXTI_IMR_IM4 EXTI_IMR_MR4
6436 #define EXTI_IMR_IM5 EXTI_IMR_MR5
6437 #define EXTI_IMR_IM6 EXTI_IMR_MR6
6438 #define EXTI_IMR_IM7 EXTI_IMR_MR7
6439 #define EXTI_IMR_IM8 EXTI_IMR_MR8
6440 #define EXTI_IMR_IM9 EXTI_IMR_MR9
6441 #define EXTI_IMR_IM10 EXTI_IMR_MR10
6442 #define EXTI_IMR_IM11 EXTI_IMR_MR11
6443 #define EXTI_IMR_IM12 EXTI_IMR_MR12
6444 #define EXTI_IMR_IM13 EXTI_IMR_MR13
6445 #define EXTI_IMR_IM14 EXTI_IMR_MR14
6446 #define EXTI_IMR_IM15 EXTI_IMR_MR15
6447 #define EXTI_IMR_IM16 EXTI_IMR_MR16
6448 #define EXTI_IMR_IM17 EXTI_IMR_MR17
6449 #define EXTI_IMR_IM18 EXTI_IMR_MR18
6450 #define EXTI_IMR_IM19 EXTI_IMR_MR19
6451 #define EXTI_IMR_IM20 EXTI_IMR_MR20
6452 #define EXTI_IMR_IM21 EXTI_IMR_MR21
6453 #define EXTI_IMR_IM22 EXTI_IMR_MR22
6454 #define EXTI_IMR_IM23 EXTI_IMR_MR23
6455 #define EXTI_IMR_IM_Pos (0U)
6456 #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
6457 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
6458
6459 /******************* Bit definition for EXTI_EMR register *******************/
6460 #define EXTI_EMR_MR0_Pos (0U)
6461 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
6462 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
6463 #define EXTI_EMR_MR1_Pos (1U)
6464 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
6465 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
6466 #define EXTI_EMR_MR2_Pos (2U)
6467 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
6468 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
6469 #define EXTI_EMR_MR3_Pos (3U)
6470 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
6471 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
6472 #define EXTI_EMR_MR4_Pos (4U)
6473 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
6474 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
6475 #define EXTI_EMR_MR5_Pos (5U)
6476 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
6477 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
6478 #define EXTI_EMR_MR6_Pos (6U)
6479 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
6480 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
6481 #define EXTI_EMR_MR7_Pos (7U)
6482 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
6483 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
6484 #define EXTI_EMR_MR8_Pos (8U)
6485 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
6486 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
6487 #define EXTI_EMR_MR9_Pos (9U)
6488 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
6489 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
6490 #define EXTI_EMR_MR10_Pos (10U)
6491 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
6492 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
6493 #define EXTI_EMR_MR11_Pos (11U)
6494 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
6495 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
6496 #define EXTI_EMR_MR12_Pos (12U)
6497 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
6498 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
6499 #define EXTI_EMR_MR13_Pos (13U)
6500 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
6501 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
6502 #define EXTI_EMR_MR14_Pos (14U)
6503 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
6504 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
6505 #define EXTI_EMR_MR15_Pos (15U)
6506 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
6507 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
6508 #define EXTI_EMR_MR16_Pos (16U)
6509 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
6510 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
6511 #define EXTI_EMR_MR17_Pos (17U)
6512 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
6513 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
6514 #define EXTI_EMR_MR18_Pos (18U)
6515 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
6516 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
6517 #define EXTI_EMR_MR19_Pos (19U)
6518 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
6519 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
6520 #define EXTI_EMR_MR20_Pos (20U)
6521 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
6522 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
6523 #define EXTI_EMR_MR21_Pos (21U)
6524 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
6525 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
6526 #define EXTI_EMR_MR22_Pos (22U)
6527 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
6528 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
6529 #define EXTI_EMR_MR23_Pos (23U)
6530 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
6531 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
6532
6533 /* Reference Defines */
6534 #define EXTI_EMR_EM0 EXTI_EMR_MR0
6535 #define EXTI_EMR_EM1 EXTI_EMR_MR1
6536 #define EXTI_EMR_EM2 EXTI_EMR_MR2
6537 #define EXTI_EMR_EM3 EXTI_EMR_MR3
6538 #define EXTI_EMR_EM4 EXTI_EMR_MR4
6539 #define EXTI_EMR_EM5 EXTI_EMR_MR5
6540 #define EXTI_EMR_EM6 EXTI_EMR_MR6
6541 #define EXTI_EMR_EM7 EXTI_EMR_MR7
6542 #define EXTI_EMR_EM8 EXTI_EMR_MR8
6543 #define EXTI_EMR_EM9 EXTI_EMR_MR9
6544 #define EXTI_EMR_EM10 EXTI_EMR_MR10
6545 #define EXTI_EMR_EM11 EXTI_EMR_MR11
6546 #define EXTI_EMR_EM12 EXTI_EMR_MR12
6547 #define EXTI_EMR_EM13 EXTI_EMR_MR13
6548 #define EXTI_EMR_EM14 EXTI_EMR_MR14
6549 #define EXTI_EMR_EM15 EXTI_EMR_MR15
6550 #define EXTI_EMR_EM16 EXTI_EMR_MR16
6551 #define EXTI_EMR_EM17 EXTI_EMR_MR17
6552 #define EXTI_EMR_EM18 EXTI_EMR_MR18
6553 #define EXTI_EMR_EM19 EXTI_EMR_MR19
6554 #define EXTI_EMR_EM20 EXTI_EMR_MR20
6555 #define EXTI_EMR_EM21 EXTI_EMR_MR21
6556 #define EXTI_EMR_EM22 EXTI_EMR_MR22
6557 #define EXTI_EMR_EM23 EXTI_EMR_MR23
6558
6559 /****************** Bit definition for EXTI_RTSR register *******************/
6560 #define EXTI_RTSR_TR0_Pos (0U)
6561 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
6562 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
6563 #define EXTI_RTSR_TR1_Pos (1U)
6564 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
6565 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
6566 #define EXTI_RTSR_TR2_Pos (2U)
6567 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
6568 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
6569 #define EXTI_RTSR_TR3_Pos (3U)
6570 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
6571 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
6572 #define EXTI_RTSR_TR4_Pos (4U)
6573 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
6574 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
6575 #define EXTI_RTSR_TR5_Pos (5U)
6576 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
6577 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
6578 #define EXTI_RTSR_TR6_Pos (6U)
6579 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
6580 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
6581 #define EXTI_RTSR_TR7_Pos (7U)
6582 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
6583 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
6584 #define EXTI_RTSR_TR8_Pos (8U)
6585 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
6586 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
6587 #define EXTI_RTSR_TR9_Pos (9U)
6588 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
6589 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
6590 #define EXTI_RTSR_TR10_Pos (10U)
6591 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
6592 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
6593 #define EXTI_RTSR_TR11_Pos (11U)
6594 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
6595 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
6596 #define EXTI_RTSR_TR12_Pos (12U)
6597 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
6598 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
6599 #define EXTI_RTSR_TR13_Pos (13U)
6600 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
6601 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
6602 #define EXTI_RTSR_TR14_Pos (14U)
6603 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
6604 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
6605 #define EXTI_RTSR_TR15_Pos (15U)
6606 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
6607 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
6608 #define EXTI_RTSR_TR16_Pos (16U)
6609 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
6610 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
6611 #define EXTI_RTSR_TR17_Pos (17U)
6612 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
6613 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
6614 #define EXTI_RTSR_TR18_Pos (18U)
6615 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
6616 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
6617 #define EXTI_RTSR_TR19_Pos (19U)
6618 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
6619 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
6620 #define EXTI_RTSR_TR20_Pos (20U)
6621 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
6622 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
6623 #define EXTI_RTSR_TR21_Pos (21U)
6624 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
6625 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
6626 #define EXTI_RTSR_TR22_Pos (22U)
6627 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
6628 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
6629 #define EXTI_RTSR_TR23_Pos (23U)
6630 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
6631 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
6632
6633 /****************** Bit definition for EXTI_FTSR register *******************/
6634 #define EXTI_FTSR_TR0_Pos (0U)
6635 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
6636 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
6637 #define EXTI_FTSR_TR1_Pos (1U)
6638 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
6639 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
6640 #define EXTI_FTSR_TR2_Pos (2U)
6641 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
6642 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
6643 #define EXTI_FTSR_TR3_Pos (3U)
6644 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
6645 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
6646 #define EXTI_FTSR_TR4_Pos (4U)
6647 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
6648 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
6649 #define EXTI_FTSR_TR5_Pos (5U)
6650 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
6651 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
6652 #define EXTI_FTSR_TR6_Pos (6U)
6653 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
6654 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
6655 #define EXTI_FTSR_TR7_Pos (7U)
6656 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
6657 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
6658 #define EXTI_FTSR_TR8_Pos (8U)
6659 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
6660 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
6661 #define EXTI_FTSR_TR9_Pos (9U)
6662 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
6663 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
6664 #define EXTI_FTSR_TR10_Pos (10U)
6665 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
6666 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
6667 #define EXTI_FTSR_TR11_Pos (11U)
6668 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
6669 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
6670 #define EXTI_FTSR_TR12_Pos (12U)
6671 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
6672 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
6673 #define EXTI_FTSR_TR13_Pos (13U)
6674 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
6675 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
6676 #define EXTI_FTSR_TR14_Pos (14U)
6677 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
6678 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
6679 #define EXTI_FTSR_TR15_Pos (15U)
6680 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
6681 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
6682 #define EXTI_FTSR_TR16_Pos (16U)
6683 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
6684 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
6685 #define EXTI_FTSR_TR17_Pos (17U)
6686 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
6687 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
6688 #define EXTI_FTSR_TR18_Pos (18U)
6689 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
6690 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
6691 #define EXTI_FTSR_TR19_Pos (19U)
6692 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
6693 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
6694 #define EXTI_FTSR_TR20_Pos (20U)
6695 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
6696 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
6697 #define EXTI_FTSR_TR21_Pos (21U)
6698 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
6699 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
6700 #define EXTI_FTSR_TR22_Pos (22U)
6701 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
6702 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
6703 #define EXTI_FTSR_TR23_Pos (23U)
6704 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
6705 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
6706
6707 /****************** Bit definition for EXTI_SWIER register ******************/
6708 #define EXTI_SWIER_SWIER0_Pos (0U)
6709 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
6710 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
6711 #define EXTI_SWIER_SWIER1_Pos (1U)
6712 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
6713 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
6714 #define EXTI_SWIER_SWIER2_Pos (2U)
6715 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
6716 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
6717 #define EXTI_SWIER_SWIER3_Pos (3U)
6718 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
6719 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
6720 #define EXTI_SWIER_SWIER4_Pos (4U)
6721 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
6722 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
6723 #define EXTI_SWIER_SWIER5_Pos (5U)
6724 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
6725 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
6726 #define EXTI_SWIER_SWIER6_Pos (6U)
6727 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
6728 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
6729 #define EXTI_SWIER_SWIER7_Pos (7U)
6730 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
6731 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
6732 #define EXTI_SWIER_SWIER8_Pos (8U)
6733 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
6734 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
6735 #define EXTI_SWIER_SWIER9_Pos (9U)
6736 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
6737 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
6738 #define EXTI_SWIER_SWIER10_Pos (10U)
6739 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
6740 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
6741 #define EXTI_SWIER_SWIER11_Pos (11U)
6742 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
6743 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
6744 #define EXTI_SWIER_SWIER12_Pos (12U)
6745 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
6746 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
6747 #define EXTI_SWIER_SWIER13_Pos (13U)
6748 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
6749 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
6750 #define EXTI_SWIER_SWIER14_Pos (14U)
6751 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
6752 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
6753 #define EXTI_SWIER_SWIER15_Pos (15U)
6754 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
6755 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
6756 #define EXTI_SWIER_SWIER16_Pos (16U)
6757 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
6758 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
6759 #define EXTI_SWIER_SWIER17_Pos (17U)
6760 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
6761 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
6762 #define EXTI_SWIER_SWIER18_Pos (18U)
6763 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
6764 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
6765 #define EXTI_SWIER_SWIER19_Pos (19U)
6766 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
6767 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
6768 #define EXTI_SWIER_SWIER20_Pos (20U)
6769 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
6770 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
6771 #define EXTI_SWIER_SWIER21_Pos (21U)
6772 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
6773 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
6774 #define EXTI_SWIER_SWIER22_Pos (22U)
6775 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
6776 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
6777 #define EXTI_SWIER_SWIER23_Pos (23U)
6778 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
6779 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
6780
6781 /******************* Bit definition for EXTI_PR register ********************/
6782 #define EXTI_PR_PR0_Pos (0U)
6783 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
6784 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
6785 #define EXTI_PR_PR1_Pos (1U)
6786 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
6787 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
6788 #define EXTI_PR_PR2_Pos (2U)
6789 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
6790 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
6791 #define EXTI_PR_PR3_Pos (3U)
6792 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
6793 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
6794 #define EXTI_PR_PR4_Pos (4U)
6795 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
6796 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
6797 #define EXTI_PR_PR5_Pos (5U)
6798 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
6799 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
6800 #define EXTI_PR_PR6_Pos (6U)
6801 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
6802 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
6803 #define EXTI_PR_PR7_Pos (7U)
6804 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
6805 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
6806 #define EXTI_PR_PR8_Pos (8U)
6807 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
6808 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
6809 #define EXTI_PR_PR9_Pos (9U)
6810 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
6811 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
6812 #define EXTI_PR_PR10_Pos (10U)
6813 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
6814 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
6815 #define EXTI_PR_PR11_Pos (11U)
6816 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
6817 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
6818 #define EXTI_PR_PR12_Pos (12U)
6819 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
6820 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
6821 #define EXTI_PR_PR13_Pos (13U)
6822 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
6823 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
6824 #define EXTI_PR_PR14_Pos (14U)
6825 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
6826 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
6827 #define EXTI_PR_PR15_Pos (15U)
6828 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
6829 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
6830 #define EXTI_PR_PR16_Pos (16U)
6831 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
6832 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
6833 #define EXTI_PR_PR17_Pos (17U)
6834 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
6835 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
6836 #define EXTI_PR_PR18_Pos (18U)
6837 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
6838 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
6839 #define EXTI_PR_PR19_Pos (19U)
6840 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
6841 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
6842 #define EXTI_PR_PR20_Pos (20U)
6843 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
6844 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
6845 #define EXTI_PR_PR21_Pos (21U)
6846 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
6847 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
6848 #define EXTI_PR_PR22_Pos (22U)
6849 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
6850 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
6851 #define EXTI_PR_PR23_Pos (23U)
6852 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
6853 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
6854
6855 /******************************************************************************/
6856 /* */
6857 /* FLASH */
6858 /* */
6859 /******************************************************************************/
6860 /******************* Bits definition for FLASH_ACR register *****************/
6861 #define FLASH_ACR_LATENCY_Pos (0U)
6862 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
6863 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6864 #define FLASH_ACR_LATENCY_0WS 0x00000000U
6865 #define FLASH_ACR_LATENCY_1WS 0x00000001U
6866 #define FLASH_ACR_LATENCY_2WS 0x00000002U
6867 #define FLASH_ACR_LATENCY_3WS 0x00000003U
6868 #define FLASH_ACR_LATENCY_4WS 0x00000004U
6869 #define FLASH_ACR_LATENCY_5WS 0x00000005U
6870 #define FLASH_ACR_LATENCY_6WS 0x00000006U
6871 #define FLASH_ACR_LATENCY_7WS 0x00000007U
6872
6873 #define FLASH_ACR_PRFTEN_Pos (8U)
6874 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
6875 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6876 #define FLASH_ACR_ICEN_Pos (9U)
6877 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
6878 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6879 #define FLASH_ACR_DCEN_Pos (10U)
6880 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
6881 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6882 #define FLASH_ACR_ICRST_Pos (11U)
6883 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
6884 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6885 #define FLASH_ACR_DCRST_Pos (12U)
6886 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
6887 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6888 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6889 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
6890 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6891 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6892 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
6893 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6894
6895 /******************* Bits definition for FLASH_SR register ******************/
6896 #define FLASH_SR_EOP_Pos (0U)
6897 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
6898 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
6899 #define FLASH_SR_SOP_Pos (1U)
6900 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
6901 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
6902 #define FLASH_SR_WRPERR_Pos (4U)
6903 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
6904 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6905 #define FLASH_SR_PGAERR_Pos (5U)
6906 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
6907 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6908 #define FLASH_SR_PGPERR_Pos (6U)
6909 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
6910 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6911 #define FLASH_SR_PGSERR_Pos (7U)
6912 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
6913 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6914 #define FLASH_SR_RDERR_Pos (8U)
6915 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
6916 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
6917 #define FLASH_SR_BSY_Pos (16U)
6918 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
6919 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
6920
6921 /******************* Bits definition for FLASH_CR register ******************/
6922 #define FLASH_CR_PG_Pos (0U)
6923 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
6924 #define FLASH_CR_PG FLASH_CR_PG_Msk
6925 #define FLASH_CR_SER_Pos (1U)
6926 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
6927 #define FLASH_CR_SER FLASH_CR_SER_Msk
6928 #define FLASH_CR_MER_Pos (2U)
6929 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
6930 #define FLASH_CR_MER FLASH_CR_MER_Msk
6931 #define FLASH_CR_SNB_Pos (3U)
6932 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
6933 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
6934 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
6935 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
6936 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
6937 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
6938 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
6939 #define FLASH_CR_PSIZE_Pos (8U)
6940 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
6941 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6942 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
6943 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
6944 #define FLASH_CR_STRT_Pos (16U)
6945 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
6946 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
6947 #define FLASH_CR_EOPIE_Pos (24U)
6948 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
6949 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6950 #define FLASH_CR_LOCK_Pos (31U)
6951 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
6952 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6953
6954 /******************* Bits definition for FLASH_OPTCR register ***************/
6955 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
6956 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
6957 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6958 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
6959 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
6960 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6961
6962 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6963 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6964 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
6965 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
6966 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6967 #define FLASH_OPTCR_WDG_SW_Pos (5U)
6968 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
6969 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6970 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
6971 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
6972 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6973 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6974 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
6975 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6976 #define FLASH_OPTCR_RDP_Pos (8U)
6977 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
6978 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6979 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
6980 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
6981 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
6982 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
6983 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
6984 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
6985 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
6986 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
6987 #define FLASH_OPTCR_nWRP_Pos (16U)
6988 #define FLASH_OPTCR_nWRP_Msk (0x7FFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x7FFF0000 */
6989 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6990 #define FLASH_OPTCR_nWRP_0 0x00010000U
6991 #define FLASH_OPTCR_nWRP_1 0x00020000U
6992 #define FLASH_OPTCR_nWRP_2 0x00040000U
6993 #define FLASH_OPTCR_nWRP_3 0x00080000U
6994 #define FLASH_OPTCR_nWRP_4 0x00100000U
6995 #define FLASH_OPTCR_nWRP_5 0x00200000U
6996 #define FLASH_OPTCR_nWRP_6 0x00400000U
6997 #define FLASH_OPTCR_nWRP_7 0x00800000U
6998 #define FLASH_OPTCR_nWRP_8 0x01000000U
6999 #define FLASH_OPTCR_nWRP_9 0x02000000U
7000 #define FLASH_OPTCR_nWRP_10 0x04000000U
7001 #define FLASH_OPTCR_nWRP_11 0x08000000U
7002 #define FLASH_OPTCR_nWRP_12 0x10000000U
7003 #define FLASH_OPTCR_nWRP_13 0x20000000U
7004 #define FLASH_OPTCR_nWRP_14 0x40000000U
7005 #define FLASH_OPTCR_nWRP_15 0x40000000U
7006
7007 /****************** Bits definition for FLASH_OPTCR1 register ***************/
7008 #define FLASH_OPTCR1_nWRP_Pos (16U)
7009 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
7010 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
7011 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
7012 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
7013 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
7014 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
7015 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
7016 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
7017 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
7018 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
7019 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
7020 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
7021 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
7022 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
7023
7024 /******************************************************************************/
7025 /* */
7026 /* Flexible Static Memory Controller */
7027 /* */
7028 /******************************************************************************/
7029 /****************** Bit definition for FSMC_BCR1 register *******************/
7030 #define FSMC_BCR1_MBKEN_Pos (0U)
7031 #define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
7032 #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
7033 #define FSMC_BCR1_MUXEN_Pos (1U)
7034 #define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
7035 #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7036
7037 #define FSMC_BCR1_MTYP_Pos (2U)
7038 #define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
7039 #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7040 #define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
7041 #define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
7042
7043 #define FSMC_BCR1_MWID_Pos (4U)
7044 #define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
7045 #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7046 #define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
7047 #define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
7048
7049 #define FSMC_BCR1_FACCEN_Pos (6U)
7050 #define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
7051 #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
7052 #define FSMC_BCR1_BURSTEN_Pos (8U)
7053 #define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
7054 #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
7055 #define FSMC_BCR1_WAITPOL_Pos (9U)
7056 #define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
7057 #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
7058 #define FSMC_BCR1_WAITCFG_Pos (11U)
7059 #define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
7060 #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
7061 #define FSMC_BCR1_WREN_Pos (12U)
7062 #define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
7063 #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
7064 #define FSMC_BCR1_WAITEN_Pos (13U)
7065 #define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
7066 #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
7067 #define FSMC_BCR1_EXTMOD_Pos (14U)
7068 #define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
7069 #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
7070 #define FSMC_BCR1_ASYNCWAIT_Pos (15U)
7071 #define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
7072 #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
7073 #define FSMC_BCR1_CPSIZE_Pos (16U)
7074 #define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
7075 #define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
7076 #define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
7077 #define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
7078 #define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
7079 #define FSMC_BCR1_CBURSTRW_Pos (19U)
7080 #define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
7081 #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
7082 #define FSMC_BCR1_CCLKEN_Pos (20U)
7083 #define FSMC_BCR1_CCLKEN_Msk (0x1U << FSMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
7084 #define FSMC_BCR1_CCLKEN FSMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
7085 #define FSMC_BCR1_WFDIS_Pos (21U)
7086 #define FSMC_BCR1_WFDIS_Msk (0x1U << FSMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
7087 #define FSMC_BCR1_WFDIS FSMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
7088
7089 /****************** Bit definition for FSMC_BCR2 register *******************/
7090 #define FSMC_BCR2_MBKEN_Pos (0U)
7091 #define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
7092 #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
7093 #define FSMC_BCR2_MUXEN_Pos (1U)
7094 #define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
7095 #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7096
7097 #define FSMC_BCR2_MTYP_Pos (2U)
7098 #define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
7099 #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7100 #define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
7101 #define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
7102
7103 #define FSMC_BCR2_MWID_Pos (4U)
7104 #define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
7105 #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7106 #define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
7107 #define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
7108
7109 #define FSMC_BCR2_FACCEN_Pos (6U)
7110 #define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
7111 #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
7112 #define FSMC_BCR2_BURSTEN_Pos (8U)
7113 #define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
7114 #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
7115 #define FSMC_BCR2_WAITPOL_Pos (9U)
7116 #define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
7117 #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
7118 #define FSMC_BCR2_WAITCFG_Pos (11U)
7119 #define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
7120 #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
7121 #define FSMC_BCR2_WREN_Pos (12U)
7122 #define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
7123 #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
7124 #define FSMC_BCR2_WAITEN_Pos (13U)
7125 #define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
7126 #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
7127 #define FSMC_BCR2_EXTMOD_Pos (14U)
7128 #define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
7129 #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
7130 #define FSMC_BCR2_ASYNCWAIT_Pos (15U)
7131 #define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
7132 #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
7133 #define FSMC_BCR2_CPSIZE_Pos (16U)
7134 #define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
7135 #define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
7136 #define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
7137 #define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
7138 #define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
7139 #define FSMC_BCR2_CBURSTRW_Pos (19U)
7140 #define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
7141 #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
7142
7143 /****************** Bit definition for FSMC_BCR3 register *******************/
7144 #define FSMC_BCR3_MBKEN_Pos (0U)
7145 #define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
7146 #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
7147 #define FSMC_BCR3_MUXEN_Pos (1U)
7148 #define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
7149 #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7150
7151 #define FSMC_BCR3_MTYP_Pos (2U)
7152 #define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
7153 #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7154 #define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
7155 #define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
7156
7157 #define FSMC_BCR3_MWID_Pos (4U)
7158 #define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
7159 #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7160 #define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
7161 #define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
7162
7163 #define FSMC_BCR3_FACCEN_Pos (6U)
7164 #define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
7165 #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
7166 #define FSMC_BCR3_BURSTEN_Pos (8U)
7167 #define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
7168 #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
7169 #define FSMC_BCR3_WAITPOL_Pos (9U)
7170 #define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
7171 #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
7172 #define FSMC_BCR3_WAITCFG_Pos (11U)
7173 #define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
7174 #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
7175 #define FSMC_BCR3_WREN_Pos (12U)
7176 #define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
7177 #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
7178 #define FSMC_BCR3_WAITEN_Pos (13U)
7179 #define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
7180 #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
7181 #define FSMC_BCR3_EXTMOD_Pos (14U)
7182 #define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
7183 #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
7184 #define FSMC_BCR3_ASYNCWAIT_Pos (15U)
7185 #define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
7186 #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
7187 #define FSMC_BCR3_CPSIZE_Pos (16U)
7188 #define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
7189 #define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
7190 #define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
7191 #define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
7192 #define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
7193 #define FSMC_BCR3_CBURSTRW_Pos (19U)
7194 #define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
7195 #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
7196
7197 /****************** Bit definition for FSMC_BCR4 register *******************/
7198 #define FSMC_BCR4_MBKEN_Pos (0U)
7199 #define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
7200 #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
7201 #define FSMC_BCR4_MUXEN_Pos (1U)
7202 #define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
7203 #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7204
7205 #define FSMC_BCR4_MTYP_Pos (2U)
7206 #define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
7207 #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7208 #define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
7209 #define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
7210
7211 #define FSMC_BCR4_MWID_Pos (4U)
7212 #define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
7213 #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7214 #define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
7215 #define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
7216
7217 #define FSMC_BCR4_FACCEN_Pos (6U)
7218 #define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
7219 #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
7220 #define FSMC_BCR4_BURSTEN_Pos (8U)
7221 #define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
7222 #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
7223 #define FSMC_BCR4_WAITPOL_Pos (9U)
7224 #define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
7225 #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
7226 #define FSMC_BCR4_WAITCFG_Pos (11U)
7227 #define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
7228 #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
7229 #define FSMC_BCR4_WREN_Pos (12U)
7230 #define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
7231 #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
7232 #define FSMC_BCR4_WAITEN_Pos (13U)
7233 #define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
7234 #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
7235 #define FSMC_BCR4_EXTMOD_Pos (14U)
7236 #define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
7237 #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
7238 #define FSMC_BCR4_ASYNCWAIT_Pos (15U)
7239 #define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
7240 #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
7241 #define FSMC_BCR4_CPSIZE_Pos (16U)
7242 #define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
7243 #define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
7244 #define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
7245 #define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
7246 #define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
7247 #define FSMC_BCR4_CBURSTRW_Pos (19U)
7248 #define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
7249 #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
7250
7251 /****************** Bit definition for FSMC_BTR1 register ******************/
7252 #define FSMC_BTR1_ADDSET_Pos (0U)
7253 #define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7254 #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7255 #define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7256 #define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7257 #define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7258 #define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
7259
7260 #define FSMC_BTR1_ADDHLD_Pos (4U)
7261 #define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7262 #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7263 #define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
7264 #define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
7265 #define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
7266 #define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
7267
7268 #define FSMC_BTR1_DATAST_Pos (8U)
7269 #define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
7270 #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7271 #define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
7272 #define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
7273 #define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
7274 #define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
7275 #define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
7276 #define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
7277 #define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
7278 #define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
7279
7280 #define FSMC_BTR1_BUSTURN_Pos (16U)
7281 #define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7282 #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7283 #define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
7284 #define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
7285 #define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
7286 #define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
7287
7288 #define FSMC_BTR1_CLKDIV_Pos (20U)
7289 #define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
7290 #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7291 #define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
7292 #define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
7293 #define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
7294 #define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
7295
7296 #define FSMC_BTR1_DATLAT_Pos (24U)
7297 #define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
7298 #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7299 #define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
7300 #define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
7301 #define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
7302 #define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
7303
7304 #define FSMC_BTR1_ACCMOD_Pos (28U)
7305 #define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
7306 #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7307 #define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
7308 #define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
7309
7310 /****************** Bit definition for FSMC_BTR2 register *******************/
7311 #define FSMC_BTR2_ADDSET_Pos (0U)
7312 #define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
7313 #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7314 #define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
7315 #define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
7316 #define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
7317 #define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
7318
7319 #define FSMC_BTR2_ADDHLD_Pos (4U)
7320 #define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7321 #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7322 #define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
7323 #define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
7324 #define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
7325 #define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7326
7327 #define FSMC_BTR2_DATAST_Pos (8U)
7328 #define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
7329 #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7330 #define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
7331 #define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
7332 #define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
7333 #define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
7334 #define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
7335 #define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
7336 #define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
7337 #define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
7338
7339 #define FSMC_BTR2_BUSTURN_Pos (16U)
7340 #define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7341 #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7342 #define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
7343 #define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
7344 #define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
7345 #define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
7346
7347 #define FSMC_BTR2_CLKDIV_Pos (20U)
7348 #define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
7349 #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7350 #define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
7351 #define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
7352 #define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
7353 #define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
7354
7355 #define FSMC_BTR2_DATLAT_Pos (24U)
7356 #define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
7357 #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7358 #define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
7359 #define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
7360 #define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
7361 #define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
7362
7363 #define FSMC_BTR2_ACCMOD_Pos (28U)
7364 #define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
7365 #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7366 #define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
7367 #define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
7368
7369 /******************* Bit definition for FSMC_BTR3 register *******************/
7370 #define FSMC_BTR3_ADDSET_Pos (0U)
7371 #define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7372 #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7373 #define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7374 #define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7375 #define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7376 #define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7377
7378 #define FSMC_BTR3_ADDHLD_Pos (4U)
7379 #define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7380 #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7381 #define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7382 #define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7383 #define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7384 #define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
7385
7386 #define FSMC_BTR3_DATAST_Pos (8U)
7387 #define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
7388 #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7389 #define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
7390 #define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
7391 #define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
7392 #define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
7393 #define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
7394 #define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
7395 #define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
7396 #define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
7397
7398 #define FSMC_BTR3_BUSTURN_Pos (16U)
7399 #define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7400 #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7401 #define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
7402 #define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
7403 #define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
7404 #define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
7405
7406 #define FSMC_BTR3_CLKDIV_Pos (20U)
7407 #define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
7408 #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7409 #define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
7410 #define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
7411 #define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
7412 #define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
7413
7414 #define FSMC_BTR3_DATLAT_Pos (24U)
7415 #define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
7416 #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7417 #define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
7418 #define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
7419 #define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
7420 #define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
7421
7422 #define FSMC_BTR3_ACCMOD_Pos (28U)
7423 #define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
7424 #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7425 #define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
7426 #define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
7427
7428 /****************** Bit definition for FSMC_BTR4 register *******************/
7429 #define FSMC_BTR4_ADDSET_Pos (0U)
7430 #define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
7431 #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7432 #define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
7433 #define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
7434 #define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
7435 #define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7436
7437 #define FSMC_BTR4_ADDHLD_Pos (4U)
7438 #define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7439 #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7440 #define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
7441 #define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
7442 #define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
7443 #define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
7444
7445 #define FSMC_BTR4_DATAST_Pos (8U)
7446 #define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
7447 #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7448 #define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
7449 #define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
7450 #define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
7451 #define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
7452 #define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
7453 #define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
7454 #define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
7455 #define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
7456
7457 #define FSMC_BTR4_BUSTURN_Pos (16U)
7458 #define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7459 #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7460 #define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
7461 #define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
7462 #define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
7463 #define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
7464
7465 #define FSMC_BTR4_CLKDIV_Pos (20U)
7466 #define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
7467 #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7468 #define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
7469 #define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
7470 #define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
7471 #define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
7472
7473 #define FSMC_BTR4_DATLAT_Pos (24U)
7474 #define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
7475 #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7476 #define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
7477 #define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
7478 #define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
7479 #define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
7480
7481 #define FSMC_BTR4_ACCMOD_Pos (28U)
7482 #define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
7483 #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7484 #define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
7485 #define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
7486
7487 /****************** Bit definition for FSMC_BWTR1 register ******************/
7488 #define FSMC_BWTR1_ADDSET_Pos (0U)
7489 #define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
7490 #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7491 #define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
7492 #define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
7493 #define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
7494 #define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
7495
7496 #define FSMC_BWTR1_ADDHLD_Pos (4U)
7497 #define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7498 #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7499 #define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
7500 #define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
7501 #define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
7502 #define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
7503
7504 #define FSMC_BWTR1_DATAST_Pos (8U)
7505 #define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
7506 #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7507 #define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
7508 #define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
7509 #define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
7510 #define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
7511 #define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
7512 #define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
7513 #define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
7514 #define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
7515
7516 #define FSMC_BWTR1_BUSTURN_Pos (16U)
7517 #define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7518 #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7519 #define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
7520 #define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
7521 #define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
7522 #define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
7523
7524 #define FSMC_BWTR1_ACCMOD_Pos (28U)
7525 #define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
7526 #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7527 #define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
7528 #define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
7529
7530 /****************** Bit definition for FSMC_BWTR2 register ******************/
7531 #define FSMC_BWTR2_ADDSET_Pos (0U)
7532 #define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7533 #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7534 #define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7535 #define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7536 #define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7537 #define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7538
7539 #define FSMC_BWTR2_ADDHLD_Pos (4U)
7540 #define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7541 #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7542 #define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
7543 #define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
7544 #define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
7545 #define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
7546
7547 #define FSMC_BWTR2_DATAST_Pos (8U)
7548 #define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
7549 #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7550 #define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
7551 #define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
7552 #define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
7553 #define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
7554 #define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
7555 #define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
7556 #define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
7557 #define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
7558
7559 #define FSMC_BWTR2_BUSTURN_Pos (16U)
7560 #define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7561 #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7562 #define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
7563 #define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
7564 #define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
7565 #define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
7566
7567 #define FSMC_BWTR2_ACCMOD_Pos (28U)
7568 #define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
7569 #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7570 #define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
7571 #define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
7572
7573 /****************** Bit definition for FSMC_BWTR3 register ******************/
7574 #define FSMC_BWTR3_ADDSET_Pos (0U)
7575 #define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
7576 #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7577 #define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
7578 #define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
7579 #define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
7580 #define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7581
7582 #define FSMC_BWTR3_ADDHLD_Pos (4U)
7583 #define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7584 #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7585 #define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
7586 #define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
7587 #define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
7588 #define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
7589
7590 #define FSMC_BWTR3_DATAST_Pos (8U)
7591 #define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
7592 #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7593 #define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
7594 #define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
7595 #define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
7596 #define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
7597 #define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
7598 #define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
7599 #define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
7600 #define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
7601
7602 #define FSMC_BWTR3_BUSTURN_Pos (16U)
7603 #define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7604 #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7605 #define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
7606 #define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
7607 #define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
7608 #define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
7609
7610 #define FSMC_BWTR3_ACCMOD_Pos (28U)
7611 #define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
7612 #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7613 #define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
7614 #define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
7615
7616 /****************** Bit definition for FSMC_BWTR4 register ******************/
7617 #define FSMC_BWTR4_ADDSET_Pos (0U)
7618 #define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
7619 #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7620 #define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
7621 #define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
7622 #define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
7623 #define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
7624
7625 #define FSMC_BWTR4_ADDHLD_Pos (4U)
7626 #define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7627 #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7628 #define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
7629 #define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
7630 #define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
7631 #define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
7632
7633 #define FSMC_BWTR4_DATAST_Pos (8U)
7634 #define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
7635 #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7636 #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
7637 #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
7638 #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
7639 #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
7640 #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
7641 #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
7642 #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
7643 #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
7644
7645 #define FSMC_BWTR4_BUSTURN_Pos (16U)
7646 #define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7647 #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7648 #define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
7649 #define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
7650 #define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
7651 #define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
7652
7653 #define FSMC_BWTR4_ACCMOD_Pos (28U)
7654 #define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
7655 #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7656 #define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
7657 #define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
7658
7659 /******************************************************************************/
7660 /* */
7661 /* General Purpose I/O */
7662 /* */
7663 /******************************************************************************/
7664 /****************** Bits definition for GPIO_MODER register *****************/
7665 #define GPIO_MODER_MODER0_Pos (0U)
7666 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
7667 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
7668 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
7669 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
7670 #define GPIO_MODER_MODER1_Pos (2U)
7671 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
7672 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
7673 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
7674 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
7675 #define GPIO_MODER_MODER2_Pos (4U)
7676 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
7677 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
7678 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
7679 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
7680 #define GPIO_MODER_MODER3_Pos (6U)
7681 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
7682 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
7683 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
7684 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
7685 #define GPIO_MODER_MODER4_Pos (8U)
7686 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
7687 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
7688 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
7689 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
7690 #define GPIO_MODER_MODER5_Pos (10U)
7691 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
7692 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
7693 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
7694 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
7695 #define GPIO_MODER_MODER6_Pos (12U)
7696 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
7697 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
7698 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
7699 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
7700 #define GPIO_MODER_MODER7_Pos (14U)
7701 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
7702 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
7703 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
7704 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
7705 #define GPIO_MODER_MODER8_Pos (16U)
7706 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
7707 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
7708 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
7709 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
7710 #define GPIO_MODER_MODER9_Pos (18U)
7711 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
7712 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
7713 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
7714 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
7715 #define GPIO_MODER_MODER10_Pos (20U)
7716 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
7717 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
7718 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
7719 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
7720 #define GPIO_MODER_MODER11_Pos (22U)
7721 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
7722 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
7723 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
7724 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
7725 #define GPIO_MODER_MODER12_Pos (24U)
7726 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
7727 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
7728 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
7729 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
7730 #define GPIO_MODER_MODER13_Pos (26U)
7731 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
7732 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
7733 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
7734 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
7735 #define GPIO_MODER_MODER14_Pos (28U)
7736 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
7737 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
7738 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
7739 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
7740 #define GPIO_MODER_MODER15_Pos (30U)
7741 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
7742 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
7743 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
7744 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
7745
7746 /****************** Bits definition for GPIO_OTYPER register ****************/
7747 #define GPIO_OTYPER_OT_0 0x00000001U
7748 #define GPIO_OTYPER_OT_1 0x00000002U
7749 #define GPIO_OTYPER_OT_2 0x00000004U
7750 #define GPIO_OTYPER_OT_3 0x00000008U
7751 #define GPIO_OTYPER_OT_4 0x00000010U
7752 #define GPIO_OTYPER_OT_5 0x00000020U
7753 #define GPIO_OTYPER_OT_6 0x00000040U
7754 #define GPIO_OTYPER_OT_7 0x00000080U
7755 #define GPIO_OTYPER_OT_8 0x00000100U
7756 #define GPIO_OTYPER_OT_9 0x00000200U
7757 #define GPIO_OTYPER_OT_10 0x00000400U
7758 #define GPIO_OTYPER_OT_11 0x00000800U
7759 #define GPIO_OTYPER_OT_12 0x00001000U
7760 #define GPIO_OTYPER_OT_13 0x00002000U
7761 #define GPIO_OTYPER_OT_14 0x00004000U
7762 #define GPIO_OTYPER_OT_15 0x00008000U
7763
7764 /****************** Bits definition for GPIO_OSPEEDR register ***************/
7765 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
7766 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
7767 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
7768 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
7769 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
7770
7771 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
7772 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
7773 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
7774 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
7775 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
7776
7777 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
7778 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
7779 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
7780 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
7781 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
7782
7783 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
7784 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
7785 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
7786 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
7787 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
7788
7789 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
7790 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
7791 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
7792 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
7793 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
7794
7795 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
7796 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
7797 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
7798 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
7799 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
7800
7801 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
7802 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
7803 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
7804 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
7805 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
7806
7807 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
7808 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
7809 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
7810 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
7811 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
7812
7813 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
7814 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
7815 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
7816 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
7817 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
7818
7819 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
7820 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
7821 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
7822 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
7823 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
7824
7825 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
7826 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
7827 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
7828 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
7829 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
7830
7831 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
7832 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
7833 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
7834 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
7835 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
7836
7837 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
7838 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
7839 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
7840 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
7841 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
7842
7843 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
7844 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
7845 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
7846 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
7847 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
7848
7849 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
7850 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
7851 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
7852 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
7853 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
7854
7855 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
7856 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
7857 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
7858 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
7859 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
7860
7861 /****************** Bits definition for GPIO_PUPDR register *****************/
7862 #define GPIO_PUPDR_PUPDR0_Pos (0U)
7863 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
7864 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
7865 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
7866 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
7867
7868 #define GPIO_PUPDR_PUPDR1_Pos (2U)
7869 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
7870 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
7871 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
7872 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
7873
7874 #define GPIO_PUPDR_PUPDR2_Pos (4U)
7875 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
7876 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
7877 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
7878 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
7879
7880 #define GPIO_PUPDR_PUPDR3_Pos (6U)
7881 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
7882 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
7883 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
7884 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
7885
7886 #define GPIO_PUPDR_PUPDR4_Pos (8U)
7887 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
7888 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
7889 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
7890 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
7891
7892 #define GPIO_PUPDR_PUPDR5_Pos (10U)
7893 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
7894 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
7895 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
7896 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
7897
7898 #define GPIO_PUPDR_PUPDR6_Pos (12U)
7899 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
7900 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
7901 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
7902 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
7903
7904 #define GPIO_PUPDR_PUPDR7_Pos (14U)
7905 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
7906 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
7907 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
7908 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
7909
7910 #define GPIO_PUPDR_PUPDR8_Pos (16U)
7911 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
7912 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
7913 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
7914 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
7915
7916 #define GPIO_PUPDR_PUPDR9_Pos (18U)
7917 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
7918 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
7919 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
7920 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
7921
7922 #define GPIO_PUPDR_PUPDR10_Pos (20U)
7923 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
7924 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
7925 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
7926 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
7927
7928 #define GPIO_PUPDR_PUPDR11_Pos (22U)
7929 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
7930 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
7931 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
7932 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
7933
7934 #define GPIO_PUPDR_PUPDR12_Pos (24U)
7935 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
7936 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
7937 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
7938 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
7939
7940 #define GPIO_PUPDR_PUPDR13_Pos (26U)
7941 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
7942 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
7943 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
7944 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
7945
7946 #define GPIO_PUPDR_PUPDR14_Pos (28U)
7947 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
7948 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
7949 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
7950 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
7951
7952 #define GPIO_PUPDR_PUPDR15_Pos (30U)
7953 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
7954 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
7955 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
7956 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
7957
7958 /****************** Bits definition for GPIO_IDR register *******************/
7959 #define GPIO_IDR_IDR_0 0x00000001U
7960 #define GPIO_IDR_IDR_1 0x00000002U
7961 #define GPIO_IDR_IDR_2 0x00000004U
7962 #define GPIO_IDR_IDR_3 0x00000008U
7963 #define GPIO_IDR_IDR_4 0x00000010U
7964 #define GPIO_IDR_IDR_5 0x00000020U
7965 #define GPIO_IDR_IDR_6 0x00000040U
7966 #define GPIO_IDR_IDR_7 0x00000080U
7967 #define GPIO_IDR_IDR_8 0x00000100U
7968 #define GPIO_IDR_IDR_9 0x00000200U
7969 #define GPIO_IDR_IDR_10 0x00000400U
7970 #define GPIO_IDR_IDR_11 0x00000800U
7971 #define GPIO_IDR_IDR_12 0x00001000U
7972 #define GPIO_IDR_IDR_13 0x00002000U
7973 #define GPIO_IDR_IDR_14 0x00004000U
7974 #define GPIO_IDR_IDR_15 0x00008000U
7975
7976 /****************** Bits definition for GPIO_ODR register *******************/
7977 #define GPIO_ODR_ODR_0 0x00000001U
7978 #define GPIO_ODR_ODR_1 0x00000002U
7979 #define GPIO_ODR_ODR_2 0x00000004U
7980 #define GPIO_ODR_ODR_3 0x00000008U
7981 #define GPIO_ODR_ODR_4 0x00000010U
7982 #define GPIO_ODR_ODR_5 0x00000020U
7983 #define GPIO_ODR_ODR_6 0x00000040U
7984 #define GPIO_ODR_ODR_7 0x00000080U
7985 #define GPIO_ODR_ODR_8 0x00000100U
7986 #define GPIO_ODR_ODR_9 0x00000200U
7987 #define GPIO_ODR_ODR_10 0x00000400U
7988 #define GPIO_ODR_ODR_11 0x00000800U
7989 #define GPIO_ODR_ODR_12 0x00001000U
7990 #define GPIO_ODR_ODR_13 0x00002000U
7991 #define GPIO_ODR_ODR_14 0x00004000U
7992 #define GPIO_ODR_ODR_15 0x00008000U
7993
7994 /****************** Bits definition for GPIO_BSRR register ******************/
7995 #define GPIO_BSRR_BS_0 0x00000001U
7996 #define GPIO_BSRR_BS_1 0x00000002U
7997 #define GPIO_BSRR_BS_2 0x00000004U
7998 #define GPIO_BSRR_BS_3 0x00000008U
7999 #define GPIO_BSRR_BS_4 0x00000010U
8000 #define GPIO_BSRR_BS_5 0x00000020U
8001 #define GPIO_BSRR_BS_6 0x00000040U
8002 #define GPIO_BSRR_BS_7 0x00000080U
8003 #define GPIO_BSRR_BS_8 0x00000100U
8004 #define GPIO_BSRR_BS_9 0x00000200U
8005 #define GPIO_BSRR_BS_10 0x00000400U
8006 #define GPIO_BSRR_BS_11 0x00000800U
8007 #define GPIO_BSRR_BS_12 0x00001000U
8008 #define GPIO_BSRR_BS_13 0x00002000U
8009 #define GPIO_BSRR_BS_14 0x00004000U
8010 #define GPIO_BSRR_BS_15 0x00008000U
8011 #define GPIO_BSRR_BR_0 0x00010000U
8012 #define GPIO_BSRR_BR_1 0x00020000U
8013 #define GPIO_BSRR_BR_2 0x00040000U
8014 #define GPIO_BSRR_BR_3 0x00080000U
8015 #define GPIO_BSRR_BR_4 0x00100000U
8016 #define GPIO_BSRR_BR_5 0x00200000U
8017 #define GPIO_BSRR_BR_6 0x00400000U
8018 #define GPIO_BSRR_BR_7 0x00800000U
8019 #define GPIO_BSRR_BR_8 0x01000000U
8020 #define GPIO_BSRR_BR_9 0x02000000U
8021 #define GPIO_BSRR_BR_10 0x04000000U
8022 #define GPIO_BSRR_BR_11 0x08000000U
8023 #define GPIO_BSRR_BR_12 0x10000000U
8024 #define GPIO_BSRR_BR_13 0x20000000U
8025 #define GPIO_BSRR_BR_14 0x40000000U
8026 #define GPIO_BSRR_BR_15 0x80000000U
8027 /****************** Bit definition for GPIO_LCKR register *********************/
8028 #define GPIO_LCKR_LCK0_Pos (0U)
8029 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
8030 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8031 #define GPIO_LCKR_LCK1_Pos (1U)
8032 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
8033 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8034 #define GPIO_LCKR_LCK2_Pos (2U)
8035 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
8036 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8037 #define GPIO_LCKR_LCK3_Pos (3U)
8038 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
8039 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8040 #define GPIO_LCKR_LCK4_Pos (4U)
8041 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
8042 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8043 #define GPIO_LCKR_LCK5_Pos (5U)
8044 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
8045 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8046 #define GPIO_LCKR_LCK6_Pos (6U)
8047 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
8048 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8049 #define GPIO_LCKR_LCK7_Pos (7U)
8050 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
8051 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8052 #define GPIO_LCKR_LCK8_Pos (8U)
8053 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
8054 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8055 #define GPIO_LCKR_LCK9_Pos (9U)
8056 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
8057 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8058 #define GPIO_LCKR_LCK10_Pos (10U)
8059 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
8060 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8061 #define GPIO_LCKR_LCK11_Pos (11U)
8062 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
8063 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8064 #define GPIO_LCKR_LCK12_Pos (12U)
8065 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
8066 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8067 #define GPIO_LCKR_LCK13_Pos (13U)
8068 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
8069 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8070 #define GPIO_LCKR_LCK14_Pos (14U)
8071 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
8072 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8073 #define GPIO_LCKR_LCK15_Pos (15U)
8074 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
8075 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8076 #define GPIO_LCKR_LCKK_Pos (16U)
8077 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
8078 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8079 /****************** Bit definition for GPIO_AFRL register *********************/
8080 #define GPIO_AFRL_AFSEL0_Pos (0U)
8081 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
8082 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8083 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
8084 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
8085 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
8086 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
8087 #define GPIO_AFRL_AFSEL1_Pos (4U)
8088 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
8089 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8090 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
8091 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
8092 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
8093 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
8094 #define GPIO_AFRL_AFSEL2_Pos (8U)
8095 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
8096 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8097 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
8098 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
8099 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
8100 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
8101 #define GPIO_AFRL_AFSEL3_Pos (12U)
8102 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
8103 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8104 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
8105 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
8106 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
8107 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
8108 #define GPIO_AFRL_AFSEL4_Pos (16U)
8109 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
8110 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8111 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
8112 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
8113 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
8114 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
8115 #define GPIO_AFRL_AFSEL5_Pos (20U)
8116 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
8117 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8118 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
8119 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
8120 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
8121 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
8122 #define GPIO_AFRL_AFSEL6_Pos (24U)
8123 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
8124 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8125 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
8126 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
8127 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
8128 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
8129 #define GPIO_AFRL_AFSEL7_Pos (28U)
8130 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
8131 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8132 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
8133 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
8134 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
8135 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
8136
8137 /* Legacy defines */
8138 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8139 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8140 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8141 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8142 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8143 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8144 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8145 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8146 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8147 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8148 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8149 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8150 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8151 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8152 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8153 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8154 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8155 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8156 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8157 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8158 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8159 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8160 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8161 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8162 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8163 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8164 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8165 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8166 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8167 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8168 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8169 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8170 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8171 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8172 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8173 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8174 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
8175 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
8176 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
8177 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
8178
8179 /****************** Bit definition for GPIO_AFRH register *********************/
8180 #define GPIO_AFRH_AFSEL8_Pos (0U)
8181 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
8182 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8183 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
8184 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
8185 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
8186 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
8187 #define GPIO_AFRH_AFSEL9_Pos (4U)
8188 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
8189 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8190 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
8191 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
8192 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
8193 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
8194 #define GPIO_AFRH_AFSEL10_Pos (8U)
8195 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
8196 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8197 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
8198 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
8199 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
8200 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
8201 #define GPIO_AFRH_AFSEL11_Pos (12U)
8202 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
8203 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8204 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
8205 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
8206 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
8207 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
8208 #define GPIO_AFRH_AFSEL12_Pos (16U)
8209 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
8210 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8211 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
8212 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
8213 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
8214 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
8215 #define GPIO_AFRH_AFSEL13_Pos (20U)
8216 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
8217 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
8218 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
8219 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
8220 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
8221 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
8222 #define GPIO_AFRH_AFSEL14_Pos (24U)
8223 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
8224 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
8225 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
8226 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
8227 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
8228 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
8229 #define GPIO_AFRH_AFSEL15_Pos (28U)
8230 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
8231 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8232 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
8233 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
8234 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
8235 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
8236
8237 /* Legacy defines */
8238 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8239 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
8240 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
8241 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
8242 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
8243 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8244 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
8245 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
8246 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
8247 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
8248 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8249 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
8250 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
8251 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
8252 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
8253 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8254 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
8255 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
8256 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
8257 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
8258 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8259 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
8260 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
8261 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
8262 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
8263 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8264 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
8265 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
8266 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
8267 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
8268 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8269 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
8270 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
8271 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
8272 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
8273 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8274 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
8275 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
8276 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
8277 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
8278
8279 /****************** Bits definition for GPIO_BRR register ******************/
8280 #define GPIO_BRR_BR0_Pos (0U)
8281 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
8282 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
8283 #define GPIO_BRR_BR1_Pos (1U)
8284 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
8285 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
8286 #define GPIO_BRR_BR2_Pos (2U)
8287 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
8288 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
8289 #define GPIO_BRR_BR3_Pos (3U)
8290 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
8291 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
8292 #define GPIO_BRR_BR4_Pos (4U)
8293 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
8294 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
8295 #define GPIO_BRR_BR5_Pos (5U)
8296 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
8297 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
8298 #define GPIO_BRR_BR6_Pos (6U)
8299 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
8300 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
8301 #define GPIO_BRR_BR7_Pos (7U)
8302 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
8303 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
8304 #define GPIO_BRR_BR8_Pos (8U)
8305 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
8306 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
8307 #define GPIO_BRR_BR9_Pos (9U)
8308 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
8309 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
8310 #define GPIO_BRR_BR10_Pos (10U)
8311 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
8312 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
8313 #define GPIO_BRR_BR11_Pos (11U)
8314 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
8315 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
8316 #define GPIO_BRR_BR12_Pos (12U)
8317 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
8318 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
8319 #define GPIO_BRR_BR13_Pos (13U)
8320 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
8321 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
8322 #define GPIO_BRR_BR14_Pos (14U)
8323 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
8324 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
8325 #define GPIO_BRR_BR15_Pos (15U)
8326 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
8327 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
8328
8329
8330 /******************************************************************************/
8331 /* */
8332 /* Inter-integrated Circuit Interface */
8333 /* */
8334 /******************************************************************************/
8335 /******************* Bit definition for I2C_CR1 register ********************/
8336 #define I2C_CR1_PE_Pos (0U)
8337 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
8338 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
8339 #define I2C_CR1_SMBUS_Pos (1U)
8340 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
8341 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
8342 #define I2C_CR1_SMBTYPE_Pos (3U)
8343 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
8344 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
8345 #define I2C_CR1_ENARP_Pos (4U)
8346 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
8347 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
8348 #define I2C_CR1_ENPEC_Pos (5U)
8349 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
8350 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
8351 #define I2C_CR1_ENGC_Pos (6U)
8352 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
8353 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
8354 #define I2C_CR1_NOSTRETCH_Pos (7U)
8355 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
8356 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
8357 #define I2C_CR1_START_Pos (8U)
8358 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
8359 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
8360 #define I2C_CR1_STOP_Pos (9U)
8361 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
8362 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
8363 #define I2C_CR1_ACK_Pos (10U)
8364 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
8365 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
8366 #define I2C_CR1_POS_Pos (11U)
8367 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
8368 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
8369 #define I2C_CR1_PEC_Pos (12U)
8370 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
8371 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
8372 #define I2C_CR1_ALERT_Pos (13U)
8373 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
8374 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
8375 #define I2C_CR1_SWRST_Pos (15U)
8376 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
8377 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
8378
8379 /******************* Bit definition for I2C_CR2 register ********************/
8380 #define I2C_CR2_FREQ_Pos (0U)
8381 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
8382 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
8383 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
8384 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
8385 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
8386 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
8387 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
8388 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
8389
8390 #define I2C_CR2_ITERREN_Pos (8U)
8391 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
8392 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
8393 #define I2C_CR2_ITEVTEN_Pos (9U)
8394 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
8395 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
8396 #define I2C_CR2_ITBUFEN_Pos (10U)
8397 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
8398 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
8399 #define I2C_CR2_DMAEN_Pos (11U)
8400 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
8401 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
8402 #define I2C_CR2_LAST_Pos (12U)
8403 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
8404 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
8405
8406 /******************* Bit definition for I2C_OAR1 register *******************/
8407 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
8408 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
8409
8410 #define I2C_OAR1_ADD0_Pos (0U)
8411 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
8412 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
8413 #define I2C_OAR1_ADD1_Pos (1U)
8414 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
8415 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
8416 #define I2C_OAR1_ADD2_Pos (2U)
8417 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
8418 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
8419 #define I2C_OAR1_ADD3_Pos (3U)
8420 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
8421 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
8422 #define I2C_OAR1_ADD4_Pos (4U)
8423 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
8424 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
8425 #define I2C_OAR1_ADD5_Pos (5U)
8426 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
8427 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
8428 #define I2C_OAR1_ADD6_Pos (6U)
8429 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
8430 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
8431 #define I2C_OAR1_ADD7_Pos (7U)
8432 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
8433 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
8434 #define I2C_OAR1_ADD8_Pos (8U)
8435 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
8436 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
8437 #define I2C_OAR1_ADD9_Pos (9U)
8438 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
8439 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
8440
8441 #define I2C_OAR1_ADDMODE_Pos (15U)
8442 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
8443 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
8444
8445 /******************* Bit definition for I2C_OAR2 register *******************/
8446 #define I2C_OAR2_ENDUAL_Pos (0U)
8447 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
8448 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
8449 #define I2C_OAR2_ADD2_Pos (1U)
8450 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
8451 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
8452
8453 /******************** Bit definition for I2C_DR register ********************/
8454 #define I2C_DR_DR_Pos (0U)
8455 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
8456 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
8457
8458 /******************* Bit definition for I2C_SR1 register ********************/
8459 #define I2C_SR1_SB_Pos (0U)
8460 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
8461 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
8462 #define I2C_SR1_ADDR_Pos (1U)
8463 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
8464 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
8465 #define I2C_SR1_BTF_Pos (2U)
8466 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
8467 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
8468 #define I2C_SR1_ADD10_Pos (3U)
8469 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
8470 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
8471 #define I2C_SR1_STOPF_Pos (4U)
8472 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
8473 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
8474 #define I2C_SR1_RXNE_Pos (6U)
8475 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
8476 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
8477 #define I2C_SR1_TXE_Pos (7U)
8478 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
8479 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
8480 #define I2C_SR1_BERR_Pos (8U)
8481 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
8482 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
8483 #define I2C_SR1_ARLO_Pos (9U)
8484 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
8485 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
8486 #define I2C_SR1_AF_Pos (10U)
8487 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
8488 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
8489 #define I2C_SR1_OVR_Pos (11U)
8490 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
8491 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
8492 #define I2C_SR1_PECERR_Pos (12U)
8493 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
8494 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
8495 #define I2C_SR1_TIMEOUT_Pos (14U)
8496 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
8497 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
8498 #define I2C_SR1_SMBALERT_Pos (15U)
8499 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
8500 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
8501
8502 /******************* Bit definition for I2C_SR2 register ********************/
8503 #define I2C_SR2_MSL_Pos (0U)
8504 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
8505 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
8506 #define I2C_SR2_BUSY_Pos (1U)
8507 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
8508 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
8509 #define I2C_SR2_TRA_Pos (2U)
8510 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
8511 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
8512 #define I2C_SR2_GENCALL_Pos (4U)
8513 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
8514 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
8515 #define I2C_SR2_SMBDEFAULT_Pos (5U)
8516 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
8517 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
8518 #define I2C_SR2_SMBHOST_Pos (6U)
8519 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
8520 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
8521 #define I2C_SR2_DUALF_Pos (7U)
8522 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
8523 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
8524 #define I2C_SR2_PEC_Pos (8U)
8525 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
8526 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
8527
8528 /******************* Bit definition for I2C_CCR register ********************/
8529 #define I2C_CCR_CCR_Pos (0U)
8530 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
8531 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
8532 #define I2C_CCR_DUTY_Pos (14U)
8533 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
8534 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
8535 #define I2C_CCR_FS_Pos (15U)
8536 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
8537 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
8538
8539 /****************** Bit definition for I2C_TRISE register *******************/
8540 #define I2C_TRISE_TRISE_Pos (0U)
8541 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
8542 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
8543
8544 /****************** Bit definition for I2C_FLTR register *******************/
8545 #define I2C_FLTR_DNF_Pos (0U)
8546 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
8547 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
8548 #define I2C_FLTR_ANOFF_Pos (4U)
8549 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
8550 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
8551
8552 /******************************************************************************/
8553 /* */
8554 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
8555 /* */
8556 /******************************************************************************/
8557 /******************* Bit definition for I2C_CR1 register *******************/
8558 #define FMPI2C_CR1_PE_Pos (0U)
8559 #define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
8560 #define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
8561 #define FMPI2C_CR1_TXIE_Pos (1U)
8562 #define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
8563 #define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
8564 #define FMPI2C_CR1_RXIE_Pos (2U)
8565 #define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
8566 #define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
8567 #define FMPI2C_CR1_ADDRIE_Pos (3U)
8568 #define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
8569 #define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
8570 #define FMPI2C_CR1_NACKIE_Pos (4U)
8571 #define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
8572 #define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
8573 #define FMPI2C_CR1_STOPIE_Pos (5U)
8574 #define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
8575 #define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
8576 #define FMPI2C_CR1_TCIE_Pos (6U)
8577 #define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
8578 #define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
8579 #define FMPI2C_CR1_ERRIE_Pos (7U)
8580 #define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
8581 #define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
8582 #define FMPI2C_CR1_DFN_Pos (8U)
8583 #define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
8584 #define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
8585 #define FMPI2C_CR1_ANFOFF_Pos (12U)
8586 #define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
8587 #define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
8588 #define FMPI2C_CR1_TXDMAEN_Pos (14U)
8589 #define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
8590 #define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
8591 #define FMPI2C_CR1_RXDMAEN_Pos (15U)
8592 #define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
8593 #define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
8594 #define FMPI2C_CR1_SBC_Pos (16U)
8595 #define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
8596 #define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
8597 #define FMPI2C_CR1_NOSTRETCH_Pos (17U)
8598 #define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
8599 #define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
8600 #define FMPI2C_CR1_GCEN_Pos (19U)
8601 #define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
8602 #define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
8603 #define FMPI2C_CR1_SMBHEN_Pos (20U)
8604 #define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
8605 #define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
8606 #define FMPI2C_CR1_SMBDEN_Pos (21U)
8607 #define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
8608 #define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
8609 #define FMPI2C_CR1_ALERTEN_Pos (22U)
8610 #define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
8611 #define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
8612 #define FMPI2C_CR1_PECEN_Pos (23U)
8613 #define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
8614 #define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
8615
8616 /****************** Bit definition for I2C_CR2 register ********************/
8617 #define FMPI2C_CR2_SADD_Pos (0U)
8618 #define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
8619 #define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
8620 #define FMPI2C_CR2_RD_WRN_Pos (10U)
8621 #define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
8622 #define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
8623 #define FMPI2C_CR2_ADD10_Pos (11U)
8624 #define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
8625 #define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
8626 #define FMPI2C_CR2_HEAD10R_Pos (12U)
8627 #define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
8628 #define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
8629 #define FMPI2C_CR2_START_Pos (13U)
8630 #define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
8631 #define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
8632 #define FMPI2C_CR2_STOP_Pos (14U)
8633 #define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
8634 #define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
8635 #define FMPI2C_CR2_NACK_Pos (15U)
8636 #define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
8637 #define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
8638 #define FMPI2C_CR2_NBYTES_Pos (16U)
8639 #define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
8640 #define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
8641 #define FMPI2C_CR2_RELOAD_Pos (24U)
8642 #define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
8643 #define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
8644 #define FMPI2C_CR2_AUTOEND_Pos (25U)
8645 #define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
8646 #define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
8647 #define FMPI2C_CR2_PECBYTE_Pos (26U)
8648 #define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
8649 #define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
8650
8651 /******************* Bit definition for I2C_OAR1 register ******************/
8652 #define FMPI2C_OAR1_OA1_Pos (0U)
8653 #define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
8654 #define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
8655 #define FMPI2C_OAR1_OA1MODE_Pos (10U)
8656 #define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
8657 #define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
8658 #define FMPI2C_OAR1_OA1EN_Pos (15U)
8659 #define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
8660 #define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
8661
8662 /******************* Bit definition for I2C_OAR2 register ******************/
8663 #define FMPI2C_OAR2_OA2_Pos (1U)
8664 #define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
8665 #define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
8666 #define FMPI2C_OAR2_OA2MSK_Pos (8U)
8667 #define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
8668 #define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
8669 #define FMPI2C_OAR2_OA2EN_Pos (15U)
8670 #define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
8671 #define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
8672
8673 /******************* Bit definition for I2C_TIMINGR register *******************/
8674 #define FMPI2C_TIMINGR_SCLL_Pos (0U)
8675 #define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
8676 #define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
8677 #define FMPI2C_TIMINGR_SCLH_Pos (8U)
8678 #define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
8679 #define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
8680 #define FMPI2C_TIMINGR_SDADEL_Pos (16U)
8681 #define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
8682 #define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
8683 #define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
8684 #define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
8685 #define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
8686 #define FMPI2C_TIMINGR_PRESC_Pos (28U)
8687 #define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
8688 #define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
8689
8690 /******************* Bit definition for I2C_TIMEOUTR register *******************/
8691 #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
8692 #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
8693 #define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
8694 #define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
8695 #define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
8696 #define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
8697 #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
8698 #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
8699 #define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
8700 #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
8701 #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
8702 #define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
8703 #define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
8704 #define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
8705 #define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
8706
8707 /****************** Bit definition for I2C_ISR register *********************/
8708 #define FMPI2C_ISR_TXE_Pos (0U)
8709 #define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
8710 #define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
8711 #define FMPI2C_ISR_TXIS_Pos (1U)
8712 #define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
8713 #define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
8714 #define FMPI2C_ISR_RXNE_Pos (2U)
8715 #define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
8716 #define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
8717 #define FMPI2C_ISR_ADDR_Pos (3U)
8718 #define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
8719 #define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
8720 #define FMPI2C_ISR_NACKF_Pos (4U)
8721 #define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
8722 #define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
8723 #define FMPI2C_ISR_STOPF_Pos (5U)
8724 #define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
8725 #define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
8726 #define FMPI2C_ISR_TC_Pos (6U)
8727 #define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
8728 #define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
8729 #define FMPI2C_ISR_TCR_Pos (7U)
8730 #define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
8731 #define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
8732 #define FMPI2C_ISR_BERR_Pos (8U)
8733 #define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
8734 #define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
8735 #define FMPI2C_ISR_ARLO_Pos (9U)
8736 #define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
8737 #define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
8738 #define FMPI2C_ISR_OVR_Pos (10U)
8739 #define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
8740 #define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
8741 #define FMPI2C_ISR_PECERR_Pos (11U)
8742 #define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
8743 #define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
8744 #define FMPI2C_ISR_TIMEOUT_Pos (12U)
8745 #define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
8746 #define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
8747 #define FMPI2C_ISR_ALERT_Pos (13U)
8748 #define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
8749 #define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
8750 #define FMPI2C_ISR_BUSY_Pos (15U)
8751 #define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
8752 #define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
8753 #define FMPI2C_ISR_DIR_Pos (16U)
8754 #define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
8755 #define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
8756 #define FMPI2C_ISR_ADDCODE_Pos (17U)
8757 #define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
8758 #define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
8759
8760 /****************** Bit definition for I2C_ICR register *********************/
8761 #define FMPI2C_ICR_ADDRCF_Pos (3U)
8762 #define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
8763 #define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
8764 #define FMPI2C_ICR_NACKCF_Pos (4U)
8765 #define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
8766 #define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
8767 #define FMPI2C_ICR_STOPCF_Pos (5U)
8768 #define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
8769 #define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
8770 #define FMPI2C_ICR_BERRCF_Pos (8U)
8771 #define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
8772 #define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
8773 #define FMPI2C_ICR_ARLOCF_Pos (9U)
8774 #define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
8775 #define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
8776 #define FMPI2C_ICR_OVRCF_Pos (10U)
8777 #define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
8778 #define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
8779 #define FMPI2C_ICR_PECCF_Pos (11U)
8780 #define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
8781 #define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
8782 #define FMPI2C_ICR_TIMOUTCF_Pos (12U)
8783 #define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
8784 #define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
8785 #define FMPI2C_ICR_ALERTCF_Pos (13U)
8786 #define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
8787 #define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
8788
8789 /****************** Bit definition for I2C_PECR register *********************/
8790 #define FMPI2C_PECR_PEC_Pos (0U)
8791 #define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
8792 #define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
8793
8794 /****************** Bit definition for I2C_RXDR register *********************/
8795 #define FMPI2C_RXDR_RXDATA_Pos (0U)
8796 #define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
8797 #define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
8798
8799 /****************** Bit definition for I2C_TXDR register *********************/
8800 #define FMPI2C_TXDR_TXDATA_Pos (0U)
8801 #define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
8802 #define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
8803
8804
8805
8806 /******************************************************************************/
8807 /* */
8808 /* Independent WATCHDOG */
8809 /* */
8810 /******************************************************************************/
8811 /******************* Bit definition for IWDG_KR register ********************/
8812 #define IWDG_KR_KEY_Pos (0U)
8813 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
8814 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
8815
8816 /******************* Bit definition for IWDG_PR register ********************/
8817 #define IWDG_PR_PR_Pos (0U)
8818 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
8819 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
8820 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
8821 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
8822 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
8823
8824 /******************* Bit definition for IWDG_RLR register *******************/
8825 #define IWDG_RLR_RL_Pos (0U)
8826 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
8827 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
8828
8829 /******************* Bit definition for IWDG_SR register ********************/
8830 #define IWDG_SR_PVU_Pos (0U)
8831 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
8832 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
8833 #define IWDG_SR_RVU_Pos (1U)
8834 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
8835 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
8836
8837
8838
8839 /******************************************************************************/
8840 /* */
8841 /* Power Control */
8842 /* */
8843 /******************************************************************************/
8844 /******************** Bit definition for PWR_CR register ********************/
8845 #define PWR_CR_LPDS_Pos (0U)
8846 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
8847 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
8848 #define PWR_CR_PDDS_Pos (1U)
8849 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
8850 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
8851 #define PWR_CR_CWUF_Pos (2U)
8852 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
8853 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
8854 #define PWR_CR_CSBF_Pos (3U)
8855 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
8856 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
8857 #define PWR_CR_PVDE_Pos (4U)
8858 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
8859 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
8860
8861 #define PWR_CR_PLS_Pos (5U)
8862 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
8863 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
8864 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
8865 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
8866 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
8867
8868 /*!< PVD level configuration */
8869 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
8870 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
8871 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
8872 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
8873 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
8874 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
8875 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
8876 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
8877 #define PWR_CR_DBP_Pos (8U)
8878 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
8879 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
8880 #define PWR_CR_FPDS_Pos (9U)
8881 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
8882 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
8883 #define PWR_CR_LPLVDS_Pos (10U)
8884 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
8885 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
8886 #define PWR_CR_MRLVDS_Pos (11U)
8887 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
8888 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
8889 #define PWR_CR_ADCDC1_Pos (13U)
8890 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
8891 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
8892 #define PWR_CR_VOS_Pos (14U)
8893 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
8894 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
8895 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
8896 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
8897 #define PWR_CR_FMSSR_Pos (20U)
8898 #define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
8899 #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
8900 #define PWR_CR_FISSR_Pos (21U)
8901 #define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
8902 #define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
8903
8904
8905 /******************* Bit definition for PWR_CSR register ********************/
8906 #define PWR_CSR_WUF_Pos (0U)
8907 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
8908 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
8909 #define PWR_CSR_SBF_Pos (1U)
8910 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
8911 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
8912 #define PWR_CSR_PVDO_Pos (2U)
8913 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
8914 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
8915 #define PWR_CSR_BRR_Pos (3U)
8916 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
8917 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
8918 #define PWR_CSR_EWUP3_Pos (6U)
8919 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
8920 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
8921 #define PWR_CSR_EWUP2_Pos (7U)
8922 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
8923 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
8924 #define PWR_CSR_EWUP1_Pos (8U)
8925 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
8926 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
8927 #define PWR_CSR_BRE_Pos (9U)
8928 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
8929 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
8930 #define PWR_CSR_VOSRDY_Pos (14U)
8931 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
8932 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
8933
8934
8935 /******************************************************************************/
8936 /* */
8937 /* QUADSPI */
8938 /* */
8939 /******************************************************************************/
8940 /***************** Bit definition for QUADSPI_CR register *******************/
8941 #define QUADSPI_CR_EN_Pos (0U)
8942 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
8943 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
8944 #define QUADSPI_CR_ABORT_Pos (1U)
8945 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
8946 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
8947 #define QUADSPI_CR_DMAEN_Pos (2U)
8948 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
8949 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
8950 #define QUADSPI_CR_TCEN_Pos (3U)
8951 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
8952 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
8953 #define QUADSPI_CR_SSHIFT_Pos (4U)
8954 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
8955 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
8956 #define QUADSPI_CR_DFM_Pos (6U)
8957 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
8958 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
8959 #define QUADSPI_CR_FSEL_Pos (7U)
8960 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
8961 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
8962 #define QUADSPI_CR_FTHRES_Pos (8U)
8963 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
8964 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
8965 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
8966 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
8967 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
8968 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
8969 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
8970 #define QUADSPI_CR_TEIE_Pos (16U)
8971 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
8972 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
8973 #define QUADSPI_CR_TCIE_Pos (17U)
8974 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
8975 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
8976 #define QUADSPI_CR_FTIE_Pos (18U)
8977 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
8978 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
8979 #define QUADSPI_CR_SMIE_Pos (19U)
8980 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
8981 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
8982 #define QUADSPI_CR_TOIE_Pos (20U)
8983 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
8984 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
8985 #define QUADSPI_CR_APMS_Pos (22U)
8986 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
8987 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
8988 #define QUADSPI_CR_PMM_Pos (23U)
8989 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
8990 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
8991 #define QUADSPI_CR_PRESCALER_Pos (24U)
8992 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
8993 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
8994 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
8995 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
8996 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
8997 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
8998 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
8999 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
9000 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
9001 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
9002
9003 /***************** Bit definition for QUADSPI_DCR register ******************/
9004 #define QUADSPI_DCR_CKMODE_Pos (0U)
9005 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
9006 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
9007 #define QUADSPI_DCR_CSHT_Pos (8U)
9008 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
9009 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
9010 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
9011 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
9012 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
9013 #define QUADSPI_DCR_FSIZE_Pos (16U)
9014 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
9015 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
9016 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
9017 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
9018 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
9019 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
9020 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
9021
9022 /****************** Bit definition for QUADSPI_SR register *******************/
9023 #define QUADSPI_SR_TEF_Pos (0U)
9024 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
9025 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
9026 #define QUADSPI_SR_TCF_Pos (1U)
9027 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
9028 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
9029 #define QUADSPI_SR_FTF_Pos (2U)
9030 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
9031 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
9032 #define QUADSPI_SR_SMF_Pos (3U)
9033 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
9034 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
9035 #define QUADSPI_SR_TOF_Pos (4U)
9036 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
9037 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
9038 #define QUADSPI_SR_BUSY_Pos (5U)
9039 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
9040 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
9041 #define QUADSPI_SR_FLEVEL_Pos (8U)
9042 #define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
9043 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
9044 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
9045 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
9046 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
9047 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
9048 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
9049 #define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
9050
9051 /****************** Bit definition for QUADSPI_FCR register ******************/
9052 #define QUADSPI_FCR_CTEF_Pos (0U)
9053 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
9054 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
9055 #define QUADSPI_FCR_CTCF_Pos (1U)
9056 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
9057 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
9058 #define QUADSPI_FCR_CSMF_Pos (3U)
9059 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
9060 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
9061 #define QUADSPI_FCR_CTOF_Pos (4U)
9062 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
9063 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
9064
9065 /****************** Bit definition for QUADSPI_DLR register ******************/
9066 #define QUADSPI_DLR_DL_Pos (0U)
9067 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
9068 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
9069
9070 /****************** Bit definition for QUADSPI_CCR register ******************/
9071 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
9072 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
9073 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
9074 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
9075 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
9076 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
9077 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
9078 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
9079 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
9080 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
9081 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
9082 #define QUADSPI_CCR_IMODE_Pos (8U)
9083 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
9084 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
9085 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
9086 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
9087 #define QUADSPI_CCR_ADMODE_Pos (10U)
9088 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
9089 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
9090 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
9091 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
9092 #define QUADSPI_CCR_ADSIZE_Pos (12U)
9093 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
9094 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
9095 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
9096 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
9097 #define QUADSPI_CCR_ABMODE_Pos (14U)
9098 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
9099 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
9100 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
9101 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
9102 #define QUADSPI_CCR_ABSIZE_Pos (16U)
9103 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
9104 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
9105 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
9106 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
9107 #define QUADSPI_CCR_DCYC_Pos (18U)
9108 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9109 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
9110 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9111 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9112 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9113 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9114 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
9115 #define QUADSPI_CCR_DMODE_Pos (24U)
9116 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
9117 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
9118 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
9119 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
9120 #define QUADSPI_CCR_FMODE_Pos (26U)
9121 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
9122 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
9123 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
9124 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
9125 #define QUADSPI_CCR_SIOO_Pos (28U)
9126 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
9127 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
9128 #define QUADSPI_CCR_DHHC_Pos (30U)
9129 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
9130 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
9131 #define QUADSPI_CCR_DDRM_Pos (31U)
9132 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
9133 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
9134 /****************** Bit definition for QUADSPI_AR register *******************/
9135 #define QUADSPI_AR_ADDRESS_Pos (0U)
9136 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
9137 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
9138
9139 /****************** Bit definition for QUADSPI_ABR register ******************/
9140 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
9141 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
9142 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
9143
9144 /****************** Bit definition for QUADSPI_DR register *******************/
9145 #define QUADSPI_DR_DATA_Pos (0U)
9146 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
9147 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
9148
9149 /****************** Bit definition for QUADSPI_PSMKR register ****************/
9150 #define QUADSPI_PSMKR_MASK_Pos (0U)
9151 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
9152 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
9153
9154 /****************** Bit definition for QUADSPI_PSMAR register ****************/
9155 #define QUADSPI_PSMAR_MATCH_Pos (0U)
9156 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
9157 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
9158
9159 /****************** Bit definition for QUADSPI_PIR register *****************/
9160 #define QUADSPI_PIR_INTERVAL_Pos (0U)
9161 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
9162 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
9163
9164 /****************** Bit definition for QUADSPI_LPTR register *****************/
9165 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
9166 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
9167 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
9168
9169 /******************************************************************************/
9170 /* */
9171 /* Reset and Clock Control */
9172 /* */
9173 /******************************************************************************/
9174 /******************** Bit definition for RCC_CR register ********************/
9175 #define RCC_CR_HSION_Pos (0U)
9176 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
9177 #define RCC_CR_HSION RCC_CR_HSION_Msk
9178 #define RCC_CR_HSIRDY_Pos (1U)
9179 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
9180 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9181
9182 #define RCC_CR_HSITRIM_Pos (3U)
9183 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
9184 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9185 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
9186 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
9187 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
9188 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
9189 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
9190
9191 #define RCC_CR_HSICAL_Pos (8U)
9192 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
9193 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9194 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
9195 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
9196 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
9197 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
9198 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
9199 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
9200 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
9201 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
9202
9203 #define RCC_CR_HSEON_Pos (16U)
9204 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
9205 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
9206 #define RCC_CR_HSERDY_Pos (17U)
9207 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
9208 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9209 #define RCC_CR_HSEBYP_Pos (18U)
9210 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
9211 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9212 #define RCC_CR_CSSON_Pos (19U)
9213 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
9214 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
9215 #define RCC_CR_PLLON_Pos (24U)
9216 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
9217 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
9218 #define RCC_CR_PLLRDY_Pos (25U)
9219 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
9220 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9221 /*
9222 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9223 */
9224 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
9225
9226 #define RCC_CR_PLLI2SON_Pos (26U)
9227 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
9228 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9229 #define RCC_CR_PLLI2SRDY_Pos (27U)
9230 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
9231 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9232
9233 /******************** Bit definition for RCC_PLLCFGR register ***************/
9234 #define RCC_PLLCFGR_PLLM_Pos (0U)
9235 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
9236 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9237 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
9238 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
9239 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
9240 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
9241 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
9242 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
9243
9244 #define RCC_PLLCFGR_PLLN_Pos (6U)
9245 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
9246 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9247 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
9248 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
9249 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
9250 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
9251 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
9252 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
9253 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
9254 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
9255 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
9256
9257 #define RCC_PLLCFGR_PLLP_Pos (16U)
9258 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
9259 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9260 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
9261 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
9262
9263 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
9264 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
9265 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9266 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9267 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
9268 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9269 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9270
9271 #define RCC_PLLCFGR_PLLQ_Pos (24U)
9272 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
9273 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9274 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
9275 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
9276 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
9277 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
9278 /*
9279 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9280 */
9281 #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
9282
9283 #define RCC_PLLCFGR_PLLR_Pos (28U)
9284 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
9285 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
9286 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
9287 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
9288 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
9289
9290 /******************** Bit definition for RCC_CFGR register ******************/
9291 /*!< SW configuration */
9292 #define RCC_CFGR_SW_Pos (0U)
9293 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
9294 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
9295 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
9296 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
9297
9298 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
9299 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
9300 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
9301
9302 /*!< SWS configuration */
9303 #define RCC_CFGR_SWS_Pos (2U)
9304 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
9305 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
9306 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
9307 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
9308
9309 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
9310 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
9311 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
9312
9313 /*!< HPRE configuration */
9314 #define RCC_CFGR_HPRE_Pos (4U)
9315 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
9316 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
9317 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
9318 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
9319 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
9320 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
9321
9322 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
9323 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
9324 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
9325 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
9326 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
9327 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
9328 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
9329 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
9330 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
9331
9332 /*!< PPRE1 configuration */
9333 #define RCC_CFGR_PPRE1_Pos (10U)
9334 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
9335 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
9336 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
9337 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
9338 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
9339
9340 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
9341 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
9342 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
9343 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
9344 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
9345
9346 /*!< PPRE2 configuration */
9347 #define RCC_CFGR_PPRE2_Pos (13U)
9348 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
9349 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
9350 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
9351 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
9352 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
9353
9354 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
9355 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
9356 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
9357 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
9358 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
9359
9360 /*!< RTCPRE configuration */
9361 #define RCC_CFGR_RTCPRE_Pos (16U)
9362 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
9363 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9364 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
9365 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
9366 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
9367 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
9368 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
9369
9370 /*!< MCO1 configuration */
9371 #define RCC_CFGR_MCO1_Pos (21U)
9372 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
9373 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9374 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
9375 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
9376
9377
9378 #define RCC_CFGR_MCO1PRE_Pos (24U)
9379 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
9380 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9381 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
9382 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
9383 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
9384
9385 #define RCC_CFGR_MCO2PRE_Pos (27U)
9386 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
9387 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9388 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
9389 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
9390 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
9391
9392 #define RCC_CFGR_MCO2_Pos (30U)
9393 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
9394 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9395 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
9396 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
9397
9398 /******************** Bit definition for RCC_CIR register *******************/
9399 #define RCC_CIR_LSIRDYF_Pos (0U)
9400 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
9401 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9402 #define RCC_CIR_LSERDYF_Pos (1U)
9403 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
9404 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9405 #define RCC_CIR_HSIRDYF_Pos (2U)
9406 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
9407 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9408 #define RCC_CIR_HSERDYF_Pos (3U)
9409 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
9410 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9411 #define RCC_CIR_PLLRDYF_Pos (4U)
9412 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
9413 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9414 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
9415 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
9416 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9417
9418 #define RCC_CIR_CSSF_Pos (7U)
9419 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
9420 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9421 #define RCC_CIR_LSIRDYIE_Pos (8U)
9422 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
9423 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9424 #define RCC_CIR_LSERDYIE_Pos (9U)
9425 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
9426 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9427 #define RCC_CIR_HSIRDYIE_Pos (10U)
9428 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
9429 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9430 #define RCC_CIR_HSERDYIE_Pos (11U)
9431 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
9432 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9433 #define RCC_CIR_PLLRDYIE_Pos (12U)
9434 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
9435 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9436 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9437 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
9438 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9439
9440 #define RCC_CIR_LSIRDYC_Pos (16U)
9441 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
9442 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9443 #define RCC_CIR_LSERDYC_Pos (17U)
9444 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
9445 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9446 #define RCC_CIR_HSIRDYC_Pos (18U)
9447 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
9448 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9449 #define RCC_CIR_HSERDYC_Pos (19U)
9450 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
9451 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9452 #define RCC_CIR_PLLRDYC_Pos (20U)
9453 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
9454 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9455 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
9456 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
9457 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9458
9459 #define RCC_CIR_CSSC_Pos (23U)
9460 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
9461 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9462
9463 /******************** Bit definition for RCC_AHB1RSTR register **************/
9464 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9465 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
9466 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9467 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9468 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
9469 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9470 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9471 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
9472 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9473 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9474 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
9475 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9476 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9477 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
9478 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9479 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9480 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
9481 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9482 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9483 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
9484 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9485 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9486 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
9487 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9488 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
9489 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
9490 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9491 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9492 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
9493 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9494 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9495 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
9496 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9497
9498 /******************** Bit definition for RCC_AHB2RSTR register **************/
9499 #define RCC_AHB2RSTR_AESRST_Pos (4U)
9500 #define RCC_AHB2RSTR_AESRST_Msk (0x1U << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00000010 */
9501 #define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
9502 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
9503 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
9504 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9505 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9506 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
9507 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9508 /******************** Bit definition for RCC_AHB3RSTR register **************/
9509 #define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9510 #define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
9511 #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9512 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
9513 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
9514 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
9515
9516
9517 /******************** Bit definition for RCC_APB1RSTR register **************/
9518 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
9519 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
9520 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9521 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
9522 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
9523 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9524 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
9525 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
9526 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9527 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
9528 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
9529 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9530 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
9531 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
9532 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9533 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
9534 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
9535 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9536 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
9537 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
9538 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9539 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
9540 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
9541 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9542 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
9543 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
9544 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9545 #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
9546 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
9547 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
9548 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
9549 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
9550 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9551 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
9552 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
9553 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9554 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
9555 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
9556 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9557 #define RCC_APB1RSTR_USART2RST_Pos (17U)
9558 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
9559 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9560 #define RCC_APB1RSTR_USART3RST_Pos (18U)
9561 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
9562 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9563 #define RCC_APB1RSTR_UART4RST_Pos (19U)
9564 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
9565 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9566 #define RCC_APB1RSTR_UART5RST_Pos (20U)
9567 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
9568 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9569 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
9570 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
9571 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9572 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
9573 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
9574 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9575 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
9576 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
9577 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9578 #define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
9579 #define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
9580 #define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
9581 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
9582 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
9583 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9584 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
9585 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
9586 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9587 #define RCC_APB1RSTR_CAN3RST_Pos (27U)
9588 #define RCC_APB1RSTR_CAN3RST_Msk (0x1U << RCC_APB1RSTR_CAN3RST_Pos) /*!< 0x08000000 */
9589 #define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
9590 #define RCC_APB1RSTR_PWRRST_Pos (28U)
9591 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
9592 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9593 #define RCC_APB1RSTR_DACRST_Pos (29U)
9594 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
9595 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9596 #define RCC_APB1RSTR_UART7RST_Pos (30U)
9597 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
9598 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
9599 #define RCC_APB1RSTR_UART8RST_Pos (31U)
9600 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
9601 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
9602
9603 /******************** Bit definition for RCC_APB2RSTR register **************/
9604 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
9605 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
9606 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9607 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
9608 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
9609 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9610 #define RCC_APB2RSTR_USART1RST_Pos (4U)
9611 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
9612 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9613 #define RCC_APB2RSTR_USART6RST_Pos (5U)
9614 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
9615 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9616 #define RCC_APB2RSTR_UART9RST_Pos (6U)
9617 #define RCC_APB2RSTR_UART9RST_Msk (0x1U << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */
9618 #define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
9619 #define RCC_APB2RSTR_UART10RST_Pos (7U)
9620 #define RCC_APB2RSTR_UART10RST_Msk (0x1U << RCC_APB2RSTR_UART10RST_Pos) /*!< 0x00000080 */
9621 #define RCC_APB2RSTR_UART10RST RCC_APB2RSTR_UART10RST_Msk
9622 #define RCC_APB2RSTR_ADCRST_Pos (8U)
9623 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
9624 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9625 #define RCC_APB2RSTR_SDIORST_Pos (11U)
9626 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
9627 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9628 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
9629 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
9630 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9631 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
9632 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
9633 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
9634 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9635 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
9636 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9637 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
9638 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
9639 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9640 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
9641 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
9642 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9643 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
9644 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
9645 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9646 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
9647 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
9648 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
9649 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
9650 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
9651 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
9652 #define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
9653 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
9654 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
9655 #define RCC_APB2RSTR_DFSDM2RST_Pos (25U)
9656 #define RCC_APB2RSTR_DFSDM2RST_Msk (0x1U << RCC_APB2RSTR_DFSDM2RST_Pos) /*!< 0x02000000 */
9657 #define RCC_APB2RSTR_DFSDM2RST RCC_APB2RSTR_DFSDM2RST_Msk
9658
9659 /******************** Bit definition for RCC_AHB1ENR register ***************/
9660 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9661 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
9662 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9663 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9664 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
9665 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9666 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9667 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
9668 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9669 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
9670 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
9671 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9672 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9673 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
9674 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9675 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9676 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
9677 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
9678 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
9679 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
9680 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
9681 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9682 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
9683 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9684 #define RCC_AHB1ENR_CRCEN_Pos (12U)
9685 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
9686 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9687 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
9688 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
9689 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9690 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
9691 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
9692 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9693 /******************** Bit definition for RCC_AHB2ENR register ***************/
9694 /*
9695 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9696 */
9697 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
9698
9699 #define RCC_AHB2ENR_AESEN_Pos (4U)
9700 #define RCC_AHB2ENR_AESEN_Msk (0x1U << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00000010 */
9701 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
9702 #define RCC_AHB2ENR_RNGEN_Pos (6U)
9703 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
9704 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9705 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9706 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
9707 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9708
9709 /******************** Bit definition for RCC_AHB3ENR register ***************/
9710 /*
9711 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9712 */
9713 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
9714
9715 #define RCC_AHB3ENR_FSMCEN_Pos (0U)
9716 #define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
9717 #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
9718 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
9719 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
9720 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
9721
9722 /******************** Bit definition for RCC_APB1ENR register ***************/
9723 #define RCC_APB1ENR_TIM2EN_Pos (0U)
9724 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
9725 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
9726 #define RCC_APB1ENR_TIM3EN_Pos (1U)
9727 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
9728 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
9729 #define RCC_APB1ENR_TIM4EN_Pos (2U)
9730 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
9731 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
9732 #define RCC_APB1ENR_TIM5EN_Pos (3U)
9733 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
9734 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
9735 #define RCC_APB1ENR_TIM6EN_Pos (4U)
9736 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
9737 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
9738 #define RCC_APB1ENR_TIM7EN_Pos (5U)
9739 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
9740 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
9741 #define RCC_APB1ENR_TIM12EN_Pos (6U)
9742 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
9743 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
9744 #define RCC_APB1ENR_TIM13EN_Pos (7U)
9745 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
9746 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
9747 #define RCC_APB1ENR_TIM14EN_Pos (8U)
9748 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
9749 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
9750 #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
9751 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
9752 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
9753 #define RCC_APB1ENR_RTCAPBEN_Pos (10U)
9754 #define RCC_APB1ENR_RTCAPBEN_Msk (0x1U << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
9755 #define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
9756 #define RCC_APB1ENR_WWDGEN_Pos (11U)
9757 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
9758 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
9759 #define RCC_APB1ENR_SPI2EN_Pos (14U)
9760 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
9761 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
9762 #define RCC_APB1ENR_SPI3EN_Pos (15U)
9763 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
9764 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
9765 #define RCC_APB1ENR_USART2EN_Pos (17U)
9766 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
9767 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
9768 #define RCC_APB1ENR_USART3EN_Pos (18U)
9769 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
9770 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
9771 #define RCC_APB1ENR_UART4EN_Pos (19U)
9772 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
9773 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
9774 #define RCC_APB1ENR_UART5EN_Pos (20U)
9775 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
9776 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
9777 #define RCC_APB1ENR_I2C1EN_Pos (21U)
9778 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
9779 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
9780 #define RCC_APB1ENR_I2C2EN_Pos (22U)
9781 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
9782 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
9783 #define RCC_APB1ENR_I2C3EN_Pos (23U)
9784 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
9785 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
9786 #define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
9787 #define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
9788 #define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
9789 #define RCC_APB1ENR_CAN1EN_Pos (25U)
9790 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
9791 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
9792 #define RCC_APB1ENR_CAN2EN_Pos (26U)
9793 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
9794 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
9795 #define RCC_APB1ENR_CAN3EN_Pos (27U)
9796 #define RCC_APB1ENR_CAN3EN_Msk (0x1U << RCC_APB1ENR_CAN3EN_Pos) /*!< 0x08000000 */
9797 #define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
9798 #define RCC_APB1ENR_PWREN_Pos (28U)
9799 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
9800 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
9801 #define RCC_APB1ENR_DACEN_Pos (29U)
9802 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
9803 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
9804 #define RCC_APB1ENR_UART7EN_Pos (30U)
9805 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
9806 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
9807 #define RCC_APB1ENR_UART8EN_Pos (31U)
9808 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
9809 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
9810
9811 /******************** Bit definition for RCC_APB2ENR register ***************/
9812 #define RCC_APB2ENR_TIM1EN_Pos (0U)
9813 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
9814 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
9815 #define RCC_APB2ENR_TIM8EN_Pos (1U)
9816 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
9817 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
9818 #define RCC_APB2ENR_USART1EN_Pos (4U)
9819 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
9820 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
9821 #define RCC_APB2ENR_USART6EN_Pos (5U)
9822 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
9823 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
9824 #define RCC_APB2ENR_UART9EN_Pos (6U)
9825 #define RCC_APB2ENR_UART9EN_Msk (0x1U << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */
9826 #define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
9827 #define RCC_APB2ENR_UART10EN_Pos (7U)
9828 #define RCC_APB2ENR_UART10EN_Msk (0x1U << RCC_APB2ENR_UART10EN_Pos) /*!< 0x00000080 */
9829 #define RCC_APB2ENR_UART10EN RCC_APB2ENR_UART10EN_Msk
9830 #define RCC_APB2ENR_ADC1EN_Pos (8U)
9831 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
9832 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
9833 #define RCC_APB2ENR_SDIOEN_Pos (11U)
9834 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
9835 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
9836 #define RCC_APB2ENR_SPI1EN_Pos (12U)
9837 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
9838 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
9839 #define RCC_APB2ENR_SPI4EN_Pos (13U)
9840 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
9841 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
9842 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
9843 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
9844 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
9845 #define RCC_APB2ENR_EXTITEN_Pos (15U)
9846 #define RCC_APB2ENR_EXTITEN_Msk (0x1U << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
9847 #define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
9848 #define RCC_APB2ENR_TIM9EN_Pos (16U)
9849 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
9850 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
9851 #define RCC_APB2ENR_TIM10EN_Pos (17U)
9852 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
9853 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
9854 #define RCC_APB2ENR_TIM11EN_Pos (18U)
9855 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
9856 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
9857 #define RCC_APB2ENR_SPI5EN_Pos (20U)
9858 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
9859 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
9860 #define RCC_APB2ENR_SAI1EN_Pos (22U)
9861 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
9862 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
9863 #define RCC_APB2ENR_DFSDM1EN_Pos (24U)
9864 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
9865 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
9866 #define RCC_APB2ENR_DFSDM2EN_Pos (25U)
9867 #define RCC_APB2ENR_DFSDM2EN_Msk (0x1U << RCC_APB2ENR_DFSDM2EN_Pos) /*!< 0x02000000 */
9868 #define RCC_APB2ENR_DFSDM2EN RCC_APB2ENR_DFSDM2EN_Msk
9869
9870 /******************** Bit definition for RCC_AHB1LPENR register *************/
9871 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
9872 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
9873 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
9874 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
9875 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
9876 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
9877 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
9878 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
9879 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
9880 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
9881 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
9882 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
9883 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
9884 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
9885 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
9886 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
9887 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
9888 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
9889 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
9890 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
9891 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
9892 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
9893 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
9894 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
9895 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
9896 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
9897 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
9898 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
9899 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
9900 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
9901 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
9902 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
9903 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
9904 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
9905 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
9906 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
9907 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
9908 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
9909 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
9910 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
9911 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
9912 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
9913
9914
9915 /******************** Bit definition for RCC_AHB2LPENR register *************/
9916 #define RCC_AHB2LPENR_AESLPEN_Pos (4U)
9917 #define RCC_AHB2LPENR_AESLPEN_Msk (0x1U << RCC_AHB2LPENR_AESLPEN_Pos) /*!< 0x00000010 */
9918 #define RCC_AHB2LPENR_AESLPEN RCC_AHB2LPENR_AESLPEN_Msk
9919 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
9920 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
9921 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
9922 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
9923 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
9924 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
9925
9926 /******************** Bit definition for RCC_AHB3LPENR register *************/
9927 #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
9928 #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
9929 #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
9930 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
9931 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
9932 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
9933
9934 /******************** Bit definition for RCC_APB1LPENR register *************/
9935 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
9936 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
9937 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
9938 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
9939 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
9940 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
9941 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
9942 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
9943 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
9944 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
9945 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
9946 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
9947 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
9948 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
9949 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
9950 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
9951 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
9952 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
9953 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
9954 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
9955 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
9956 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
9957 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
9958 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
9959 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
9960 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
9961 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
9962 #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
9963 #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
9964 #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
9965 #define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
9966 #define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1U << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
9967 #define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
9968 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
9969 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
9970 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
9971 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
9972 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
9973 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
9974 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
9975 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
9976 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
9977 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
9978 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
9979 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
9980 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
9981 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
9982 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
9983 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
9984 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
9985 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
9986 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
9987 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
9988 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
9989 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
9990 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
9991 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
9992 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
9993 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
9994 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
9995 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
9996 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
9997 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
9998 #define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
9999 #define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
10000 #define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
10001 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10002 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
10003 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10004 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10005 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
10006 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10007 #define RCC_APB1LPENR_CAN3LPEN_Pos (27U)
10008 #define RCC_APB1LPENR_CAN3LPEN_Msk (0x1U << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x08000000 */
10009 #define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
10010 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10011 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
10012 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10013 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
10014 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
10015 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10016 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
10017 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
10018 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
10019 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
10020 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
10021 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
10022
10023 /******************** Bit definition for RCC_APB2LPENR register *************/
10024 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10025 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
10026 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10027 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10028 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
10029 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10030 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10031 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
10032 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10033 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10034 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
10035 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10036 #define RCC_APB2LPENR_UART9LPEN_Pos (6U)
10037 #define RCC_APB2LPENR_UART9LPEN_Msk (0x1U << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */
10038 #define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
10039 #define RCC_APB2LPENR_UART10LPEN_Pos (7U)
10040 #define RCC_APB2LPENR_UART10LPEN_Msk (0x1U << RCC_APB2LPENR_UART10LPEN_Pos) /*!< 0x00000080 */
10041 #define RCC_APB2LPENR_UART10LPEN RCC_APB2LPENR_UART10LPEN_Msk
10042 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10043 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
10044 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10045 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
10046 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
10047 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
10048 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10049 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
10050 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10051 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
10052 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
10053 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
10054 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10055 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
10056 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10057 #define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
10058 #define RCC_APB2LPENR_EXTITLPEN_Msk (0x1U << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
10059 #define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
10060 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10061 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
10062 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10063 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10064 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
10065 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10066 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10067 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
10068 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10069 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
10070 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
10071 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
10072 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
10073 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
10074 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
10075 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (24U)
10076 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */
10077 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
10078 #define RCC_APB2LPENR_DFSDM2LPEN_Pos (25U)
10079 #define RCC_APB2LPENR_DFSDM2LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM2LPEN_Pos) /*!< 0x02000000 */
10080 #define RCC_APB2LPENR_DFSDM2LPEN RCC_APB2LPENR_DFSDM2LPEN_Msk
10081
10082 /******************** Bit definition for RCC_BDCR register ******************/
10083 #define RCC_BDCR_LSEON_Pos (0U)
10084 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
10085 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10086 #define RCC_BDCR_LSERDY_Pos (1U)
10087 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
10088 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10089 #define RCC_BDCR_LSEBYP_Pos (2U)
10090 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
10091 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10092 #define RCC_BDCR_LSEMOD_Pos (3U)
10093 #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
10094 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
10095
10096 #define RCC_BDCR_RTCSEL_Pos (8U)
10097 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
10098 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10099 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
10100 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
10101
10102 #define RCC_BDCR_RTCEN_Pos (15U)
10103 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
10104 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10105 #define RCC_BDCR_BDRST_Pos (16U)
10106 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
10107 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10108
10109 /******************** Bit definition for RCC_CSR register *******************/
10110 #define RCC_CSR_LSION_Pos (0U)
10111 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
10112 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
10113 #define RCC_CSR_LSIRDY_Pos (1U)
10114 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
10115 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10116 #define RCC_CSR_RMVF_Pos (24U)
10117 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
10118 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10119 #define RCC_CSR_PINRSTF_Pos (26U)
10120 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
10121 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10122 #define RCC_CSR_PORRSTF_Pos (27U)
10123 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
10124 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10125 #define RCC_CSR_SFTRSTF_Pos (28U)
10126 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
10127 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10128 #define RCC_CSR_IWDGRSTF_Pos (29U)
10129 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
10130 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10131 #define RCC_CSR_WWDGRSTF_Pos (30U)
10132 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
10133 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10134 #define RCC_CSR_LPWRRSTF_Pos (31U)
10135 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
10136 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10137 /* Legacy defines */
10138 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10139 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10140
10141 /******************** Bit definition for RCC_SSCGR register *****************/
10142 #define RCC_SSCGR_MODPER_Pos (0U)
10143 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
10144 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10145 #define RCC_SSCGR_INCSTEP_Pos (13U)
10146 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
10147 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10148 #define RCC_SSCGR_SPREADSEL_Pos (30U)
10149 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
10150 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10151 #define RCC_SSCGR_SSCGEN_Pos (31U)
10152 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
10153 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10154
10155 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
10156 #define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
10157 #define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
10158 #define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
10159 #define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
10160 #define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
10161 #define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
10162 #define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
10163 #define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
10164 #define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
10165
10166 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10167 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
10168 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10169 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
10170 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
10171 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
10172 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
10173 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
10174 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
10175 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
10176 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
10177 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
10178
10179 #define RCC_PLLI2SCFGR_PLLI2SSRC_Pos (22U)
10180 #define RCC_PLLI2SCFGR_PLLI2SSRC_Msk (0x1U << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */
10181 #define RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC_Msk
10182 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
10183 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
10184 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
10185 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
10186 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
10187 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
10188 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
10189 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10190 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
10191 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10192 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
10193 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
10194 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
10195
10196
10197
10198 /******************** Bit definition for RCC_DCKCFGR register ***************/
10199 #define RCC_DCKCFGR_PLLI2SDIVR_Pos (0U)
10200 #define RCC_DCKCFGR_PLLI2SDIVR_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x0000001F */
10201 #define RCC_DCKCFGR_PLLI2SDIVR RCC_DCKCFGR_PLLI2SDIVR_Msk
10202 #define RCC_DCKCFGR_PLLI2SDIVR_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000001 */
10203 #define RCC_DCKCFGR_PLLI2SDIVR_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000002 */
10204 #define RCC_DCKCFGR_PLLI2SDIVR_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000004 */
10205 #define RCC_DCKCFGR_PLLI2SDIVR_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000008 */
10206 #define RCC_DCKCFGR_PLLI2SDIVR_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000010 */
10207
10208 #define RCC_DCKCFGR_PLLDIVR_Pos (8U)
10209 #define RCC_DCKCFGR_PLLDIVR_Msk (0x1FU << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001F00 */
10210 #define RCC_DCKCFGR_PLLDIVR RCC_DCKCFGR_PLLDIVR_Msk
10211 #define RCC_DCKCFGR_PLLDIVR_0 (0x01U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000100 */
10212 #define RCC_DCKCFGR_PLLDIVR_1 (0x02U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000200 */
10213 #define RCC_DCKCFGR_PLLDIVR_2 (0x04U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000400 */
10214 #define RCC_DCKCFGR_PLLDIVR_3 (0x08U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000800 */
10215 #define RCC_DCKCFGR_PLLDIVR_4 (0x10U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001000 */
10216
10217 #define RCC_DCKCFGR_CKDFSDM2ASEL_Pos (14U)
10218 #define RCC_DCKCFGR_CKDFSDM2ASEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM2ASEL_Pos) /*!< 0x00004000 */
10219 #define RCC_DCKCFGR_CKDFSDM2ASEL RCC_DCKCFGR_CKDFSDM2ASEL_Msk
10220 #define RCC_DCKCFGR_CKDFSDM1ASEL_Pos (15U)
10221 #define RCC_DCKCFGR_CKDFSDM1ASEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */
10222 #define RCC_DCKCFGR_CKDFSDM1ASEL RCC_DCKCFGR_CKDFSDM1ASEL_Msk
10223
10224 /*
10225 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10226 */
10227 #define RCC_SAI1A_PLLSOURCE_SUPPORT /*!< SAI1 block A PLL Main source clock support */
10228 #define RCC_SAI1B_PLLSOURCE_SUPPORT /*!< SAI1 block B PLL Main source clock support */
10229
10230 #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
10231 #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
10232 #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
10233 #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
10234 #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
10235 #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
10236 #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
10237 #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
10238 #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
10239 #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
10240 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
10241 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
10242 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
10243 #define RCC_DCKCFGR_I2S1SRC_Pos (25U)
10244 #define RCC_DCKCFGR_I2S1SRC_Msk (0x3U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x06000000 */
10245 #define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
10246 #define RCC_DCKCFGR_I2S1SRC_0 (0x1U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x02000000 */
10247 #define RCC_DCKCFGR_I2S1SRC_1 (0x2U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x04000000 */
10248
10249 #define RCC_DCKCFGR_I2S2SRC_Pos (27U)
10250 #define RCC_DCKCFGR_I2S2SRC_Msk (0x3U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x18000000 */
10251 #define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
10252 #define RCC_DCKCFGR_I2S2SRC_0 (0x1U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x08000000 */
10253 #define RCC_DCKCFGR_I2S2SRC_1 (0x2U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x10000000 */
10254 #define RCC_DCKCFGR_CKDFSDM1SEL_Pos (31U)
10255 #define RCC_DCKCFGR_CKDFSDM1SEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */
10256 #define RCC_DCKCFGR_CKDFSDM1SEL RCC_DCKCFGR_CKDFSDM1SEL_Msk
10257
10258 /******************** Bit definition for RCC_CKGATENR register ***************/
10259 #define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
10260 #define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
10261 #define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
10262 #define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
10263 #define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
10264 #define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
10265 #define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
10266 #define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1U << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
10267 #define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
10268 #define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
10269 #define RCC_CKGATENR_SPARE_CKEN_Msk (0x1U << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
10270 #define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
10271 #define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
10272 #define RCC_CKGATENR_SRAM_CKEN_Msk (0x1U << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
10273 #define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
10274 #define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
10275 #define RCC_CKGATENR_FLITF_CKEN_Msk (0x1U << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
10276 #define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
10277 #define RCC_CKGATENR_RCC_CKEN_Pos (6U)
10278 #define RCC_CKGATENR_RCC_CKEN_Msk (0x1U << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
10279 #define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
10280 #define RCC_CKGATENR_RCC_EVTCTL_Pos (7U)
10281 #define RCC_CKGATENR_RCC_EVTCTL_Msk (0x1U << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */
10282 #define RCC_CKGATENR_RCC_EVTCTL RCC_CKGATENR_RCC_EVTCTL_Msk
10283
10284 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
10285 #define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
10286 #define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
10287 #define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
10288 #define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
10289 #define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
10290 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
10291 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
10292 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
10293 #define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
10294 #define RCC_DCKCFGR2_SDIOSEL_Msk (0x1U << RCC_DCKCFGR2_SDIOSEL_Pos) /*!< 0x10000000 */
10295 #define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
10296 #define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
10297 #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
10298 #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
10299 #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
10300 #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
10301
10302
10303 /******************************************************************************/
10304 /* */
10305 /* Advanced Encryption Standard (AES) */
10306 /* */
10307 /******************************************************************************/
10308 /******************* Bit definition for AES_CR register *********************/
10309 #define AES_CR_EN ((uint32_t)0x00000001U) /*!< AES Enable */
10310 #define AES_CR_DATATYPE ((uint32_t)0x00000006U) /*!< Data type selection */
10311 #define AES_CR_DATATYPE_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
10312 #define AES_CR_DATATYPE_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
10313
10314 #define AES_CR_MODE ((uint32_t)0x00000018U) /*!< AES Mode Of Operation */
10315 #define AES_CR_MODE_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
10316 #define AES_CR_MODE_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
10317
10318 #define AES_CR_CHMOD ((uint32_t)0x00010060U) /*!< AES Chaining Mode */
10319 #define AES_CR_CHMOD_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
10320 #define AES_CR_CHMOD_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
10321 #define AES_CR_CHMOD_2 ((uint32_t)0x00010000U) /*!< Bit 2 */
10322
10323 #define AES_CR_CCFC ((uint32_t)0x00000080U) /*!< Computation Complete Flag Clear */
10324 #define AES_CR_ERRC ((uint32_t)0x00000100U) /*!< Error Clear */
10325 #define AES_CR_CCFIE ((uint32_t)0x00000200U) /*!< Computation Complete Flag Interrupt Enable */
10326 #define AES_CR_ERRIE ((uint32_t)0x00000400U) /*!< Error Interrupt Enable */
10327 #define AES_CR_DMAINEN ((uint32_t)0x00000800U) /*!< Enable data input phase DMA management */
10328 #define AES_CR_DMAOUTEN ((uint32_t)0x00001000U) /*!< Enable data output phase DMA management */
10329
10330 #define AES_CR_GCMPH ((uint32_t)0x00006000U) /*!< GCM Phase */
10331 #define AES_CR_GCMPH_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
10332 #define AES_CR_GCMPH_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
10333
10334 #define AES_CR_KEYSIZE ((uint32_t)0x00040000U) /*!< Key size selection */
10335
10336 /******************* Bit definition for AES_SR register *********************/
10337 #define AES_SR_CCF ((uint32_t)0x00000001U) /*!< Computation Complete Flag */
10338 #define AES_SR_RDERR ((uint32_t)0x00000002U) /*!< Read Error Flag */
10339 #define AES_SR_WRERR ((uint32_t)0x00000004U) /*!< Write Error Flag */
10340 #define AES_SR_BUSY ((uint32_t)0x00000008U) /*!< Busy Flag */
10341
10342 /******************* Bit definition for AES_DINR register *******************/
10343 #define AES_DINR ((uint32_t)0xFFFFFFFFU) /*!< AES Data Input Register */
10344
10345 /******************* Bit definition for AES_DOUTR register ******************/
10346 #define AES_DOUTR ((uint32_t)0xFFFFFFFFU) /*!< AES Data Output Register */
10347
10348 /******************* Bit definition for AES_KEYR0 register ******************/
10349 #define AES_KEYR0 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 0 */
10350
10351 /******************* Bit definition for AES_KEYR1 register ******************/
10352 #define AES_KEYR1 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 1 */
10353
10354 /******************* Bit definition for AES_KEYR2 register ******************/
10355 #define AES_KEYR2 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 2 */
10356
10357 /******************* Bit definition for AES_KEYR3 register ******************/
10358 #define AES_KEYR3 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 3 */
10359
10360 /******************* Bit definition for AES_KEYR4 register ******************/
10361 #define AES_KEYR4 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 4 */
10362
10363 /******************* Bit definition for AES_KEYR5 register ******************/
10364 #define AES_KEYR5 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 5 */
10365
10366 /******************* Bit definition for AES_KEYR6 register ******************/
10367 #define AES_KEYR6 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 6 */
10368
10369 /******************* Bit definition for AES_KEYR7 register ******************/
10370 #define AES_KEYR7 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 7 */
10371
10372 /******************* Bit definition for AES_IVR0 register ******************/
10373 #define AES_IVR0 ((uint32_t)0xFFFFFFFFU) /*!< AES Initialization Vector Register 0 */
10374
10375 /******************* Bit definition for AES_IVR1 register ******************/
10376 #define AES_IVR1 ((uint32_t)0xFFFFFFFFU) /*!< AES Initialization Vector Register 1 */
10377
10378 /******************* Bit definition for AES_IVR2 register ******************/
10379 #define AES_IVR2 ((uint32_t)0xFFFFFFFFU) /*!< AES Initialization Vector Register 2 */
10380
10381 /******************* Bit definition for AES_IVR3 register ******************/
10382 #define AES_IVR3 ((uint32_t)0xFFFFFFFFU) /*!< AES Initialization Vector Register 3 */
10383
10384 /******************* Bit definition for AES_SUSP0R register ******************/
10385 #define AES_SUSP0R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 0 */
10386
10387 /******************* Bit definition for AES_SUSP1R register ******************/
10388 #define AES_SUSP1R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 1 */
10389
10390 /******************* Bit definition for AES_SUSP2R register ******************/
10391 #define AES_SUSP2R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 2 */
10392
10393 /******************* Bit definition for AES_SUSP3R register ******************/
10394 #define AES_SUSP3R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 3 */
10395
10396 /******************* Bit definition for AES_SUSP4R register ******************/
10397 #define AES_SUSP4R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 4 */
10398
10399 /******************* Bit definition for AES_SUSP5R register ******************/
10400 #define AES_SUSP5R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 5 */
10401
10402 /******************* Bit definition for AES_SUSP6R register ******************/
10403 #define AES_SUSP6R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 6 */
10404
10405 /******************* Bit definition for AES_SUSP7R register ******************/
10406 #define AES_SUSP7R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 7 */
10407
10408 /******************************************************************************/
10409 /* */
10410 /* RNG */
10411 /* */
10412 /******************************************************************************/
10413 /******************** Bits definition for RNG_CR register *******************/
10414 #define RNG_CR_RNGEN_Pos (2U)
10415 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
10416 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10417 #define RNG_CR_IE_Pos (3U)
10418 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
10419 #define RNG_CR_IE RNG_CR_IE_Msk
10420
10421 /******************** Bits definition for RNG_SR register *******************/
10422 #define RNG_SR_DRDY_Pos (0U)
10423 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
10424 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
10425 #define RNG_SR_CECS_Pos (1U)
10426 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
10427 #define RNG_SR_CECS RNG_SR_CECS_Msk
10428 #define RNG_SR_SECS_Pos (2U)
10429 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
10430 #define RNG_SR_SECS RNG_SR_SECS_Msk
10431 #define RNG_SR_CEIS_Pos (5U)
10432 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
10433 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
10434 #define RNG_SR_SEIS_Pos (6U)
10435 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
10436 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
10437
10438 /******************************************************************************/
10439 /* */
10440 /* Real-Time Clock (RTC) */
10441 /* */
10442 /******************************************************************************/
10443 /******************** Bits definition for RTC_TR register *******************/
10444 #define RTC_TR_PM_Pos (22U)
10445 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
10446 #define RTC_TR_PM RTC_TR_PM_Msk
10447 #define RTC_TR_HT_Pos (20U)
10448 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
10449 #define RTC_TR_HT RTC_TR_HT_Msk
10450 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
10451 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
10452 #define RTC_TR_HU_Pos (16U)
10453 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
10454 #define RTC_TR_HU RTC_TR_HU_Msk
10455 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
10456 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
10457 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
10458 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
10459 #define RTC_TR_MNT_Pos (12U)
10460 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
10461 #define RTC_TR_MNT RTC_TR_MNT_Msk
10462 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
10463 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
10464 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
10465 #define RTC_TR_MNU_Pos (8U)
10466 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
10467 #define RTC_TR_MNU RTC_TR_MNU_Msk
10468 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
10469 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
10470 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
10471 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
10472 #define RTC_TR_ST_Pos (4U)
10473 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
10474 #define RTC_TR_ST RTC_TR_ST_Msk
10475 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
10476 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
10477 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
10478 #define RTC_TR_SU_Pos (0U)
10479 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
10480 #define RTC_TR_SU RTC_TR_SU_Msk
10481 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
10482 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
10483 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
10484 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
10485
10486 /******************** Bits definition for RTC_DR register *******************/
10487 #define RTC_DR_YT_Pos (20U)
10488 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
10489 #define RTC_DR_YT RTC_DR_YT_Msk
10490 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
10491 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
10492 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
10493 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
10494 #define RTC_DR_YU_Pos (16U)
10495 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
10496 #define RTC_DR_YU RTC_DR_YU_Msk
10497 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
10498 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
10499 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
10500 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
10501 #define RTC_DR_WDU_Pos (13U)
10502 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
10503 #define RTC_DR_WDU RTC_DR_WDU_Msk
10504 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
10505 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
10506 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
10507 #define RTC_DR_MT_Pos (12U)
10508 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
10509 #define RTC_DR_MT RTC_DR_MT_Msk
10510 #define RTC_DR_MU_Pos (8U)
10511 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
10512 #define RTC_DR_MU RTC_DR_MU_Msk
10513 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
10514 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
10515 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
10516 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
10517 #define RTC_DR_DT_Pos (4U)
10518 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
10519 #define RTC_DR_DT RTC_DR_DT_Msk
10520 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
10521 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
10522 #define RTC_DR_DU_Pos (0U)
10523 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
10524 #define RTC_DR_DU RTC_DR_DU_Msk
10525 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
10526 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
10527 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
10528 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
10529
10530 /******************** Bits definition for RTC_CR register *******************/
10531 #define RTC_CR_COE_Pos (23U)
10532 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
10533 #define RTC_CR_COE RTC_CR_COE_Msk
10534 #define RTC_CR_OSEL_Pos (21U)
10535 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
10536 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
10537 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
10538 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
10539 #define RTC_CR_POL_Pos (20U)
10540 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
10541 #define RTC_CR_POL RTC_CR_POL_Msk
10542 #define RTC_CR_COSEL_Pos (19U)
10543 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
10544 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
10545 #define RTC_CR_BKP_Pos (18U)
10546 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
10547 #define RTC_CR_BKP RTC_CR_BKP_Msk
10548 #define RTC_CR_SUB1H_Pos (17U)
10549 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
10550 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10551 #define RTC_CR_ADD1H_Pos (16U)
10552 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
10553 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10554 #define RTC_CR_TSIE_Pos (15U)
10555 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
10556 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
10557 #define RTC_CR_WUTIE_Pos (14U)
10558 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
10559 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10560 #define RTC_CR_ALRBIE_Pos (13U)
10561 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
10562 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10563 #define RTC_CR_ALRAIE_Pos (12U)
10564 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
10565 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10566 #define RTC_CR_TSE_Pos (11U)
10567 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
10568 #define RTC_CR_TSE RTC_CR_TSE_Msk
10569 #define RTC_CR_WUTE_Pos (10U)
10570 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
10571 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
10572 #define RTC_CR_ALRBE_Pos (9U)
10573 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
10574 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10575 #define RTC_CR_ALRAE_Pos (8U)
10576 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
10577 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10578 #define RTC_CR_DCE_Pos (7U)
10579 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
10580 #define RTC_CR_DCE RTC_CR_DCE_Msk
10581 #define RTC_CR_FMT_Pos (6U)
10582 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
10583 #define RTC_CR_FMT RTC_CR_FMT_Msk
10584 #define RTC_CR_BYPSHAD_Pos (5U)
10585 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
10586 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10587 #define RTC_CR_REFCKON_Pos (4U)
10588 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
10589 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10590 #define RTC_CR_TSEDGE_Pos (3U)
10591 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
10592 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10593 #define RTC_CR_WUCKSEL_Pos (0U)
10594 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
10595 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10596 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
10597 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
10598 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
10599
10600 /* Legacy defines */
10601 #define RTC_CR_BCK RTC_CR_BKP
10602
10603 /******************** Bits definition for RTC_ISR register ******************/
10604 #define RTC_ISR_RECALPF_Pos (16U)
10605 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
10606 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10607 #define RTC_ISR_TAMP1F_Pos (13U)
10608 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
10609 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10610 #define RTC_ISR_TAMP2F_Pos (14U)
10611 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
10612 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10613 #define RTC_ISR_TSOVF_Pos (12U)
10614 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
10615 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10616 #define RTC_ISR_TSF_Pos (11U)
10617 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
10618 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
10619 #define RTC_ISR_WUTF_Pos (10U)
10620 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
10621 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10622 #define RTC_ISR_ALRBF_Pos (9U)
10623 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
10624 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10625 #define RTC_ISR_ALRAF_Pos (8U)
10626 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
10627 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10628 #define RTC_ISR_INIT_Pos (7U)
10629 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
10630 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
10631 #define RTC_ISR_INITF_Pos (6U)
10632 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
10633 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
10634 #define RTC_ISR_RSF_Pos (5U)
10635 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
10636 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
10637 #define RTC_ISR_INITS_Pos (4U)
10638 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
10639 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
10640 #define RTC_ISR_SHPF_Pos (3U)
10641 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
10642 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10643 #define RTC_ISR_WUTWF_Pos (2U)
10644 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
10645 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10646 #define RTC_ISR_ALRBWF_Pos (1U)
10647 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
10648 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10649 #define RTC_ISR_ALRAWF_Pos (0U)
10650 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
10651 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10652
10653 /******************** Bits definition for RTC_PRER register *****************/
10654 #define RTC_PRER_PREDIV_A_Pos (16U)
10655 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
10656 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10657 #define RTC_PRER_PREDIV_S_Pos (0U)
10658 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
10659 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10660
10661 /******************** Bits definition for RTC_WUTR register *****************/
10662 #define RTC_WUTR_WUT_Pos (0U)
10663 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
10664 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10665
10666 /******************** Bits definition for RTC_CALIBR register ***************/
10667 #define RTC_CALIBR_DCS_Pos (7U)
10668 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
10669 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10670 #define RTC_CALIBR_DC_Pos (0U)
10671 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
10672 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10673
10674 /******************** Bits definition for RTC_ALRMAR register ***************/
10675 #define RTC_ALRMAR_MSK4_Pos (31U)
10676 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
10677 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10678 #define RTC_ALRMAR_WDSEL_Pos (30U)
10679 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
10680 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10681 #define RTC_ALRMAR_DT_Pos (28U)
10682 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
10683 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10684 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
10685 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
10686 #define RTC_ALRMAR_DU_Pos (24U)
10687 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
10688 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10689 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
10690 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
10691 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
10692 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
10693 #define RTC_ALRMAR_MSK3_Pos (23U)
10694 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
10695 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10696 #define RTC_ALRMAR_PM_Pos (22U)
10697 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
10698 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10699 #define RTC_ALRMAR_HT_Pos (20U)
10700 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
10701 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10702 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
10703 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
10704 #define RTC_ALRMAR_HU_Pos (16U)
10705 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
10706 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10707 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
10708 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
10709 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
10710 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
10711 #define RTC_ALRMAR_MSK2_Pos (15U)
10712 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
10713 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10714 #define RTC_ALRMAR_MNT_Pos (12U)
10715 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
10716 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10717 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
10718 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
10719 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
10720 #define RTC_ALRMAR_MNU_Pos (8U)
10721 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
10722 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10723 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
10724 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
10725 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
10726 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
10727 #define RTC_ALRMAR_MSK1_Pos (7U)
10728 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
10729 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10730 #define RTC_ALRMAR_ST_Pos (4U)
10731 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
10732 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10733 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
10734 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
10735 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
10736 #define RTC_ALRMAR_SU_Pos (0U)
10737 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
10738 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10739 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
10740 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
10741 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
10742 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
10743
10744 /******************** Bits definition for RTC_ALRMBR register ***************/
10745 #define RTC_ALRMBR_MSK4_Pos (31U)
10746 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
10747 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10748 #define RTC_ALRMBR_WDSEL_Pos (30U)
10749 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
10750 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10751 #define RTC_ALRMBR_DT_Pos (28U)
10752 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
10753 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10754 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
10755 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
10756 #define RTC_ALRMBR_DU_Pos (24U)
10757 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
10758 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10759 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
10760 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
10761 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
10762 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
10763 #define RTC_ALRMBR_MSK3_Pos (23U)
10764 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
10765 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10766 #define RTC_ALRMBR_PM_Pos (22U)
10767 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
10768 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10769 #define RTC_ALRMBR_HT_Pos (20U)
10770 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
10771 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10772 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
10773 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
10774 #define RTC_ALRMBR_HU_Pos (16U)
10775 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
10776 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10777 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
10778 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
10779 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
10780 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
10781 #define RTC_ALRMBR_MSK2_Pos (15U)
10782 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
10783 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10784 #define RTC_ALRMBR_MNT_Pos (12U)
10785 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
10786 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10787 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
10788 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
10789 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
10790 #define RTC_ALRMBR_MNU_Pos (8U)
10791 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
10792 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10793 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
10794 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
10795 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
10796 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
10797 #define RTC_ALRMBR_MSK1_Pos (7U)
10798 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
10799 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10800 #define RTC_ALRMBR_ST_Pos (4U)
10801 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
10802 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10803 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
10804 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
10805 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
10806 #define RTC_ALRMBR_SU_Pos (0U)
10807 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
10808 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10809 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
10810 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
10811 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
10812 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
10813
10814 /******************** Bits definition for RTC_WPR register ******************/
10815 #define RTC_WPR_KEY_Pos (0U)
10816 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
10817 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
10818
10819 /******************** Bits definition for RTC_SSR register ******************/
10820 #define RTC_SSR_SS_Pos (0U)
10821 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
10822 #define RTC_SSR_SS RTC_SSR_SS_Msk
10823
10824 /******************** Bits definition for RTC_SHIFTR register ***************/
10825 #define RTC_SHIFTR_SUBFS_Pos (0U)
10826 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
10827 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10828 #define RTC_SHIFTR_ADD1S_Pos (31U)
10829 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
10830 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10831
10832 /******************** Bits definition for RTC_TSTR register *****************/
10833 #define RTC_TSTR_PM_Pos (22U)
10834 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
10835 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
10836 #define RTC_TSTR_HT_Pos (20U)
10837 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
10838 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
10839 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
10840 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
10841 #define RTC_TSTR_HU_Pos (16U)
10842 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
10843 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
10844 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
10845 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
10846 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
10847 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
10848 #define RTC_TSTR_MNT_Pos (12U)
10849 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
10850 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10851 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
10852 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
10853 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
10854 #define RTC_TSTR_MNU_Pos (8U)
10855 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
10856 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10857 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
10858 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
10859 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
10860 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
10861 #define RTC_TSTR_ST_Pos (4U)
10862 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
10863 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
10864 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
10865 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
10866 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
10867 #define RTC_TSTR_SU_Pos (0U)
10868 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
10869 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
10870 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
10871 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
10872 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
10873 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
10874
10875 /******************** Bits definition for RTC_TSDR register *****************/
10876 #define RTC_TSDR_WDU_Pos (13U)
10877 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
10878 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10879 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
10880 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
10881 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
10882 #define RTC_TSDR_MT_Pos (12U)
10883 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
10884 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
10885 #define RTC_TSDR_MU_Pos (8U)
10886 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
10887 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
10888 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
10889 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
10890 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
10891 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
10892 #define RTC_TSDR_DT_Pos (4U)
10893 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
10894 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
10895 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
10896 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
10897 #define RTC_TSDR_DU_Pos (0U)
10898 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
10899 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
10900 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
10901 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
10902 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
10903 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
10904
10905 /******************** Bits definition for RTC_TSSSR register ****************/
10906 #define RTC_TSSSR_SS_Pos (0U)
10907 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
10908 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10909
10910 /******************** Bits definition for RTC_CAL register *****************/
10911 #define RTC_CALR_CALP_Pos (15U)
10912 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
10913 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
10914 #define RTC_CALR_CALW8_Pos (14U)
10915 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
10916 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10917 #define RTC_CALR_CALW16_Pos (13U)
10918 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
10919 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10920 #define RTC_CALR_CALM_Pos (0U)
10921 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
10922 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
10923 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
10924 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
10925 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
10926 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
10927 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
10928 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
10929 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
10930 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
10931 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
10932
10933 /******************** Bits definition for RTC_TAFCR register ****************/
10934 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
10935 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
10936 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
10937 #define RTC_TAFCR_TSINSEL_Pos (17U)
10938 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
10939 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
10940 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
10941 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
10942 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
10943 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
10944 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
10945 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
10946 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
10947 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
10948 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
10949 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
10950 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
10951 #define RTC_TAFCR_TAMPFLT_Pos (11U)
10952 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
10953 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
10954 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
10955 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
10956 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
10957 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
10958 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
10959 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
10960 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
10961 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
10962 #define RTC_TAFCR_TAMPTS_Pos (7U)
10963 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
10964 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
10965 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
10966 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
10967 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
10968 #define RTC_TAFCR_TAMP2E_Pos (3U)
10969 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
10970 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
10971 #define RTC_TAFCR_TAMPIE_Pos (2U)
10972 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
10973 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
10974 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
10975 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
10976 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
10977 #define RTC_TAFCR_TAMP1E_Pos (0U)
10978 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
10979 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
10980
10981 /* Legacy defines */
10982 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
10983
10984 /******************** Bits definition for RTC_ALRMASSR register *************/
10985 #define RTC_ALRMASSR_MASKSS_Pos (24U)
10986 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
10987 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10988 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
10989 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
10990 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
10991 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
10992 #define RTC_ALRMASSR_SS_Pos (0U)
10993 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
10994 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10995
10996 /******************** Bits definition for RTC_ALRMBSSR register *************/
10997 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
10998 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
10999 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
11000 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
11001 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
11002 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
11003 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
11004 #define RTC_ALRMBSSR_SS_Pos (0U)
11005 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
11006 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
11007
11008 /******************** Bits definition for RTC_BKP0R register ****************/
11009 #define RTC_BKP0R_Pos (0U)
11010 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
11011 #define RTC_BKP0R RTC_BKP0R_Msk
11012
11013 /******************** Bits definition for RTC_BKP1R register ****************/
11014 #define RTC_BKP1R_Pos (0U)
11015 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
11016 #define RTC_BKP1R RTC_BKP1R_Msk
11017
11018 /******************** Bits definition for RTC_BKP2R register ****************/
11019 #define RTC_BKP2R_Pos (0U)
11020 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
11021 #define RTC_BKP2R RTC_BKP2R_Msk
11022
11023 /******************** Bits definition for RTC_BKP3R register ****************/
11024 #define RTC_BKP3R_Pos (0U)
11025 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
11026 #define RTC_BKP3R RTC_BKP3R_Msk
11027
11028 /******************** Bits definition for RTC_BKP4R register ****************/
11029 #define RTC_BKP4R_Pos (0U)
11030 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
11031 #define RTC_BKP4R RTC_BKP4R_Msk
11032
11033 /******************** Bits definition for RTC_BKP5R register ****************/
11034 #define RTC_BKP5R_Pos (0U)
11035 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
11036 #define RTC_BKP5R RTC_BKP5R_Msk
11037
11038 /******************** Bits definition for RTC_BKP6R register ****************/
11039 #define RTC_BKP6R_Pos (0U)
11040 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
11041 #define RTC_BKP6R RTC_BKP6R_Msk
11042
11043 /******************** Bits definition for RTC_BKP7R register ****************/
11044 #define RTC_BKP7R_Pos (0U)
11045 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
11046 #define RTC_BKP7R RTC_BKP7R_Msk
11047
11048 /******************** Bits definition for RTC_BKP8R register ****************/
11049 #define RTC_BKP8R_Pos (0U)
11050 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
11051 #define RTC_BKP8R RTC_BKP8R_Msk
11052
11053 /******************** Bits definition for RTC_BKP9R register ****************/
11054 #define RTC_BKP9R_Pos (0U)
11055 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
11056 #define RTC_BKP9R RTC_BKP9R_Msk
11057
11058 /******************** Bits definition for RTC_BKP10R register ***************/
11059 #define RTC_BKP10R_Pos (0U)
11060 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
11061 #define RTC_BKP10R RTC_BKP10R_Msk
11062
11063 /******************** Bits definition for RTC_BKP11R register ***************/
11064 #define RTC_BKP11R_Pos (0U)
11065 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
11066 #define RTC_BKP11R RTC_BKP11R_Msk
11067
11068 /******************** Bits definition for RTC_BKP12R register ***************/
11069 #define RTC_BKP12R_Pos (0U)
11070 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
11071 #define RTC_BKP12R RTC_BKP12R_Msk
11072
11073 /******************** Bits definition for RTC_BKP13R register ***************/
11074 #define RTC_BKP13R_Pos (0U)
11075 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
11076 #define RTC_BKP13R RTC_BKP13R_Msk
11077
11078 /******************** Bits definition for RTC_BKP14R register ***************/
11079 #define RTC_BKP14R_Pos (0U)
11080 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
11081 #define RTC_BKP14R RTC_BKP14R_Msk
11082
11083 /******************** Bits definition for RTC_BKP15R register ***************/
11084 #define RTC_BKP15R_Pos (0U)
11085 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
11086 #define RTC_BKP15R RTC_BKP15R_Msk
11087
11088 /******************** Bits definition for RTC_BKP16R register ***************/
11089 #define RTC_BKP16R_Pos (0U)
11090 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
11091 #define RTC_BKP16R RTC_BKP16R_Msk
11092
11093 /******************** Bits definition for RTC_BKP17R register ***************/
11094 #define RTC_BKP17R_Pos (0U)
11095 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
11096 #define RTC_BKP17R RTC_BKP17R_Msk
11097
11098 /******************** Bits definition for RTC_BKP18R register ***************/
11099 #define RTC_BKP18R_Pos (0U)
11100 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
11101 #define RTC_BKP18R RTC_BKP18R_Msk
11102
11103 /******************** Bits definition for RTC_BKP19R register ***************/
11104 #define RTC_BKP19R_Pos (0U)
11105 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
11106 #define RTC_BKP19R RTC_BKP19R_Msk
11107
11108 /******************** Number of backup registers ******************************/
11109 #define RTC_BKP_NUMBER 0x000000014U
11110
11111 /******************************************************************************/
11112 /* */
11113 /* Serial Audio Interface */
11114 /* */
11115 /******************************************************************************/
11116 /******************** Bit definition for SAI_GCR register *******************/
11117 #define SAI_GCR_SYNCIN_Pos (0U)
11118 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
11119 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
11120 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
11121 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
11122
11123 #define SAI_GCR_SYNCOUT_Pos (4U)
11124 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
11125 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
11126 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
11127 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
11128
11129 /******************* Bit definition for SAI_xCR1 register *******************/
11130 #define SAI_xCR1_MODE_Pos (0U)
11131 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
11132 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
11133 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
11134 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
11135
11136 #define SAI_xCR1_PRTCFG_Pos (2U)
11137 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
11138 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
11139 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
11140 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
11141
11142 #define SAI_xCR1_DS_Pos (5U)
11143 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
11144 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
11145 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
11146 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
11147 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
11148
11149 #define SAI_xCR1_LSBFIRST_Pos (8U)
11150 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
11151 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
11152 #define SAI_xCR1_CKSTR_Pos (9U)
11153 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
11154 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
11155
11156 #define SAI_xCR1_SYNCEN_Pos (10U)
11157 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
11158 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
11159 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
11160 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
11161
11162 #define SAI_xCR1_MONO_Pos (12U)
11163 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
11164 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
11165 #define SAI_xCR1_OUTDRIV_Pos (13U)
11166 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
11167 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
11168 #define SAI_xCR1_SAIEN_Pos (16U)
11169 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
11170 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
11171 #define SAI_xCR1_DMAEN_Pos (17U)
11172 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
11173 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
11174 #define SAI_xCR1_NODIV_Pos (19U)
11175 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
11176 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
11177
11178 #define SAI_xCR1_MCKDIV_Pos (20U)
11179 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
11180 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
11181 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
11182 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
11183 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
11184 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
11185
11186 /******************* Bit definition for SAI_xCR2 register *******************/
11187 #define SAI_xCR2_FTH_Pos (0U)
11188 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
11189 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
11190 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
11191 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
11192 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
11193
11194 #define SAI_xCR2_FFLUSH_Pos (3U)
11195 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
11196 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
11197 #define SAI_xCR2_TRIS_Pos (4U)
11198 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
11199 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
11200 #define SAI_xCR2_MUTE_Pos (5U)
11201 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
11202 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
11203 #define SAI_xCR2_MUTEVAL_Pos (6U)
11204 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
11205 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
11206
11207 #define SAI_xCR2_MUTECNT_Pos (7U)
11208 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
11209 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
11210 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
11211 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
11212 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
11213 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
11214 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
11215 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
11216
11217 #define SAI_xCR2_CPL_Pos (13U)
11218 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
11219 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
11220
11221 #define SAI_xCR2_COMP_Pos (14U)
11222 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
11223 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
11224 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
11225 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
11226
11227 /****************** Bit definition for SAI_xFRCR register *******************/
11228 #define SAI_xFRCR_FRL_Pos (0U)
11229 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
11230 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
11231 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
11232 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
11233 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
11234 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
11235 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
11236 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
11237 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
11238 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
11239
11240 #define SAI_xFRCR_FSALL_Pos (8U)
11241 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
11242 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
11243 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
11244 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
11245 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
11246 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
11247 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
11248 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
11249 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
11250
11251 #define SAI_xFRCR_FSDEF_Pos (16U)
11252 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
11253 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
11254 #define SAI_xFRCR_FSPOL_Pos (17U)
11255 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
11256 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
11257 #define SAI_xFRCR_FSOFF_Pos (18U)
11258 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
11259 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
11260 /* Legacy defines */
11261 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
11262
11263 /****************** Bit definition for SAI_xSLOTR register *******************/
11264 #define SAI_xSLOTR_FBOFF_Pos (0U)
11265 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
11266 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
11267 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
11268 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
11269 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
11270 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
11271 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
11272
11273 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
11274 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
11275 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
11276 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
11277 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
11278
11279 #define SAI_xSLOTR_NBSLOT_Pos (8U)
11280 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
11281 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
11282 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
11283 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
11284 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
11285 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
11286
11287 #define SAI_xSLOTR_SLOTEN_Pos (16U)
11288 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
11289 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
11290
11291 /******************* Bit definition for SAI_xIMR register *******************/
11292 #define SAI_xIMR_OVRUDRIE_Pos (0U)
11293 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
11294 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
11295 #define SAI_xIMR_MUTEDETIE_Pos (1U)
11296 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
11297 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
11298 #define SAI_xIMR_WCKCFGIE_Pos (2U)
11299 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
11300 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
11301 #define SAI_xIMR_FREQIE_Pos (3U)
11302 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
11303 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
11304 #define SAI_xIMR_CNRDYIE_Pos (4U)
11305 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
11306 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
11307 #define SAI_xIMR_AFSDETIE_Pos (5U)
11308 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
11309 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
11310 #define SAI_xIMR_LFSDETIE_Pos (6U)
11311 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
11312 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
11313
11314 /******************** Bit definition for SAI_xSR register *******************/
11315 #define SAI_xSR_OVRUDR_Pos (0U)
11316 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
11317 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
11318 #define SAI_xSR_MUTEDET_Pos (1U)
11319 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
11320 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
11321 #define SAI_xSR_WCKCFG_Pos (2U)
11322 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
11323 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
11324 #define SAI_xSR_FREQ_Pos (3U)
11325 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
11326 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
11327 #define SAI_xSR_CNRDY_Pos (4U)
11328 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
11329 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
11330 #define SAI_xSR_AFSDET_Pos (5U)
11331 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
11332 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
11333 #define SAI_xSR_LFSDET_Pos (6U)
11334 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
11335 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
11336
11337 #define SAI_xSR_FLVL_Pos (16U)
11338 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
11339 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
11340 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
11341 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
11342 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
11343
11344 /****************** Bit definition for SAI_xCLRFR register ******************/
11345 #define SAI_xCLRFR_COVRUDR_Pos (0U)
11346 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
11347 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
11348 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
11349 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
11350 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
11351 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
11352 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
11353 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
11354 #define SAI_xCLRFR_CFREQ_Pos (3U)
11355 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
11356 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
11357 #define SAI_xCLRFR_CCNRDY_Pos (4U)
11358 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
11359 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
11360 #define SAI_xCLRFR_CAFSDET_Pos (5U)
11361 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
11362 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
11363 #define SAI_xCLRFR_CLFSDET_Pos (6U)
11364 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
11365 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
11366
11367 /****************** Bit definition for SAI_xDR register ******************/
11368 #define SAI_xDR_DATA_Pos (0U)
11369 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
11370 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
11371
11372
11373 /******************************************************************************/
11374 /* */
11375 /* SD host Interface */
11376 /* */
11377 /******************************************************************************/
11378 /****************** Bit definition for SDIO_POWER register ******************/
11379 #define SDIO_POWER_PWRCTRL_Pos (0U)
11380 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
11381 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
11382 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
11383 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
11384
11385 /****************** Bit definition for SDIO_CLKCR register ******************/
11386 #define SDIO_CLKCR_CLKDIV_Pos (0U)
11387 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
11388 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
11389 #define SDIO_CLKCR_CLKEN_Pos (8U)
11390 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
11391 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
11392 #define SDIO_CLKCR_PWRSAV_Pos (9U)
11393 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
11394 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
11395 #define SDIO_CLKCR_BYPASS_Pos (10U)
11396 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
11397 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
11398
11399 #define SDIO_CLKCR_WIDBUS_Pos (11U)
11400 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
11401 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
11402 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
11403 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
11404
11405 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
11406 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
11407 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
11408 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
11409 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
11410 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
11411
11412 /******************* Bit definition for SDIO_ARG register *******************/
11413 #define SDIO_ARG_CMDARG_Pos (0U)
11414 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
11415 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
11416
11417 /******************* Bit definition for SDIO_CMD register *******************/
11418 #define SDIO_CMD_CMDINDEX_Pos (0U)
11419 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
11420 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
11421
11422 #define SDIO_CMD_WAITRESP_Pos (6U)
11423 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
11424 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
11425 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
11426 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
11427
11428 #define SDIO_CMD_WAITINT_Pos (8U)
11429 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
11430 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
11431 #define SDIO_CMD_WAITPEND_Pos (9U)
11432 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
11433 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
11434 #define SDIO_CMD_CPSMEN_Pos (10U)
11435 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
11436 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
11437 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
11438 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
11439 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
11440
11441 /***************** Bit definition for SDIO_RESPCMD register *****************/
11442 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
11443 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
11444 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
11445
11446 /****************** Bit definition for SDIO_RESP0 register ******************/
11447 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
11448 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
11449 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
11450
11451 /****************** Bit definition for SDIO_RESP1 register ******************/
11452 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
11453 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
11454 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
11455
11456 /****************** Bit definition for SDIO_RESP2 register ******************/
11457 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
11458 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
11459 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
11460
11461 /****************** Bit definition for SDIO_RESP3 register ******************/
11462 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
11463 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
11464 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
11465
11466 /****************** Bit definition for SDIO_RESP4 register ******************/
11467 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
11468 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
11469 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
11470
11471 /****************** Bit definition for SDIO_DTIMER register *****************/
11472 #define SDIO_DTIMER_DATATIME_Pos (0U)
11473 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
11474 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
11475
11476 /****************** Bit definition for SDIO_DLEN register *******************/
11477 #define SDIO_DLEN_DATALENGTH_Pos (0U)
11478 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
11479 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
11480
11481 /****************** Bit definition for SDIO_DCTRL register ******************/
11482 #define SDIO_DCTRL_DTEN_Pos (0U)
11483 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
11484 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
11485 #define SDIO_DCTRL_DTDIR_Pos (1U)
11486 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
11487 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
11488 #define SDIO_DCTRL_DTMODE_Pos (2U)
11489 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
11490 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
11491 #define SDIO_DCTRL_DMAEN_Pos (3U)
11492 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
11493 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
11494
11495 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
11496 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
11497 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
11498 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
11499 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
11500 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
11501 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
11502
11503 #define SDIO_DCTRL_RWSTART_Pos (8U)
11504 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
11505 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
11506 #define SDIO_DCTRL_RWSTOP_Pos (9U)
11507 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
11508 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
11509 #define SDIO_DCTRL_RWMOD_Pos (10U)
11510 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
11511 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
11512 #define SDIO_DCTRL_SDIOEN_Pos (11U)
11513 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
11514 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
11515
11516 /****************** Bit definition for SDIO_DCOUNT register *****************/
11517 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
11518 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
11519 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
11520
11521 /****************** Bit definition for SDIO_STA register ********************/
11522 #define SDIO_STA_CCRCFAIL_Pos (0U)
11523 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
11524 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
11525 #define SDIO_STA_DCRCFAIL_Pos (1U)
11526 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
11527 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
11528 #define SDIO_STA_CTIMEOUT_Pos (2U)
11529 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
11530 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
11531 #define SDIO_STA_DTIMEOUT_Pos (3U)
11532 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
11533 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
11534 #define SDIO_STA_TXUNDERR_Pos (4U)
11535 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
11536 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
11537 #define SDIO_STA_RXOVERR_Pos (5U)
11538 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
11539 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
11540 #define SDIO_STA_CMDREND_Pos (6U)
11541 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
11542 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
11543 #define SDIO_STA_CMDSENT_Pos (7U)
11544 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
11545 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
11546 #define SDIO_STA_DATAEND_Pos (8U)
11547 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
11548 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
11549 #define SDIO_STA_DBCKEND_Pos (10U)
11550 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
11551 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
11552 #define SDIO_STA_CMDACT_Pos (11U)
11553 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
11554 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
11555 #define SDIO_STA_TXACT_Pos (12U)
11556 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
11557 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
11558 #define SDIO_STA_RXACT_Pos (13U)
11559 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
11560 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
11561 #define SDIO_STA_TXFIFOHE_Pos (14U)
11562 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
11563 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
11564 #define SDIO_STA_RXFIFOHF_Pos (15U)
11565 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
11566 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
11567 #define SDIO_STA_TXFIFOF_Pos (16U)
11568 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
11569 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
11570 #define SDIO_STA_RXFIFOF_Pos (17U)
11571 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
11572 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
11573 #define SDIO_STA_TXFIFOE_Pos (18U)
11574 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
11575 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
11576 #define SDIO_STA_RXFIFOE_Pos (19U)
11577 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
11578 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
11579 #define SDIO_STA_TXDAVL_Pos (20U)
11580 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
11581 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
11582 #define SDIO_STA_RXDAVL_Pos (21U)
11583 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
11584 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
11585 #define SDIO_STA_SDIOIT_Pos (22U)
11586 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
11587 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
11588
11589 /******************* Bit definition for SDIO_ICR register *******************/
11590 #define SDIO_ICR_CCRCFAILC_Pos (0U)
11591 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
11592 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
11593 #define SDIO_ICR_DCRCFAILC_Pos (1U)
11594 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11595 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
11596 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
11597 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
11598 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
11599 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
11600 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
11601 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
11602 #define SDIO_ICR_TXUNDERRC_Pos (4U)
11603 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
11604 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
11605 #define SDIO_ICR_RXOVERRC_Pos (5U)
11606 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
11607 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
11608 #define SDIO_ICR_CMDRENDC_Pos (6U)
11609 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
11610 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
11611 #define SDIO_ICR_CMDSENTC_Pos (7U)
11612 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
11613 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
11614 #define SDIO_ICR_DATAENDC_Pos (8U)
11615 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
11616 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
11617 #define SDIO_ICR_DBCKENDC_Pos (10U)
11618 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
11619 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
11620 #define SDIO_ICR_SDIOITC_Pos (22U)
11621 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
11622 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
11623
11624 /****************** Bit definition for SDIO_MASK register *******************/
11625 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
11626 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
11627 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
11628 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
11629 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
11630 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
11631 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
11632 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
11633 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
11634 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
11635 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
11636 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
11637 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
11638 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
11639 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
11640 #define SDIO_MASK_RXOVERRIE_Pos (5U)
11641 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
11642 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
11643 #define SDIO_MASK_CMDRENDIE_Pos (6U)
11644 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
11645 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
11646 #define SDIO_MASK_CMDSENTIE_Pos (7U)
11647 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
11648 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
11649 #define SDIO_MASK_DATAENDIE_Pos (8U)
11650 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
11651 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
11652 #define SDIO_MASK_DBCKENDIE_Pos (10U)
11653 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
11654 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
11655 #define SDIO_MASK_CMDACTIE_Pos (11U)
11656 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
11657 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
11658 #define SDIO_MASK_TXACTIE_Pos (12U)
11659 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
11660 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
11661 #define SDIO_MASK_RXACTIE_Pos (13U)
11662 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
11663 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
11664 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
11665 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
11666 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
11667 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
11668 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
11669 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
11670 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
11671 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
11672 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
11673 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
11674 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
11675 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
11676 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
11677 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
11678 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
11679 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
11680 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
11681 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
11682 #define SDIO_MASK_TXDAVLIE_Pos (20U)
11683 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
11684 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
11685 #define SDIO_MASK_RXDAVLIE_Pos (21U)
11686 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
11687 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
11688 #define SDIO_MASK_SDIOITIE_Pos (22U)
11689 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
11690 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
11691
11692 /***************** Bit definition for SDIO_FIFOCNT register *****************/
11693 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
11694 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
11695 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
11696
11697 /****************** Bit definition for SDIO_FIFO register *******************/
11698 #define SDIO_FIFO_FIFODATA_Pos (0U)
11699 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
11700 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
11701
11702 /******************************************************************************/
11703 /* */
11704 /* Serial Peripheral Interface */
11705 /* */
11706 /******************************************************************************/
11707 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
11708 #define I2S_APB1_APB2_FEATURE /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
11709
11710 /******************* Bit definition for SPI_CR1 register ********************/
11711 #define SPI_CR1_CPHA_Pos (0U)
11712 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
11713 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
11714 #define SPI_CR1_CPOL_Pos (1U)
11715 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
11716 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
11717 #define SPI_CR1_MSTR_Pos (2U)
11718 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
11719 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
11720
11721 #define SPI_CR1_BR_Pos (3U)
11722 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
11723 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
11724 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
11725 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
11726 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
11727
11728 #define SPI_CR1_SPE_Pos (6U)
11729 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
11730 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
11731 #define SPI_CR1_LSBFIRST_Pos (7U)
11732 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
11733 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
11734 #define SPI_CR1_SSI_Pos (8U)
11735 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
11736 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
11737 #define SPI_CR1_SSM_Pos (9U)
11738 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
11739 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
11740 #define SPI_CR1_RXONLY_Pos (10U)
11741 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
11742 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
11743 #define SPI_CR1_DFF_Pos (11U)
11744 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
11745 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
11746 #define SPI_CR1_CRCNEXT_Pos (12U)
11747 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
11748 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
11749 #define SPI_CR1_CRCEN_Pos (13U)
11750 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
11751 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
11752 #define SPI_CR1_BIDIOE_Pos (14U)
11753 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
11754 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
11755 #define SPI_CR1_BIDIMODE_Pos (15U)
11756 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
11757 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
11758
11759 /******************* Bit definition for SPI_CR2 register ********************/
11760 #define SPI_CR2_RXDMAEN_Pos (0U)
11761 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
11762 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
11763 #define SPI_CR2_TXDMAEN_Pos (1U)
11764 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
11765 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
11766 #define SPI_CR2_SSOE_Pos (2U)
11767 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
11768 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
11769 #define SPI_CR2_FRF_Pos (4U)
11770 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
11771 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
11772 #define SPI_CR2_ERRIE_Pos (5U)
11773 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
11774 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
11775 #define SPI_CR2_RXNEIE_Pos (6U)
11776 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
11777 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
11778 #define SPI_CR2_TXEIE_Pos (7U)
11779 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
11780 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
11781
11782 /******************** Bit definition for SPI_SR register ********************/
11783 #define SPI_SR_RXNE_Pos (0U)
11784 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
11785 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
11786 #define SPI_SR_TXE_Pos (1U)
11787 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
11788 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
11789 #define SPI_SR_CHSIDE_Pos (2U)
11790 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
11791 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
11792 #define SPI_SR_UDR_Pos (3U)
11793 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
11794 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
11795 #define SPI_SR_CRCERR_Pos (4U)
11796 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
11797 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
11798 #define SPI_SR_MODF_Pos (5U)
11799 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
11800 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
11801 #define SPI_SR_OVR_Pos (6U)
11802 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
11803 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
11804 #define SPI_SR_BSY_Pos (7U)
11805 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
11806 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
11807 #define SPI_SR_FRE_Pos (8U)
11808 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
11809 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
11810
11811 /******************** Bit definition for SPI_DR register ********************/
11812 #define SPI_DR_DR_Pos (0U)
11813 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
11814 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
11815
11816 /******************* Bit definition for SPI_CRCPR register ******************/
11817 #define SPI_CRCPR_CRCPOLY_Pos (0U)
11818 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
11819 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
11820
11821 /****************** Bit definition for SPI_RXCRCR register ******************/
11822 #define SPI_RXCRCR_RXCRC_Pos (0U)
11823 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
11824 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
11825
11826 /****************** Bit definition for SPI_TXCRCR register ******************/
11827 #define SPI_TXCRCR_TXCRC_Pos (0U)
11828 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
11829 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
11830
11831 /****************** Bit definition for SPI_I2SCFGR register *****************/
11832 #define SPI_I2SCFGR_CHLEN_Pos (0U)
11833 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
11834 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
11835
11836 #define SPI_I2SCFGR_DATLEN_Pos (1U)
11837 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
11838 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
11839 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
11840 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
11841
11842 #define SPI_I2SCFGR_CKPOL_Pos (3U)
11843 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
11844 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
11845
11846 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
11847 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
11848 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
11849 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
11850 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
11851
11852 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11853 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
11854 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
11855
11856 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
11857 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
11858 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
11859 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
11860 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
11861
11862 #define SPI_I2SCFGR_I2SE_Pos (10U)
11863 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
11864 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
11865 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
11866 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
11867 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
11868 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
11869 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
11870 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
11871
11872 /****************** Bit definition for SPI_I2SPR register *******************/
11873 #define SPI_I2SPR_I2SDIV_Pos (0U)
11874 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
11875 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
11876 #define SPI_I2SPR_ODD_Pos (8U)
11877 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
11878 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
11879 #define SPI_I2SPR_MCKOE_Pos (9U)
11880 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
11881 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
11882
11883 /******************************************************************************/
11884 /* */
11885 /* SYSCFG */
11886 /* */
11887 /******************************************************************************/
11888 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
11889 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11890 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
11891 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
11892 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
11893 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
11894 /****************** Bit definition for SYSCFG_PMC register ******************/
11895 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
11896 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
11897 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
11898
11899 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
11900 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11901 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
11902 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
11903 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11904 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
11905 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
11906 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11907 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
11908 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
11909 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11910 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
11911 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
11912 /**
11913 * @brief EXTI0 configuration
11914 */
11915 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
11916 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
11917 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
11918 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
11919 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
11920 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
11921 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
11922 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
11923
11924 /**
11925 * @brief EXTI1 configuration
11926 */
11927 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
11928 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
11929 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
11930 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
11931 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
11932 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
11933 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
11934 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
11935
11936 /**
11937 * @brief EXTI2 configuration
11938 */
11939 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
11940 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
11941 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
11942 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
11943 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
11944 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
11945 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
11946 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
11947
11948 /**
11949 * @brief EXTI3 configuration
11950 */
11951 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
11952 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
11953 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
11954 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
11955 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
11956 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
11957 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
11958 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
11959
11960 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
11961 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11962 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
11963 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
11964 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11965 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
11966 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
11967 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11968 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
11969 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
11970 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11971 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
11972 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
11973
11974 /**
11975 * @brief EXTI4 configuration
11976 */
11977 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
11978 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
11979 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
11980 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
11981 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
11982 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
11983 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
11984 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
11985
11986 /**
11987 * @brief EXTI5 configuration
11988 */
11989 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
11990 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
11991 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
11992 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
11993 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
11994 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
11995 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
11996 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
11997
11998 /**
11999 * @brief EXTI6 configuration
12000 */
12001 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
12002 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
12003 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
12004 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
12005 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
12006 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
12007 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
12008 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
12009
12010 /**
12011 * @brief EXTI7 configuration
12012 */
12013 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
12014 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
12015 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
12016 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
12017 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
12018 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
12019 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
12020 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
12021
12022 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
12023 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
12024 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
12025 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
12026 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
12027 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
12028 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
12029 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
12030 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
12031 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
12032 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12033 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
12034 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
12035
12036 /**
12037 * @brief EXTI8 configuration
12038 */
12039 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
12040 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
12041 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
12042 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
12043 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
12044 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
12045 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
12046 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
12047
12048 /**
12049 * @brief EXTI9 configuration
12050 */
12051 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
12052 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
12053 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
12054 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
12055 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
12056 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
12057 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
12058 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
12059
12060 /**
12061 * @brief EXTI10 configuration
12062 */
12063 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
12064 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
12065 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
12066 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
12067 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
12068 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
12069 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
12070 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
12071
12072 /**
12073 * @brief EXTI11 configuration
12074 */
12075 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
12076 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
12077 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
12078 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
12079 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
12080 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
12081 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
12082 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
12083
12084 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
12085 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
12086 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
12087 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
12088 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
12089 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
12090 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
12091 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
12092 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
12093 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
12094 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
12095 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
12096 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
12097
12098 /**
12099 * @brief EXTI12 configuration
12100 */
12101 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
12102 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
12103 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
12104 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
12105 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
12106 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
12107 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
12108 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
12109
12110 /**
12111 * @brief EXTI13 configuration
12112 */
12113 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
12114 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
12115 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
12116 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
12117 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
12118 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
12119 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
12120 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
12121
12122 /**
12123 * @brief EXTI14 configuration
12124 */
12125 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
12126 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
12127 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
12128 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
12129 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
12130 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
12131 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
12132 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
12133
12134 /**
12135 * @brief EXTI15 configuration
12136 */
12137 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
12138 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
12139 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
12140 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
12141 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
12142 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
12143 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
12144 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
12145
12146 /****************** Bit definition for SYSCFG_CMPCR register ****************/
12147 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
12148 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
12149 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
12150 #define SYSCFG_CMPCR_READY_Pos (8U)
12151 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
12152 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
12153 /****************** Bit definition for SYSCFG_CFGR register *****************/
12154 #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
12155 #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
12156 #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
12157 #define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
12158 #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
12159 #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
12160
12161 /****************** Bit definition for SYSCFG_CFGR2 register *****************/
12162 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
12163 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
12164 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */
12165 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
12166 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
12167 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */
12168 /****************** Bit definition for SYSCFG_MCHDLYCR register *****************/
12169 #define SYSCFG_MCHDLYCR_BSCKSEL_Pos (0U)
12170 #define SYSCFG_MCHDLYCR_BSCKSEL_Msk (0x1U << SYSCFG_MCHDLYCR_BSCKSEL_Pos) /*!< 0x00000001 */
12171 #define SYSCFG_MCHDLYCR_BSCKSEL SYSCFG_MCHDLYCR_BSCKSEL_Msk /*!<Bitstream clock source selection */
12172 #define SYSCFG_MCHDLYCR_MCHDLY1EN_Pos (1U)
12173 #define SYSCFG_MCHDLYCR_MCHDLY1EN_Msk (0x1U << SYSCFG_MCHDLYCR_MCHDLY1EN_Pos) /*!< 0x00000002 */
12174 #define SYSCFG_MCHDLYCR_MCHDLY1EN SYSCFG_MCHDLYCR_MCHDLY1EN_Msk /*!<MCHDLY clock enable for DFSDM1 */
12175 #define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos (2U)
12176 #define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos) /*!< 0x00000004 */
12177 #define SYSCFG_MCHDLYCR_DFSDM1D0SEL SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk /*!<Source selection for DatIn0 for DFSDM1 */
12178 #define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos (3U)
12179 #define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos) /*!< 0x00000008 */
12180 #define SYSCFG_MCHDLYCR_DFSDM1D2SEL SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk /*!<Source selection for DatIn2 for DFSDM1 */
12181 #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos (4U)
12182 #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos) /*!< 0x00000010 */
12183 #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC2 */
12184 #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos (5U)
12185 #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos) /*!< 0x00000020 */
12186 #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC1 */
12187 #define SYSCFG_MCHDLYCR_DFSDM1CFG_Pos (6U)
12188 #define SYSCFG_MCHDLYCR_DFSDM1CFG_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CFG_Pos) /*!< 0x00000040 */
12189 #define SYSCFG_MCHDLYCR_DFSDM1CFG SYSCFG_MCHDLYCR_DFSDM1CFG_Msk /*!<Source selection for DFSDM1 */
12190 #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos (7U)
12191 #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos) /*!< 0x00000080 */
12192 #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk /*!<Source selection for 1_CKOUT */
12193 #define SYSCFG_MCHDLYCR_MCHDLY2EN_Pos (8U)
12194 #define SYSCFG_MCHDLYCR_MCHDLY2EN_Msk (0x1U << SYSCFG_MCHDLYCR_MCHDLY2EN_Pos) /*!< 0x00000100 */
12195 #define SYSCFG_MCHDLYCR_MCHDLY2EN SYSCFG_MCHDLYCR_MCHDLY2EN_Msk /*!<MCHDLY clock enable for DFSDM2 */
12196 #define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos (9U)
12197 #define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos) /*!< 0x00000200 */
12198 #define SYSCFG_MCHDLYCR_DFSDM2D0SEL SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk /*!<Source selection for DatIn0 for DFSDM2 */
12199 #define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos (10U)
12200 #define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos) /*!< 0x00000400 */
12201 #define SYSCFG_MCHDLYCR_DFSDM2D2SEL SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk /*!<Source selection for DatIn2 for DFSDM2 */
12202 #define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos (11U)
12203 #define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos) /*!< 0x00000800 */
12204 #define SYSCFG_MCHDLYCR_DFSDM2D4SEL SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk /*!<Source selection for DatIn4 for DFSDM2 */
12205 #define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos (12U)
12206 #define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos) /*!< 0x00001000 */
12207 #define SYSCFG_MCHDLYCR_DFSDM2D6SEL SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk /*!<Source selection for DatIn6 for DFSDM2 */
12208 #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos (13U)
12209 #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos) /*!< 0x00002000 */
12210 #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC4 */
12211 #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos (14U)
12212 #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos) /*!< 0x00004000 */
12213 #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC3 */
12214 #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos (15U)
12215 #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos) /*!< 0x00008000 */
12216 #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk /*!Distribution of the bitstreamclock gated by TIM3 OC2 */
12217 #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos (16U)
12218 #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos) /*!< 0x00010000 */
12219 #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC1 */
12220 #define SYSCFG_MCHDLYCR_DFSDM2CFG_Pos (17U)
12221 #define SYSCFG_MCHDLYCR_DFSDM2CFG_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CFG_Pos) /*!< 0x00020000 */
12222 #define SYSCFG_MCHDLYCR_DFSDM2CFG SYSCFG_MCHDLYCR_DFSDM2CFG_Msk /*!<Source selection for DFSDM2 */
12223 #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos (18U)
12224 #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos) /*!< 0x00040000 */
12225 #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk /*!<Source selection for 2_CKOUT */
12226
12227 /******************************************************************************/
12228 /* */
12229 /* TIM */
12230 /* */
12231 /******************************************************************************/
12232 /******************* Bit definition for TIM_CR1 register ********************/
12233 #define TIM_CR1_CEN_Pos (0U)
12234 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
12235 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
12236 #define TIM_CR1_UDIS_Pos (1U)
12237 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
12238 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
12239 #define TIM_CR1_URS_Pos (2U)
12240 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
12241 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
12242 #define TIM_CR1_OPM_Pos (3U)
12243 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
12244 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
12245 #define TIM_CR1_DIR_Pos (4U)
12246 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
12247 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
12248
12249 #define TIM_CR1_CMS_Pos (5U)
12250 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
12251 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
12252 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
12253 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
12254
12255 #define TIM_CR1_ARPE_Pos (7U)
12256 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
12257 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
12258
12259 #define TIM_CR1_CKD_Pos (8U)
12260 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
12261 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
12262 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
12263 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
12264
12265 /******************* Bit definition for TIM_CR2 register ********************/
12266 #define TIM_CR2_CCPC_Pos (0U)
12267 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
12268 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
12269 #define TIM_CR2_CCUS_Pos (2U)
12270 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
12271 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
12272 #define TIM_CR2_CCDS_Pos (3U)
12273 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
12274 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
12275
12276 #define TIM_CR2_MMS_Pos (4U)
12277 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
12278 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
12279 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
12280 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
12281 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
12282
12283 #define TIM_CR2_TI1S_Pos (7U)
12284 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
12285 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
12286 #define TIM_CR2_OIS1_Pos (8U)
12287 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
12288 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
12289 #define TIM_CR2_OIS1N_Pos (9U)
12290 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
12291 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
12292 #define TIM_CR2_OIS2_Pos (10U)
12293 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
12294 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
12295 #define TIM_CR2_OIS2N_Pos (11U)
12296 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
12297 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
12298 #define TIM_CR2_OIS3_Pos (12U)
12299 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
12300 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
12301 #define TIM_CR2_OIS3N_Pos (13U)
12302 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
12303 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
12304 #define TIM_CR2_OIS4_Pos (14U)
12305 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
12306 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
12307
12308 /******************* Bit definition for TIM_SMCR register *******************/
12309 #define TIM_SMCR_SMS_Pos (0U)
12310 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
12311 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
12312 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
12313 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
12314 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
12315
12316 #define TIM_SMCR_TS_Pos (4U)
12317 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
12318 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
12319 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
12320 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
12321 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
12322
12323 #define TIM_SMCR_MSM_Pos (7U)
12324 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
12325 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
12326
12327 #define TIM_SMCR_ETF_Pos (8U)
12328 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
12329 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
12330 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
12331 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
12332 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
12333 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
12334
12335 #define TIM_SMCR_ETPS_Pos (12U)
12336 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
12337 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
12338 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
12339 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
12340
12341 #define TIM_SMCR_ECE_Pos (14U)
12342 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
12343 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
12344 #define TIM_SMCR_ETP_Pos (15U)
12345 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
12346 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
12347
12348 /******************* Bit definition for TIM_DIER register *******************/
12349 #define TIM_DIER_UIE_Pos (0U)
12350 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
12351 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
12352 #define TIM_DIER_CC1IE_Pos (1U)
12353 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
12354 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
12355 #define TIM_DIER_CC2IE_Pos (2U)
12356 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
12357 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
12358 #define TIM_DIER_CC3IE_Pos (3U)
12359 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
12360 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
12361 #define TIM_DIER_CC4IE_Pos (4U)
12362 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
12363 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
12364 #define TIM_DIER_COMIE_Pos (5U)
12365 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
12366 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
12367 #define TIM_DIER_TIE_Pos (6U)
12368 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
12369 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
12370 #define TIM_DIER_BIE_Pos (7U)
12371 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
12372 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
12373 #define TIM_DIER_UDE_Pos (8U)
12374 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
12375 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
12376 #define TIM_DIER_CC1DE_Pos (9U)
12377 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
12378 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
12379 #define TIM_DIER_CC2DE_Pos (10U)
12380 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
12381 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
12382 #define TIM_DIER_CC3DE_Pos (11U)
12383 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
12384 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
12385 #define TIM_DIER_CC4DE_Pos (12U)
12386 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
12387 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
12388 #define TIM_DIER_COMDE_Pos (13U)
12389 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
12390 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
12391 #define TIM_DIER_TDE_Pos (14U)
12392 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
12393 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
12394
12395 /******************** Bit definition for TIM_SR register ********************/
12396 #define TIM_SR_UIF_Pos (0U)
12397 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
12398 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
12399 #define TIM_SR_CC1IF_Pos (1U)
12400 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
12401 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
12402 #define TIM_SR_CC2IF_Pos (2U)
12403 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
12404 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
12405 #define TIM_SR_CC3IF_Pos (3U)
12406 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
12407 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
12408 #define TIM_SR_CC4IF_Pos (4U)
12409 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
12410 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
12411 #define TIM_SR_COMIF_Pos (5U)
12412 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
12413 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
12414 #define TIM_SR_TIF_Pos (6U)
12415 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
12416 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
12417 #define TIM_SR_BIF_Pos (7U)
12418 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
12419 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
12420 #define TIM_SR_CC1OF_Pos (9U)
12421 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
12422 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
12423 #define TIM_SR_CC2OF_Pos (10U)
12424 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
12425 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
12426 #define TIM_SR_CC3OF_Pos (11U)
12427 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
12428 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
12429 #define TIM_SR_CC4OF_Pos (12U)
12430 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
12431 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
12432
12433 /******************* Bit definition for TIM_EGR register ********************/
12434 #define TIM_EGR_UG_Pos (0U)
12435 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
12436 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
12437 #define TIM_EGR_CC1G_Pos (1U)
12438 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
12439 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
12440 #define TIM_EGR_CC2G_Pos (2U)
12441 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
12442 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
12443 #define TIM_EGR_CC3G_Pos (3U)
12444 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
12445 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
12446 #define TIM_EGR_CC4G_Pos (4U)
12447 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
12448 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
12449 #define TIM_EGR_COMG_Pos (5U)
12450 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
12451 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
12452 #define TIM_EGR_TG_Pos (6U)
12453 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
12454 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
12455 #define TIM_EGR_BG_Pos (7U)
12456 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
12457 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
12458
12459 /****************** Bit definition for TIM_CCMR1 register *******************/
12460 #define TIM_CCMR1_CC1S_Pos (0U)
12461 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
12462 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
12463 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
12464 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
12465
12466 #define TIM_CCMR1_OC1FE_Pos (2U)
12467 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
12468 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
12469 #define TIM_CCMR1_OC1PE_Pos (3U)
12470 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
12471 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
12472
12473 #define TIM_CCMR1_OC1M_Pos (4U)
12474 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
12475 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
12476 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
12477 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
12478 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
12479
12480 #define TIM_CCMR1_OC1CE_Pos (7U)
12481 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
12482 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
12483
12484 #define TIM_CCMR1_CC2S_Pos (8U)
12485 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
12486 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
12487 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
12488 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
12489
12490 #define TIM_CCMR1_OC2FE_Pos (10U)
12491 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
12492 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
12493 #define TIM_CCMR1_OC2PE_Pos (11U)
12494 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
12495 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
12496
12497 #define TIM_CCMR1_OC2M_Pos (12U)
12498 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
12499 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
12500 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
12501 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
12502 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
12503
12504 #define TIM_CCMR1_OC2CE_Pos (15U)
12505 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
12506 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
12507
12508 /*----------------------------------------------------------------------------*/
12509
12510 #define TIM_CCMR1_IC1PSC_Pos (2U)
12511 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
12512 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
12513 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
12514 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
12515
12516 #define TIM_CCMR1_IC1F_Pos (4U)
12517 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
12518 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
12519 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
12520 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
12521 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
12522 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
12523
12524 #define TIM_CCMR1_IC2PSC_Pos (10U)
12525 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
12526 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
12527 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
12528 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
12529
12530 #define TIM_CCMR1_IC2F_Pos (12U)
12531 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
12532 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
12533 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
12534 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
12535 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
12536 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
12537
12538 /****************** Bit definition for TIM_CCMR2 register *******************/
12539 #define TIM_CCMR2_CC3S_Pos (0U)
12540 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
12541 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
12542 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
12543 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
12544
12545 #define TIM_CCMR2_OC3FE_Pos (2U)
12546 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
12547 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
12548 #define TIM_CCMR2_OC3PE_Pos (3U)
12549 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
12550 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
12551
12552 #define TIM_CCMR2_OC3M_Pos (4U)
12553 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
12554 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
12555 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
12556 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
12557 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
12558
12559 #define TIM_CCMR2_OC3CE_Pos (7U)
12560 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
12561 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
12562
12563 #define TIM_CCMR2_CC4S_Pos (8U)
12564 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
12565 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
12566 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
12567 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
12568
12569 #define TIM_CCMR2_OC4FE_Pos (10U)
12570 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
12571 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
12572 #define TIM_CCMR2_OC4PE_Pos (11U)
12573 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
12574 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
12575
12576 #define TIM_CCMR2_OC4M_Pos (12U)
12577 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
12578 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
12579 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
12580 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
12581 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
12582
12583 #define TIM_CCMR2_OC4CE_Pos (15U)
12584 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
12585 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
12586
12587 /*----------------------------------------------------------------------------*/
12588
12589 #define TIM_CCMR2_IC3PSC_Pos (2U)
12590 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
12591 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
12592 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
12593 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
12594
12595 #define TIM_CCMR2_IC3F_Pos (4U)
12596 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
12597 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
12598 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
12599 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
12600 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
12601 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
12602
12603 #define TIM_CCMR2_IC4PSC_Pos (10U)
12604 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
12605 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
12606 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
12607 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
12608
12609 #define TIM_CCMR2_IC4F_Pos (12U)
12610 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
12611 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
12612 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
12613 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
12614 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
12615 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
12616
12617 /******************* Bit definition for TIM_CCER register *******************/
12618 #define TIM_CCER_CC1E_Pos (0U)
12619 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
12620 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
12621 #define TIM_CCER_CC1P_Pos (1U)
12622 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
12623 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
12624 #define TIM_CCER_CC1NE_Pos (2U)
12625 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
12626 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
12627 #define TIM_CCER_CC1NP_Pos (3U)
12628 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
12629 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
12630 #define TIM_CCER_CC2E_Pos (4U)
12631 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
12632 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
12633 #define TIM_CCER_CC2P_Pos (5U)
12634 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
12635 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
12636 #define TIM_CCER_CC2NE_Pos (6U)
12637 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
12638 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
12639 #define TIM_CCER_CC2NP_Pos (7U)
12640 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
12641 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
12642 #define TIM_CCER_CC3E_Pos (8U)
12643 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
12644 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
12645 #define TIM_CCER_CC3P_Pos (9U)
12646 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
12647 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
12648 #define TIM_CCER_CC3NE_Pos (10U)
12649 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
12650 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
12651 #define TIM_CCER_CC3NP_Pos (11U)
12652 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
12653 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
12654 #define TIM_CCER_CC4E_Pos (12U)
12655 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
12656 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
12657 #define TIM_CCER_CC4P_Pos (13U)
12658 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
12659 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
12660 #define TIM_CCER_CC4NP_Pos (15U)
12661 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
12662 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
12663
12664 /******************* Bit definition for TIM_CNT register ********************/
12665 #define TIM_CNT_CNT_Pos (0U)
12666 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
12667 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
12668
12669 /******************* Bit definition for TIM_PSC register ********************/
12670 #define TIM_PSC_PSC_Pos (0U)
12671 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
12672 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
12673
12674 /******************* Bit definition for TIM_ARR register ********************/
12675 #define TIM_ARR_ARR_Pos (0U)
12676 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
12677 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
12678
12679 /******************* Bit definition for TIM_RCR register ********************/
12680 #define TIM_RCR_REP_Pos (0U)
12681 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
12682 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
12683
12684 /******************* Bit definition for TIM_CCR1 register *******************/
12685 #define TIM_CCR1_CCR1_Pos (0U)
12686 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
12687 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
12688
12689 /******************* Bit definition for TIM_CCR2 register *******************/
12690 #define TIM_CCR2_CCR2_Pos (0U)
12691 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
12692 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
12693
12694 /******************* Bit definition for TIM_CCR3 register *******************/
12695 #define TIM_CCR3_CCR3_Pos (0U)
12696 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
12697 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
12698
12699 /******************* Bit definition for TIM_CCR4 register *******************/
12700 #define TIM_CCR4_CCR4_Pos (0U)
12701 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
12702 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
12703
12704 /******************* Bit definition for TIM_BDTR register *******************/
12705 #define TIM_BDTR_DTG_Pos (0U)
12706 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
12707 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
12708 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
12709 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
12710 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
12711 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
12712 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
12713 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
12714 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
12715 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
12716
12717 #define TIM_BDTR_LOCK_Pos (8U)
12718 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
12719 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
12720 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
12721 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
12722
12723 #define TIM_BDTR_OSSI_Pos (10U)
12724 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
12725 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
12726 #define TIM_BDTR_OSSR_Pos (11U)
12727 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
12728 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
12729 #define TIM_BDTR_BKE_Pos (12U)
12730 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
12731 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
12732 #define TIM_BDTR_BKP_Pos (13U)
12733 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
12734 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
12735 #define TIM_BDTR_AOE_Pos (14U)
12736 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
12737 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
12738 #define TIM_BDTR_MOE_Pos (15U)
12739 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
12740 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
12741
12742 /******************* Bit definition for TIM_DCR register ********************/
12743 #define TIM_DCR_DBA_Pos (0U)
12744 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
12745 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
12746 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
12747 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
12748 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
12749 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
12750 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
12751
12752 #define TIM_DCR_DBL_Pos (8U)
12753 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
12754 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
12755 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
12756 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
12757 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
12758 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
12759 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
12760
12761 /******************* Bit definition for TIM_DMAR register *******************/
12762 #define TIM_DMAR_DMAB_Pos (0U)
12763 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
12764 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
12765
12766 /******************* Bit definition for TIM_OR register *********************/
12767 #define TIM_OR_TI1_RMP_Pos (0U)
12768 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
12769 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
12770 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
12771 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
12772
12773 #define TIM_OR_TI4_RMP_Pos (6U)
12774 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
12775 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
12776 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
12777 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
12778 #define TIM_OR_ITR1_RMP_Pos (10U)
12779 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
12780 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
12781 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
12782 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
12783
12784 /******************************************************************************/
12785 /* */
12786 /* Low Power Timer (LPTIM) */
12787 /* */
12788 /******************************************************************************/
12789 /****************** Bit definition for LPTIM_ISR register *******************/
12790 #define LPTIM_ISR_CMPM_Pos (0U)
12791 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
12792 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
12793 #define LPTIM_ISR_ARRM_Pos (1U)
12794 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
12795 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
12796 #define LPTIM_ISR_EXTTRIG_Pos (2U)
12797 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
12798 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
12799 #define LPTIM_ISR_CMPOK_Pos (3U)
12800 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
12801 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
12802 #define LPTIM_ISR_ARROK_Pos (4U)
12803 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
12804 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
12805 #define LPTIM_ISR_UP_Pos (5U)
12806 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
12807 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
12808 #define LPTIM_ISR_DOWN_Pos (6U)
12809 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
12810 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
12811
12812 /****************** Bit definition for LPTIM_ICR register *******************/
12813 #define LPTIM_ICR_CMPMCF_Pos (0U)
12814 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
12815 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
12816 #define LPTIM_ICR_ARRMCF_Pos (1U)
12817 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
12818 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
12819 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
12820 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
12821 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
12822 #define LPTIM_ICR_CMPOKCF_Pos (3U)
12823 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
12824 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
12825 #define LPTIM_ICR_ARROKCF_Pos (4U)
12826 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
12827 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
12828 #define LPTIM_ICR_UPCF_Pos (5U)
12829 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
12830 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
12831 #define LPTIM_ICR_DOWNCF_Pos (6U)
12832 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
12833 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
12834
12835 /****************** Bit definition for LPTIM_IER register ********************/
12836 #define LPTIM_IER_CMPMIE_Pos (0U)
12837 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
12838 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
12839 #define LPTIM_IER_ARRMIE_Pos (1U)
12840 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
12841 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
12842 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
12843 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
12844 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
12845 #define LPTIM_IER_CMPOKIE_Pos (3U)
12846 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
12847 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
12848 #define LPTIM_IER_ARROKIE_Pos (4U)
12849 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
12850 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
12851 #define LPTIM_IER_UPIE_Pos (5U)
12852 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
12853 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
12854 #define LPTIM_IER_DOWNIE_Pos (6U)
12855 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
12856 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
12857
12858 /****************** Bit definition for LPTIM_CFGR register *******************/
12859 #define LPTIM_CFGR_CKSEL_Pos (0U)
12860 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
12861 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
12862
12863 #define LPTIM_CFGR_CKPOL_Pos (1U)
12864 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
12865 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
12866 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
12867 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
12868
12869 #define LPTIM_CFGR_CKFLT_Pos (3U)
12870 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
12871 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
12872 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
12873 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
12874
12875 #define LPTIM_CFGR_TRGFLT_Pos (6U)
12876 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
12877 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
12878 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
12879 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
12880
12881 #define LPTIM_CFGR_PRESC_Pos (9U)
12882 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
12883 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
12884 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
12885 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
12886 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
12887
12888 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
12889 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
12890 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
12891 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
12892 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
12893 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
12894
12895 #define LPTIM_CFGR_TRIGEN_Pos (17U)
12896 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
12897 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
12898 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
12899 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
12900
12901 #define LPTIM_CFGR_TIMOUT_Pos (19U)
12902 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
12903 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
12904 #define LPTIM_CFGR_WAVE_Pos (20U)
12905 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
12906 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
12907 #define LPTIM_CFGR_WAVPOL_Pos (21U)
12908 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
12909 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
12910 #define LPTIM_CFGR_PRELOAD_Pos (22U)
12911 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
12912 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
12913 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
12914 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
12915 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
12916 #define LPTIM_CFGR_ENC_Pos (24U)
12917 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
12918 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
12919
12920 /****************** Bit definition for LPTIM_CR register ********************/
12921 #define LPTIM_CR_ENABLE_Pos (0U)
12922 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
12923 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
12924 #define LPTIM_CR_SNGSTRT_Pos (1U)
12925 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
12926 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
12927 #define LPTIM_CR_CNTSTRT_Pos (2U)
12928 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
12929 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
12930
12931 /****************** Bit definition for LPTIM_CMP register *******************/
12932 #define LPTIM_CMP_CMP_Pos (0U)
12933 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
12934 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
12935
12936 /****************** Bit definition for LPTIM_ARR register *******************/
12937 #define LPTIM_ARR_ARR_Pos (0U)
12938 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
12939 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
12940
12941 /****************** Bit definition for LPTIM_CNT register *******************/
12942 #define LPTIM_CNT_CNT_Pos (0U)
12943 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
12944 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
12945
12946 /****************** Bit definition for LPTIM_OR register *******************/
12947 #define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
12948 #define LPTIM_OR_LPT_IN1_RMP_Msk (0x3U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000003 */
12949 #define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
12950 #define LPTIM_OR_LPT_IN1_RMP_0 (0x1U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000001 */
12951 #define LPTIM_OR_LPT_IN1_RMP_1 (0x2U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000002 */
12952 #define LPTIM_OR_TIM1_ITR2_RMP_Pos (2U)
12953 #define LPTIM_OR_TIM1_ITR2_RMP_Msk (0x1U << LPTIM_OR_TIM1_ITR2_RMP_Pos) /*!< 0x00000004 */
12954 #define LPTIM_OR_TIM1_ITR2_RMP LPTIM_OR_TIM1_ITR2_RMP_Msk /*!< Bit 2 */
12955 #define LPTIM_OR_TIM5_ITR1_RMP_Pos (3U)
12956 #define LPTIM_OR_TIM5_ITR1_RMP_Msk (0x1U << LPTIM_OR_TIM5_ITR1_RMP_Pos) /*!< 0x00000008 */
12957 #define LPTIM_OR_TIM5_ITR1_RMP LPTIM_OR_TIM5_ITR1_RMP_Msk /*!< Bit 3 */
12958 #define LPTIM_OR_TIM9_ITR1_RMP_Pos (4U)
12959 #define LPTIM_OR_TIM9_ITR1_RMP_Msk (0x1U << LPTIM_OR_TIM9_ITR1_RMP_Pos) /*!< 0x00000010 */
12960 #define LPTIM_OR_TIM9_ITR1_RMP LPTIM_OR_TIM9_ITR1_RMP_Msk /*!< Bit 4 */
12961
12962 /* Legacy Defines */
12963 #define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
12964 #define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
12965 #define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
12966
12967
12968 /******************************************************************************/
12969 /* */
12970 /* Universal Synchronous Asynchronous Receiver Transmitter */
12971 /* */
12972 /******************************************************************************/
12973 /******************* Bit definition for USART_SR register *******************/
12974 #define USART_SR_PE_Pos (0U)
12975 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
12976 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
12977 #define USART_SR_FE_Pos (1U)
12978 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
12979 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
12980 #define USART_SR_NE_Pos (2U)
12981 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
12982 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
12983 #define USART_SR_ORE_Pos (3U)
12984 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
12985 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
12986 #define USART_SR_IDLE_Pos (4U)
12987 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
12988 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
12989 #define USART_SR_RXNE_Pos (5U)
12990 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
12991 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
12992 #define USART_SR_TC_Pos (6U)
12993 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
12994 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
12995 #define USART_SR_TXE_Pos (7U)
12996 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
12997 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
12998 #define USART_SR_LBD_Pos (8U)
12999 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
13000 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
13001 #define USART_SR_CTS_Pos (9U)
13002 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
13003 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
13004
13005 /******************* Bit definition for USART_DR register *******************/
13006 #define USART_DR_DR_Pos (0U)
13007 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
13008 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
13009
13010 /****************** Bit definition for USART_BRR register *******************/
13011 #define USART_BRR_DIV_Fraction_Pos (0U)
13012 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
13013 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
13014 #define USART_BRR_DIV_Mantissa_Pos (4U)
13015 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
13016 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
13017
13018 /****************** Bit definition for USART_CR1 register *******************/
13019 #define USART_CR1_SBK_Pos (0U)
13020 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
13021 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
13022 #define USART_CR1_RWU_Pos (1U)
13023 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
13024 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
13025 #define USART_CR1_RE_Pos (2U)
13026 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
13027 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
13028 #define USART_CR1_TE_Pos (3U)
13029 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
13030 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
13031 #define USART_CR1_IDLEIE_Pos (4U)
13032 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
13033 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
13034 #define USART_CR1_RXNEIE_Pos (5U)
13035 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
13036 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
13037 #define USART_CR1_TCIE_Pos (6U)
13038 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
13039 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
13040 #define USART_CR1_TXEIE_Pos (7U)
13041 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
13042 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
13043 #define USART_CR1_PEIE_Pos (8U)
13044 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
13045 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
13046 #define USART_CR1_PS_Pos (9U)
13047 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
13048 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
13049 #define USART_CR1_PCE_Pos (10U)
13050 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
13051 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
13052 #define USART_CR1_WAKE_Pos (11U)
13053 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
13054 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
13055 #define USART_CR1_M_Pos (12U)
13056 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
13057 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
13058 #define USART_CR1_UE_Pos (13U)
13059 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
13060 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
13061 #define USART_CR1_OVER8_Pos (15U)
13062 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
13063 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
13064
13065 /****************** Bit definition for USART_CR2 register *******************/
13066 #define USART_CR2_ADD_Pos (0U)
13067 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
13068 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
13069 #define USART_CR2_LBDL_Pos (5U)
13070 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
13071 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
13072 #define USART_CR2_LBDIE_Pos (6U)
13073 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
13074 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
13075 #define USART_CR2_LBCL_Pos (8U)
13076 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
13077 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
13078 #define USART_CR2_CPHA_Pos (9U)
13079 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
13080 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
13081 #define USART_CR2_CPOL_Pos (10U)
13082 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
13083 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
13084 #define USART_CR2_CLKEN_Pos (11U)
13085 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
13086 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
13087
13088 #define USART_CR2_STOP_Pos (12U)
13089 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
13090 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
13091 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
13092 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
13093
13094 #define USART_CR2_LINEN_Pos (14U)
13095 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
13096 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
13097
13098 /****************** Bit definition for USART_CR3 register *******************/
13099 #define USART_CR3_EIE_Pos (0U)
13100 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
13101 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
13102 #define USART_CR3_IREN_Pos (1U)
13103 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
13104 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
13105 #define USART_CR3_IRLP_Pos (2U)
13106 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
13107 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
13108 #define USART_CR3_HDSEL_Pos (3U)
13109 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
13110 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
13111 #define USART_CR3_NACK_Pos (4U)
13112 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
13113 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
13114 #define USART_CR3_SCEN_Pos (5U)
13115 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
13116 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
13117 #define USART_CR3_DMAR_Pos (6U)
13118 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
13119 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
13120 #define USART_CR3_DMAT_Pos (7U)
13121 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
13122 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
13123 #define USART_CR3_RTSE_Pos (8U)
13124 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
13125 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
13126 #define USART_CR3_CTSE_Pos (9U)
13127 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
13128 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
13129 #define USART_CR3_CTSIE_Pos (10U)
13130 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
13131 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
13132 #define USART_CR3_ONEBIT_Pos (11U)
13133 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
13134 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
13135
13136 /****************** Bit definition for USART_GTPR register ******************/
13137 #define USART_GTPR_PSC_Pos (0U)
13138 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
13139 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
13140 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
13141 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
13142 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
13143 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
13144 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
13145 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
13146 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
13147 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
13148
13149 #define USART_GTPR_GT_Pos (8U)
13150 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
13151 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
13152
13153 /******************************************************************************/
13154 /* */
13155 /* Window WATCHDOG */
13156 /* */
13157 /******************************************************************************/
13158 /******************* Bit definition for WWDG_CR register ********************/
13159 #define WWDG_CR_T_Pos (0U)
13160 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
13161 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
13162 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
13163 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
13164 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
13165 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
13166 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
13167 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
13168 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
13169 /* Legacy defines */
13170 #define WWDG_CR_T0 WWDG_CR_T_0
13171 #define WWDG_CR_T1 WWDG_CR_T_1
13172 #define WWDG_CR_T2 WWDG_CR_T_2
13173 #define WWDG_CR_T3 WWDG_CR_T_3
13174 #define WWDG_CR_T4 WWDG_CR_T_4
13175 #define WWDG_CR_T5 WWDG_CR_T_5
13176 #define WWDG_CR_T6 WWDG_CR_T_6
13177
13178 #define WWDG_CR_WDGA_Pos (7U)
13179 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
13180 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
13181
13182 /******************* Bit definition for WWDG_CFR register *******************/
13183 #define WWDG_CFR_W_Pos (0U)
13184 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
13185 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
13186 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
13187 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
13188 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
13189 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
13190 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
13191 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
13192 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
13193 /* Legacy defines */
13194 #define WWDG_CFR_W0 WWDG_CFR_W_0
13195 #define WWDG_CFR_W1 WWDG_CFR_W_1
13196 #define WWDG_CFR_W2 WWDG_CFR_W_2
13197 #define WWDG_CFR_W3 WWDG_CFR_W_3
13198 #define WWDG_CFR_W4 WWDG_CFR_W_4
13199 #define WWDG_CFR_W5 WWDG_CFR_W_5
13200 #define WWDG_CFR_W6 WWDG_CFR_W_6
13201
13202 #define WWDG_CFR_WDGTB_Pos (7U)
13203 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
13204 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
13205 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
13206 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
13207 /* Legacy defines */
13208 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
13209 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
13210
13211 #define WWDG_CFR_EWI_Pos (9U)
13212 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
13213 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
13214
13215 /******************* Bit definition for WWDG_SR register ********************/
13216 #define WWDG_SR_EWIF_Pos (0U)
13217 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
13218 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
13219
13220
13221 /******************************************************************************/
13222 /* */
13223 /* DBG */
13224 /* */
13225 /******************************************************************************/
13226 /******************** Bit definition for DBGMCU_IDCODE register *************/
13227 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
13228 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
13229 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
13230 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
13231 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
13232 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
13233
13234 /******************** Bit definition for DBGMCU_CR register *****************/
13235 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
13236 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
13237 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
13238 #define DBGMCU_CR_DBG_STOP_Pos (1U)
13239 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
13240 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
13241 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
13242 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
13243 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
13244 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
13245 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
13246 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
13247
13248 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
13249 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
13250 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
13251 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
13252 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
13253
13254 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
13255 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
13256 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
13257 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
13258 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
13259 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
13260 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
13261 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
13262 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
13263 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
13264 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
13265 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
13266 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
13267 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
13268 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
13269 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
13270 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
13271 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
13272 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
13273 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
13274 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
13275 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
13276 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
13277 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
13278 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
13279 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
13280 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
13281 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
13282 #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos (9U)
13283 #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos) /*!< 0x00000200 */
13284 #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk
13285 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
13286 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
13287 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
13288 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
13289 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
13290 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
13291 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
13292 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
13293 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
13294 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
13295 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
13296 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
13297 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
13298 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
13299 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
13300 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
13301 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
13302 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
13303 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
13304 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
13305 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
13306 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
13307 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
13308 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
13309 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
13310 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
13311 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
13312 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (27U)
13313 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x08000000 */
13314 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
13315
13316 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
13317 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
13318 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
13319 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
13320 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
13321 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
13322 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
13323 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
13324 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
13325 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
13326 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
13327 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
13328 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
13329 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
13330 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
13331 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
13332
13333 /******************************************************************************/
13334 /* */
13335 /* USB_OTG */
13336 /* */
13337 /******************************************************************************/
13338 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
13339 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
13340 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
13341 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
13342 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
13343 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
13344 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
13345 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
13346 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
13347 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
13348 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
13349 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
13350 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
13351 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
13352 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
13353 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
13354 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
13355 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
13356 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
13357 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
13358 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
13359 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
13360 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
13361 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
13362 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
13363 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
13364 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
13365 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
13366 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
13367 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
13368 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
13369 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
13370 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
13371 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
13372 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
13373 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
13374 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
13375 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
13376 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
13377 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
13378 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
13379 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
13380 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
13381 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
13382 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
13383 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
13384 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
13385 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
13386 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
13387 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
13388 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
13389 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
13390 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
13391 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
13392 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
13393
13394 /******************** Bit definition forUSB_OTG_HCFG register ********************/
13395
13396 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
13397 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
13398 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
13399 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
13400 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
13401 #define USB_OTG_HCFG_FSLSS_Pos (2U)
13402 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
13403 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
13404
13405 /******************** Bit definition for USB_OTG_DCFG register ********************/
13406
13407 #define USB_OTG_DCFG_DSPD_Pos (0U)
13408 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
13409 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
13410 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
13411 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
13412 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
13413 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
13414 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
13415
13416 #define USB_OTG_DCFG_DAD_Pos (4U)
13417 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
13418 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
13419 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
13420 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
13421 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
13422 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
13423 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
13424 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
13425 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
13426
13427 #define USB_OTG_DCFG_PFIVL_Pos (11U)
13428 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
13429 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
13430 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
13431 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
13432
13433 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
13434 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
13435 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
13436 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
13437 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
13438
13439 /******************** Bit definition for USB_OTG_PCGCR register ********************/
13440 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
13441 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
13442 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
13443 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
13444 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
13445 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
13446 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
13447 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
13448 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
13449
13450 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
13451 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
13452 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
13453 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
13454 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
13455 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
13456 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
13457 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
13458 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
13459 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
13460 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
13461 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
13462 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
13463 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
13464 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
13465 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
13466 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
13467 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
13468 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
13469 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
13470 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
13471 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
13472
13473 /******************** Bit definition for USB_OTG_DCTL register ********************/
13474 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
13475 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
13476 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
13477 #define USB_OTG_DCTL_SDIS_Pos (1U)
13478 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
13479 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
13480 #define USB_OTG_DCTL_GINSTS_Pos (2U)
13481 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
13482 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
13483 #define USB_OTG_DCTL_GONSTS_Pos (3U)
13484 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
13485 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
13486
13487 #define USB_OTG_DCTL_TCTL_Pos (4U)
13488 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
13489 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
13490 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
13491 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
13492 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
13493 #define USB_OTG_DCTL_SGINAK_Pos (7U)
13494 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
13495 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
13496 #define USB_OTG_DCTL_CGINAK_Pos (8U)
13497 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
13498 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
13499 #define USB_OTG_DCTL_SGONAK_Pos (9U)
13500 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
13501 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
13502 #define USB_OTG_DCTL_CGONAK_Pos (10U)
13503 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
13504 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
13505 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
13506 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
13507 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
13508
13509 /******************** Bit definition for USB_OTG_HFIR register ********************/
13510 #define USB_OTG_HFIR_FRIVL_Pos (0U)
13511 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
13512 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
13513
13514 /******************** Bit definition for USB_OTG_HFNUM register ********************/
13515 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
13516 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
13517 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
13518 #define USB_OTG_HFNUM_FTREM_Pos (16U)
13519 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
13520 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
13521
13522 /******************** Bit definition for USB_OTG_DSTS register ********************/
13523 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
13524 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
13525 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
13526
13527 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
13528 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
13529 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
13530 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
13531 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
13532 #define USB_OTG_DSTS_EERR_Pos (3U)
13533 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
13534 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
13535 #define USB_OTG_DSTS_FNSOF_Pos (8U)
13536 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
13537 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
13538
13539 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
13540 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
13541 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
13542 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
13543 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
13544 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
13545 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
13546 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
13547 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
13548 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
13549 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
13550 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
13551 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
13552 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
13553 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
13554 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
13555 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
13556 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
13557 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
13558 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
13559 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
13560
13561 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
13562
13563 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
13564 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
13565 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
13566 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
13567 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
13568 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
13569 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
13570 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
13571 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
13572 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
13573 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
13574 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
13575 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
13576 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
13577 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
13578 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
13579 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
13580 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
13581 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
13582 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
13583 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
13584 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
13585 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
13586 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
13587 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
13588 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
13589 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
13590 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
13591 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
13592 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
13593 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
13594 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
13595 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
13596 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
13597 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
13598 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
13599 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
13600 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
13601 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
13602 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
13603 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
13604 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
13605 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
13606 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
13607 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
13608 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
13609 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
13610 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
13611 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
13612 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
13613 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
13614 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
13615 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
13616 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
13617 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
13618 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
13619 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
13620 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
13621 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
13622 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
13623 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
13624
13625 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
13626 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
13627 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
13628 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
13629 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
13630 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
13631 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
13632 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
13633 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
13634 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
13635 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
13636 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
13637 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
13638 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
13639 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
13640 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
13641
13642
13643 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
13644 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
13645 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
13646 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
13647 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
13648 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
13649 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
13650 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
13651 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
13652 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
13653 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
13654 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
13655 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
13656 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
13657
13658 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
13659 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
13660 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
13661 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
13662 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
13663 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
13664 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
13665 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
13666 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
13667 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
13668 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
13669 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
13670 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
13671 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
13672 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
13673 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
13674 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
13675 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
13676 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
13677 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
13678 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
13679 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
13680 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
13681 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
13682 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
13683
13684 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
13685 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
13686 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
13687 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
13688 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
13689 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
13690 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
13691 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
13692 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
13693 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
13694 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
13695 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
13696 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
13697 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
13698 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
13699
13700 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
13701 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
13702 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
13703 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
13704 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
13705 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
13706 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
13707 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
13708 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
13709 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
13710 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
13711
13712 /******************** Bit definition for USB_OTG_HAINT register ********************/
13713 #define USB_OTG_HAINT_HAINT_Pos (0U)
13714 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
13715 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
13716
13717 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
13718 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
13719 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
13720 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
13721 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
13722 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
13723 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
13724 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
13725 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
13726 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
13727 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
13728 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
13729 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
13730 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
13731 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
13732 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
13733 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
13734 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
13735 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
13736 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
13737 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
13738 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
13739 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
13740 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
13741 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
13742
13743 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
13744 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
13745 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
13746 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
13747 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
13748 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
13749 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
13750 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
13751 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
13752 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
13753 #define USB_OTG_GINTSTS_SOF_Pos (3U)
13754 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
13755 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
13756 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
13757 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
13758 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
13759 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
13760 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
13761 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
13762 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
13763 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
13764 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
13765 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
13766 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
13767 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
13768 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
13769 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
13770 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
13771 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
13772 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
13773 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
13774 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
13775 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
13776 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
13777 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
13778 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
13779 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
13780 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
13781 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
13782 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
13783 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
13784 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
13785 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
13786 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
13787 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
13788 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
13789 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
13790 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
13791 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
13792 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
13793 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
13794 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
13795 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
13796 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
13797 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
13798 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
13799 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
13800 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
13801 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
13802 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
13803 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
13804 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
13805 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
13806 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
13807 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
13808 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
13809 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
13810 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
13811 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
13812 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
13813 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
13814 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
13815 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
13816 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
13817 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
13818 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
13819 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
13820 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
13821 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
13822 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
13823 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
13824 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
13825 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
13826 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
13827 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
13828
13829 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
13830 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
13831 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
13832 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
13833 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
13834 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
13835 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
13836 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
13837 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
13838 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
13839 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
13840 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
13841 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
13842 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
13843 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
13844 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
13845 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
13846 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
13847 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
13848 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
13849 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
13850 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
13851 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
13852 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
13853 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
13854 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
13855 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
13856 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
13857 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
13858 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
13859 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
13860 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
13861 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
13862 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
13863 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
13864 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
13865 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
13866 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
13867 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
13868 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
13869 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
13870 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
13871 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
13872 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
13873 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
13874 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
13875 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
13876 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
13877 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
13878 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
13879 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
13880 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
13881 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
13882 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
13883 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
13884 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
13885 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
13886 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
13887 #define USB_OTG_GINTMSK_RSTDETM_Pos (23U)
13888 #define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */
13889 #define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */
13890 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
13891 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
13892 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
13893 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
13894 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
13895 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
13896 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
13897 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
13898 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
13899 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
13900 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
13901 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
13902 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
13903 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
13904 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
13905 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
13906 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
13907 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
13908 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
13909 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
13910 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
13911 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
13912 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
13913 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
13914
13915 /******************** Bit definition for USB_OTG_DAINT register ********************/
13916 #define USB_OTG_DAINT_IEPINT_Pos (0U)
13917 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
13918 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
13919 #define USB_OTG_DAINT_OEPINT_Pos (16U)
13920 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
13921 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
13922
13923 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
13924 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
13925 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
13926 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
13927
13928 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
13929 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
13930 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
13931 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
13932 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
13933 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
13934 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
13935 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
13936 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
13937 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
13938 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
13939 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
13940 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
13941
13942 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
13943 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
13944 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
13945 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
13946 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
13947 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
13948 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
13949
13950 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
13951 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
13952 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
13953 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
13954
13955 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
13956 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
13957 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
13958 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
13959
13960 /******************** Bit definition for OTG register ********************/
13961 #define USB_OTG_NPTXFSA_Pos (0U)
13962 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
13963 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
13964 #define USB_OTG_NPTXFD_Pos (16U)
13965 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
13966 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
13967 #define USB_OTG_TX0FSA_Pos (0U)
13968 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
13969 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
13970 #define USB_OTG_TX0FD_Pos (16U)
13971 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
13972 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
13973
13974 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
13975 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
13976 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
13977 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
13978
13979 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
13980 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
13981 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
13982 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
13983
13984 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
13985 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
13986 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
13987 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
13988 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
13989 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
13990 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
13991 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
13992 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
13993 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
13994 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
13995
13996 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
13997 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
13998 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
13999 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
14000 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
14001 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
14002 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
14003 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
14004 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
14005 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
14006
14007 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14008 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14009 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
14010 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
14011 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14012 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
14013 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
14014
14015 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14016 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
14017 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
14018 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
14019 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
14020 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
14021 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
14022 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
14023 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
14024 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
14025 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
14026 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
14027 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14028 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
14029 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
14030
14031 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14032 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
14033 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
14034 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
14035 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
14036 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
14037 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
14038 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
14039 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
14040 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
14041 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
14042 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
14043 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14044 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
14045 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
14046
14047 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14048 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14049 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
14050 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
14051
14052 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
14053 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14054 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
14055 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
14056 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14057 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
14058 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
14059
14060 /******************** Bit definition for USB_OTG_GCCFG register ********************/
14061 #define USB_OTG_GCCFG_DCDET_Pos (0U)
14062 #define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
14063 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
14064 #define USB_OTG_GCCFG_PDET_Pos (1U)
14065 #define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
14066 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
14067 #define USB_OTG_GCCFG_SDET_Pos (2U)
14068 #define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
14069 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
14070 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
14071 #define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
14072 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
14073 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14074 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
14075 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
14076 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
14077 #define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
14078 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
14079 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
14080 #define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
14081 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
14082 #define USB_OTG_GCCFG_PDEN_Pos (19U)
14083 #define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
14084 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
14085 #define USB_OTG_GCCFG_SDEN_Pos (20U)
14086 #define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
14087 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
14088 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
14089 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
14090 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
14091
14092 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
14093 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14094 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
14095 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
14096 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14097 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
14098 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
14099
14100 /******************** Bit definition for USB_OTG_CID register ********************/
14101 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14102 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
14103 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
14104
14105 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
14106 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
14107 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
14108 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
14109 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
14110 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
14111 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
14112 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
14113 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
14114 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
14115 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
14116 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
14117 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
14118 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
14119 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
14120 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
14121 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
14122 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
14123 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
14124 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
14125 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
14126 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
14127 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
14128 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
14129 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
14130 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
14131 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
14132 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
14133 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
14134 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
14135 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
14136 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
14137 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
14138 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
14139 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
14140 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
14141 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
14142 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
14143 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
14144 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
14145 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
14146 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
14147 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
14148 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
14149 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
14150 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
14151
14152 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14153 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14154 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14155 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
14156 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14157 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14158 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14159 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14160 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14161 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
14162 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14163 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14164 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
14165 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14166 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14167 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
14168 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14169 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14170 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
14171 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14172 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14173 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
14174 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14175 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14176 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
14177 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14178 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14179 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
14180
14181 /******************** Bit definition for USB_OTG_HPRT register ********************/
14182 #define USB_OTG_HPRT_PCSTS_Pos (0U)
14183 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
14184 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
14185 #define USB_OTG_HPRT_PCDET_Pos (1U)
14186 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
14187 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
14188 #define USB_OTG_HPRT_PENA_Pos (2U)
14189 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
14190 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
14191 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
14192 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
14193 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
14194 #define USB_OTG_HPRT_POCA_Pos (4U)
14195 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
14196 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
14197 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
14198 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
14199 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
14200 #define USB_OTG_HPRT_PRES_Pos (6U)
14201 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
14202 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
14203 #define USB_OTG_HPRT_PSUSP_Pos (7U)
14204 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
14205 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
14206 #define USB_OTG_HPRT_PRST_Pos (8U)
14207 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
14208 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
14209
14210 #define USB_OTG_HPRT_PLSTS_Pos (10U)
14211 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
14212 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
14213 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
14214 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
14215 #define USB_OTG_HPRT_PPWR_Pos (12U)
14216 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
14217 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
14218
14219 #define USB_OTG_HPRT_PTCTL_Pos (13U)
14220 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
14221 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
14222 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
14223 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
14224 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
14225 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
14226
14227 #define USB_OTG_HPRT_PSPD_Pos (17U)
14228 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
14229 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
14230 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
14231 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
14232
14233 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
14234 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14235 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14236 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
14237 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14238 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14239 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14240 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14241 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14242 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
14243 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14244 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14245 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
14246 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14247 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14248 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
14249 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14250 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14251 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
14252 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14253 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14254 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
14255 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14256 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14257 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
14258 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14259 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
14260 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
14261 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14262 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14263 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
14264 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14265 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
14266 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
14267
14268 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
14269 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14270 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
14271 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
14272 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14273 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
14274 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
14275
14276 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
14277 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14278 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
14279 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
14280 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14281 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
14282 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
14283 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14284 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
14285 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
14286 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
14287 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
14288 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
14289
14290 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
14291 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
14292 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
14293 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
14294 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
14295 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
14296 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
14297 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
14298
14299 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
14300 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
14301 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
14302 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
14303 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
14304 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
14305 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
14306 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
14307 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
14308 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
14309 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
14310 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
14311 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
14312 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
14313 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
14314 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
14315 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
14316 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
14317 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
14318 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
14319 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
14320 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
14321 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
14322 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
14323 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
14324
14325 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
14326 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
14327 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
14328 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
14329
14330 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
14331 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
14332 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
14333 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
14334 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
14335 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
14336 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
14337 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
14338 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
14339 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
14340 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
14341 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
14342 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
14343
14344 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
14345 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
14346 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
14347 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
14348 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
14349
14350 #define USB_OTG_HCCHAR_MC_Pos (20U)
14351 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
14352 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
14353 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
14354 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
14355
14356 #define USB_OTG_HCCHAR_DAD_Pos (22U)
14357 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
14358 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
14359 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
14360 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
14361 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
14362 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
14363 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
14364 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
14365 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
14366 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
14367 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
14368 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
14369 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
14370 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
14371 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
14372 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
14373 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
14374 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
14375
14376 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
14377
14378 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
14379 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
14380 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
14381 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
14382 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
14383 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
14384 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
14385 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
14386 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
14387 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
14388
14389 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
14390 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
14391 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
14392 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
14393 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
14394 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
14395 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
14396 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
14397 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
14398 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
14399
14400 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
14401 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
14402 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
14403 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
14404 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
14405 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
14406 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
14407 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
14408 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
14409 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
14410 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
14411
14412 /******************** Bit definition for USB_OTG_HCINT register ********************/
14413 #define USB_OTG_HCINT_XFRC_Pos (0U)
14414 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
14415 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
14416 #define USB_OTG_HCINT_CHH_Pos (1U)
14417 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
14418 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
14419 #define USB_OTG_HCINT_AHBERR_Pos (2U)
14420 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
14421 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
14422 #define USB_OTG_HCINT_STALL_Pos (3U)
14423 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
14424 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
14425 #define USB_OTG_HCINT_NAK_Pos (4U)
14426 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
14427 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
14428 #define USB_OTG_HCINT_ACK_Pos (5U)
14429 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
14430 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
14431 #define USB_OTG_HCINT_NYET_Pos (6U)
14432 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
14433 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
14434 #define USB_OTG_HCINT_TXERR_Pos (7U)
14435 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
14436 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
14437 #define USB_OTG_HCINT_BBERR_Pos (8U)
14438 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
14439 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
14440 #define USB_OTG_HCINT_FRMOR_Pos (9U)
14441 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
14442 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
14443 #define USB_OTG_HCINT_DTERR_Pos (10U)
14444 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
14445 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
14446
14447 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
14448 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
14449 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
14450 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
14451 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
14452 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
14453 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
14454 #define USB_OTG_DIEPINT_TOC_Pos (3U)
14455 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
14456 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
14457 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
14458 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
14459 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
14460 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
14461 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
14462 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
14463 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
14464 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
14465 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
14466 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
14467 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
14468 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
14469 #define USB_OTG_DIEPINT_BNA_Pos (9U)
14470 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
14471 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
14472 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
14473 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
14474 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
14475 #define USB_OTG_DIEPINT_BERR_Pos (12U)
14476 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
14477 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
14478 #define USB_OTG_DIEPINT_NAK_Pos (13U)
14479 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
14480 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
14481
14482 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
14483 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
14484 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
14485 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
14486 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
14487 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
14488 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
14489 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
14490 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
14491 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
14492 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
14493 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
14494 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
14495 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
14496 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
14497 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
14498 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
14499 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
14500 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
14501 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
14502 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
14503 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
14504 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
14505 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
14506 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
14507 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
14508 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
14509 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
14510 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
14511 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
14512 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
14513 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
14514 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
14515 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
14516
14517 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
14518
14519 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
14520 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14521 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
14522 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
14523 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14524 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
14525 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
14526 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
14527 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
14528 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
14529 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
14530 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14531 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
14532 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
14533 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14534 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
14535 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
14536 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
14537 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
14538 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
14539 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
14540 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
14541 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
14542 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
14543
14544 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
14545 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
14546 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
14547 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
14548
14549 /******************** Bit definition for USB_OTG_HCDMA register ********************/
14550 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
14551 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
14552 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
14553
14554 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
14555 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
14556 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
14557 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
14558
14559 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
14560 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
14561 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
14562 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
14563 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
14564 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
14565 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
14566
14567 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
14568
14569 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
14570 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
14571 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
14572 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
14573 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
14574 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
14575 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
14576 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
14577 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
14578 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
14579 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
14580 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
14581 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
14582 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
14583 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
14584 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
14585 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
14586 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
14587 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
14588 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
14589 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
14590 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
14591 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
14592 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
14593 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
14594 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
14595 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
14596 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
14597 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
14598 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
14599 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
14600 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
14601 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
14602 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
14603 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
14604 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
14605 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
14606 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
14607
14608 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
14609 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
14610 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
14611 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
14612 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
14613 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
14614 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
14615 #define USB_OTG_DOEPINT_STUP_Pos (3U)
14616 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
14617 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
14618 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
14619 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
14620 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
14621 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
14622 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
14623 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
14624 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
14625 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
14626 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
14627 #define USB_OTG_DOEPINT_NYET_Pos (14U)
14628 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
14629 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
14630
14631 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
14632
14633 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
14634 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14635 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
14636 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
14637 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14638 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
14639
14640 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
14641 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
14642 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
14643 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
14644 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
14645
14646 /******************** Bit definition for PCGCCTL register ********************/
14647 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
14648 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
14649 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
14650 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
14651 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
14652 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
14653 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
14654 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
14655 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
14656
14657 /* Legacy define */
14658 /******************** Bit definition for OTG register ********************/
14659 #define USB_OTG_CHNUM_Pos (0U)
14660 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
14661 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
14662 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
14663 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
14664 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
14665 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
14666 #define USB_OTG_BCNT_Pos (4U)
14667 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
14668 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
14669
14670 #define USB_OTG_DPID_Pos (15U)
14671 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
14672 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
14673 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
14674 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
14675
14676 #define USB_OTG_PKTSTS_Pos (17U)
14677 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
14678 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
14679 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
14680 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
14681 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
14682 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
14683
14684 #define USB_OTG_EPNUM_Pos (0U)
14685 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
14686 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
14687 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
14688 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
14689 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
14690 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
14691
14692 #define USB_OTG_FRMNUM_Pos (21U)
14693 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
14694 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
14695 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
14696 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
14697 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
14698 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
14699 /**
14700 * @}
14701 */
14702
14703 /**
14704 * @}
14705 */
14706
14707 /** @addtogroup Exported_macros
14708 * @{
14709 */
14710
14711 /******************************* ADC Instances ********************************/
14712 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14713
14714 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
14715
14716 /******************************* CAN Instances ********************************/
14717 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
14718 ((INSTANCE) == CAN2) || \
14719 ((INSTANCE) == CAN3))
14720
14721 /****************************** DFSDM Instances *******************************/
14722 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
14723 ((INSTANCE) == DFSDM1_Filter1) || \
14724 ((INSTANCE) == DFSDM2_Filter0) || \
14725 ((INSTANCE) == DFSDM2_Filter1) || \
14726 ((INSTANCE) == DFSDM2_Filter2) || \
14727 ((INSTANCE) == DFSDM2_Filter3))
14728
14729 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
14730 ((INSTANCE) == DFSDM1_Channel1) || \
14731 ((INSTANCE) == DFSDM1_Channel2) || \
14732 ((INSTANCE) == DFSDM1_Channel3) || \
14733 ((INSTANCE) == DFSDM2_Channel0) || \
14734 ((INSTANCE) == DFSDM2_Channel1) || \
14735 ((INSTANCE) == DFSDM2_Channel2) || \
14736 ((INSTANCE) == DFSDM2_Channel3) || \
14737 ((INSTANCE) == DFSDM2_Channel4) || \
14738 ((INSTANCE) == DFSDM2_Channel5) || \
14739 ((INSTANCE) == DFSDM2_Channel6) || \
14740 ((INSTANCE) == DFSDM2_Channel7))
14741 /******************************* CRC Instances ********************************/
14742 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14743
14744 /******************************* DAC Instances ********************************/
14745 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14746
14747
14748 /******************************** DMA Instances *******************************/
14749 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
14750 ((INSTANCE) == DMA1_Stream1) || \
14751 ((INSTANCE) == DMA1_Stream2) || \
14752 ((INSTANCE) == DMA1_Stream3) || \
14753 ((INSTANCE) == DMA1_Stream4) || \
14754 ((INSTANCE) == DMA1_Stream5) || \
14755 ((INSTANCE) == DMA1_Stream6) || \
14756 ((INSTANCE) == DMA1_Stream7) || \
14757 ((INSTANCE) == DMA2_Stream0) || \
14758 ((INSTANCE) == DMA2_Stream1) || \
14759 ((INSTANCE) == DMA2_Stream2) || \
14760 ((INSTANCE) == DMA2_Stream3) || \
14761 ((INSTANCE) == DMA2_Stream4) || \
14762 ((INSTANCE) == DMA2_Stream5) || \
14763 ((INSTANCE) == DMA2_Stream6) || \
14764 ((INSTANCE) == DMA2_Stream7))
14765
14766 /******************************* GPIO Instances *******************************/
14767 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14768 ((INSTANCE) == GPIOB) || \
14769 ((INSTANCE) == GPIOC) || \
14770 ((INSTANCE) == GPIOD) || \
14771 ((INSTANCE) == GPIOE) || \
14772 ((INSTANCE) == GPIOF) || \
14773 ((INSTANCE) == GPIOG) || \
14774 ((INSTANCE) == GPIOH))
14775
14776 /******************************** I2C Instances *******************************/
14777 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14778 ((INSTANCE) == I2C2) || \
14779 ((INSTANCE) == I2C3))
14780
14781
14782 /******************************** I2S Instances *******************************/
14783 #define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
14784 ((INSTANCE) == SPI3))
14785
14786 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14787 ((INSTANCE) == SPI2) || \
14788 ((INSTANCE) == SPI3) || \
14789 ((INSTANCE) == SPI4) || \
14790 ((INSTANCE) == SPI5))
14791
14792 /*************************** I2S Extended Instances ***************************/
14793 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
14794 ((INSTANCE) == I2S3ext))
14795 /* Legacy Defines */
14796 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
14797
14798 /******************************* AES Instances ********************************/
14799 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
14800
14801 /******************************* LPTIM Instances ******************************/
14802 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
14803
14804 /******************************* RNG Instances ********************************/
14805 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
14806
14807 /****************************** RTC Instances *********************************/
14808 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
14809
14810
14811 /******************************** SPI Instances *******************************/
14812
14813 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14814 ((INSTANCE) == SPI2) || \
14815 ((INSTANCE) == SPI3) || \
14816 ((INSTANCE) == SPI4) || \
14817 ((INSTANCE) == SPI5))
14818
14819
14820 /*************************** SPI Extended Instances ***************************/
14821 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
14822 ((INSTANCE) == SPI2) || \
14823 ((INSTANCE) == SPI3) || \
14824 ((INSTANCE) == SPI4) || \
14825 ((INSTANCE) == SPI5) || \
14826 ((INSTANCE) == I2S2ext) || \
14827 ((INSTANCE) == I2S3ext))
14828 /******************************* SAI Instances ********************************/
14829 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
14830 ((PERIPH) == SAI1_Block_B))
14831 /****************** TIM Instances : All supported instances *******************/
14832 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14833 ((INSTANCE) == TIM2) || \
14834 ((INSTANCE) == TIM3) || \
14835 ((INSTANCE) == TIM4) || \
14836 ((INSTANCE) == TIM5) || \
14837 ((INSTANCE) == TIM6) || \
14838 ((INSTANCE) == TIM7) || \
14839 ((INSTANCE) == TIM8) || \
14840 ((INSTANCE) == TIM9) || \
14841 ((INSTANCE) == TIM10)|| \
14842 ((INSTANCE) == TIM11)|| \
14843 ((INSTANCE) == TIM12)|| \
14844 ((INSTANCE) == TIM13)|| \
14845 ((INSTANCE) == TIM14))
14846
14847 /************* TIM Instances : at least 1 capture/compare channel *************/
14848 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14849 ((INSTANCE) == TIM2) || \
14850 ((INSTANCE) == TIM3) || \
14851 ((INSTANCE) == TIM4) || \
14852 ((INSTANCE) == TIM5) || \
14853 ((INSTANCE) == TIM8) || \
14854 ((INSTANCE) == TIM9) || \
14855 ((INSTANCE) == TIM10) || \
14856 ((INSTANCE) == TIM11) || \
14857 ((INSTANCE) == TIM12) || \
14858 ((INSTANCE) == TIM13) || \
14859 ((INSTANCE) == TIM14))
14860
14861 /************ TIM Instances : at least 2 capture/compare channels *************/
14862 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14863 ((INSTANCE) == TIM2) || \
14864 ((INSTANCE) == TIM3) || \
14865 ((INSTANCE) == TIM4) || \
14866 ((INSTANCE) == TIM5) || \
14867 ((INSTANCE) == TIM8) || \
14868 ((INSTANCE) == TIM9) || \
14869 ((INSTANCE) == TIM12))
14870
14871 /************ TIM Instances : at least 3 capture/compare channels *************/
14872 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14873 ((INSTANCE) == TIM2) || \
14874 ((INSTANCE) == TIM3) || \
14875 ((INSTANCE) == TIM4) || \
14876 ((INSTANCE) == TIM5) || \
14877 ((INSTANCE) == TIM8))
14878
14879 /************ TIM Instances : at least 4 capture/compare channels *************/
14880 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14881 ((INSTANCE) == TIM2) || \
14882 ((INSTANCE) == TIM3) || \
14883 ((INSTANCE) == TIM4) || \
14884 ((INSTANCE) == TIM5) || \
14885 ((INSTANCE) == TIM8))
14886
14887 /******************** TIM Instances : Advanced-control timers *****************/
14888 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14889 ((INSTANCE) == TIM8))
14890
14891 /******************* TIM Instances : Timer input XOR function *****************/
14892 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14893 ((INSTANCE) == TIM2) || \
14894 ((INSTANCE) == TIM3) || \
14895 ((INSTANCE) == TIM4) || \
14896 ((INSTANCE) == TIM5) || \
14897 ((INSTANCE) == TIM8))
14898
14899 /****************** TIM Instances : DMA requests generation (UDE) *************/
14900 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14901 ((INSTANCE) == TIM2) || \
14902 ((INSTANCE) == TIM3) || \
14903 ((INSTANCE) == TIM4) || \
14904 ((INSTANCE) == TIM5) || \
14905 ((INSTANCE) == TIM6) || \
14906 ((INSTANCE) == TIM7) || \
14907 ((INSTANCE) == TIM8))
14908
14909 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
14910 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14911 ((INSTANCE) == TIM2) || \
14912 ((INSTANCE) == TIM3) || \
14913 ((INSTANCE) == TIM4) || \
14914 ((INSTANCE) == TIM5) || \
14915 ((INSTANCE) == TIM8))
14916
14917 /************ TIM Instances : DMA requests generation (COMDE) *****************/
14918 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14919 ((INSTANCE) == TIM2) || \
14920 ((INSTANCE) == TIM3) || \
14921 ((INSTANCE) == TIM4) || \
14922 ((INSTANCE) == TIM5) || \
14923 ((INSTANCE) == TIM8))
14924
14925 /******************** TIM Instances : DMA burst feature ***********************/
14926 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14927 ((INSTANCE) == TIM2) || \
14928 ((INSTANCE) == TIM3) || \
14929 ((INSTANCE) == TIM4) || \
14930 ((INSTANCE) == TIM5) || \
14931 ((INSTANCE) == TIM8))
14932
14933 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
14934 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14935 ((INSTANCE) == TIM2) || \
14936 ((INSTANCE) == TIM3) || \
14937 ((INSTANCE) == TIM4) || \
14938 ((INSTANCE) == TIM5) || \
14939 ((INSTANCE) == TIM6) || \
14940 ((INSTANCE) == TIM7) || \
14941 ((INSTANCE) == TIM8))
14942
14943 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
14944 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14945 ((INSTANCE) == TIM2) || \
14946 ((INSTANCE) == TIM3) || \
14947 ((INSTANCE) == TIM4) || \
14948 ((INSTANCE) == TIM5) || \
14949 ((INSTANCE) == TIM8) || \
14950 ((INSTANCE) == TIM9) || \
14951 ((INSTANCE) == TIM12))
14952
14953 /********************** TIM Instances : 32 bit Counter ************************/
14954 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
14955 ((INSTANCE) == TIM5))
14956
14957 /***************** TIM Instances : external trigger input availabe ************/
14958 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14959 ((INSTANCE) == TIM2) || \
14960 ((INSTANCE) == TIM3) || \
14961 ((INSTANCE) == TIM4) || \
14962 ((INSTANCE) == TIM5) || \
14963 ((INSTANCE) == TIM8))
14964
14965 /****************** TIM Instances : remapping capability **********************/
14966 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
14967 ((INSTANCE) == TIM5) || \
14968 ((INSTANCE) == TIM11))
14969
14970 /******************* TIM Instances : output(s) available **********************/
14971 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
14972 ((((INSTANCE) == TIM1) && \
14973 (((CHANNEL) == TIM_CHANNEL_1) || \
14974 ((CHANNEL) == TIM_CHANNEL_2) || \
14975 ((CHANNEL) == TIM_CHANNEL_3) || \
14976 ((CHANNEL) == TIM_CHANNEL_4))) \
14977 || \
14978 (((INSTANCE) == TIM2) && \
14979 (((CHANNEL) == TIM_CHANNEL_1) || \
14980 ((CHANNEL) == TIM_CHANNEL_2) || \
14981 ((CHANNEL) == TIM_CHANNEL_3) || \
14982 ((CHANNEL) == TIM_CHANNEL_4))) \
14983 || \
14984 (((INSTANCE) == TIM3) && \
14985 (((CHANNEL) == TIM_CHANNEL_1) || \
14986 ((CHANNEL) == TIM_CHANNEL_2) || \
14987 ((CHANNEL) == TIM_CHANNEL_3) || \
14988 ((CHANNEL) == TIM_CHANNEL_4))) \
14989 || \
14990 (((INSTANCE) == TIM4) && \
14991 (((CHANNEL) == TIM_CHANNEL_1) || \
14992 ((CHANNEL) == TIM_CHANNEL_2) || \
14993 ((CHANNEL) == TIM_CHANNEL_3) || \
14994 ((CHANNEL) == TIM_CHANNEL_4))) \
14995 || \
14996 (((INSTANCE) == TIM5) && \
14997 (((CHANNEL) == TIM_CHANNEL_1) || \
14998 ((CHANNEL) == TIM_CHANNEL_2) || \
14999 ((CHANNEL) == TIM_CHANNEL_3) || \
15000 ((CHANNEL) == TIM_CHANNEL_4))) \
15001 || \
15002 (((INSTANCE) == TIM8) && \
15003 (((CHANNEL) == TIM_CHANNEL_1) || \
15004 ((CHANNEL) == TIM_CHANNEL_2) || \
15005 ((CHANNEL) == TIM_CHANNEL_3) || \
15006 ((CHANNEL) == TIM_CHANNEL_4))) \
15007 || \
15008 (((INSTANCE) == TIM9) && \
15009 (((CHANNEL) == TIM_CHANNEL_1) || \
15010 ((CHANNEL) == TIM_CHANNEL_2))) \
15011 || \
15012 (((INSTANCE) == TIM10) && \
15013 (((CHANNEL) == TIM_CHANNEL_1))) \
15014 || \
15015 (((INSTANCE) == TIM11) && \
15016 (((CHANNEL) == TIM_CHANNEL_1))) \
15017 || \
15018 (((INSTANCE) == TIM12) && \
15019 (((CHANNEL) == TIM_CHANNEL_1) || \
15020 ((CHANNEL) == TIM_CHANNEL_2))) \
15021 || \
15022 (((INSTANCE) == TIM13) && \
15023 (((CHANNEL) == TIM_CHANNEL_1))) \
15024 || \
15025 (((INSTANCE) == TIM14) && \
15026 (((CHANNEL) == TIM_CHANNEL_1))))
15027
15028 /************ TIM Instances : complementary output(s) available ***************/
15029 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15030 ((((INSTANCE) == TIM1) && \
15031 (((CHANNEL) == TIM_CHANNEL_1) || \
15032 ((CHANNEL) == TIM_CHANNEL_2) || \
15033 ((CHANNEL) == TIM_CHANNEL_3))) \
15034 || \
15035 (((INSTANCE) == TIM8) && \
15036 (((CHANNEL) == TIM_CHANNEL_1) || \
15037 ((CHANNEL) == TIM_CHANNEL_2) || \
15038 ((CHANNEL) == TIM_CHANNEL_3))))
15039
15040 /****************** TIM Instances : supporting counting mode selection ********/
15041 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15042 ((INSTANCE) == TIM2) || \
15043 ((INSTANCE) == TIM3) || \
15044 ((INSTANCE) == TIM4) || \
15045 ((INSTANCE) == TIM5) || \
15046 ((INSTANCE) == TIM8))
15047
15048 /****************** TIM Instances : supporting clock division *****************/
15049 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15050 ((INSTANCE) == TIM2) || \
15051 ((INSTANCE) == TIM3) || \
15052 ((INSTANCE) == TIM4) || \
15053 ((INSTANCE) == TIM5) || \
15054 ((INSTANCE) == TIM8) || \
15055 ((INSTANCE) == TIM9) || \
15056 ((INSTANCE) == TIM10)|| \
15057 ((INSTANCE) == TIM11)|| \
15058 ((INSTANCE) == TIM12)|| \
15059 ((INSTANCE) == TIM13)|| \
15060 ((INSTANCE) == TIM14))
15061
15062 /****************** TIM Instances : supporting commutation event generation ***/
15063 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15064 ((INSTANCE) == TIM8))
15065
15066
15067 /****************** TIM Instances : supporting OCxREF clear *******************/
15068 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15069 ((INSTANCE) == TIM2) || \
15070 ((INSTANCE) == TIM3) || \
15071 ((INSTANCE) == TIM4) || \
15072 ((INSTANCE) == TIM5) || \
15073 ((INSTANCE) == TIM8))
15074
15075 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15076 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15077 ((INSTANCE) == TIM2) || \
15078 ((INSTANCE) == TIM3) || \
15079 ((INSTANCE) == TIM4) || \
15080 ((INSTANCE) == TIM5) || \
15081 ((INSTANCE) == TIM8) || \
15082 ((INSTANCE) == TIM9) || \
15083 ((INSTANCE) == TIM12))
15084
15085 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15086 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15087 ((INSTANCE) == TIM2) || \
15088 ((INSTANCE) == TIM3) || \
15089 ((INSTANCE) == TIM4) || \
15090 ((INSTANCE) == TIM5) || \
15091 ((INSTANCE) == TIM8))
15092
15093 /****************** TIM Instances : supporting repetition counter *************/
15094 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15095 ((INSTANCE) == TIM8))
15096
15097 /****************** TIM Instances : supporting encoder interface **************/
15098 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15099 ((INSTANCE) == TIM2) || \
15100 ((INSTANCE) == TIM3) || \
15101 ((INSTANCE) == TIM4) || \
15102 ((INSTANCE) == TIM5) || \
15103 ((INSTANCE) == TIM8) || \
15104 ((INSTANCE) == TIM9))
15105 /****************** TIM Instances : supporting Hall sensor interface **********/
15106 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15107 ((INSTANCE) == TIM2) || \
15108 ((INSTANCE) == TIM3) || \
15109 ((INSTANCE) == TIM4) || \
15110 ((INSTANCE) == TIM5) || \
15111 ((INSTANCE) == TIM8))
15112 /****************** TIM Instances : supporting the break function *************/
15113 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15114 ((INSTANCE) == TIM8))
15115
15116 /******************** USART Instances : Synchronous mode **********************/
15117 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15118 ((INSTANCE) == USART2) || \
15119 ((INSTANCE) == USART3) || \
15120 ((INSTANCE) == USART6))
15121
15122 /******************** UART Instances : Half-Duplex mode **********************/
15123 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15124 ((INSTANCE) == USART2) || \
15125 ((INSTANCE) == USART3) || \
15126 ((INSTANCE) == UART4) || \
15127 ((INSTANCE) == UART5) || \
15128 ((INSTANCE) == USART6) || \
15129 ((INSTANCE) == UART7) || \
15130 ((INSTANCE) == UART8) || \
15131 ((INSTANCE) == UART9) || \
15132 ((INSTANCE) == UART10))
15133
15134 /* Legacy defines */
15135 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15136
15137 /****************** UART Instances : Hardware Flow control ********************/
15138 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15139 ((INSTANCE) == USART2) || \
15140 ((INSTANCE) == USART3) || \
15141 ((INSTANCE) == USART6))
15142 /******************** UART Instances : LIN mode **********************/
15143 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15144
15145 /********************* UART Instances : Smart card mode ***********************/
15146 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15147 ((INSTANCE) == USART2) || \
15148 ((INSTANCE) == USART3) || \
15149 ((INSTANCE) == USART6))
15150
15151 /*********************** UART Instances : IRDA mode ***************************/
15152 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15153 ((INSTANCE) == USART2) || \
15154 ((INSTANCE) == USART3) || \
15155 ((INSTANCE) == UART4) || \
15156 ((INSTANCE) == UART5) || \
15157 ((INSTANCE) == USART6) || \
15158 ((INSTANCE) == UART7) || \
15159 ((INSTANCE) == UART8) || \
15160 ((INSTANCE) == UART9) || \
15161 ((INSTANCE) == UART10))
15162
15163 /*********************** PCD Instances ****************************************/
15164 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
15165
15166 /*********************** HCD Instances ****************************************/
15167 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
15168
15169 /****************************** SDIO Instances ********************************/
15170 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15171
15172 /****************************** IWDG Instances ********************************/
15173 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15174
15175 /****************************** WWDG Instances ********************************/
15176 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15177
15178
15179 /***************************** FMPI2C Instances *******************************/
15180 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
15181
15182 /****************************** QSPI Instances ********************************/
15183 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
15184 /****************************** USB Instances ********************************/
15185 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
15186 /****************************** USB Exported Constants ************************/
15187 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
15188 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
15189 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
15190 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
15191
15192 /*
15193 * @brief Specific devices reset values definitions
15194 */
15195 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
15196 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
15197
15198 #define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
15199 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
15200 #define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
15201 #define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
15202 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
15203 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
15204 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
15205 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
15206
15207 #define RCC_PLLN_MIN_VALUE 50U
15208 #define RCC_PLLN_MAX_VALUE 432U
15209
15210 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
15211 #define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
15212 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
15213
15214 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
15215 #define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
15216
15217 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
15218 #define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
15219
15220
15221 /**
15222 * @}
15223 */
15224
15225 /**
15226 * @}
15227 */
15228
15229 /**
15230 * @}
15231 */
15232
15233 #ifdef __cplusplus
15234 }
15235 #endif /* __cplusplus */
15236
15237 #endif /* __STM32F423xx_H */
15238
15239
15240
15241 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/