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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f415xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F415xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - peripherals registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f415xx
47 * @{
48 */
49
50 #ifndef __STM32F415xx_H
51 #define __STM32F415xx_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #define __FPU_PRESENT 1U /*!< FPU present */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78 /**
79 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
87 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
88 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
89 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
91 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
92 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
93 /****** STM32 specific Interrupt Numbers **********************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
99 RCC_IRQn = 5, /*!< RCC global Interrupt */
100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
112 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
113 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
114 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
115 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
116 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
133 USART3_IRQn = 39, /*!< USART3 global Interrupt */
134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
137 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
138 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
139 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
140 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
141 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
142 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
143 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
144 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
149 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
150 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
151 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
152 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
153 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
154 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
155 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
156 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
157 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
158 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
159 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
160 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
161 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
162 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
163 USART6_IRQn = 71, /*!< USART6 global interrupt */
164 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
165 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
166 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
167 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
168 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
169 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
170 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
171 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
172 FPU_IRQn = 81 /*!< FPU global interrupt */
173 } IRQn_Type;
174
175 /**
176 * @}
177 */
178
179 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
180 #include "system_stm32f4xx.h"
181 #include <stdint.h>
182
183 /** @addtogroup Peripheral_registers_structures
184 * @{
185 */
186
187 /**
188 * @brief Analog to Digital Converter
189 */
190
191 typedef struct
192 {
193 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
194 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
195 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
196 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
197 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
198 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
199 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
200 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
201 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
202 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
203 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
204 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
205 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
206 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
207 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
208 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
209 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
210 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
211 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
212 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
213 } ADC_TypeDef;
214
215 typedef struct
216 {
217 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
218 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
219 __IO uint32_t CDR; /*!< ADC common regular data register for dual
220 AND triple modes, Address offset: ADC1 base address + 0x308 */
221 } ADC_Common_TypeDef;
222
223
224 /**
225 * @brief Controller Area Network TxMailBox
226 */
227
228 typedef struct
229 {
230 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
231 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
232 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
233 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
234 } CAN_TxMailBox_TypeDef;
235
236 /**
237 * @brief Controller Area Network FIFOMailBox
238 */
239
240 typedef struct
241 {
242 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
243 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
244 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
245 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
246 } CAN_FIFOMailBox_TypeDef;
247
248 /**
249 * @brief Controller Area Network FilterRegister
250 */
251
252 typedef struct
253 {
254 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
255 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
256 } CAN_FilterRegister_TypeDef;
257
258 /**
259 * @brief Controller Area Network
260 */
261
262 typedef struct
263 {
264 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
265 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
266 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
267 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
268 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
269 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
270 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
271 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
272 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
273 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
274 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
275 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
276 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
277 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
278 uint32_t RESERVED2; /*!< Reserved, 0x208 */
279 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
280 uint32_t RESERVED3; /*!< Reserved, 0x210 */
281 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
282 uint32_t RESERVED4; /*!< Reserved, 0x218 */
283 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
284 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
285 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
286 } CAN_TypeDef;
287
288 /**
289 * @brief CRC calculation unit
290 */
291
292 typedef struct
293 {
294 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
295 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
296 uint8_t RESERVED0; /*!< Reserved, 0x05 */
297 uint16_t RESERVED1; /*!< Reserved, 0x06 */
298 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
299 } CRC_TypeDef;
300
301 /**
302 * @brief Digital to Analog Converter
303 */
304
305 typedef struct
306 {
307 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
308 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
309 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
310 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
311 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
312 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
313 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
314 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
315 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
316 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
317 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
318 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
319 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
320 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
321 } DAC_TypeDef;
322
323 /**
324 * @brief Debug MCU
325 */
326
327 typedef struct
328 {
329 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
330 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
331 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
332 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
333 }DBGMCU_TypeDef;
334
335
336 /**
337 * @brief DMA Controller
338 */
339
340 typedef struct
341 {
342 __IO uint32_t CR; /*!< DMA stream x configuration register */
343 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
344 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
345 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
346 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
347 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
348 } DMA_Stream_TypeDef;
349
350 typedef struct
351 {
352 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
353 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
354 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
355 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
356 } DMA_TypeDef;
357
358 /**
359 * @brief External Interrupt/Event Controller
360 */
361
362 typedef struct
363 {
364 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
365 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
366 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
367 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
368 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
369 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
370 } EXTI_TypeDef;
371
372 /**
373 * @brief FLASH Registers
374 */
375
376 typedef struct
377 {
378 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
379 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
380 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
381 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
382 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
383 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
384 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
385 } FLASH_TypeDef;
386
387
388
389 /**
390 * @brief Flexible Static Memory Controller
391 */
392
393 typedef struct
394 {
395 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
396 } FSMC_Bank1_TypeDef;
397
398 /**
399 * @brief Flexible Static Memory Controller Bank1E
400 */
401
402 typedef struct
403 {
404 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
405 } FSMC_Bank1E_TypeDef;
406
407 /**
408 * @brief Flexible Static Memory Controller Bank2
409 */
410
411 typedef struct
412 {
413 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
414 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
415 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
416 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
417 uint32_t RESERVED0; /*!< Reserved, 0x70 */
418 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
419 uint32_t RESERVED1; /*!< Reserved, 0x78 */
420 uint32_t RESERVED2; /*!< Reserved, 0x7C */
421 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
422 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
423 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
424 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
425 uint32_t RESERVED3; /*!< Reserved, 0x90 */
426 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
427 } FSMC_Bank2_3_TypeDef;
428
429 /**
430 * @brief Flexible Static Memory Controller Bank4
431 */
432
433 typedef struct
434 {
435 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
436 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
437 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
438 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
439 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
440 } FSMC_Bank4_TypeDef;
441
442 /**
443 * @brief General Purpose I/O
444 */
445
446 typedef struct
447 {
448 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
449 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
450 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
451 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
452 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
453 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
454 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
455 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
456 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
457 } GPIO_TypeDef;
458
459 /**
460 * @brief System configuration controller
461 */
462
463 typedef struct
464 {
465 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
466 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
467 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
468 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
469 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
470 } SYSCFG_TypeDef;
471
472 /**
473 * @brief Inter-integrated Circuit Interface
474 */
475
476 typedef struct
477 {
478 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
479 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
480 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
481 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
482 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
483 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
484 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
485 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
486 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
487 } I2C_TypeDef;
488
489 /**
490 * @brief Independent WATCHDOG
491 */
492
493 typedef struct
494 {
495 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
496 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
497 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
498 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
499 } IWDG_TypeDef;
500
501
502 /**
503 * @brief Power Control
504 */
505
506 typedef struct
507 {
508 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
509 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
510 } PWR_TypeDef;
511
512 /**
513 * @brief Reset and Clock Control
514 */
515
516 typedef struct
517 {
518 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
519 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
520 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
521 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
522 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
523 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
524 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
525 uint32_t RESERVED0; /*!< Reserved, 0x1C */
526 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
527 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
528 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
529 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
530 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
531 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
532 uint32_t RESERVED2; /*!< Reserved, 0x3C */
533 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
534 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
535 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
536 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
537 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
538 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
539 uint32_t RESERVED4; /*!< Reserved, 0x5C */
540 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
541 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
542 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
543 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
544 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
545 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
546 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
547 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
548 } RCC_TypeDef;
549
550 /**
551 * @brief Real-Time Clock
552 */
553
554 typedef struct
555 {
556 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
557 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
558 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
559 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
560 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
561 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
562 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
563 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
564 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
565 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
566 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
567 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
568 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
569 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
570 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
571 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
572 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
573 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
574 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
575 uint32_t RESERVED7; /*!< Reserved, 0x4C */
576 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
577 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
578 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
579 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
580 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
581 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
582 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
583 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
584 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
585 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
586 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
587 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
588 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
589 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
590 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
591 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
592 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
593 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
594 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
595 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
596 } RTC_TypeDef;
597
598 /**
599 * @brief SD host Interface
600 */
601
602 typedef struct
603 {
604 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
605 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
606 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
607 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
608 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
609 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
610 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
611 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
612 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
613 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
614 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
615 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
616 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
617 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
618 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
619 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
620 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
621 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
622 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
623 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
624 } SDIO_TypeDef;
625
626 /**
627 * @brief Serial Peripheral Interface
628 */
629
630 typedef struct
631 {
632 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
633 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
634 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
635 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
636 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
637 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
638 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
639 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
640 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
641 } SPI_TypeDef;
642
643
644 /**
645 * @brief TIM
646 */
647
648 typedef struct
649 {
650 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
651 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
652 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
653 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
654 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
655 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
656 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
657 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
658 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
659 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
660 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
661 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
662 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
663 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
664 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
665 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
666 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
667 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
668 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
669 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
670 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
671 } TIM_TypeDef;
672
673 /**
674 * @brief Universal Synchronous Asynchronous Receiver Transmitter
675 */
676
677 typedef struct
678 {
679 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
680 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
681 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
682 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
683 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
684 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
685 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
686 } USART_TypeDef;
687
688 /**
689 * @brief Window WATCHDOG
690 */
691
692 typedef struct
693 {
694 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
695 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
696 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
697 } WWDG_TypeDef;
698
699 /**
700 * @brief Crypto Processor
701 */
702
703 typedef struct
704 {
705 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
706 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
707 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
708 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
709 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
710 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
711 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
712 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
713 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
714 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
715 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
716 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
717 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
718 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
719 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
720 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
721 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
722 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
723 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
724 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
725 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
726 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
727 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
728 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
729 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
730 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
731 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
732 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
733 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
734 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
735 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
736 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
737 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
738 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
739 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
740 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
741 } CRYP_TypeDef;
742
743 /**
744 * @brief HASH
745 */
746
747 typedef struct
748 {
749 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
750 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
751 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
752 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
753 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
754 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
755 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
756 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
757 } HASH_TypeDef;
758
759 /**
760 * @brief HASH_DIGEST
761 */
762
763 typedef struct
764 {
765 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
766 } HASH_DIGEST_TypeDef;
767
768 /**
769 * @brief RNG
770 */
771
772 typedef struct
773 {
774 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
775 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
776 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
777 } RNG_TypeDef;
778
779 /**
780 * @brief USB_OTG_Core_Registers
781 */
782 typedef struct
783 {
784 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
785 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
786 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
787 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
788 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
789 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
790 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
791 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
792 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
793 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
794 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
795 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
796 uint32_t Reserved30[2]; /*!< Reserved 030h */
797 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
798 __IO uint32_t CID; /*!< User ID Register 03Ch */
799 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
800 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
801 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
802 } USB_OTG_GlobalTypeDef;
803
804 /**
805 * @brief USB_OTG_device_Registers
806 */
807 typedef struct
808 {
809 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
810 __IO uint32_t DCTL; /*!< dev Control Register 804h */
811 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
812 uint32_t Reserved0C; /*!< Reserved 80Ch */
813 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
814 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
815 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
816 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
817 uint32_t Reserved20; /*!< Reserved 820h */
818 uint32_t Reserved9; /*!< Reserved 824h */
819 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
820 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
821 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
822 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
823 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
824 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
825 uint32_t Reserved40; /*!< dedicated EP mask 840h */
826 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
827 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
828 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
829 } USB_OTG_DeviceTypeDef;
830
831 /**
832 * @brief USB_OTG_IN_Endpoint-Specific_Register
833 */
834 typedef struct
835 {
836 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
837 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
838 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
839 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
840 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
841 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
842 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
843 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
844 } USB_OTG_INEndpointTypeDef;
845
846 /**
847 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
848 */
849 typedef struct
850 {
851 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
852 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
853 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
854 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
855 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
856 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
857 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
858 } USB_OTG_OUTEndpointTypeDef;
859
860 /**
861 * @brief USB_OTG_Host_Mode_Register_Structures
862 */
863 typedef struct
864 {
865 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
866 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
867 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
868 uint32_t Reserved40C; /*!< Reserved 40Ch */
869 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
870 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
871 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
872 } USB_OTG_HostTypeDef;
873
874 /**
875 * @brief USB_OTG_Host_Channel_Specific_Registers
876 */
877 typedef struct
878 {
879 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
880 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
881 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
882 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
883 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
884 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
885 uint32_t Reserved[2]; /*!< Reserved */
886 } USB_OTG_HostChannelTypeDef;
887
888 /**
889 * @}
890 */
891
892 /** @addtogroup Peripheral_memory_map
893 * @{
894 */
895 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
896 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
897 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
898 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
899 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
900 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
901 #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
902 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
903 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
904 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
905 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
906 #define FLASH_END 0x080FFFFFU /*!< FLASH end address */
907 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
908 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
909 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
910
911 /* Legacy defines */
912 #define SRAM_BASE SRAM1_BASE
913 #define SRAM_BB_BASE SRAM1_BB_BASE
914
915 /*!< Peripheral memory map */
916 #define APB1PERIPH_BASE PERIPH_BASE
917 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
918 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
919 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
920
921 /*!< APB1 peripherals */
922 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
923 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
924 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
925 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
926 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
927 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
928 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
929 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
930 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
931 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
932 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
933 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
934 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
935 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
936 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
937 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
938 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
939 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
940 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
941 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
942 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
943 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
944 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
945 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
946 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
947 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
948 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
949
950 /*!< APB2 peripherals */
951 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
952 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
953 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
954 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
955 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
956 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
957 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
958 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
959 /* Legacy define */
960 #define ADC_BASE ADC123_COMMON_BASE
961 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
962 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
963 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
964 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
965 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
966 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
967 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
968
969 /*!< AHB1 peripherals */
970 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
971 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
972 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
973 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
974 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
975 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
976 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
977 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
978 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
979 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
980 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
981 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
982 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
983 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
984 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
985 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
986 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
987 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
988 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
989 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
990 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
991 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
992 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
993 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
994 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
995 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
996 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
997 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
998 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
999 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1000
1001 /*!< AHB2 peripherals */
1002 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1003 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1004 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1005 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1006
1007 /*!< FSMC Bankx registers base address */
1008 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
1009 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
1010 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
1011 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
1012
1013
1014 /*!< Debug MCU registers base address */
1015 #define DBGMCU_BASE 0xE0042000U
1016 /*!< USB registers base address */
1017 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1018 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1019
1020 #define USB_OTG_GLOBAL_BASE 0x000U
1021 #define USB_OTG_DEVICE_BASE 0x800U
1022 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1023 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1024 #define USB_OTG_EP_REG_SIZE 0x20U
1025 #define USB_OTG_HOST_BASE 0x400U
1026 #define USB_OTG_HOST_PORT_BASE 0x440U
1027 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1028 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1029 #define USB_OTG_PCGCCTL_BASE 0xE00U
1030 #define USB_OTG_FIFO_BASE 0x1000U
1031 #define USB_OTG_FIFO_SIZE 0x1000U
1032
1033 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
1034 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
1035 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1036 /**
1037 * @}
1038 */
1039
1040 /** @addtogroup Peripheral_declaration
1041 * @{
1042 */
1043 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1044 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1045 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1046 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1047 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1048 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1049 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1050 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1051 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1052 #define RTC ((RTC_TypeDef *) RTC_BASE)
1053 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1054 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1055 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1056 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1057 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1058 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1059 #define USART2 ((USART_TypeDef *) USART2_BASE)
1060 #define USART3 ((USART_TypeDef *) USART3_BASE)
1061 #define UART4 ((USART_TypeDef *) UART4_BASE)
1062 #define UART5 ((USART_TypeDef *) UART5_BASE)
1063 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1064 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1065 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1066 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1067 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1068 #define PWR ((PWR_TypeDef *) PWR_BASE)
1069 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1070 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1071 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1072 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1073 #define USART1 ((USART_TypeDef *) USART1_BASE)
1074 #define USART6 ((USART_TypeDef *) USART6_BASE)
1075 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1076 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1077 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1078 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1079 /* Legacy define */
1080 #define ADC ADC123_COMMON
1081 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1082 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1083 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1084 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1085 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1086 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1087 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1088 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1089 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1090 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1091 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1092 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1093 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1094 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1095 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1096 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1097 #define CRC ((CRC_TypeDef *) CRC_BASE)
1098 #define RCC ((RCC_TypeDef *) RCC_BASE)
1099 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1100 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1101 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1102 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1103 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1104 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1105 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1106 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1107 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1108 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1109 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1110 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1111 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1112 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1113 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1114 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1115 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1116 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1117 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1118 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1119 #define HASH ((HASH_TypeDef *) HASH_BASE)
1120 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1121 #define RNG ((RNG_TypeDef *) RNG_BASE)
1122 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1123 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1124 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1125 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1126 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1127 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1128 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1129
1130 /**
1131 * @}
1132 */
1133
1134 /** @addtogroup Exported_constants
1135 * @{
1136 */
1137
1138 /** @addtogroup Peripheral_Registers_Bits_Definition
1139 * @{
1140 */
1141
1142 /******************************************************************************/
1143 /* Peripheral Registers_Bits_Definition */
1144 /******************************************************************************/
1145
1146 /******************************************************************************/
1147 /* */
1148 /* Analog to Digital Converter */
1149 /* */
1150 /******************************************************************************/
1151 /*
1152 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1153 */
1154 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
1155
1156 /******************** Bit definition for ADC_SR register ********************/
1157 #define ADC_SR_AWD_Pos (0U)
1158 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1159 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1160 #define ADC_SR_EOC_Pos (1U)
1161 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1162 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1163 #define ADC_SR_JEOC_Pos (2U)
1164 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1165 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1166 #define ADC_SR_JSTRT_Pos (3U)
1167 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1168 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1169 #define ADC_SR_STRT_Pos (4U)
1170 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1171 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1172 #define ADC_SR_OVR_Pos (5U)
1173 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1174 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1175
1176 /******************* Bit definition for ADC_CR1 register ********************/
1177 #define ADC_CR1_AWDCH_Pos (0U)
1178 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1179 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1180 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1181 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1182 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1183 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1184 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1185 #define ADC_CR1_EOCIE_Pos (5U)
1186 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1187 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1188 #define ADC_CR1_AWDIE_Pos (6U)
1189 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1190 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1191 #define ADC_CR1_JEOCIE_Pos (7U)
1192 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1193 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1194 #define ADC_CR1_SCAN_Pos (8U)
1195 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1196 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1197 #define ADC_CR1_AWDSGL_Pos (9U)
1198 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1199 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1200 #define ADC_CR1_JAUTO_Pos (10U)
1201 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1202 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1203 #define ADC_CR1_DISCEN_Pos (11U)
1204 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1205 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1206 #define ADC_CR1_JDISCEN_Pos (12U)
1207 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1208 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1209 #define ADC_CR1_DISCNUM_Pos (13U)
1210 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1211 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1212 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1213 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1214 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1215 #define ADC_CR1_JAWDEN_Pos (22U)
1216 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1217 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1218 #define ADC_CR1_AWDEN_Pos (23U)
1219 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1220 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1221 #define ADC_CR1_RES_Pos (24U)
1222 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1223 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1224 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1225 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1226 #define ADC_CR1_OVRIE_Pos (26U)
1227 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1228 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1229
1230 /******************* Bit definition for ADC_CR2 register ********************/
1231 #define ADC_CR2_ADON_Pos (0U)
1232 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1233 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1234 #define ADC_CR2_CONT_Pos (1U)
1235 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1236 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1237 #define ADC_CR2_DMA_Pos (8U)
1238 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1239 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1240 #define ADC_CR2_DDS_Pos (9U)
1241 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1242 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1243 #define ADC_CR2_EOCS_Pos (10U)
1244 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1245 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1246 #define ADC_CR2_ALIGN_Pos (11U)
1247 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1248 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1249 #define ADC_CR2_JEXTSEL_Pos (16U)
1250 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1251 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1252 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1253 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1254 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1255 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1256 #define ADC_CR2_JEXTEN_Pos (20U)
1257 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1258 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1259 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1260 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1261 #define ADC_CR2_JSWSTART_Pos (22U)
1262 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1263 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1264 #define ADC_CR2_EXTSEL_Pos (24U)
1265 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1266 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1267 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1268 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1269 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1270 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1271 #define ADC_CR2_EXTEN_Pos (28U)
1272 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1273 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1274 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1275 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1276 #define ADC_CR2_SWSTART_Pos (30U)
1277 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1278 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1279
1280 /****************** Bit definition for ADC_SMPR1 register *******************/
1281 #define ADC_SMPR1_SMP10_Pos (0U)
1282 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1283 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1284 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1285 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1286 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1287 #define ADC_SMPR1_SMP11_Pos (3U)
1288 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1289 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1290 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1291 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1292 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1293 #define ADC_SMPR1_SMP12_Pos (6U)
1294 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1295 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1296 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1297 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1298 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1299 #define ADC_SMPR1_SMP13_Pos (9U)
1300 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1301 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1302 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1303 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1304 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1305 #define ADC_SMPR1_SMP14_Pos (12U)
1306 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1307 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1308 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1309 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1310 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1311 #define ADC_SMPR1_SMP15_Pos (15U)
1312 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1313 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1314 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1315 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1316 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1317 #define ADC_SMPR1_SMP16_Pos (18U)
1318 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1319 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1320 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1321 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1322 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1323 #define ADC_SMPR1_SMP17_Pos (21U)
1324 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1325 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1326 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1327 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1328 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1329 #define ADC_SMPR1_SMP18_Pos (24U)
1330 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1331 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1332 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1333 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1334 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1335
1336 /****************** Bit definition for ADC_SMPR2 register *******************/
1337 #define ADC_SMPR2_SMP0_Pos (0U)
1338 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1339 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1340 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1341 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1342 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1343 #define ADC_SMPR2_SMP1_Pos (3U)
1344 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1345 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1346 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1347 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1348 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1349 #define ADC_SMPR2_SMP2_Pos (6U)
1350 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1351 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1352 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1353 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1354 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1355 #define ADC_SMPR2_SMP3_Pos (9U)
1356 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1357 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1358 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1359 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1360 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1361 #define ADC_SMPR2_SMP4_Pos (12U)
1362 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1363 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1364 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1365 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1366 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1367 #define ADC_SMPR2_SMP5_Pos (15U)
1368 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1369 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1370 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1371 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1372 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1373 #define ADC_SMPR2_SMP6_Pos (18U)
1374 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1375 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1376 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1377 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1378 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1379 #define ADC_SMPR2_SMP7_Pos (21U)
1380 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1381 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1382 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1383 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1384 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1385 #define ADC_SMPR2_SMP8_Pos (24U)
1386 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1387 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1388 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1389 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1390 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1391 #define ADC_SMPR2_SMP9_Pos (27U)
1392 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1393 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1394 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1395 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1396 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1397
1398 /****************** Bit definition for ADC_JOFR1 register *******************/
1399 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1400 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1401 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1402
1403 /****************** Bit definition for ADC_JOFR2 register *******************/
1404 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1405 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1406 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1407
1408 /****************** Bit definition for ADC_JOFR3 register *******************/
1409 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1410 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1411 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1412
1413 /****************** Bit definition for ADC_JOFR4 register *******************/
1414 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1415 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1416 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1417
1418 /******************* Bit definition for ADC_HTR register ********************/
1419 #define ADC_HTR_HT_Pos (0U)
1420 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1421 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1422
1423 /******************* Bit definition for ADC_LTR register ********************/
1424 #define ADC_LTR_LT_Pos (0U)
1425 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1426 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1427
1428 /******************* Bit definition for ADC_SQR1 register *******************/
1429 #define ADC_SQR1_SQ13_Pos (0U)
1430 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1431 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1432 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1433 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1434 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1435 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1436 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1437 #define ADC_SQR1_SQ14_Pos (5U)
1438 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1439 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1440 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1441 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1442 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1443 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1444 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1445 #define ADC_SQR1_SQ15_Pos (10U)
1446 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1447 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1448 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1449 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1450 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1451 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1452 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1453 #define ADC_SQR1_SQ16_Pos (15U)
1454 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1455 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1456 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1457 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1458 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1459 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1460 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1461 #define ADC_SQR1_L_Pos (20U)
1462 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1463 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1464 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1465 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1466 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1467 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1468
1469 /******************* Bit definition for ADC_SQR2 register *******************/
1470 #define ADC_SQR2_SQ7_Pos (0U)
1471 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1472 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1473 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1474 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1475 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1476 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1477 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1478 #define ADC_SQR2_SQ8_Pos (5U)
1479 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1480 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1481 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1482 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1483 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1484 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1485 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1486 #define ADC_SQR2_SQ9_Pos (10U)
1487 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1488 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1489 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1490 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1491 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1492 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1493 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1494 #define ADC_SQR2_SQ10_Pos (15U)
1495 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1496 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1497 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1498 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1499 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1500 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1501 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1502 #define ADC_SQR2_SQ11_Pos (20U)
1503 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1504 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1505 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1506 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1507 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1508 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1509 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1510 #define ADC_SQR2_SQ12_Pos (25U)
1511 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1512 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1513 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1514 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1515 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1516 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1517 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1518
1519 /******************* Bit definition for ADC_SQR3 register *******************/
1520 #define ADC_SQR3_SQ1_Pos (0U)
1521 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1522 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1523 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1524 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1525 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1526 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1527 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1528 #define ADC_SQR3_SQ2_Pos (5U)
1529 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1530 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1531 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1532 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1533 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1534 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1535 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1536 #define ADC_SQR3_SQ3_Pos (10U)
1537 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1538 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1539 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1540 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1541 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1542 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1543 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1544 #define ADC_SQR3_SQ4_Pos (15U)
1545 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1546 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1547 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1548 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1549 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1550 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1551 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1552 #define ADC_SQR3_SQ5_Pos (20U)
1553 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1554 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1555 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1556 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1557 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1558 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1559 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1560 #define ADC_SQR3_SQ6_Pos (25U)
1561 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1562 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1563 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1564 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1565 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1566 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1567 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1568
1569 /******************* Bit definition for ADC_JSQR register *******************/
1570 #define ADC_JSQR_JSQ1_Pos (0U)
1571 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1572 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1573 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1574 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1575 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1576 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1577 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1578 #define ADC_JSQR_JSQ2_Pos (5U)
1579 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1580 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1581 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1582 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1583 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1584 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1585 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1586 #define ADC_JSQR_JSQ3_Pos (10U)
1587 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1588 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1589 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1590 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1591 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1592 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1593 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1594 #define ADC_JSQR_JSQ4_Pos (15U)
1595 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1596 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1597 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1598 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1599 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1600 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1601 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1602 #define ADC_JSQR_JL_Pos (20U)
1603 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1604 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1605 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1606 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1607
1608 /******************* Bit definition for ADC_JDR1 register *******************/
1609 #define ADC_JDR1_JDATA_Pos (0U)
1610 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1611 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1612
1613 /******************* Bit definition for ADC_JDR2 register *******************/
1614 #define ADC_JDR2_JDATA_Pos (0U)
1615 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1616 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1617
1618 /******************* Bit definition for ADC_JDR3 register *******************/
1619 #define ADC_JDR3_JDATA_Pos (0U)
1620 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1621 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1622
1623 /******************* Bit definition for ADC_JDR4 register *******************/
1624 #define ADC_JDR4_JDATA_Pos (0U)
1625 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1626 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1627
1628 /******************** Bit definition for ADC_DR register ********************/
1629 #define ADC_DR_DATA_Pos (0U)
1630 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1631 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1632 #define ADC_DR_ADC2DATA_Pos (16U)
1633 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1634 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1635
1636 /******************* Bit definition for ADC_CSR register ********************/
1637 #define ADC_CSR_AWD1_Pos (0U)
1638 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1639 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1640 #define ADC_CSR_EOC1_Pos (1U)
1641 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1642 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1643 #define ADC_CSR_JEOC1_Pos (2U)
1644 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1645 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1646 #define ADC_CSR_JSTRT1_Pos (3U)
1647 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1648 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1649 #define ADC_CSR_STRT1_Pos (4U)
1650 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1651 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1652 #define ADC_CSR_OVR1_Pos (5U)
1653 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1654 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1655 #define ADC_CSR_AWD2_Pos (8U)
1656 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
1657 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
1658 #define ADC_CSR_EOC2_Pos (9U)
1659 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
1660 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
1661 #define ADC_CSR_JEOC2_Pos (10U)
1662 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
1663 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
1664 #define ADC_CSR_JSTRT2_Pos (11U)
1665 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
1666 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
1667 #define ADC_CSR_STRT2_Pos (12U)
1668 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
1669 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
1670 #define ADC_CSR_OVR2_Pos (13U)
1671 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
1672 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
1673 #define ADC_CSR_AWD3_Pos (16U)
1674 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
1675 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
1676 #define ADC_CSR_EOC3_Pos (17U)
1677 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
1678 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
1679 #define ADC_CSR_JEOC3_Pos (18U)
1680 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
1681 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
1682 #define ADC_CSR_JSTRT3_Pos (19U)
1683 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
1684 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
1685 #define ADC_CSR_STRT3_Pos (20U)
1686 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
1687 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
1688 #define ADC_CSR_OVR3_Pos (21U)
1689 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
1690 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
1691
1692 /* Legacy defines */
1693 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1694 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1695 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1696
1697 /******************* Bit definition for ADC_CCR register ********************/
1698 #define ADC_CCR_MULTI_Pos (0U)
1699 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1700 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1701 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1702 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1703 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1704 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1705 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1706 #define ADC_CCR_DELAY_Pos (8U)
1707 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1708 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1709 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1710 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1711 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1712 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1713 #define ADC_CCR_DDS_Pos (13U)
1714 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1715 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1716 #define ADC_CCR_DMA_Pos (14U)
1717 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1718 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1719 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1720 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1721 #define ADC_CCR_ADCPRE_Pos (16U)
1722 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1723 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1724 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1725 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1726 #define ADC_CCR_VBATE_Pos (22U)
1727 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1728 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1729 #define ADC_CCR_TSVREFE_Pos (23U)
1730 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1731 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1732
1733 /******************* Bit definition for ADC_CDR register ********************/
1734 #define ADC_CDR_DATA1_Pos (0U)
1735 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1736 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1737 #define ADC_CDR_DATA2_Pos (16U)
1738 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1739 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1740
1741 /* Legacy defines */
1742 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1743 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1744
1745 /******************************************************************************/
1746 /* */
1747 /* Controller Area Network */
1748 /* */
1749 /******************************************************************************/
1750 /*!<CAN control and status registers */
1751 /******************* Bit definition for CAN_MCR register ********************/
1752 #define CAN_MCR_INRQ_Pos (0U)
1753 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
1754 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
1755 #define CAN_MCR_SLEEP_Pos (1U)
1756 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
1757 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
1758 #define CAN_MCR_TXFP_Pos (2U)
1759 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
1760 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
1761 #define CAN_MCR_RFLM_Pos (3U)
1762 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
1763 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
1764 #define CAN_MCR_NART_Pos (4U)
1765 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
1766 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
1767 #define CAN_MCR_AWUM_Pos (5U)
1768 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
1769 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
1770 #define CAN_MCR_ABOM_Pos (6U)
1771 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
1772 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
1773 #define CAN_MCR_TTCM_Pos (7U)
1774 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
1775 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
1776 #define CAN_MCR_RESET_Pos (15U)
1777 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
1778 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
1779 #define CAN_MCR_DBF_Pos (16U)
1780 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
1781 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
1782 /******************* Bit definition for CAN_MSR register ********************/
1783 #define CAN_MSR_INAK_Pos (0U)
1784 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
1785 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
1786 #define CAN_MSR_SLAK_Pos (1U)
1787 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
1788 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
1789 #define CAN_MSR_ERRI_Pos (2U)
1790 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
1791 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
1792 #define CAN_MSR_WKUI_Pos (3U)
1793 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
1794 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
1795 #define CAN_MSR_SLAKI_Pos (4U)
1796 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
1797 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
1798 #define CAN_MSR_TXM_Pos (8U)
1799 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
1800 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
1801 #define CAN_MSR_RXM_Pos (9U)
1802 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
1803 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
1804 #define CAN_MSR_SAMP_Pos (10U)
1805 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
1806 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
1807 #define CAN_MSR_RX_Pos (11U)
1808 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
1809 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
1810
1811 /******************* Bit definition for CAN_TSR register ********************/
1812 #define CAN_TSR_RQCP0_Pos (0U)
1813 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
1814 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
1815 #define CAN_TSR_TXOK0_Pos (1U)
1816 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
1817 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
1818 #define CAN_TSR_ALST0_Pos (2U)
1819 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
1820 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
1821 #define CAN_TSR_TERR0_Pos (3U)
1822 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
1823 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
1824 #define CAN_TSR_ABRQ0_Pos (7U)
1825 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
1826 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
1827 #define CAN_TSR_RQCP1_Pos (8U)
1828 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
1829 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
1830 #define CAN_TSR_TXOK1_Pos (9U)
1831 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
1832 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
1833 #define CAN_TSR_ALST1_Pos (10U)
1834 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
1835 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
1836 #define CAN_TSR_TERR1_Pos (11U)
1837 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
1838 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
1839 #define CAN_TSR_ABRQ1_Pos (15U)
1840 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
1841 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
1842 #define CAN_TSR_RQCP2_Pos (16U)
1843 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
1844 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
1845 #define CAN_TSR_TXOK2_Pos (17U)
1846 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
1847 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
1848 #define CAN_TSR_ALST2_Pos (18U)
1849 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
1850 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
1851 #define CAN_TSR_TERR2_Pos (19U)
1852 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
1853 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
1854 #define CAN_TSR_ABRQ2_Pos (23U)
1855 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
1856 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
1857 #define CAN_TSR_CODE_Pos (24U)
1858 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
1859 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
1860
1861 #define CAN_TSR_TME_Pos (26U)
1862 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
1863 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
1864 #define CAN_TSR_TME0_Pos (26U)
1865 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
1866 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
1867 #define CAN_TSR_TME1_Pos (27U)
1868 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
1869 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
1870 #define CAN_TSR_TME2_Pos (28U)
1871 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
1872 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
1873
1874 #define CAN_TSR_LOW_Pos (29U)
1875 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
1876 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
1877 #define CAN_TSR_LOW0_Pos (29U)
1878 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
1879 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
1880 #define CAN_TSR_LOW1_Pos (30U)
1881 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
1882 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
1883 #define CAN_TSR_LOW2_Pos (31U)
1884 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
1885 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
1886
1887 /******************* Bit definition for CAN_RF0R register *******************/
1888 #define CAN_RF0R_FMP0_Pos (0U)
1889 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
1890 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
1891 #define CAN_RF0R_FULL0_Pos (3U)
1892 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
1893 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
1894 #define CAN_RF0R_FOVR0_Pos (4U)
1895 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
1896 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
1897 #define CAN_RF0R_RFOM0_Pos (5U)
1898 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
1899 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
1900
1901 /******************* Bit definition for CAN_RF1R register *******************/
1902 #define CAN_RF1R_FMP1_Pos (0U)
1903 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
1904 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
1905 #define CAN_RF1R_FULL1_Pos (3U)
1906 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
1907 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
1908 #define CAN_RF1R_FOVR1_Pos (4U)
1909 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
1910 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
1911 #define CAN_RF1R_RFOM1_Pos (5U)
1912 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
1913 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
1914
1915 /******************** Bit definition for CAN_IER register *******************/
1916 #define CAN_IER_TMEIE_Pos (0U)
1917 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
1918 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
1919 #define CAN_IER_FMPIE0_Pos (1U)
1920 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
1921 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
1922 #define CAN_IER_FFIE0_Pos (2U)
1923 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
1924 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
1925 #define CAN_IER_FOVIE0_Pos (3U)
1926 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
1927 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
1928 #define CAN_IER_FMPIE1_Pos (4U)
1929 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
1930 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
1931 #define CAN_IER_FFIE1_Pos (5U)
1932 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
1933 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
1934 #define CAN_IER_FOVIE1_Pos (6U)
1935 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
1936 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
1937 #define CAN_IER_EWGIE_Pos (8U)
1938 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
1939 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
1940 #define CAN_IER_EPVIE_Pos (9U)
1941 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
1942 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
1943 #define CAN_IER_BOFIE_Pos (10U)
1944 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
1945 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
1946 #define CAN_IER_LECIE_Pos (11U)
1947 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
1948 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
1949 #define CAN_IER_ERRIE_Pos (15U)
1950 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
1951 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
1952 #define CAN_IER_WKUIE_Pos (16U)
1953 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
1954 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
1955 #define CAN_IER_SLKIE_Pos (17U)
1956 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
1957 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
1958 #define CAN_IER_EWGIE_Pos (8U)
1959
1960 /******************** Bit definition for CAN_ESR register *******************/
1961 #define CAN_ESR_EWGF_Pos (0U)
1962 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
1963 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
1964 #define CAN_ESR_EPVF_Pos (1U)
1965 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
1966 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
1967 #define CAN_ESR_BOFF_Pos (2U)
1968 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
1969 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
1970
1971 #define CAN_ESR_LEC_Pos (4U)
1972 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
1973 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
1974 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
1975 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
1976 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
1977
1978 #define CAN_ESR_TEC_Pos (16U)
1979 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
1980 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
1981 #define CAN_ESR_REC_Pos (24U)
1982 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
1983 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
1984
1985 /******************* Bit definition for CAN_BTR register ********************/
1986 #define CAN_BTR_BRP_Pos (0U)
1987 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
1988 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
1989 #define CAN_BTR_TS1_Pos (16U)
1990 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
1991 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
1992 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
1993 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
1994 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
1995 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
1996 #define CAN_BTR_TS2_Pos (20U)
1997 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
1998 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
1999 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2000 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2001 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2002 #define CAN_BTR_SJW_Pos (24U)
2003 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2004 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2005 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2006 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2007 #define CAN_BTR_LBKM_Pos (30U)
2008 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2009 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2010 #define CAN_BTR_SILM_Pos (31U)
2011 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2012 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2013
2014
2015 /*!<Mailbox registers */
2016 /****************** Bit definition for CAN_TI0R register ********************/
2017 #define CAN_TI0R_TXRQ_Pos (0U)
2018 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2019 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2020 #define CAN_TI0R_RTR_Pos (1U)
2021 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2022 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2023 #define CAN_TI0R_IDE_Pos (2U)
2024 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2025 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2026 #define CAN_TI0R_EXID_Pos (3U)
2027 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2028 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2029 #define CAN_TI0R_STID_Pos (21U)
2030 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2031 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2032
2033 /****************** Bit definition for CAN_TDT0R register *******************/
2034 #define CAN_TDT0R_DLC_Pos (0U)
2035 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2036 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2037 #define CAN_TDT0R_TGT_Pos (8U)
2038 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2039 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2040 #define CAN_TDT0R_TIME_Pos (16U)
2041 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2042 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2043
2044 /****************** Bit definition for CAN_TDL0R register *******************/
2045 #define CAN_TDL0R_DATA0_Pos (0U)
2046 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2047 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2048 #define CAN_TDL0R_DATA1_Pos (8U)
2049 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2050 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2051 #define CAN_TDL0R_DATA2_Pos (16U)
2052 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2053 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2054 #define CAN_TDL0R_DATA3_Pos (24U)
2055 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2056 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2057
2058 /****************** Bit definition for CAN_TDH0R register *******************/
2059 #define CAN_TDH0R_DATA4_Pos (0U)
2060 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2061 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2062 #define CAN_TDH0R_DATA5_Pos (8U)
2063 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2064 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2065 #define CAN_TDH0R_DATA6_Pos (16U)
2066 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2067 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2068 #define CAN_TDH0R_DATA7_Pos (24U)
2069 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2070 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2071
2072 /******************* Bit definition for CAN_TI1R register *******************/
2073 #define CAN_TI1R_TXRQ_Pos (0U)
2074 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2075 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2076 #define CAN_TI1R_RTR_Pos (1U)
2077 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2078 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2079 #define CAN_TI1R_IDE_Pos (2U)
2080 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2081 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2082 #define CAN_TI1R_EXID_Pos (3U)
2083 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2084 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2085 #define CAN_TI1R_STID_Pos (21U)
2086 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2087 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2088
2089 /******************* Bit definition for CAN_TDT1R register ******************/
2090 #define CAN_TDT1R_DLC_Pos (0U)
2091 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2092 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2093 #define CAN_TDT1R_TGT_Pos (8U)
2094 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2095 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2096 #define CAN_TDT1R_TIME_Pos (16U)
2097 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2098 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2099
2100 /******************* Bit definition for CAN_TDL1R register ******************/
2101 #define CAN_TDL1R_DATA0_Pos (0U)
2102 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2103 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2104 #define CAN_TDL1R_DATA1_Pos (8U)
2105 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2106 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2107 #define CAN_TDL1R_DATA2_Pos (16U)
2108 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2109 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2110 #define CAN_TDL1R_DATA3_Pos (24U)
2111 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2112 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2113
2114 /******************* Bit definition for CAN_TDH1R register ******************/
2115 #define CAN_TDH1R_DATA4_Pos (0U)
2116 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2117 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2118 #define CAN_TDH1R_DATA5_Pos (8U)
2119 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2120 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2121 #define CAN_TDH1R_DATA6_Pos (16U)
2122 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2123 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2124 #define CAN_TDH1R_DATA7_Pos (24U)
2125 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2126 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2127
2128 /******************* Bit definition for CAN_TI2R register *******************/
2129 #define CAN_TI2R_TXRQ_Pos (0U)
2130 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2131 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2132 #define CAN_TI2R_RTR_Pos (1U)
2133 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2134 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2135 #define CAN_TI2R_IDE_Pos (2U)
2136 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2137 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2138 #define CAN_TI2R_EXID_Pos (3U)
2139 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2140 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2141 #define CAN_TI2R_STID_Pos (21U)
2142 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2143 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2144
2145 /******************* Bit definition for CAN_TDT2R register ******************/
2146 #define CAN_TDT2R_DLC_Pos (0U)
2147 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2148 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2149 #define CAN_TDT2R_TGT_Pos (8U)
2150 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2151 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2152 #define CAN_TDT2R_TIME_Pos (16U)
2153 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2154 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2155
2156 /******************* Bit definition for CAN_TDL2R register ******************/
2157 #define CAN_TDL2R_DATA0_Pos (0U)
2158 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2159 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2160 #define CAN_TDL2R_DATA1_Pos (8U)
2161 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2162 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2163 #define CAN_TDL2R_DATA2_Pos (16U)
2164 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2165 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2166 #define CAN_TDL2R_DATA3_Pos (24U)
2167 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2168 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2169
2170 /******************* Bit definition for CAN_TDH2R register ******************/
2171 #define CAN_TDH2R_DATA4_Pos (0U)
2172 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2173 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2174 #define CAN_TDH2R_DATA5_Pos (8U)
2175 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2176 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2177 #define CAN_TDH2R_DATA6_Pos (16U)
2178 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2179 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2180 #define CAN_TDH2R_DATA7_Pos (24U)
2181 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2182 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2183
2184 /******************* Bit definition for CAN_RI0R register *******************/
2185 #define CAN_RI0R_RTR_Pos (1U)
2186 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2187 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2188 #define CAN_RI0R_IDE_Pos (2U)
2189 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2190 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2191 #define CAN_RI0R_EXID_Pos (3U)
2192 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2193 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2194 #define CAN_RI0R_STID_Pos (21U)
2195 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2196 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2197
2198 /******************* Bit definition for CAN_RDT0R register ******************/
2199 #define CAN_RDT0R_DLC_Pos (0U)
2200 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2201 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2202 #define CAN_RDT0R_FMI_Pos (8U)
2203 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2204 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2205 #define CAN_RDT0R_TIME_Pos (16U)
2206 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2207 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2208
2209 /******************* Bit definition for CAN_RDL0R register ******************/
2210 #define CAN_RDL0R_DATA0_Pos (0U)
2211 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2212 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2213 #define CAN_RDL0R_DATA1_Pos (8U)
2214 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2215 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2216 #define CAN_RDL0R_DATA2_Pos (16U)
2217 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2218 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2219 #define CAN_RDL0R_DATA3_Pos (24U)
2220 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2221 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2222
2223 /******************* Bit definition for CAN_RDH0R register ******************/
2224 #define CAN_RDH0R_DATA4_Pos (0U)
2225 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2226 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2227 #define CAN_RDH0R_DATA5_Pos (8U)
2228 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2229 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2230 #define CAN_RDH0R_DATA6_Pos (16U)
2231 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2232 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2233 #define CAN_RDH0R_DATA7_Pos (24U)
2234 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2235 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2236
2237 /******************* Bit definition for CAN_RI1R register *******************/
2238 #define CAN_RI1R_RTR_Pos (1U)
2239 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2240 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2241 #define CAN_RI1R_IDE_Pos (2U)
2242 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2243 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2244 #define CAN_RI1R_EXID_Pos (3U)
2245 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2246 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2247 #define CAN_RI1R_STID_Pos (21U)
2248 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2249 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2250
2251 /******************* Bit definition for CAN_RDT1R register ******************/
2252 #define CAN_RDT1R_DLC_Pos (0U)
2253 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2254 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2255 #define CAN_RDT1R_FMI_Pos (8U)
2256 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2257 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2258 #define CAN_RDT1R_TIME_Pos (16U)
2259 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2260 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2261
2262 /******************* Bit definition for CAN_RDL1R register ******************/
2263 #define CAN_RDL1R_DATA0_Pos (0U)
2264 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2265 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2266 #define CAN_RDL1R_DATA1_Pos (8U)
2267 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2268 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2269 #define CAN_RDL1R_DATA2_Pos (16U)
2270 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2271 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2272 #define CAN_RDL1R_DATA3_Pos (24U)
2273 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2274 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2275
2276 /******************* Bit definition for CAN_RDH1R register ******************/
2277 #define CAN_RDH1R_DATA4_Pos (0U)
2278 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2279 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2280 #define CAN_RDH1R_DATA5_Pos (8U)
2281 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2282 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2283 #define CAN_RDH1R_DATA6_Pos (16U)
2284 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2285 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2286 #define CAN_RDH1R_DATA7_Pos (24U)
2287 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2288 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2289
2290 /*!<CAN filter registers */
2291 /******************* Bit definition for CAN_FMR register ********************/
2292 #define CAN_FMR_FINIT_Pos (0U)
2293 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2294 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2295 #define CAN_FMR_CAN2SB_Pos (8U)
2296 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2297 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2298
2299 /******************* Bit definition for CAN_FM1R register *******************/
2300 #define CAN_FM1R_FBM_Pos (0U)
2301 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2302 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2303 #define CAN_FM1R_FBM0_Pos (0U)
2304 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2305 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2306 #define CAN_FM1R_FBM1_Pos (1U)
2307 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2308 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2309 #define CAN_FM1R_FBM2_Pos (2U)
2310 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2311 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2312 #define CAN_FM1R_FBM3_Pos (3U)
2313 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2314 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2315 #define CAN_FM1R_FBM4_Pos (4U)
2316 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2317 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2318 #define CAN_FM1R_FBM5_Pos (5U)
2319 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2320 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2321 #define CAN_FM1R_FBM6_Pos (6U)
2322 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2323 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2324 #define CAN_FM1R_FBM7_Pos (7U)
2325 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2326 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2327 #define CAN_FM1R_FBM8_Pos (8U)
2328 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2329 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2330 #define CAN_FM1R_FBM9_Pos (9U)
2331 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2332 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2333 #define CAN_FM1R_FBM10_Pos (10U)
2334 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2335 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2336 #define CAN_FM1R_FBM11_Pos (11U)
2337 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2338 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2339 #define CAN_FM1R_FBM12_Pos (12U)
2340 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2341 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2342 #define CAN_FM1R_FBM13_Pos (13U)
2343 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2344 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2345 #define CAN_FM1R_FBM14_Pos (14U)
2346 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2347 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2348 #define CAN_FM1R_FBM15_Pos (15U)
2349 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2350 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2351 #define CAN_FM1R_FBM16_Pos (16U)
2352 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2353 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2354 #define CAN_FM1R_FBM17_Pos (17U)
2355 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2356 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2357 #define CAN_FM1R_FBM18_Pos (18U)
2358 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2359 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2360 #define CAN_FM1R_FBM19_Pos (19U)
2361 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2362 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2363 #define CAN_FM1R_FBM20_Pos (20U)
2364 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2365 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2366 #define CAN_FM1R_FBM21_Pos (21U)
2367 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2368 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2369 #define CAN_FM1R_FBM22_Pos (22U)
2370 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2371 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2372 #define CAN_FM1R_FBM23_Pos (23U)
2373 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2374 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2375 #define CAN_FM1R_FBM24_Pos (24U)
2376 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2377 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2378 #define CAN_FM1R_FBM25_Pos (25U)
2379 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2380 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2381 #define CAN_FM1R_FBM26_Pos (26U)
2382 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2383 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2384 #define CAN_FM1R_FBM27_Pos (27U)
2385 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2386 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2387
2388 /******************* Bit definition for CAN_FS1R register *******************/
2389 #define CAN_FS1R_FSC_Pos (0U)
2390 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2391 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2392 #define CAN_FS1R_FSC0_Pos (0U)
2393 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2394 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2395 #define CAN_FS1R_FSC1_Pos (1U)
2396 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2397 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2398 #define CAN_FS1R_FSC2_Pos (2U)
2399 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2400 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2401 #define CAN_FS1R_FSC3_Pos (3U)
2402 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2403 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2404 #define CAN_FS1R_FSC4_Pos (4U)
2405 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2406 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2407 #define CAN_FS1R_FSC5_Pos (5U)
2408 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2409 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2410 #define CAN_FS1R_FSC6_Pos (6U)
2411 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2412 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2413 #define CAN_FS1R_FSC7_Pos (7U)
2414 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2415 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2416 #define CAN_FS1R_FSC8_Pos (8U)
2417 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2418 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2419 #define CAN_FS1R_FSC9_Pos (9U)
2420 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2421 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2422 #define CAN_FS1R_FSC10_Pos (10U)
2423 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2424 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2425 #define CAN_FS1R_FSC11_Pos (11U)
2426 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2427 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2428 #define CAN_FS1R_FSC12_Pos (12U)
2429 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2430 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2431 #define CAN_FS1R_FSC13_Pos (13U)
2432 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2433 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2434 #define CAN_FS1R_FSC14_Pos (14U)
2435 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2436 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2437 #define CAN_FS1R_FSC15_Pos (15U)
2438 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2439 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2440 #define CAN_FS1R_FSC16_Pos (16U)
2441 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2442 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2443 #define CAN_FS1R_FSC17_Pos (17U)
2444 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2445 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2446 #define CAN_FS1R_FSC18_Pos (18U)
2447 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2448 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2449 #define CAN_FS1R_FSC19_Pos (19U)
2450 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2451 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2452 #define CAN_FS1R_FSC20_Pos (20U)
2453 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2454 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2455 #define CAN_FS1R_FSC21_Pos (21U)
2456 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2457 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2458 #define CAN_FS1R_FSC22_Pos (22U)
2459 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2460 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2461 #define CAN_FS1R_FSC23_Pos (23U)
2462 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2463 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2464 #define CAN_FS1R_FSC24_Pos (24U)
2465 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2466 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2467 #define CAN_FS1R_FSC25_Pos (25U)
2468 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2469 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2470 #define CAN_FS1R_FSC26_Pos (26U)
2471 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2472 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2473 #define CAN_FS1R_FSC27_Pos (27U)
2474 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2475 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2476
2477 /****************** Bit definition for CAN_FFA1R register *******************/
2478 #define CAN_FFA1R_FFA_Pos (0U)
2479 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2480 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2481 #define CAN_FFA1R_FFA0_Pos (0U)
2482 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2483 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2484 #define CAN_FFA1R_FFA1_Pos (1U)
2485 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2486 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2487 #define CAN_FFA1R_FFA2_Pos (2U)
2488 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2489 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2490 #define CAN_FFA1R_FFA3_Pos (3U)
2491 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2492 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2493 #define CAN_FFA1R_FFA4_Pos (4U)
2494 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2495 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2496 #define CAN_FFA1R_FFA5_Pos (5U)
2497 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2498 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2499 #define CAN_FFA1R_FFA6_Pos (6U)
2500 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2501 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2502 #define CAN_FFA1R_FFA7_Pos (7U)
2503 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2504 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2505 #define CAN_FFA1R_FFA8_Pos (8U)
2506 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2507 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2508 #define CAN_FFA1R_FFA9_Pos (9U)
2509 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2510 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2511 #define CAN_FFA1R_FFA10_Pos (10U)
2512 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2513 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2514 #define CAN_FFA1R_FFA11_Pos (11U)
2515 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2516 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2517 #define CAN_FFA1R_FFA12_Pos (12U)
2518 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2519 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2520 #define CAN_FFA1R_FFA13_Pos (13U)
2521 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2522 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2523 #define CAN_FFA1R_FFA14_Pos (14U)
2524 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2525 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2526 #define CAN_FFA1R_FFA15_Pos (15U)
2527 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2528 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2529 #define CAN_FFA1R_FFA16_Pos (16U)
2530 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2531 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2532 #define CAN_FFA1R_FFA17_Pos (17U)
2533 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2534 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2535 #define CAN_FFA1R_FFA18_Pos (18U)
2536 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2537 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2538 #define CAN_FFA1R_FFA19_Pos (19U)
2539 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2540 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2541 #define CAN_FFA1R_FFA20_Pos (20U)
2542 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2543 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2544 #define CAN_FFA1R_FFA21_Pos (21U)
2545 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2546 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2547 #define CAN_FFA1R_FFA22_Pos (22U)
2548 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2549 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2550 #define CAN_FFA1R_FFA23_Pos (23U)
2551 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2552 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2553 #define CAN_FFA1R_FFA24_Pos (24U)
2554 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2555 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2556 #define CAN_FFA1R_FFA25_Pos (25U)
2557 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2558 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2559 #define CAN_FFA1R_FFA26_Pos (26U)
2560 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2561 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2562 #define CAN_FFA1R_FFA27_Pos (27U)
2563 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2564 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2565
2566 /******************* Bit definition for CAN_FA1R register *******************/
2567 #define CAN_FA1R_FACT_Pos (0U)
2568 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2569 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2570 #define CAN_FA1R_FACT0_Pos (0U)
2571 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2572 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2573 #define CAN_FA1R_FACT1_Pos (1U)
2574 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2575 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2576 #define CAN_FA1R_FACT2_Pos (2U)
2577 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2578 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2579 #define CAN_FA1R_FACT3_Pos (3U)
2580 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2581 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2582 #define CAN_FA1R_FACT4_Pos (4U)
2583 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2584 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2585 #define CAN_FA1R_FACT5_Pos (5U)
2586 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2587 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2588 #define CAN_FA1R_FACT6_Pos (6U)
2589 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2590 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2591 #define CAN_FA1R_FACT7_Pos (7U)
2592 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2593 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2594 #define CAN_FA1R_FACT8_Pos (8U)
2595 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2596 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2597 #define CAN_FA1R_FACT9_Pos (9U)
2598 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2599 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2600 #define CAN_FA1R_FACT10_Pos (10U)
2601 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2602 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2603 #define CAN_FA1R_FACT11_Pos (11U)
2604 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2605 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2606 #define CAN_FA1R_FACT12_Pos (12U)
2607 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2608 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2609 #define CAN_FA1R_FACT13_Pos (13U)
2610 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2611 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2612 #define CAN_FA1R_FACT14_Pos (14U)
2613 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2614 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2615 #define CAN_FA1R_FACT15_Pos (15U)
2616 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2617 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2618 #define CAN_FA1R_FACT16_Pos (16U)
2619 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2620 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2621 #define CAN_FA1R_FACT17_Pos (17U)
2622 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2623 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2624 #define CAN_FA1R_FACT18_Pos (18U)
2625 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2626 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2627 #define CAN_FA1R_FACT19_Pos (19U)
2628 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2629 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2630 #define CAN_FA1R_FACT20_Pos (20U)
2631 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2632 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2633 #define CAN_FA1R_FACT21_Pos (21U)
2634 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2635 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2636 #define CAN_FA1R_FACT22_Pos (22U)
2637 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2638 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2639 #define CAN_FA1R_FACT23_Pos (23U)
2640 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2641 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2642 #define CAN_FA1R_FACT24_Pos (24U)
2643 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2644 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2645 #define CAN_FA1R_FACT25_Pos (25U)
2646 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2647 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2648 #define CAN_FA1R_FACT26_Pos (26U)
2649 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2650 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
2651 #define CAN_FA1R_FACT27_Pos (27U)
2652 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
2653 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
2654
2655
2656 /******************* Bit definition for CAN_F0R1 register *******************/
2657 #define CAN_F0R1_FB0_Pos (0U)
2658 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2659 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2660 #define CAN_F0R1_FB1_Pos (1U)
2661 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2662 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2663 #define CAN_F0R1_FB2_Pos (2U)
2664 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2665 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2666 #define CAN_F0R1_FB3_Pos (3U)
2667 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2668 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2669 #define CAN_F0R1_FB4_Pos (4U)
2670 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2671 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2672 #define CAN_F0R1_FB5_Pos (5U)
2673 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2674 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2675 #define CAN_F0R1_FB6_Pos (6U)
2676 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2677 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2678 #define CAN_F0R1_FB7_Pos (7U)
2679 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2680 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2681 #define CAN_F0R1_FB8_Pos (8U)
2682 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2683 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2684 #define CAN_F0R1_FB9_Pos (9U)
2685 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2686 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2687 #define CAN_F0R1_FB10_Pos (10U)
2688 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2689 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2690 #define CAN_F0R1_FB11_Pos (11U)
2691 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2692 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2693 #define CAN_F0R1_FB12_Pos (12U)
2694 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2695 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2696 #define CAN_F0R1_FB13_Pos (13U)
2697 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2698 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2699 #define CAN_F0R1_FB14_Pos (14U)
2700 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2701 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2702 #define CAN_F0R1_FB15_Pos (15U)
2703 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2704 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2705 #define CAN_F0R1_FB16_Pos (16U)
2706 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2707 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2708 #define CAN_F0R1_FB17_Pos (17U)
2709 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2710 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2711 #define CAN_F0R1_FB18_Pos (18U)
2712 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2713 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2714 #define CAN_F0R1_FB19_Pos (19U)
2715 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2716 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2717 #define CAN_F0R1_FB20_Pos (20U)
2718 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2719 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2720 #define CAN_F0R1_FB21_Pos (21U)
2721 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2722 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2723 #define CAN_F0R1_FB22_Pos (22U)
2724 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2725 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2726 #define CAN_F0R1_FB23_Pos (23U)
2727 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2728 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
2729 #define CAN_F0R1_FB24_Pos (24U)
2730 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
2731 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
2732 #define CAN_F0R1_FB25_Pos (25U)
2733 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
2734 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
2735 #define CAN_F0R1_FB26_Pos (26U)
2736 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
2737 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
2738 #define CAN_F0R1_FB27_Pos (27U)
2739 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
2740 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
2741 #define CAN_F0R1_FB28_Pos (28U)
2742 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
2743 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
2744 #define CAN_F0R1_FB29_Pos (29U)
2745 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
2746 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
2747 #define CAN_F0R1_FB30_Pos (30U)
2748 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
2749 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
2750 #define CAN_F0R1_FB31_Pos (31U)
2751 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
2752 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
2753
2754 /******************* Bit definition for CAN_F1R1 register *******************/
2755 #define CAN_F1R1_FB0_Pos (0U)
2756 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
2757 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
2758 #define CAN_F1R1_FB1_Pos (1U)
2759 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
2760 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
2761 #define CAN_F1R1_FB2_Pos (2U)
2762 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
2763 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
2764 #define CAN_F1R1_FB3_Pos (3U)
2765 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
2766 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
2767 #define CAN_F1R1_FB4_Pos (4U)
2768 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
2769 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
2770 #define CAN_F1R1_FB5_Pos (5U)
2771 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
2772 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
2773 #define CAN_F1R1_FB6_Pos (6U)
2774 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
2775 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
2776 #define CAN_F1R1_FB7_Pos (7U)
2777 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
2778 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
2779 #define CAN_F1R1_FB8_Pos (8U)
2780 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
2781 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
2782 #define CAN_F1R1_FB9_Pos (9U)
2783 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
2784 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
2785 #define CAN_F1R1_FB10_Pos (10U)
2786 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
2787 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
2788 #define CAN_F1R1_FB11_Pos (11U)
2789 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
2790 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
2791 #define CAN_F1R1_FB12_Pos (12U)
2792 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
2793 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
2794 #define CAN_F1R1_FB13_Pos (13U)
2795 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
2796 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
2797 #define CAN_F1R1_FB14_Pos (14U)
2798 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
2799 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
2800 #define CAN_F1R1_FB15_Pos (15U)
2801 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
2802 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
2803 #define CAN_F1R1_FB16_Pos (16U)
2804 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
2805 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
2806 #define CAN_F1R1_FB17_Pos (17U)
2807 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
2808 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
2809 #define CAN_F1R1_FB18_Pos (18U)
2810 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
2811 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
2812 #define CAN_F1R1_FB19_Pos (19U)
2813 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
2814 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
2815 #define CAN_F1R1_FB20_Pos (20U)
2816 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
2817 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
2818 #define CAN_F1R1_FB21_Pos (21U)
2819 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
2820 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
2821 #define CAN_F1R1_FB22_Pos (22U)
2822 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
2823 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
2824 #define CAN_F1R1_FB23_Pos (23U)
2825 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
2826 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
2827 #define CAN_F1R1_FB24_Pos (24U)
2828 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
2829 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
2830 #define CAN_F1R1_FB25_Pos (25U)
2831 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
2832 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
2833 #define CAN_F1R1_FB26_Pos (26U)
2834 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
2835 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
2836 #define CAN_F1R1_FB27_Pos (27U)
2837 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
2838 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
2839 #define CAN_F1R1_FB28_Pos (28U)
2840 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
2841 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
2842 #define CAN_F1R1_FB29_Pos (29U)
2843 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
2844 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
2845 #define CAN_F1R1_FB30_Pos (30U)
2846 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
2847 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
2848 #define CAN_F1R1_FB31_Pos (31U)
2849 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
2850 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
2851
2852 /******************* Bit definition for CAN_F2R1 register *******************/
2853 #define CAN_F2R1_FB0_Pos (0U)
2854 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
2855 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
2856 #define CAN_F2R1_FB1_Pos (1U)
2857 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
2858 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
2859 #define CAN_F2R1_FB2_Pos (2U)
2860 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
2861 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
2862 #define CAN_F2R1_FB3_Pos (3U)
2863 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
2864 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
2865 #define CAN_F2R1_FB4_Pos (4U)
2866 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
2867 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
2868 #define CAN_F2R1_FB5_Pos (5U)
2869 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
2870 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
2871 #define CAN_F2R1_FB6_Pos (6U)
2872 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
2873 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
2874 #define CAN_F2R1_FB7_Pos (7U)
2875 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
2876 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
2877 #define CAN_F2R1_FB8_Pos (8U)
2878 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
2879 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
2880 #define CAN_F2R1_FB9_Pos (9U)
2881 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
2882 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
2883 #define CAN_F2R1_FB10_Pos (10U)
2884 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
2885 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
2886 #define CAN_F2R1_FB11_Pos (11U)
2887 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
2888 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
2889 #define CAN_F2R1_FB12_Pos (12U)
2890 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
2891 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
2892 #define CAN_F2R1_FB13_Pos (13U)
2893 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
2894 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
2895 #define CAN_F2R1_FB14_Pos (14U)
2896 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
2897 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
2898 #define CAN_F2R1_FB15_Pos (15U)
2899 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
2900 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
2901 #define CAN_F2R1_FB16_Pos (16U)
2902 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
2903 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
2904 #define CAN_F2R1_FB17_Pos (17U)
2905 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
2906 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
2907 #define CAN_F2R1_FB18_Pos (18U)
2908 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
2909 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
2910 #define CAN_F2R1_FB19_Pos (19U)
2911 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
2912 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
2913 #define CAN_F2R1_FB20_Pos (20U)
2914 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
2915 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
2916 #define CAN_F2R1_FB21_Pos (21U)
2917 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
2918 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
2919 #define CAN_F2R1_FB22_Pos (22U)
2920 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
2921 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
2922 #define CAN_F2R1_FB23_Pos (23U)
2923 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
2924 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
2925 #define CAN_F2R1_FB24_Pos (24U)
2926 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
2927 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
2928 #define CAN_F2R1_FB25_Pos (25U)
2929 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
2930 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
2931 #define CAN_F2R1_FB26_Pos (26U)
2932 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
2933 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
2934 #define CAN_F2R1_FB27_Pos (27U)
2935 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
2936 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
2937 #define CAN_F2R1_FB28_Pos (28U)
2938 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
2939 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
2940 #define CAN_F2R1_FB29_Pos (29U)
2941 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
2942 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
2943 #define CAN_F2R1_FB30_Pos (30U)
2944 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
2945 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
2946 #define CAN_F2R1_FB31_Pos (31U)
2947 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
2948 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
2949
2950 /******************* Bit definition for CAN_F3R1 register *******************/
2951 #define CAN_F3R1_FB0_Pos (0U)
2952 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
2953 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
2954 #define CAN_F3R1_FB1_Pos (1U)
2955 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
2956 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
2957 #define CAN_F3R1_FB2_Pos (2U)
2958 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
2959 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
2960 #define CAN_F3R1_FB3_Pos (3U)
2961 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
2962 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
2963 #define CAN_F3R1_FB4_Pos (4U)
2964 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
2965 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
2966 #define CAN_F3R1_FB5_Pos (5U)
2967 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
2968 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
2969 #define CAN_F3R1_FB6_Pos (6U)
2970 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
2971 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
2972 #define CAN_F3R1_FB7_Pos (7U)
2973 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
2974 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
2975 #define CAN_F3R1_FB8_Pos (8U)
2976 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
2977 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
2978 #define CAN_F3R1_FB9_Pos (9U)
2979 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
2980 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
2981 #define CAN_F3R1_FB10_Pos (10U)
2982 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
2983 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
2984 #define CAN_F3R1_FB11_Pos (11U)
2985 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
2986 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
2987 #define CAN_F3R1_FB12_Pos (12U)
2988 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
2989 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
2990 #define CAN_F3R1_FB13_Pos (13U)
2991 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
2992 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
2993 #define CAN_F3R1_FB14_Pos (14U)
2994 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
2995 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
2996 #define CAN_F3R1_FB15_Pos (15U)
2997 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
2998 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
2999 #define CAN_F3R1_FB16_Pos (16U)
3000 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3001 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3002 #define CAN_F3R1_FB17_Pos (17U)
3003 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3004 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3005 #define CAN_F3R1_FB18_Pos (18U)
3006 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3007 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3008 #define CAN_F3R1_FB19_Pos (19U)
3009 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3010 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3011 #define CAN_F3R1_FB20_Pos (20U)
3012 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3013 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3014 #define CAN_F3R1_FB21_Pos (21U)
3015 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3016 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3017 #define CAN_F3R1_FB22_Pos (22U)
3018 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3019 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3020 #define CAN_F3R1_FB23_Pos (23U)
3021 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3022 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3023 #define CAN_F3R1_FB24_Pos (24U)
3024 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3025 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3026 #define CAN_F3R1_FB25_Pos (25U)
3027 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3028 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3029 #define CAN_F3R1_FB26_Pos (26U)
3030 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3031 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3032 #define CAN_F3R1_FB27_Pos (27U)
3033 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3034 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3035 #define CAN_F3R1_FB28_Pos (28U)
3036 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3037 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3038 #define CAN_F3R1_FB29_Pos (29U)
3039 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3040 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3041 #define CAN_F3R1_FB30_Pos (30U)
3042 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3043 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3044 #define CAN_F3R1_FB31_Pos (31U)
3045 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3046 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3047
3048 /******************* Bit definition for CAN_F4R1 register *******************/
3049 #define CAN_F4R1_FB0_Pos (0U)
3050 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3051 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3052 #define CAN_F4R1_FB1_Pos (1U)
3053 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3054 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3055 #define CAN_F4R1_FB2_Pos (2U)
3056 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3057 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3058 #define CAN_F4R1_FB3_Pos (3U)
3059 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3060 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3061 #define CAN_F4R1_FB4_Pos (4U)
3062 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3063 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3064 #define CAN_F4R1_FB5_Pos (5U)
3065 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3066 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3067 #define CAN_F4R1_FB6_Pos (6U)
3068 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3069 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3070 #define CAN_F4R1_FB7_Pos (7U)
3071 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3072 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3073 #define CAN_F4R1_FB8_Pos (8U)
3074 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3075 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3076 #define CAN_F4R1_FB9_Pos (9U)
3077 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3078 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3079 #define CAN_F4R1_FB10_Pos (10U)
3080 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3081 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3082 #define CAN_F4R1_FB11_Pos (11U)
3083 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3084 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3085 #define CAN_F4R1_FB12_Pos (12U)
3086 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3087 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3088 #define CAN_F4R1_FB13_Pos (13U)
3089 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3090 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3091 #define CAN_F4R1_FB14_Pos (14U)
3092 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3093 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3094 #define CAN_F4R1_FB15_Pos (15U)
3095 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3096 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3097 #define CAN_F4R1_FB16_Pos (16U)
3098 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3099 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3100 #define CAN_F4R1_FB17_Pos (17U)
3101 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3102 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3103 #define CAN_F4R1_FB18_Pos (18U)
3104 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3105 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3106 #define CAN_F4R1_FB19_Pos (19U)
3107 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3108 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3109 #define CAN_F4R1_FB20_Pos (20U)
3110 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3111 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3112 #define CAN_F4R1_FB21_Pos (21U)
3113 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3114 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3115 #define CAN_F4R1_FB22_Pos (22U)
3116 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3117 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3118 #define CAN_F4R1_FB23_Pos (23U)
3119 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3120 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3121 #define CAN_F4R1_FB24_Pos (24U)
3122 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3123 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3124 #define CAN_F4R1_FB25_Pos (25U)
3125 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3126 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3127 #define CAN_F4R1_FB26_Pos (26U)
3128 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3129 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3130 #define CAN_F4R1_FB27_Pos (27U)
3131 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3132 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3133 #define CAN_F4R1_FB28_Pos (28U)
3134 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3135 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3136 #define CAN_F4R1_FB29_Pos (29U)
3137 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3138 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3139 #define CAN_F4R1_FB30_Pos (30U)
3140 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3141 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3142 #define CAN_F4R1_FB31_Pos (31U)
3143 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3144 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3145
3146 /******************* Bit definition for CAN_F5R1 register *******************/
3147 #define CAN_F5R1_FB0_Pos (0U)
3148 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3149 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3150 #define CAN_F5R1_FB1_Pos (1U)
3151 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3152 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3153 #define CAN_F5R1_FB2_Pos (2U)
3154 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3155 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3156 #define CAN_F5R1_FB3_Pos (3U)
3157 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3158 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3159 #define CAN_F5R1_FB4_Pos (4U)
3160 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3161 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3162 #define CAN_F5R1_FB5_Pos (5U)
3163 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3164 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3165 #define CAN_F5R1_FB6_Pos (6U)
3166 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3167 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3168 #define CAN_F5R1_FB7_Pos (7U)
3169 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3170 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3171 #define CAN_F5R1_FB8_Pos (8U)
3172 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3173 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3174 #define CAN_F5R1_FB9_Pos (9U)
3175 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3176 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3177 #define CAN_F5R1_FB10_Pos (10U)
3178 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3179 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3180 #define CAN_F5R1_FB11_Pos (11U)
3181 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3182 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3183 #define CAN_F5R1_FB12_Pos (12U)
3184 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3185 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3186 #define CAN_F5R1_FB13_Pos (13U)
3187 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3188 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3189 #define CAN_F5R1_FB14_Pos (14U)
3190 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3191 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3192 #define CAN_F5R1_FB15_Pos (15U)
3193 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3194 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3195 #define CAN_F5R1_FB16_Pos (16U)
3196 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3197 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3198 #define CAN_F5R1_FB17_Pos (17U)
3199 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3200 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3201 #define CAN_F5R1_FB18_Pos (18U)
3202 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3203 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3204 #define CAN_F5R1_FB19_Pos (19U)
3205 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3206 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3207 #define CAN_F5R1_FB20_Pos (20U)
3208 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3209 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3210 #define CAN_F5R1_FB21_Pos (21U)
3211 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3212 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3213 #define CAN_F5R1_FB22_Pos (22U)
3214 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3215 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3216 #define CAN_F5R1_FB23_Pos (23U)
3217 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3218 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3219 #define CAN_F5R1_FB24_Pos (24U)
3220 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3221 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3222 #define CAN_F5R1_FB25_Pos (25U)
3223 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3224 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3225 #define CAN_F5R1_FB26_Pos (26U)
3226 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3227 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3228 #define CAN_F5R1_FB27_Pos (27U)
3229 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3230 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3231 #define CAN_F5R1_FB28_Pos (28U)
3232 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3233 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3234 #define CAN_F5R1_FB29_Pos (29U)
3235 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3236 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3237 #define CAN_F5R1_FB30_Pos (30U)
3238 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3239 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3240 #define CAN_F5R1_FB31_Pos (31U)
3241 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3242 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3243
3244 /******************* Bit definition for CAN_F6R1 register *******************/
3245 #define CAN_F6R1_FB0_Pos (0U)
3246 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3247 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3248 #define CAN_F6R1_FB1_Pos (1U)
3249 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3250 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3251 #define CAN_F6R1_FB2_Pos (2U)
3252 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3253 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3254 #define CAN_F6R1_FB3_Pos (3U)
3255 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3256 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3257 #define CAN_F6R1_FB4_Pos (4U)
3258 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3259 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3260 #define CAN_F6R1_FB5_Pos (5U)
3261 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3262 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3263 #define CAN_F6R1_FB6_Pos (6U)
3264 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3265 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3266 #define CAN_F6R1_FB7_Pos (7U)
3267 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3268 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3269 #define CAN_F6R1_FB8_Pos (8U)
3270 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3271 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3272 #define CAN_F6R1_FB9_Pos (9U)
3273 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3274 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3275 #define CAN_F6R1_FB10_Pos (10U)
3276 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3277 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3278 #define CAN_F6R1_FB11_Pos (11U)
3279 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3280 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3281 #define CAN_F6R1_FB12_Pos (12U)
3282 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3283 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3284 #define CAN_F6R1_FB13_Pos (13U)
3285 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3286 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3287 #define CAN_F6R1_FB14_Pos (14U)
3288 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3289 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3290 #define CAN_F6R1_FB15_Pos (15U)
3291 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3292 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3293 #define CAN_F6R1_FB16_Pos (16U)
3294 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3295 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3296 #define CAN_F6R1_FB17_Pos (17U)
3297 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3298 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3299 #define CAN_F6R1_FB18_Pos (18U)
3300 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3301 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3302 #define CAN_F6R1_FB19_Pos (19U)
3303 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3304 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3305 #define CAN_F6R1_FB20_Pos (20U)
3306 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3307 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3308 #define CAN_F6R1_FB21_Pos (21U)
3309 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3310 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3311 #define CAN_F6R1_FB22_Pos (22U)
3312 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3313 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3314 #define CAN_F6R1_FB23_Pos (23U)
3315 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3316 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3317 #define CAN_F6R1_FB24_Pos (24U)
3318 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3319 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3320 #define CAN_F6R1_FB25_Pos (25U)
3321 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3322 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3323 #define CAN_F6R1_FB26_Pos (26U)
3324 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3325 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3326 #define CAN_F6R1_FB27_Pos (27U)
3327 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3328 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3329 #define CAN_F6R1_FB28_Pos (28U)
3330 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3331 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3332 #define CAN_F6R1_FB29_Pos (29U)
3333 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3334 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3335 #define CAN_F6R1_FB30_Pos (30U)
3336 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3337 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3338 #define CAN_F6R1_FB31_Pos (31U)
3339 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3340 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3341
3342 /******************* Bit definition for CAN_F7R1 register *******************/
3343 #define CAN_F7R1_FB0_Pos (0U)
3344 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3345 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3346 #define CAN_F7R1_FB1_Pos (1U)
3347 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3348 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3349 #define CAN_F7R1_FB2_Pos (2U)
3350 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3351 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3352 #define CAN_F7R1_FB3_Pos (3U)
3353 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3354 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3355 #define CAN_F7R1_FB4_Pos (4U)
3356 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3357 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3358 #define CAN_F7R1_FB5_Pos (5U)
3359 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3360 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3361 #define CAN_F7R1_FB6_Pos (6U)
3362 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3363 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3364 #define CAN_F7R1_FB7_Pos (7U)
3365 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3366 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3367 #define CAN_F7R1_FB8_Pos (8U)
3368 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3369 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3370 #define CAN_F7R1_FB9_Pos (9U)
3371 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3372 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3373 #define CAN_F7R1_FB10_Pos (10U)
3374 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3375 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3376 #define CAN_F7R1_FB11_Pos (11U)
3377 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3378 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3379 #define CAN_F7R1_FB12_Pos (12U)
3380 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3381 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3382 #define CAN_F7R1_FB13_Pos (13U)
3383 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3384 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3385 #define CAN_F7R1_FB14_Pos (14U)
3386 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3387 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3388 #define CAN_F7R1_FB15_Pos (15U)
3389 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3390 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3391 #define CAN_F7R1_FB16_Pos (16U)
3392 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3393 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3394 #define CAN_F7R1_FB17_Pos (17U)
3395 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3396 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3397 #define CAN_F7R1_FB18_Pos (18U)
3398 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3399 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3400 #define CAN_F7R1_FB19_Pos (19U)
3401 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3402 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3403 #define CAN_F7R1_FB20_Pos (20U)
3404 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3405 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3406 #define CAN_F7R1_FB21_Pos (21U)
3407 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3408 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3409 #define CAN_F7R1_FB22_Pos (22U)
3410 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3411 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3412 #define CAN_F7R1_FB23_Pos (23U)
3413 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3414 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3415 #define CAN_F7R1_FB24_Pos (24U)
3416 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3417 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3418 #define CAN_F7R1_FB25_Pos (25U)
3419 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3420 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3421 #define CAN_F7R1_FB26_Pos (26U)
3422 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3423 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3424 #define CAN_F7R1_FB27_Pos (27U)
3425 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3426 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3427 #define CAN_F7R1_FB28_Pos (28U)
3428 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3429 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3430 #define CAN_F7R1_FB29_Pos (29U)
3431 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3432 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3433 #define CAN_F7R1_FB30_Pos (30U)
3434 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3435 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3436 #define CAN_F7R1_FB31_Pos (31U)
3437 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3438 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3439
3440 /******************* Bit definition for CAN_F8R1 register *******************/
3441 #define CAN_F8R1_FB0_Pos (0U)
3442 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3443 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3444 #define CAN_F8R1_FB1_Pos (1U)
3445 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3446 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3447 #define CAN_F8R1_FB2_Pos (2U)
3448 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3449 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3450 #define CAN_F8R1_FB3_Pos (3U)
3451 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3452 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3453 #define CAN_F8R1_FB4_Pos (4U)
3454 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3455 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3456 #define CAN_F8R1_FB5_Pos (5U)
3457 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3458 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3459 #define CAN_F8R1_FB6_Pos (6U)
3460 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3461 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3462 #define CAN_F8R1_FB7_Pos (7U)
3463 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3464 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3465 #define CAN_F8R1_FB8_Pos (8U)
3466 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3467 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3468 #define CAN_F8R1_FB9_Pos (9U)
3469 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3470 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3471 #define CAN_F8R1_FB10_Pos (10U)
3472 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3473 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3474 #define CAN_F8R1_FB11_Pos (11U)
3475 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3476 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3477 #define CAN_F8R1_FB12_Pos (12U)
3478 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3479 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3480 #define CAN_F8R1_FB13_Pos (13U)
3481 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3482 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3483 #define CAN_F8R1_FB14_Pos (14U)
3484 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3485 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3486 #define CAN_F8R1_FB15_Pos (15U)
3487 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3488 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3489 #define CAN_F8R1_FB16_Pos (16U)
3490 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3491 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3492 #define CAN_F8R1_FB17_Pos (17U)
3493 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3494 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3495 #define CAN_F8R1_FB18_Pos (18U)
3496 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3497 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3498 #define CAN_F8R1_FB19_Pos (19U)
3499 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3500 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3501 #define CAN_F8R1_FB20_Pos (20U)
3502 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3503 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3504 #define CAN_F8R1_FB21_Pos (21U)
3505 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3506 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3507 #define CAN_F8R1_FB22_Pos (22U)
3508 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3509 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3510 #define CAN_F8R1_FB23_Pos (23U)
3511 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3512 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3513 #define CAN_F8R1_FB24_Pos (24U)
3514 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3515 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3516 #define CAN_F8R1_FB25_Pos (25U)
3517 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3518 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3519 #define CAN_F8R1_FB26_Pos (26U)
3520 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3521 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3522 #define CAN_F8R1_FB27_Pos (27U)
3523 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3524 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3525 #define CAN_F8R1_FB28_Pos (28U)
3526 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3527 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3528 #define CAN_F8R1_FB29_Pos (29U)
3529 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3530 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3531 #define CAN_F8R1_FB30_Pos (30U)
3532 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3533 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3534 #define CAN_F8R1_FB31_Pos (31U)
3535 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3536 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3537
3538 /******************* Bit definition for CAN_F9R1 register *******************/
3539 #define CAN_F9R1_FB0_Pos (0U)
3540 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3541 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3542 #define CAN_F9R1_FB1_Pos (1U)
3543 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3544 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3545 #define CAN_F9R1_FB2_Pos (2U)
3546 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3547 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3548 #define CAN_F9R1_FB3_Pos (3U)
3549 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3550 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3551 #define CAN_F9R1_FB4_Pos (4U)
3552 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3553 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3554 #define CAN_F9R1_FB5_Pos (5U)
3555 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3556 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3557 #define CAN_F9R1_FB6_Pos (6U)
3558 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3559 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3560 #define CAN_F9R1_FB7_Pos (7U)
3561 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3562 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3563 #define CAN_F9R1_FB8_Pos (8U)
3564 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3565 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3566 #define CAN_F9R1_FB9_Pos (9U)
3567 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3568 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3569 #define CAN_F9R1_FB10_Pos (10U)
3570 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3571 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3572 #define CAN_F9R1_FB11_Pos (11U)
3573 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3574 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3575 #define CAN_F9R1_FB12_Pos (12U)
3576 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3577 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3578 #define CAN_F9R1_FB13_Pos (13U)
3579 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3580 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3581 #define CAN_F9R1_FB14_Pos (14U)
3582 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3583 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3584 #define CAN_F9R1_FB15_Pos (15U)
3585 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3586 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3587 #define CAN_F9R1_FB16_Pos (16U)
3588 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3589 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3590 #define CAN_F9R1_FB17_Pos (17U)
3591 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3592 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3593 #define CAN_F9R1_FB18_Pos (18U)
3594 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3595 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3596 #define CAN_F9R1_FB19_Pos (19U)
3597 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3598 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3599 #define CAN_F9R1_FB20_Pos (20U)
3600 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3601 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3602 #define CAN_F9R1_FB21_Pos (21U)
3603 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3604 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3605 #define CAN_F9R1_FB22_Pos (22U)
3606 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3607 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3608 #define CAN_F9R1_FB23_Pos (23U)
3609 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3610 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3611 #define CAN_F9R1_FB24_Pos (24U)
3612 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3613 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3614 #define CAN_F9R1_FB25_Pos (25U)
3615 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3616 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3617 #define CAN_F9R1_FB26_Pos (26U)
3618 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3619 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3620 #define CAN_F9R1_FB27_Pos (27U)
3621 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3622 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3623 #define CAN_F9R1_FB28_Pos (28U)
3624 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3625 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3626 #define CAN_F9R1_FB29_Pos (29U)
3627 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3628 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3629 #define CAN_F9R1_FB30_Pos (30U)
3630 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3631 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3632 #define CAN_F9R1_FB31_Pos (31U)
3633 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3634 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3635
3636 /******************* Bit definition for CAN_F10R1 register ******************/
3637 #define CAN_F10R1_FB0_Pos (0U)
3638 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3639 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3640 #define CAN_F10R1_FB1_Pos (1U)
3641 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3642 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3643 #define CAN_F10R1_FB2_Pos (2U)
3644 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3645 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3646 #define CAN_F10R1_FB3_Pos (3U)
3647 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3648 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3649 #define CAN_F10R1_FB4_Pos (4U)
3650 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3651 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3652 #define CAN_F10R1_FB5_Pos (5U)
3653 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3654 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3655 #define CAN_F10R1_FB6_Pos (6U)
3656 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3657 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3658 #define CAN_F10R1_FB7_Pos (7U)
3659 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3660 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3661 #define CAN_F10R1_FB8_Pos (8U)
3662 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3663 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3664 #define CAN_F10R1_FB9_Pos (9U)
3665 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3666 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3667 #define CAN_F10R1_FB10_Pos (10U)
3668 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3669 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3670 #define CAN_F10R1_FB11_Pos (11U)
3671 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3672 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3673 #define CAN_F10R1_FB12_Pos (12U)
3674 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3675 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3676 #define CAN_F10R1_FB13_Pos (13U)
3677 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3678 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3679 #define CAN_F10R1_FB14_Pos (14U)
3680 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3681 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3682 #define CAN_F10R1_FB15_Pos (15U)
3683 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3684 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3685 #define CAN_F10R1_FB16_Pos (16U)
3686 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3687 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3688 #define CAN_F10R1_FB17_Pos (17U)
3689 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3690 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3691 #define CAN_F10R1_FB18_Pos (18U)
3692 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3693 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3694 #define CAN_F10R1_FB19_Pos (19U)
3695 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3696 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3697 #define CAN_F10R1_FB20_Pos (20U)
3698 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3699 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3700 #define CAN_F10R1_FB21_Pos (21U)
3701 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3702 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
3703 #define CAN_F10R1_FB22_Pos (22U)
3704 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
3705 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
3706 #define CAN_F10R1_FB23_Pos (23U)
3707 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
3708 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
3709 #define CAN_F10R1_FB24_Pos (24U)
3710 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
3711 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
3712 #define CAN_F10R1_FB25_Pos (25U)
3713 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
3714 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
3715 #define CAN_F10R1_FB26_Pos (26U)
3716 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
3717 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
3718 #define CAN_F10R1_FB27_Pos (27U)
3719 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
3720 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
3721 #define CAN_F10R1_FB28_Pos (28U)
3722 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
3723 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
3724 #define CAN_F10R1_FB29_Pos (29U)
3725 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
3726 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
3727 #define CAN_F10R1_FB30_Pos (30U)
3728 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
3729 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
3730 #define CAN_F10R1_FB31_Pos (31U)
3731 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
3732 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
3733
3734 /******************* Bit definition for CAN_F11R1 register ******************/
3735 #define CAN_F11R1_FB0_Pos (0U)
3736 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
3737 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
3738 #define CAN_F11R1_FB1_Pos (1U)
3739 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
3740 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
3741 #define CAN_F11R1_FB2_Pos (2U)
3742 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
3743 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
3744 #define CAN_F11R1_FB3_Pos (3U)
3745 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
3746 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
3747 #define CAN_F11R1_FB4_Pos (4U)
3748 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
3749 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
3750 #define CAN_F11R1_FB5_Pos (5U)
3751 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
3752 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
3753 #define CAN_F11R1_FB6_Pos (6U)
3754 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
3755 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
3756 #define CAN_F11R1_FB7_Pos (7U)
3757 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
3758 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
3759 #define CAN_F11R1_FB8_Pos (8U)
3760 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
3761 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
3762 #define CAN_F11R1_FB9_Pos (9U)
3763 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
3764 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
3765 #define CAN_F11R1_FB10_Pos (10U)
3766 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
3767 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
3768 #define CAN_F11R1_FB11_Pos (11U)
3769 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
3770 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
3771 #define CAN_F11R1_FB12_Pos (12U)
3772 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
3773 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
3774 #define CAN_F11R1_FB13_Pos (13U)
3775 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
3776 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
3777 #define CAN_F11R1_FB14_Pos (14U)
3778 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
3779 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
3780 #define CAN_F11R1_FB15_Pos (15U)
3781 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
3782 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
3783 #define CAN_F11R1_FB16_Pos (16U)
3784 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
3785 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
3786 #define CAN_F11R1_FB17_Pos (17U)
3787 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
3788 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
3789 #define CAN_F11R1_FB18_Pos (18U)
3790 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
3791 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
3792 #define CAN_F11R1_FB19_Pos (19U)
3793 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
3794 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
3795 #define CAN_F11R1_FB20_Pos (20U)
3796 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
3797 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
3798 #define CAN_F11R1_FB21_Pos (21U)
3799 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
3800 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
3801 #define CAN_F11R1_FB22_Pos (22U)
3802 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
3803 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
3804 #define CAN_F11R1_FB23_Pos (23U)
3805 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
3806 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
3807 #define CAN_F11R1_FB24_Pos (24U)
3808 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
3809 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
3810 #define CAN_F11R1_FB25_Pos (25U)
3811 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
3812 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
3813 #define CAN_F11R1_FB26_Pos (26U)
3814 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
3815 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
3816 #define CAN_F11R1_FB27_Pos (27U)
3817 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
3818 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
3819 #define CAN_F11R1_FB28_Pos (28U)
3820 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
3821 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
3822 #define CAN_F11R1_FB29_Pos (29U)
3823 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
3824 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
3825 #define CAN_F11R1_FB30_Pos (30U)
3826 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
3827 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
3828 #define CAN_F11R1_FB31_Pos (31U)
3829 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
3830 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
3831
3832 /******************* Bit definition for CAN_F12R1 register ******************/
3833 #define CAN_F12R1_FB0_Pos (0U)
3834 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
3835 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
3836 #define CAN_F12R1_FB1_Pos (1U)
3837 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
3838 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
3839 #define CAN_F12R1_FB2_Pos (2U)
3840 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
3841 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
3842 #define CAN_F12R1_FB3_Pos (3U)
3843 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
3844 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
3845 #define CAN_F12R1_FB4_Pos (4U)
3846 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
3847 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
3848 #define CAN_F12R1_FB5_Pos (5U)
3849 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
3850 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
3851 #define CAN_F12R1_FB6_Pos (6U)
3852 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
3853 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
3854 #define CAN_F12R1_FB7_Pos (7U)
3855 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
3856 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
3857 #define CAN_F12R1_FB8_Pos (8U)
3858 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
3859 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
3860 #define CAN_F12R1_FB9_Pos (9U)
3861 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
3862 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
3863 #define CAN_F12R1_FB10_Pos (10U)
3864 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
3865 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
3866 #define CAN_F12R1_FB11_Pos (11U)
3867 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
3868 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
3869 #define CAN_F12R1_FB12_Pos (12U)
3870 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
3871 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
3872 #define CAN_F12R1_FB13_Pos (13U)
3873 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
3874 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
3875 #define CAN_F12R1_FB14_Pos (14U)
3876 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
3877 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
3878 #define CAN_F12R1_FB15_Pos (15U)
3879 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
3880 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
3881 #define CAN_F12R1_FB16_Pos (16U)
3882 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
3883 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
3884 #define CAN_F12R1_FB17_Pos (17U)
3885 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
3886 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
3887 #define CAN_F12R1_FB18_Pos (18U)
3888 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
3889 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
3890 #define CAN_F12R1_FB19_Pos (19U)
3891 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
3892 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
3893 #define CAN_F12R1_FB20_Pos (20U)
3894 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
3895 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
3896 #define CAN_F12R1_FB21_Pos (21U)
3897 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
3898 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
3899 #define CAN_F12R1_FB22_Pos (22U)
3900 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
3901 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
3902 #define CAN_F12R1_FB23_Pos (23U)
3903 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
3904 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
3905 #define CAN_F12R1_FB24_Pos (24U)
3906 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
3907 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
3908 #define CAN_F12R1_FB25_Pos (25U)
3909 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
3910 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
3911 #define CAN_F12R1_FB26_Pos (26U)
3912 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
3913 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
3914 #define CAN_F12R1_FB27_Pos (27U)
3915 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
3916 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
3917 #define CAN_F12R1_FB28_Pos (28U)
3918 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
3919 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
3920 #define CAN_F12R1_FB29_Pos (29U)
3921 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
3922 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
3923 #define CAN_F12R1_FB30_Pos (30U)
3924 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
3925 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
3926 #define CAN_F12R1_FB31_Pos (31U)
3927 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
3928 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
3929
3930 /******************* Bit definition for CAN_F13R1 register ******************/
3931 #define CAN_F13R1_FB0_Pos (0U)
3932 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
3933 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
3934 #define CAN_F13R1_FB1_Pos (1U)
3935 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
3936 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
3937 #define CAN_F13R1_FB2_Pos (2U)
3938 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
3939 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
3940 #define CAN_F13R1_FB3_Pos (3U)
3941 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
3942 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
3943 #define CAN_F13R1_FB4_Pos (4U)
3944 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
3945 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
3946 #define CAN_F13R1_FB5_Pos (5U)
3947 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
3948 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
3949 #define CAN_F13R1_FB6_Pos (6U)
3950 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
3951 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
3952 #define CAN_F13R1_FB7_Pos (7U)
3953 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
3954 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
3955 #define CAN_F13R1_FB8_Pos (8U)
3956 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
3957 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
3958 #define CAN_F13R1_FB9_Pos (9U)
3959 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
3960 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
3961 #define CAN_F13R1_FB10_Pos (10U)
3962 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
3963 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
3964 #define CAN_F13R1_FB11_Pos (11U)
3965 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
3966 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
3967 #define CAN_F13R1_FB12_Pos (12U)
3968 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
3969 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
3970 #define CAN_F13R1_FB13_Pos (13U)
3971 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
3972 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
3973 #define CAN_F13R1_FB14_Pos (14U)
3974 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
3975 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
3976 #define CAN_F13R1_FB15_Pos (15U)
3977 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
3978 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
3979 #define CAN_F13R1_FB16_Pos (16U)
3980 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
3981 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
3982 #define CAN_F13R1_FB17_Pos (17U)
3983 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
3984 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
3985 #define CAN_F13R1_FB18_Pos (18U)
3986 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
3987 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
3988 #define CAN_F13R1_FB19_Pos (19U)
3989 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
3990 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
3991 #define CAN_F13R1_FB20_Pos (20U)
3992 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
3993 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
3994 #define CAN_F13R1_FB21_Pos (21U)
3995 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
3996 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
3997 #define CAN_F13R1_FB22_Pos (22U)
3998 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
3999 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4000 #define CAN_F13R1_FB23_Pos (23U)
4001 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4002 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4003 #define CAN_F13R1_FB24_Pos (24U)
4004 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4005 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4006 #define CAN_F13R1_FB25_Pos (25U)
4007 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4008 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4009 #define CAN_F13R1_FB26_Pos (26U)
4010 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4011 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4012 #define CAN_F13R1_FB27_Pos (27U)
4013 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4014 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4015 #define CAN_F13R1_FB28_Pos (28U)
4016 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4017 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4018 #define CAN_F13R1_FB29_Pos (29U)
4019 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4020 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4021 #define CAN_F13R1_FB30_Pos (30U)
4022 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4023 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4024 #define CAN_F13R1_FB31_Pos (31U)
4025 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4026 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4027
4028 /******************* Bit definition for CAN_F0R2 register *******************/
4029 #define CAN_F0R2_FB0_Pos (0U)
4030 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4031 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4032 #define CAN_F0R2_FB1_Pos (1U)
4033 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4034 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4035 #define CAN_F0R2_FB2_Pos (2U)
4036 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4037 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4038 #define CAN_F0R2_FB3_Pos (3U)
4039 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4040 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4041 #define CAN_F0R2_FB4_Pos (4U)
4042 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4043 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4044 #define CAN_F0R2_FB5_Pos (5U)
4045 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4046 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4047 #define CAN_F0R2_FB6_Pos (6U)
4048 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4049 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4050 #define CAN_F0R2_FB7_Pos (7U)
4051 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4052 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4053 #define CAN_F0R2_FB8_Pos (8U)
4054 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4055 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4056 #define CAN_F0R2_FB9_Pos (9U)
4057 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4058 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4059 #define CAN_F0R2_FB10_Pos (10U)
4060 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4061 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4062 #define CAN_F0R2_FB11_Pos (11U)
4063 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4064 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4065 #define CAN_F0R2_FB12_Pos (12U)
4066 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4067 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4068 #define CAN_F0R2_FB13_Pos (13U)
4069 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4070 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4071 #define CAN_F0R2_FB14_Pos (14U)
4072 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4073 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4074 #define CAN_F0R2_FB15_Pos (15U)
4075 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4076 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4077 #define CAN_F0R2_FB16_Pos (16U)
4078 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4079 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4080 #define CAN_F0R2_FB17_Pos (17U)
4081 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4082 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4083 #define CAN_F0R2_FB18_Pos (18U)
4084 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4085 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4086 #define CAN_F0R2_FB19_Pos (19U)
4087 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4088 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4089 #define CAN_F0R2_FB20_Pos (20U)
4090 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4091 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4092 #define CAN_F0R2_FB21_Pos (21U)
4093 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4094 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4095 #define CAN_F0R2_FB22_Pos (22U)
4096 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4097 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4098 #define CAN_F0R2_FB23_Pos (23U)
4099 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4100 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4101 #define CAN_F0R2_FB24_Pos (24U)
4102 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4103 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4104 #define CAN_F0R2_FB25_Pos (25U)
4105 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4106 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4107 #define CAN_F0R2_FB26_Pos (26U)
4108 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4109 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4110 #define CAN_F0R2_FB27_Pos (27U)
4111 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4112 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4113 #define CAN_F0R2_FB28_Pos (28U)
4114 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4115 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4116 #define CAN_F0R2_FB29_Pos (29U)
4117 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4118 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4119 #define CAN_F0R2_FB30_Pos (30U)
4120 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4121 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4122 #define CAN_F0R2_FB31_Pos (31U)
4123 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4124 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4125
4126 /******************* Bit definition for CAN_F1R2 register *******************/
4127 #define CAN_F1R2_FB0_Pos (0U)
4128 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4129 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4130 #define CAN_F1R2_FB1_Pos (1U)
4131 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4132 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4133 #define CAN_F1R2_FB2_Pos (2U)
4134 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4135 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4136 #define CAN_F1R2_FB3_Pos (3U)
4137 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4138 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4139 #define CAN_F1R2_FB4_Pos (4U)
4140 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4141 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4142 #define CAN_F1R2_FB5_Pos (5U)
4143 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4144 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4145 #define CAN_F1R2_FB6_Pos (6U)
4146 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4147 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4148 #define CAN_F1R2_FB7_Pos (7U)
4149 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4150 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4151 #define CAN_F1R2_FB8_Pos (8U)
4152 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4153 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4154 #define CAN_F1R2_FB9_Pos (9U)
4155 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4156 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4157 #define CAN_F1R2_FB10_Pos (10U)
4158 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4159 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4160 #define CAN_F1R2_FB11_Pos (11U)
4161 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4162 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4163 #define CAN_F1R2_FB12_Pos (12U)
4164 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4165 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4166 #define CAN_F1R2_FB13_Pos (13U)
4167 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4168 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4169 #define CAN_F1R2_FB14_Pos (14U)
4170 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4171 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4172 #define CAN_F1R2_FB15_Pos (15U)
4173 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4174 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4175 #define CAN_F1R2_FB16_Pos (16U)
4176 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4177 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4178 #define CAN_F1R2_FB17_Pos (17U)
4179 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4180 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4181 #define CAN_F1R2_FB18_Pos (18U)
4182 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4183 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4184 #define CAN_F1R2_FB19_Pos (19U)
4185 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4186 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4187 #define CAN_F1R2_FB20_Pos (20U)
4188 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4189 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4190 #define CAN_F1R2_FB21_Pos (21U)
4191 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4192 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4193 #define CAN_F1R2_FB22_Pos (22U)
4194 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4195 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4196 #define CAN_F1R2_FB23_Pos (23U)
4197 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4198 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4199 #define CAN_F1R2_FB24_Pos (24U)
4200 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4201 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4202 #define CAN_F1R2_FB25_Pos (25U)
4203 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4204 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4205 #define CAN_F1R2_FB26_Pos (26U)
4206 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4207 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4208 #define CAN_F1R2_FB27_Pos (27U)
4209 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4210 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4211 #define CAN_F1R2_FB28_Pos (28U)
4212 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4213 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4214 #define CAN_F1R2_FB29_Pos (29U)
4215 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4216 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4217 #define CAN_F1R2_FB30_Pos (30U)
4218 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4219 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4220 #define CAN_F1R2_FB31_Pos (31U)
4221 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4222 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4223
4224 /******************* Bit definition for CAN_F2R2 register *******************/
4225 #define CAN_F2R2_FB0_Pos (0U)
4226 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4227 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4228 #define CAN_F2R2_FB1_Pos (1U)
4229 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4230 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4231 #define CAN_F2R2_FB2_Pos (2U)
4232 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4233 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4234 #define CAN_F2R2_FB3_Pos (3U)
4235 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4236 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4237 #define CAN_F2R2_FB4_Pos (4U)
4238 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4239 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4240 #define CAN_F2R2_FB5_Pos (5U)
4241 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4242 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4243 #define CAN_F2R2_FB6_Pos (6U)
4244 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4245 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4246 #define CAN_F2R2_FB7_Pos (7U)
4247 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4248 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4249 #define CAN_F2R2_FB8_Pos (8U)
4250 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4251 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4252 #define CAN_F2R2_FB9_Pos (9U)
4253 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4254 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4255 #define CAN_F2R2_FB10_Pos (10U)
4256 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4257 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4258 #define CAN_F2R2_FB11_Pos (11U)
4259 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4260 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4261 #define CAN_F2R2_FB12_Pos (12U)
4262 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4263 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4264 #define CAN_F2R2_FB13_Pos (13U)
4265 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4266 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4267 #define CAN_F2R2_FB14_Pos (14U)
4268 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4269 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4270 #define CAN_F2R2_FB15_Pos (15U)
4271 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4272 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4273 #define CAN_F2R2_FB16_Pos (16U)
4274 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4275 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4276 #define CAN_F2R2_FB17_Pos (17U)
4277 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4278 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4279 #define CAN_F2R2_FB18_Pos (18U)
4280 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4281 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4282 #define CAN_F2R2_FB19_Pos (19U)
4283 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4284 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4285 #define CAN_F2R2_FB20_Pos (20U)
4286 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4287 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4288 #define CAN_F2R2_FB21_Pos (21U)
4289 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4290 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4291 #define CAN_F2R2_FB22_Pos (22U)
4292 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4293 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4294 #define CAN_F2R2_FB23_Pos (23U)
4295 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4296 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4297 #define CAN_F2R2_FB24_Pos (24U)
4298 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4299 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4300 #define CAN_F2R2_FB25_Pos (25U)
4301 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4302 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4303 #define CAN_F2R2_FB26_Pos (26U)
4304 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4305 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4306 #define CAN_F2R2_FB27_Pos (27U)
4307 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4308 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4309 #define CAN_F2R2_FB28_Pos (28U)
4310 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4311 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4312 #define CAN_F2R2_FB29_Pos (29U)
4313 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4314 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4315 #define CAN_F2R2_FB30_Pos (30U)
4316 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4317 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4318 #define CAN_F2R2_FB31_Pos (31U)
4319 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4320 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4321
4322 /******************* Bit definition for CAN_F3R2 register *******************/
4323 #define CAN_F3R2_FB0_Pos (0U)
4324 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4325 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4326 #define CAN_F3R2_FB1_Pos (1U)
4327 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4328 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4329 #define CAN_F3R2_FB2_Pos (2U)
4330 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4331 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4332 #define CAN_F3R2_FB3_Pos (3U)
4333 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4334 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4335 #define CAN_F3R2_FB4_Pos (4U)
4336 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4337 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4338 #define CAN_F3R2_FB5_Pos (5U)
4339 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4340 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4341 #define CAN_F3R2_FB6_Pos (6U)
4342 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4343 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4344 #define CAN_F3R2_FB7_Pos (7U)
4345 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4346 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4347 #define CAN_F3R2_FB8_Pos (8U)
4348 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4349 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4350 #define CAN_F3R2_FB9_Pos (9U)
4351 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4352 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4353 #define CAN_F3R2_FB10_Pos (10U)
4354 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4355 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4356 #define CAN_F3R2_FB11_Pos (11U)
4357 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4358 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4359 #define CAN_F3R2_FB12_Pos (12U)
4360 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4361 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4362 #define CAN_F3R2_FB13_Pos (13U)
4363 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4364 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4365 #define CAN_F3R2_FB14_Pos (14U)
4366 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4367 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4368 #define CAN_F3R2_FB15_Pos (15U)
4369 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4370 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4371 #define CAN_F3R2_FB16_Pos (16U)
4372 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4373 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4374 #define CAN_F3R2_FB17_Pos (17U)
4375 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4376 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4377 #define CAN_F3R2_FB18_Pos (18U)
4378 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4379 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4380 #define CAN_F3R2_FB19_Pos (19U)
4381 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4382 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4383 #define CAN_F3R2_FB20_Pos (20U)
4384 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4385 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4386 #define CAN_F3R2_FB21_Pos (21U)
4387 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4388 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4389 #define CAN_F3R2_FB22_Pos (22U)
4390 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4391 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4392 #define CAN_F3R2_FB23_Pos (23U)
4393 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4394 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4395 #define CAN_F3R2_FB24_Pos (24U)
4396 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4397 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4398 #define CAN_F3R2_FB25_Pos (25U)
4399 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4400 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4401 #define CAN_F3R2_FB26_Pos (26U)
4402 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4403 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4404 #define CAN_F3R2_FB27_Pos (27U)
4405 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4406 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4407 #define CAN_F3R2_FB28_Pos (28U)
4408 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4409 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4410 #define CAN_F3R2_FB29_Pos (29U)
4411 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4412 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4413 #define CAN_F3R2_FB30_Pos (30U)
4414 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4415 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4416 #define CAN_F3R2_FB31_Pos (31U)
4417 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4418 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4419
4420 /******************* Bit definition for CAN_F4R2 register *******************/
4421 #define CAN_F4R2_FB0_Pos (0U)
4422 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4423 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4424 #define CAN_F4R2_FB1_Pos (1U)
4425 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4426 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4427 #define CAN_F4R2_FB2_Pos (2U)
4428 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4429 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4430 #define CAN_F4R2_FB3_Pos (3U)
4431 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4432 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4433 #define CAN_F4R2_FB4_Pos (4U)
4434 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4435 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4436 #define CAN_F4R2_FB5_Pos (5U)
4437 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4438 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4439 #define CAN_F4R2_FB6_Pos (6U)
4440 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4441 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4442 #define CAN_F4R2_FB7_Pos (7U)
4443 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4444 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4445 #define CAN_F4R2_FB8_Pos (8U)
4446 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4447 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4448 #define CAN_F4R2_FB9_Pos (9U)
4449 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4450 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4451 #define CAN_F4R2_FB10_Pos (10U)
4452 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4453 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4454 #define CAN_F4R2_FB11_Pos (11U)
4455 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4456 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4457 #define CAN_F4R2_FB12_Pos (12U)
4458 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4459 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4460 #define CAN_F4R2_FB13_Pos (13U)
4461 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4462 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4463 #define CAN_F4R2_FB14_Pos (14U)
4464 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4465 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4466 #define CAN_F4R2_FB15_Pos (15U)
4467 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4468 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4469 #define CAN_F4R2_FB16_Pos (16U)
4470 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4471 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4472 #define CAN_F4R2_FB17_Pos (17U)
4473 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4474 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4475 #define CAN_F4R2_FB18_Pos (18U)
4476 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4477 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4478 #define CAN_F4R2_FB19_Pos (19U)
4479 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4480 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4481 #define CAN_F4R2_FB20_Pos (20U)
4482 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4483 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4484 #define CAN_F4R2_FB21_Pos (21U)
4485 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4486 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4487 #define CAN_F4R2_FB22_Pos (22U)
4488 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4489 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4490 #define CAN_F4R2_FB23_Pos (23U)
4491 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4492 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4493 #define CAN_F4R2_FB24_Pos (24U)
4494 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4495 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4496 #define CAN_F4R2_FB25_Pos (25U)
4497 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4498 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4499 #define CAN_F4R2_FB26_Pos (26U)
4500 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4501 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4502 #define CAN_F4R2_FB27_Pos (27U)
4503 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4504 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4505 #define CAN_F4R2_FB28_Pos (28U)
4506 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4507 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4508 #define CAN_F4R2_FB29_Pos (29U)
4509 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4510 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4511 #define CAN_F4R2_FB30_Pos (30U)
4512 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4513 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4514 #define CAN_F4R2_FB31_Pos (31U)
4515 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4516 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4517
4518 /******************* Bit definition for CAN_F5R2 register *******************/
4519 #define CAN_F5R2_FB0_Pos (0U)
4520 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4521 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4522 #define CAN_F5R2_FB1_Pos (1U)
4523 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4524 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4525 #define CAN_F5R2_FB2_Pos (2U)
4526 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4527 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4528 #define CAN_F5R2_FB3_Pos (3U)
4529 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4530 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4531 #define CAN_F5R2_FB4_Pos (4U)
4532 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4533 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4534 #define CAN_F5R2_FB5_Pos (5U)
4535 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4536 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4537 #define CAN_F5R2_FB6_Pos (6U)
4538 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4539 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4540 #define CAN_F5R2_FB7_Pos (7U)
4541 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4542 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4543 #define CAN_F5R2_FB8_Pos (8U)
4544 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4545 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4546 #define CAN_F5R2_FB9_Pos (9U)
4547 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4548 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4549 #define CAN_F5R2_FB10_Pos (10U)
4550 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4551 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4552 #define CAN_F5R2_FB11_Pos (11U)
4553 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4554 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4555 #define CAN_F5R2_FB12_Pos (12U)
4556 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4557 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4558 #define CAN_F5R2_FB13_Pos (13U)
4559 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4560 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4561 #define CAN_F5R2_FB14_Pos (14U)
4562 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4563 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4564 #define CAN_F5R2_FB15_Pos (15U)
4565 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4566 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4567 #define CAN_F5R2_FB16_Pos (16U)
4568 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4569 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4570 #define CAN_F5R2_FB17_Pos (17U)
4571 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4572 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4573 #define CAN_F5R2_FB18_Pos (18U)
4574 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4575 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4576 #define CAN_F5R2_FB19_Pos (19U)
4577 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4578 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4579 #define CAN_F5R2_FB20_Pos (20U)
4580 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4581 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4582 #define CAN_F5R2_FB21_Pos (21U)
4583 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4584 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4585 #define CAN_F5R2_FB22_Pos (22U)
4586 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4587 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4588 #define CAN_F5R2_FB23_Pos (23U)
4589 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4590 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4591 #define CAN_F5R2_FB24_Pos (24U)
4592 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4593 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4594 #define CAN_F5R2_FB25_Pos (25U)
4595 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4596 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4597 #define CAN_F5R2_FB26_Pos (26U)
4598 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4599 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4600 #define CAN_F5R2_FB27_Pos (27U)
4601 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4602 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4603 #define CAN_F5R2_FB28_Pos (28U)
4604 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4605 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4606 #define CAN_F5R2_FB29_Pos (29U)
4607 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4608 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4609 #define CAN_F5R2_FB30_Pos (30U)
4610 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4611 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4612 #define CAN_F5R2_FB31_Pos (31U)
4613 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4614 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4615
4616 /******************* Bit definition for CAN_F6R2 register *******************/
4617 #define CAN_F6R2_FB0_Pos (0U)
4618 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4619 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4620 #define CAN_F6R2_FB1_Pos (1U)
4621 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4622 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4623 #define CAN_F6R2_FB2_Pos (2U)
4624 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4625 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4626 #define CAN_F6R2_FB3_Pos (3U)
4627 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4628 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4629 #define CAN_F6R2_FB4_Pos (4U)
4630 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4631 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4632 #define CAN_F6R2_FB5_Pos (5U)
4633 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4634 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4635 #define CAN_F6R2_FB6_Pos (6U)
4636 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4637 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4638 #define CAN_F6R2_FB7_Pos (7U)
4639 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4640 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4641 #define CAN_F6R2_FB8_Pos (8U)
4642 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4643 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4644 #define CAN_F6R2_FB9_Pos (9U)
4645 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4646 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4647 #define CAN_F6R2_FB10_Pos (10U)
4648 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4649 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4650 #define CAN_F6R2_FB11_Pos (11U)
4651 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4652 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4653 #define CAN_F6R2_FB12_Pos (12U)
4654 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4655 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4656 #define CAN_F6R2_FB13_Pos (13U)
4657 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4658 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4659 #define CAN_F6R2_FB14_Pos (14U)
4660 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4661 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4662 #define CAN_F6R2_FB15_Pos (15U)
4663 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4664 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4665 #define CAN_F6R2_FB16_Pos (16U)
4666 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4667 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4668 #define CAN_F6R2_FB17_Pos (17U)
4669 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4670 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4671 #define CAN_F6R2_FB18_Pos (18U)
4672 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4673 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4674 #define CAN_F6R2_FB19_Pos (19U)
4675 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4676 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4677 #define CAN_F6R2_FB20_Pos (20U)
4678 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4679 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4680 #define CAN_F6R2_FB21_Pos (21U)
4681 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4682 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4683 #define CAN_F6R2_FB22_Pos (22U)
4684 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4685 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4686 #define CAN_F6R2_FB23_Pos (23U)
4687 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4688 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4689 #define CAN_F6R2_FB24_Pos (24U)
4690 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4691 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4692 #define CAN_F6R2_FB25_Pos (25U)
4693 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4694 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4695 #define CAN_F6R2_FB26_Pos (26U)
4696 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4697 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4698 #define CAN_F6R2_FB27_Pos (27U)
4699 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4700 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4701 #define CAN_F6R2_FB28_Pos (28U)
4702 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
4703 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
4704 #define CAN_F6R2_FB29_Pos (29U)
4705 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
4706 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
4707 #define CAN_F6R2_FB30_Pos (30U)
4708 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
4709 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
4710 #define CAN_F6R2_FB31_Pos (31U)
4711 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
4712 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
4713
4714 /******************* Bit definition for CAN_F7R2 register *******************/
4715 #define CAN_F7R2_FB0_Pos (0U)
4716 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
4717 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
4718 #define CAN_F7R2_FB1_Pos (1U)
4719 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
4720 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
4721 #define CAN_F7R2_FB2_Pos (2U)
4722 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
4723 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
4724 #define CAN_F7R2_FB3_Pos (3U)
4725 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
4726 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
4727 #define CAN_F7R2_FB4_Pos (4U)
4728 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
4729 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
4730 #define CAN_F7R2_FB5_Pos (5U)
4731 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
4732 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
4733 #define CAN_F7R2_FB6_Pos (6U)
4734 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
4735 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
4736 #define CAN_F7R2_FB7_Pos (7U)
4737 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
4738 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
4739 #define CAN_F7R2_FB8_Pos (8U)
4740 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
4741 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
4742 #define CAN_F7R2_FB9_Pos (9U)
4743 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
4744 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
4745 #define CAN_F7R2_FB10_Pos (10U)
4746 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
4747 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
4748 #define CAN_F7R2_FB11_Pos (11U)
4749 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
4750 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
4751 #define CAN_F7R2_FB12_Pos (12U)
4752 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
4753 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
4754 #define CAN_F7R2_FB13_Pos (13U)
4755 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
4756 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
4757 #define CAN_F7R2_FB14_Pos (14U)
4758 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
4759 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
4760 #define CAN_F7R2_FB15_Pos (15U)
4761 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
4762 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
4763 #define CAN_F7R2_FB16_Pos (16U)
4764 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
4765 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
4766 #define CAN_F7R2_FB17_Pos (17U)
4767 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
4768 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
4769 #define CAN_F7R2_FB18_Pos (18U)
4770 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
4771 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
4772 #define CAN_F7R2_FB19_Pos (19U)
4773 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
4774 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
4775 #define CAN_F7R2_FB20_Pos (20U)
4776 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
4777 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
4778 #define CAN_F7R2_FB21_Pos (21U)
4779 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
4780 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
4781 #define CAN_F7R2_FB22_Pos (22U)
4782 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
4783 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
4784 #define CAN_F7R2_FB23_Pos (23U)
4785 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
4786 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
4787 #define CAN_F7R2_FB24_Pos (24U)
4788 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
4789 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
4790 #define CAN_F7R2_FB25_Pos (25U)
4791 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
4792 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
4793 #define CAN_F7R2_FB26_Pos (26U)
4794 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
4795 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
4796 #define CAN_F7R2_FB27_Pos (27U)
4797 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
4798 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
4799 #define CAN_F7R2_FB28_Pos (28U)
4800 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
4801 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
4802 #define CAN_F7R2_FB29_Pos (29U)
4803 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
4804 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
4805 #define CAN_F7R2_FB30_Pos (30U)
4806 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
4807 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
4808 #define CAN_F7R2_FB31_Pos (31U)
4809 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
4810 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
4811
4812 /******************* Bit definition for CAN_F8R2 register *******************/
4813 #define CAN_F8R2_FB0_Pos (0U)
4814 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
4815 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
4816 #define CAN_F8R2_FB1_Pos (1U)
4817 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
4818 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
4819 #define CAN_F8R2_FB2_Pos (2U)
4820 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
4821 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
4822 #define CAN_F8R2_FB3_Pos (3U)
4823 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
4824 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
4825 #define CAN_F8R2_FB4_Pos (4U)
4826 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
4827 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
4828 #define CAN_F8R2_FB5_Pos (5U)
4829 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
4830 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
4831 #define CAN_F8R2_FB6_Pos (6U)
4832 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
4833 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
4834 #define CAN_F8R2_FB7_Pos (7U)
4835 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
4836 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
4837 #define CAN_F8R2_FB8_Pos (8U)
4838 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
4839 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
4840 #define CAN_F8R2_FB9_Pos (9U)
4841 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
4842 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
4843 #define CAN_F8R2_FB10_Pos (10U)
4844 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
4845 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
4846 #define CAN_F8R2_FB11_Pos (11U)
4847 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
4848 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
4849 #define CAN_F8R2_FB12_Pos (12U)
4850 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
4851 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
4852 #define CAN_F8R2_FB13_Pos (13U)
4853 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
4854 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
4855 #define CAN_F8R2_FB14_Pos (14U)
4856 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
4857 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
4858 #define CAN_F8R2_FB15_Pos (15U)
4859 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
4860 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
4861 #define CAN_F8R2_FB16_Pos (16U)
4862 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
4863 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
4864 #define CAN_F8R2_FB17_Pos (17U)
4865 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
4866 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
4867 #define CAN_F8R2_FB18_Pos (18U)
4868 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
4869 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
4870 #define CAN_F8R2_FB19_Pos (19U)
4871 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
4872 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
4873 #define CAN_F8R2_FB20_Pos (20U)
4874 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
4875 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
4876 #define CAN_F8R2_FB21_Pos (21U)
4877 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
4878 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
4879 #define CAN_F8R2_FB22_Pos (22U)
4880 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
4881 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
4882 #define CAN_F8R2_FB23_Pos (23U)
4883 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
4884 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
4885 #define CAN_F8R2_FB24_Pos (24U)
4886 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
4887 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
4888 #define CAN_F8R2_FB25_Pos (25U)
4889 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
4890 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
4891 #define CAN_F8R2_FB26_Pos (26U)
4892 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
4893 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
4894 #define CAN_F8R2_FB27_Pos (27U)
4895 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
4896 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
4897 #define CAN_F8R2_FB28_Pos (28U)
4898 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
4899 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
4900 #define CAN_F8R2_FB29_Pos (29U)
4901 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
4902 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
4903 #define CAN_F8R2_FB30_Pos (30U)
4904 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
4905 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
4906 #define CAN_F8R2_FB31_Pos (31U)
4907 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
4908 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
4909
4910 /******************* Bit definition for CAN_F9R2 register *******************/
4911 #define CAN_F9R2_FB0_Pos (0U)
4912 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
4913 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
4914 #define CAN_F9R2_FB1_Pos (1U)
4915 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
4916 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
4917 #define CAN_F9R2_FB2_Pos (2U)
4918 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
4919 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
4920 #define CAN_F9R2_FB3_Pos (3U)
4921 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
4922 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
4923 #define CAN_F9R2_FB4_Pos (4U)
4924 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
4925 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
4926 #define CAN_F9R2_FB5_Pos (5U)
4927 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
4928 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
4929 #define CAN_F9R2_FB6_Pos (6U)
4930 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
4931 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
4932 #define CAN_F9R2_FB7_Pos (7U)
4933 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
4934 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
4935 #define CAN_F9R2_FB8_Pos (8U)
4936 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
4937 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
4938 #define CAN_F9R2_FB9_Pos (9U)
4939 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
4940 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
4941 #define CAN_F9R2_FB10_Pos (10U)
4942 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
4943 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
4944 #define CAN_F9R2_FB11_Pos (11U)
4945 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
4946 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
4947 #define CAN_F9R2_FB12_Pos (12U)
4948 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
4949 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
4950 #define CAN_F9R2_FB13_Pos (13U)
4951 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
4952 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
4953 #define CAN_F9R2_FB14_Pos (14U)
4954 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
4955 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
4956 #define CAN_F9R2_FB15_Pos (15U)
4957 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
4958 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
4959 #define CAN_F9R2_FB16_Pos (16U)
4960 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
4961 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
4962 #define CAN_F9R2_FB17_Pos (17U)
4963 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
4964 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
4965 #define CAN_F9R2_FB18_Pos (18U)
4966 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
4967 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
4968 #define CAN_F9R2_FB19_Pos (19U)
4969 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
4970 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
4971 #define CAN_F9R2_FB20_Pos (20U)
4972 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
4973 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
4974 #define CAN_F9R2_FB21_Pos (21U)
4975 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
4976 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
4977 #define CAN_F9R2_FB22_Pos (22U)
4978 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
4979 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
4980 #define CAN_F9R2_FB23_Pos (23U)
4981 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
4982 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
4983 #define CAN_F9R2_FB24_Pos (24U)
4984 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
4985 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
4986 #define CAN_F9R2_FB25_Pos (25U)
4987 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
4988 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
4989 #define CAN_F9R2_FB26_Pos (26U)
4990 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
4991 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
4992 #define CAN_F9R2_FB27_Pos (27U)
4993 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
4994 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
4995 #define CAN_F9R2_FB28_Pos (28U)
4996 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
4997 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
4998 #define CAN_F9R2_FB29_Pos (29U)
4999 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5000 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5001 #define CAN_F9R2_FB30_Pos (30U)
5002 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5003 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5004 #define CAN_F9R2_FB31_Pos (31U)
5005 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5006 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5007
5008 /******************* Bit definition for CAN_F10R2 register ******************/
5009 #define CAN_F10R2_FB0_Pos (0U)
5010 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5011 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5012 #define CAN_F10R2_FB1_Pos (1U)
5013 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5014 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5015 #define CAN_F10R2_FB2_Pos (2U)
5016 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5017 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5018 #define CAN_F10R2_FB3_Pos (3U)
5019 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5020 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5021 #define CAN_F10R2_FB4_Pos (4U)
5022 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5023 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5024 #define CAN_F10R2_FB5_Pos (5U)
5025 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5026 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5027 #define CAN_F10R2_FB6_Pos (6U)
5028 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5029 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5030 #define CAN_F10R2_FB7_Pos (7U)
5031 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5032 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5033 #define CAN_F10R2_FB8_Pos (8U)
5034 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5035 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5036 #define CAN_F10R2_FB9_Pos (9U)
5037 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5038 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5039 #define CAN_F10R2_FB10_Pos (10U)
5040 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5041 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5042 #define CAN_F10R2_FB11_Pos (11U)
5043 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5044 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5045 #define CAN_F10R2_FB12_Pos (12U)
5046 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5047 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5048 #define CAN_F10R2_FB13_Pos (13U)
5049 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5050 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5051 #define CAN_F10R2_FB14_Pos (14U)
5052 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5053 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5054 #define CAN_F10R2_FB15_Pos (15U)
5055 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5056 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5057 #define CAN_F10R2_FB16_Pos (16U)
5058 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5059 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5060 #define CAN_F10R2_FB17_Pos (17U)
5061 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5062 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5063 #define CAN_F10R2_FB18_Pos (18U)
5064 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5065 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5066 #define CAN_F10R2_FB19_Pos (19U)
5067 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5068 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5069 #define CAN_F10R2_FB20_Pos (20U)
5070 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5071 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5072 #define CAN_F10R2_FB21_Pos (21U)
5073 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5074 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5075 #define CAN_F10R2_FB22_Pos (22U)
5076 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5077 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5078 #define CAN_F10R2_FB23_Pos (23U)
5079 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5080 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5081 #define CAN_F10R2_FB24_Pos (24U)
5082 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5083 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5084 #define CAN_F10R2_FB25_Pos (25U)
5085 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5086 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5087 #define CAN_F10R2_FB26_Pos (26U)
5088 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5089 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5090 #define CAN_F10R2_FB27_Pos (27U)
5091 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5092 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5093 #define CAN_F10R2_FB28_Pos (28U)
5094 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5095 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5096 #define CAN_F10R2_FB29_Pos (29U)
5097 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5098 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5099 #define CAN_F10R2_FB30_Pos (30U)
5100 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5101 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5102 #define CAN_F10R2_FB31_Pos (31U)
5103 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5104 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5105
5106 /******************* Bit definition for CAN_F11R2 register ******************/
5107 #define CAN_F11R2_FB0_Pos (0U)
5108 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5109 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5110 #define CAN_F11R2_FB1_Pos (1U)
5111 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5112 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5113 #define CAN_F11R2_FB2_Pos (2U)
5114 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5115 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5116 #define CAN_F11R2_FB3_Pos (3U)
5117 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5118 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5119 #define CAN_F11R2_FB4_Pos (4U)
5120 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5121 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5122 #define CAN_F11R2_FB5_Pos (5U)
5123 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5124 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5125 #define CAN_F11R2_FB6_Pos (6U)
5126 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5127 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5128 #define CAN_F11R2_FB7_Pos (7U)
5129 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5130 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5131 #define CAN_F11R2_FB8_Pos (8U)
5132 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5133 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5134 #define CAN_F11R2_FB9_Pos (9U)
5135 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5136 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5137 #define CAN_F11R2_FB10_Pos (10U)
5138 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5139 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5140 #define CAN_F11R2_FB11_Pos (11U)
5141 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5142 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5143 #define CAN_F11R2_FB12_Pos (12U)
5144 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5145 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5146 #define CAN_F11R2_FB13_Pos (13U)
5147 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5148 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5149 #define CAN_F11R2_FB14_Pos (14U)
5150 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5151 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5152 #define CAN_F11R2_FB15_Pos (15U)
5153 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5154 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5155 #define CAN_F11R2_FB16_Pos (16U)
5156 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5157 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5158 #define CAN_F11R2_FB17_Pos (17U)
5159 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5160 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5161 #define CAN_F11R2_FB18_Pos (18U)
5162 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5163 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5164 #define CAN_F11R2_FB19_Pos (19U)
5165 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5166 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5167 #define CAN_F11R2_FB20_Pos (20U)
5168 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5169 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5170 #define CAN_F11R2_FB21_Pos (21U)
5171 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5172 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5173 #define CAN_F11R2_FB22_Pos (22U)
5174 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5175 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5176 #define CAN_F11R2_FB23_Pos (23U)
5177 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5178 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5179 #define CAN_F11R2_FB24_Pos (24U)
5180 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5181 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5182 #define CAN_F11R2_FB25_Pos (25U)
5183 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5184 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5185 #define CAN_F11R2_FB26_Pos (26U)
5186 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5187 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5188 #define CAN_F11R2_FB27_Pos (27U)
5189 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5190 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5191 #define CAN_F11R2_FB28_Pos (28U)
5192 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5193 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5194 #define CAN_F11R2_FB29_Pos (29U)
5195 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5196 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5197 #define CAN_F11R2_FB30_Pos (30U)
5198 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5199 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5200 #define CAN_F11R2_FB31_Pos (31U)
5201 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5202 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5203
5204 /******************* Bit definition for CAN_F12R2 register ******************/
5205 #define CAN_F12R2_FB0_Pos (0U)
5206 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5207 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5208 #define CAN_F12R2_FB1_Pos (1U)
5209 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5210 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5211 #define CAN_F12R2_FB2_Pos (2U)
5212 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5213 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5214 #define CAN_F12R2_FB3_Pos (3U)
5215 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5216 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5217 #define CAN_F12R2_FB4_Pos (4U)
5218 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5219 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5220 #define CAN_F12R2_FB5_Pos (5U)
5221 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5222 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5223 #define CAN_F12R2_FB6_Pos (6U)
5224 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5225 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5226 #define CAN_F12R2_FB7_Pos (7U)
5227 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5228 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5229 #define CAN_F12R2_FB8_Pos (8U)
5230 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5231 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5232 #define CAN_F12R2_FB9_Pos (9U)
5233 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5234 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5235 #define CAN_F12R2_FB10_Pos (10U)
5236 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5237 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5238 #define CAN_F12R2_FB11_Pos (11U)
5239 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5240 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5241 #define CAN_F12R2_FB12_Pos (12U)
5242 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5243 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5244 #define CAN_F12R2_FB13_Pos (13U)
5245 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5246 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5247 #define CAN_F12R2_FB14_Pos (14U)
5248 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5249 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5250 #define CAN_F12R2_FB15_Pos (15U)
5251 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5252 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5253 #define CAN_F12R2_FB16_Pos (16U)
5254 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5255 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5256 #define CAN_F12R2_FB17_Pos (17U)
5257 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5258 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5259 #define CAN_F12R2_FB18_Pos (18U)
5260 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5261 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5262 #define CAN_F12R2_FB19_Pos (19U)
5263 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5264 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5265 #define CAN_F12R2_FB20_Pos (20U)
5266 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5267 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5268 #define CAN_F12R2_FB21_Pos (21U)
5269 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5270 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5271 #define CAN_F12R2_FB22_Pos (22U)
5272 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5273 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5274 #define CAN_F12R2_FB23_Pos (23U)
5275 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5276 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5277 #define CAN_F12R2_FB24_Pos (24U)
5278 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5279 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5280 #define CAN_F12R2_FB25_Pos (25U)
5281 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5282 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5283 #define CAN_F12R2_FB26_Pos (26U)
5284 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5285 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5286 #define CAN_F12R2_FB27_Pos (27U)
5287 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5288 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5289 #define CAN_F12R2_FB28_Pos (28U)
5290 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5291 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5292 #define CAN_F12R2_FB29_Pos (29U)
5293 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5294 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5295 #define CAN_F12R2_FB30_Pos (30U)
5296 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5297 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5298 #define CAN_F12R2_FB31_Pos (31U)
5299 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5300 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5301
5302 /******************* Bit definition for CAN_F13R2 register ******************/
5303 #define CAN_F13R2_FB0_Pos (0U)
5304 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5305 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5306 #define CAN_F13R2_FB1_Pos (1U)
5307 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5308 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5309 #define CAN_F13R2_FB2_Pos (2U)
5310 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5311 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5312 #define CAN_F13R2_FB3_Pos (3U)
5313 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5314 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5315 #define CAN_F13R2_FB4_Pos (4U)
5316 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5317 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5318 #define CAN_F13R2_FB5_Pos (5U)
5319 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5320 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5321 #define CAN_F13R2_FB6_Pos (6U)
5322 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5323 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5324 #define CAN_F13R2_FB7_Pos (7U)
5325 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5326 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5327 #define CAN_F13R2_FB8_Pos (8U)
5328 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5329 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5330 #define CAN_F13R2_FB9_Pos (9U)
5331 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5332 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5333 #define CAN_F13R2_FB10_Pos (10U)
5334 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5335 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5336 #define CAN_F13R2_FB11_Pos (11U)
5337 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5338 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5339 #define CAN_F13R2_FB12_Pos (12U)
5340 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5341 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5342 #define CAN_F13R2_FB13_Pos (13U)
5343 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5344 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5345 #define CAN_F13R2_FB14_Pos (14U)
5346 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5347 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5348 #define CAN_F13R2_FB15_Pos (15U)
5349 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5350 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5351 #define CAN_F13R2_FB16_Pos (16U)
5352 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5353 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5354 #define CAN_F13R2_FB17_Pos (17U)
5355 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5356 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5357 #define CAN_F13R2_FB18_Pos (18U)
5358 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5359 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5360 #define CAN_F13R2_FB19_Pos (19U)
5361 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5362 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5363 #define CAN_F13R2_FB20_Pos (20U)
5364 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5365 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5366 #define CAN_F13R2_FB21_Pos (21U)
5367 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5368 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5369 #define CAN_F13R2_FB22_Pos (22U)
5370 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5371 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5372 #define CAN_F13R2_FB23_Pos (23U)
5373 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5374 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5375 #define CAN_F13R2_FB24_Pos (24U)
5376 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5377 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5378 #define CAN_F13R2_FB25_Pos (25U)
5379 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5380 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5381 #define CAN_F13R2_FB26_Pos (26U)
5382 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5383 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5384 #define CAN_F13R2_FB27_Pos (27U)
5385 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5386 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5387 #define CAN_F13R2_FB28_Pos (28U)
5388 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5389 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5390 #define CAN_F13R2_FB29_Pos (29U)
5391 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5392 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5393 #define CAN_F13R2_FB30_Pos (30U)
5394 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5395 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5396 #define CAN_F13R2_FB31_Pos (31U)
5397 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5398 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5399
5400 /******************************************************************************/
5401 /* */
5402 /* CRC calculation unit */
5403 /* */
5404 /******************************************************************************/
5405 /******************* Bit definition for CRC_DR register *********************/
5406 #define CRC_DR_DR_Pos (0U)
5407 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5408 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5409
5410
5411 /******************* Bit definition for CRC_IDR register ********************/
5412 #define CRC_IDR_IDR_Pos (0U)
5413 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5414 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5415
5416
5417 /******************** Bit definition for CRC_CR register ********************/
5418 #define CRC_CR_RESET_Pos (0U)
5419 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5420 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5421
5422 /******************************************************************************/
5423 /* */
5424 /* Crypto Processor */
5425 /* */
5426 /******************************************************************************/
5427 /******************* Bits definition for CRYP_CR register ********************/
5428 #define CRYP_CR_ALGODIR_Pos (2U)
5429 #define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
5430 #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5431
5432 #define CRYP_CR_ALGOMODE_Pos (3U)
5433 #define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
5434 #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5435 #define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
5436 #define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
5437 #define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
5438 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
5439 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5440 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5441 #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5442 #define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5443 #define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5444 #define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5445 #define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5446 #define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5447 #define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5448 #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5449 #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5450 #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5451 #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5452 #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5453 #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5454 #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5455 #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5456 #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5457 #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5458 #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5459 #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5460
5461 #define CRYP_CR_DATATYPE_Pos (6U)
5462 #define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
5463 #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5464 #define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
5465 #define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
5466 #define CRYP_CR_KEYSIZE_Pos (8U)
5467 #define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
5468 #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5469 #define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
5470 #define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
5471 #define CRYP_CR_FFLUSH_Pos (14U)
5472 #define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
5473 #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5474 #define CRYP_CR_CRYPEN_Pos (15U)
5475 #define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
5476 #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5477
5478 #define CRYP_CR_GCM_CCMPH_Pos (16U)
5479 #define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
5480 #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5481 #define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
5482 #define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
5483 #define CRYP_CR_ALGOMODE_3 0x00080000U
5484
5485 /****************** Bits definition for CRYP_SR register *********************/
5486 #define CRYP_SR_IFEM_Pos (0U)
5487 #define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
5488 #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5489 #define CRYP_SR_IFNF_Pos (1U)
5490 #define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
5491 #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5492 #define CRYP_SR_OFNE_Pos (2U)
5493 #define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
5494 #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5495 #define CRYP_SR_OFFU_Pos (3U)
5496 #define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
5497 #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5498 #define CRYP_SR_BUSY_Pos (4U)
5499 #define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
5500 #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5501 /****************** Bits definition for CRYP_DMACR register ******************/
5502 #define CRYP_DMACR_DIEN_Pos (0U)
5503 #define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
5504 #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5505 #define CRYP_DMACR_DOEN_Pos (1U)
5506 #define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
5507 #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5508 /***************** Bits definition for CRYP_IMSCR register ******************/
5509 #define CRYP_IMSCR_INIM_Pos (0U)
5510 #define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
5511 #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5512 #define CRYP_IMSCR_OUTIM_Pos (1U)
5513 #define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
5514 #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5515 /****************** Bits definition for CRYP_RISR register *******************/
5516 #define CRYP_RISR_OUTRIS_Pos (0U)
5517 #define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
5518 #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5519 #define CRYP_RISR_INRIS_Pos (1U)
5520 #define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
5521 #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5522 /****************** Bits definition for CRYP_MISR register *******************/
5523 #define CRYP_MISR_INMIS_Pos (0U)
5524 #define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
5525 #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5526 #define CRYP_MISR_OUTMIS_Pos (1U)
5527 #define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
5528 #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5529
5530 /******************************************************************************/
5531 /* */
5532 /* Digital to Analog Converter */
5533 /* */
5534 /******************************************************************************/
5535 /*
5536 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5537 */
5538 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5539 /******************** Bit definition for DAC_CR register ********************/
5540 #define DAC_CR_EN1_Pos (0U)
5541 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5542 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5543 #define DAC_CR_BOFF1_Pos (1U)
5544 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5545 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5546 #define DAC_CR_TEN1_Pos (2U)
5547 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5548 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5549
5550 #define DAC_CR_TSEL1_Pos (3U)
5551 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5552 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5553 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5554 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5555 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5556
5557 #define DAC_CR_WAVE1_Pos (6U)
5558 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5559 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5560 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5561 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5562
5563 #define DAC_CR_MAMP1_Pos (8U)
5564 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5565 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5566 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5567 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5568 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5569 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5570
5571 #define DAC_CR_DMAEN1_Pos (12U)
5572 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5573 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5574 #define DAC_CR_DMAUDRIE1_Pos (13U)
5575 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5576 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5577 #define DAC_CR_EN2_Pos (16U)
5578 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5579 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5580 #define DAC_CR_BOFF2_Pos (17U)
5581 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5582 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5583 #define DAC_CR_TEN2_Pos (18U)
5584 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5585 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5586
5587 #define DAC_CR_TSEL2_Pos (19U)
5588 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5589 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5590 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5591 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5592 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5593
5594 #define DAC_CR_WAVE2_Pos (22U)
5595 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5596 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5597 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5598 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5599
5600 #define DAC_CR_MAMP2_Pos (24U)
5601 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5602 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5603 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5604 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5605 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5606 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5607
5608 #define DAC_CR_DMAEN2_Pos (28U)
5609 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5610 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5611 #define DAC_CR_DMAUDRIE2_Pos (29U)
5612 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5613 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5614
5615 /***************** Bit definition for DAC_SWTRIGR register ******************/
5616 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5617 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5618 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5619 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5620 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5621 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5622
5623 /***************** Bit definition for DAC_DHR12R1 register ******************/
5624 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5625 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5626 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5627
5628 /***************** Bit definition for DAC_DHR12L1 register ******************/
5629 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5630 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5631 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5632
5633 /****************** Bit definition for DAC_DHR8R1 register ******************/
5634 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5635 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5636 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5637
5638 /***************** Bit definition for DAC_DHR12R2 register ******************/
5639 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5640 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5641 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5642
5643 /***************** Bit definition for DAC_DHR12L2 register ******************/
5644 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5645 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5646 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5647
5648 /****************** Bit definition for DAC_DHR8R2 register ******************/
5649 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5650 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5651 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5652
5653 /***************** Bit definition for DAC_DHR12RD register ******************/
5654 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5655 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5656 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5657 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5658 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5659 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5660
5661 /***************** Bit definition for DAC_DHR12LD register ******************/
5662 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5663 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5664 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5665 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5666 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5667 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5668
5669 /****************** Bit definition for DAC_DHR8RD register ******************/
5670 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5671 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5672 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5673 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5674 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5675 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5676
5677 /******************* Bit definition for DAC_DOR1 register *******************/
5678 #define DAC_DOR1_DACC1DOR_Pos (0U)
5679 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5680 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5681
5682 /******************* Bit definition for DAC_DOR2 register *******************/
5683 #define DAC_DOR2_DACC2DOR_Pos (0U)
5684 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5685 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5686
5687 /******************** Bit definition for DAC_SR register ********************/
5688 #define DAC_SR_DMAUDR1_Pos (13U)
5689 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5690 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5691 #define DAC_SR_DMAUDR2_Pos (29U)
5692 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5693 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5694
5695
5696 /******************************************************************************/
5697 /* */
5698 /* DMA Controller */
5699 /* */
5700 /******************************************************************************/
5701 /******************** Bits definition for DMA_SxCR register *****************/
5702 #define DMA_SxCR_CHSEL_Pos (25U)
5703 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
5704 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5705 #define DMA_SxCR_CHSEL_0 0x02000000U
5706 #define DMA_SxCR_CHSEL_1 0x04000000U
5707 #define DMA_SxCR_CHSEL_2 0x08000000U
5708 #define DMA_SxCR_MBURST_Pos (23U)
5709 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
5710 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5711 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
5712 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
5713 #define DMA_SxCR_PBURST_Pos (21U)
5714 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
5715 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5716 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
5717 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
5718 #define DMA_SxCR_CT_Pos (19U)
5719 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
5720 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
5721 #define DMA_SxCR_DBM_Pos (18U)
5722 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
5723 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5724 #define DMA_SxCR_PL_Pos (16U)
5725 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
5726 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
5727 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
5728 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
5729 #define DMA_SxCR_PINCOS_Pos (15U)
5730 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
5731 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5732 #define DMA_SxCR_MSIZE_Pos (13U)
5733 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
5734 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5735 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
5736 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
5737 #define DMA_SxCR_PSIZE_Pos (11U)
5738 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
5739 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5740 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
5741 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
5742 #define DMA_SxCR_MINC_Pos (10U)
5743 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5744 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5745 #define DMA_SxCR_PINC_Pos (9U)
5746 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
5747 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5748 #define DMA_SxCR_CIRC_Pos (8U)
5749 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
5750 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5751 #define DMA_SxCR_DIR_Pos (6U)
5752 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
5753 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5754 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
5755 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
5756 #define DMA_SxCR_PFCTRL_Pos (5U)
5757 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
5758 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5759 #define DMA_SxCR_TCIE_Pos (4U)
5760 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
5761 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5762 #define DMA_SxCR_HTIE_Pos (3U)
5763 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
5764 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5765 #define DMA_SxCR_TEIE_Pos (2U)
5766 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
5767 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5768 #define DMA_SxCR_DMEIE_Pos (1U)
5769 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
5770 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5771 #define DMA_SxCR_EN_Pos (0U)
5772 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
5773 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
5774
5775 /* Legacy defines */
5776 #define DMA_SxCR_ACK_Pos (20U)
5777 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
5778 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
5779
5780 /******************** Bits definition for DMA_SxCNDTR register **************/
5781 #define DMA_SxNDT_Pos (0U)
5782 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
5783 #define DMA_SxNDT DMA_SxNDT_Msk
5784 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
5785 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
5786 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
5787 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
5788 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
5789 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
5790 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
5791 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
5792 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
5793 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
5794 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
5795 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
5796 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
5797 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
5798 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
5799 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
5800
5801 /******************** Bits definition for DMA_SxFCR register ****************/
5802 #define DMA_SxFCR_FEIE_Pos (7U)
5803 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
5804 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
5805 #define DMA_SxFCR_FS_Pos (3U)
5806 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
5807 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
5808 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
5809 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
5810 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
5811 #define DMA_SxFCR_DMDIS_Pos (2U)
5812 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
5813 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
5814 #define DMA_SxFCR_FTH_Pos (0U)
5815 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
5816 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
5817 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
5818 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
5819
5820 /******************** Bits definition for DMA_LISR register *****************/
5821 #define DMA_LISR_TCIF3_Pos (27U)
5822 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
5823 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
5824 #define DMA_LISR_HTIF3_Pos (26U)
5825 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
5826 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
5827 #define DMA_LISR_TEIF3_Pos (25U)
5828 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
5829 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
5830 #define DMA_LISR_DMEIF3_Pos (24U)
5831 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
5832 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
5833 #define DMA_LISR_FEIF3_Pos (22U)
5834 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
5835 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
5836 #define DMA_LISR_TCIF2_Pos (21U)
5837 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
5838 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
5839 #define DMA_LISR_HTIF2_Pos (20U)
5840 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
5841 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
5842 #define DMA_LISR_TEIF2_Pos (19U)
5843 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
5844 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
5845 #define DMA_LISR_DMEIF2_Pos (18U)
5846 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
5847 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
5848 #define DMA_LISR_FEIF2_Pos (16U)
5849 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
5850 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
5851 #define DMA_LISR_TCIF1_Pos (11U)
5852 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
5853 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
5854 #define DMA_LISR_HTIF1_Pos (10U)
5855 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
5856 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
5857 #define DMA_LISR_TEIF1_Pos (9U)
5858 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
5859 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
5860 #define DMA_LISR_DMEIF1_Pos (8U)
5861 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
5862 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
5863 #define DMA_LISR_FEIF1_Pos (6U)
5864 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
5865 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
5866 #define DMA_LISR_TCIF0_Pos (5U)
5867 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
5868 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
5869 #define DMA_LISR_HTIF0_Pos (4U)
5870 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
5871 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
5872 #define DMA_LISR_TEIF0_Pos (3U)
5873 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
5874 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
5875 #define DMA_LISR_DMEIF0_Pos (2U)
5876 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
5877 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
5878 #define DMA_LISR_FEIF0_Pos (0U)
5879 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
5880 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
5881
5882 /******************** Bits definition for DMA_HISR register *****************/
5883 #define DMA_HISR_TCIF7_Pos (27U)
5884 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
5885 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
5886 #define DMA_HISR_HTIF7_Pos (26U)
5887 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
5888 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
5889 #define DMA_HISR_TEIF7_Pos (25U)
5890 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
5891 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
5892 #define DMA_HISR_DMEIF7_Pos (24U)
5893 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
5894 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
5895 #define DMA_HISR_FEIF7_Pos (22U)
5896 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
5897 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
5898 #define DMA_HISR_TCIF6_Pos (21U)
5899 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
5900 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
5901 #define DMA_HISR_HTIF6_Pos (20U)
5902 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
5903 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
5904 #define DMA_HISR_TEIF6_Pos (19U)
5905 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
5906 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
5907 #define DMA_HISR_DMEIF6_Pos (18U)
5908 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
5909 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
5910 #define DMA_HISR_FEIF6_Pos (16U)
5911 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
5912 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
5913 #define DMA_HISR_TCIF5_Pos (11U)
5914 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
5915 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
5916 #define DMA_HISR_HTIF5_Pos (10U)
5917 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
5918 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
5919 #define DMA_HISR_TEIF5_Pos (9U)
5920 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
5921 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
5922 #define DMA_HISR_DMEIF5_Pos (8U)
5923 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
5924 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
5925 #define DMA_HISR_FEIF5_Pos (6U)
5926 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
5927 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
5928 #define DMA_HISR_TCIF4_Pos (5U)
5929 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
5930 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
5931 #define DMA_HISR_HTIF4_Pos (4U)
5932 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
5933 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
5934 #define DMA_HISR_TEIF4_Pos (3U)
5935 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
5936 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
5937 #define DMA_HISR_DMEIF4_Pos (2U)
5938 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
5939 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
5940 #define DMA_HISR_FEIF4_Pos (0U)
5941 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
5942 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
5943
5944 /******************** Bits definition for DMA_LIFCR register ****************/
5945 #define DMA_LIFCR_CTCIF3_Pos (27U)
5946 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
5947 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
5948 #define DMA_LIFCR_CHTIF3_Pos (26U)
5949 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
5950 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
5951 #define DMA_LIFCR_CTEIF3_Pos (25U)
5952 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
5953 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
5954 #define DMA_LIFCR_CDMEIF3_Pos (24U)
5955 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
5956 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
5957 #define DMA_LIFCR_CFEIF3_Pos (22U)
5958 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
5959 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
5960 #define DMA_LIFCR_CTCIF2_Pos (21U)
5961 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
5962 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
5963 #define DMA_LIFCR_CHTIF2_Pos (20U)
5964 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
5965 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
5966 #define DMA_LIFCR_CTEIF2_Pos (19U)
5967 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
5968 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
5969 #define DMA_LIFCR_CDMEIF2_Pos (18U)
5970 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
5971 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
5972 #define DMA_LIFCR_CFEIF2_Pos (16U)
5973 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
5974 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
5975 #define DMA_LIFCR_CTCIF1_Pos (11U)
5976 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
5977 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
5978 #define DMA_LIFCR_CHTIF1_Pos (10U)
5979 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
5980 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
5981 #define DMA_LIFCR_CTEIF1_Pos (9U)
5982 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
5983 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
5984 #define DMA_LIFCR_CDMEIF1_Pos (8U)
5985 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
5986 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
5987 #define DMA_LIFCR_CFEIF1_Pos (6U)
5988 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
5989 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
5990 #define DMA_LIFCR_CTCIF0_Pos (5U)
5991 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
5992 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
5993 #define DMA_LIFCR_CHTIF0_Pos (4U)
5994 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
5995 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
5996 #define DMA_LIFCR_CTEIF0_Pos (3U)
5997 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
5998 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
5999 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6000 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6001 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6002 #define DMA_LIFCR_CFEIF0_Pos (0U)
6003 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6004 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6005
6006 /******************** Bits definition for DMA_HIFCR register ****************/
6007 #define DMA_HIFCR_CTCIF7_Pos (27U)
6008 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6009 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6010 #define DMA_HIFCR_CHTIF7_Pos (26U)
6011 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6012 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6013 #define DMA_HIFCR_CTEIF7_Pos (25U)
6014 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6015 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6016 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6017 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6018 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6019 #define DMA_HIFCR_CFEIF7_Pos (22U)
6020 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6021 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6022 #define DMA_HIFCR_CTCIF6_Pos (21U)
6023 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6024 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6025 #define DMA_HIFCR_CHTIF6_Pos (20U)
6026 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6027 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6028 #define DMA_HIFCR_CTEIF6_Pos (19U)
6029 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6030 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6031 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6032 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6033 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6034 #define DMA_HIFCR_CFEIF6_Pos (16U)
6035 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6036 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6037 #define DMA_HIFCR_CTCIF5_Pos (11U)
6038 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6039 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6040 #define DMA_HIFCR_CHTIF5_Pos (10U)
6041 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6042 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6043 #define DMA_HIFCR_CTEIF5_Pos (9U)
6044 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6045 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6046 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6047 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6048 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6049 #define DMA_HIFCR_CFEIF5_Pos (6U)
6050 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6051 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6052 #define DMA_HIFCR_CTCIF4_Pos (5U)
6053 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6054 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6055 #define DMA_HIFCR_CHTIF4_Pos (4U)
6056 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6057 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6058 #define DMA_HIFCR_CTEIF4_Pos (3U)
6059 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6060 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6061 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6062 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6063 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6064 #define DMA_HIFCR_CFEIF4_Pos (0U)
6065 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6066 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6067
6068 /****************** Bit definition for DMA_SxPAR register ********************/
6069 #define DMA_SxPAR_PA_Pos (0U)
6070 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6071 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6072
6073 /****************** Bit definition for DMA_SxM0AR register ********************/
6074 #define DMA_SxM0AR_M0A_Pos (0U)
6075 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6076 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6077
6078 /****************** Bit definition for DMA_SxM1AR register ********************/
6079 #define DMA_SxM1AR_M1A_Pos (0U)
6080 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6081 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6082
6083
6084 /******************************************************************************/
6085 /* */
6086 /* External Interrupt/Event Controller */
6087 /* */
6088 /******************************************************************************/
6089 /******************* Bit definition for EXTI_IMR register *******************/
6090 #define EXTI_IMR_MR0_Pos (0U)
6091 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
6092 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
6093 #define EXTI_IMR_MR1_Pos (1U)
6094 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
6095 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
6096 #define EXTI_IMR_MR2_Pos (2U)
6097 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
6098 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
6099 #define EXTI_IMR_MR3_Pos (3U)
6100 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
6101 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
6102 #define EXTI_IMR_MR4_Pos (4U)
6103 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
6104 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
6105 #define EXTI_IMR_MR5_Pos (5U)
6106 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
6107 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
6108 #define EXTI_IMR_MR6_Pos (6U)
6109 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
6110 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
6111 #define EXTI_IMR_MR7_Pos (7U)
6112 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
6113 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
6114 #define EXTI_IMR_MR8_Pos (8U)
6115 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
6116 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
6117 #define EXTI_IMR_MR9_Pos (9U)
6118 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
6119 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
6120 #define EXTI_IMR_MR10_Pos (10U)
6121 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
6122 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
6123 #define EXTI_IMR_MR11_Pos (11U)
6124 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
6125 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
6126 #define EXTI_IMR_MR12_Pos (12U)
6127 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
6128 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
6129 #define EXTI_IMR_MR13_Pos (13U)
6130 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
6131 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
6132 #define EXTI_IMR_MR14_Pos (14U)
6133 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
6134 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
6135 #define EXTI_IMR_MR15_Pos (15U)
6136 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
6137 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
6138 #define EXTI_IMR_MR16_Pos (16U)
6139 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
6140 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
6141 #define EXTI_IMR_MR17_Pos (17U)
6142 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
6143 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
6144 #define EXTI_IMR_MR18_Pos (18U)
6145 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
6146 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
6147 #define EXTI_IMR_MR19_Pos (19U)
6148 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
6149 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
6150 #define EXTI_IMR_MR20_Pos (20U)
6151 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
6152 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
6153 #define EXTI_IMR_MR21_Pos (21U)
6154 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
6155 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
6156 #define EXTI_IMR_MR22_Pos (22U)
6157 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
6158 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
6159
6160 /* Reference Defines */
6161 #define EXTI_IMR_IM0 EXTI_IMR_MR0
6162 #define EXTI_IMR_IM1 EXTI_IMR_MR1
6163 #define EXTI_IMR_IM2 EXTI_IMR_MR2
6164 #define EXTI_IMR_IM3 EXTI_IMR_MR3
6165 #define EXTI_IMR_IM4 EXTI_IMR_MR4
6166 #define EXTI_IMR_IM5 EXTI_IMR_MR5
6167 #define EXTI_IMR_IM6 EXTI_IMR_MR6
6168 #define EXTI_IMR_IM7 EXTI_IMR_MR7
6169 #define EXTI_IMR_IM8 EXTI_IMR_MR8
6170 #define EXTI_IMR_IM9 EXTI_IMR_MR9
6171 #define EXTI_IMR_IM10 EXTI_IMR_MR10
6172 #define EXTI_IMR_IM11 EXTI_IMR_MR11
6173 #define EXTI_IMR_IM12 EXTI_IMR_MR12
6174 #define EXTI_IMR_IM13 EXTI_IMR_MR13
6175 #define EXTI_IMR_IM14 EXTI_IMR_MR14
6176 #define EXTI_IMR_IM15 EXTI_IMR_MR15
6177 #define EXTI_IMR_IM16 EXTI_IMR_MR16
6178 #define EXTI_IMR_IM17 EXTI_IMR_MR17
6179 #define EXTI_IMR_IM18 EXTI_IMR_MR18
6180 #define EXTI_IMR_IM19 EXTI_IMR_MR19
6181 #define EXTI_IMR_IM20 EXTI_IMR_MR20
6182 #define EXTI_IMR_IM21 EXTI_IMR_MR21
6183 #define EXTI_IMR_IM22 EXTI_IMR_MR22
6184 #define EXTI_IMR_IM_Pos (0U)
6185 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
6186 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
6187
6188 /******************* Bit definition for EXTI_EMR register *******************/
6189 #define EXTI_EMR_MR0_Pos (0U)
6190 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
6191 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
6192 #define EXTI_EMR_MR1_Pos (1U)
6193 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
6194 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
6195 #define EXTI_EMR_MR2_Pos (2U)
6196 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
6197 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
6198 #define EXTI_EMR_MR3_Pos (3U)
6199 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
6200 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
6201 #define EXTI_EMR_MR4_Pos (4U)
6202 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
6203 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
6204 #define EXTI_EMR_MR5_Pos (5U)
6205 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
6206 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
6207 #define EXTI_EMR_MR6_Pos (6U)
6208 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
6209 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
6210 #define EXTI_EMR_MR7_Pos (7U)
6211 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
6212 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
6213 #define EXTI_EMR_MR8_Pos (8U)
6214 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
6215 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
6216 #define EXTI_EMR_MR9_Pos (9U)
6217 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
6218 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
6219 #define EXTI_EMR_MR10_Pos (10U)
6220 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
6221 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
6222 #define EXTI_EMR_MR11_Pos (11U)
6223 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
6224 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
6225 #define EXTI_EMR_MR12_Pos (12U)
6226 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
6227 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
6228 #define EXTI_EMR_MR13_Pos (13U)
6229 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
6230 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
6231 #define EXTI_EMR_MR14_Pos (14U)
6232 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
6233 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
6234 #define EXTI_EMR_MR15_Pos (15U)
6235 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
6236 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
6237 #define EXTI_EMR_MR16_Pos (16U)
6238 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
6239 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
6240 #define EXTI_EMR_MR17_Pos (17U)
6241 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
6242 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
6243 #define EXTI_EMR_MR18_Pos (18U)
6244 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
6245 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
6246 #define EXTI_EMR_MR19_Pos (19U)
6247 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
6248 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
6249 #define EXTI_EMR_MR20_Pos (20U)
6250 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
6251 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
6252 #define EXTI_EMR_MR21_Pos (21U)
6253 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
6254 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
6255 #define EXTI_EMR_MR22_Pos (22U)
6256 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
6257 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
6258
6259 /* Reference Defines */
6260 #define EXTI_EMR_EM0 EXTI_EMR_MR0
6261 #define EXTI_EMR_EM1 EXTI_EMR_MR1
6262 #define EXTI_EMR_EM2 EXTI_EMR_MR2
6263 #define EXTI_EMR_EM3 EXTI_EMR_MR3
6264 #define EXTI_EMR_EM4 EXTI_EMR_MR4
6265 #define EXTI_EMR_EM5 EXTI_EMR_MR5
6266 #define EXTI_EMR_EM6 EXTI_EMR_MR6
6267 #define EXTI_EMR_EM7 EXTI_EMR_MR7
6268 #define EXTI_EMR_EM8 EXTI_EMR_MR8
6269 #define EXTI_EMR_EM9 EXTI_EMR_MR9
6270 #define EXTI_EMR_EM10 EXTI_EMR_MR10
6271 #define EXTI_EMR_EM11 EXTI_EMR_MR11
6272 #define EXTI_EMR_EM12 EXTI_EMR_MR12
6273 #define EXTI_EMR_EM13 EXTI_EMR_MR13
6274 #define EXTI_EMR_EM14 EXTI_EMR_MR14
6275 #define EXTI_EMR_EM15 EXTI_EMR_MR15
6276 #define EXTI_EMR_EM16 EXTI_EMR_MR16
6277 #define EXTI_EMR_EM17 EXTI_EMR_MR17
6278 #define EXTI_EMR_EM18 EXTI_EMR_MR18
6279 #define EXTI_EMR_EM19 EXTI_EMR_MR19
6280 #define EXTI_EMR_EM20 EXTI_EMR_MR20
6281 #define EXTI_EMR_EM21 EXTI_EMR_MR21
6282 #define EXTI_EMR_EM22 EXTI_EMR_MR22
6283
6284 /****************** Bit definition for EXTI_RTSR register *******************/
6285 #define EXTI_RTSR_TR0_Pos (0U)
6286 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
6287 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
6288 #define EXTI_RTSR_TR1_Pos (1U)
6289 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
6290 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
6291 #define EXTI_RTSR_TR2_Pos (2U)
6292 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
6293 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
6294 #define EXTI_RTSR_TR3_Pos (3U)
6295 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
6296 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
6297 #define EXTI_RTSR_TR4_Pos (4U)
6298 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
6299 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
6300 #define EXTI_RTSR_TR5_Pos (5U)
6301 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
6302 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
6303 #define EXTI_RTSR_TR6_Pos (6U)
6304 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
6305 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
6306 #define EXTI_RTSR_TR7_Pos (7U)
6307 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
6308 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
6309 #define EXTI_RTSR_TR8_Pos (8U)
6310 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
6311 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
6312 #define EXTI_RTSR_TR9_Pos (9U)
6313 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
6314 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
6315 #define EXTI_RTSR_TR10_Pos (10U)
6316 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
6317 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
6318 #define EXTI_RTSR_TR11_Pos (11U)
6319 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
6320 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
6321 #define EXTI_RTSR_TR12_Pos (12U)
6322 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
6323 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
6324 #define EXTI_RTSR_TR13_Pos (13U)
6325 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
6326 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
6327 #define EXTI_RTSR_TR14_Pos (14U)
6328 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
6329 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
6330 #define EXTI_RTSR_TR15_Pos (15U)
6331 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
6332 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
6333 #define EXTI_RTSR_TR16_Pos (16U)
6334 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
6335 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
6336 #define EXTI_RTSR_TR17_Pos (17U)
6337 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
6338 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
6339 #define EXTI_RTSR_TR18_Pos (18U)
6340 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
6341 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
6342 #define EXTI_RTSR_TR19_Pos (19U)
6343 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
6344 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
6345 #define EXTI_RTSR_TR20_Pos (20U)
6346 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
6347 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
6348 #define EXTI_RTSR_TR21_Pos (21U)
6349 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
6350 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
6351 #define EXTI_RTSR_TR22_Pos (22U)
6352 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
6353 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
6354
6355 /****************** Bit definition for EXTI_FTSR register *******************/
6356 #define EXTI_FTSR_TR0_Pos (0U)
6357 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
6358 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
6359 #define EXTI_FTSR_TR1_Pos (1U)
6360 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
6361 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
6362 #define EXTI_FTSR_TR2_Pos (2U)
6363 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
6364 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
6365 #define EXTI_FTSR_TR3_Pos (3U)
6366 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
6367 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
6368 #define EXTI_FTSR_TR4_Pos (4U)
6369 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
6370 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
6371 #define EXTI_FTSR_TR5_Pos (5U)
6372 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
6373 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
6374 #define EXTI_FTSR_TR6_Pos (6U)
6375 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
6376 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
6377 #define EXTI_FTSR_TR7_Pos (7U)
6378 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
6379 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
6380 #define EXTI_FTSR_TR8_Pos (8U)
6381 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
6382 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
6383 #define EXTI_FTSR_TR9_Pos (9U)
6384 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
6385 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
6386 #define EXTI_FTSR_TR10_Pos (10U)
6387 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
6388 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
6389 #define EXTI_FTSR_TR11_Pos (11U)
6390 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
6391 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
6392 #define EXTI_FTSR_TR12_Pos (12U)
6393 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
6394 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
6395 #define EXTI_FTSR_TR13_Pos (13U)
6396 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
6397 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
6398 #define EXTI_FTSR_TR14_Pos (14U)
6399 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
6400 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
6401 #define EXTI_FTSR_TR15_Pos (15U)
6402 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
6403 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
6404 #define EXTI_FTSR_TR16_Pos (16U)
6405 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
6406 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
6407 #define EXTI_FTSR_TR17_Pos (17U)
6408 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
6409 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
6410 #define EXTI_FTSR_TR18_Pos (18U)
6411 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
6412 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
6413 #define EXTI_FTSR_TR19_Pos (19U)
6414 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
6415 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
6416 #define EXTI_FTSR_TR20_Pos (20U)
6417 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
6418 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
6419 #define EXTI_FTSR_TR21_Pos (21U)
6420 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
6421 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
6422 #define EXTI_FTSR_TR22_Pos (22U)
6423 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
6424 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
6425
6426 /****************** Bit definition for EXTI_SWIER register ******************/
6427 #define EXTI_SWIER_SWIER0_Pos (0U)
6428 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
6429 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
6430 #define EXTI_SWIER_SWIER1_Pos (1U)
6431 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
6432 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
6433 #define EXTI_SWIER_SWIER2_Pos (2U)
6434 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
6435 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
6436 #define EXTI_SWIER_SWIER3_Pos (3U)
6437 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
6438 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
6439 #define EXTI_SWIER_SWIER4_Pos (4U)
6440 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
6441 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
6442 #define EXTI_SWIER_SWIER5_Pos (5U)
6443 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
6444 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
6445 #define EXTI_SWIER_SWIER6_Pos (6U)
6446 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
6447 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
6448 #define EXTI_SWIER_SWIER7_Pos (7U)
6449 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
6450 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
6451 #define EXTI_SWIER_SWIER8_Pos (8U)
6452 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
6453 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
6454 #define EXTI_SWIER_SWIER9_Pos (9U)
6455 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
6456 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
6457 #define EXTI_SWIER_SWIER10_Pos (10U)
6458 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
6459 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
6460 #define EXTI_SWIER_SWIER11_Pos (11U)
6461 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
6462 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
6463 #define EXTI_SWIER_SWIER12_Pos (12U)
6464 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
6465 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
6466 #define EXTI_SWIER_SWIER13_Pos (13U)
6467 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
6468 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
6469 #define EXTI_SWIER_SWIER14_Pos (14U)
6470 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
6471 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
6472 #define EXTI_SWIER_SWIER15_Pos (15U)
6473 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
6474 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
6475 #define EXTI_SWIER_SWIER16_Pos (16U)
6476 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
6477 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
6478 #define EXTI_SWIER_SWIER17_Pos (17U)
6479 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
6480 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
6481 #define EXTI_SWIER_SWIER18_Pos (18U)
6482 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
6483 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
6484 #define EXTI_SWIER_SWIER19_Pos (19U)
6485 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
6486 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
6487 #define EXTI_SWIER_SWIER20_Pos (20U)
6488 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
6489 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
6490 #define EXTI_SWIER_SWIER21_Pos (21U)
6491 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
6492 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
6493 #define EXTI_SWIER_SWIER22_Pos (22U)
6494 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
6495 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
6496
6497 /******************* Bit definition for EXTI_PR register ********************/
6498 #define EXTI_PR_PR0_Pos (0U)
6499 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
6500 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
6501 #define EXTI_PR_PR1_Pos (1U)
6502 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
6503 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
6504 #define EXTI_PR_PR2_Pos (2U)
6505 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
6506 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
6507 #define EXTI_PR_PR3_Pos (3U)
6508 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
6509 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
6510 #define EXTI_PR_PR4_Pos (4U)
6511 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
6512 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
6513 #define EXTI_PR_PR5_Pos (5U)
6514 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
6515 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
6516 #define EXTI_PR_PR6_Pos (6U)
6517 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
6518 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
6519 #define EXTI_PR_PR7_Pos (7U)
6520 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
6521 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
6522 #define EXTI_PR_PR8_Pos (8U)
6523 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
6524 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
6525 #define EXTI_PR_PR9_Pos (9U)
6526 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
6527 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
6528 #define EXTI_PR_PR10_Pos (10U)
6529 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
6530 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
6531 #define EXTI_PR_PR11_Pos (11U)
6532 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
6533 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
6534 #define EXTI_PR_PR12_Pos (12U)
6535 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
6536 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
6537 #define EXTI_PR_PR13_Pos (13U)
6538 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
6539 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
6540 #define EXTI_PR_PR14_Pos (14U)
6541 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
6542 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
6543 #define EXTI_PR_PR15_Pos (15U)
6544 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
6545 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
6546 #define EXTI_PR_PR16_Pos (16U)
6547 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
6548 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
6549 #define EXTI_PR_PR17_Pos (17U)
6550 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
6551 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
6552 #define EXTI_PR_PR18_Pos (18U)
6553 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
6554 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
6555 #define EXTI_PR_PR19_Pos (19U)
6556 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
6557 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
6558 #define EXTI_PR_PR20_Pos (20U)
6559 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
6560 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
6561 #define EXTI_PR_PR21_Pos (21U)
6562 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
6563 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
6564 #define EXTI_PR_PR22_Pos (22U)
6565 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
6566 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
6567
6568 /******************************************************************************/
6569 /* */
6570 /* FLASH */
6571 /* */
6572 /******************************************************************************/
6573 /******************* Bits definition for FLASH_ACR register *****************/
6574 #define FLASH_ACR_LATENCY_Pos (0U)
6575 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
6576 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6577 #define FLASH_ACR_LATENCY_0WS 0x00000000U
6578 #define FLASH_ACR_LATENCY_1WS 0x00000001U
6579 #define FLASH_ACR_LATENCY_2WS 0x00000002U
6580 #define FLASH_ACR_LATENCY_3WS 0x00000003U
6581 #define FLASH_ACR_LATENCY_4WS 0x00000004U
6582 #define FLASH_ACR_LATENCY_5WS 0x00000005U
6583 #define FLASH_ACR_LATENCY_6WS 0x00000006U
6584 #define FLASH_ACR_LATENCY_7WS 0x00000007U
6585
6586 #define FLASH_ACR_PRFTEN_Pos (8U)
6587 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
6588 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6589 #define FLASH_ACR_ICEN_Pos (9U)
6590 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
6591 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6592 #define FLASH_ACR_DCEN_Pos (10U)
6593 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
6594 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6595 #define FLASH_ACR_ICRST_Pos (11U)
6596 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
6597 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6598 #define FLASH_ACR_DCRST_Pos (12U)
6599 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
6600 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6601 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6602 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
6603 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6604 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6605 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
6606 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6607
6608 /******************* Bits definition for FLASH_SR register ******************/
6609 #define FLASH_SR_EOP_Pos (0U)
6610 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
6611 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
6612 #define FLASH_SR_SOP_Pos (1U)
6613 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
6614 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
6615 #define FLASH_SR_WRPERR_Pos (4U)
6616 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
6617 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6618 #define FLASH_SR_PGAERR_Pos (5U)
6619 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
6620 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6621 #define FLASH_SR_PGPERR_Pos (6U)
6622 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
6623 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6624 #define FLASH_SR_PGSERR_Pos (7U)
6625 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
6626 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6627 #define FLASH_SR_BSY_Pos (16U)
6628 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
6629 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
6630
6631 /******************* Bits definition for FLASH_CR register ******************/
6632 #define FLASH_CR_PG_Pos (0U)
6633 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
6634 #define FLASH_CR_PG FLASH_CR_PG_Msk
6635 #define FLASH_CR_SER_Pos (1U)
6636 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
6637 #define FLASH_CR_SER FLASH_CR_SER_Msk
6638 #define FLASH_CR_MER_Pos (2U)
6639 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
6640 #define FLASH_CR_MER FLASH_CR_MER_Msk
6641 #define FLASH_CR_SNB_Pos (3U)
6642 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
6643 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
6644 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
6645 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
6646 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
6647 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
6648 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
6649 #define FLASH_CR_PSIZE_Pos (8U)
6650 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
6651 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6652 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
6653 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
6654 #define FLASH_CR_STRT_Pos (16U)
6655 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
6656 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
6657 #define FLASH_CR_EOPIE_Pos (24U)
6658 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
6659 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6660 #define FLASH_CR_LOCK_Pos (31U)
6661 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
6662 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6663
6664 /******************* Bits definition for FLASH_OPTCR register ***************/
6665 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
6666 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
6667 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6668 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
6669 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
6670 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6671
6672 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6673 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6674 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
6675 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
6676 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6677 #define FLASH_OPTCR_WDG_SW_Pos (5U)
6678 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
6679 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6680 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
6681 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
6682 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6683 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6684 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
6685 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6686 #define FLASH_OPTCR_RDP_Pos (8U)
6687 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
6688 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6689 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
6690 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
6691 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
6692 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
6693 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
6694 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
6695 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
6696 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
6697 #define FLASH_OPTCR_nWRP_Pos (16U)
6698 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
6699 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6700 #define FLASH_OPTCR_nWRP_0 0x00010000U
6701 #define FLASH_OPTCR_nWRP_1 0x00020000U
6702 #define FLASH_OPTCR_nWRP_2 0x00040000U
6703 #define FLASH_OPTCR_nWRP_3 0x00080000U
6704 #define FLASH_OPTCR_nWRP_4 0x00100000U
6705 #define FLASH_OPTCR_nWRP_5 0x00200000U
6706 #define FLASH_OPTCR_nWRP_6 0x00400000U
6707 #define FLASH_OPTCR_nWRP_7 0x00800000U
6708 #define FLASH_OPTCR_nWRP_8 0x01000000U
6709 #define FLASH_OPTCR_nWRP_9 0x02000000U
6710 #define FLASH_OPTCR_nWRP_10 0x04000000U
6711 #define FLASH_OPTCR_nWRP_11 0x08000000U
6712
6713 /****************** Bits definition for FLASH_OPTCR1 register ***************/
6714 #define FLASH_OPTCR1_nWRP_Pos (16U)
6715 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
6716 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
6717 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
6718 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
6719 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
6720 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
6721 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
6722 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
6723 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
6724 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
6725 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
6726 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
6727 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
6728 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
6729
6730 /******************************************************************************/
6731 /* */
6732 /* Flexible Static Memory Controller */
6733 /* */
6734 /******************************************************************************/
6735 /****************** Bit definition for FSMC_BCR1 register *******************/
6736 #define FSMC_BCR1_MBKEN_Pos (0U)
6737 #define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
6738 #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
6739 #define FSMC_BCR1_MUXEN_Pos (1U)
6740 #define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
6741 #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6742
6743 #define FSMC_BCR1_MTYP_Pos (2U)
6744 #define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
6745 #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6746 #define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
6747 #define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
6748
6749 #define FSMC_BCR1_MWID_Pos (4U)
6750 #define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
6751 #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6752 #define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
6753 #define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
6754
6755 #define FSMC_BCR1_FACCEN_Pos (6U)
6756 #define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
6757 #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
6758 #define FSMC_BCR1_BURSTEN_Pos (8U)
6759 #define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
6760 #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
6761 #define FSMC_BCR1_WAITPOL_Pos (9U)
6762 #define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
6763 #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
6764 #define FSMC_BCR1_WRAPMOD_Pos (10U)
6765 #define FSMC_BCR1_WRAPMOD_Msk (0x1U << FSMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
6766 #define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
6767 #define FSMC_BCR1_WAITCFG_Pos (11U)
6768 #define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
6769 #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
6770 #define FSMC_BCR1_WREN_Pos (12U)
6771 #define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
6772 #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
6773 #define FSMC_BCR1_WAITEN_Pos (13U)
6774 #define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
6775 #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
6776 #define FSMC_BCR1_EXTMOD_Pos (14U)
6777 #define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
6778 #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
6779 #define FSMC_BCR1_ASYNCWAIT_Pos (15U)
6780 #define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
6781 #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
6782 #define FSMC_BCR1_CPSIZE_Pos (16U)
6783 #define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
6784 #define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
6785 #define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
6786 #define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
6787 #define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
6788 #define FSMC_BCR1_CBURSTRW_Pos (19U)
6789 #define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
6790 #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
6791
6792 /****************** Bit definition for FSMC_BCR2 register *******************/
6793 #define FSMC_BCR2_MBKEN_Pos (0U)
6794 #define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
6795 #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
6796 #define FSMC_BCR2_MUXEN_Pos (1U)
6797 #define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
6798 #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6799
6800 #define FSMC_BCR2_MTYP_Pos (2U)
6801 #define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6802 #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6803 #define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6804 #define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
6805
6806 #define FSMC_BCR2_MWID_Pos (4U)
6807 #define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6808 #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6809 #define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6810 #define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
6811
6812 #define FSMC_BCR2_FACCEN_Pos (6U)
6813 #define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
6814 #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
6815 #define FSMC_BCR2_BURSTEN_Pos (8U)
6816 #define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
6817 #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
6818 #define FSMC_BCR2_WAITPOL_Pos (9U)
6819 #define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
6820 #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
6821 #define FSMC_BCR2_WRAPMOD_Pos (10U)
6822 #define FSMC_BCR2_WRAPMOD_Msk (0x1U << FSMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
6823 #define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
6824 #define FSMC_BCR2_WAITCFG_Pos (11U)
6825 #define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
6826 #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
6827 #define FSMC_BCR2_WREN_Pos (12U)
6828 #define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
6829 #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
6830 #define FSMC_BCR2_WAITEN_Pos (13U)
6831 #define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
6832 #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
6833 #define FSMC_BCR2_EXTMOD_Pos (14U)
6834 #define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
6835 #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
6836 #define FSMC_BCR2_ASYNCWAIT_Pos (15U)
6837 #define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
6838 #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
6839 #define FSMC_BCR2_CPSIZE_Pos (16U)
6840 #define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
6841 #define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
6842 #define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
6843 #define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
6844 #define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
6845 #define FSMC_BCR2_CBURSTRW_Pos (19U)
6846 #define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
6847 #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
6848
6849 /****************** Bit definition for FSMC_BCR3 register *******************/
6850 #define FSMC_BCR3_MBKEN_Pos (0U)
6851 #define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
6852 #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
6853 #define FSMC_BCR3_MUXEN_Pos (1U)
6854 #define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
6855 #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6856
6857 #define FSMC_BCR3_MTYP_Pos (2U)
6858 #define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6859 #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6860 #define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6861 #define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
6862
6863 #define FSMC_BCR3_MWID_Pos (4U)
6864 #define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
6865 #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6866 #define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
6867 #define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
6868
6869 #define FSMC_BCR3_FACCEN_Pos (6U)
6870 #define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
6871 #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
6872 #define FSMC_BCR3_BURSTEN_Pos (8U)
6873 #define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
6874 #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
6875 #define FSMC_BCR3_WAITPOL_Pos (9U)
6876 #define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
6877 #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
6878 #define FSMC_BCR3_WRAPMOD_Pos (10U)
6879 #define FSMC_BCR3_WRAPMOD_Msk (0x1U << FSMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
6880 #define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
6881 #define FSMC_BCR3_WAITCFG_Pos (11U)
6882 #define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
6883 #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
6884 #define FSMC_BCR3_WREN_Pos (12U)
6885 #define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
6886 #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
6887 #define FSMC_BCR3_WAITEN_Pos (13U)
6888 #define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
6889 #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
6890 #define FSMC_BCR3_EXTMOD_Pos (14U)
6891 #define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
6892 #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
6893 #define FSMC_BCR3_ASYNCWAIT_Pos (15U)
6894 #define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
6895 #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
6896 #define FSMC_BCR3_CPSIZE_Pos (16U)
6897 #define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
6898 #define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
6899 #define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
6900 #define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
6901 #define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
6902 #define FSMC_BCR3_CBURSTRW_Pos (19U)
6903 #define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
6904 #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
6905
6906 /****************** Bit definition for FSMC_BCR4 register *******************/
6907 #define FSMC_BCR4_MBKEN_Pos (0U)
6908 #define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
6909 #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
6910 #define FSMC_BCR4_MUXEN_Pos (1U)
6911 #define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
6912 #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6913
6914 #define FSMC_BCR4_MTYP_Pos (2U)
6915 #define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
6916 #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6917 #define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
6918 #define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
6919
6920 #define FSMC_BCR4_MWID_Pos (4U)
6921 #define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
6922 #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6923 #define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
6924 #define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
6925
6926 #define FSMC_BCR4_FACCEN_Pos (6U)
6927 #define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
6928 #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
6929 #define FSMC_BCR4_BURSTEN_Pos (8U)
6930 #define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
6931 #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
6932 #define FSMC_BCR4_WAITPOL_Pos (9U)
6933 #define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
6934 #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
6935 #define FSMC_BCR4_WRAPMOD_Pos (10U)
6936 #define FSMC_BCR4_WRAPMOD_Msk (0x1U << FSMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
6937 #define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
6938 #define FSMC_BCR4_WAITCFG_Pos (11U)
6939 #define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
6940 #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
6941 #define FSMC_BCR4_WREN_Pos (12U)
6942 #define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
6943 #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
6944 #define FSMC_BCR4_WAITEN_Pos (13U)
6945 #define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
6946 #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
6947 #define FSMC_BCR4_EXTMOD_Pos (14U)
6948 #define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
6949 #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
6950 #define FSMC_BCR4_ASYNCWAIT_Pos (15U)
6951 #define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
6952 #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
6953 #define FSMC_BCR4_CPSIZE_Pos (16U)
6954 #define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
6955 #define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
6956 #define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
6957 #define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
6958 #define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
6959 #define FSMC_BCR4_CBURSTRW_Pos (19U)
6960 #define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
6961 #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
6962
6963 /****************** Bit definition for FSMC_BTR1 register ******************/
6964 #define FSMC_BTR1_ADDSET_Pos (0U)
6965 #define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
6966 #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
6967 #define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
6968 #define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
6969 #define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
6970 #define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
6971
6972 #define FSMC_BTR1_ADDHLD_Pos (4U)
6973 #define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
6974 #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
6975 #define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
6976 #define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
6977 #define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
6978 #define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
6979
6980 #define FSMC_BTR1_DATAST_Pos (8U)
6981 #define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
6982 #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
6983 #define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
6984 #define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
6985 #define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
6986 #define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
6987 #define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
6988 #define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
6989 #define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
6990 #define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
6991
6992 #define FSMC_BTR1_BUSTURN_Pos (16U)
6993 #define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
6994 #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
6995 #define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
6996 #define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
6997 #define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
6998 #define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
6999
7000 #define FSMC_BTR1_CLKDIV_Pos (20U)
7001 #define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
7002 #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7003 #define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
7004 #define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
7005 #define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
7006 #define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
7007
7008 #define FSMC_BTR1_DATLAT_Pos (24U)
7009 #define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
7010 #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7011 #define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
7012 #define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
7013 #define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
7014 #define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
7015
7016 #define FSMC_BTR1_ACCMOD_Pos (28U)
7017 #define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
7018 #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7019 #define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
7020 #define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
7021
7022 /****************** Bit definition for FSMC_BTR2 register *******************/
7023 #define FSMC_BTR2_ADDSET_Pos (0U)
7024 #define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
7025 #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7026 #define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
7027 #define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
7028 #define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
7029 #define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
7030
7031 #define FSMC_BTR2_ADDHLD_Pos (4U)
7032 #define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7033 #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7034 #define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
7035 #define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
7036 #define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
7037 #define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7038
7039 #define FSMC_BTR2_DATAST_Pos (8U)
7040 #define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
7041 #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7042 #define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
7043 #define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
7044 #define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
7045 #define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
7046 #define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
7047 #define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
7048 #define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
7049 #define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
7050
7051 #define FSMC_BTR2_BUSTURN_Pos (16U)
7052 #define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7053 #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7054 #define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
7055 #define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
7056 #define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
7057 #define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
7058
7059 #define FSMC_BTR2_CLKDIV_Pos (20U)
7060 #define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
7061 #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7062 #define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
7063 #define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
7064 #define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
7065 #define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
7066
7067 #define FSMC_BTR2_DATLAT_Pos (24U)
7068 #define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
7069 #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7070 #define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
7071 #define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
7072 #define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
7073 #define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
7074
7075 #define FSMC_BTR2_ACCMOD_Pos (28U)
7076 #define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
7077 #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7078 #define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
7079 #define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
7080
7081 /******************* Bit definition for FSMC_BTR3 register *******************/
7082 #define FSMC_BTR3_ADDSET_Pos (0U)
7083 #define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7084 #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7085 #define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7086 #define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7087 #define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7088 #define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7089
7090 #define FSMC_BTR3_ADDHLD_Pos (4U)
7091 #define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7092 #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7093 #define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7094 #define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7095 #define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7096 #define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
7097
7098 #define FSMC_BTR3_DATAST_Pos (8U)
7099 #define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
7100 #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7101 #define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
7102 #define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
7103 #define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
7104 #define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
7105 #define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
7106 #define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
7107 #define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
7108 #define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
7109
7110 #define FSMC_BTR3_BUSTURN_Pos (16U)
7111 #define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7112 #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7113 #define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
7114 #define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
7115 #define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
7116 #define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
7117
7118 #define FSMC_BTR3_CLKDIV_Pos (20U)
7119 #define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
7120 #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7121 #define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
7122 #define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
7123 #define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
7124 #define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
7125
7126 #define FSMC_BTR3_DATLAT_Pos (24U)
7127 #define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
7128 #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7129 #define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
7130 #define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
7131 #define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
7132 #define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
7133
7134 #define FSMC_BTR3_ACCMOD_Pos (28U)
7135 #define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
7136 #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7137 #define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
7138 #define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
7139
7140 /****************** Bit definition for FSMC_BTR4 register *******************/
7141 #define FSMC_BTR4_ADDSET_Pos (0U)
7142 #define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
7143 #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7144 #define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
7145 #define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
7146 #define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
7147 #define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7148
7149 #define FSMC_BTR4_ADDHLD_Pos (4U)
7150 #define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7151 #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7152 #define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
7153 #define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
7154 #define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
7155 #define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
7156
7157 #define FSMC_BTR4_DATAST_Pos (8U)
7158 #define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
7159 #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7160 #define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
7161 #define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
7162 #define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
7163 #define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
7164 #define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
7165 #define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
7166 #define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
7167 #define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
7168
7169 #define FSMC_BTR4_BUSTURN_Pos (16U)
7170 #define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7171 #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7172 #define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
7173 #define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
7174 #define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
7175 #define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
7176
7177 #define FSMC_BTR4_CLKDIV_Pos (20U)
7178 #define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
7179 #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7180 #define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
7181 #define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
7182 #define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
7183 #define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
7184
7185 #define FSMC_BTR4_DATLAT_Pos (24U)
7186 #define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
7187 #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7188 #define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
7189 #define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
7190 #define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
7191 #define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
7192
7193 #define FSMC_BTR4_ACCMOD_Pos (28U)
7194 #define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
7195 #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7196 #define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
7197 #define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
7198
7199 /****************** Bit definition for FSMC_BWTR1 register ******************/
7200 #define FSMC_BWTR1_ADDSET_Pos (0U)
7201 #define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
7202 #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7203 #define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
7204 #define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
7205 #define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
7206 #define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
7207
7208 #define FSMC_BWTR1_ADDHLD_Pos (4U)
7209 #define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7210 #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7211 #define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
7212 #define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
7213 #define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
7214 #define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
7215
7216 #define FSMC_BWTR1_DATAST_Pos (8U)
7217 #define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
7218 #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7219 #define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
7220 #define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
7221 #define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
7222 #define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
7223 #define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
7224 #define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
7225 #define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
7226 #define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
7227
7228 #define FSMC_BWTR1_BUSTURN_Pos (16U)
7229 #define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7230 #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7231 #define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
7232 #define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
7233 #define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
7234 #define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
7235
7236 #define FSMC_BWTR1_ACCMOD_Pos (28U)
7237 #define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
7238 #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7239 #define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
7240 #define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
7241
7242 /****************** Bit definition for FSMC_BWTR2 register ******************/
7243 #define FSMC_BWTR2_ADDSET_Pos (0U)
7244 #define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7245 #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7246 #define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7247 #define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7248 #define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7249 #define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7250
7251 #define FSMC_BWTR2_ADDHLD_Pos (4U)
7252 #define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7253 #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7254 #define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
7255 #define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
7256 #define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
7257 #define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
7258
7259 #define FSMC_BWTR2_DATAST_Pos (8U)
7260 #define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
7261 #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7262 #define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
7263 #define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
7264 #define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
7265 #define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
7266 #define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
7267 #define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
7268 #define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
7269 #define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
7270
7271 #define FSMC_BWTR2_BUSTURN_Pos (16U)
7272 #define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7273 #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7274 #define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
7275 #define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
7276 #define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
7277 #define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
7278
7279 #define FSMC_BWTR2_ACCMOD_Pos (28U)
7280 #define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
7281 #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7282 #define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
7283 #define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
7284
7285 /****************** Bit definition for FSMC_BWTR3 register ******************/
7286 #define FSMC_BWTR3_ADDSET_Pos (0U)
7287 #define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
7288 #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7289 #define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
7290 #define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
7291 #define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
7292 #define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7293
7294 #define FSMC_BWTR3_ADDHLD_Pos (4U)
7295 #define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7296 #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7297 #define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
7298 #define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
7299 #define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
7300 #define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
7301
7302 #define FSMC_BWTR3_DATAST_Pos (8U)
7303 #define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
7304 #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7305 #define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
7306 #define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
7307 #define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
7308 #define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
7309 #define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
7310 #define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
7311 #define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
7312 #define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
7313
7314 #define FSMC_BWTR3_BUSTURN_Pos (16U)
7315 #define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7316 #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7317 #define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
7318 #define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
7319 #define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
7320 #define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
7321
7322 #define FSMC_BWTR3_ACCMOD_Pos (28U)
7323 #define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
7324 #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7325 #define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
7326 #define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
7327
7328 /****************** Bit definition for FSMC_BWTR4 register ******************/
7329 #define FSMC_BWTR4_ADDSET_Pos (0U)
7330 #define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
7331 #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7332 #define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
7333 #define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
7334 #define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
7335 #define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
7336
7337 #define FSMC_BWTR4_ADDHLD_Pos (4U)
7338 #define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7339 #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7340 #define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
7341 #define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
7342 #define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
7343 #define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
7344
7345 #define FSMC_BWTR4_DATAST_Pos (8U)
7346 #define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
7347 #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7348 #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
7349 #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
7350 #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
7351 #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
7352 #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
7353 #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
7354 #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
7355 #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
7356
7357 #define FSMC_BWTR4_BUSTURN_Pos (16U)
7358 #define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7359 #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7360 #define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
7361 #define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
7362 #define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
7363 #define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
7364
7365 #define FSMC_BWTR4_ACCMOD_Pos (28U)
7366 #define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
7367 #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7368 #define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
7369 #define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
7370
7371 /****************** Bit definition for FSMC_PCR2 register *******************/
7372 #define FSMC_PCR2_PWAITEN_Pos (1U)
7373 #define FSMC_PCR2_PWAITEN_Msk (0x1U << FSMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
7374 #define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
7375 #define FSMC_PCR2_PBKEN_Pos (2U)
7376 #define FSMC_PCR2_PBKEN_Msk (0x1U << FSMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
7377 #define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7378 #define FSMC_PCR2_PTYP_Pos (3U)
7379 #define FSMC_PCR2_PTYP_Msk (0x1U << FSMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
7380 #define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk /*!<Memory type */
7381
7382 #define FSMC_PCR2_PWID_Pos (4U)
7383 #define FSMC_PCR2_PWID_Msk (0x3U << FSMC_PCR2_PWID_Pos) /*!< 0x00000030 */
7384 #define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7385 #define FSMC_PCR2_PWID_0 (0x1U << FSMC_PCR2_PWID_Pos) /*!< 0x00000010 */
7386 #define FSMC_PCR2_PWID_1 (0x2U << FSMC_PCR2_PWID_Pos) /*!< 0x00000020 */
7387
7388 #define FSMC_PCR2_ECCEN_Pos (6U)
7389 #define FSMC_PCR2_ECCEN_Msk (0x1U << FSMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
7390 #define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
7391
7392 #define FSMC_PCR2_TCLR_Pos (9U)
7393 #define FSMC_PCR2_TCLR_Msk (0xFU << FSMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
7394 #define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7395 #define FSMC_PCR2_TCLR_0 (0x1U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
7396 #define FSMC_PCR2_TCLR_1 (0x2U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
7397 #define FSMC_PCR2_TCLR_2 (0x4U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
7398 #define FSMC_PCR2_TCLR_3 (0x8U << FSMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
7399
7400 #define FSMC_PCR2_TAR_Pos (13U)
7401 #define FSMC_PCR2_TAR_Msk (0xFU << FSMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
7402 #define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7403 #define FSMC_PCR2_TAR_0 (0x1U << FSMC_PCR2_TAR_Pos) /*!< 0x00002000 */
7404 #define FSMC_PCR2_TAR_1 (0x2U << FSMC_PCR2_TAR_Pos) /*!< 0x00004000 */
7405 #define FSMC_PCR2_TAR_2 (0x4U << FSMC_PCR2_TAR_Pos) /*!< 0x00008000 */
7406 #define FSMC_PCR2_TAR_3 (0x8U << FSMC_PCR2_TAR_Pos) /*!< 0x00010000 */
7407
7408 #define FSMC_PCR2_ECCPS_Pos (17U)
7409 #define FSMC_PCR2_ECCPS_Msk (0x7U << FSMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
7410 #define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
7411 #define FSMC_PCR2_ECCPS_0 (0x1U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
7412 #define FSMC_PCR2_ECCPS_1 (0x2U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
7413 #define FSMC_PCR2_ECCPS_2 (0x4U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
7414
7415 /****************** Bit definition for FSMC_PCR3 register *******************/
7416 #define FSMC_PCR3_PWAITEN_Pos (1U)
7417 #define FSMC_PCR3_PWAITEN_Msk (0x1U << FSMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
7418 #define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
7419 #define FSMC_PCR3_PBKEN_Pos (2U)
7420 #define FSMC_PCR3_PBKEN_Msk (0x1U << FSMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
7421 #define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7422 #define FSMC_PCR3_PTYP_Pos (3U)
7423 #define FSMC_PCR3_PTYP_Msk (0x1U << FSMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
7424 #define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk /*!<Memory type */
7425
7426 #define FSMC_PCR3_PWID_Pos (4U)
7427 #define FSMC_PCR3_PWID_Msk (0x3U << FSMC_PCR3_PWID_Pos) /*!< 0x00000030 */
7428 #define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7429 #define FSMC_PCR3_PWID_0 (0x1U << FSMC_PCR3_PWID_Pos) /*!< 0x00000010 */
7430 #define FSMC_PCR3_PWID_1 (0x2U << FSMC_PCR3_PWID_Pos) /*!< 0x00000020 */
7431
7432 #define FSMC_PCR3_ECCEN_Pos (6U)
7433 #define FSMC_PCR3_ECCEN_Msk (0x1U << FSMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
7434 #define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
7435
7436 #define FSMC_PCR3_TCLR_Pos (9U)
7437 #define FSMC_PCR3_TCLR_Msk (0xFU << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7438 #define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7439 #define FSMC_PCR3_TCLR_0 (0x1U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7440 #define FSMC_PCR3_TCLR_1 (0x2U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7441 #define FSMC_PCR3_TCLR_2 (0x4U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7442 #define FSMC_PCR3_TCLR_3 (0x8U << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
7443
7444 #define FSMC_PCR3_TAR_Pos (13U)
7445 #define FSMC_PCR3_TAR_Msk (0xFU << FSMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
7446 #define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7447 #define FSMC_PCR3_TAR_0 (0x1U << FSMC_PCR3_TAR_Pos) /*!< 0x00002000 */
7448 #define FSMC_PCR3_TAR_1 (0x2U << FSMC_PCR3_TAR_Pos) /*!< 0x00004000 */
7449 #define FSMC_PCR3_TAR_2 (0x4U << FSMC_PCR3_TAR_Pos) /*!< 0x00008000 */
7450 #define FSMC_PCR3_TAR_3 (0x8U << FSMC_PCR3_TAR_Pos) /*!< 0x00010000 */
7451
7452 #define FSMC_PCR3_ECCPS_Pos (17U)
7453 #define FSMC_PCR3_ECCPS_Msk (0x7U << FSMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
7454 #define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
7455 #define FSMC_PCR3_ECCPS_0 (0x1U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
7456 #define FSMC_PCR3_ECCPS_1 (0x2U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
7457 #define FSMC_PCR3_ECCPS_2 (0x4U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
7458
7459 /****************** Bit definition for FSMC_PCR4 register *******************/
7460 #define FSMC_PCR4_PWAITEN_Pos (1U)
7461 #define FSMC_PCR4_PWAITEN_Msk (0x1U << FSMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
7462 #define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
7463 #define FSMC_PCR4_PBKEN_Pos (2U)
7464 #define FSMC_PCR4_PBKEN_Msk (0x1U << FSMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
7465 #define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7466 #define FSMC_PCR4_PTYP_Pos (3U)
7467 #define FSMC_PCR4_PTYP_Msk (0x1U << FSMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
7468 #define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk /*!<Memory type */
7469
7470 #define FSMC_PCR4_PWID_Pos (4U)
7471 #define FSMC_PCR4_PWID_Msk (0x3U << FSMC_PCR4_PWID_Pos) /*!< 0x00000030 */
7472 #define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7473 #define FSMC_PCR4_PWID_0 (0x1U << FSMC_PCR4_PWID_Pos) /*!< 0x00000010 */
7474 #define FSMC_PCR4_PWID_1 (0x2U << FSMC_PCR4_PWID_Pos) /*!< 0x00000020 */
7475
7476 #define FSMC_PCR4_ECCEN_Pos (6U)
7477 #define FSMC_PCR4_ECCEN_Msk (0x1U << FSMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
7478 #define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
7479
7480 #define FSMC_PCR4_TCLR_Pos (9U)
7481 #define FSMC_PCR4_TCLR_Msk (0xFU << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
7482 #define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7483 #define FSMC_PCR4_TCLR_0 (0x1U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
7484 #define FSMC_PCR4_TCLR_1 (0x2U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
7485 #define FSMC_PCR4_TCLR_2 (0x4U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
7486 #define FSMC_PCR4_TCLR_3 (0x8U << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7487
7488 #define FSMC_PCR4_TAR_Pos (13U)
7489 #define FSMC_PCR4_TAR_Msk (0xFU << FSMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
7490 #define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7491 #define FSMC_PCR4_TAR_0 (0x1U << FSMC_PCR4_TAR_Pos) /*!< 0x00002000 */
7492 #define FSMC_PCR4_TAR_1 (0x2U << FSMC_PCR4_TAR_Pos) /*!< 0x00004000 */
7493 #define FSMC_PCR4_TAR_2 (0x4U << FSMC_PCR4_TAR_Pos) /*!< 0x00008000 */
7494 #define FSMC_PCR4_TAR_3 (0x8U << FSMC_PCR4_TAR_Pos) /*!< 0x00010000 */
7495
7496 #define FSMC_PCR4_ECCPS_Pos (17U)
7497 #define FSMC_PCR4_ECCPS_Msk (0x7U << FSMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
7498 #define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
7499 #define FSMC_PCR4_ECCPS_0 (0x1U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
7500 #define FSMC_PCR4_ECCPS_1 (0x2U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
7501 #define FSMC_PCR4_ECCPS_2 (0x4U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
7502
7503 /******************* Bit definition for FSMC_SR2 register *******************/
7504 #define FSMC_SR2_IRS_Pos (0U)
7505 #define FSMC_SR2_IRS_Msk (0x1U << FSMC_SR2_IRS_Pos) /*!< 0x00000001 */
7506 #define FSMC_SR2_IRS FSMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
7507 #define FSMC_SR2_ILS_Pos (1U)
7508 #define FSMC_SR2_ILS_Msk (0x1U << FSMC_SR2_ILS_Pos) /*!< 0x00000002 */
7509 #define FSMC_SR2_ILS FSMC_SR2_ILS_Msk /*!<Interrupt Level status */
7510 #define FSMC_SR2_IFS_Pos (2U)
7511 #define FSMC_SR2_IFS_Msk (0x1U << FSMC_SR2_IFS_Pos) /*!< 0x00000004 */
7512 #define FSMC_SR2_IFS FSMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
7513 #define FSMC_SR2_IREN_Pos (3U)
7514 #define FSMC_SR2_IREN_Msk (0x1U << FSMC_SR2_IREN_Pos) /*!< 0x00000008 */
7515 #define FSMC_SR2_IREN FSMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7516 #define FSMC_SR2_ILEN_Pos (4U)
7517 #define FSMC_SR2_ILEN_Msk (0x1U << FSMC_SR2_ILEN_Pos) /*!< 0x00000010 */
7518 #define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7519 #define FSMC_SR2_IFEN_Pos (5U)
7520 #define FSMC_SR2_IFEN_Msk (0x1U << FSMC_SR2_IFEN_Pos) /*!< 0x00000020 */
7521 #define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7522 #define FSMC_SR2_FEMPT_Pos (6U)
7523 #define FSMC_SR2_FEMPT_Msk (0x1U << FSMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
7524 #define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk /*!<FIFO empty */
7525
7526 /******************* Bit definition for FSMC_SR3 register *******************/
7527 #define FSMC_SR3_IRS_Pos (0U)
7528 #define FSMC_SR3_IRS_Msk (0x1U << FSMC_SR3_IRS_Pos) /*!< 0x00000001 */
7529 #define FSMC_SR3_IRS FSMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
7530 #define FSMC_SR3_ILS_Pos (1U)
7531 #define FSMC_SR3_ILS_Msk (0x1U << FSMC_SR3_ILS_Pos) /*!< 0x00000002 */
7532 #define FSMC_SR3_ILS FSMC_SR3_ILS_Msk /*!<Interrupt Level status */
7533 #define FSMC_SR3_IFS_Pos (2U)
7534 #define FSMC_SR3_IFS_Msk (0x1U << FSMC_SR3_IFS_Pos) /*!< 0x00000004 */
7535 #define FSMC_SR3_IFS FSMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
7536 #define FSMC_SR3_IREN_Pos (3U)
7537 #define FSMC_SR3_IREN_Msk (0x1U << FSMC_SR3_IREN_Pos) /*!< 0x00000008 */
7538 #define FSMC_SR3_IREN FSMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7539 #define FSMC_SR3_ILEN_Pos (4U)
7540 #define FSMC_SR3_ILEN_Msk (0x1U << FSMC_SR3_ILEN_Pos) /*!< 0x00000010 */
7541 #define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7542 #define FSMC_SR3_IFEN_Pos (5U)
7543 #define FSMC_SR3_IFEN_Msk (0x1U << FSMC_SR3_IFEN_Pos) /*!< 0x00000020 */
7544 #define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7545 #define FSMC_SR3_FEMPT_Pos (6U)
7546 #define FSMC_SR3_FEMPT_Msk (0x1U << FSMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
7547 #define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk /*!<FIFO empty */
7548
7549 /******************* Bit definition for FSMC_SR4 register *******************/
7550 #define FSMC_SR4_IRS_Pos (0U)
7551 #define FSMC_SR4_IRS_Msk (0x1U << FSMC_SR4_IRS_Pos) /*!< 0x00000001 */
7552 #define FSMC_SR4_IRS FSMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
7553 #define FSMC_SR4_ILS_Pos (1U)
7554 #define FSMC_SR4_ILS_Msk (0x1U << FSMC_SR4_ILS_Pos) /*!< 0x00000002 */
7555 #define FSMC_SR4_ILS FSMC_SR4_ILS_Msk /*!<Interrupt Level status */
7556 #define FSMC_SR4_IFS_Pos (2U)
7557 #define FSMC_SR4_IFS_Msk (0x1U << FSMC_SR4_IFS_Pos) /*!< 0x00000004 */
7558 #define FSMC_SR4_IFS FSMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
7559 #define FSMC_SR4_IREN_Pos (3U)
7560 #define FSMC_SR4_IREN_Msk (0x1U << FSMC_SR4_IREN_Pos) /*!< 0x00000008 */
7561 #define FSMC_SR4_IREN FSMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7562 #define FSMC_SR4_ILEN_Pos (4U)
7563 #define FSMC_SR4_ILEN_Msk (0x1U << FSMC_SR4_ILEN_Pos) /*!< 0x00000010 */
7564 #define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7565 #define FSMC_SR4_IFEN_Pos (5U)
7566 #define FSMC_SR4_IFEN_Msk (0x1U << FSMC_SR4_IFEN_Pos) /*!< 0x00000020 */
7567 #define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7568 #define FSMC_SR4_FEMPT_Pos (6U)
7569 #define FSMC_SR4_FEMPT_Msk (0x1U << FSMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
7570 #define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk /*!<FIFO empty */
7571
7572 /****************** Bit definition for FSMC_PMEM2 register ******************/
7573 #define FSMC_PMEM2_MEMSET2_Pos (0U)
7574 #define FSMC_PMEM2_MEMSET2_Msk (0xFFU << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
7575 #define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
7576 #define FSMC_PMEM2_MEMSET2_0 (0x01U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
7577 #define FSMC_PMEM2_MEMSET2_1 (0x02U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
7578 #define FSMC_PMEM2_MEMSET2_2 (0x04U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
7579 #define FSMC_PMEM2_MEMSET2_3 (0x08U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
7580 #define FSMC_PMEM2_MEMSET2_4 (0x10U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
7581 #define FSMC_PMEM2_MEMSET2_5 (0x20U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
7582 #define FSMC_PMEM2_MEMSET2_6 (0x40U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
7583 #define FSMC_PMEM2_MEMSET2_7 (0x80U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
7584
7585 #define FSMC_PMEM2_MEMWAIT2_Pos (8U)
7586 #define FSMC_PMEM2_MEMWAIT2_Msk (0xFFU << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
7587 #define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
7588 #define FSMC_PMEM2_MEMWAIT2_0 (0x01U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
7589 #define FSMC_PMEM2_MEMWAIT2_1 (0x02U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
7590 #define FSMC_PMEM2_MEMWAIT2_2 (0x04U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
7591 #define FSMC_PMEM2_MEMWAIT2_3 (0x08U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
7592 #define FSMC_PMEM2_MEMWAIT2_4 (0x10U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
7593 #define FSMC_PMEM2_MEMWAIT2_5 (0x20U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
7594 #define FSMC_PMEM2_MEMWAIT2_6 (0x40U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
7595 #define FSMC_PMEM2_MEMWAIT2_7 (0x80U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
7596
7597 #define FSMC_PMEM2_MEMHOLD2_Pos (16U)
7598 #define FSMC_PMEM2_MEMHOLD2_Msk (0xFFU << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
7599 #define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
7600 #define FSMC_PMEM2_MEMHOLD2_0 (0x01U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
7601 #define FSMC_PMEM2_MEMHOLD2_1 (0x02U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
7602 #define FSMC_PMEM2_MEMHOLD2_2 (0x04U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
7603 #define FSMC_PMEM2_MEMHOLD2_3 (0x08U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
7604 #define FSMC_PMEM2_MEMHOLD2_4 (0x10U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
7605 #define FSMC_PMEM2_MEMHOLD2_5 (0x20U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
7606 #define FSMC_PMEM2_MEMHOLD2_6 (0x40U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
7607 #define FSMC_PMEM2_MEMHOLD2_7 (0x80U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
7608
7609 #define FSMC_PMEM2_MEMHIZ2_Pos (24U)
7610 #define FSMC_PMEM2_MEMHIZ2_Msk (0xFFU << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
7611 #define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
7612 #define FSMC_PMEM2_MEMHIZ2_0 (0x01U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
7613 #define FSMC_PMEM2_MEMHIZ2_1 (0x02U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
7614 #define FSMC_PMEM2_MEMHIZ2_2 (0x04U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
7615 #define FSMC_PMEM2_MEMHIZ2_3 (0x08U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
7616 #define FSMC_PMEM2_MEMHIZ2_4 (0x10U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
7617 #define FSMC_PMEM2_MEMHIZ2_5 (0x20U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
7618 #define FSMC_PMEM2_MEMHIZ2_6 (0x40U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
7619 #define FSMC_PMEM2_MEMHIZ2_7 (0x80U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
7620
7621 /****************** Bit definition for FSMC_PMEM3 register ******************/
7622 #define FSMC_PMEM3_MEMSET3_Pos (0U)
7623 #define FSMC_PMEM3_MEMSET3_Msk (0xFFU << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
7624 #define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
7625 #define FSMC_PMEM3_MEMSET3_0 (0x01U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
7626 #define FSMC_PMEM3_MEMSET3_1 (0x02U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
7627 #define FSMC_PMEM3_MEMSET3_2 (0x04U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
7628 #define FSMC_PMEM3_MEMSET3_3 (0x08U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
7629 #define FSMC_PMEM3_MEMSET3_4 (0x10U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
7630 #define FSMC_PMEM3_MEMSET3_5 (0x20U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
7631 #define FSMC_PMEM3_MEMSET3_6 (0x40U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
7632 #define FSMC_PMEM3_MEMSET3_7 (0x80U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
7633
7634 #define FSMC_PMEM3_MEMWAIT3_Pos (8U)
7635 #define FSMC_PMEM3_MEMWAIT3_Msk (0xFFU << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
7636 #define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
7637 #define FSMC_PMEM3_MEMWAIT3_0 (0x01U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
7638 #define FSMC_PMEM3_MEMWAIT3_1 (0x02U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
7639 #define FSMC_PMEM3_MEMWAIT3_2 (0x04U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
7640 #define FSMC_PMEM3_MEMWAIT3_3 (0x08U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
7641 #define FSMC_PMEM3_MEMWAIT3_4 (0x10U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
7642 #define FSMC_PMEM3_MEMWAIT3_5 (0x20U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
7643 #define FSMC_PMEM3_MEMWAIT3_6 (0x40U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
7644 #define FSMC_PMEM3_MEMWAIT3_7 (0x80U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
7645
7646 #define FSMC_PMEM3_MEMHOLD3_Pos (16U)
7647 #define FSMC_PMEM3_MEMHOLD3_Msk (0xFFU << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
7648 #define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
7649 #define FSMC_PMEM3_MEMHOLD3_0 (0x01U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
7650 #define FSMC_PMEM3_MEMHOLD3_1 (0x02U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
7651 #define FSMC_PMEM3_MEMHOLD3_2 (0x04U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
7652 #define FSMC_PMEM3_MEMHOLD3_3 (0x08U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
7653 #define FSMC_PMEM3_MEMHOLD3_4 (0x10U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
7654 #define FSMC_PMEM3_MEMHOLD3_5 (0x20U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
7655 #define FSMC_PMEM3_MEMHOLD3_6 (0x40U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
7656 #define FSMC_PMEM3_MEMHOLD3_7 (0x80U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
7657
7658 #define FSMC_PMEM3_MEMHIZ3_Pos (24U)
7659 #define FSMC_PMEM3_MEMHIZ3_Msk (0xFFU << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
7660 #define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
7661 #define FSMC_PMEM3_MEMHIZ3_0 (0x01U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
7662 #define FSMC_PMEM3_MEMHIZ3_1 (0x02U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
7663 #define FSMC_PMEM3_MEMHIZ3_2 (0x04U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
7664 #define FSMC_PMEM3_MEMHIZ3_3 (0x08U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
7665 #define FSMC_PMEM3_MEMHIZ3_4 (0x10U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
7666 #define FSMC_PMEM3_MEMHIZ3_5 (0x20U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
7667 #define FSMC_PMEM3_MEMHIZ3_6 (0x40U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
7668 #define FSMC_PMEM3_MEMHIZ3_7 (0x80U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
7669
7670 /****************** Bit definition for FSMC_PMEM4 register ******************/
7671 #define FSMC_PMEM4_MEMSET4_Pos (0U)
7672 #define FSMC_PMEM4_MEMSET4_Msk (0xFFU << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
7673 #define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
7674 #define FSMC_PMEM4_MEMSET4_0 (0x01U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
7675 #define FSMC_PMEM4_MEMSET4_1 (0x02U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
7676 #define FSMC_PMEM4_MEMSET4_2 (0x04U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
7677 #define FSMC_PMEM4_MEMSET4_3 (0x08U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
7678 #define FSMC_PMEM4_MEMSET4_4 (0x10U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
7679 #define FSMC_PMEM4_MEMSET4_5 (0x20U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
7680 #define FSMC_PMEM4_MEMSET4_6 (0x40U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
7681 #define FSMC_PMEM4_MEMSET4_7 (0x80U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
7682
7683 #define FSMC_PMEM4_MEMWAIT4_Pos (8U)
7684 #define FSMC_PMEM4_MEMWAIT4_Msk (0xFFU << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
7685 #define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
7686 #define FSMC_PMEM4_MEMWAIT4_0 (0x01U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
7687 #define FSMC_PMEM4_MEMWAIT4_1 (0x02U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
7688 #define FSMC_PMEM4_MEMWAIT4_2 (0x04U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
7689 #define FSMC_PMEM4_MEMWAIT4_3 (0x08U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
7690 #define FSMC_PMEM4_MEMWAIT4_4 (0x10U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
7691 #define FSMC_PMEM4_MEMWAIT4_5 (0x20U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
7692 #define FSMC_PMEM4_MEMWAIT4_6 (0x40U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
7693 #define FSMC_PMEM4_MEMWAIT4_7 (0x80U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
7694
7695 #define FSMC_PMEM4_MEMHOLD4_Pos (16U)
7696 #define FSMC_PMEM4_MEMHOLD4_Msk (0xFFU << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
7697 #define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
7698 #define FSMC_PMEM4_MEMHOLD4_0 (0x01U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
7699 #define FSMC_PMEM4_MEMHOLD4_1 (0x02U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
7700 #define FSMC_PMEM4_MEMHOLD4_2 (0x04U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
7701 #define FSMC_PMEM4_MEMHOLD4_3 (0x08U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
7702 #define FSMC_PMEM4_MEMHOLD4_4 (0x10U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
7703 #define FSMC_PMEM4_MEMHOLD4_5 (0x20U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
7704 #define FSMC_PMEM4_MEMHOLD4_6 (0x40U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
7705 #define FSMC_PMEM4_MEMHOLD4_7 (0x80U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
7706
7707 #define FSMC_PMEM4_MEMHIZ4_Pos (24U)
7708 #define FSMC_PMEM4_MEMHIZ4_Msk (0xFFU << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
7709 #define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
7710 #define FSMC_PMEM4_MEMHIZ4_0 (0x01U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
7711 #define FSMC_PMEM4_MEMHIZ4_1 (0x02U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
7712 #define FSMC_PMEM4_MEMHIZ4_2 (0x04U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
7713 #define FSMC_PMEM4_MEMHIZ4_3 (0x08U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
7714 #define FSMC_PMEM4_MEMHIZ4_4 (0x10U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
7715 #define FSMC_PMEM4_MEMHIZ4_5 (0x20U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
7716 #define FSMC_PMEM4_MEMHIZ4_6 (0x40U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
7717 #define FSMC_PMEM4_MEMHIZ4_7 (0x80U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
7718
7719 /****************** Bit definition for FSMC_PATT2 register ******************/
7720 #define FSMC_PATT2_ATTSET2_Pos (0U)
7721 #define FSMC_PATT2_ATTSET2_Msk (0xFFU << FSMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
7722 #define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
7723 #define FSMC_PATT2_ATTSET2_0 (0x01U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
7724 #define FSMC_PATT2_ATTSET2_1 (0x02U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
7725 #define FSMC_PATT2_ATTSET2_2 (0x04U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
7726 #define FSMC_PATT2_ATTSET2_3 (0x08U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
7727 #define FSMC_PATT2_ATTSET2_4 (0x10U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
7728 #define FSMC_PATT2_ATTSET2_5 (0x20U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
7729 #define FSMC_PATT2_ATTSET2_6 (0x40U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
7730 #define FSMC_PATT2_ATTSET2_7 (0x80U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
7731
7732 #define FSMC_PATT2_ATTWAIT2_Pos (8U)
7733 #define FSMC_PATT2_ATTWAIT2_Msk (0xFFU << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
7734 #define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
7735 #define FSMC_PATT2_ATTWAIT2_0 (0x01U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
7736 #define FSMC_PATT2_ATTWAIT2_1 (0x02U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
7737 #define FSMC_PATT2_ATTWAIT2_2 (0x04U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
7738 #define FSMC_PATT2_ATTWAIT2_3 (0x08U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
7739 #define FSMC_PATT2_ATTWAIT2_4 (0x10U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
7740 #define FSMC_PATT2_ATTWAIT2_5 (0x20U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
7741 #define FSMC_PATT2_ATTWAIT2_6 (0x40U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
7742 #define FSMC_PATT2_ATTWAIT2_7 (0x80U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
7743
7744 #define FSMC_PATT2_ATTHOLD2_Pos (16U)
7745 #define FSMC_PATT2_ATTHOLD2_Msk (0xFFU << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
7746 #define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
7747 #define FSMC_PATT2_ATTHOLD2_0 (0x01U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
7748 #define FSMC_PATT2_ATTHOLD2_1 (0x02U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
7749 #define FSMC_PATT2_ATTHOLD2_2 (0x04U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
7750 #define FSMC_PATT2_ATTHOLD2_3 (0x08U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
7751 #define FSMC_PATT2_ATTHOLD2_4 (0x10U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
7752 #define FSMC_PATT2_ATTHOLD2_5 (0x20U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
7753 #define FSMC_PATT2_ATTHOLD2_6 (0x40U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
7754 #define FSMC_PATT2_ATTHOLD2_7 (0x80U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
7755
7756 #define FSMC_PATT2_ATTHIZ2_Pos (24U)
7757 #define FSMC_PATT2_ATTHIZ2_Msk (0xFFU << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
7758 #define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
7759 #define FSMC_PATT2_ATTHIZ2_0 (0x01U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
7760 #define FSMC_PATT2_ATTHIZ2_1 (0x02U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
7761 #define FSMC_PATT2_ATTHIZ2_2 (0x04U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
7762 #define FSMC_PATT2_ATTHIZ2_3 (0x08U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
7763 #define FSMC_PATT2_ATTHIZ2_4 (0x10U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
7764 #define FSMC_PATT2_ATTHIZ2_5 (0x20U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
7765 #define FSMC_PATT2_ATTHIZ2_6 (0x40U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
7766 #define FSMC_PATT2_ATTHIZ2_7 (0x80U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
7767
7768 /****************** Bit definition for FSMC_PATT3 register ******************/
7769 #define FSMC_PATT3_ATTSET3_Pos (0U)
7770 #define FSMC_PATT3_ATTSET3_Msk (0xFFU << FSMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
7771 #define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
7772 #define FSMC_PATT3_ATTSET3_0 (0x01U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
7773 #define FSMC_PATT3_ATTSET3_1 (0x02U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
7774 #define FSMC_PATT3_ATTSET3_2 (0x04U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
7775 #define FSMC_PATT3_ATTSET3_3 (0x08U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
7776 #define FSMC_PATT3_ATTSET3_4 (0x10U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
7777 #define FSMC_PATT3_ATTSET3_5 (0x20U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
7778 #define FSMC_PATT3_ATTSET3_6 (0x40U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
7779 #define FSMC_PATT3_ATTSET3_7 (0x80U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
7780
7781 #define FSMC_PATT3_ATTWAIT3_Pos (8U)
7782 #define FSMC_PATT3_ATTWAIT3_Msk (0xFFU << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
7783 #define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
7784 #define FSMC_PATT3_ATTWAIT3_0 (0x01U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
7785 #define FSMC_PATT3_ATTWAIT3_1 (0x02U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
7786 #define FSMC_PATT3_ATTWAIT3_2 (0x04U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
7787 #define FSMC_PATT3_ATTWAIT3_3 (0x08U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
7788 #define FSMC_PATT3_ATTWAIT3_4 (0x10U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
7789 #define FSMC_PATT3_ATTWAIT3_5 (0x20U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
7790 #define FSMC_PATT3_ATTWAIT3_6 (0x40U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
7791 #define FSMC_PATT3_ATTWAIT3_7 (0x80U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
7792
7793 #define FSMC_PATT3_ATTHOLD3_Pos (16U)
7794 #define FSMC_PATT3_ATTHOLD3_Msk (0xFFU << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
7795 #define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
7796 #define FSMC_PATT3_ATTHOLD3_0 (0x01U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
7797 #define FSMC_PATT3_ATTHOLD3_1 (0x02U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
7798 #define FSMC_PATT3_ATTHOLD3_2 (0x04U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
7799 #define FSMC_PATT3_ATTHOLD3_3 (0x08U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
7800 #define FSMC_PATT3_ATTHOLD3_4 (0x10U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
7801 #define FSMC_PATT3_ATTHOLD3_5 (0x20U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
7802 #define FSMC_PATT3_ATTHOLD3_6 (0x40U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
7803 #define FSMC_PATT3_ATTHOLD3_7 (0x80U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
7804
7805 #define FSMC_PATT3_ATTHIZ3_Pos (24U)
7806 #define FSMC_PATT3_ATTHIZ3_Msk (0xFFU << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
7807 #define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
7808 #define FSMC_PATT3_ATTHIZ3_0 (0x01U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
7809 #define FSMC_PATT3_ATTHIZ3_1 (0x02U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
7810 #define FSMC_PATT3_ATTHIZ3_2 (0x04U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
7811 #define FSMC_PATT3_ATTHIZ3_3 (0x08U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
7812 #define FSMC_PATT3_ATTHIZ3_4 (0x10U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
7813 #define FSMC_PATT3_ATTHIZ3_5 (0x20U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
7814 #define FSMC_PATT3_ATTHIZ3_6 (0x40U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
7815 #define FSMC_PATT3_ATTHIZ3_7 (0x80U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
7816
7817 /****************** Bit definition for FSMC_PATT4 register ******************/
7818 #define FSMC_PATT4_ATTSET4_Pos (0U)
7819 #define FSMC_PATT4_ATTSET4_Msk (0xFFU << FSMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
7820 #define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
7821 #define FSMC_PATT4_ATTSET4_0 (0x01U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
7822 #define FSMC_PATT4_ATTSET4_1 (0x02U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
7823 #define FSMC_PATT4_ATTSET4_2 (0x04U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
7824 #define FSMC_PATT4_ATTSET4_3 (0x08U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
7825 #define FSMC_PATT4_ATTSET4_4 (0x10U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
7826 #define FSMC_PATT4_ATTSET4_5 (0x20U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
7827 #define FSMC_PATT4_ATTSET4_6 (0x40U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
7828 #define FSMC_PATT4_ATTSET4_7 (0x80U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
7829
7830 #define FSMC_PATT4_ATTWAIT4_Pos (8U)
7831 #define FSMC_PATT4_ATTWAIT4_Msk (0xFFU << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
7832 #define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
7833 #define FSMC_PATT4_ATTWAIT4_0 (0x01U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
7834 #define FSMC_PATT4_ATTWAIT4_1 (0x02U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
7835 #define FSMC_PATT4_ATTWAIT4_2 (0x04U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
7836 #define FSMC_PATT4_ATTWAIT4_3 (0x08U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
7837 #define FSMC_PATT4_ATTWAIT4_4 (0x10U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
7838 #define FSMC_PATT4_ATTWAIT4_5 (0x20U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
7839 #define FSMC_PATT4_ATTWAIT4_6 (0x40U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
7840 #define FSMC_PATT4_ATTWAIT4_7 (0x80U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
7841
7842 #define FSMC_PATT4_ATTHOLD4_Pos (16U)
7843 #define FSMC_PATT4_ATTHOLD4_Msk (0xFFU << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
7844 #define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
7845 #define FSMC_PATT4_ATTHOLD4_0 (0x01U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
7846 #define FSMC_PATT4_ATTHOLD4_1 (0x02U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
7847 #define FSMC_PATT4_ATTHOLD4_2 (0x04U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
7848 #define FSMC_PATT4_ATTHOLD4_3 (0x08U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
7849 #define FSMC_PATT4_ATTHOLD4_4 (0x10U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
7850 #define FSMC_PATT4_ATTHOLD4_5 (0x20U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
7851 #define FSMC_PATT4_ATTHOLD4_6 (0x40U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
7852 #define FSMC_PATT4_ATTHOLD4_7 (0x80U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
7853
7854 #define FSMC_PATT4_ATTHIZ4_Pos (24U)
7855 #define FSMC_PATT4_ATTHIZ4_Msk (0xFFU << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
7856 #define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
7857 #define FSMC_PATT4_ATTHIZ4_0 (0x01U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
7858 #define FSMC_PATT4_ATTHIZ4_1 (0x02U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
7859 #define FSMC_PATT4_ATTHIZ4_2 (0x04U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
7860 #define FSMC_PATT4_ATTHIZ4_3 (0x08U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
7861 #define FSMC_PATT4_ATTHIZ4_4 (0x10U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
7862 #define FSMC_PATT4_ATTHIZ4_5 (0x20U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
7863 #define FSMC_PATT4_ATTHIZ4_6 (0x40U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
7864 #define FSMC_PATT4_ATTHIZ4_7 (0x80U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
7865
7866 /****************** Bit definition for FSMC_PIO4 register *******************/
7867 #define FSMC_PIO4_IOSET4_Pos (0U)
7868 #define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
7869 #define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
7870 #define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
7871 #define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
7872 #define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
7873 #define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
7874 #define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
7875 #define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
7876 #define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
7877 #define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
7878
7879 #define FSMC_PIO4_IOWAIT4_Pos (8U)
7880 #define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
7881 #define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
7882 #define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
7883 #define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
7884 #define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
7885 #define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
7886 #define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
7887 #define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
7888 #define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
7889 #define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
7890
7891 #define FSMC_PIO4_IOHOLD4_Pos (16U)
7892 #define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
7893 #define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
7894 #define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
7895 #define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
7896 #define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
7897 #define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
7898 #define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
7899 #define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
7900 #define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
7901 #define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
7902
7903 #define FSMC_PIO4_IOHIZ4_Pos (24U)
7904 #define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
7905 #define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
7906 #define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
7907 #define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
7908 #define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
7909 #define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
7910 #define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
7911 #define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
7912 #define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
7913 #define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
7914
7915 /****************** Bit definition for FSMC_ECCR2 register ******************/
7916 #define FSMC_ECCR2_ECC2_Pos (0U)
7917 #define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
7918 #define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!<ECC result */
7919
7920 /****************** Bit definition for FSMC_ECCR3 register ******************/
7921 #define FSMC_ECCR3_ECC3_Pos (0U)
7922 #define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
7923 #define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!<ECC result */
7924
7925 /******************************************************************************/
7926 /* */
7927 /* General Purpose I/O */
7928 /* */
7929 /******************************************************************************/
7930 /****************** Bits definition for GPIO_MODER register *****************/
7931 #define GPIO_MODER_MODE0_Pos (0U)
7932 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
7933 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
7934 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
7935 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
7936 #define GPIO_MODER_MODE1_Pos (2U)
7937 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
7938 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
7939 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
7940 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
7941 #define GPIO_MODER_MODE2_Pos (4U)
7942 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
7943 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
7944 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
7945 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
7946 #define GPIO_MODER_MODE3_Pos (6U)
7947 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
7948 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
7949 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
7950 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
7951 #define GPIO_MODER_MODE4_Pos (8U)
7952 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
7953 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
7954 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
7955 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
7956 #define GPIO_MODER_MODE5_Pos (10U)
7957 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
7958 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
7959 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
7960 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
7961 #define GPIO_MODER_MODE6_Pos (12U)
7962 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
7963 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
7964 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
7965 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
7966 #define GPIO_MODER_MODE7_Pos (14U)
7967 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
7968 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
7969 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
7970 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
7971 #define GPIO_MODER_MODE8_Pos (16U)
7972 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
7973 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
7974 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
7975 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
7976 #define GPIO_MODER_MODE9_Pos (18U)
7977 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
7978 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
7979 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
7980 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
7981 #define GPIO_MODER_MODE10_Pos (20U)
7982 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
7983 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
7984 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
7985 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
7986 #define GPIO_MODER_MODE11_Pos (22U)
7987 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
7988 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
7989 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
7990 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
7991 #define GPIO_MODER_MODE12_Pos (24U)
7992 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
7993 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
7994 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
7995 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
7996 #define GPIO_MODER_MODE13_Pos (26U)
7997 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
7998 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
7999 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
8000 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
8001 #define GPIO_MODER_MODE14_Pos (28U)
8002 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
8003 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8004 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
8005 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
8006 #define GPIO_MODER_MODE15_Pos (30U)
8007 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
8008 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8009 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
8010 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
8011
8012 /* Legacy defines */
8013 #define GPIO_MODER_MODER0_Pos (0U)
8014 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
8015 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8016 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
8017 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
8018 #define GPIO_MODER_MODER1_Pos (2U)
8019 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
8020 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8021 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
8022 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
8023 #define GPIO_MODER_MODER2_Pos (4U)
8024 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
8025 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8026 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
8027 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
8028 #define GPIO_MODER_MODER3_Pos (6U)
8029 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
8030 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8031 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
8032 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
8033 #define GPIO_MODER_MODER4_Pos (8U)
8034 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
8035 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8036 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
8037 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
8038 #define GPIO_MODER_MODER5_Pos (10U)
8039 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
8040 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8041 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
8042 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
8043 #define GPIO_MODER_MODER6_Pos (12U)
8044 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
8045 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8046 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
8047 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
8048 #define GPIO_MODER_MODER7_Pos (14U)
8049 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
8050 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8051 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
8052 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
8053 #define GPIO_MODER_MODER8_Pos (16U)
8054 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
8055 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8056 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
8057 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
8058 #define GPIO_MODER_MODER9_Pos (18U)
8059 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
8060 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8061 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
8062 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
8063 #define GPIO_MODER_MODER10_Pos (20U)
8064 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
8065 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8066 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
8067 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
8068 #define GPIO_MODER_MODER11_Pos (22U)
8069 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
8070 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8071 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
8072 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
8073 #define GPIO_MODER_MODER12_Pos (24U)
8074 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
8075 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8076 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
8077 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
8078 #define GPIO_MODER_MODER13_Pos (26U)
8079 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
8080 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8081 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
8082 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
8083 #define GPIO_MODER_MODER14_Pos (28U)
8084 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
8085 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8086 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
8087 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
8088 #define GPIO_MODER_MODER15_Pos (30U)
8089 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
8090 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8091 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
8092 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
8093
8094 /****************** Bits definition for GPIO_OTYPER register ****************/
8095 #define GPIO_OTYPER_OT0_Pos (0U)
8096 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
8097 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8098 #define GPIO_OTYPER_OT1_Pos (1U)
8099 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
8100 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8101 #define GPIO_OTYPER_OT2_Pos (2U)
8102 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
8103 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8104 #define GPIO_OTYPER_OT3_Pos (3U)
8105 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
8106 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8107 #define GPIO_OTYPER_OT4_Pos (4U)
8108 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
8109 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8110 #define GPIO_OTYPER_OT5_Pos (5U)
8111 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
8112 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8113 #define GPIO_OTYPER_OT6_Pos (6U)
8114 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
8115 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8116 #define GPIO_OTYPER_OT7_Pos (7U)
8117 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
8118 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8119 #define GPIO_OTYPER_OT8_Pos (8U)
8120 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
8121 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8122 #define GPIO_OTYPER_OT9_Pos (9U)
8123 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
8124 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8125 #define GPIO_OTYPER_OT10_Pos (10U)
8126 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
8127 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8128 #define GPIO_OTYPER_OT11_Pos (11U)
8129 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
8130 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8131 #define GPIO_OTYPER_OT12_Pos (12U)
8132 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
8133 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8134 #define GPIO_OTYPER_OT13_Pos (13U)
8135 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
8136 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8137 #define GPIO_OTYPER_OT14_Pos (14U)
8138 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
8139 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8140 #define GPIO_OTYPER_OT15_Pos (15U)
8141 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
8142 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8143
8144 /* Legacy defines */
8145 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8146 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8147 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8148 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8149 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8150 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8151 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8152 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8153 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8154 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8155 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8156 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8157 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8158 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8159 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8160 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8161
8162 /****************** Bits definition for GPIO_OSPEEDR register ***************/
8163 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8164 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
8165 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8166 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
8167 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
8168 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8169 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
8170 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8171 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
8172 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
8173 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8174 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
8175 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8176 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
8177 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
8178 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8179 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
8180 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8181 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
8182 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
8183 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8184 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
8185 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8186 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
8187 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
8188 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8189 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
8190 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8191 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
8192 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
8193 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8194 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
8195 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8196 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
8197 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
8198 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8199 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
8200 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8201 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
8202 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
8203 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8204 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
8205 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8206 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
8207 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
8208 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8209 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
8210 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8211 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
8212 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
8213 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8214 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
8215 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8216 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
8217 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
8218 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8219 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
8220 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8221 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
8222 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
8223 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8224 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
8225 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8226 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
8227 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
8228 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8229 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
8230 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8231 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
8232 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
8233 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8234 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
8235 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8236 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
8237 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
8238 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8239 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
8240 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8241 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
8242 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
8243
8244 /* Legacy defines */
8245 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8246 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8247 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8248 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8249 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8250 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8251 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8252 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8253 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8254 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8255 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8256 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8257 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8258 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8259 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8260 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8261 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8262 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8263 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8264 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8265 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8266 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8267 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8268 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8269 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8270 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8271 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8272 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8273 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8274 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8275 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8276 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8277 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8278 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8279 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8280 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8281 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8282 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8283 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8284 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8285 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8286 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8287 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8288 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8289 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8290 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8291 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8292 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8293
8294 /****************** Bits definition for GPIO_PUPDR register *****************/
8295 #define GPIO_PUPDR_PUPD0_Pos (0U)
8296 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
8297 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8298 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
8299 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
8300 #define GPIO_PUPDR_PUPD1_Pos (2U)
8301 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
8302 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8303 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
8304 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
8305 #define GPIO_PUPDR_PUPD2_Pos (4U)
8306 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
8307 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8308 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
8309 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
8310 #define GPIO_PUPDR_PUPD3_Pos (6U)
8311 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
8312 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8313 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
8314 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
8315 #define GPIO_PUPDR_PUPD4_Pos (8U)
8316 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
8317 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8318 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
8319 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
8320 #define GPIO_PUPDR_PUPD5_Pos (10U)
8321 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
8322 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8323 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
8324 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
8325 #define GPIO_PUPDR_PUPD6_Pos (12U)
8326 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
8327 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8328 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
8329 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
8330 #define GPIO_PUPDR_PUPD7_Pos (14U)
8331 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
8332 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8333 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
8334 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
8335 #define GPIO_PUPDR_PUPD8_Pos (16U)
8336 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
8337 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8338 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
8339 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
8340 #define GPIO_PUPDR_PUPD9_Pos (18U)
8341 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
8342 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8343 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
8344 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
8345 #define GPIO_PUPDR_PUPD10_Pos (20U)
8346 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
8347 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8348 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
8349 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
8350 #define GPIO_PUPDR_PUPD11_Pos (22U)
8351 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
8352 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8353 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
8354 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
8355 #define GPIO_PUPDR_PUPD12_Pos (24U)
8356 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
8357 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8358 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
8359 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
8360 #define GPIO_PUPDR_PUPD13_Pos (26U)
8361 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
8362 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8363 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
8364 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
8365 #define GPIO_PUPDR_PUPD14_Pos (28U)
8366 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
8367 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8368 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
8369 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
8370 #define GPIO_PUPDR_PUPD15_Pos (30U)
8371 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
8372 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8373 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
8374 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
8375
8376 /* Legacy defines */
8377 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8378 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8379 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8380 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8381 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8382 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8383 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8384 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8385 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8386 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8387 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8388 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8389 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8390 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8391 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8392 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8393 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8394 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8395 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8396 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8397 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8398 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8399 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8400 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8401 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8402 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8403 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8404 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8405 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8406 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8407 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8408 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8409 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8410 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8411 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8412 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8413 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8414 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8415 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8416 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8417 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8418 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8419 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8420 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8421 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8422 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8423 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8424 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8425
8426 /****************** Bits definition for GPIO_IDR register *******************/
8427 #define GPIO_IDR_ID0_Pos (0U)
8428 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
8429 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8430 #define GPIO_IDR_ID1_Pos (1U)
8431 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
8432 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8433 #define GPIO_IDR_ID2_Pos (2U)
8434 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
8435 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8436 #define GPIO_IDR_ID3_Pos (3U)
8437 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
8438 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8439 #define GPIO_IDR_ID4_Pos (4U)
8440 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
8441 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8442 #define GPIO_IDR_ID5_Pos (5U)
8443 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
8444 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8445 #define GPIO_IDR_ID6_Pos (6U)
8446 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
8447 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8448 #define GPIO_IDR_ID7_Pos (7U)
8449 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
8450 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8451 #define GPIO_IDR_ID8_Pos (8U)
8452 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
8453 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8454 #define GPIO_IDR_ID9_Pos (9U)
8455 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
8456 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8457 #define GPIO_IDR_ID10_Pos (10U)
8458 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
8459 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8460 #define GPIO_IDR_ID11_Pos (11U)
8461 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
8462 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8463 #define GPIO_IDR_ID12_Pos (12U)
8464 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
8465 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8466 #define GPIO_IDR_ID13_Pos (13U)
8467 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
8468 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8469 #define GPIO_IDR_ID14_Pos (14U)
8470 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
8471 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8472 #define GPIO_IDR_ID15_Pos (15U)
8473 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
8474 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8475
8476 /* Legacy defines */
8477 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8478 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8479 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8480 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8481 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8482 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8483 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8484 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8485 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8486 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8487 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8488 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8489 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8490 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8491 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8492 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8493
8494 /****************** Bits definition for GPIO_ODR register *******************/
8495 #define GPIO_ODR_OD0_Pos (0U)
8496 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
8497 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8498 #define GPIO_ODR_OD1_Pos (1U)
8499 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
8500 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8501 #define GPIO_ODR_OD2_Pos (2U)
8502 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
8503 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8504 #define GPIO_ODR_OD3_Pos (3U)
8505 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
8506 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8507 #define GPIO_ODR_OD4_Pos (4U)
8508 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
8509 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8510 #define GPIO_ODR_OD5_Pos (5U)
8511 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
8512 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8513 #define GPIO_ODR_OD6_Pos (6U)
8514 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
8515 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8516 #define GPIO_ODR_OD7_Pos (7U)
8517 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
8518 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8519 #define GPIO_ODR_OD8_Pos (8U)
8520 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
8521 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8522 #define GPIO_ODR_OD9_Pos (9U)
8523 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
8524 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8525 #define GPIO_ODR_OD10_Pos (10U)
8526 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
8527 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8528 #define GPIO_ODR_OD11_Pos (11U)
8529 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
8530 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8531 #define GPIO_ODR_OD12_Pos (12U)
8532 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
8533 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8534 #define GPIO_ODR_OD13_Pos (13U)
8535 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
8536 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8537 #define GPIO_ODR_OD14_Pos (14U)
8538 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
8539 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8540 #define GPIO_ODR_OD15_Pos (15U)
8541 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
8542 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8543 /* Legacy defines */
8544 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8545 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8546 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8547 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8548 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8549 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8550 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8551 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8552 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8553 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8554 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8555 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8556 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8557 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8558 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8559 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8560
8561 /****************** Bits definition for GPIO_BSRR register ******************/
8562 #define GPIO_BSRR_BS0_Pos (0U)
8563 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
8564 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8565 #define GPIO_BSRR_BS1_Pos (1U)
8566 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
8567 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8568 #define GPIO_BSRR_BS2_Pos (2U)
8569 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
8570 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8571 #define GPIO_BSRR_BS3_Pos (3U)
8572 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
8573 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8574 #define GPIO_BSRR_BS4_Pos (4U)
8575 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
8576 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8577 #define GPIO_BSRR_BS5_Pos (5U)
8578 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
8579 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8580 #define GPIO_BSRR_BS6_Pos (6U)
8581 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
8582 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8583 #define GPIO_BSRR_BS7_Pos (7U)
8584 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
8585 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8586 #define GPIO_BSRR_BS8_Pos (8U)
8587 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
8588 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8589 #define GPIO_BSRR_BS9_Pos (9U)
8590 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
8591 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8592 #define GPIO_BSRR_BS10_Pos (10U)
8593 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
8594 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8595 #define GPIO_BSRR_BS11_Pos (11U)
8596 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
8597 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8598 #define GPIO_BSRR_BS12_Pos (12U)
8599 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
8600 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8601 #define GPIO_BSRR_BS13_Pos (13U)
8602 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
8603 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8604 #define GPIO_BSRR_BS14_Pos (14U)
8605 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
8606 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8607 #define GPIO_BSRR_BS15_Pos (15U)
8608 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
8609 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8610 #define GPIO_BSRR_BR0_Pos (16U)
8611 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
8612 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8613 #define GPIO_BSRR_BR1_Pos (17U)
8614 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
8615 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8616 #define GPIO_BSRR_BR2_Pos (18U)
8617 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
8618 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8619 #define GPIO_BSRR_BR3_Pos (19U)
8620 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
8621 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8622 #define GPIO_BSRR_BR4_Pos (20U)
8623 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
8624 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8625 #define GPIO_BSRR_BR5_Pos (21U)
8626 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
8627 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8628 #define GPIO_BSRR_BR6_Pos (22U)
8629 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
8630 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8631 #define GPIO_BSRR_BR7_Pos (23U)
8632 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
8633 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8634 #define GPIO_BSRR_BR8_Pos (24U)
8635 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
8636 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8637 #define GPIO_BSRR_BR9_Pos (25U)
8638 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
8639 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8640 #define GPIO_BSRR_BR10_Pos (26U)
8641 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
8642 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8643 #define GPIO_BSRR_BR11_Pos (27U)
8644 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
8645 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8646 #define GPIO_BSRR_BR12_Pos (28U)
8647 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
8648 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8649 #define GPIO_BSRR_BR13_Pos (29U)
8650 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
8651 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8652 #define GPIO_BSRR_BR14_Pos (30U)
8653 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
8654 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8655 #define GPIO_BSRR_BR15_Pos (31U)
8656 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
8657 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8658
8659 /* Legacy defines */
8660 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8661 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8662 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8663 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8664 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8665 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8666 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8667 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8668 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8669 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8670 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8671 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8672 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8673 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8674 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8675 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8676 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8677 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8678 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8679 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8680 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8681 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8682 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8683 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8684 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8685 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8686 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8687 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8688 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8689 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8690 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8691 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8692 /****************** Bit definition for GPIO_LCKR register *********************/
8693 #define GPIO_LCKR_LCK0_Pos (0U)
8694 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
8695 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8696 #define GPIO_LCKR_LCK1_Pos (1U)
8697 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
8698 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8699 #define GPIO_LCKR_LCK2_Pos (2U)
8700 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
8701 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8702 #define GPIO_LCKR_LCK3_Pos (3U)
8703 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
8704 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8705 #define GPIO_LCKR_LCK4_Pos (4U)
8706 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
8707 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8708 #define GPIO_LCKR_LCK5_Pos (5U)
8709 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
8710 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8711 #define GPIO_LCKR_LCK6_Pos (6U)
8712 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
8713 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8714 #define GPIO_LCKR_LCK7_Pos (7U)
8715 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
8716 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8717 #define GPIO_LCKR_LCK8_Pos (8U)
8718 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
8719 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8720 #define GPIO_LCKR_LCK9_Pos (9U)
8721 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
8722 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8723 #define GPIO_LCKR_LCK10_Pos (10U)
8724 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
8725 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8726 #define GPIO_LCKR_LCK11_Pos (11U)
8727 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
8728 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8729 #define GPIO_LCKR_LCK12_Pos (12U)
8730 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
8731 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8732 #define GPIO_LCKR_LCK13_Pos (13U)
8733 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
8734 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8735 #define GPIO_LCKR_LCK14_Pos (14U)
8736 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
8737 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8738 #define GPIO_LCKR_LCK15_Pos (15U)
8739 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
8740 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8741 #define GPIO_LCKR_LCKK_Pos (16U)
8742 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
8743 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8744 /****************** Bit definition for GPIO_AFRL register *********************/
8745 #define GPIO_AFRL_AFSEL0_Pos (0U)
8746 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
8747 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8748 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
8749 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
8750 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
8751 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
8752 #define GPIO_AFRL_AFSEL1_Pos (4U)
8753 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
8754 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8755 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
8756 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
8757 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
8758 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
8759 #define GPIO_AFRL_AFSEL2_Pos (8U)
8760 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
8761 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8762 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
8763 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
8764 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
8765 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
8766 #define GPIO_AFRL_AFSEL3_Pos (12U)
8767 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
8768 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8769 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
8770 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
8771 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
8772 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
8773 #define GPIO_AFRL_AFSEL4_Pos (16U)
8774 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
8775 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8776 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
8777 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
8778 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
8779 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
8780 #define GPIO_AFRL_AFSEL5_Pos (20U)
8781 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
8782 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8783 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
8784 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
8785 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
8786 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
8787 #define GPIO_AFRL_AFSEL6_Pos (24U)
8788 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
8789 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8790 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
8791 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
8792 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
8793 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
8794 #define GPIO_AFRL_AFSEL7_Pos (28U)
8795 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
8796 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8797 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
8798 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
8799 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
8800 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
8801
8802 /* Legacy defines */
8803 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8804 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8805 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8806 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8807 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8808 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8809 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8810 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8811 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8812 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8813 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8814 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8815 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8816 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8817 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8818 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8819 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8820 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8821 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8822 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8823 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8824 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8825 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8826 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8827 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8828 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8829 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8830 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8831 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8832 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8833 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8834 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8835 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8836 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8837 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8838 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8839 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
8840 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
8841 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
8842 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
8843
8844 /****************** Bit definition for GPIO_AFRH register *********************/
8845 #define GPIO_AFRH_AFSEL8_Pos (0U)
8846 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
8847 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8848 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
8849 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
8850 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
8851 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
8852 #define GPIO_AFRH_AFSEL9_Pos (4U)
8853 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
8854 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8855 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
8856 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
8857 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
8858 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
8859 #define GPIO_AFRH_AFSEL10_Pos (8U)
8860 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
8861 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8862 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
8863 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
8864 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
8865 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
8866 #define GPIO_AFRH_AFSEL11_Pos (12U)
8867 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
8868 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8869 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
8870 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
8871 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
8872 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
8873 #define GPIO_AFRH_AFSEL12_Pos (16U)
8874 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
8875 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8876 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
8877 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
8878 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
8879 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
8880 #define GPIO_AFRH_AFSEL13_Pos (20U)
8881 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
8882 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
8883 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
8884 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
8885 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
8886 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
8887 #define GPIO_AFRH_AFSEL14_Pos (24U)
8888 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
8889 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
8890 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
8891 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
8892 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
8893 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
8894 #define GPIO_AFRH_AFSEL15_Pos (28U)
8895 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
8896 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8897 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
8898 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
8899 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
8900 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
8901
8902 /* Legacy defines */
8903 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8904 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
8905 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
8906 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
8907 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
8908 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8909 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
8910 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
8911 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
8912 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
8913 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8914 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
8915 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
8916 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
8917 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
8918 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8919 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
8920 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
8921 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
8922 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
8923 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8924 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
8925 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
8926 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
8927 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
8928 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8929 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
8930 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
8931 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
8932 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
8933 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8934 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
8935 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
8936 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
8937 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
8938 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8939 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
8940 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
8941 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
8942 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
8943
8944 /****************** Bits definition for GPIO_BRR register ******************/
8945 #define GPIO_BRR_BR0_Pos (0U)
8946 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
8947 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
8948 #define GPIO_BRR_BR1_Pos (1U)
8949 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
8950 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
8951 #define GPIO_BRR_BR2_Pos (2U)
8952 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
8953 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
8954 #define GPIO_BRR_BR3_Pos (3U)
8955 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
8956 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
8957 #define GPIO_BRR_BR4_Pos (4U)
8958 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
8959 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
8960 #define GPIO_BRR_BR5_Pos (5U)
8961 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
8962 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
8963 #define GPIO_BRR_BR6_Pos (6U)
8964 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
8965 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
8966 #define GPIO_BRR_BR7_Pos (7U)
8967 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
8968 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
8969 #define GPIO_BRR_BR8_Pos (8U)
8970 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
8971 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
8972 #define GPIO_BRR_BR9_Pos (9U)
8973 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
8974 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
8975 #define GPIO_BRR_BR10_Pos (10U)
8976 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
8977 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
8978 #define GPIO_BRR_BR11_Pos (11U)
8979 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
8980 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
8981 #define GPIO_BRR_BR12_Pos (12U)
8982 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
8983 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
8984 #define GPIO_BRR_BR13_Pos (13U)
8985 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
8986 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
8987 #define GPIO_BRR_BR14_Pos (14U)
8988 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
8989 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
8990 #define GPIO_BRR_BR15_Pos (15U)
8991 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
8992 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
8993
8994
8995 /******************************************************************************/
8996 /* */
8997 /* HASH */
8998 /* */
8999 /******************************************************************************/
9000 /****************** Bits definition for HASH_CR register ********************/
9001 #define HASH_CR_INIT_Pos (2U)
9002 #define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
9003 #define HASH_CR_INIT HASH_CR_INIT_Msk
9004 #define HASH_CR_DMAE_Pos (3U)
9005 #define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
9006 #define HASH_CR_DMAE HASH_CR_DMAE_Msk
9007 #define HASH_CR_DATATYPE_Pos (4U)
9008 #define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
9009 #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
9010 #define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
9011 #define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
9012 #define HASH_CR_MODE_Pos (6U)
9013 #define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
9014 #define HASH_CR_MODE HASH_CR_MODE_Msk
9015 #define HASH_CR_ALGO_Pos (7U)
9016 #define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
9017 #define HASH_CR_ALGO HASH_CR_ALGO_Msk
9018 #define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
9019 #define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
9020 #define HASH_CR_NBW_Pos (8U)
9021 #define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
9022 #define HASH_CR_NBW HASH_CR_NBW_Msk
9023 #define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
9024 #define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
9025 #define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
9026 #define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
9027 #define HASH_CR_DINNE_Pos (12U)
9028 #define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
9029 #define HASH_CR_DINNE HASH_CR_DINNE_Msk
9030 #define HASH_CR_MDMAT_Pos (13U)
9031 #define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
9032 #define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
9033 #define HASH_CR_LKEY_Pos (16U)
9034 #define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
9035 #define HASH_CR_LKEY HASH_CR_LKEY_Msk
9036
9037 /****************** Bits definition for HASH_STR register *******************/
9038 #define HASH_STR_NBLW_Pos (0U)
9039 #define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
9040 #define HASH_STR_NBLW HASH_STR_NBLW_Msk
9041 #define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
9042 #define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
9043 #define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
9044 #define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
9045 #define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
9046 #define HASH_STR_DCAL_Pos (8U)
9047 #define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
9048 #define HASH_STR_DCAL HASH_STR_DCAL_Msk
9049 /* Aliases for HASH_STR register */
9050 #define HASH_STR_NBW HASH_STR_NBLW
9051 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
9052 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
9053 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
9054 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
9055 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
9056
9057 /****************** Bits definition for HASH_IMR register *******************/
9058 #define HASH_IMR_DINIE_Pos (0U)
9059 #define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
9060 #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
9061 #define HASH_IMR_DCIE_Pos (1U)
9062 #define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
9063 #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
9064 /* Aliases for HASH_IMR register */
9065 #define HASH_IMR_DINIM HASH_IMR_DINIE
9066 #define HASH_IMR_DCIM HASH_IMR_DCIE
9067
9068 /****************** Bits definition for HASH_SR register ********************/
9069 #define HASH_SR_DINIS_Pos (0U)
9070 #define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
9071 #define HASH_SR_DINIS HASH_SR_DINIS_Msk
9072 #define HASH_SR_DCIS_Pos (1U)
9073 #define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
9074 #define HASH_SR_DCIS HASH_SR_DCIS_Msk
9075 #define HASH_SR_DMAS_Pos (2U)
9076 #define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
9077 #define HASH_SR_DMAS HASH_SR_DMAS_Msk
9078 #define HASH_SR_BUSY_Pos (3U)
9079 #define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
9080 #define HASH_SR_BUSY HASH_SR_BUSY_Msk
9081
9082 /******************************************************************************/
9083 /* */
9084 /* Inter-integrated Circuit Interface */
9085 /* */
9086 /******************************************************************************/
9087 /******************* Bit definition for I2C_CR1 register ********************/
9088 #define I2C_CR1_PE_Pos (0U)
9089 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
9090 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
9091 #define I2C_CR1_SMBUS_Pos (1U)
9092 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
9093 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
9094 #define I2C_CR1_SMBTYPE_Pos (3U)
9095 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
9096 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
9097 #define I2C_CR1_ENARP_Pos (4U)
9098 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
9099 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
9100 #define I2C_CR1_ENPEC_Pos (5U)
9101 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
9102 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
9103 #define I2C_CR1_ENGC_Pos (6U)
9104 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
9105 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
9106 #define I2C_CR1_NOSTRETCH_Pos (7U)
9107 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
9108 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
9109 #define I2C_CR1_START_Pos (8U)
9110 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
9111 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
9112 #define I2C_CR1_STOP_Pos (9U)
9113 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
9114 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
9115 #define I2C_CR1_ACK_Pos (10U)
9116 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
9117 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
9118 #define I2C_CR1_POS_Pos (11U)
9119 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
9120 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
9121 #define I2C_CR1_PEC_Pos (12U)
9122 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
9123 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
9124 #define I2C_CR1_ALERT_Pos (13U)
9125 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
9126 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
9127 #define I2C_CR1_SWRST_Pos (15U)
9128 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
9129 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
9130
9131 /******************* Bit definition for I2C_CR2 register ********************/
9132 #define I2C_CR2_FREQ_Pos (0U)
9133 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
9134 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
9135 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
9136 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
9137 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
9138 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
9139 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
9140 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
9141
9142 #define I2C_CR2_ITERREN_Pos (8U)
9143 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
9144 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
9145 #define I2C_CR2_ITEVTEN_Pos (9U)
9146 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
9147 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
9148 #define I2C_CR2_ITBUFEN_Pos (10U)
9149 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
9150 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
9151 #define I2C_CR2_DMAEN_Pos (11U)
9152 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
9153 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
9154 #define I2C_CR2_LAST_Pos (12U)
9155 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
9156 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
9157
9158 /******************* Bit definition for I2C_OAR1 register *******************/
9159 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
9160 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
9161
9162 #define I2C_OAR1_ADD0_Pos (0U)
9163 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
9164 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
9165 #define I2C_OAR1_ADD1_Pos (1U)
9166 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
9167 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
9168 #define I2C_OAR1_ADD2_Pos (2U)
9169 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
9170 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
9171 #define I2C_OAR1_ADD3_Pos (3U)
9172 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
9173 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
9174 #define I2C_OAR1_ADD4_Pos (4U)
9175 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
9176 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
9177 #define I2C_OAR1_ADD5_Pos (5U)
9178 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
9179 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
9180 #define I2C_OAR1_ADD6_Pos (6U)
9181 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
9182 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
9183 #define I2C_OAR1_ADD7_Pos (7U)
9184 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
9185 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
9186 #define I2C_OAR1_ADD8_Pos (8U)
9187 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
9188 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
9189 #define I2C_OAR1_ADD9_Pos (9U)
9190 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
9191 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
9192
9193 #define I2C_OAR1_ADDMODE_Pos (15U)
9194 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
9195 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
9196
9197 /******************* Bit definition for I2C_OAR2 register *******************/
9198 #define I2C_OAR2_ENDUAL_Pos (0U)
9199 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
9200 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
9201 #define I2C_OAR2_ADD2_Pos (1U)
9202 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
9203 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
9204
9205 /******************** Bit definition for I2C_DR register ********************/
9206 #define I2C_DR_DR_Pos (0U)
9207 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
9208 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
9209
9210 /******************* Bit definition for I2C_SR1 register ********************/
9211 #define I2C_SR1_SB_Pos (0U)
9212 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
9213 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
9214 #define I2C_SR1_ADDR_Pos (1U)
9215 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
9216 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
9217 #define I2C_SR1_BTF_Pos (2U)
9218 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
9219 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
9220 #define I2C_SR1_ADD10_Pos (3U)
9221 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
9222 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
9223 #define I2C_SR1_STOPF_Pos (4U)
9224 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
9225 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
9226 #define I2C_SR1_RXNE_Pos (6U)
9227 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
9228 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
9229 #define I2C_SR1_TXE_Pos (7U)
9230 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
9231 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
9232 #define I2C_SR1_BERR_Pos (8U)
9233 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
9234 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
9235 #define I2C_SR1_ARLO_Pos (9U)
9236 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
9237 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
9238 #define I2C_SR1_AF_Pos (10U)
9239 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
9240 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
9241 #define I2C_SR1_OVR_Pos (11U)
9242 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
9243 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
9244 #define I2C_SR1_PECERR_Pos (12U)
9245 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
9246 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
9247 #define I2C_SR1_TIMEOUT_Pos (14U)
9248 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
9249 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
9250 #define I2C_SR1_SMBALERT_Pos (15U)
9251 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
9252 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
9253
9254 /******************* Bit definition for I2C_SR2 register ********************/
9255 #define I2C_SR2_MSL_Pos (0U)
9256 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
9257 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
9258 #define I2C_SR2_BUSY_Pos (1U)
9259 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
9260 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
9261 #define I2C_SR2_TRA_Pos (2U)
9262 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
9263 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
9264 #define I2C_SR2_GENCALL_Pos (4U)
9265 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
9266 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
9267 #define I2C_SR2_SMBDEFAULT_Pos (5U)
9268 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
9269 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
9270 #define I2C_SR2_SMBHOST_Pos (6U)
9271 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
9272 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
9273 #define I2C_SR2_DUALF_Pos (7U)
9274 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
9275 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
9276 #define I2C_SR2_PEC_Pos (8U)
9277 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
9278 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
9279
9280 /******************* Bit definition for I2C_CCR register ********************/
9281 #define I2C_CCR_CCR_Pos (0U)
9282 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
9283 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
9284 #define I2C_CCR_DUTY_Pos (14U)
9285 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
9286 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
9287 #define I2C_CCR_FS_Pos (15U)
9288 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
9289 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
9290
9291 /****************** Bit definition for I2C_TRISE register *******************/
9292 #define I2C_TRISE_TRISE_Pos (0U)
9293 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
9294 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
9295
9296
9297 /******************************************************************************/
9298 /* */
9299 /* Independent WATCHDOG */
9300 /* */
9301 /******************************************************************************/
9302 /******************* Bit definition for IWDG_KR register ********************/
9303 #define IWDG_KR_KEY_Pos (0U)
9304 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
9305 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
9306
9307 /******************* Bit definition for IWDG_PR register ********************/
9308 #define IWDG_PR_PR_Pos (0U)
9309 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
9310 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
9311 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
9312 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
9313 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
9314
9315 /******************* Bit definition for IWDG_RLR register *******************/
9316 #define IWDG_RLR_RL_Pos (0U)
9317 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
9318 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
9319
9320 /******************* Bit definition for IWDG_SR register ********************/
9321 #define IWDG_SR_PVU_Pos (0U)
9322 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
9323 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
9324 #define IWDG_SR_RVU_Pos (1U)
9325 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
9326 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
9327
9328
9329
9330 /******************************************************************************/
9331 /* */
9332 /* Power Control */
9333 /* */
9334 /******************************************************************************/
9335 /******************** Bit definition for PWR_CR register ********************/
9336 #define PWR_CR_LPDS_Pos (0U)
9337 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
9338 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
9339 #define PWR_CR_PDDS_Pos (1U)
9340 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
9341 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
9342 #define PWR_CR_CWUF_Pos (2U)
9343 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
9344 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
9345 #define PWR_CR_CSBF_Pos (3U)
9346 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
9347 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
9348 #define PWR_CR_PVDE_Pos (4U)
9349 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
9350 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
9351
9352 #define PWR_CR_PLS_Pos (5U)
9353 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
9354 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
9355 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
9356 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
9357 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
9358
9359 /*!< PVD level configuration */
9360 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
9361 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
9362 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
9363 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
9364 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
9365 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
9366 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
9367 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
9368 #define PWR_CR_DBP_Pos (8U)
9369 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
9370 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
9371 #define PWR_CR_FPDS_Pos (9U)
9372 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
9373 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
9374 #define PWR_CR_VOS_Pos (14U)
9375 #define PWR_CR_VOS_Msk (0x1U << PWR_CR_VOS_Pos) /*!< 0x00004000 */
9376 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS bit (Regulator voltage scaling output selection) */
9377
9378 /* Legacy define */
9379 #define PWR_CR_PMODE PWR_CR_VOS
9380
9381 /******************* Bit definition for PWR_CSR register ********************/
9382 #define PWR_CSR_WUF_Pos (0U)
9383 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
9384 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
9385 #define PWR_CSR_SBF_Pos (1U)
9386 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
9387 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
9388 #define PWR_CSR_PVDO_Pos (2U)
9389 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
9390 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
9391 #define PWR_CSR_BRR_Pos (3U)
9392 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
9393 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
9394 #define PWR_CSR_EWUP_Pos (8U)
9395 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
9396 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
9397 #define PWR_CSR_BRE_Pos (9U)
9398 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
9399 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
9400 #define PWR_CSR_VOSRDY_Pos (14U)
9401 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
9402 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
9403
9404 /* Legacy define */
9405 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
9406
9407 /******************************************************************************/
9408 /* */
9409 /* Reset and Clock Control */
9410 /* */
9411 /******************************************************************************/
9412 /******************** Bit definition for RCC_CR register ********************/
9413 #define RCC_CR_HSION_Pos (0U)
9414 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
9415 #define RCC_CR_HSION RCC_CR_HSION_Msk
9416 #define RCC_CR_HSIRDY_Pos (1U)
9417 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
9418 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9419
9420 #define RCC_CR_HSITRIM_Pos (3U)
9421 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
9422 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9423 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
9424 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
9425 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
9426 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
9427 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
9428
9429 #define RCC_CR_HSICAL_Pos (8U)
9430 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
9431 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9432 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
9433 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
9434 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
9435 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
9436 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
9437 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
9438 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
9439 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
9440
9441 #define RCC_CR_HSEON_Pos (16U)
9442 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
9443 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
9444 #define RCC_CR_HSERDY_Pos (17U)
9445 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
9446 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9447 #define RCC_CR_HSEBYP_Pos (18U)
9448 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
9449 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9450 #define RCC_CR_CSSON_Pos (19U)
9451 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
9452 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
9453 #define RCC_CR_PLLON_Pos (24U)
9454 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
9455 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
9456 #define RCC_CR_PLLRDY_Pos (25U)
9457 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
9458 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9459 /*
9460 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9461 */
9462 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
9463
9464 #define RCC_CR_PLLI2SON_Pos (26U)
9465 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
9466 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9467 #define RCC_CR_PLLI2SRDY_Pos (27U)
9468 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
9469 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9470
9471 /******************** Bit definition for RCC_PLLCFGR register ***************/
9472 #define RCC_PLLCFGR_PLLM_Pos (0U)
9473 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
9474 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9475 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
9476 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
9477 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
9478 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
9479 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
9480 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
9481
9482 #define RCC_PLLCFGR_PLLN_Pos (6U)
9483 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
9484 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9485 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
9486 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
9487 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
9488 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
9489 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
9490 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
9491 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
9492 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
9493 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
9494
9495 #define RCC_PLLCFGR_PLLP_Pos (16U)
9496 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
9497 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9498 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
9499 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
9500
9501 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
9502 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
9503 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9504 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9505 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
9506 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9507 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9508
9509 #define RCC_PLLCFGR_PLLQ_Pos (24U)
9510 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
9511 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9512 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
9513 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
9514 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
9515 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
9516
9517
9518 /******************** Bit definition for RCC_CFGR register ******************/
9519 /*!< SW configuration */
9520 #define RCC_CFGR_SW_Pos (0U)
9521 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
9522 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
9523 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
9524 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
9525
9526 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
9527 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
9528 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
9529
9530 /*!< SWS configuration */
9531 #define RCC_CFGR_SWS_Pos (2U)
9532 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
9533 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
9534 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
9535 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
9536
9537 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
9538 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
9539 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
9540
9541 /*!< HPRE configuration */
9542 #define RCC_CFGR_HPRE_Pos (4U)
9543 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
9544 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
9545 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
9546 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
9547 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
9548 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
9549
9550 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
9551 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
9552 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
9553 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
9554 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
9555 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
9556 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
9557 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
9558 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
9559
9560 /*!< PPRE1 configuration */
9561 #define RCC_CFGR_PPRE1_Pos (10U)
9562 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
9563 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
9564 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
9565 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
9566 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
9567
9568 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
9569 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
9570 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
9571 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
9572 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
9573
9574 /*!< PPRE2 configuration */
9575 #define RCC_CFGR_PPRE2_Pos (13U)
9576 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
9577 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
9578 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
9579 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
9580 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
9581
9582 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
9583 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
9584 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
9585 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
9586 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
9587
9588 /*!< RTCPRE configuration */
9589 #define RCC_CFGR_RTCPRE_Pos (16U)
9590 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
9591 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9592 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
9593 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
9594 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
9595 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
9596 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
9597
9598 /*!< MCO1 configuration */
9599 #define RCC_CFGR_MCO1_Pos (21U)
9600 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
9601 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9602 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
9603 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
9604
9605 #define RCC_CFGR_I2SSRC_Pos (23U)
9606 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
9607 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
9608
9609 #define RCC_CFGR_MCO1PRE_Pos (24U)
9610 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
9611 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9612 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
9613 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
9614 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
9615
9616 #define RCC_CFGR_MCO2PRE_Pos (27U)
9617 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
9618 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9619 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
9620 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
9621 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
9622
9623 #define RCC_CFGR_MCO2_Pos (30U)
9624 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
9625 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9626 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
9627 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
9628
9629 /******************** Bit definition for RCC_CIR register *******************/
9630 #define RCC_CIR_LSIRDYF_Pos (0U)
9631 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
9632 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9633 #define RCC_CIR_LSERDYF_Pos (1U)
9634 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
9635 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9636 #define RCC_CIR_HSIRDYF_Pos (2U)
9637 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
9638 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9639 #define RCC_CIR_HSERDYF_Pos (3U)
9640 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
9641 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9642 #define RCC_CIR_PLLRDYF_Pos (4U)
9643 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
9644 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9645 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
9646 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
9647 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9648
9649 #define RCC_CIR_CSSF_Pos (7U)
9650 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
9651 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9652 #define RCC_CIR_LSIRDYIE_Pos (8U)
9653 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
9654 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9655 #define RCC_CIR_LSERDYIE_Pos (9U)
9656 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
9657 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9658 #define RCC_CIR_HSIRDYIE_Pos (10U)
9659 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
9660 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9661 #define RCC_CIR_HSERDYIE_Pos (11U)
9662 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
9663 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9664 #define RCC_CIR_PLLRDYIE_Pos (12U)
9665 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
9666 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9667 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9668 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
9669 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9670
9671 #define RCC_CIR_LSIRDYC_Pos (16U)
9672 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
9673 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9674 #define RCC_CIR_LSERDYC_Pos (17U)
9675 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
9676 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9677 #define RCC_CIR_HSIRDYC_Pos (18U)
9678 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
9679 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9680 #define RCC_CIR_HSERDYC_Pos (19U)
9681 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
9682 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9683 #define RCC_CIR_PLLRDYC_Pos (20U)
9684 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
9685 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9686 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
9687 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
9688 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9689
9690 #define RCC_CIR_CSSC_Pos (23U)
9691 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
9692 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9693
9694 /******************** Bit definition for RCC_AHB1RSTR register **************/
9695 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9696 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
9697 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9698 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9699 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
9700 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9701 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9702 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
9703 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9704 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9705 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
9706 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9707 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9708 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
9709 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9710 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9711 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
9712 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9713 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9714 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
9715 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9716 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9717 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
9718 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9719 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
9720 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
9721 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
9722 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
9723 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
9724 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9725 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9726 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
9727 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9728 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9729 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
9730 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9731 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
9732 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
9733 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
9734
9735 /******************** Bit definition for RCC_AHB2RSTR register **************/
9736 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
9737 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
9738 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
9739 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
9740 #define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
9741 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
9742 /* maintained for legacy purpose */
9743 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
9744 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
9745 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
9746 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9747 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9748 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
9749 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9750 /******************** Bit definition for RCC_AHB3RSTR register **************/
9751 #define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9752 #define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
9753 #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9754
9755
9756 /******************** Bit definition for RCC_APB1RSTR register **************/
9757 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
9758 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
9759 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9760 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
9761 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
9762 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9763 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
9764 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
9765 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9766 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
9767 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
9768 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9769 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
9770 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
9771 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9772 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
9773 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
9774 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9775 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
9776 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
9777 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9778 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
9779 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
9780 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9781 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
9782 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
9783 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9784 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
9785 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
9786 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9787 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
9788 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
9789 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9790 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
9791 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
9792 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9793 #define RCC_APB1RSTR_USART2RST_Pos (17U)
9794 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
9795 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9796 #define RCC_APB1RSTR_USART3RST_Pos (18U)
9797 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
9798 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9799 #define RCC_APB1RSTR_UART4RST_Pos (19U)
9800 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
9801 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9802 #define RCC_APB1RSTR_UART5RST_Pos (20U)
9803 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
9804 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9805 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
9806 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
9807 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9808 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
9809 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
9810 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9811 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
9812 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
9813 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9814 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
9815 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
9816 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9817 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
9818 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
9819 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9820 #define RCC_APB1RSTR_PWRRST_Pos (28U)
9821 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
9822 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9823 #define RCC_APB1RSTR_DACRST_Pos (29U)
9824 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
9825 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9826
9827 /******************** Bit definition for RCC_APB2RSTR register **************/
9828 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
9829 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
9830 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9831 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
9832 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
9833 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9834 #define RCC_APB2RSTR_USART1RST_Pos (4U)
9835 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
9836 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9837 #define RCC_APB2RSTR_USART6RST_Pos (5U)
9838 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
9839 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9840 #define RCC_APB2RSTR_ADCRST_Pos (8U)
9841 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
9842 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9843 #define RCC_APB2RSTR_SDIORST_Pos (11U)
9844 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
9845 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9846 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
9847 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
9848 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9849 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9850 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
9851 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9852 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
9853 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
9854 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9855 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
9856 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
9857 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9858 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
9859 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
9860 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9861
9862 /* Old SPI1RST bit definition, maintained for legacy purpose */
9863 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
9864
9865 /******************** Bit definition for RCC_AHB1ENR register ***************/
9866 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9867 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
9868 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9869 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9870 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
9871 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9872 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9873 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
9874 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9875 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
9876 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
9877 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9878 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9879 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
9880 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9881 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9882 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
9883 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
9884 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
9885 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
9886 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
9887 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9888 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
9889 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9890 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
9891 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
9892 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
9893 #define RCC_AHB1ENR_CRCEN_Pos (12U)
9894 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
9895 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9896 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
9897 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
9898 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
9899 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
9900 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
9901 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
9902 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
9903 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
9904 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9905 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
9906 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
9907 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9908 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
9909 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
9910 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
9911 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
9912 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
9913 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
9914 /******************** Bit definition for RCC_AHB2ENR register ***************/
9915 /*
9916 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9917 */
9918 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
9919
9920 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
9921 #define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
9922 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
9923 #define RCC_AHB2ENR_HASHEN_Pos (5U)
9924 #define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
9925 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
9926 #define RCC_AHB2ENR_RNGEN_Pos (6U)
9927 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
9928 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9929 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9930 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
9931 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9932
9933 /******************** Bit definition for RCC_AHB3ENR register ***************/
9934 /*
9935 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9936 */
9937 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
9938
9939 #define RCC_AHB3ENR_FSMCEN_Pos (0U)
9940 #define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
9941 #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
9942
9943 /******************** Bit definition for RCC_APB1ENR register ***************/
9944 #define RCC_APB1ENR_TIM2EN_Pos (0U)
9945 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
9946 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
9947 #define RCC_APB1ENR_TIM3EN_Pos (1U)
9948 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
9949 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
9950 #define RCC_APB1ENR_TIM4EN_Pos (2U)
9951 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
9952 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
9953 #define RCC_APB1ENR_TIM5EN_Pos (3U)
9954 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
9955 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
9956 #define RCC_APB1ENR_TIM6EN_Pos (4U)
9957 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
9958 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
9959 #define RCC_APB1ENR_TIM7EN_Pos (5U)
9960 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
9961 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
9962 #define RCC_APB1ENR_TIM12EN_Pos (6U)
9963 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
9964 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
9965 #define RCC_APB1ENR_TIM13EN_Pos (7U)
9966 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
9967 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
9968 #define RCC_APB1ENR_TIM14EN_Pos (8U)
9969 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
9970 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
9971 #define RCC_APB1ENR_WWDGEN_Pos (11U)
9972 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
9973 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
9974 #define RCC_APB1ENR_SPI2EN_Pos (14U)
9975 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
9976 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
9977 #define RCC_APB1ENR_SPI3EN_Pos (15U)
9978 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
9979 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
9980 #define RCC_APB1ENR_USART2EN_Pos (17U)
9981 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
9982 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
9983 #define RCC_APB1ENR_USART3EN_Pos (18U)
9984 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
9985 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
9986 #define RCC_APB1ENR_UART4EN_Pos (19U)
9987 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
9988 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
9989 #define RCC_APB1ENR_UART5EN_Pos (20U)
9990 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
9991 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
9992 #define RCC_APB1ENR_I2C1EN_Pos (21U)
9993 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
9994 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
9995 #define RCC_APB1ENR_I2C2EN_Pos (22U)
9996 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
9997 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
9998 #define RCC_APB1ENR_I2C3EN_Pos (23U)
9999 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
10000 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
10001 #define RCC_APB1ENR_CAN1EN_Pos (25U)
10002 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
10003 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
10004 #define RCC_APB1ENR_CAN2EN_Pos (26U)
10005 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
10006 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
10007 #define RCC_APB1ENR_PWREN_Pos (28U)
10008 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
10009 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
10010 #define RCC_APB1ENR_DACEN_Pos (29U)
10011 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
10012 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
10013
10014 /******************** Bit definition for RCC_APB2ENR register ***************/
10015 #define RCC_APB2ENR_TIM1EN_Pos (0U)
10016 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
10017 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10018 #define RCC_APB2ENR_TIM8EN_Pos (1U)
10019 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
10020 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
10021 #define RCC_APB2ENR_USART1EN_Pos (4U)
10022 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
10023 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10024 #define RCC_APB2ENR_USART6EN_Pos (5U)
10025 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
10026 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
10027 #define RCC_APB2ENR_ADC1EN_Pos (8U)
10028 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
10029 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
10030 #define RCC_APB2ENR_ADC2EN_Pos (9U)
10031 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
10032 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
10033 #define RCC_APB2ENR_ADC3EN_Pos (10U)
10034 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
10035 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
10036 #define RCC_APB2ENR_SDIOEN_Pos (11U)
10037 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
10038 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
10039 #define RCC_APB2ENR_SPI1EN_Pos (12U)
10040 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
10041 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10042 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
10043 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
10044 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10045 #define RCC_APB2ENR_TIM9EN_Pos (16U)
10046 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
10047 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
10048 #define RCC_APB2ENR_TIM10EN_Pos (17U)
10049 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
10050 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
10051 #define RCC_APB2ENR_TIM11EN_Pos (18U)
10052 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
10053 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
10054
10055 /******************** Bit definition for RCC_AHB1LPENR register *************/
10056 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
10057 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
10058 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
10059 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
10060 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
10061 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
10062 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
10063 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
10064 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
10065 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
10066 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
10067 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
10068 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
10069 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
10070 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
10071 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
10072 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
10073 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
10074 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
10075 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
10076 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
10077 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
10078 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
10079 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
10080 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
10081 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
10082 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
10083 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
10084 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
10085 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
10086 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
10087 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
10088 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
10089 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
10090 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
10091 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
10092 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
10093 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
10094 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
10095 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
10096 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
10097 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
10098 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
10099 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
10100 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
10101 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
10102 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
10103 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
10104
10105 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
10106 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
10107 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
10108 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
10109 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
10110 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
10111
10112 /******************** Bit definition for RCC_AHB2LPENR register *************/
10113 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
10114 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
10115 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
10116 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
10117 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
10118 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
10119 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
10120 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
10121 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
10122 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
10123 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
10124 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
10125
10126 /******************** Bit definition for RCC_AHB3LPENR register *************/
10127 #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
10128 #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
10129 #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
10130
10131 /******************** Bit definition for RCC_APB1LPENR register *************/
10132 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
10133 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
10134 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
10135 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
10136 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
10137 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
10138 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
10139 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
10140 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
10141 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
10142 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
10143 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
10144 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
10145 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
10146 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
10147 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
10148 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
10149 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
10150 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
10151 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
10152 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
10153 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
10154 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
10155 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
10156 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
10157 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
10158 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
10159 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
10160 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
10161 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
10162 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
10163 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
10164 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
10165 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
10166 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
10167 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
10168 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
10169 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
10170 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
10171 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
10172 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
10173 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
10174 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
10175 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
10176 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
10177 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
10178 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
10179 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
10180 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
10181 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
10182 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
10183 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
10184 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
10185 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
10186 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
10187 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
10188 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
10189 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10190 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
10191 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10192 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10193 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
10194 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10195 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10196 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
10197 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10198 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
10199 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
10200 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10201
10202 /******************** Bit definition for RCC_APB2LPENR register *************/
10203 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10204 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
10205 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10206 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10207 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
10208 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10209 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10210 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
10211 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10212 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10213 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
10214 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10215 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10216 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
10217 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10218 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
10219 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
10220 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
10221 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
10222 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
10223 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
10224 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
10225 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
10226 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
10227 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10228 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
10229 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10230 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10231 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
10232 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10233 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10234 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
10235 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10236 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10237 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
10238 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10239 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10240 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
10241 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10242
10243 /******************** Bit definition for RCC_BDCR register ******************/
10244 #define RCC_BDCR_LSEON_Pos (0U)
10245 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
10246 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10247 #define RCC_BDCR_LSERDY_Pos (1U)
10248 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
10249 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10250 #define RCC_BDCR_LSEBYP_Pos (2U)
10251 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
10252 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10253
10254 #define RCC_BDCR_RTCSEL_Pos (8U)
10255 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
10256 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10257 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
10258 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
10259
10260 #define RCC_BDCR_RTCEN_Pos (15U)
10261 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
10262 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10263 #define RCC_BDCR_BDRST_Pos (16U)
10264 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
10265 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10266
10267 /******************** Bit definition for RCC_CSR register *******************/
10268 #define RCC_CSR_LSION_Pos (0U)
10269 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
10270 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
10271 #define RCC_CSR_LSIRDY_Pos (1U)
10272 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
10273 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10274 #define RCC_CSR_RMVF_Pos (24U)
10275 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
10276 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10277 #define RCC_CSR_BORRSTF_Pos (25U)
10278 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
10279 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10280 #define RCC_CSR_PINRSTF_Pos (26U)
10281 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
10282 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10283 #define RCC_CSR_PORRSTF_Pos (27U)
10284 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
10285 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10286 #define RCC_CSR_SFTRSTF_Pos (28U)
10287 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
10288 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10289 #define RCC_CSR_IWDGRSTF_Pos (29U)
10290 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
10291 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10292 #define RCC_CSR_WWDGRSTF_Pos (30U)
10293 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
10294 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10295 #define RCC_CSR_LPWRRSTF_Pos (31U)
10296 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
10297 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10298 /* Legacy defines */
10299 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10300 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10301
10302 /******************** Bit definition for RCC_SSCGR register *****************/
10303 #define RCC_SSCGR_MODPER_Pos (0U)
10304 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
10305 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10306 #define RCC_SSCGR_INCSTEP_Pos (13U)
10307 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
10308 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10309 #define RCC_SSCGR_SPREADSEL_Pos (30U)
10310 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
10311 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10312 #define RCC_SSCGR_SSCGEN_Pos (31U)
10313 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
10314 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10315
10316 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
10317 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10318 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
10319 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10320 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
10321 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
10322 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
10323 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
10324 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
10325 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
10326 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
10327 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
10328 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
10329
10330 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10331 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
10332 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10333 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
10334 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
10335 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
10336
10337
10338 /******************************************************************************/
10339 /* */
10340 /* RNG */
10341 /* */
10342 /******************************************************************************/
10343 /******************** Bits definition for RNG_CR register *******************/
10344 #define RNG_CR_RNGEN_Pos (2U)
10345 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
10346 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10347 #define RNG_CR_IE_Pos (3U)
10348 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
10349 #define RNG_CR_IE RNG_CR_IE_Msk
10350
10351 /******************** Bits definition for RNG_SR register *******************/
10352 #define RNG_SR_DRDY_Pos (0U)
10353 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
10354 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
10355 #define RNG_SR_CECS_Pos (1U)
10356 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
10357 #define RNG_SR_CECS RNG_SR_CECS_Msk
10358 #define RNG_SR_SECS_Pos (2U)
10359 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
10360 #define RNG_SR_SECS RNG_SR_SECS_Msk
10361 #define RNG_SR_CEIS_Pos (5U)
10362 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
10363 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
10364 #define RNG_SR_SEIS_Pos (6U)
10365 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
10366 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
10367
10368 /******************************************************************************/
10369 /* */
10370 /* Real-Time Clock (RTC) */
10371 /* */
10372 /******************************************************************************/
10373 /*
10374 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10375 */
10376 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
10377 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
10378 /******************** Bits definition for RTC_TR register *******************/
10379 #define RTC_TR_PM_Pos (22U)
10380 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
10381 #define RTC_TR_PM RTC_TR_PM_Msk
10382 #define RTC_TR_HT_Pos (20U)
10383 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
10384 #define RTC_TR_HT RTC_TR_HT_Msk
10385 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
10386 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
10387 #define RTC_TR_HU_Pos (16U)
10388 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
10389 #define RTC_TR_HU RTC_TR_HU_Msk
10390 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
10391 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
10392 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
10393 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
10394 #define RTC_TR_MNT_Pos (12U)
10395 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
10396 #define RTC_TR_MNT RTC_TR_MNT_Msk
10397 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
10398 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
10399 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
10400 #define RTC_TR_MNU_Pos (8U)
10401 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
10402 #define RTC_TR_MNU RTC_TR_MNU_Msk
10403 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
10404 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
10405 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
10406 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
10407 #define RTC_TR_ST_Pos (4U)
10408 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
10409 #define RTC_TR_ST RTC_TR_ST_Msk
10410 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
10411 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
10412 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
10413 #define RTC_TR_SU_Pos (0U)
10414 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
10415 #define RTC_TR_SU RTC_TR_SU_Msk
10416 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
10417 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
10418 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
10419 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
10420
10421 /******************** Bits definition for RTC_DR register *******************/
10422 #define RTC_DR_YT_Pos (20U)
10423 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
10424 #define RTC_DR_YT RTC_DR_YT_Msk
10425 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
10426 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
10427 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
10428 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
10429 #define RTC_DR_YU_Pos (16U)
10430 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
10431 #define RTC_DR_YU RTC_DR_YU_Msk
10432 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
10433 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
10434 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
10435 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
10436 #define RTC_DR_WDU_Pos (13U)
10437 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
10438 #define RTC_DR_WDU RTC_DR_WDU_Msk
10439 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
10440 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
10441 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
10442 #define RTC_DR_MT_Pos (12U)
10443 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
10444 #define RTC_DR_MT RTC_DR_MT_Msk
10445 #define RTC_DR_MU_Pos (8U)
10446 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
10447 #define RTC_DR_MU RTC_DR_MU_Msk
10448 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
10449 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
10450 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
10451 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
10452 #define RTC_DR_DT_Pos (4U)
10453 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
10454 #define RTC_DR_DT RTC_DR_DT_Msk
10455 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
10456 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
10457 #define RTC_DR_DU_Pos (0U)
10458 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
10459 #define RTC_DR_DU RTC_DR_DU_Msk
10460 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
10461 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
10462 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
10463 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
10464
10465 /******************** Bits definition for RTC_CR register *******************/
10466 #define RTC_CR_COE_Pos (23U)
10467 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
10468 #define RTC_CR_COE RTC_CR_COE_Msk
10469 #define RTC_CR_OSEL_Pos (21U)
10470 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
10471 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
10472 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
10473 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
10474 #define RTC_CR_POL_Pos (20U)
10475 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
10476 #define RTC_CR_POL RTC_CR_POL_Msk
10477 #define RTC_CR_COSEL_Pos (19U)
10478 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
10479 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
10480 #define RTC_CR_BKP_Pos (18U)
10481 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
10482 #define RTC_CR_BKP RTC_CR_BKP_Msk
10483 #define RTC_CR_SUB1H_Pos (17U)
10484 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
10485 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10486 #define RTC_CR_ADD1H_Pos (16U)
10487 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
10488 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10489 #define RTC_CR_TSIE_Pos (15U)
10490 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
10491 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
10492 #define RTC_CR_WUTIE_Pos (14U)
10493 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
10494 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10495 #define RTC_CR_ALRBIE_Pos (13U)
10496 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
10497 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10498 #define RTC_CR_ALRAIE_Pos (12U)
10499 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
10500 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10501 #define RTC_CR_TSE_Pos (11U)
10502 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
10503 #define RTC_CR_TSE RTC_CR_TSE_Msk
10504 #define RTC_CR_WUTE_Pos (10U)
10505 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
10506 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
10507 #define RTC_CR_ALRBE_Pos (9U)
10508 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
10509 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10510 #define RTC_CR_ALRAE_Pos (8U)
10511 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
10512 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10513 #define RTC_CR_DCE_Pos (7U)
10514 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
10515 #define RTC_CR_DCE RTC_CR_DCE_Msk
10516 #define RTC_CR_FMT_Pos (6U)
10517 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
10518 #define RTC_CR_FMT RTC_CR_FMT_Msk
10519 #define RTC_CR_BYPSHAD_Pos (5U)
10520 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
10521 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10522 #define RTC_CR_REFCKON_Pos (4U)
10523 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
10524 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10525 #define RTC_CR_TSEDGE_Pos (3U)
10526 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
10527 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10528 #define RTC_CR_WUCKSEL_Pos (0U)
10529 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
10530 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10531 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
10532 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
10533 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
10534
10535 /* Legacy defines */
10536 #define RTC_CR_BCK RTC_CR_BKP
10537
10538 /******************** Bits definition for RTC_ISR register ******************/
10539 #define RTC_ISR_RECALPF_Pos (16U)
10540 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
10541 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10542 #define RTC_ISR_TAMP1F_Pos (13U)
10543 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
10544 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10545 #define RTC_ISR_TAMP2F_Pos (14U)
10546 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
10547 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10548 #define RTC_ISR_TSOVF_Pos (12U)
10549 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
10550 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10551 #define RTC_ISR_TSF_Pos (11U)
10552 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
10553 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
10554 #define RTC_ISR_WUTF_Pos (10U)
10555 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
10556 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10557 #define RTC_ISR_ALRBF_Pos (9U)
10558 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
10559 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10560 #define RTC_ISR_ALRAF_Pos (8U)
10561 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
10562 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10563 #define RTC_ISR_INIT_Pos (7U)
10564 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
10565 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
10566 #define RTC_ISR_INITF_Pos (6U)
10567 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
10568 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
10569 #define RTC_ISR_RSF_Pos (5U)
10570 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
10571 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
10572 #define RTC_ISR_INITS_Pos (4U)
10573 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
10574 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
10575 #define RTC_ISR_SHPF_Pos (3U)
10576 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
10577 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10578 #define RTC_ISR_WUTWF_Pos (2U)
10579 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
10580 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10581 #define RTC_ISR_ALRBWF_Pos (1U)
10582 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
10583 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10584 #define RTC_ISR_ALRAWF_Pos (0U)
10585 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
10586 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10587
10588 /******************** Bits definition for RTC_PRER register *****************/
10589 #define RTC_PRER_PREDIV_A_Pos (16U)
10590 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
10591 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10592 #define RTC_PRER_PREDIV_S_Pos (0U)
10593 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
10594 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10595
10596 /******************** Bits definition for RTC_WUTR register *****************/
10597 #define RTC_WUTR_WUT_Pos (0U)
10598 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
10599 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10600
10601 /******************** Bits definition for RTC_CALIBR register ***************/
10602 #define RTC_CALIBR_DCS_Pos (7U)
10603 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
10604 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10605 #define RTC_CALIBR_DC_Pos (0U)
10606 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
10607 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10608
10609 /******************** Bits definition for RTC_ALRMAR register ***************/
10610 #define RTC_ALRMAR_MSK4_Pos (31U)
10611 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
10612 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10613 #define RTC_ALRMAR_WDSEL_Pos (30U)
10614 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
10615 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10616 #define RTC_ALRMAR_DT_Pos (28U)
10617 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
10618 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10619 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
10620 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
10621 #define RTC_ALRMAR_DU_Pos (24U)
10622 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
10623 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10624 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
10625 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
10626 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
10627 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
10628 #define RTC_ALRMAR_MSK3_Pos (23U)
10629 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
10630 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10631 #define RTC_ALRMAR_PM_Pos (22U)
10632 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
10633 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10634 #define RTC_ALRMAR_HT_Pos (20U)
10635 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
10636 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10637 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
10638 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
10639 #define RTC_ALRMAR_HU_Pos (16U)
10640 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
10641 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10642 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
10643 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
10644 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
10645 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
10646 #define RTC_ALRMAR_MSK2_Pos (15U)
10647 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
10648 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10649 #define RTC_ALRMAR_MNT_Pos (12U)
10650 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
10651 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10652 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
10653 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
10654 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
10655 #define RTC_ALRMAR_MNU_Pos (8U)
10656 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
10657 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10658 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
10659 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
10660 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
10661 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
10662 #define RTC_ALRMAR_MSK1_Pos (7U)
10663 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
10664 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10665 #define RTC_ALRMAR_ST_Pos (4U)
10666 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
10667 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10668 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
10669 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
10670 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
10671 #define RTC_ALRMAR_SU_Pos (0U)
10672 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
10673 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10674 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
10675 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
10676 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
10677 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
10678
10679 /******************** Bits definition for RTC_ALRMBR register ***************/
10680 #define RTC_ALRMBR_MSK4_Pos (31U)
10681 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
10682 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10683 #define RTC_ALRMBR_WDSEL_Pos (30U)
10684 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
10685 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10686 #define RTC_ALRMBR_DT_Pos (28U)
10687 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
10688 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10689 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
10690 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
10691 #define RTC_ALRMBR_DU_Pos (24U)
10692 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
10693 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10694 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
10695 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
10696 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
10697 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
10698 #define RTC_ALRMBR_MSK3_Pos (23U)
10699 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
10700 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10701 #define RTC_ALRMBR_PM_Pos (22U)
10702 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
10703 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10704 #define RTC_ALRMBR_HT_Pos (20U)
10705 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
10706 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10707 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
10708 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
10709 #define RTC_ALRMBR_HU_Pos (16U)
10710 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
10711 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10712 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
10713 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
10714 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
10715 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
10716 #define RTC_ALRMBR_MSK2_Pos (15U)
10717 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
10718 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10719 #define RTC_ALRMBR_MNT_Pos (12U)
10720 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
10721 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10722 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
10723 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
10724 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
10725 #define RTC_ALRMBR_MNU_Pos (8U)
10726 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
10727 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10728 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
10729 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
10730 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
10731 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
10732 #define RTC_ALRMBR_MSK1_Pos (7U)
10733 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
10734 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10735 #define RTC_ALRMBR_ST_Pos (4U)
10736 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
10737 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10738 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
10739 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
10740 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
10741 #define RTC_ALRMBR_SU_Pos (0U)
10742 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
10743 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10744 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
10745 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
10746 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
10747 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
10748
10749 /******************** Bits definition for RTC_WPR register ******************/
10750 #define RTC_WPR_KEY_Pos (0U)
10751 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
10752 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
10753
10754 /******************** Bits definition for RTC_SSR register ******************/
10755 #define RTC_SSR_SS_Pos (0U)
10756 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
10757 #define RTC_SSR_SS RTC_SSR_SS_Msk
10758
10759 /******************** Bits definition for RTC_SHIFTR register ***************/
10760 #define RTC_SHIFTR_SUBFS_Pos (0U)
10761 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
10762 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10763 #define RTC_SHIFTR_ADD1S_Pos (31U)
10764 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
10765 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10766
10767 /******************** Bits definition for RTC_TSTR register *****************/
10768 #define RTC_TSTR_PM_Pos (22U)
10769 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
10770 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
10771 #define RTC_TSTR_HT_Pos (20U)
10772 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
10773 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
10774 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
10775 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
10776 #define RTC_TSTR_HU_Pos (16U)
10777 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
10778 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
10779 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
10780 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
10781 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
10782 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
10783 #define RTC_TSTR_MNT_Pos (12U)
10784 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
10785 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10786 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
10787 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
10788 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
10789 #define RTC_TSTR_MNU_Pos (8U)
10790 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
10791 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10792 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
10793 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
10794 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
10795 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
10796 #define RTC_TSTR_ST_Pos (4U)
10797 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
10798 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
10799 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
10800 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
10801 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
10802 #define RTC_TSTR_SU_Pos (0U)
10803 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
10804 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
10805 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
10806 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
10807 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
10808 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
10809
10810 /******************** Bits definition for RTC_TSDR register *****************/
10811 #define RTC_TSDR_WDU_Pos (13U)
10812 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
10813 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10814 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
10815 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
10816 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
10817 #define RTC_TSDR_MT_Pos (12U)
10818 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
10819 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
10820 #define RTC_TSDR_MU_Pos (8U)
10821 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
10822 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
10823 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
10824 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
10825 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
10826 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
10827 #define RTC_TSDR_DT_Pos (4U)
10828 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
10829 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
10830 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
10831 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
10832 #define RTC_TSDR_DU_Pos (0U)
10833 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
10834 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
10835 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
10836 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
10837 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
10838 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
10839
10840 /******************** Bits definition for RTC_TSSSR register ****************/
10841 #define RTC_TSSSR_SS_Pos (0U)
10842 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
10843 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10844
10845 /******************** Bits definition for RTC_CAL register *****************/
10846 #define RTC_CALR_CALP_Pos (15U)
10847 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
10848 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
10849 #define RTC_CALR_CALW8_Pos (14U)
10850 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
10851 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10852 #define RTC_CALR_CALW16_Pos (13U)
10853 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
10854 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10855 #define RTC_CALR_CALM_Pos (0U)
10856 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
10857 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
10858 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
10859 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
10860 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
10861 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
10862 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
10863 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
10864 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
10865 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
10866 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
10867
10868 /******************** Bits definition for RTC_TAFCR register ****************/
10869 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
10870 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
10871 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
10872 #define RTC_TAFCR_TSINSEL_Pos (17U)
10873 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
10874 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
10875 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
10876 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
10877 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
10878 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
10879 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
10880 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
10881 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
10882 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
10883 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
10884 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
10885 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
10886 #define RTC_TAFCR_TAMPFLT_Pos (11U)
10887 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
10888 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
10889 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
10890 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
10891 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
10892 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
10893 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
10894 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
10895 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
10896 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
10897 #define RTC_TAFCR_TAMPTS_Pos (7U)
10898 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
10899 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
10900 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
10901 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
10902 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
10903 #define RTC_TAFCR_TAMP2E_Pos (3U)
10904 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
10905 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
10906 #define RTC_TAFCR_TAMPIE_Pos (2U)
10907 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
10908 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
10909 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
10910 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
10911 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
10912 #define RTC_TAFCR_TAMP1E_Pos (0U)
10913 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
10914 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
10915
10916 /* Legacy defines */
10917 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
10918
10919 /******************** Bits definition for RTC_ALRMASSR register *************/
10920 #define RTC_ALRMASSR_MASKSS_Pos (24U)
10921 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
10922 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10923 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
10924 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
10925 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
10926 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
10927 #define RTC_ALRMASSR_SS_Pos (0U)
10928 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
10929 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10930
10931 /******************** Bits definition for RTC_ALRMBSSR register *************/
10932 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
10933 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
10934 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
10935 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
10936 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
10937 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
10938 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
10939 #define RTC_ALRMBSSR_SS_Pos (0U)
10940 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
10941 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
10942
10943 /******************** Bits definition for RTC_BKP0R register ****************/
10944 #define RTC_BKP0R_Pos (0U)
10945 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
10946 #define RTC_BKP0R RTC_BKP0R_Msk
10947
10948 /******************** Bits definition for RTC_BKP1R register ****************/
10949 #define RTC_BKP1R_Pos (0U)
10950 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
10951 #define RTC_BKP1R RTC_BKP1R_Msk
10952
10953 /******************** Bits definition for RTC_BKP2R register ****************/
10954 #define RTC_BKP2R_Pos (0U)
10955 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
10956 #define RTC_BKP2R RTC_BKP2R_Msk
10957
10958 /******************** Bits definition for RTC_BKP3R register ****************/
10959 #define RTC_BKP3R_Pos (0U)
10960 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
10961 #define RTC_BKP3R RTC_BKP3R_Msk
10962
10963 /******************** Bits definition for RTC_BKP4R register ****************/
10964 #define RTC_BKP4R_Pos (0U)
10965 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
10966 #define RTC_BKP4R RTC_BKP4R_Msk
10967
10968 /******************** Bits definition for RTC_BKP5R register ****************/
10969 #define RTC_BKP5R_Pos (0U)
10970 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
10971 #define RTC_BKP5R RTC_BKP5R_Msk
10972
10973 /******************** Bits definition for RTC_BKP6R register ****************/
10974 #define RTC_BKP6R_Pos (0U)
10975 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
10976 #define RTC_BKP6R RTC_BKP6R_Msk
10977
10978 /******************** Bits definition for RTC_BKP7R register ****************/
10979 #define RTC_BKP7R_Pos (0U)
10980 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
10981 #define RTC_BKP7R RTC_BKP7R_Msk
10982
10983 /******************** Bits definition for RTC_BKP8R register ****************/
10984 #define RTC_BKP8R_Pos (0U)
10985 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
10986 #define RTC_BKP8R RTC_BKP8R_Msk
10987
10988 /******************** Bits definition for RTC_BKP9R register ****************/
10989 #define RTC_BKP9R_Pos (0U)
10990 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
10991 #define RTC_BKP9R RTC_BKP9R_Msk
10992
10993 /******************** Bits definition for RTC_BKP10R register ***************/
10994 #define RTC_BKP10R_Pos (0U)
10995 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
10996 #define RTC_BKP10R RTC_BKP10R_Msk
10997
10998 /******************** Bits definition for RTC_BKP11R register ***************/
10999 #define RTC_BKP11R_Pos (0U)
11000 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
11001 #define RTC_BKP11R RTC_BKP11R_Msk
11002
11003 /******************** Bits definition for RTC_BKP12R register ***************/
11004 #define RTC_BKP12R_Pos (0U)
11005 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
11006 #define RTC_BKP12R RTC_BKP12R_Msk
11007
11008 /******************** Bits definition for RTC_BKP13R register ***************/
11009 #define RTC_BKP13R_Pos (0U)
11010 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
11011 #define RTC_BKP13R RTC_BKP13R_Msk
11012
11013 /******************** Bits definition for RTC_BKP14R register ***************/
11014 #define RTC_BKP14R_Pos (0U)
11015 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
11016 #define RTC_BKP14R RTC_BKP14R_Msk
11017
11018 /******************** Bits definition for RTC_BKP15R register ***************/
11019 #define RTC_BKP15R_Pos (0U)
11020 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
11021 #define RTC_BKP15R RTC_BKP15R_Msk
11022
11023 /******************** Bits definition for RTC_BKP16R register ***************/
11024 #define RTC_BKP16R_Pos (0U)
11025 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
11026 #define RTC_BKP16R RTC_BKP16R_Msk
11027
11028 /******************** Bits definition for RTC_BKP17R register ***************/
11029 #define RTC_BKP17R_Pos (0U)
11030 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
11031 #define RTC_BKP17R RTC_BKP17R_Msk
11032
11033 /******************** Bits definition for RTC_BKP18R register ***************/
11034 #define RTC_BKP18R_Pos (0U)
11035 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
11036 #define RTC_BKP18R RTC_BKP18R_Msk
11037
11038 /******************** Bits definition for RTC_BKP19R register ***************/
11039 #define RTC_BKP19R_Pos (0U)
11040 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
11041 #define RTC_BKP19R RTC_BKP19R_Msk
11042
11043 /******************** Number of backup registers ******************************/
11044 #define RTC_BKP_NUMBER 0x000000014U
11045
11046
11047 /******************************************************************************/
11048 /* */
11049 /* SD host Interface */
11050 /* */
11051 /******************************************************************************/
11052 /****************** Bit definition for SDIO_POWER register ******************/
11053 #define SDIO_POWER_PWRCTRL_Pos (0U)
11054 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
11055 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
11056 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
11057 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
11058
11059 /****************** Bit definition for SDIO_CLKCR register ******************/
11060 #define SDIO_CLKCR_CLKDIV_Pos (0U)
11061 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
11062 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
11063 #define SDIO_CLKCR_CLKEN_Pos (8U)
11064 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
11065 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
11066 #define SDIO_CLKCR_PWRSAV_Pos (9U)
11067 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
11068 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
11069 #define SDIO_CLKCR_BYPASS_Pos (10U)
11070 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
11071 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
11072
11073 #define SDIO_CLKCR_WIDBUS_Pos (11U)
11074 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
11075 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
11076 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
11077 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
11078
11079 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
11080 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
11081 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
11082 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
11083 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
11084 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
11085
11086 /******************* Bit definition for SDIO_ARG register *******************/
11087 #define SDIO_ARG_CMDARG_Pos (0U)
11088 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
11089 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
11090
11091 /******************* Bit definition for SDIO_CMD register *******************/
11092 #define SDIO_CMD_CMDINDEX_Pos (0U)
11093 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
11094 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
11095
11096 #define SDIO_CMD_WAITRESP_Pos (6U)
11097 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
11098 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
11099 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
11100 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
11101
11102 #define SDIO_CMD_WAITINT_Pos (8U)
11103 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
11104 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
11105 #define SDIO_CMD_WAITPEND_Pos (9U)
11106 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
11107 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
11108 #define SDIO_CMD_CPSMEN_Pos (10U)
11109 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
11110 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
11111 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
11112 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
11113 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
11114 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
11115 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
11116 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
11117 #define SDIO_CMD_NIEN_Pos (13U)
11118 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
11119 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
11120 #define SDIO_CMD_CEATACMD_Pos (14U)
11121 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
11122 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
11123
11124 /***************** Bit definition for SDIO_RESPCMD register *****************/
11125 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
11126 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
11127 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
11128
11129 /****************** Bit definition for SDIO_RESP0 register ******************/
11130 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
11131 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
11132 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
11133
11134 /****************** Bit definition for SDIO_RESP1 register ******************/
11135 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
11136 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
11137 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
11138
11139 /****************** Bit definition for SDIO_RESP2 register ******************/
11140 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
11141 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
11142 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
11143
11144 /****************** Bit definition for SDIO_RESP3 register ******************/
11145 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
11146 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
11147 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
11148
11149 /****************** Bit definition for SDIO_RESP4 register ******************/
11150 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
11151 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
11152 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
11153
11154 /****************** Bit definition for SDIO_DTIMER register *****************/
11155 #define SDIO_DTIMER_DATATIME_Pos (0U)
11156 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
11157 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
11158
11159 /****************** Bit definition for SDIO_DLEN register *******************/
11160 #define SDIO_DLEN_DATALENGTH_Pos (0U)
11161 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
11162 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
11163
11164 /****************** Bit definition for SDIO_DCTRL register ******************/
11165 #define SDIO_DCTRL_DTEN_Pos (0U)
11166 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
11167 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
11168 #define SDIO_DCTRL_DTDIR_Pos (1U)
11169 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
11170 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
11171 #define SDIO_DCTRL_DTMODE_Pos (2U)
11172 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
11173 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
11174 #define SDIO_DCTRL_DMAEN_Pos (3U)
11175 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
11176 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
11177
11178 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
11179 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
11180 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
11181 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
11182 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
11183 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
11184 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
11185
11186 #define SDIO_DCTRL_RWSTART_Pos (8U)
11187 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
11188 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
11189 #define SDIO_DCTRL_RWSTOP_Pos (9U)
11190 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
11191 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
11192 #define SDIO_DCTRL_RWMOD_Pos (10U)
11193 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
11194 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
11195 #define SDIO_DCTRL_SDIOEN_Pos (11U)
11196 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
11197 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
11198
11199 /****************** Bit definition for SDIO_DCOUNT register *****************/
11200 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
11201 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
11202 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
11203
11204 /****************** Bit definition for SDIO_STA register ********************/
11205 #define SDIO_STA_CCRCFAIL_Pos (0U)
11206 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
11207 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
11208 #define SDIO_STA_DCRCFAIL_Pos (1U)
11209 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
11210 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
11211 #define SDIO_STA_CTIMEOUT_Pos (2U)
11212 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
11213 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
11214 #define SDIO_STA_DTIMEOUT_Pos (3U)
11215 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
11216 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
11217 #define SDIO_STA_TXUNDERR_Pos (4U)
11218 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
11219 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
11220 #define SDIO_STA_RXOVERR_Pos (5U)
11221 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
11222 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
11223 #define SDIO_STA_CMDREND_Pos (6U)
11224 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
11225 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
11226 #define SDIO_STA_CMDSENT_Pos (7U)
11227 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
11228 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
11229 #define SDIO_STA_DATAEND_Pos (8U)
11230 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
11231 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
11232 #define SDIO_STA_STBITERR_Pos (9U)
11233 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
11234 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
11235 #define SDIO_STA_DBCKEND_Pos (10U)
11236 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
11237 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
11238 #define SDIO_STA_CMDACT_Pos (11U)
11239 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
11240 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
11241 #define SDIO_STA_TXACT_Pos (12U)
11242 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
11243 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
11244 #define SDIO_STA_RXACT_Pos (13U)
11245 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
11246 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
11247 #define SDIO_STA_TXFIFOHE_Pos (14U)
11248 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
11249 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
11250 #define SDIO_STA_RXFIFOHF_Pos (15U)
11251 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
11252 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
11253 #define SDIO_STA_TXFIFOF_Pos (16U)
11254 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
11255 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
11256 #define SDIO_STA_RXFIFOF_Pos (17U)
11257 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
11258 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
11259 #define SDIO_STA_TXFIFOE_Pos (18U)
11260 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
11261 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
11262 #define SDIO_STA_RXFIFOE_Pos (19U)
11263 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
11264 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
11265 #define SDIO_STA_TXDAVL_Pos (20U)
11266 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
11267 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
11268 #define SDIO_STA_RXDAVL_Pos (21U)
11269 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
11270 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
11271 #define SDIO_STA_SDIOIT_Pos (22U)
11272 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
11273 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
11274 #define SDIO_STA_CEATAEND_Pos (23U)
11275 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
11276 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
11277
11278 /******************* Bit definition for SDIO_ICR register *******************/
11279 #define SDIO_ICR_CCRCFAILC_Pos (0U)
11280 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
11281 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
11282 #define SDIO_ICR_DCRCFAILC_Pos (1U)
11283 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11284 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
11285 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
11286 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
11287 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
11288 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
11289 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
11290 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
11291 #define SDIO_ICR_TXUNDERRC_Pos (4U)
11292 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
11293 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
11294 #define SDIO_ICR_RXOVERRC_Pos (5U)
11295 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
11296 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
11297 #define SDIO_ICR_CMDRENDC_Pos (6U)
11298 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
11299 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
11300 #define SDIO_ICR_CMDSENTC_Pos (7U)
11301 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
11302 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
11303 #define SDIO_ICR_DATAENDC_Pos (8U)
11304 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
11305 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
11306 #define SDIO_ICR_STBITERRC_Pos (9U)
11307 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
11308 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
11309 #define SDIO_ICR_DBCKENDC_Pos (10U)
11310 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
11311 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
11312 #define SDIO_ICR_SDIOITC_Pos (22U)
11313 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
11314 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
11315 #define SDIO_ICR_CEATAENDC_Pos (23U)
11316 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
11317 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
11318
11319 /****************** Bit definition for SDIO_MASK register *******************/
11320 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
11321 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
11322 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
11323 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
11324 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
11325 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
11326 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
11327 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
11328 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
11329 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
11330 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
11331 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
11332 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
11333 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
11334 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
11335 #define SDIO_MASK_RXOVERRIE_Pos (5U)
11336 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
11337 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
11338 #define SDIO_MASK_CMDRENDIE_Pos (6U)
11339 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
11340 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
11341 #define SDIO_MASK_CMDSENTIE_Pos (7U)
11342 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
11343 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
11344 #define SDIO_MASK_DATAENDIE_Pos (8U)
11345 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
11346 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
11347 #define SDIO_MASK_STBITERRIE_Pos (9U)
11348 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
11349 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
11350 #define SDIO_MASK_DBCKENDIE_Pos (10U)
11351 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
11352 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
11353 #define SDIO_MASK_CMDACTIE_Pos (11U)
11354 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
11355 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
11356 #define SDIO_MASK_TXACTIE_Pos (12U)
11357 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
11358 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
11359 #define SDIO_MASK_RXACTIE_Pos (13U)
11360 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
11361 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
11362 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
11363 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
11364 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
11365 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
11366 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
11367 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
11368 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
11369 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
11370 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
11371 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
11372 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
11373 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
11374 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
11375 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
11376 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
11377 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
11378 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
11379 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
11380 #define SDIO_MASK_TXDAVLIE_Pos (20U)
11381 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
11382 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
11383 #define SDIO_MASK_RXDAVLIE_Pos (21U)
11384 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
11385 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
11386 #define SDIO_MASK_SDIOITIE_Pos (22U)
11387 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
11388 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
11389 #define SDIO_MASK_CEATAENDIE_Pos (23U)
11390 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
11391 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
11392
11393 /***************** Bit definition for SDIO_FIFOCNT register *****************/
11394 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
11395 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
11396 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
11397
11398 /****************** Bit definition for SDIO_FIFO register *******************/
11399 #define SDIO_FIFO_FIFODATA_Pos (0U)
11400 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
11401 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
11402
11403 /******************************************************************************/
11404 /* */
11405 /* Serial Peripheral Interface */
11406 /* */
11407 /******************************************************************************/
11408 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
11409
11410 /******************* Bit definition for SPI_CR1 register ********************/
11411 #define SPI_CR1_CPHA_Pos (0U)
11412 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
11413 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
11414 #define SPI_CR1_CPOL_Pos (1U)
11415 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
11416 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
11417 #define SPI_CR1_MSTR_Pos (2U)
11418 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
11419 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
11420
11421 #define SPI_CR1_BR_Pos (3U)
11422 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
11423 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
11424 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
11425 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
11426 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
11427
11428 #define SPI_CR1_SPE_Pos (6U)
11429 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
11430 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
11431 #define SPI_CR1_LSBFIRST_Pos (7U)
11432 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
11433 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
11434 #define SPI_CR1_SSI_Pos (8U)
11435 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
11436 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
11437 #define SPI_CR1_SSM_Pos (9U)
11438 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
11439 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
11440 #define SPI_CR1_RXONLY_Pos (10U)
11441 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
11442 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
11443 #define SPI_CR1_DFF_Pos (11U)
11444 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
11445 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
11446 #define SPI_CR1_CRCNEXT_Pos (12U)
11447 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
11448 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
11449 #define SPI_CR1_CRCEN_Pos (13U)
11450 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
11451 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
11452 #define SPI_CR1_BIDIOE_Pos (14U)
11453 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
11454 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
11455 #define SPI_CR1_BIDIMODE_Pos (15U)
11456 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
11457 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
11458
11459 /******************* Bit definition for SPI_CR2 register ********************/
11460 #define SPI_CR2_RXDMAEN_Pos (0U)
11461 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
11462 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
11463 #define SPI_CR2_TXDMAEN_Pos (1U)
11464 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
11465 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
11466 #define SPI_CR2_SSOE_Pos (2U)
11467 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
11468 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
11469 #define SPI_CR2_FRF_Pos (4U)
11470 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
11471 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
11472 #define SPI_CR2_ERRIE_Pos (5U)
11473 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
11474 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
11475 #define SPI_CR2_RXNEIE_Pos (6U)
11476 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
11477 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
11478 #define SPI_CR2_TXEIE_Pos (7U)
11479 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
11480 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
11481
11482 /******************** Bit definition for SPI_SR register ********************/
11483 #define SPI_SR_RXNE_Pos (0U)
11484 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
11485 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
11486 #define SPI_SR_TXE_Pos (1U)
11487 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
11488 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
11489 #define SPI_SR_CHSIDE_Pos (2U)
11490 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
11491 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
11492 #define SPI_SR_UDR_Pos (3U)
11493 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
11494 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
11495 #define SPI_SR_CRCERR_Pos (4U)
11496 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
11497 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
11498 #define SPI_SR_MODF_Pos (5U)
11499 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
11500 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
11501 #define SPI_SR_OVR_Pos (6U)
11502 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
11503 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
11504 #define SPI_SR_BSY_Pos (7U)
11505 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
11506 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
11507 #define SPI_SR_FRE_Pos (8U)
11508 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
11509 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
11510
11511 /******************** Bit definition for SPI_DR register ********************/
11512 #define SPI_DR_DR_Pos (0U)
11513 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
11514 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
11515
11516 /******************* Bit definition for SPI_CRCPR register ******************/
11517 #define SPI_CRCPR_CRCPOLY_Pos (0U)
11518 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
11519 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
11520
11521 /****************** Bit definition for SPI_RXCRCR register ******************/
11522 #define SPI_RXCRCR_RXCRC_Pos (0U)
11523 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
11524 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
11525
11526 /****************** Bit definition for SPI_TXCRCR register ******************/
11527 #define SPI_TXCRCR_TXCRC_Pos (0U)
11528 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
11529 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
11530
11531 /****************** Bit definition for SPI_I2SCFGR register *****************/
11532 #define SPI_I2SCFGR_CHLEN_Pos (0U)
11533 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
11534 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
11535
11536 #define SPI_I2SCFGR_DATLEN_Pos (1U)
11537 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
11538 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
11539 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
11540 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
11541
11542 #define SPI_I2SCFGR_CKPOL_Pos (3U)
11543 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
11544 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
11545
11546 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
11547 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
11548 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
11549 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
11550 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
11551
11552 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11553 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
11554 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
11555
11556 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
11557 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
11558 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
11559 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
11560 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
11561
11562 #define SPI_I2SCFGR_I2SE_Pos (10U)
11563 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
11564 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
11565 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
11566 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
11567 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
11568
11569 /****************** Bit definition for SPI_I2SPR register *******************/
11570 #define SPI_I2SPR_I2SDIV_Pos (0U)
11571 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
11572 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
11573 #define SPI_I2SPR_ODD_Pos (8U)
11574 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
11575 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
11576 #define SPI_I2SPR_MCKOE_Pos (9U)
11577 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
11578 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
11579
11580 /******************************************************************************/
11581 /* */
11582 /* SYSCFG */
11583 /* */
11584 /******************************************************************************/
11585 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
11586 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11587 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
11588 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
11589 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
11590 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
11591 /****************** Bit definition for SYSCFG_PMC register ******************/
11592 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
11593 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
11594 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
11595 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
11596 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
11597
11598 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
11599 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11600 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
11601 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
11602 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11603 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
11604 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
11605 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11606 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
11607 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
11608 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11609 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
11610 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
11611 /**
11612 * @brief EXTI0 configuration
11613 */
11614 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
11615 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
11616 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
11617 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
11618 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
11619 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
11620 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
11621 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
11622 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
11623
11624 /**
11625 * @brief EXTI1 configuration
11626 */
11627 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
11628 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
11629 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
11630 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
11631 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
11632 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
11633 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
11634 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
11635 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
11636
11637 /**
11638 * @brief EXTI2 configuration
11639 */
11640 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
11641 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
11642 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
11643 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
11644 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
11645 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
11646 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
11647 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
11648 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
11649
11650 /**
11651 * @brief EXTI3 configuration
11652 */
11653 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
11654 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
11655 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
11656 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
11657 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
11658 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
11659 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
11660 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
11661 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
11662
11663 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
11664 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11665 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
11666 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
11667 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11668 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
11669 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
11670 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11671 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
11672 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
11673 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11674 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
11675 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
11676
11677 /**
11678 * @brief EXTI4 configuration
11679 */
11680 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
11681 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
11682 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
11683 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
11684 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
11685 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
11686 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
11687 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
11688 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
11689
11690 /**
11691 * @brief EXTI5 configuration
11692 */
11693 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
11694 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
11695 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
11696 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
11697 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
11698 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
11699 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
11700 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
11701 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
11702
11703 /**
11704 * @brief EXTI6 configuration
11705 */
11706 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
11707 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
11708 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
11709 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
11710 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
11711 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
11712 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
11713 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
11714 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
11715
11716 /**
11717 * @brief EXTI7 configuration
11718 */
11719 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
11720 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
11721 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
11722 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
11723 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
11724 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
11725 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
11726 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
11727 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
11728
11729 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
11730 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
11731 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
11732 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
11733 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
11734 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
11735 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
11736 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
11737 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
11738 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
11739 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
11740 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
11741 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
11742
11743 /**
11744 * @brief EXTI8 configuration
11745 */
11746 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
11747 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
11748 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
11749 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
11750 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
11751 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
11752 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
11753 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
11754 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
11755
11756 /**
11757 * @brief EXTI9 configuration
11758 */
11759 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
11760 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
11761 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
11762 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
11763 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
11764 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
11765 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
11766 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
11767 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
11768
11769 /**
11770 * @brief EXTI10 configuration
11771 */
11772 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
11773 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
11774 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
11775 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
11776 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
11777 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
11778 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
11779 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
11780 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
11781
11782 /**
11783 * @brief EXTI11 configuration
11784 */
11785 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
11786 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
11787 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
11788 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
11789 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
11790 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
11791 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
11792 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
11793 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
11794
11795 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
11796 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
11797 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
11798 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
11799 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
11800 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
11801 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
11802 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
11803 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
11804 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
11805 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
11806 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
11807 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
11808
11809 /**
11810 * @brief EXTI12 configuration
11811 */
11812 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
11813 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
11814 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
11815 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
11816 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
11817 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
11818 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
11819 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
11820
11821 /**
11822 * @brief EXTI13 configuration
11823 */
11824 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
11825 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
11826 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
11827 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
11828 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
11829 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
11830 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
11831 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
11832
11833 /**
11834 * @brief EXTI14 configuration
11835 */
11836 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
11837 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
11838 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
11839 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
11840 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
11841 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
11842 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
11843 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
11844
11845 /**
11846 * @brief EXTI15 configuration
11847 */
11848 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
11849 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
11850 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
11851 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
11852 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
11853 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
11854 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
11855 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
11856
11857 /****************** Bit definition for SYSCFG_CMPCR register ****************/
11858 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
11859 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
11860 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
11861 #define SYSCFG_CMPCR_READY_Pos (8U)
11862 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
11863 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
11864
11865 /******************************************************************************/
11866 /* */
11867 /* TIM */
11868 /* */
11869 /******************************************************************************/
11870 /******************* Bit definition for TIM_CR1 register ********************/
11871 #define TIM_CR1_CEN_Pos (0U)
11872 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
11873 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
11874 #define TIM_CR1_UDIS_Pos (1U)
11875 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
11876 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
11877 #define TIM_CR1_URS_Pos (2U)
11878 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
11879 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
11880 #define TIM_CR1_OPM_Pos (3U)
11881 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
11882 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
11883 #define TIM_CR1_DIR_Pos (4U)
11884 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
11885 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
11886
11887 #define TIM_CR1_CMS_Pos (5U)
11888 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
11889 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
11890 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
11891 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
11892
11893 #define TIM_CR1_ARPE_Pos (7U)
11894 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
11895 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
11896
11897 #define TIM_CR1_CKD_Pos (8U)
11898 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
11899 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
11900 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
11901 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
11902
11903 /******************* Bit definition for TIM_CR2 register ********************/
11904 #define TIM_CR2_CCPC_Pos (0U)
11905 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
11906 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
11907 #define TIM_CR2_CCUS_Pos (2U)
11908 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
11909 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
11910 #define TIM_CR2_CCDS_Pos (3U)
11911 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
11912 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
11913
11914 #define TIM_CR2_MMS_Pos (4U)
11915 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
11916 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
11917 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
11918 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
11919 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
11920
11921 #define TIM_CR2_TI1S_Pos (7U)
11922 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
11923 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
11924 #define TIM_CR2_OIS1_Pos (8U)
11925 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
11926 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
11927 #define TIM_CR2_OIS1N_Pos (9U)
11928 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
11929 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
11930 #define TIM_CR2_OIS2_Pos (10U)
11931 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
11932 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
11933 #define TIM_CR2_OIS2N_Pos (11U)
11934 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
11935 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
11936 #define TIM_CR2_OIS3_Pos (12U)
11937 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
11938 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
11939 #define TIM_CR2_OIS3N_Pos (13U)
11940 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
11941 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
11942 #define TIM_CR2_OIS4_Pos (14U)
11943 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
11944 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
11945
11946 /******************* Bit definition for TIM_SMCR register *******************/
11947 #define TIM_SMCR_SMS_Pos (0U)
11948 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
11949 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
11950 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
11951 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
11952 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
11953
11954 #define TIM_SMCR_TS_Pos (4U)
11955 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
11956 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
11957 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
11958 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
11959 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
11960
11961 #define TIM_SMCR_MSM_Pos (7U)
11962 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
11963 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
11964
11965 #define TIM_SMCR_ETF_Pos (8U)
11966 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
11967 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
11968 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
11969 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
11970 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
11971 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
11972
11973 #define TIM_SMCR_ETPS_Pos (12U)
11974 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
11975 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
11976 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
11977 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
11978
11979 #define TIM_SMCR_ECE_Pos (14U)
11980 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
11981 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
11982 #define TIM_SMCR_ETP_Pos (15U)
11983 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
11984 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
11985
11986 /******************* Bit definition for TIM_DIER register *******************/
11987 #define TIM_DIER_UIE_Pos (0U)
11988 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
11989 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
11990 #define TIM_DIER_CC1IE_Pos (1U)
11991 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
11992 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
11993 #define TIM_DIER_CC2IE_Pos (2U)
11994 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
11995 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
11996 #define TIM_DIER_CC3IE_Pos (3U)
11997 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
11998 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
11999 #define TIM_DIER_CC4IE_Pos (4U)
12000 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
12001 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
12002 #define TIM_DIER_COMIE_Pos (5U)
12003 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
12004 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
12005 #define TIM_DIER_TIE_Pos (6U)
12006 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
12007 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
12008 #define TIM_DIER_BIE_Pos (7U)
12009 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
12010 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
12011 #define TIM_DIER_UDE_Pos (8U)
12012 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
12013 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
12014 #define TIM_DIER_CC1DE_Pos (9U)
12015 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
12016 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
12017 #define TIM_DIER_CC2DE_Pos (10U)
12018 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
12019 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
12020 #define TIM_DIER_CC3DE_Pos (11U)
12021 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
12022 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
12023 #define TIM_DIER_CC4DE_Pos (12U)
12024 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
12025 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
12026 #define TIM_DIER_COMDE_Pos (13U)
12027 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
12028 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
12029 #define TIM_DIER_TDE_Pos (14U)
12030 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
12031 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
12032
12033 /******************** Bit definition for TIM_SR register ********************/
12034 #define TIM_SR_UIF_Pos (0U)
12035 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
12036 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
12037 #define TIM_SR_CC1IF_Pos (1U)
12038 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
12039 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
12040 #define TIM_SR_CC2IF_Pos (2U)
12041 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
12042 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
12043 #define TIM_SR_CC3IF_Pos (3U)
12044 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
12045 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
12046 #define TIM_SR_CC4IF_Pos (4U)
12047 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
12048 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
12049 #define TIM_SR_COMIF_Pos (5U)
12050 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
12051 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
12052 #define TIM_SR_TIF_Pos (6U)
12053 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
12054 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
12055 #define TIM_SR_BIF_Pos (7U)
12056 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
12057 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
12058 #define TIM_SR_CC1OF_Pos (9U)
12059 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
12060 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
12061 #define TIM_SR_CC2OF_Pos (10U)
12062 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
12063 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
12064 #define TIM_SR_CC3OF_Pos (11U)
12065 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
12066 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
12067 #define TIM_SR_CC4OF_Pos (12U)
12068 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
12069 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
12070
12071 /******************* Bit definition for TIM_EGR register ********************/
12072 #define TIM_EGR_UG_Pos (0U)
12073 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
12074 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
12075 #define TIM_EGR_CC1G_Pos (1U)
12076 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
12077 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
12078 #define TIM_EGR_CC2G_Pos (2U)
12079 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
12080 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
12081 #define TIM_EGR_CC3G_Pos (3U)
12082 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
12083 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
12084 #define TIM_EGR_CC4G_Pos (4U)
12085 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
12086 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
12087 #define TIM_EGR_COMG_Pos (5U)
12088 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
12089 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
12090 #define TIM_EGR_TG_Pos (6U)
12091 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
12092 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
12093 #define TIM_EGR_BG_Pos (7U)
12094 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
12095 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
12096
12097 /****************** Bit definition for TIM_CCMR1 register *******************/
12098 #define TIM_CCMR1_CC1S_Pos (0U)
12099 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
12100 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
12101 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
12102 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
12103
12104 #define TIM_CCMR1_OC1FE_Pos (2U)
12105 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
12106 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
12107 #define TIM_CCMR1_OC1PE_Pos (3U)
12108 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
12109 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
12110
12111 #define TIM_CCMR1_OC1M_Pos (4U)
12112 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
12113 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
12114 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
12115 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
12116 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
12117
12118 #define TIM_CCMR1_OC1CE_Pos (7U)
12119 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
12120 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
12121
12122 #define TIM_CCMR1_CC2S_Pos (8U)
12123 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
12124 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
12125 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
12126 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
12127
12128 #define TIM_CCMR1_OC2FE_Pos (10U)
12129 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
12130 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
12131 #define TIM_CCMR1_OC2PE_Pos (11U)
12132 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
12133 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
12134
12135 #define TIM_CCMR1_OC2M_Pos (12U)
12136 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
12137 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
12138 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
12139 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
12140 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
12141
12142 #define TIM_CCMR1_OC2CE_Pos (15U)
12143 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
12144 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
12145
12146 /*----------------------------------------------------------------------------*/
12147
12148 #define TIM_CCMR1_IC1PSC_Pos (2U)
12149 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
12150 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
12151 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
12152 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
12153
12154 #define TIM_CCMR1_IC1F_Pos (4U)
12155 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
12156 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
12157 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
12158 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
12159 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
12160 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
12161
12162 #define TIM_CCMR1_IC2PSC_Pos (10U)
12163 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
12164 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
12165 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
12166 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
12167
12168 #define TIM_CCMR1_IC2F_Pos (12U)
12169 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
12170 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
12171 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
12172 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
12173 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
12174 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
12175
12176 /****************** Bit definition for TIM_CCMR2 register *******************/
12177 #define TIM_CCMR2_CC3S_Pos (0U)
12178 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
12179 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
12180 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
12181 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
12182
12183 #define TIM_CCMR2_OC3FE_Pos (2U)
12184 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
12185 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
12186 #define TIM_CCMR2_OC3PE_Pos (3U)
12187 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
12188 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
12189
12190 #define TIM_CCMR2_OC3M_Pos (4U)
12191 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
12192 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
12193 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
12194 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
12195 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
12196
12197 #define TIM_CCMR2_OC3CE_Pos (7U)
12198 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
12199 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
12200
12201 #define TIM_CCMR2_CC4S_Pos (8U)
12202 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
12203 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
12204 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
12205 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
12206
12207 #define TIM_CCMR2_OC4FE_Pos (10U)
12208 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
12209 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
12210 #define TIM_CCMR2_OC4PE_Pos (11U)
12211 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
12212 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
12213
12214 #define TIM_CCMR2_OC4M_Pos (12U)
12215 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
12216 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
12217 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
12218 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
12219 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
12220
12221 #define TIM_CCMR2_OC4CE_Pos (15U)
12222 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
12223 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
12224
12225 /*----------------------------------------------------------------------------*/
12226
12227 #define TIM_CCMR2_IC3PSC_Pos (2U)
12228 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
12229 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
12230 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
12231 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
12232
12233 #define TIM_CCMR2_IC3F_Pos (4U)
12234 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
12235 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
12236 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
12237 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
12238 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
12239 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
12240
12241 #define TIM_CCMR2_IC4PSC_Pos (10U)
12242 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
12243 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
12244 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
12245 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
12246
12247 #define TIM_CCMR2_IC4F_Pos (12U)
12248 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
12249 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
12250 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
12251 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
12252 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
12253 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
12254
12255 /******************* Bit definition for TIM_CCER register *******************/
12256 #define TIM_CCER_CC1E_Pos (0U)
12257 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
12258 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
12259 #define TIM_CCER_CC1P_Pos (1U)
12260 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
12261 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
12262 #define TIM_CCER_CC1NE_Pos (2U)
12263 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
12264 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
12265 #define TIM_CCER_CC1NP_Pos (3U)
12266 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
12267 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
12268 #define TIM_CCER_CC2E_Pos (4U)
12269 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
12270 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
12271 #define TIM_CCER_CC2P_Pos (5U)
12272 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
12273 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
12274 #define TIM_CCER_CC2NE_Pos (6U)
12275 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
12276 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
12277 #define TIM_CCER_CC2NP_Pos (7U)
12278 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
12279 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
12280 #define TIM_CCER_CC3E_Pos (8U)
12281 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
12282 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
12283 #define TIM_CCER_CC3P_Pos (9U)
12284 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
12285 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
12286 #define TIM_CCER_CC3NE_Pos (10U)
12287 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
12288 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
12289 #define TIM_CCER_CC3NP_Pos (11U)
12290 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
12291 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
12292 #define TIM_CCER_CC4E_Pos (12U)
12293 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
12294 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
12295 #define TIM_CCER_CC4P_Pos (13U)
12296 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
12297 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
12298 #define TIM_CCER_CC4NP_Pos (15U)
12299 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
12300 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
12301
12302 /******************* Bit definition for TIM_CNT register ********************/
12303 #define TIM_CNT_CNT_Pos (0U)
12304 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
12305 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
12306
12307 /******************* Bit definition for TIM_PSC register ********************/
12308 #define TIM_PSC_PSC_Pos (0U)
12309 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
12310 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
12311
12312 /******************* Bit definition for TIM_ARR register ********************/
12313 #define TIM_ARR_ARR_Pos (0U)
12314 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
12315 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
12316
12317 /******************* Bit definition for TIM_RCR register ********************/
12318 #define TIM_RCR_REP_Pos (0U)
12319 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
12320 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
12321
12322 /******************* Bit definition for TIM_CCR1 register *******************/
12323 #define TIM_CCR1_CCR1_Pos (0U)
12324 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
12325 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
12326
12327 /******************* Bit definition for TIM_CCR2 register *******************/
12328 #define TIM_CCR2_CCR2_Pos (0U)
12329 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
12330 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
12331
12332 /******************* Bit definition for TIM_CCR3 register *******************/
12333 #define TIM_CCR3_CCR3_Pos (0U)
12334 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
12335 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
12336
12337 /******************* Bit definition for TIM_CCR4 register *******************/
12338 #define TIM_CCR4_CCR4_Pos (0U)
12339 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
12340 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
12341
12342 /******************* Bit definition for TIM_BDTR register *******************/
12343 #define TIM_BDTR_DTG_Pos (0U)
12344 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
12345 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
12346 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
12347 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
12348 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
12349 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
12350 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
12351 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
12352 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
12353 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
12354
12355 #define TIM_BDTR_LOCK_Pos (8U)
12356 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
12357 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
12358 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
12359 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
12360
12361 #define TIM_BDTR_OSSI_Pos (10U)
12362 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
12363 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
12364 #define TIM_BDTR_OSSR_Pos (11U)
12365 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
12366 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
12367 #define TIM_BDTR_BKE_Pos (12U)
12368 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
12369 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
12370 #define TIM_BDTR_BKP_Pos (13U)
12371 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
12372 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
12373 #define TIM_BDTR_AOE_Pos (14U)
12374 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
12375 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
12376 #define TIM_BDTR_MOE_Pos (15U)
12377 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
12378 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
12379
12380 /******************* Bit definition for TIM_DCR register ********************/
12381 #define TIM_DCR_DBA_Pos (0U)
12382 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
12383 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
12384 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
12385 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
12386 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
12387 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
12388 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
12389
12390 #define TIM_DCR_DBL_Pos (8U)
12391 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
12392 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
12393 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
12394 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
12395 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
12396 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
12397 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
12398
12399 /******************* Bit definition for TIM_DMAR register *******************/
12400 #define TIM_DMAR_DMAB_Pos (0U)
12401 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
12402 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
12403
12404 /******************* Bit definition for TIM_OR register *********************/
12405 #define TIM_OR_TI1_RMP_Pos (0U)
12406 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
12407 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
12408 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
12409 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
12410
12411 #define TIM_OR_TI4_RMP_Pos (6U)
12412 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
12413 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
12414 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
12415 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
12416 #define TIM_OR_ITR1_RMP_Pos (10U)
12417 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
12418 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
12419 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
12420 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
12421
12422
12423 /******************************************************************************/
12424 /* */
12425 /* Universal Synchronous Asynchronous Receiver Transmitter */
12426 /* */
12427 /******************************************************************************/
12428 /******************* Bit definition for USART_SR register *******************/
12429 #define USART_SR_PE_Pos (0U)
12430 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
12431 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
12432 #define USART_SR_FE_Pos (1U)
12433 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
12434 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
12435 #define USART_SR_NE_Pos (2U)
12436 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
12437 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
12438 #define USART_SR_ORE_Pos (3U)
12439 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
12440 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
12441 #define USART_SR_IDLE_Pos (4U)
12442 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
12443 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
12444 #define USART_SR_RXNE_Pos (5U)
12445 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
12446 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
12447 #define USART_SR_TC_Pos (6U)
12448 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
12449 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
12450 #define USART_SR_TXE_Pos (7U)
12451 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
12452 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
12453 #define USART_SR_LBD_Pos (8U)
12454 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
12455 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
12456 #define USART_SR_CTS_Pos (9U)
12457 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
12458 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
12459
12460 /******************* Bit definition for USART_DR register *******************/
12461 #define USART_DR_DR_Pos (0U)
12462 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
12463 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
12464
12465 /****************** Bit definition for USART_BRR register *******************/
12466 #define USART_BRR_DIV_Fraction_Pos (0U)
12467 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
12468 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
12469 #define USART_BRR_DIV_Mantissa_Pos (4U)
12470 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
12471 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
12472
12473 /****************** Bit definition for USART_CR1 register *******************/
12474 #define USART_CR1_SBK_Pos (0U)
12475 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
12476 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
12477 #define USART_CR1_RWU_Pos (1U)
12478 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
12479 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
12480 #define USART_CR1_RE_Pos (2U)
12481 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
12482 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
12483 #define USART_CR1_TE_Pos (3U)
12484 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
12485 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
12486 #define USART_CR1_IDLEIE_Pos (4U)
12487 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
12488 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
12489 #define USART_CR1_RXNEIE_Pos (5U)
12490 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
12491 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
12492 #define USART_CR1_TCIE_Pos (6U)
12493 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
12494 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
12495 #define USART_CR1_TXEIE_Pos (7U)
12496 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
12497 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
12498 #define USART_CR1_PEIE_Pos (8U)
12499 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
12500 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
12501 #define USART_CR1_PS_Pos (9U)
12502 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
12503 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
12504 #define USART_CR1_PCE_Pos (10U)
12505 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
12506 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
12507 #define USART_CR1_WAKE_Pos (11U)
12508 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
12509 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
12510 #define USART_CR1_M_Pos (12U)
12511 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
12512 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
12513 #define USART_CR1_UE_Pos (13U)
12514 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
12515 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
12516 #define USART_CR1_OVER8_Pos (15U)
12517 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
12518 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
12519
12520 /****************** Bit definition for USART_CR2 register *******************/
12521 #define USART_CR2_ADD_Pos (0U)
12522 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
12523 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
12524 #define USART_CR2_LBDL_Pos (5U)
12525 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
12526 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
12527 #define USART_CR2_LBDIE_Pos (6U)
12528 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
12529 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
12530 #define USART_CR2_LBCL_Pos (8U)
12531 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
12532 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
12533 #define USART_CR2_CPHA_Pos (9U)
12534 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
12535 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
12536 #define USART_CR2_CPOL_Pos (10U)
12537 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
12538 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
12539 #define USART_CR2_CLKEN_Pos (11U)
12540 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
12541 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
12542
12543 #define USART_CR2_STOP_Pos (12U)
12544 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
12545 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
12546 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
12547 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
12548
12549 #define USART_CR2_LINEN_Pos (14U)
12550 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
12551 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
12552
12553 /****************** Bit definition for USART_CR3 register *******************/
12554 #define USART_CR3_EIE_Pos (0U)
12555 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
12556 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
12557 #define USART_CR3_IREN_Pos (1U)
12558 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
12559 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
12560 #define USART_CR3_IRLP_Pos (2U)
12561 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
12562 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
12563 #define USART_CR3_HDSEL_Pos (3U)
12564 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
12565 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
12566 #define USART_CR3_NACK_Pos (4U)
12567 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
12568 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
12569 #define USART_CR3_SCEN_Pos (5U)
12570 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
12571 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
12572 #define USART_CR3_DMAR_Pos (6U)
12573 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
12574 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
12575 #define USART_CR3_DMAT_Pos (7U)
12576 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
12577 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
12578 #define USART_CR3_RTSE_Pos (8U)
12579 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
12580 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
12581 #define USART_CR3_CTSE_Pos (9U)
12582 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
12583 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
12584 #define USART_CR3_CTSIE_Pos (10U)
12585 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
12586 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
12587 #define USART_CR3_ONEBIT_Pos (11U)
12588 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
12589 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
12590
12591 /****************** Bit definition for USART_GTPR register ******************/
12592 #define USART_GTPR_PSC_Pos (0U)
12593 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
12594 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
12595 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
12596 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
12597 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
12598 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
12599 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
12600 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
12601 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
12602 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
12603
12604 #define USART_GTPR_GT_Pos (8U)
12605 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
12606 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
12607
12608 /******************************************************************************/
12609 /* */
12610 /* Window WATCHDOG */
12611 /* */
12612 /******************************************************************************/
12613 /******************* Bit definition for WWDG_CR register ********************/
12614 #define WWDG_CR_T_Pos (0U)
12615 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
12616 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
12617 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
12618 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
12619 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
12620 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
12621 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
12622 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
12623 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
12624 /* Legacy defines */
12625 #define WWDG_CR_T0 WWDG_CR_T_0
12626 #define WWDG_CR_T1 WWDG_CR_T_1
12627 #define WWDG_CR_T2 WWDG_CR_T_2
12628 #define WWDG_CR_T3 WWDG_CR_T_3
12629 #define WWDG_CR_T4 WWDG_CR_T_4
12630 #define WWDG_CR_T5 WWDG_CR_T_5
12631 #define WWDG_CR_T6 WWDG_CR_T_6
12632
12633 #define WWDG_CR_WDGA_Pos (7U)
12634 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
12635 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
12636
12637 /******************* Bit definition for WWDG_CFR register *******************/
12638 #define WWDG_CFR_W_Pos (0U)
12639 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
12640 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
12641 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
12642 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
12643 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
12644 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
12645 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
12646 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
12647 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
12648 /* Legacy defines */
12649 #define WWDG_CFR_W0 WWDG_CFR_W_0
12650 #define WWDG_CFR_W1 WWDG_CFR_W_1
12651 #define WWDG_CFR_W2 WWDG_CFR_W_2
12652 #define WWDG_CFR_W3 WWDG_CFR_W_3
12653 #define WWDG_CFR_W4 WWDG_CFR_W_4
12654 #define WWDG_CFR_W5 WWDG_CFR_W_5
12655 #define WWDG_CFR_W6 WWDG_CFR_W_6
12656
12657 #define WWDG_CFR_WDGTB_Pos (7U)
12658 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
12659 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
12660 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
12661 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
12662 /* Legacy defines */
12663 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
12664 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
12665
12666 #define WWDG_CFR_EWI_Pos (9U)
12667 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
12668 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
12669
12670 /******************* Bit definition for WWDG_SR register ********************/
12671 #define WWDG_SR_EWIF_Pos (0U)
12672 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
12673 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
12674
12675
12676 /******************************************************************************/
12677 /* */
12678 /* DBG */
12679 /* */
12680 /******************************************************************************/
12681 /******************** Bit definition for DBGMCU_IDCODE register *************/
12682 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
12683 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
12684 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
12685 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
12686 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
12687 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
12688
12689 /******************** Bit definition for DBGMCU_CR register *****************/
12690 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
12691 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
12692 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
12693 #define DBGMCU_CR_DBG_STOP_Pos (1U)
12694 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
12695 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
12696 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
12697 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
12698 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
12699 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
12700 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
12701 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
12702
12703 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
12704 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
12705 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
12706 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
12707 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
12708
12709 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
12710 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
12711 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
12712 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
12713 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
12714 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
12715 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
12716 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
12717 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
12718 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
12719 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
12720 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
12721 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
12722 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
12723 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
12724 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
12725 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
12726 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
12727 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
12728 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
12729 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
12730 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
12731 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
12732 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
12733 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
12734 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
12735 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
12736 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
12737 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
12738 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
12739 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
12740 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
12741 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
12742 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
12743 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
12744 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
12745 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
12746 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
12747 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
12748 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
12749 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
12750 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
12751 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
12752 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
12753 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
12754 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
12755 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
12756 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
12757 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
12758 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
12759 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
12760 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
12761 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
12762 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
12763
12764 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
12765 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
12766 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
12767 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
12768 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
12769 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
12770 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
12771 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
12772 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
12773 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
12774 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
12775 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
12776 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
12777 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
12778 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
12779 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
12780
12781 /******************************************************************************/
12782 /* */
12783 /* USB_OTG */
12784 /* */
12785 /******************************************************************************/
12786 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
12787 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
12788 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
12789 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
12790 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
12791 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
12792 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
12793 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
12794 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
12795 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
12796 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
12797 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
12798 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
12799 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
12800 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
12801 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
12802 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
12803 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
12804 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
12805 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
12806 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
12807 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
12808 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
12809 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
12810 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
12811 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
12812 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
12813 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
12814 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
12815 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
12816 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
12817
12818 /******************** Bit definition forUSB_OTG_HCFG register ********************/
12819
12820 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
12821 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
12822 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
12823 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
12824 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
12825 #define USB_OTG_HCFG_FSLSS_Pos (2U)
12826 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
12827 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
12828
12829 /******************** Bit definition for USB_OTG_DCFG register ********************/
12830
12831 #define USB_OTG_DCFG_DSPD_Pos (0U)
12832 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
12833 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
12834 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
12835 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
12836 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
12837 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
12838 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
12839
12840 #define USB_OTG_DCFG_DAD_Pos (4U)
12841 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
12842 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
12843 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
12844 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
12845 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
12846 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
12847 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
12848 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
12849 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
12850
12851 #define USB_OTG_DCFG_PFIVL_Pos (11U)
12852 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
12853 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
12854 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
12855 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
12856
12857 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
12858 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
12859 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
12860 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
12861 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
12862
12863 /******************** Bit definition for USB_OTG_PCGCR register ********************/
12864 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
12865 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
12866 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
12867 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
12868 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
12869 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
12870 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
12871 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
12872 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
12873
12874 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
12875 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
12876 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
12877 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
12878 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
12879 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
12880 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
12881 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
12882 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
12883 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
12884 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
12885 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
12886 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
12887 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
12888 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
12889 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
12890 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
12891 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
12892 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
12893
12894 /******************** Bit definition for USB_OTG_DCTL register ********************/
12895 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
12896 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
12897 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
12898 #define USB_OTG_DCTL_SDIS_Pos (1U)
12899 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
12900 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
12901 #define USB_OTG_DCTL_GINSTS_Pos (2U)
12902 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
12903 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
12904 #define USB_OTG_DCTL_GONSTS_Pos (3U)
12905 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
12906 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
12907
12908 #define USB_OTG_DCTL_TCTL_Pos (4U)
12909 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
12910 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
12911 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
12912 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
12913 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
12914 #define USB_OTG_DCTL_SGINAK_Pos (7U)
12915 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
12916 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
12917 #define USB_OTG_DCTL_CGINAK_Pos (8U)
12918 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
12919 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
12920 #define USB_OTG_DCTL_SGONAK_Pos (9U)
12921 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
12922 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
12923 #define USB_OTG_DCTL_CGONAK_Pos (10U)
12924 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
12925 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
12926 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
12927 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
12928 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
12929
12930 /******************** Bit definition for USB_OTG_HFIR register ********************/
12931 #define USB_OTG_HFIR_FRIVL_Pos (0U)
12932 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
12933 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
12934
12935 /******************** Bit definition for USB_OTG_HFNUM register ********************/
12936 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
12937 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
12938 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
12939 #define USB_OTG_HFNUM_FTREM_Pos (16U)
12940 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
12941 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
12942
12943 /******************** Bit definition for USB_OTG_DSTS register ********************/
12944 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
12945 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
12946 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
12947
12948 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
12949 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
12950 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
12951 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
12952 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
12953 #define USB_OTG_DSTS_EERR_Pos (3U)
12954 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
12955 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
12956 #define USB_OTG_DSTS_FNSOF_Pos (8U)
12957 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
12958 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
12959
12960 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
12961 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
12962 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
12963 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
12964 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
12965 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
12966 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
12967 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
12968 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
12969 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
12970 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
12971 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
12972 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
12973 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
12974 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
12975 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
12976 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
12977 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
12978 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
12979 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
12980 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
12981
12982 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
12983
12984 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
12985 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
12986 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
12987 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
12988 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
12989 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
12990 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
12991 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
12992 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
12993 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
12994 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
12995 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
12996 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
12997 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
12998 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
12999 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
13000 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
13001 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
13002 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
13003 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
13004 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
13005 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
13006 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
13007 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
13008 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
13009 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
13010 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
13011 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
13012 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
13013 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
13014 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
13015 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
13016 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
13017 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
13018 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
13019 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
13020 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
13021 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
13022 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
13023 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
13024 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
13025 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
13026 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
13027 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
13028 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
13029 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
13030 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
13031 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
13032 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
13033 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
13034 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
13035 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
13036 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
13037 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
13038 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
13039 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
13040 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
13041 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
13042 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
13043 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
13044 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
13045
13046 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
13047 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
13048 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
13049 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
13050 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
13051 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
13052 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
13053 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
13054 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
13055 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
13056 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
13057 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
13058 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
13059 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
13060 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
13061 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
13062
13063
13064 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
13065 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
13066 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
13067 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
13068 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
13069 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
13070 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
13071 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
13072 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
13073 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
13074 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
13075 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
13076 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
13077 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
13078
13079 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
13080 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
13081 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
13082 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
13083 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
13084 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
13085 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
13086 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
13087 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
13088 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
13089 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
13090 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
13091 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
13092 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
13093 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
13094 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
13095 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
13096 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
13097 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
13098 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
13099 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
13100 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
13101 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
13102 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
13103 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
13104
13105 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
13106 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
13107 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
13108 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
13109 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
13110 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
13111 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
13112 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
13113 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
13114 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
13115 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
13116 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
13117 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
13118 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
13119 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
13120
13121 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
13122 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
13123 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
13124 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
13125 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
13126 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
13127 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
13128 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
13129 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
13130 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
13131 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
13132
13133 /******************** Bit definition for USB_OTG_HAINT register ********************/
13134 #define USB_OTG_HAINT_HAINT_Pos (0U)
13135 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
13136 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
13137
13138 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
13139 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
13140 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
13141 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
13142 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
13143 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
13144 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
13145 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
13146 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
13147 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
13148 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
13149 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
13150 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
13151 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
13152 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
13153 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
13154 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
13155 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
13156 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
13157 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
13158 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
13159 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
13160
13161 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
13162 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
13163 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
13164 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
13165 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
13166 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
13167 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
13168 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
13169 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
13170 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
13171 #define USB_OTG_GINTSTS_SOF_Pos (3U)
13172 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
13173 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
13174 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
13175 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
13176 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
13177 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
13178 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
13179 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
13180 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
13181 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
13182 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
13183 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
13184 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
13185 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
13186 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
13187 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
13188 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
13189 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
13190 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
13191 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
13192 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
13193 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
13194 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
13195 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
13196 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
13197 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
13198 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
13199 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
13200 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
13201 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
13202 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
13203 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
13204 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
13205 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
13206 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
13207 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
13208 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
13209 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
13210 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
13211 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
13212 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
13213 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
13214 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
13215 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
13216 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
13217 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
13218 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
13219 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
13220 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
13221 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
13222 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
13223 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
13224 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
13225 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
13226 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
13227 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
13228 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
13229 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
13230 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
13231 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
13232 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
13233 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
13234 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
13235 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
13236 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
13237 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
13238 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
13239 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
13240
13241 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
13242 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
13243 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
13244 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
13245 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
13246 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
13247 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
13248 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
13249 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
13250 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
13251 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
13252 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
13253 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
13254 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
13255 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
13256 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
13257 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
13258 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
13259 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
13260 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
13261 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
13262 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
13263 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
13264 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
13265 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
13266 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
13267 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
13268 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
13269 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
13270 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
13271 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
13272 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
13273 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
13274 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
13275 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
13276 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
13277 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
13278 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
13279 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
13280 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
13281 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
13282 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
13283 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
13284 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
13285 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
13286 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
13287 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
13288 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
13289 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
13290 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
13291 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
13292 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
13293 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
13294 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
13295 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
13296 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
13297 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
13298 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
13299 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
13300 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
13301 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
13302 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
13303 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
13304 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
13305 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
13306 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
13307 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
13308 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
13309 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
13310 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
13311 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
13312 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
13313 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
13314 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
13315 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
13316 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
13317 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
13318 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
13319 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
13320
13321 /******************** Bit definition for USB_OTG_DAINT register ********************/
13322 #define USB_OTG_DAINT_IEPINT_Pos (0U)
13323 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
13324 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
13325 #define USB_OTG_DAINT_OEPINT_Pos (16U)
13326 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
13327 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
13328
13329 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
13330 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
13331 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
13332 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
13333
13334 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
13335 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
13336 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
13337 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
13338 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
13339 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
13340 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
13341 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
13342 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
13343 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
13344 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
13345 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
13346 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
13347
13348 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
13349 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
13350 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
13351 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
13352 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
13353 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
13354 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
13355
13356 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
13357 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
13358 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
13359 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
13360
13361 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
13362 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
13363 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
13364 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
13365
13366 /******************** Bit definition for OTG register ********************/
13367 #define USB_OTG_NPTXFSA_Pos (0U)
13368 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
13369 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
13370 #define USB_OTG_NPTXFD_Pos (16U)
13371 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
13372 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
13373 #define USB_OTG_TX0FSA_Pos (0U)
13374 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
13375 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
13376 #define USB_OTG_TX0FD_Pos (16U)
13377 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
13378 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
13379
13380 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
13381 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
13382 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
13383 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
13384
13385 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
13386 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
13387 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
13388 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
13389
13390 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
13391 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
13392 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
13393 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
13394 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
13395 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
13396 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
13397 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
13398 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
13399 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
13400 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
13401
13402 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
13403 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
13404 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
13405 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
13406 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
13407 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
13408 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
13409 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
13410 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
13411 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
13412
13413 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
13414 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
13415 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
13416 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
13417 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
13418 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
13419 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
13420
13421 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
13422 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
13423 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
13424 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
13425 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
13426 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
13427 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
13428 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
13429 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
13430 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
13431 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
13432 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
13433 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
13434 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
13435 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
13436
13437 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
13438 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
13439 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
13440 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
13441 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
13442 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
13443 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
13444 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
13445 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
13446 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
13447 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
13448 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
13449 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
13450 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
13451 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
13452
13453 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
13454 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
13455 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
13456 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
13457
13458 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
13459 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
13460 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
13461 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
13462 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
13463 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
13464 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
13465
13466 /******************** Bit definition for USB_OTG_GCCFG register ********************/
13467 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
13468 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
13469 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
13470 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
13471 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
13472 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
13473 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
13474 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
13475 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
13476 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
13477 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
13478 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
13479 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
13480 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
13481 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
13482 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
13483 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
13484 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
13485
13486 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
13487 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
13488 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
13489 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
13490 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
13491 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
13492 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
13493
13494 /******************** Bit definition for USB_OTG_CID register ********************/
13495 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
13496 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
13497 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
13498
13499 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
13500 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
13501 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
13502 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
13503 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
13504 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
13505 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
13506 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
13507 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
13508 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
13509 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
13510 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
13511 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
13512 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
13513 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
13514 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
13515 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
13516 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
13517 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
13518 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
13519 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
13520 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
13521 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
13522 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
13523 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
13524 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
13525 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
13526 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
13527
13528 /******************** Bit definition for USB_OTG_HPRT register ********************/
13529 #define USB_OTG_HPRT_PCSTS_Pos (0U)
13530 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
13531 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
13532 #define USB_OTG_HPRT_PCDET_Pos (1U)
13533 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
13534 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
13535 #define USB_OTG_HPRT_PENA_Pos (2U)
13536 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
13537 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
13538 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
13539 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
13540 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
13541 #define USB_OTG_HPRT_POCA_Pos (4U)
13542 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
13543 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
13544 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
13545 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
13546 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
13547 #define USB_OTG_HPRT_PRES_Pos (6U)
13548 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
13549 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
13550 #define USB_OTG_HPRT_PSUSP_Pos (7U)
13551 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
13552 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
13553 #define USB_OTG_HPRT_PRST_Pos (8U)
13554 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
13555 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
13556
13557 #define USB_OTG_HPRT_PLSTS_Pos (10U)
13558 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
13559 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
13560 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
13561 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
13562 #define USB_OTG_HPRT_PPWR_Pos (12U)
13563 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
13564 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
13565
13566 #define USB_OTG_HPRT_PTCTL_Pos (13U)
13567 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
13568 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
13569 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
13570 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
13571 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
13572 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
13573
13574 #define USB_OTG_HPRT_PSPD_Pos (17U)
13575 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
13576 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
13577 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
13578 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
13579
13580 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
13581 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
13582 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
13583 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
13584 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
13585 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
13586 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
13587 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
13588 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
13589 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
13590 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
13591 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
13592 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
13593 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
13594 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
13595 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
13596 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
13597 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
13598 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
13599 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
13600 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
13601 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
13602 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
13603 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
13604 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
13605 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
13606 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
13607 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
13608 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
13609 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
13610 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
13611 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
13612 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
13613 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
13614
13615 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
13616 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
13617 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
13618 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
13619 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
13620 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
13621 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
13622
13623 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
13624 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
13625 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
13626 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
13627 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
13628 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
13629 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
13630 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
13631 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
13632 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
13633 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
13634 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
13635 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
13636
13637 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
13638 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
13639 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
13640 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
13641 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
13642 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
13643 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
13644 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
13645
13646 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
13647 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
13648 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
13649 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
13650 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
13651 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
13652 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
13653 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
13654 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
13655 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
13656 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
13657 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
13658 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
13659 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
13660 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
13661 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
13662 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
13663 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
13664 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
13665 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
13666 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
13667 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
13668 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
13669 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
13670 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
13671
13672 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
13673 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
13674 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
13675 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
13676
13677 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
13678 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
13679 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
13680 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
13681 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
13682 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
13683 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
13684 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
13685 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
13686 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
13687 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
13688 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
13689 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
13690
13691 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
13692 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
13693 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
13694 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
13695 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
13696
13697 #define USB_OTG_HCCHAR_MC_Pos (20U)
13698 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
13699 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
13700 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
13701 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
13702
13703 #define USB_OTG_HCCHAR_DAD_Pos (22U)
13704 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
13705 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
13706 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
13707 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
13708 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
13709 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
13710 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
13711 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
13712 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
13713 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
13714 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
13715 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
13716 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
13717 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
13718 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
13719 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
13720 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
13721 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
13722
13723 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
13724
13725 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
13726 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
13727 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
13728 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
13729 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
13730 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
13731 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
13732 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
13733 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
13734 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
13735
13736 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
13737 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
13738 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
13739 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
13740 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
13741 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
13742 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
13743 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
13744 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
13745 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
13746
13747 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
13748 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
13749 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
13750 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
13751 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
13752 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
13753 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
13754 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
13755 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
13756 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
13757 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
13758
13759 /******************** Bit definition for USB_OTG_HCINT register ********************/
13760 #define USB_OTG_HCINT_XFRC_Pos (0U)
13761 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
13762 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
13763 #define USB_OTG_HCINT_CHH_Pos (1U)
13764 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
13765 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
13766 #define USB_OTG_HCINT_AHBERR_Pos (2U)
13767 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
13768 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
13769 #define USB_OTG_HCINT_STALL_Pos (3U)
13770 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
13771 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
13772 #define USB_OTG_HCINT_NAK_Pos (4U)
13773 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
13774 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
13775 #define USB_OTG_HCINT_ACK_Pos (5U)
13776 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
13777 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
13778 #define USB_OTG_HCINT_NYET_Pos (6U)
13779 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
13780 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
13781 #define USB_OTG_HCINT_TXERR_Pos (7U)
13782 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
13783 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
13784 #define USB_OTG_HCINT_BBERR_Pos (8U)
13785 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
13786 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
13787 #define USB_OTG_HCINT_FRMOR_Pos (9U)
13788 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
13789 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
13790 #define USB_OTG_HCINT_DTERR_Pos (10U)
13791 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
13792 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
13793
13794 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
13795 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
13796 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
13797 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
13798 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
13799 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
13800 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
13801 #define USB_OTG_DIEPINT_TOC_Pos (3U)
13802 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
13803 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
13804 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
13805 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
13806 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
13807 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
13808 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
13809 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
13810 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
13811 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
13812 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
13813 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
13814 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
13815 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
13816 #define USB_OTG_DIEPINT_BNA_Pos (9U)
13817 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
13818 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
13819 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
13820 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
13821 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
13822 #define USB_OTG_DIEPINT_BERR_Pos (12U)
13823 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
13824 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
13825 #define USB_OTG_DIEPINT_NAK_Pos (13U)
13826 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
13827 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
13828
13829 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
13830 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
13831 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
13832 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
13833 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
13834 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
13835 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
13836 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
13837 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
13838 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
13839 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
13840 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
13841 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
13842 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
13843 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
13844 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
13845 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
13846 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
13847 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
13848 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
13849 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
13850 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
13851 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
13852 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
13853 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
13854 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
13855 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
13856 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
13857 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
13858 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
13859 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
13860 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
13861 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
13862 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
13863
13864 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
13865
13866 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
13867 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
13868 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
13869 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
13870 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
13871 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
13872 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
13873 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
13874 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
13875 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
13876 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
13877 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
13878 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
13879 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
13880 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
13881 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
13882 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
13883 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
13884 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
13885 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
13886 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
13887 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
13888 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
13889 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
13890
13891 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
13892 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
13893 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
13894 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
13895
13896 /******************** Bit definition for USB_OTG_HCDMA register ********************/
13897 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
13898 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
13899 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
13900
13901 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
13902 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
13903 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
13904 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
13905
13906 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
13907 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
13908 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
13909 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
13910 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
13911 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
13912 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
13913
13914 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
13915
13916 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
13917 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
13918 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
13919 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
13920 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
13921 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
13922 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
13923 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
13924 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
13925 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
13926 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
13927 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
13928 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
13929 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
13930 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
13931 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
13932 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
13933 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
13934 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
13935 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
13936 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
13937 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
13938 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
13939 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
13940 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
13941 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
13942 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
13943 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
13944 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
13945 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
13946 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
13947 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
13948 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
13949 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
13950 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
13951 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
13952 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
13953 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
13954
13955 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
13956 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
13957 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
13958 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
13959 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
13960 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
13961 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
13962 #define USB_OTG_DOEPINT_STUP_Pos (3U)
13963 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
13964 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
13965 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
13966 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
13967 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
13968 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
13969 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
13970 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
13971 #define USB_OTG_DOEPINT_NYET_Pos (14U)
13972 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
13973 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
13974
13975 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
13976
13977 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
13978 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
13979 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
13980 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
13981 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
13982 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
13983
13984 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
13985 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
13986 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
13987 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
13988 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
13989
13990 /******************** Bit definition for PCGCCTL register ********************/
13991 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
13992 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
13993 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
13994 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
13995 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
13996 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
13997 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
13998 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
13999 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
14000
14001 /* Legacy define */
14002 /******************** Bit definition for OTG register ********************/
14003 #define USB_OTG_CHNUM_Pos (0U)
14004 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
14005 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
14006 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
14007 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
14008 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
14009 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
14010 #define USB_OTG_BCNT_Pos (4U)
14011 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
14012 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
14013
14014 #define USB_OTG_DPID_Pos (15U)
14015 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
14016 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
14017 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
14018 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
14019
14020 #define USB_OTG_PKTSTS_Pos (17U)
14021 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
14022 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
14023 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
14024 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
14025 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
14026 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
14027
14028 #define USB_OTG_EPNUM_Pos (0U)
14029 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
14030 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
14031 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
14032 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
14033 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
14034 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
14035
14036 #define USB_OTG_FRMNUM_Pos (21U)
14037 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
14038 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
14039 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
14040 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
14041 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
14042 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
14043 /**
14044 * @}
14045 */
14046
14047 /**
14048 * @}
14049 */
14050
14051 /** @addtogroup Exported_macros
14052 * @{
14053 */
14054
14055 /******************************* ADC Instances ********************************/
14056 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
14057 ((INSTANCE) == ADC2) || \
14058 ((INSTANCE) == ADC3))
14059
14060 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14061
14062 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
14063
14064 /******************************* CAN Instances ********************************/
14065 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
14066 ((INSTANCE) == CAN2))
14067 /******************************* CRC Instances ********************************/
14068 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14069
14070 /******************************* DAC Instances ********************************/
14071 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14072
14073
14074 /******************************** DMA Instances *******************************/
14075 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
14076 ((INSTANCE) == DMA1_Stream1) || \
14077 ((INSTANCE) == DMA1_Stream2) || \
14078 ((INSTANCE) == DMA1_Stream3) || \
14079 ((INSTANCE) == DMA1_Stream4) || \
14080 ((INSTANCE) == DMA1_Stream5) || \
14081 ((INSTANCE) == DMA1_Stream6) || \
14082 ((INSTANCE) == DMA1_Stream7) || \
14083 ((INSTANCE) == DMA2_Stream0) || \
14084 ((INSTANCE) == DMA2_Stream1) || \
14085 ((INSTANCE) == DMA2_Stream2) || \
14086 ((INSTANCE) == DMA2_Stream3) || \
14087 ((INSTANCE) == DMA2_Stream4) || \
14088 ((INSTANCE) == DMA2_Stream5) || \
14089 ((INSTANCE) == DMA2_Stream6) || \
14090 ((INSTANCE) == DMA2_Stream7))
14091
14092 /******************************* GPIO Instances *******************************/
14093 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14094 ((INSTANCE) == GPIOB) || \
14095 ((INSTANCE) == GPIOC) || \
14096 ((INSTANCE) == GPIOD) || \
14097 ((INSTANCE) == GPIOE) || \
14098 ((INSTANCE) == GPIOF) || \
14099 ((INSTANCE) == GPIOG) || \
14100 ((INSTANCE) == GPIOH) || \
14101 ((INSTANCE) == GPIOI))
14102
14103 /******************************** I2C Instances *******************************/
14104 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14105 ((INSTANCE) == I2C2) || \
14106 ((INSTANCE) == I2C3))
14107
14108 /******************************* SMBUS Instances ******************************/
14109 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
14110
14111 /******************************** I2S Instances *******************************/
14112
14113 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
14114 ((INSTANCE) == SPI3))
14115
14116 /*************************** I2S Extended Instances ***************************/
14117 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
14118 ((INSTANCE) == I2S3ext))
14119 /* Legacy Defines */
14120 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
14121
14122 /******************************* RNG Instances ********************************/
14123 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
14124
14125 /****************************** RTC Instances *********************************/
14126 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
14127
14128
14129 /******************************** SPI Instances *******************************/
14130 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14131 ((INSTANCE) == SPI2) || \
14132 ((INSTANCE) == SPI3))
14133
14134
14135 /****************** TIM Instances : All supported instances *******************/
14136 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14137 ((INSTANCE) == TIM2) || \
14138 ((INSTANCE) == TIM3) || \
14139 ((INSTANCE) == TIM4) || \
14140 ((INSTANCE) == TIM5) || \
14141 ((INSTANCE) == TIM6) || \
14142 ((INSTANCE) == TIM7) || \
14143 ((INSTANCE) == TIM8) || \
14144 ((INSTANCE) == TIM9) || \
14145 ((INSTANCE) == TIM10)|| \
14146 ((INSTANCE) == TIM11)|| \
14147 ((INSTANCE) == TIM12)|| \
14148 ((INSTANCE) == TIM13)|| \
14149 ((INSTANCE) == TIM14))
14150
14151 /************* TIM Instances : at least 1 capture/compare channel *************/
14152 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14153 ((INSTANCE) == TIM2) || \
14154 ((INSTANCE) == TIM3) || \
14155 ((INSTANCE) == TIM4) || \
14156 ((INSTANCE) == TIM5) || \
14157 ((INSTANCE) == TIM8) || \
14158 ((INSTANCE) == TIM9) || \
14159 ((INSTANCE) == TIM10) || \
14160 ((INSTANCE) == TIM11) || \
14161 ((INSTANCE) == TIM12) || \
14162 ((INSTANCE) == TIM13) || \
14163 ((INSTANCE) == TIM14))
14164
14165 /************ TIM Instances : at least 2 capture/compare channels *************/
14166 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14167 ((INSTANCE) == TIM2) || \
14168 ((INSTANCE) == TIM3) || \
14169 ((INSTANCE) == TIM4) || \
14170 ((INSTANCE) == TIM5) || \
14171 ((INSTANCE) == TIM8) || \
14172 ((INSTANCE) == TIM9) || \
14173 ((INSTANCE) == TIM12))
14174
14175 /************ TIM Instances : at least 3 capture/compare channels *************/
14176 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14177 ((INSTANCE) == TIM2) || \
14178 ((INSTANCE) == TIM3) || \
14179 ((INSTANCE) == TIM4) || \
14180 ((INSTANCE) == TIM5) || \
14181 ((INSTANCE) == TIM8))
14182
14183 /************ TIM Instances : at least 4 capture/compare channels *************/
14184 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14185 ((INSTANCE) == TIM2) || \
14186 ((INSTANCE) == TIM3) || \
14187 ((INSTANCE) == TIM4) || \
14188 ((INSTANCE) == TIM5) || \
14189 ((INSTANCE) == TIM8))
14190
14191 /******************** TIM Instances : Advanced-control timers *****************/
14192 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14193 ((INSTANCE) == TIM8))
14194
14195 /******************* TIM Instances : Timer input XOR function *****************/
14196 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14197 ((INSTANCE) == TIM2) || \
14198 ((INSTANCE) == TIM3) || \
14199 ((INSTANCE) == TIM4) || \
14200 ((INSTANCE) == TIM5) || \
14201 ((INSTANCE) == TIM8))
14202
14203 /****************** TIM Instances : DMA requests generation (UDE) *************/
14204 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14205 ((INSTANCE) == TIM2) || \
14206 ((INSTANCE) == TIM3) || \
14207 ((INSTANCE) == TIM4) || \
14208 ((INSTANCE) == TIM5) || \
14209 ((INSTANCE) == TIM6) || \
14210 ((INSTANCE) == TIM7) || \
14211 ((INSTANCE) == TIM8))
14212
14213 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
14214 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14215 ((INSTANCE) == TIM2) || \
14216 ((INSTANCE) == TIM3) || \
14217 ((INSTANCE) == TIM4) || \
14218 ((INSTANCE) == TIM5) || \
14219 ((INSTANCE) == TIM8))
14220
14221 /************ TIM Instances : DMA requests generation (COMDE) *****************/
14222 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14223 ((INSTANCE) == TIM2) || \
14224 ((INSTANCE) == TIM3) || \
14225 ((INSTANCE) == TIM4) || \
14226 ((INSTANCE) == TIM5) || \
14227 ((INSTANCE) == TIM8))
14228
14229 /******************** TIM Instances : DMA burst feature ***********************/
14230 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14231 ((INSTANCE) == TIM2) || \
14232 ((INSTANCE) == TIM3) || \
14233 ((INSTANCE) == TIM4) || \
14234 ((INSTANCE) == TIM5) || \
14235 ((INSTANCE) == TIM8))
14236
14237 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
14238 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14239 ((INSTANCE) == TIM2) || \
14240 ((INSTANCE) == TIM3) || \
14241 ((INSTANCE) == TIM4) || \
14242 ((INSTANCE) == TIM5) || \
14243 ((INSTANCE) == TIM6) || \
14244 ((INSTANCE) == TIM7) || \
14245 ((INSTANCE) == TIM8))
14246
14247 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
14248 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14249 ((INSTANCE) == TIM2) || \
14250 ((INSTANCE) == TIM3) || \
14251 ((INSTANCE) == TIM4) || \
14252 ((INSTANCE) == TIM5) || \
14253 ((INSTANCE) == TIM8) || \
14254 ((INSTANCE) == TIM9) || \
14255 ((INSTANCE) == TIM12))
14256
14257 /********************** TIM Instances : 32 bit Counter ************************/
14258 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
14259 ((INSTANCE) == TIM5))
14260
14261 /***************** TIM Instances : external trigger input availabe ************/
14262 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14263 ((INSTANCE) == TIM2) || \
14264 ((INSTANCE) == TIM3) || \
14265 ((INSTANCE) == TIM4) || \
14266 ((INSTANCE) == TIM5) || \
14267 ((INSTANCE) == TIM8))
14268
14269 /****************** TIM Instances : remapping capability **********************/
14270 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
14271 ((INSTANCE) == TIM5) || \
14272 ((INSTANCE) == TIM11))
14273
14274 /******************* TIM Instances : output(s) available **********************/
14275 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
14276 ((((INSTANCE) == TIM1) && \
14277 (((CHANNEL) == TIM_CHANNEL_1) || \
14278 ((CHANNEL) == TIM_CHANNEL_2) || \
14279 ((CHANNEL) == TIM_CHANNEL_3) || \
14280 ((CHANNEL) == TIM_CHANNEL_4))) \
14281 || \
14282 (((INSTANCE) == TIM2) && \
14283 (((CHANNEL) == TIM_CHANNEL_1) || \
14284 ((CHANNEL) == TIM_CHANNEL_2) || \
14285 ((CHANNEL) == TIM_CHANNEL_3) || \
14286 ((CHANNEL) == TIM_CHANNEL_4))) \
14287 || \
14288 (((INSTANCE) == TIM3) && \
14289 (((CHANNEL) == TIM_CHANNEL_1) || \
14290 ((CHANNEL) == TIM_CHANNEL_2) || \
14291 ((CHANNEL) == TIM_CHANNEL_3) || \
14292 ((CHANNEL) == TIM_CHANNEL_4))) \
14293 || \
14294 (((INSTANCE) == TIM4) && \
14295 (((CHANNEL) == TIM_CHANNEL_1) || \
14296 ((CHANNEL) == TIM_CHANNEL_2) || \
14297 ((CHANNEL) == TIM_CHANNEL_3) || \
14298 ((CHANNEL) == TIM_CHANNEL_4))) \
14299 || \
14300 (((INSTANCE) == TIM5) && \
14301 (((CHANNEL) == TIM_CHANNEL_1) || \
14302 ((CHANNEL) == TIM_CHANNEL_2) || \
14303 ((CHANNEL) == TIM_CHANNEL_3) || \
14304 ((CHANNEL) == TIM_CHANNEL_4))) \
14305 || \
14306 (((INSTANCE) == TIM8) && \
14307 (((CHANNEL) == TIM_CHANNEL_1) || \
14308 ((CHANNEL) == TIM_CHANNEL_2) || \
14309 ((CHANNEL) == TIM_CHANNEL_3) || \
14310 ((CHANNEL) == TIM_CHANNEL_4))) \
14311 || \
14312 (((INSTANCE) == TIM9) && \
14313 (((CHANNEL) == TIM_CHANNEL_1) || \
14314 ((CHANNEL) == TIM_CHANNEL_2))) \
14315 || \
14316 (((INSTANCE) == TIM10) && \
14317 (((CHANNEL) == TIM_CHANNEL_1))) \
14318 || \
14319 (((INSTANCE) == TIM11) && \
14320 (((CHANNEL) == TIM_CHANNEL_1))) \
14321 || \
14322 (((INSTANCE) == TIM12) && \
14323 (((CHANNEL) == TIM_CHANNEL_1) || \
14324 ((CHANNEL) == TIM_CHANNEL_2))) \
14325 || \
14326 (((INSTANCE) == TIM13) && \
14327 (((CHANNEL) == TIM_CHANNEL_1))) \
14328 || \
14329 (((INSTANCE) == TIM14) && \
14330 (((CHANNEL) == TIM_CHANNEL_1))))
14331
14332 /************ TIM Instances : complementary output(s) available ***************/
14333 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
14334 ((((INSTANCE) == TIM1) && \
14335 (((CHANNEL) == TIM_CHANNEL_1) || \
14336 ((CHANNEL) == TIM_CHANNEL_2) || \
14337 ((CHANNEL) == TIM_CHANNEL_3))) \
14338 || \
14339 (((INSTANCE) == TIM8) && \
14340 (((CHANNEL) == TIM_CHANNEL_1) || \
14341 ((CHANNEL) == TIM_CHANNEL_2) || \
14342 ((CHANNEL) == TIM_CHANNEL_3))))
14343
14344 /****************** TIM Instances : supporting counting mode selection ********/
14345 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14346 ((INSTANCE) == TIM2) || \
14347 ((INSTANCE) == TIM3) || \
14348 ((INSTANCE) == TIM4) || \
14349 ((INSTANCE) == TIM5) || \
14350 ((INSTANCE) == TIM8))
14351
14352 /****************** TIM Instances : supporting clock division *****************/
14353 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14354 ((INSTANCE) == TIM2) || \
14355 ((INSTANCE) == TIM3) || \
14356 ((INSTANCE) == TIM4) || \
14357 ((INSTANCE) == TIM5) || \
14358 ((INSTANCE) == TIM8) || \
14359 ((INSTANCE) == TIM9) || \
14360 ((INSTANCE) == TIM10)|| \
14361 ((INSTANCE) == TIM11)|| \
14362 ((INSTANCE) == TIM12)|| \
14363 ((INSTANCE) == TIM13)|| \
14364 ((INSTANCE) == TIM14))
14365
14366 /****************** TIM Instances : supporting commutation event generation ***/
14367 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
14368 ((INSTANCE) == TIM8))
14369
14370
14371 /****************** TIM Instances : supporting OCxREF clear *******************/
14372 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14373 ((INSTANCE) == TIM2) || \
14374 ((INSTANCE) == TIM3) || \
14375 ((INSTANCE) == TIM4) || \
14376 ((INSTANCE) == TIM5) || \
14377 ((INSTANCE) == TIM8))
14378
14379 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
14380 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14381 ((INSTANCE) == TIM2) || \
14382 ((INSTANCE) == TIM3) || \
14383 ((INSTANCE) == TIM4) || \
14384 ((INSTANCE) == TIM5) || \
14385 ((INSTANCE) == TIM8) || \
14386 ((INSTANCE) == TIM9) || \
14387 ((INSTANCE) == TIM12))
14388
14389 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
14390 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14391 ((INSTANCE) == TIM2) || \
14392 ((INSTANCE) == TIM3) || \
14393 ((INSTANCE) == TIM4) || \
14394 ((INSTANCE) == TIM5) || \
14395 ((INSTANCE) == TIM8))
14396
14397 /****************** TIM Instances : supporting repetition counter *************/
14398 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14399 ((INSTANCE) == TIM8))
14400
14401 /****************** TIM Instances : supporting encoder interface **************/
14402 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14403 ((INSTANCE) == TIM2) || \
14404 ((INSTANCE) == TIM3) || \
14405 ((INSTANCE) == TIM4) || \
14406 ((INSTANCE) == TIM5) || \
14407 ((INSTANCE) == TIM8) || \
14408 ((INSTANCE) == TIM9) || \
14409 ((INSTANCE) == TIM12))
14410 /****************** TIM Instances : supporting Hall sensor interface **********/
14411 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14412 ((INSTANCE) == TIM2) || \
14413 ((INSTANCE) == TIM3) || \
14414 ((INSTANCE) == TIM4) || \
14415 ((INSTANCE) == TIM5) || \
14416 ((INSTANCE) == TIM8))
14417 /****************** TIM Instances : supporting the break function *************/
14418 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14419 ((INSTANCE) == TIM8))
14420
14421 /******************** USART Instances : Synchronous mode **********************/
14422 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14423 ((INSTANCE) == USART2) || \
14424 ((INSTANCE) == USART3) || \
14425 ((INSTANCE) == USART6))
14426
14427 /******************** UART Instances : Half-Duplex mode **********************/
14428 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14429 ((INSTANCE) == USART2) || \
14430 ((INSTANCE) == USART3) || \
14431 ((INSTANCE) == UART4) || \
14432 ((INSTANCE) == UART5) || \
14433 ((INSTANCE) == USART6))
14434
14435 /* Legacy defines */
14436 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
14437
14438 /****************** UART Instances : Hardware Flow control ********************/
14439 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14440 ((INSTANCE) == USART2) || \
14441 ((INSTANCE) == USART3) || \
14442 ((INSTANCE) == USART6))
14443 /******************** UART Instances : LIN mode **********************/
14444 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
14445
14446 /********************* UART Instances : Smart card mode ***********************/
14447 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14448 ((INSTANCE) == USART2) || \
14449 ((INSTANCE) == USART3) || \
14450 ((INSTANCE) == USART6))
14451
14452 /*********************** UART Instances : IRDA mode ***************************/
14453 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14454 ((INSTANCE) == USART2) || \
14455 ((INSTANCE) == USART3) || \
14456 ((INSTANCE) == UART4) || \
14457 ((INSTANCE) == UART5) || \
14458 ((INSTANCE) == USART6))
14459
14460
14461 /*********************** PCD Instances ****************************************/
14462 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
14463 ((INSTANCE) == USB_OTG_HS))
14464
14465 /*********************** HCD Instances ****************************************/
14466 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
14467 ((INSTANCE) == USB_OTG_HS))
14468
14469 /****************************** SDIO Instances ********************************/
14470 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
14471
14472 /****************************** IWDG Instances ********************************/
14473 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
14474
14475 /****************************** WWDG Instances ********************************/
14476 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
14477
14478 /****************************** USB Exported Constants ************************/
14479 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
14480 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
14481 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
14482 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
14483
14484 /*
14485 * @brief Specific devices reset values definitions
14486 */
14487 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
14488 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
14489
14490 #define RCC_MAX_FREQUENCY 168000000U /*!< Max frequency of family in Hz*/
14491 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
14492 #define RCC_MAX_FREQUENCY_SCALE2 144000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
14493 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
14494 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
14495 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
14496 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
14497
14498 #define RCC_PLLN_MIN_VALUE 50U
14499 #define RCC_PLLN_MAX_VALUE 432U
14500
14501 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
14502 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
14503 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
14504 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
14505 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
14506
14507 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
14508 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
14509 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
14510 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
14511
14512 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
14513 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
14514 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
14515 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
14516 /******************************************************************************/
14517 /* For a painless codes migration between the STM32F4xx device product */
14518 /* lines, the aliases defined below are put in place to overcome the */
14519 /* differences in the interrupt handlers and IRQn definitions. */
14520 /* No need to update developed interrupt code when moving across */
14521 /* product lines within the same STM32F4 Family */
14522 /******************************************************************************/
14523 /* Aliases for __IRQn */
14524 #define FMC_IRQn FSMC_IRQn
14525
14526 /* Aliases for __IRQHandler */
14527 #define FMC_IRQHandler FSMC_IRQHandler
14528
14529 /**
14530 * @}
14531 */
14532
14533 /**
14534 * @}
14535 */
14536
14537 /**
14538 * @}
14539 */
14540
14541 #ifdef __cplusplus
14542 }
14543 #endif /* __cplusplus */
14544
14545 #endif /* __STM32F415xx_H */
14546
14547
14548
14549 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/