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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f410tx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F410Tx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - peripherals registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f410tx
47 * @{
48 */
49
50 #ifndef __STM32F410Tx_H
51 #define __STM32F410Tx_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #define __FPU_PRESENT 1U /*!< FPU present */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78 /**
79 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
87 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
88 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
89 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
91 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
92 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
93 /****** STM32 specific Interrupt Numbers **********************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
99 RCC_IRQn = 5, /*!< RCC global Interrupt */
100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
112 ADC_IRQn = 18, /*!< ADC1 global Interrupts */
113 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
114 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
115 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
116 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
117 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
118 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
119 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
120 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
121 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
122 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
123 USART1_IRQn = 37, /*!< USART1 global Interrupt */
124 USART2_IRQn = 38, /*!< USART2 global Interrupt */
125 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
126 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
127 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
128 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
129 TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
130 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
131 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
132 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
133 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
134 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
135 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
136 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
137 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
138 RNG_IRQn = 80, /*!< RNG global Interrupt */
139 FPU_IRQn = 81, /*!< FPU global interrupt */
140 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
141 FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
142 LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
143 } IRQn_Type;
144
145 /**
146 * @}
147 */
148
149 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
150 #include "system_stm32f4xx.h"
151 #include <stdint.h>
152
153 /** @addtogroup Peripheral_registers_structures
154 * @{
155 */
156
157 /**
158 * @brief Analog to Digital Converter
159 */
160
161 typedef struct
162 {
163 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
164 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
165 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
166 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
167 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
168 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
169 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
170 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
171 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
172 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
173 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
174 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
175 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
176 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
177 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
178 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
179 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
180 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
181 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
182 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
183 } ADC_TypeDef;
184
185 typedef struct
186 {
187 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
188 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
189 __IO uint32_t CDR; /*!< ADC common regular data register for dual
190 AND triple modes, Address offset: ADC1 base address + 0x308 */
191 } ADC_Common_TypeDef;
192
193 /**
194 * @brief CRC calculation unit
195 */
196
197 typedef struct
198 {
199 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
200 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
201 uint8_t RESERVED0; /*!< Reserved, 0x05 */
202 uint16_t RESERVED1; /*!< Reserved, 0x06 */
203 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
204 } CRC_TypeDef;
205
206 /**
207 * @brief Digital to Analog Converter
208 */
209
210 typedef struct
211 {
212 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
213 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
214 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
215 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
216 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
217 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
218 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
219 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
220 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
221 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
222 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
223 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
224 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
225 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
226 } DAC_TypeDef;
227
228 /**
229 * @brief Debug MCU
230 */
231
232 typedef struct
233 {
234 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
235 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
236 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
237 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
238 }DBGMCU_TypeDef;
239
240
241 /**
242 * @brief DMA Controller
243 */
244
245 typedef struct
246 {
247 __IO uint32_t CR; /*!< DMA stream x configuration register */
248 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
249 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
250 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
251 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
252 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
253 } DMA_Stream_TypeDef;
254
255 typedef struct
256 {
257 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
258 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
259 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
260 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
261 } DMA_TypeDef;
262
263 /**
264 * @brief External Interrupt/Event Controller
265 */
266
267 typedef struct
268 {
269 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
270 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
271 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
272 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
273 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
274 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
275 } EXTI_TypeDef;
276
277 /**
278 * @brief FLASH Registers
279 */
280
281 typedef struct
282 {
283 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
284 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
285 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
286 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
287 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
288 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
289 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
290 } FLASH_TypeDef;
291
292 /**
293 * @brief General Purpose I/O
294 */
295
296 typedef struct
297 {
298 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
299 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
300 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
301 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
302 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
303 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
304 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
305 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
306 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
307 } GPIO_TypeDef;
308
309 /**
310 * @brief System configuration controller
311 */
312
313 typedef struct
314 {
315 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
316 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
317 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
318 uint32_t RESERVED; /*!< Reserved, 0x18 */
319 __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
320 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
321 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x24 */
322 } SYSCFG_TypeDef;
323
324 /**
325 * @brief Inter-integrated Circuit Interface
326 */
327
328 typedef struct
329 {
330 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
331 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
332 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
333 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
334 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
335 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
336 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
337 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
338 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
339 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
340 } I2C_TypeDef;
341
342 /**
343 * @brief Inter-integrated Circuit Interface
344 */
345
346 typedef struct
347 {
348 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
349 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
350 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
351 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
352 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
353 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
354 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
355 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
356 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
357 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
358 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
359 } FMPI2C_TypeDef;
360
361 /**
362 * @brief Independent WATCHDOG
363 */
364
365 typedef struct
366 {
367 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
368 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
369 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
370 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
371 } IWDG_TypeDef;
372
373
374 /**
375 * @brief Power Control
376 */
377
378 typedef struct
379 {
380 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
381 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
382 } PWR_TypeDef;
383
384 /**
385 * @brief Reset and Clock Control
386 */
387
388 typedef struct
389 {
390 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
391 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
392 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
393 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
394 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
395 uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
396 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
397 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
398 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
399 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
400 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
401 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
402 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
403 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
404 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
405 uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
406 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
407 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
408 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
409 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
410 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
411 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
412 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
413 uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
414 __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
415 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
416 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
417 } RCC_TypeDef;
418
419 /**
420 * @brief Real-Time Clock
421 */
422
423 typedef struct
424 {
425 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
426 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
427 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
428 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
429 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
430 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
431 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
432 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
433 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
434 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
435 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
436 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
437 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
438 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
439 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
440 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
441 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
442 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
443 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
444 uint32_t RESERVED7; /*!< Reserved, 0x4C */
445 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
446 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
447 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
448 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
449 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
450 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
451 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
452 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
453 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
454 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
455 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
456 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
457 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
458 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
459 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
460 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
461 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
462 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
463 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
464 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
465 } RTC_TypeDef;
466
467 /**
468 * @brief Serial Peripheral Interface
469 */
470
471 typedef struct
472 {
473 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
474 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
475 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
476 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
477 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
478 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
479 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
480 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
481 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
482 } SPI_TypeDef;
483
484
485 /**
486 * @brief TIM
487 */
488
489 typedef struct
490 {
491 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
492 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
493 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
494 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
495 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
496 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
497 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
498 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
499 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
500 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
501 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
502 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
503 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
504 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
505 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
506 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
507 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
508 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
509 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
510 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
511 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
512 } TIM_TypeDef;
513
514 /**
515 * @brief Universal Synchronous Asynchronous Receiver Transmitter
516 */
517
518 typedef struct
519 {
520 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
521 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
522 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
523 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
524 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
525 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
526 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
527 } USART_TypeDef;
528
529 /**
530 * @brief Window WATCHDOG
531 */
532
533 typedef struct
534 {
535 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
536 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
537 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
538 } WWDG_TypeDef;
539
540 /**
541 * @brief RNG
542 */
543
544 typedef struct
545 {
546 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
547 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
548 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
549 } RNG_TypeDef;
550
551
552 /**
553 * @brief LPTIMER
554 */
555 typedef struct
556 {
557 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
558 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
559 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
560 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
561 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
562 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
563 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
564 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
565 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
566 } LPTIM_TypeDef;
567
568 /**
569 * @}
570 */
571
572 /** @addtogroup Peripheral_memory_map
573 * @{
574 */
575 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
576 #define SRAM1_BASE 0x20000000U /*!< SRAM1(32 KB) base address in the alias region */
577 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
578 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region */
579 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
580 #define FLASH_END 0x0801FFFFU /*!< FLASH end address */
581 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
582 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
583
584 /* Legacy defines */
585 #define SRAM_BASE SRAM1_BASE
586 #define SRAM_BB_BASE SRAM1_BB_BASE
587
588 /*!< Peripheral memory map */
589 #define APB1PERIPH_BASE PERIPH_BASE
590 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
591 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
592
593 /*!< APB1 peripherals */
594 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
595 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
596 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
597 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
598 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
599 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
600 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
601 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
602 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
603 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
604 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
605 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
606
607 /*!< APB2 peripherals */
608 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
609 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
610 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
611 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
612 /* Legacy define */
613 #define ADC_BASE ADC1_COMMON_BASE
614 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
615 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
616 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
617 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
618 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
619
620 /*!< AHB1 peripherals */
621 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
622 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
623 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
624 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
625 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
626 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
627 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
628 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
629 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
630 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
631 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
632 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
633 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
634 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
635 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
636 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
637 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
638 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
639 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
640 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
641 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
642 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
643 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
644 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
645 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
646
647 #define RNG_BASE (PERIPH_BASE + 0x80000U)
648
649 /*!< Debug MCU registers base address */
650 #define DBGMCU_BASE 0xE0042000U
651
652 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
653 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
654 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
655 /**
656 * @}
657 */
658
659 /** @addtogroup Peripheral_declaration
660 * @{
661 */
662 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
663 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
664 #define RTC ((RTC_TypeDef *) RTC_BASE)
665 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
666 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
667 #define USART2 ((USART_TypeDef *) USART2_BASE)
668 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
669 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
670 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
671 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
672 #define PWR ((PWR_TypeDef *) PWR_BASE)
673 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
674 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
675 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
676 #define USART1 ((USART_TypeDef *) USART1_BASE)
677 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
678 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
679 /* Legacy define */
680 #define ADC ADC1_COMMON
681 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
682 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
683 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
684 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
685 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
686 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
687 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
688 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
689 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
690 #define CRC ((CRC_TypeDef *) CRC_BASE)
691 #define RCC ((RCC_TypeDef *) RCC_BASE)
692 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
693 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
694 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
695 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
696 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
697 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
698 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
699 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
700 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
701 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
702 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
703 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
704 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
705 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
706 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
707 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
708 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
709 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
710 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
711 #define RNG ((RNG_TypeDef *) RNG_BASE)
712 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
713
714 /**
715 * @}
716 */
717
718 /** @addtogroup Exported_constants
719 * @{
720 */
721
722 /** @addtogroup Peripheral_Registers_Bits_Definition
723 * @{
724 */
725
726 /******************************************************************************/
727 /* Peripheral Registers_Bits_Definition */
728 /******************************************************************************/
729
730 /******************************************************************************/
731 /* */
732 /* Analog to Digital Converter */
733 /* */
734 /******************************************************************************/
735
736 /******************** Bit definition for ADC_SR register ********************/
737 #define ADC_SR_AWD_Pos (0U)
738 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
739 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
740 #define ADC_SR_EOC_Pos (1U)
741 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
742 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
743 #define ADC_SR_JEOC_Pos (2U)
744 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
745 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
746 #define ADC_SR_JSTRT_Pos (3U)
747 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
748 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
749 #define ADC_SR_STRT_Pos (4U)
750 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
751 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
752 #define ADC_SR_OVR_Pos (5U)
753 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
754 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
755
756 /******************* Bit definition for ADC_CR1 register ********************/
757 #define ADC_CR1_AWDCH_Pos (0U)
758 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
759 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
760 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
761 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
762 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
763 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
764 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
765 #define ADC_CR1_EOCIE_Pos (5U)
766 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
767 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
768 #define ADC_CR1_AWDIE_Pos (6U)
769 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
770 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
771 #define ADC_CR1_JEOCIE_Pos (7U)
772 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
773 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
774 #define ADC_CR1_SCAN_Pos (8U)
775 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
776 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
777 #define ADC_CR1_AWDSGL_Pos (9U)
778 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
779 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
780 #define ADC_CR1_JAUTO_Pos (10U)
781 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
782 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
783 #define ADC_CR1_DISCEN_Pos (11U)
784 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
785 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
786 #define ADC_CR1_JDISCEN_Pos (12U)
787 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
788 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
789 #define ADC_CR1_DISCNUM_Pos (13U)
790 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
791 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
792 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
793 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
794 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
795 #define ADC_CR1_JAWDEN_Pos (22U)
796 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
797 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
798 #define ADC_CR1_AWDEN_Pos (23U)
799 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
800 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
801 #define ADC_CR1_RES_Pos (24U)
802 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
803 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
804 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
805 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
806 #define ADC_CR1_OVRIE_Pos (26U)
807 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
808 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
809
810 /******************* Bit definition for ADC_CR2 register ********************/
811 #define ADC_CR2_ADON_Pos (0U)
812 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
813 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
814 #define ADC_CR2_CONT_Pos (1U)
815 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
816 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
817 #define ADC_CR2_DMA_Pos (8U)
818 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
819 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
820 #define ADC_CR2_DDS_Pos (9U)
821 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
822 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
823 #define ADC_CR2_EOCS_Pos (10U)
824 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
825 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
826 #define ADC_CR2_ALIGN_Pos (11U)
827 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
828 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
829 #define ADC_CR2_JEXTSEL_Pos (16U)
830 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
831 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
832 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
833 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
834 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
835 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
836 #define ADC_CR2_JEXTEN_Pos (20U)
837 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
838 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
839 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
840 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
841 #define ADC_CR2_JSWSTART_Pos (22U)
842 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
843 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
844 #define ADC_CR2_EXTSEL_Pos (24U)
845 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
846 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
847 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
848 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
849 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
850 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
851 #define ADC_CR2_EXTEN_Pos (28U)
852 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
853 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
854 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
855 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
856 #define ADC_CR2_SWSTART_Pos (30U)
857 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
858 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
859
860 /****************** Bit definition for ADC_SMPR1 register *******************/
861 #define ADC_SMPR1_SMP10_Pos (0U)
862 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
863 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
864 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
865 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
866 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
867 #define ADC_SMPR1_SMP11_Pos (3U)
868 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
869 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
870 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
871 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
872 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
873 #define ADC_SMPR1_SMP12_Pos (6U)
874 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
875 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
876 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
877 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
878 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
879 #define ADC_SMPR1_SMP13_Pos (9U)
880 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
881 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
882 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
883 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
884 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
885 #define ADC_SMPR1_SMP14_Pos (12U)
886 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
887 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
888 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
889 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
890 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
891 #define ADC_SMPR1_SMP15_Pos (15U)
892 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
893 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
894 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
895 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
896 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
897 #define ADC_SMPR1_SMP16_Pos (18U)
898 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
899 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
900 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
901 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
902 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
903 #define ADC_SMPR1_SMP17_Pos (21U)
904 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
905 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
906 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
907 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
908 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
909 #define ADC_SMPR1_SMP18_Pos (24U)
910 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
911 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
912 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
913 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
914 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
915
916 /****************** Bit definition for ADC_SMPR2 register *******************/
917 #define ADC_SMPR2_SMP0_Pos (0U)
918 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
919 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
920 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
921 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
922 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
923 #define ADC_SMPR2_SMP1_Pos (3U)
924 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
925 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
926 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
927 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
928 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
929 #define ADC_SMPR2_SMP2_Pos (6U)
930 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
931 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
932 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
933 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
934 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
935 #define ADC_SMPR2_SMP3_Pos (9U)
936 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
937 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
938 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
939 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
940 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
941 #define ADC_SMPR2_SMP4_Pos (12U)
942 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
943 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
944 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
945 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
946 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
947 #define ADC_SMPR2_SMP5_Pos (15U)
948 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
949 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
950 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
951 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
952 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
953 #define ADC_SMPR2_SMP6_Pos (18U)
954 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
955 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
956 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
957 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
958 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
959 #define ADC_SMPR2_SMP7_Pos (21U)
960 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
961 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
962 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
963 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
964 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
965 #define ADC_SMPR2_SMP8_Pos (24U)
966 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
967 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
968 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
969 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
970 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
971 #define ADC_SMPR2_SMP9_Pos (27U)
972 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
973 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
974 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
975 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
976 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
977
978 /****************** Bit definition for ADC_JOFR1 register *******************/
979 #define ADC_JOFR1_JOFFSET1_Pos (0U)
980 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
981 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
982
983 /****************** Bit definition for ADC_JOFR2 register *******************/
984 #define ADC_JOFR2_JOFFSET2_Pos (0U)
985 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
986 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
987
988 /****************** Bit definition for ADC_JOFR3 register *******************/
989 #define ADC_JOFR3_JOFFSET3_Pos (0U)
990 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
991 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
992
993 /****************** Bit definition for ADC_JOFR4 register *******************/
994 #define ADC_JOFR4_JOFFSET4_Pos (0U)
995 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
996 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
997
998 /******************* Bit definition for ADC_HTR register ********************/
999 #define ADC_HTR_HT_Pos (0U)
1000 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1001 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1002
1003 /******************* Bit definition for ADC_LTR register ********************/
1004 #define ADC_LTR_LT_Pos (0U)
1005 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1006 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1007
1008 /******************* Bit definition for ADC_SQR1 register *******************/
1009 #define ADC_SQR1_SQ13_Pos (0U)
1010 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1011 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1012 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1013 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1014 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1015 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1016 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1017 #define ADC_SQR1_SQ14_Pos (5U)
1018 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1019 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1020 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1021 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1022 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1023 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1024 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1025 #define ADC_SQR1_SQ15_Pos (10U)
1026 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1027 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1028 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1029 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1030 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1031 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1032 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1033 #define ADC_SQR1_SQ16_Pos (15U)
1034 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1035 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1036 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1037 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1038 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1039 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1040 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1041 #define ADC_SQR1_L_Pos (20U)
1042 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1043 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1044 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1045 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1046 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1047 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1048
1049 /******************* Bit definition for ADC_SQR2 register *******************/
1050 #define ADC_SQR2_SQ7_Pos (0U)
1051 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1052 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1053 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1054 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1055 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1056 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1057 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1058 #define ADC_SQR2_SQ8_Pos (5U)
1059 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1060 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1061 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1062 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1063 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1064 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1065 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1066 #define ADC_SQR2_SQ9_Pos (10U)
1067 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1068 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1069 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1070 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1071 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1072 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1073 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1074 #define ADC_SQR2_SQ10_Pos (15U)
1075 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1076 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1077 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1078 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1079 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1080 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1081 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1082 #define ADC_SQR2_SQ11_Pos (20U)
1083 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1084 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1085 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1086 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1087 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1088 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1089 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1090 #define ADC_SQR2_SQ12_Pos (25U)
1091 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1092 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1093 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1094 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1095 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1096 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1097 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1098
1099 /******************* Bit definition for ADC_SQR3 register *******************/
1100 #define ADC_SQR3_SQ1_Pos (0U)
1101 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1102 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1103 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1104 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1105 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1106 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1107 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1108 #define ADC_SQR3_SQ2_Pos (5U)
1109 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1110 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1111 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1112 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1113 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1114 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1115 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1116 #define ADC_SQR3_SQ3_Pos (10U)
1117 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1118 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1119 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1120 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1121 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1122 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1123 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1124 #define ADC_SQR3_SQ4_Pos (15U)
1125 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1126 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1127 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1128 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1129 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1130 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1131 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1132 #define ADC_SQR3_SQ5_Pos (20U)
1133 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1134 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1135 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1136 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1137 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1138 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1139 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1140 #define ADC_SQR3_SQ6_Pos (25U)
1141 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1142 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1143 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1144 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1145 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1146 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1147 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1148
1149 /******************* Bit definition for ADC_JSQR register *******************/
1150 #define ADC_JSQR_JSQ1_Pos (0U)
1151 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1152 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1153 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1154 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1155 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1156 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1157 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1158 #define ADC_JSQR_JSQ2_Pos (5U)
1159 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1160 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1161 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1162 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1163 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1164 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1165 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1166 #define ADC_JSQR_JSQ3_Pos (10U)
1167 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1168 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1169 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1170 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1171 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1172 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1173 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1174 #define ADC_JSQR_JSQ4_Pos (15U)
1175 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1176 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1177 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1178 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1179 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1180 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1181 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1182 #define ADC_JSQR_JL_Pos (20U)
1183 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1184 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1185 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1186 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1187
1188 /******************* Bit definition for ADC_JDR1 register *******************/
1189 #define ADC_JDR1_JDATA_Pos (0U)
1190 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1191 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1192
1193 /******************* Bit definition for ADC_JDR2 register *******************/
1194 #define ADC_JDR2_JDATA_Pos (0U)
1195 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1196 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1197
1198 /******************* Bit definition for ADC_JDR3 register *******************/
1199 #define ADC_JDR3_JDATA_Pos (0U)
1200 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1201 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1202
1203 /******************* Bit definition for ADC_JDR4 register *******************/
1204 #define ADC_JDR4_JDATA_Pos (0U)
1205 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1206 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1207
1208 /******************** Bit definition for ADC_DR register ********************/
1209 #define ADC_DR_DATA_Pos (0U)
1210 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1211 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1212 #define ADC_DR_ADC2DATA_Pos (16U)
1213 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1214 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1215
1216 /******************* Bit definition for ADC_CSR register ********************/
1217 #define ADC_CSR_AWD1_Pos (0U)
1218 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1219 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1220 #define ADC_CSR_EOC1_Pos (1U)
1221 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1222 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1223 #define ADC_CSR_JEOC1_Pos (2U)
1224 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1225 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1226 #define ADC_CSR_JSTRT1_Pos (3U)
1227 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1228 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1229 #define ADC_CSR_STRT1_Pos (4U)
1230 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1231 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1232 #define ADC_CSR_OVR1_Pos (5U)
1233 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1234 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1235
1236 /* Legacy defines */
1237 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1238
1239 /******************* Bit definition for ADC_CCR register ********************/
1240 #define ADC_CCR_MULTI_Pos (0U)
1241 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1242 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1243 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1244 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1245 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1246 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1247 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1248 #define ADC_CCR_DELAY_Pos (8U)
1249 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1250 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1251 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1252 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1253 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1254 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1255 #define ADC_CCR_DDS_Pos (13U)
1256 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1257 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1258 #define ADC_CCR_DMA_Pos (14U)
1259 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1260 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1261 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1262 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1263 #define ADC_CCR_ADCPRE_Pos (16U)
1264 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1265 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1266 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1267 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1268 #define ADC_CCR_VBATE_Pos (22U)
1269 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1270 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1271 #define ADC_CCR_TSVREFE_Pos (23U)
1272 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1273 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1274
1275 /******************* Bit definition for ADC_CDR register ********************/
1276 #define ADC_CDR_DATA1_Pos (0U)
1277 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1278 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1279 #define ADC_CDR_DATA2_Pos (16U)
1280 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1281 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1282
1283 /* Legacy defines */
1284 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1285 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1286
1287 /******************************************************************************/
1288 /* */
1289 /* CRC calculation unit */
1290 /* */
1291 /******************************************************************************/
1292 /******************* Bit definition for CRC_DR register *********************/
1293 #define CRC_DR_DR_Pos (0U)
1294 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1295 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1296
1297
1298 /******************* Bit definition for CRC_IDR register ********************/
1299 #define CRC_IDR_IDR_Pos (0U)
1300 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
1301 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
1302
1303
1304 /******************** Bit definition for CRC_CR register ********************/
1305 #define CRC_CR_RESET_Pos (0U)
1306 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1307 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
1308
1309 /******************************************************************************/
1310 /* */
1311 /* Digital to Analog Converter */
1312 /* */
1313 /******************************************************************************/
1314 /******************** Bit definition for DAC_CR register ********************/
1315 #define DAC_CR_EN1_Pos (0U)
1316 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
1317 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
1318 #define DAC_CR_BOFF1_Pos (1U)
1319 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
1320 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
1321 #define DAC_CR_TEN1_Pos (2U)
1322 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
1323 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
1324
1325 #define DAC_CR_TSEL1_Pos (3U)
1326 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
1327 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
1328 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
1329 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
1330 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
1331
1332 #define DAC_CR_WAVE1_Pos (6U)
1333 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
1334 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1335 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
1336 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
1337
1338 #define DAC_CR_MAMP1_Pos (8U)
1339 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
1340 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1341 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
1342 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
1343 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
1344 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
1345
1346 #define DAC_CR_DMAEN1_Pos (12U)
1347 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
1348 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
1349 #define DAC_CR_DMAUDRIE1_Pos (13U)
1350 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
1351 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
1352 #define DAC_CR_EN2_Pos (16U)
1353 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
1354 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
1355 #define DAC_CR_BOFF2_Pos (17U)
1356 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
1357 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
1358 #define DAC_CR_TEN2_Pos (18U)
1359 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
1360 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
1361
1362 #define DAC_CR_TSEL2_Pos (19U)
1363 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
1364 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
1365 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
1366 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
1367 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
1368
1369 #define DAC_CR_WAVE2_Pos (22U)
1370 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
1371 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1372 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
1373 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
1374
1375 #define DAC_CR_MAMP2_Pos (24U)
1376 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
1377 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1378 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
1379 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
1380 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
1381 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
1382
1383 #define DAC_CR_DMAEN2_Pos (28U)
1384 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
1385 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
1386 #define DAC_CR_DMAUDRIE2_Pos (29U)
1387 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
1388 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
1389
1390 /***************** Bit definition for DAC_SWTRIGR register ******************/
1391 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
1392 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
1393 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
1394 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
1395 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
1396 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
1397
1398 /***************** Bit definition for DAC_DHR12R1 register ******************/
1399 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
1400 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
1401 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
1402
1403 /***************** Bit definition for DAC_DHR12L1 register ******************/
1404 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
1405 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1406 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
1407
1408 /****************** Bit definition for DAC_DHR8R1 register ******************/
1409 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
1410 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
1411 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
1412
1413 /***************** Bit definition for DAC_DHR12R2 register ******************/
1414 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
1415 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
1416 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
1417
1418 /***************** Bit definition for DAC_DHR12L2 register ******************/
1419 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
1420 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
1421 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
1422
1423 /****************** Bit definition for DAC_DHR8R2 register ******************/
1424 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
1425 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
1426 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
1427
1428 /***************** Bit definition for DAC_DHR12RD register ******************/
1429 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
1430 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
1431 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
1432 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
1433 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
1434 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
1435
1436 /***************** Bit definition for DAC_DHR12LD register ******************/
1437 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
1438 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1439 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
1440 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
1441 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
1442 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
1443
1444 /****************** Bit definition for DAC_DHR8RD register ******************/
1445 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
1446 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
1447 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
1448 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
1449 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
1450 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
1451
1452 /******************* Bit definition for DAC_DOR1 register *******************/
1453 #define DAC_DOR1_DACC1DOR_Pos (0U)
1454 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
1455 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
1456
1457 /******************* Bit definition for DAC_DOR2 register *******************/
1458 #define DAC_DOR2_DACC2DOR_Pos (0U)
1459 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
1460 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
1461
1462 /******************** Bit definition for DAC_SR register ********************/
1463 #define DAC_SR_DMAUDR1_Pos (13U)
1464 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
1465 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
1466 #define DAC_SR_DMAUDR2_Pos (29U)
1467 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
1468 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
1469
1470
1471 /******************************************************************************/
1472 /* */
1473 /* DMA Controller */
1474 /* */
1475 /******************************************************************************/
1476 /******************** Bits definition for DMA_SxCR register *****************/
1477 #define DMA_SxCR_CHSEL_Pos (25U)
1478 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
1479 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
1480 #define DMA_SxCR_CHSEL_0 0x02000000U
1481 #define DMA_SxCR_CHSEL_1 0x04000000U
1482 #define DMA_SxCR_CHSEL_2 0x08000000U
1483 #define DMA_SxCR_MBURST_Pos (23U)
1484 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
1485 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
1486 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
1487 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
1488 #define DMA_SxCR_PBURST_Pos (21U)
1489 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
1490 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
1491 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
1492 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
1493 #define DMA_SxCR_CT_Pos (19U)
1494 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
1495 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
1496 #define DMA_SxCR_DBM_Pos (18U)
1497 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
1498 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
1499 #define DMA_SxCR_PL_Pos (16U)
1500 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
1501 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
1502 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
1503 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
1504 #define DMA_SxCR_PINCOS_Pos (15U)
1505 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
1506 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
1507 #define DMA_SxCR_MSIZE_Pos (13U)
1508 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
1509 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
1510 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
1511 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
1512 #define DMA_SxCR_PSIZE_Pos (11U)
1513 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
1514 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
1515 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
1516 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
1517 #define DMA_SxCR_MINC_Pos (10U)
1518 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
1519 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
1520 #define DMA_SxCR_PINC_Pos (9U)
1521 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
1522 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
1523 #define DMA_SxCR_CIRC_Pos (8U)
1524 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
1525 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
1526 #define DMA_SxCR_DIR_Pos (6U)
1527 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
1528 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
1529 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
1530 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
1531 #define DMA_SxCR_PFCTRL_Pos (5U)
1532 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
1533 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
1534 #define DMA_SxCR_TCIE_Pos (4U)
1535 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
1536 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
1537 #define DMA_SxCR_HTIE_Pos (3U)
1538 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
1539 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
1540 #define DMA_SxCR_TEIE_Pos (2U)
1541 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
1542 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
1543 #define DMA_SxCR_DMEIE_Pos (1U)
1544 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
1545 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
1546 #define DMA_SxCR_EN_Pos (0U)
1547 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
1548 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
1549
1550 /* Legacy defines */
1551 #define DMA_SxCR_ACK_Pos (20U)
1552 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
1553 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
1554
1555 /******************** Bits definition for DMA_SxCNDTR register **************/
1556 #define DMA_SxNDT_Pos (0U)
1557 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
1558 #define DMA_SxNDT DMA_SxNDT_Msk
1559 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
1560 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
1561 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
1562 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
1563 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
1564 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
1565 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
1566 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
1567 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
1568 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
1569 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
1570 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
1571 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
1572 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
1573 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
1574 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
1575
1576 /******************** Bits definition for DMA_SxFCR register ****************/
1577 #define DMA_SxFCR_FEIE_Pos (7U)
1578 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
1579 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
1580 #define DMA_SxFCR_FS_Pos (3U)
1581 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
1582 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
1583 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
1584 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
1585 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
1586 #define DMA_SxFCR_DMDIS_Pos (2U)
1587 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
1588 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
1589 #define DMA_SxFCR_FTH_Pos (0U)
1590 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
1591 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
1592 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
1593 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
1594
1595 /******************** Bits definition for DMA_LISR register *****************/
1596 #define DMA_LISR_TCIF3_Pos (27U)
1597 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
1598 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
1599 #define DMA_LISR_HTIF3_Pos (26U)
1600 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
1601 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
1602 #define DMA_LISR_TEIF3_Pos (25U)
1603 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
1604 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
1605 #define DMA_LISR_DMEIF3_Pos (24U)
1606 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
1607 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
1608 #define DMA_LISR_FEIF3_Pos (22U)
1609 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
1610 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
1611 #define DMA_LISR_TCIF2_Pos (21U)
1612 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
1613 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
1614 #define DMA_LISR_HTIF2_Pos (20U)
1615 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
1616 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
1617 #define DMA_LISR_TEIF2_Pos (19U)
1618 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
1619 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
1620 #define DMA_LISR_DMEIF2_Pos (18U)
1621 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
1622 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
1623 #define DMA_LISR_FEIF2_Pos (16U)
1624 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
1625 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
1626 #define DMA_LISR_TCIF1_Pos (11U)
1627 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
1628 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
1629 #define DMA_LISR_HTIF1_Pos (10U)
1630 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
1631 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
1632 #define DMA_LISR_TEIF1_Pos (9U)
1633 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
1634 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
1635 #define DMA_LISR_DMEIF1_Pos (8U)
1636 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
1637 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
1638 #define DMA_LISR_FEIF1_Pos (6U)
1639 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
1640 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
1641 #define DMA_LISR_TCIF0_Pos (5U)
1642 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
1643 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
1644 #define DMA_LISR_HTIF0_Pos (4U)
1645 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
1646 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
1647 #define DMA_LISR_TEIF0_Pos (3U)
1648 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
1649 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
1650 #define DMA_LISR_DMEIF0_Pos (2U)
1651 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
1652 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
1653 #define DMA_LISR_FEIF0_Pos (0U)
1654 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
1655 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
1656
1657 /******************** Bits definition for DMA_HISR register *****************/
1658 #define DMA_HISR_TCIF7_Pos (27U)
1659 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
1660 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
1661 #define DMA_HISR_HTIF7_Pos (26U)
1662 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
1663 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
1664 #define DMA_HISR_TEIF7_Pos (25U)
1665 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
1666 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
1667 #define DMA_HISR_DMEIF7_Pos (24U)
1668 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
1669 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
1670 #define DMA_HISR_FEIF7_Pos (22U)
1671 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
1672 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
1673 #define DMA_HISR_TCIF6_Pos (21U)
1674 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
1675 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
1676 #define DMA_HISR_HTIF6_Pos (20U)
1677 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
1678 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
1679 #define DMA_HISR_TEIF6_Pos (19U)
1680 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
1681 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
1682 #define DMA_HISR_DMEIF6_Pos (18U)
1683 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
1684 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
1685 #define DMA_HISR_FEIF6_Pos (16U)
1686 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
1687 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
1688 #define DMA_HISR_TCIF5_Pos (11U)
1689 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
1690 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
1691 #define DMA_HISR_HTIF5_Pos (10U)
1692 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
1693 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
1694 #define DMA_HISR_TEIF5_Pos (9U)
1695 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
1696 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
1697 #define DMA_HISR_DMEIF5_Pos (8U)
1698 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
1699 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
1700 #define DMA_HISR_FEIF5_Pos (6U)
1701 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
1702 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
1703 #define DMA_HISR_TCIF4_Pos (5U)
1704 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
1705 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
1706 #define DMA_HISR_HTIF4_Pos (4U)
1707 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
1708 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
1709 #define DMA_HISR_TEIF4_Pos (3U)
1710 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
1711 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
1712 #define DMA_HISR_DMEIF4_Pos (2U)
1713 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
1714 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
1715 #define DMA_HISR_FEIF4_Pos (0U)
1716 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
1717 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
1718
1719 /******************** Bits definition for DMA_LIFCR register ****************/
1720 #define DMA_LIFCR_CTCIF3_Pos (27U)
1721 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
1722 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
1723 #define DMA_LIFCR_CHTIF3_Pos (26U)
1724 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
1725 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
1726 #define DMA_LIFCR_CTEIF3_Pos (25U)
1727 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
1728 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
1729 #define DMA_LIFCR_CDMEIF3_Pos (24U)
1730 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
1731 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
1732 #define DMA_LIFCR_CFEIF3_Pos (22U)
1733 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
1734 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
1735 #define DMA_LIFCR_CTCIF2_Pos (21U)
1736 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
1737 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
1738 #define DMA_LIFCR_CHTIF2_Pos (20U)
1739 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
1740 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
1741 #define DMA_LIFCR_CTEIF2_Pos (19U)
1742 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
1743 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
1744 #define DMA_LIFCR_CDMEIF2_Pos (18U)
1745 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
1746 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
1747 #define DMA_LIFCR_CFEIF2_Pos (16U)
1748 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
1749 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
1750 #define DMA_LIFCR_CTCIF1_Pos (11U)
1751 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
1752 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
1753 #define DMA_LIFCR_CHTIF1_Pos (10U)
1754 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
1755 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
1756 #define DMA_LIFCR_CTEIF1_Pos (9U)
1757 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
1758 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
1759 #define DMA_LIFCR_CDMEIF1_Pos (8U)
1760 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
1761 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
1762 #define DMA_LIFCR_CFEIF1_Pos (6U)
1763 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
1764 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
1765 #define DMA_LIFCR_CTCIF0_Pos (5U)
1766 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
1767 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
1768 #define DMA_LIFCR_CHTIF0_Pos (4U)
1769 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
1770 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
1771 #define DMA_LIFCR_CTEIF0_Pos (3U)
1772 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
1773 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
1774 #define DMA_LIFCR_CDMEIF0_Pos (2U)
1775 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
1776 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
1777 #define DMA_LIFCR_CFEIF0_Pos (0U)
1778 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
1779 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
1780
1781 /******************** Bits definition for DMA_HIFCR register ****************/
1782 #define DMA_HIFCR_CTCIF7_Pos (27U)
1783 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
1784 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
1785 #define DMA_HIFCR_CHTIF7_Pos (26U)
1786 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
1787 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
1788 #define DMA_HIFCR_CTEIF7_Pos (25U)
1789 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
1790 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
1791 #define DMA_HIFCR_CDMEIF7_Pos (24U)
1792 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
1793 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
1794 #define DMA_HIFCR_CFEIF7_Pos (22U)
1795 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
1796 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
1797 #define DMA_HIFCR_CTCIF6_Pos (21U)
1798 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
1799 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
1800 #define DMA_HIFCR_CHTIF6_Pos (20U)
1801 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
1802 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
1803 #define DMA_HIFCR_CTEIF6_Pos (19U)
1804 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
1805 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
1806 #define DMA_HIFCR_CDMEIF6_Pos (18U)
1807 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
1808 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
1809 #define DMA_HIFCR_CFEIF6_Pos (16U)
1810 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
1811 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
1812 #define DMA_HIFCR_CTCIF5_Pos (11U)
1813 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
1814 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
1815 #define DMA_HIFCR_CHTIF5_Pos (10U)
1816 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
1817 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
1818 #define DMA_HIFCR_CTEIF5_Pos (9U)
1819 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
1820 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
1821 #define DMA_HIFCR_CDMEIF5_Pos (8U)
1822 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
1823 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
1824 #define DMA_HIFCR_CFEIF5_Pos (6U)
1825 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
1826 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
1827 #define DMA_HIFCR_CTCIF4_Pos (5U)
1828 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
1829 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
1830 #define DMA_HIFCR_CHTIF4_Pos (4U)
1831 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
1832 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
1833 #define DMA_HIFCR_CTEIF4_Pos (3U)
1834 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
1835 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
1836 #define DMA_HIFCR_CDMEIF4_Pos (2U)
1837 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
1838 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
1839 #define DMA_HIFCR_CFEIF4_Pos (0U)
1840 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
1841 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
1842
1843 /****************** Bit definition for DMA_SxPAR register ********************/
1844 #define DMA_SxPAR_PA_Pos (0U)
1845 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
1846 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
1847
1848 /****************** Bit definition for DMA_SxM0AR register ********************/
1849 #define DMA_SxM0AR_M0A_Pos (0U)
1850 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
1851 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
1852
1853 /****************** Bit definition for DMA_SxM1AR register ********************/
1854 #define DMA_SxM1AR_M1A_Pos (0U)
1855 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
1856 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
1857
1858
1859 /******************************************************************************/
1860 /* */
1861 /* External Interrupt/Event Controller */
1862 /* */
1863 /******************************************************************************/
1864 /******************* Bit definition for EXTI_IMR register *******************/
1865 #define EXTI_IMR_MR0_Pos (0U)
1866 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
1867 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
1868 #define EXTI_IMR_MR1_Pos (1U)
1869 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
1870 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
1871 #define EXTI_IMR_MR2_Pos (2U)
1872 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
1873 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
1874 #define EXTI_IMR_MR3_Pos (3U)
1875 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
1876 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
1877 #define EXTI_IMR_MR4_Pos (4U)
1878 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
1879 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
1880 #define EXTI_IMR_MR5_Pos (5U)
1881 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
1882 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
1883 #define EXTI_IMR_MR6_Pos (6U)
1884 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
1885 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
1886 #define EXTI_IMR_MR7_Pos (7U)
1887 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
1888 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
1889 #define EXTI_IMR_MR8_Pos (8U)
1890 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
1891 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
1892 #define EXTI_IMR_MR9_Pos (9U)
1893 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
1894 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
1895 #define EXTI_IMR_MR10_Pos (10U)
1896 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
1897 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
1898 #define EXTI_IMR_MR11_Pos (11U)
1899 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
1900 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
1901 #define EXTI_IMR_MR12_Pos (12U)
1902 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
1903 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
1904 #define EXTI_IMR_MR13_Pos (13U)
1905 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
1906 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
1907 #define EXTI_IMR_MR14_Pos (14U)
1908 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
1909 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
1910 #define EXTI_IMR_MR15_Pos (15U)
1911 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
1912 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
1913 #define EXTI_IMR_MR16_Pos (16U)
1914 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
1915 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
1916 #define EXTI_IMR_MR17_Pos (17U)
1917 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
1918 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
1919 #define EXTI_IMR_MR18_Pos (18U)
1920 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
1921 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
1922 #define EXTI_IMR_MR19_Pos (19U)
1923 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
1924 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
1925 #define EXTI_IMR_MR20_Pos (20U)
1926 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
1927 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
1928 #define EXTI_IMR_MR21_Pos (21U)
1929 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
1930 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
1931 #define EXTI_IMR_MR22_Pos (22U)
1932 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
1933 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
1934 #define EXTI_IMR_MR23_Pos (23U)
1935 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
1936 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
1937
1938 /* Reference Defines */
1939 #define EXTI_IMR_IM0 EXTI_IMR_MR0
1940 #define EXTI_IMR_IM1 EXTI_IMR_MR1
1941 #define EXTI_IMR_IM2 EXTI_IMR_MR2
1942 #define EXTI_IMR_IM3 EXTI_IMR_MR3
1943 #define EXTI_IMR_IM4 EXTI_IMR_MR4
1944 #define EXTI_IMR_IM5 EXTI_IMR_MR5
1945 #define EXTI_IMR_IM6 EXTI_IMR_MR6
1946 #define EXTI_IMR_IM7 EXTI_IMR_MR7
1947 #define EXTI_IMR_IM8 EXTI_IMR_MR8
1948 #define EXTI_IMR_IM9 EXTI_IMR_MR9
1949 #define EXTI_IMR_IM10 EXTI_IMR_MR10
1950 #define EXTI_IMR_IM11 EXTI_IMR_MR11
1951 #define EXTI_IMR_IM12 EXTI_IMR_MR12
1952 #define EXTI_IMR_IM13 EXTI_IMR_MR13
1953 #define EXTI_IMR_IM14 EXTI_IMR_MR14
1954 #define EXTI_IMR_IM15 EXTI_IMR_MR15
1955 #define EXTI_IMR_IM16 EXTI_IMR_MR16
1956 #define EXTI_IMR_IM17 EXTI_IMR_MR17
1957 #define EXTI_IMR_IM18 EXTI_IMR_MR18
1958 #define EXTI_IMR_IM19 EXTI_IMR_MR19
1959 #define EXTI_IMR_IM20 EXTI_IMR_MR20
1960 #define EXTI_IMR_IM21 EXTI_IMR_MR21
1961 #define EXTI_IMR_IM22 EXTI_IMR_MR22
1962 #define EXTI_IMR_IM23 EXTI_IMR_MR23
1963 #define EXTI_IMR_IM_Pos (0U)
1964 #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
1965 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
1966
1967 /******************* Bit definition for EXTI_EMR register *******************/
1968 #define EXTI_EMR_MR0_Pos (0U)
1969 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
1970 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
1971 #define EXTI_EMR_MR1_Pos (1U)
1972 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
1973 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
1974 #define EXTI_EMR_MR2_Pos (2U)
1975 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
1976 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
1977 #define EXTI_EMR_MR3_Pos (3U)
1978 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
1979 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
1980 #define EXTI_EMR_MR4_Pos (4U)
1981 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
1982 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
1983 #define EXTI_EMR_MR5_Pos (5U)
1984 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
1985 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
1986 #define EXTI_EMR_MR6_Pos (6U)
1987 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
1988 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
1989 #define EXTI_EMR_MR7_Pos (7U)
1990 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
1991 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
1992 #define EXTI_EMR_MR8_Pos (8U)
1993 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
1994 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
1995 #define EXTI_EMR_MR9_Pos (9U)
1996 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
1997 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
1998 #define EXTI_EMR_MR10_Pos (10U)
1999 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
2000 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
2001 #define EXTI_EMR_MR11_Pos (11U)
2002 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
2003 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
2004 #define EXTI_EMR_MR12_Pos (12U)
2005 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
2006 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
2007 #define EXTI_EMR_MR13_Pos (13U)
2008 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
2009 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
2010 #define EXTI_EMR_MR14_Pos (14U)
2011 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
2012 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
2013 #define EXTI_EMR_MR15_Pos (15U)
2014 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
2015 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
2016 #define EXTI_EMR_MR16_Pos (16U)
2017 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
2018 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
2019 #define EXTI_EMR_MR17_Pos (17U)
2020 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
2021 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
2022 #define EXTI_EMR_MR18_Pos (18U)
2023 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
2024 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
2025 #define EXTI_EMR_MR19_Pos (19U)
2026 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
2027 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
2028 #define EXTI_EMR_MR20_Pos (20U)
2029 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
2030 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
2031 #define EXTI_EMR_MR21_Pos (21U)
2032 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
2033 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
2034 #define EXTI_EMR_MR22_Pos (22U)
2035 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
2036 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
2037 #define EXTI_EMR_MR23_Pos (23U)
2038 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
2039 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
2040
2041 /* Reference Defines */
2042 #define EXTI_EMR_EM0 EXTI_EMR_MR0
2043 #define EXTI_EMR_EM1 EXTI_EMR_MR1
2044 #define EXTI_EMR_EM2 EXTI_EMR_MR2
2045 #define EXTI_EMR_EM3 EXTI_EMR_MR3
2046 #define EXTI_EMR_EM4 EXTI_EMR_MR4
2047 #define EXTI_EMR_EM5 EXTI_EMR_MR5
2048 #define EXTI_EMR_EM6 EXTI_EMR_MR6
2049 #define EXTI_EMR_EM7 EXTI_EMR_MR7
2050 #define EXTI_EMR_EM8 EXTI_EMR_MR8
2051 #define EXTI_EMR_EM9 EXTI_EMR_MR9
2052 #define EXTI_EMR_EM10 EXTI_EMR_MR10
2053 #define EXTI_EMR_EM11 EXTI_EMR_MR11
2054 #define EXTI_EMR_EM12 EXTI_EMR_MR12
2055 #define EXTI_EMR_EM13 EXTI_EMR_MR13
2056 #define EXTI_EMR_EM14 EXTI_EMR_MR14
2057 #define EXTI_EMR_EM15 EXTI_EMR_MR15
2058 #define EXTI_EMR_EM16 EXTI_EMR_MR16
2059 #define EXTI_EMR_EM17 EXTI_EMR_MR17
2060 #define EXTI_EMR_EM18 EXTI_EMR_MR18
2061 #define EXTI_EMR_EM19 EXTI_EMR_MR19
2062 #define EXTI_EMR_EM20 EXTI_EMR_MR20
2063 #define EXTI_EMR_EM21 EXTI_EMR_MR21
2064 #define EXTI_EMR_EM22 EXTI_EMR_MR22
2065 #define EXTI_EMR_EM23 EXTI_EMR_MR23
2066
2067 /****************** Bit definition for EXTI_RTSR register *******************/
2068 #define EXTI_RTSR_TR0_Pos (0U)
2069 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
2070 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
2071 #define EXTI_RTSR_TR1_Pos (1U)
2072 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
2073 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
2074 #define EXTI_RTSR_TR2_Pos (2U)
2075 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
2076 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
2077 #define EXTI_RTSR_TR3_Pos (3U)
2078 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
2079 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
2080 #define EXTI_RTSR_TR4_Pos (4U)
2081 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
2082 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
2083 #define EXTI_RTSR_TR5_Pos (5U)
2084 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
2085 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
2086 #define EXTI_RTSR_TR6_Pos (6U)
2087 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
2088 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
2089 #define EXTI_RTSR_TR7_Pos (7U)
2090 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
2091 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
2092 #define EXTI_RTSR_TR8_Pos (8U)
2093 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
2094 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
2095 #define EXTI_RTSR_TR9_Pos (9U)
2096 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
2097 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
2098 #define EXTI_RTSR_TR10_Pos (10U)
2099 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
2100 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
2101 #define EXTI_RTSR_TR11_Pos (11U)
2102 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
2103 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
2104 #define EXTI_RTSR_TR12_Pos (12U)
2105 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
2106 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
2107 #define EXTI_RTSR_TR13_Pos (13U)
2108 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
2109 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
2110 #define EXTI_RTSR_TR14_Pos (14U)
2111 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
2112 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
2113 #define EXTI_RTSR_TR15_Pos (15U)
2114 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
2115 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
2116 #define EXTI_RTSR_TR16_Pos (16U)
2117 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
2118 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
2119 #define EXTI_RTSR_TR17_Pos (17U)
2120 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
2121 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
2122 #define EXTI_RTSR_TR18_Pos (18U)
2123 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
2124 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
2125 #define EXTI_RTSR_TR19_Pos (19U)
2126 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
2127 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
2128 #define EXTI_RTSR_TR20_Pos (20U)
2129 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
2130 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
2131 #define EXTI_RTSR_TR21_Pos (21U)
2132 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
2133 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
2134 #define EXTI_RTSR_TR22_Pos (22U)
2135 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
2136 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
2137 #define EXTI_RTSR_TR23_Pos (23U)
2138 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
2139 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
2140
2141 /****************** Bit definition for EXTI_FTSR register *******************/
2142 #define EXTI_FTSR_TR0_Pos (0U)
2143 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
2144 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
2145 #define EXTI_FTSR_TR1_Pos (1U)
2146 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
2147 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
2148 #define EXTI_FTSR_TR2_Pos (2U)
2149 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
2150 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
2151 #define EXTI_FTSR_TR3_Pos (3U)
2152 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
2153 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
2154 #define EXTI_FTSR_TR4_Pos (4U)
2155 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
2156 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
2157 #define EXTI_FTSR_TR5_Pos (5U)
2158 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
2159 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
2160 #define EXTI_FTSR_TR6_Pos (6U)
2161 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
2162 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
2163 #define EXTI_FTSR_TR7_Pos (7U)
2164 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
2165 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
2166 #define EXTI_FTSR_TR8_Pos (8U)
2167 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
2168 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
2169 #define EXTI_FTSR_TR9_Pos (9U)
2170 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
2171 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
2172 #define EXTI_FTSR_TR10_Pos (10U)
2173 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
2174 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
2175 #define EXTI_FTSR_TR11_Pos (11U)
2176 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
2177 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
2178 #define EXTI_FTSR_TR12_Pos (12U)
2179 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
2180 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
2181 #define EXTI_FTSR_TR13_Pos (13U)
2182 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
2183 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
2184 #define EXTI_FTSR_TR14_Pos (14U)
2185 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
2186 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
2187 #define EXTI_FTSR_TR15_Pos (15U)
2188 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
2189 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
2190 #define EXTI_FTSR_TR16_Pos (16U)
2191 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
2192 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
2193 #define EXTI_FTSR_TR17_Pos (17U)
2194 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
2195 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
2196 #define EXTI_FTSR_TR18_Pos (18U)
2197 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
2198 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
2199 #define EXTI_FTSR_TR19_Pos (19U)
2200 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
2201 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
2202 #define EXTI_FTSR_TR20_Pos (20U)
2203 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
2204 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
2205 #define EXTI_FTSR_TR21_Pos (21U)
2206 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
2207 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
2208 #define EXTI_FTSR_TR22_Pos (22U)
2209 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
2210 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
2211 #define EXTI_FTSR_TR23_Pos (23U)
2212 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
2213 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
2214
2215 /****************** Bit definition for EXTI_SWIER register ******************/
2216 #define EXTI_SWIER_SWIER0_Pos (0U)
2217 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
2218 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
2219 #define EXTI_SWIER_SWIER1_Pos (1U)
2220 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
2221 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
2222 #define EXTI_SWIER_SWIER2_Pos (2U)
2223 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
2224 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
2225 #define EXTI_SWIER_SWIER3_Pos (3U)
2226 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
2227 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
2228 #define EXTI_SWIER_SWIER4_Pos (4U)
2229 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
2230 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
2231 #define EXTI_SWIER_SWIER5_Pos (5U)
2232 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
2233 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
2234 #define EXTI_SWIER_SWIER6_Pos (6U)
2235 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
2236 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
2237 #define EXTI_SWIER_SWIER7_Pos (7U)
2238 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
2239 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
2240 #define EXTI_SWIER_SWIER8_Pos (8U)
2241 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
2242 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
2243 #define EXTI_SWIER_SWIER9_Pos (9U)
2244 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
2245 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
2246 #define EXTI_SWIER_SWIER10_Pos (10U)
2247 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
2248 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
2249 #define EXTI_SWIER_SWIER11_Pos (11U)
2250 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
2251 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
2252 #define EXTI_SWIER_SWIER12_Pos (12U)
2253 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
2254 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
2255 #define EXTI_SWIER_SWIER13_Pos (13U)
2256 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
2257 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
2258 #define EXTI_SWIER_SWIER14_Pos (14U)
2259 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
2260 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
2261 #define EXTI_SWIER_SWIER15_Pos (15U)
2262 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
2263 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
2264 #define EXTI_SWIER_SWIER16_Pos (16U)
2265 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
2266 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
2267 #define EXTI_SWIER_SWIER17_Pos (17U)
2268 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
2269 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
2270 #define EXTI_SWIER_SWIER18_Pos (18U)
2271 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
2272 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
2273 #define EXTI_SWIER_SWIER19_Pos (19U)
2274 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
2275 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
2276 #define EXTI_SWIER_SWIER20_Pos (20U)
2277 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
2278 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
2279 #define EXTI_SWIER_SWIER21_Pos (21U)
2280 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
2281 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
2282 #define EXTI_SWIER_SWIER22_Pos (22U)
2283 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
2284 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
2285 #define EXTI_SWIER_SWIER23_Pos (23U)
2286 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
2287 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
2288
2289 /******************* Bit definition for EXTI_PR register ********************/
2290 #define EXTI_PR_PR0_Pos (0U)
2291 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
2292 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
2293 #define EXTI_PR_PR1_Pos (1U)
2294 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
2295 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
2296 #define EXTI_PR_PR2_Pos (2U)
2297 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
2298 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
2299 #define EXTI_PR_PR3_Pos (3U)
2300 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
2301 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
2302 #define EXTI_PR_PR4_Pos (4U)
2303 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
2304 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
2305 #define EXTI_PR_PR5_Pos (5U)
2306 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
2307 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
2308 #define EXTI_PR_PR6_Pos (6U)
2309 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
2310 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
2311 #define EXTI_PR_PR7_Pos (7U)
2312 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
2313 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
2314 #define EXTI_PR_PR8_Pos (8U)
2315 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
2316 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
2317 #define EXTI_PR_PR9_Pos (9U)
2318 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
2319 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
2320 #define EXTI_PR_PR10_Pos (10U)
2321 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
2322 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
2323 #define EXTI_PR_PR11_Pos (11U)
2324 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
2325 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
2326 #define EXTI_PR_PR12_Pos (12U)
2327 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
2328 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
2329 #define EXTI_PR_PR13_Pos (13U)
2330 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
2331 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
2332 #define EXTI_PR_PR14_Pos (14U)
2333 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
2334 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
2335 #define EXTI_PR_PR15_Pos (15U)
2336 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
2337 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
2338 #define EXTI_PR_PR16_Pos (16U)
2339 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
2340 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
2341 #define EXTI_PR_PR17_Pos (17U)
2342 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
2343 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
2344 #define EXTI_PR_PR18_Pos (18U)
2345 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
2346 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
2347 #define EXTI_PR_PR19_Pos (19U)
2348 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
2349 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
2350 #define EXTI_PR_PR20_Pos (20U)
2351 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
2352 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
2353 #define EXTI_PR_PR21_Pos (21U)
2354 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
2355 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
2356 #define EXTI_PR_PR22_Pos (22U)
2357 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
2358 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
2359 #define EXTI_PR_PR23_Pos (23U)
2360 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
2361 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
2362
2363 /******************************************************************************/
2364 /* */
2365 /* FLASH */
2366 /* */
2367 /******************************************************************************/
2368 /******************* Bits definition for FLASH_ACR register *****************/
2369 #define FLASH_ACR_LATENCY_Pos (0U)
2370 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
2371 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
2372 #define FLASH_ACR_LATENCY_0WS 0x00000000U
2373 #define FLASH_ACR_LATENCY_1WS 0x00000001U
2374 #define FLASH_ACR_LATENCY_2WS 0x00000002U
2375 #define FLASH_ACR_LATENCY_3WS 0x00000003U
2376 #define FLASH_ACR_LATENCY_4WS 0x00000004U
2377 #define FLASH_ACR_LATENCY_5WS 0x00000005U
2378 #define FLASH_ACR_LATENCY_6WS 0x00000006U
2379 #define FLASH_ACR_LATENCY_7WS 0x00000007U
2380
2381 #define FLASH_ACR_PRFTEN_Pos (8U)
2382 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
2383 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
2384 #define FLASH_ACR_ICEN_Pos (9U)
2385 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
2386 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
2387 #define FLASH_ACR_DCEN_Pos (10U)
2388 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
2389 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
2390 #define FLASH_ACR_ICRST_Pos (11U)
2391 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
2392 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
2393 #define FLASH_ACR_DCRST_Pos (12U)
2394 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
2395 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
2396 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
2397 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
2398 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
2399 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
2400 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
2401 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
2402
2403 /******************* Bits definition for FLASH_SR register ******************/
2404 #define FLASH_SR_EOP_Pos (0U)
2405 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
2406 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
2407 #define FLASH_SR_SOP_Pos (1U)
2408 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
2409 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
2410 #define FLASH_SR_WRPERR_Pos (4U)
2411 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
2412 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
2413 #define FLASH_SR_PGAERR_Pos (5U)
2414 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
2415 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
2416 #define FLASH_SR_PGPERR_Pos (6U)
2417 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
2418 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
2419 #define FLASH_SR_PGSERR_Pos (7U)
2420 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
2421 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
2422 #define FLASH_SR_RDERR_Pos (8U)
2423 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
2424 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
2425 #define FLASH_SR_BSY_Pos (16U)
2426 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
2427 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
2428
2429 /******************* Bits definition for FLASH_CR register ******************/
2430 #define FLASH_CR_PG_Pos (0U)
2431 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
2432 #define FLASH_CR_PG FLASH_CR_PG_Msk
2433 #define FLASH_CR_SER_Pos (1U)
2434 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
2435 #define FLASH_CR_SER FLASH_CR_SER_Msk
2436 #define FLASH_CR_MER_Pos (2U)
2437 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
2438 #define FLASH_CR_MER FLASH_CR_MER_Msk
2439 #define FLASH_CR_SNB_Pos (3U)
2440 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
2441 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
2442 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
2443 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
2444 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
2445 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
2446 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
2447 #define FLASH_CR_PSIZE_Pos (8U)
2448 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
2449 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
2450 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
2451 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
2452 #define FLASH_CR_STRT_Pos (16U)
2453 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
2454 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
2455 #define FLASH_CR_EOPIE_Pos (24U)
2456 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
2457 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
2458 #define FLASH_CR_LOCK_Pos (31U)
2459 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
2460 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
2461
2462 /******************* Bits definition for FLASH_OPTCR register ***************/
2463 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
2464 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
2465 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
2466 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
2467 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
2468 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
2469
2470 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
2471 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
2472 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
2473 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
2474 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
2475 #define FLASH_OPTCR_WDG_SW_Pos (5U)
2476 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
2477 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
2478 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
2479 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
2480 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
2481 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
2482 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
2483 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
2484 #define FLASH_OPTCR_RDP_Pos (8U)
2485 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
2486 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
2487 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
2488 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
2489 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
2490 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
2491 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
2492 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
2493 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
2494 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
2495 #define FLASH_OPTCR_nWRP_Pos (16U)
2496 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
2497 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
2498 #define FLASH_OPTCR_nWRP_0 0x00010000U
2499 #define FLASH_OPTCR_nWRP_1 0x00020000U
2500 #define FLASH_OPTCR_nWRP_2 0x00040000U
2501 #define FLASH_OPTCR_nWRP_3 0x00080000U
2502 #define FLASH_OPTCR_nWRP_4 0x00100000U
2503 #define FLASH_OPTCR_nWRP_5 0x00200000U
2504 #define FLASH_OPTCR_nWRP_6 0x00400000U
2505 #define FLASH_OPTCR_nWRP_7 0x00800000U
2506 #define FLASH_OPTCR_nWRP_8 0x01000000U
2507 #define FLASH_OPTCR_nWRP_9 0x02000000U
2508 #define FLASH_OPTCR_nWRP_10 0x04000000U
2509 #define FLASH_OPTCR_nWRP_11 0x08000000U
2510
2511 /****************** Bits definition for FLASH_OPTCR1 register ***************/
2512 #define FLASH_OPTCR1_nWRP_Pos (16U)
2513 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
2514 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
2515 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
2516 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
2517 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
2518 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
2519 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
2520 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
2521 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
2522 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
2523 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
2524 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
2525 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
2526 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
2527
2528 /******************************************************************************/
2529 /* */
2530 /* General Purpose I/O */
2531 /* */
2532 /******************************************************************************/
2533 /****************** Bits definition for GPIO_MODER register *****************/
2534 #define GPIO_MODER_MODE0_Pos (0U)
2535 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
2536 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
2537 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
2538 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
2539 #define GPIO_MODER_MODE1_Pos (2U)
2540 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
2541 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
2542 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
2543 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
2544 #define GPIO_MODER_MODE2_Pos (4U)
2545 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
2546 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
2547 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
2548 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
2549 #define GPIO_MODER_MODE3_Pos (6U)
2550 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
2551 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
2552 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
2553 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
2554 #define GPIO_MODER_MODE4_Pos (8U)
2555 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
2556 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
2557 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
2558 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
2559 #define GPIO_MODER_MODE5_Pos (10U)
2560 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
2561 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
2562 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
2563 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
2564 #define GPIO_MODER_MODE6_Pos (12U)
2565 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
2566 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
2567 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
2568 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
2569 #define GPIO_MODER_MODE7_Pos (14U)
2570 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
2571 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
2572 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
2573 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
2574 #define GPIO_MODER_MODE8_Pos (16U)
2575 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
2576 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
2577 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
2578 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
2579 #define GPIO_MODER_MODE9_Pos (18U)
2580 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
2581 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
2582 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
2583 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
2584 #define GPIO_MODER_MODE10_Pos (20U)
2585 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
2586 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
2587 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
2588 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
2589 #define GPIO_MODER_MODE11_Pos (22U)
2590 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
2591 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
2592 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
2593 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
2594 #define GPIO_MODER_MODE12_Pos (24U)
2595 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
2596 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
2597 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
2598 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
2599 #define GPIO_MODER_MODE13_Pos (26U)
2600 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
2601 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
2602 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
2603 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
2604 #define GPIO_MODER_MODE14_Pos (28U)
2605 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
2606 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
2607 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
2608 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
2609 #define GPIO_MODER_MODE15_Pos (30U)
2610 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
2611 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
2612 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
2613 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
2614
2615 /* Legacy defines */
2616 #define GPIO_MODER_MODER0_Pos (0U)
2617 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
2618 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
2619 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
2620 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
2621 #define GPIO_MODER_MODER1_Pos (2U)
2622 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
2623 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
2624 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
2625 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
2626 #define GPIO_MODER_MODER2_Pos (4U)
2627 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
2628 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
2629 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
2630 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
2631 #define GPIO_MODER_MODER3_Pos (6U)
2632 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
2633 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
2634 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
2635 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
2636 #define GPIO_MODER_MODER4_Pos (8U)
2637 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
2638 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
2639 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
2640 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
2641 #define GPIO_MODER_MODER5_Pos (10U)
2642 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
2643 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
2644 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
2645 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
2646 #define GPIO_MODER_MODER6_Pos (12U)
2647 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
2648 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
2649 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
2650 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
2651 #define GPIO_MODER_MODER7_Pos (14U)
2652 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
2653 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
2654 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
2655 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
2656 #define GPIO_MODER_MODER8_Pos (16U)
2657 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
2658 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
2659 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
2660 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
2661 #define GPIO_MODER_MODER9_Pos (18U)
2662 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
2663 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
2664 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
2665 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
2666 #define GPIO_MODER_MODER10_Pos (20U)
2667 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
2668 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
2669 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
2670 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
2671 #define GPIO_MODER_MODER11_Pos (22U)
2672 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
2673 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
2674 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
2675 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
2676 #define GPIO_MODER_MODER12_Pos (24U)
2677 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
2678 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
2679 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
2680 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
2681 #define GPIO_MODER_MODER13_Pos (26U)
2682 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
2683 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
2684 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
2685 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
2686 #define GPIO_MODER_MODER14_Pos (28U)
2687 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
2688 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
2689 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
2690 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
2691 #define GPIO_MODER_MODER15_Pos (30U)
2692 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
2693 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
2694 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
2695 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
2696
2697 /****************** Bits definition for GPIO_OTYPER register ****************/
2698 #define GPIO_OTYPER_OT0_Pos (0U)
2699 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
2700 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
2701 #define GPIO_OTYPER_OT1_Pos (1U)
2702 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
2703 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
2704 #define GPIO_OTYPER_OT2_Pos (2U)
2705 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
2706 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
2707 #define GPIO_OTYPER_OT3_Pos (3U)
2708 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
2709 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
2710 #define GPIO_OTYPER_OT4_Pos (4U)
2711 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
2712 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
2713 #define GPIO_OTYPER_OT5_Pos (5U)
2714 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
2715 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
2716 #define GPIO_OTYPER_OT6_Pos (6U)
2717 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
2718 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
2719 #define GPIO_OTYPER_OT7_Pos (7U)
2720 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
2721 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
2722 #define GPIO_OTYPER_OT8_Pos (8U)
2723 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
2724 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
2725 #define GPIO_OTYPER_OT9_Pos (9U)
2726 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
2727 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
2728 #define GPIO_OTYPER_OT10_Pos (10U)
2729 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
2730 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
2731 #define GPIO_OTYPER_OT11_Pos (11U)
2732 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
2733 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
2734 #define GPIO_OTYPER_OT12_Pos (12U)
2735 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
2736 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
2737 #define GPIO_OTYPER_OT13_Pos (13U)
2738 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
2739 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
2740 #define GPIO_OTYPER_OT14_Pos (14U)
2741 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
2742 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
2743 #define GPIO_OTYPER_OT15_Pos (15U)
2744 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
2745 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
2746
2747 /* Legacy defines */
2748 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
2749 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
2750 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
2751 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
2752 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
2753 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
2754 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
2755 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
2756 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
2757 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
2758 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
2759 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
2760 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
2761 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
2762 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
2763 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
2764
2765 /****************** Bits definition for GPIO_OSPEEDR register ***************/
2766 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
2767 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
2768 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
2769 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
2770 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
2771 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
2772 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
2773 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
2774 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
2775 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
2776 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
2777 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
2778 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
2779 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
2780 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
2781 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
2782 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
2783 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
2784 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
2785 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
2786 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
2787 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
2788 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
2789 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
2790 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
2791 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
2792 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
2793 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
2794 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
2795 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
2796 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
2797 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
2798 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
2799 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
2800 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
2801 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
2802 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
2803 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
2804 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
2805 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
2806 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
2807 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
2808 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
2809 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
2810 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
2811 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
2812 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
2813 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
2814 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
2815 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
2816 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
2817 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
2818 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
2819 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
2820 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
2821 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
2822 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
2823 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
2824 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
2825 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
2826 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
2827 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
2828 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
2829 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
2830 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
2831 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
2832 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
2833 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
2834 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
2835 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
2836 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
2837 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
2838 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
2839 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
2840 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
2841 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
2842 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
2843 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
2844 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
2845 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
2846
2847 /* Legacy defines */
2848 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
2849 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
2850 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
2851 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
2852 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
2853 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
2854 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
2855 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
2856 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
2857 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
2858 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
2859 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
2860 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
2861 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
2862 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
2863 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
2864 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
2865 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
2866 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
2867 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
2868 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
2869 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
2870 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
2871 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
2872 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
2873 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
2874 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
2875 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
2876 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
2877 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
2878 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
2879 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
2880 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
2881 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
2882 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
2883 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
2884 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
2885 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
2886 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
2887 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
2888 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
2889 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
2890 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
2891 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
2892 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
2893 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
2894 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
2895 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
2896
2897 /****************** Bits definition for GPIO_PUPDR register *****************/
2898 #define GPIO_PUPDR_PUPD0_Pos (0U)
2899 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
2900 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
2901 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
2902 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
2903 #define GPIO_PUPDR_PUPD1_Pos (2U)
2904 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
2905 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
2906 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
2907 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
2908 #define GPIO_PUPDR_PUPD2_Pos (4U)
2909 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
2910 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
2911 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
2912 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
2913 #define GPIO_PUPDR_PUPD3_Pos (6U)
2914 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
2915 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
2916 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
2917 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
2918 #define GPIO_PUPDR_PUPD4_Pos (8U)
2919 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
2920 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
2921 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
2922 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
2923 #define GPIO_PUPDR_PUPD5_Pos (10U)
2924 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
2925 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
2926 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
2927 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
2928 #define GPIO_PUPDR_PUPD6_Pos (12U)
2929 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
2930 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
2931 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
2932 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
2933 #define GPIO_PUPDR_PUPD7_Pos (14U)
2934 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
2935 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
2936 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
2937 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
2938 #define GPIO_PUPDR_PUPD8_Pos (16U)
2939 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
2940 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
2941 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
2942 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
2943 #define GPIO_PUPDR_PUPD9_Pos (18U)
2944 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
2945 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
2946 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
2947 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
2948 #define GPIO_PUPDR_PUPD10_Pos (20U)
2949 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
2950 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
2951 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
2952 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
2953 #define GPIO_PUPDR_PUPD11_Pos (22U)
2954 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
2955 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
2956 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
2957 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
2958 #define GPIO_PUPDR_PUPD12_Pos (24U)
2959 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
2960 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
2961 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
2962 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
2963 #define GPIO_PUPDR_PUPD13_Pos (26U)
2964 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
2965 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
2966 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
2967 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
2968 #define GPIO_PUPDR_PUPD14_Pos (28U)
2969 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
2970 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
2971 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
2972 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
2973 #define GPIO_PUPDR_PUPD15_Pos (30U)
2974 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
2975 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
2976 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
2977 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
2978
2979 /* Legacy defines */
2980 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
2981 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
2982 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
2983 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
2984 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
2985 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
2986 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
2987 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
2988 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
2989 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
2990 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
2991 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
2992 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
2993 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
2994 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
2995 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
2996 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
2997 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
2998 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
2999 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
3000 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
3001 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
3002 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
3003 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
3004 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
3005 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
3006 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
3007 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
3008 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
3009 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
3010 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
3011 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
3012 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
3013 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
3014 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
3015 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
3016 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
3017 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
3018 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
3019 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
3020 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
3021 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
3022 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
3023 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
3024 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
3025 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
3026 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
3027 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
3028
3029 /****************** Bits definition for GPIO_IDR register *******************/
3030 #define GPIO_IDR_ID0_Pos (0U)
3031 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
3032 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
3033 #define GPIO_IDR_ID1_Pos (1U)
3034 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
3035 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
3036 #define GPIO_IDR_ID2_Pos (2U)
3037 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
3038 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
3039 #define GPIO_IDR_ID3_Pos (3U)
3040 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
3041 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
3042 #define GPIO_IDR_ID4_Pos (4U)
3043 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
3044 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
3045 #define GPIO_IDR_ID5_Pos (5U)
3046 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
3047 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
3048 #define GPIO_IDR_ID6_Pos (6U)
3049 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
3050 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
3051 #define GPIO_IDR_ID7_Pos (7U)
3052 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
3053 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
3054 #define GPIO_IDR_ID8_Pos (8U)
3055 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
3056 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
3057 #define GPIO_IDR_ID9_Pos (9U)
3058 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
3059 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
3060 #define GPIO_IDR_ID10_Pos (10U)
3061 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
3062 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
3063 #define GPIO_IDR_ID11_Pos (11U)
3064 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
3065 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
3066 #define GPIO_IDR_ID12_Pos (12U)
3067 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
3068 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
3069 #define GPIO_IDR_ID13_Pos (13U)
3070 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
3071 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
3072 #define GPIO_IDR_ID14_Pos (14U)
3073 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
3074 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
3075 #define GPIO_IDR_ID15_Pos (15U)
3076 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
3077 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
3078
3079 /* Legacy defines */
3080 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
3081 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
3082 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
3083 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
3084 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
3085 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
3086 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
3087 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
3088 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
3089 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
3090 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
3091 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
3092 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
3093 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
3094 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
3095 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
3096
3097 /****************** Bits definition for GPIO_ODR register *******************/
3098 #define GPIO_ODR_OD0_Pos (0U)
3099 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
3100 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
3101 #define GPIO_ODR_OD1_Pos (1U)
3102 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
3103 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
3104 #define GPIO_ODR_OD2_Pos (2U)
3105 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
3106 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
3107 #define GPIO_ODR_OD3_Pos (3U)
3108 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
3109 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
3110 #define GPIO_ODR_OD4_Pos (4U)
3111 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
3112 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
3113 #define GPIO_ODR_OD5_Pos (5U)
3114 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
3115 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
3116 #define GPIO_ODR_OD6_Pos (6U)
3117 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
3118 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
3119 #define GPIO_ODR_OD7_Pos (7U)
3120 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
3121 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
3122 #define GPIO_ODR_OD8_Pos (8U)
3123 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
3124 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
3125 #define GPIO_ODR_OD9_Pos (9U)
3126 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
3127 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
3128 #define GPIO_ODR_OD10_Pos (10U)
3129 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
3130 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
3131 #define GPIO_ODR_OD11_Pos (11U)
3132 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
3133 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
3134 #define GPIO_ODR_OD12_Pos (12U)
3135 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
3136 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
3137 #define GPIO_ODR_OD13_Pos (13U)
3138 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
3139 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
3140 #define GPIO_ODR_OD14_Pos (14U)
3141 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
3142 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
3143 #define GPIO_ODR_OD15_Pos (15U)
3144 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
3145 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
3146 /* Legacy defines */
3147 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
3148 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
3149 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
3150 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
3151 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
3152 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
3153 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
3154 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
3155 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
3156 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
3157 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
3158 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
3159 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
3160 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
3161 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
3162 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
3163
3164 /****************** Bits definition for GPIO_BSRR register ******************/
3165 #define GPIO_BSRR_BS0_Pos (0U)
3166 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
3167 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
3168 #define GPIO_BSRR_BS1_Pos (1U)
3169 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
3170 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
3171 #define GPIO_BSRR_BS2_Pos (2U)
3172 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
3173 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
3174 #define GPIO_BSRR_BS3_Pos (3U)
3175 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
3176 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
3177 #define GPIO_BSRR_BS4_Pos (4U)
3178 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
3179 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
3180 #define GPIO_BSRR_BS5_Pos (5U)
3181 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
3182 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
3183 #define GPIO_BSRR_BS6_Pos (6U)
3184 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
3185 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
3186 #define GPIO_BSRR_BS7_Pos (7U)
3187 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
3188 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
3189 #define GPIO_BSRR_BS8_Pos (8U)
3190 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
3191 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
3192 #define GPIO_BSRR_BS9_Pos (9U)
3193 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
3194 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
3195 #define GPIO_BSRR_BS10_Pos (10U)
3196 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
3197 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
3198 #define GPIO_BSRR_BS11_Pos (11U)
3199 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
3200 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
3201 #define GPIO_BSRR_BS12_Pos (12U)
3202 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
3203 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
3204 #define GPIO_BSRR_BS13_Pos (13U)
3205 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
3206 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
3207 #define GPIO_BSRR_BS14_Pos (14U)
3208 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
3209 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
3210 #define GPIO_BSRR_BS15_Pos (15U)
3211 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
3212 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
3213 #define GPIO_BSRR_BR0_Pos (16U)
3214 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
3215 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
3216 #define GPIO_BSRR_BR1_Pos (17U)
3217 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
3218 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
3219 #define GPIO_BSRR_BR2_Pos (18U)
3220 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
3221 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
3222 #define GPIO_BSRR_BR3_Pos (19U)
3223 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
3224 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
3225 #define GPIO_BSRR_BR4_Pos (20U)
3226 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
3227 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
3228 #define GPIO_BSRR_BR5_Pos (21U)
3229 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
3230 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
3231 #define GPIO_BSRR_BR6_Pos (22U)
3232 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
3233 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
3234 #define GPIO_BSRR_BR7_Pos (23U)
3235 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
3236 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
3237 #define GPIO_BSRR_BR8_Pos (24U)
3238 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
3239 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
3240 #define GPIO_BSRR_BR9_Pos (25U)
3241 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
3242 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
3243 #define GPIO_BSRR_BR10_Pos (26U)
3244 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
3245 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
3246 #define GPIO_BSRR_BR11_Pos (27U)
3247 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
3248 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
3249 #define GPIO_BSRR_BR12_Pos (28U)
3250 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
3251 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
3252 #define GPIO_BSRR_BR13_Pos (29U)
3253 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
3254 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
3255 #define GPIO_BSRR_BR14_Pos (30U)
3256 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
3257 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
3258 #define GPIO_BSRR_BR15_Pos (31U)
3259 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
3260 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
3261
3262 /* Legacy defines */
3263 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
3264 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
3265 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
3266 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
3267 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
3268 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
3269 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
3270 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
3271 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
3272 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
3273 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
3274 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
3275 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
3276 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
3277 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
3278 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
3279 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
3280 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
3281 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
3282 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
3283 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
3284 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
3285 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
3286 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
3287 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
3288 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
3289 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
3290 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
3291 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
3292 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
3293 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
3294 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
3295 /****************** Bit definition for GPIO_LCKR register *********************/
3296 #define GPIO_LCKR_LCK0_Pos (0U)
3297 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
3298 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
3299 #define GPIO_LCKR_LCK1_Pos (1U)
3300 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
3301 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
3302 #define GPIO_LCKR_LCK2_Pos (2U)
3303 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
3304 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
3305 #define GPIO_LCKR_LCK3_Pos (3U)
3306 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
3307 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
3308 #define GPIO_LCKR_LCK4_Pos (4U)
3309 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
3310 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
3311 #define GPIO_LCKR_LCK5_Pos (5U)
3312 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
3313 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
3314 #define GPIO_LCKR_LCK6_Pos (6U)
3315 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
3316 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
3317 #define GPIO_LCKR_LCK7_Pos (7U)
3318 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
3319 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
3320 #define GPIO_LCKR_LCK8_Pos (8U)
3321 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
3322 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
3323 #define GPIO_LCKR_LCK9_Pos (9U)
3324 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
3325 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
3326 #define GPIO_LCKR_LCK10_Pos (10U)
3327 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
3328 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
3329 #define GPIO_LCKR_LCK11_Pos (11U)
3330 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
3331 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
3332 #define GPIO_LCKR_LCK12_Pos (12U)
3333 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
3334 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
3335 #define GPIO_LCKR_LCK13_Pos (13U)
3336 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
3337 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
3338 #define GPIO_LCKR_LCK14_Pos (14U)
3339 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
3340 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
3341 #define GPIO_LCKR_LCK15_Pos (15U)
3342 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
3343 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
3344 #define GPIO_LCKR_LCKK_Pos (16U)
3345 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
3346 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
3347 /****************** Bit definition for GPIO_AFRL register *********************/
3348 #define GPIO_AFRL_AFSEL0_Pos (0U)
3349 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
3350 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
3351 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
3352 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
3353 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
3354 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
3355 #define GPIO_AFRL_AFSEL1_Pos (4U)
3356 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
3357 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
3358 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
3359 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
3360 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
3361 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
3362 #define GPIO_AFRL_AFSEL2_Pos (8U)
3363 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
3364 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
3365 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
3366 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
3367 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
3368 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
3369 #define GPIO_AFRL_AFSEL3_Pos (12U)
3370 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
3371 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
3372 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
3373 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
3374 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
3375 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
3376 #define GPIO_AFRL_AFSEL4_Pos (16U)
3377 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
3378 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
3379 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
3380 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
3381 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
3382 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
3383 #define GPIO_AFRL_AFSEL5_Pos (20U)
3384 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
3385 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
3386 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
3387 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
3388 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
3389 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
3390 #define GPIO_AFRL_AFSEL6_Pos (24U)
3391 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
3392 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
3393 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
3394 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
3395 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
3396 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
3397 #define GPIO_AFRL_AFSEL7_Pos (28U)
3398 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
3399 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
3400 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
3401 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
3402 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
3403 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
3404
3405 /* Legacy defines */
3406 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
3407 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
3408 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
3409 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
3410 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
3411 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
3412 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
3413 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
3414 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
3415 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
3416 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
3417 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
3418 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
3419 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
3420 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
3421 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
3422 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
3423 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
3424 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
3425 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
3426 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
3427 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
3428 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
3429 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
3430 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
3431 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
3432 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
3433 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
3434 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
3435 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
3436 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
3437 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
3438 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
3439 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
3440 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
3441 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
3442 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
3443 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
3444 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
3445 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
3446
3447 /****************** Bit definition for GPIO_AFRH register *********************/
3448 #define GPIO_AFRH_AFSEL8_Pos (0U)
3449 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
3450 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
3451 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
3452 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
3453 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
3454 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
3455 #define GPIO_AFRH_AFSEL9_Pos (4U)
3456 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
3457 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
3458 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
3459 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
3460 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
3461 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
3462 #define GPIO_AFRH_AFSEL10_Pos (8U)
3463 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
3464 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
3465 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
3466 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
3467 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
3468 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
3469 #define GPIO_AFRH_AFSEL11_Pos (12U)
3470 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
3471 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
3472 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
3473 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
3474 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
3475 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
3476 #define GPIO_AFRH_AFSEL12_Pos (16U)
3477 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
3478 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
3479 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
3480 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
3481 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
3482 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
3483 #define GPIO_AFRH_AFSEL13_Pos (20U)
3484 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
3485 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
3486 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
3487 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
3488 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
3489 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
3490 #define GPIO_AFRH_AFSEL14_Pos (24U)
3491 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
3492 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
3493 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
3494 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
3495 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
3496 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
3497 #define GPIO_AFRH_AFSEL15_Pos (28U)
3498 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
3499 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
3500 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
3501 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
3502 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
3503 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
3504
3505 /* Legacy defines */
3506 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
3507 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
3508 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
3509 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
3510 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
3511 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
3512 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
3513 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
3514 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
3515 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
3516 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
3517 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
3518 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
3519 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
3520 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
3521 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
3522 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
3523 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
3524 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
3525 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
3526 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
3527 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
3528 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
3529 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
3530 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
3531 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
3532 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
3533 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
3534 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
3535 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
3536 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
3537 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
3538 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
3539 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
3540 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
3541 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
3542 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
3543 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
3544 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
3545 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
3546
3547 /****************** Bits definition for GPIO_BRR register ******************/
3548 #define GPIO_BRR_BR0_Pos (0U)
3549 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
3550 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
3551 #define GPIO_BRR_BR1_Pos (1U)
3552 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
3553 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
3554 #define GPIO_BRR_BR2_Pos (2U)
3555 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
3556 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
3557 #define GPIO_BRR_BR3_Pos (3U)
3558 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
3559 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
3560 #define GPIO_BRR_BR4_Pos (4U)
3561 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
3562 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
3563 #define GPIO_BRR_BR5_Pos (5U)
3564 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
3565 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
3566 #define GPIO_BRR_BR6_Pos (6U)
3567 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
3568 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
3569 #define GPIO_BRR_BR7_Pos (7U)
3570 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
3571 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
3572 #define GPIO_BRR_BR8_Pos (8U)
3573 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
3574 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
3575 #define GPIO_BRR_BR9_Pos (9U)
3576 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
3577 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
3578 #define GPIO_BRR_BR10_Pos (10U)
3579 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
3580 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
3581 #define GPIO_BRR_BR11_Pos (11U)
3582 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
3583 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
3584 #define GPIO_BRR_BR12_Pos (12U)
3585 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
3586 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
3587 #define GPIO_BRR_BR13_Pos (13U)
3588 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
3589 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
3590 #define GPIO_BRR_BR14_Pos (14U)
3591 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
3592 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
3593 #define GPIO_BRR_BR15_Pos (15U)
3594 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
3595 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
3596
3597
3598 /******************************************************************************/
3599 /* */
3600 /* Inter-integrated Circuit Interface */
3601 /* */
3602 /******************************************************************************/
3603 /******************* Bit definition for I2C_CR1 register ********************/
3604 #define I2C_CR1_PE_Pos (0U)
3605 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
3606 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
3607 #define I2C_CR1_SMBUS_Pos (1U)
3608 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
3609 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
3610 #define I2C_CR1_SMBTYPE_Pos (3U)
3611 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
3612 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
3613 #define I2C_CR1_ENARP_Pos (4U)
3614 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
3615 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
3616 #define I2C_CR1_ENPEC_Pos (5U)
3617 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
3618 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
3619 #define I2C_CR1_ENGC_Pos (6U)
3620 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
3621 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
3622 #define I2C_CR1_NOSTRETCH_Pos (7U)
3623 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
3624 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
3625 #define I2C_CR1_START_Pos (8U)
3626 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
3627 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
3628 #define I2C_CR1_STOP_Pos (9U)
3629 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
3630 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
3631 #define I2C_CR1_ACK_Pos (10U)
3632 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
3633 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
3634 #define I2C_CR1_POS_Pos (11U)
3635 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
3636 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
3637 #define I2C_CR1_PEC_Pos (12U)
3638 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
3639 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
3640 #define I2C_CR1_ALERT_Pos (13U)
3641 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
3642 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
3643 #define I2C_CR1_SWRST_Pos (15U)
3644 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
3645 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
3646
3647 /******************* Bit definition for I2C_CR2 register ********************/
3648 #define I2C_CR2_FREQ_Pos (0U)
3649 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
3650 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
3651 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
3652 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
3653 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
3654 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
3655 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
3656 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
3657
3658 #define I2C_CR2_ITERREN_Pos (8U)
3659 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
3660 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
3661 #define I2C_CR2_ITEVTEN_Pos (9U)
3662 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
3663 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
3664 #define I2C_CR2_ITBUFEN_Pos (10U)
3665 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
3666 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
3667 #define I2C_CR2_DMAEN_Pos (11U)
3668 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
3669 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
3670 #define I2C_CR2_LAST_Pos (12U)
3671 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
3672 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
3673
3674 /******************* Bit definition for I2C_OAR1 register *******************/
3675 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
3676 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
3677
3678 #define I2C_OAR1_ADD0_Pos (0U)
3679 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
3680 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
3681 #define I2C_OAR1_ADD1_Pos (1U)
3682 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
3683 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
3684 #define I2C_OAR1_ADD2_Pos (2U)
3685 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
3686 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
3687 #define I2C_OAR1_ADD3_Pos (3U)
3688 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
3689 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
3690 #define I2C_OAR1_ADD4_Pos (4U)
3691 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
3692 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
3693 #define I2C_OAR1_ADD5_Pos (5U)
3694 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
3695 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
3696 #define I2C_OAR1_ADD6_Pos (6U)
3697 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
3698 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
3699 #define I2C_OAR1_ADD7_Pos (7U)
3700 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
3701 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
3702 #define I2C_OAR1_ADD8_Pos (8U)
3703 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
3704 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
3705 #define I2C_OAR1_ADD9_Pos (9U)
3706 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
3707 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
3708
3709 #define I2C_OAR1_ADDMODE_Pos (15U)
3710 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
3711 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
3712
3713 /******************* Bit definition for I2C_OAR2 register *******************/
3714 #define I2C_OAR2_ENDUAL_Pos (0U)
3715 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
3716 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
3717 #define I2C_OAR2_ADD2_Pos (1U)
3718 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
3719 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
3720
3721 /******************** Bit definition for I2C_DR register ********************/
3722 #define I2C_DR_DR_Pos (0U)
3723 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
3724 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
3725
3726 /******************* Bit definition for I2C_SR1 register ********************/
3727 #define I2C_SR1_SB_Pos (0U)
3728 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
3729 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
3730 #define I2C_SR1_ADDR_Pos (1U)
3731 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
3732 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
3733 #define I2C_SR1_BTF_Pos (2U)
3734 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
3735 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
3736 #define I2C_SR1_ADD10_Pos (3U)
3737 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
3738 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
3739 #define I2C_SR1_STOPF_Pos (4U)
3740 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
3741 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
3742 #define I2C_SR1_RXNE_Pos (6U)
3743 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
3744 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
3745 #define I2C_SR1_TXE_Pos (7U)
3746 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
3747 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
3748 #define I2C_SR1_BERR_Pos (8U)
3749 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
3750 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
3751 #define I2C_SR1_ARLO_Pos (9U)
3752 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
3753 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
3754 #define I2C_SR1_AF_Pos (10U)
3755 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
3756 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
3757 #define I2C_SR1_OVR_Pos (11U)
3758 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
3759 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
3760 #define I2C_SR1_PECERR_Pos (12U)
3761 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
3762 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
3763 #define I2C_SR1_TIMEOUT_Pos (14U)
3764 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
3765 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
3766 #define I2C_SR1_SMBALERT_Pos (15U)
3767 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
3768 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
3769
3770 /******************* Bit definition for I2C_SR2 register ********************/
3771 #define I2C_SR2_MSL_Pos (0U)
3772 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
3773 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
3774 #define I2C_SR2_BUSY_Pos (1U)
3775 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
3776 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
3777 #define I2C_SR2_TRA_Pos (2U)
3778 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
3779 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
3780 #define I2C_SR2_GENCALL_Pos (4U)
3781 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
3782 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
3783 #define I2C_SR2_SMBDEFAULT_Pos (5U)
3784 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
3785 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
3786 #define I2C_SR2_SMBHOST_Pos (6U)
3787 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
3788 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
3789 #define I2C_SR2_DUALF_Pos (7U)
3790 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
3791 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
3792 #define I2C_SR2_PEC_Pos (8U)
3793 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
3794 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
3795
3796 /******************* Bit definition for I2C_CCR register ********************/
3797 #define I2C_CCR_CCR_Pos (0U)
3798 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
3799 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
3800 #define I2C_CCR_DUTY_Pos (14U)
3801 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
3802 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
3803 #define I2C_CCR_FS_Pos (15U)
3804 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
3805 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
3806
3807 /****************** Bit definition for I2C_TRISE register *******************/
3808 #define I2C_TRISE_TRISE_Pos (0U)
3809 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
3810 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
3811
3812 /****************** Bit definition for I2C_FLTR register *******************/
3813 #define I2C_FLTR_DNF_Pos (0U)
3814 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
3815 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
3816 #define I2C_FLTR_ANOFF_Pos (4U)
3817 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
3818 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
3819
3820 /******************************************************************************/
3821 /* */
3822 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
3823 /* */
3824 /******************************************************************************/
3825 /******************* Bit definition for I2C_CR1 register *******************/
3826 #define FMPI2C_CR1_PE_Pos (0U)
3827 #define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
3828 #define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
3829 #define FMPI2C_CR1_TXIE_Pos (1U)
3830 #define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
3831 #define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
3832 #define FMPI2C_CR1_RXIE_Pos (2U)
3833 #define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
3834 #define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
3835 #define FMPI2C_CR1_ADDRIE_Pos (3U)
3836 #define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
3837 #define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
3838 #define FMPI2C_CR1_NACKIE_Pos (4U)
3839 #define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
3840 #define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
3841 #define FMPI2C_CR1_STOPIE_Pos (5U)
3842 #define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
3843 #define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
3844 #define FMPI2C_CR1_TCIE_Pos (6U)
3845 #define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
3846 #define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
3847 #define FMPI2C_CR1_ERRIE_Pos (7U)
3848 #define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
3849 #define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
3850 #define FMPI2C_CR1_DFN_Pos (8U)
3851 #define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
3852 #define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
3853 #define FMPI2C_CR1_ANFOFF_Pos (12U)
3854 #define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
3855 #define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
3856 #define FMPI2C_CR1_TXDMAEN_Pos (14U)
3857 #define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
3858 #define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
3859 #define FMPI2C_CR1_RXDMAEN_Pos (15U)
3860 #define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
3861 #define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
3862 #define FMPI2C_CR1_SBC_Pos (16U)
3863 #define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
3864 #define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
3865 #define FMPI2C_CR1_NOSTRETCH_Pos (17U)
3866 #define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
3867 #define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
3868 #define FMPI2C_CR1_GCEN_Pos (19U)
3869 #define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
3870 #define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
3871 #define FMPI2C_CR1_ALERTEN_Pos (22U)
3872 #define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
3873 #define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
3874 #define FMPI2C_CR1_PECEN_Pos (23U)
3875 #define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
3876 #define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
3877
3878 /****************** Bit definition for I2C_CR2 register ********************/
3879 #define FMPI2C_CR2_SADD_Pos (0U)
3880 #define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
3881 #define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
3882 #define FMPI2C_CR2_RD_WRN_Pos (10U)
3883 #define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
3884 #define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
3885 #define FMPI2C_CR2_ADD10_Pos (11U)
3886 #define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
3887 #define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
3888 #define FMPI2C_CR2_HEAD10R_Pos (12U)
3889 #define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
3890 #define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
3891 #define FMPI2C_CR2_START_Pos (13U)
3892 #define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
3893 #define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
3894 #define FMPI2C_CR2_STOP_Pos (14U)
3895 #define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
3896 #define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
3897 #define FMPI2C_CR2_NACK_Pos (15U)
3898 #define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
3899 #define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
3900 #define FMPI2C_CR2_NBYTES_Pos (16U)
3901 #define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
3902 #define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
3903 #define FMPI2C_CR2_RELOAD_Pos (24U)
3904 #define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
3905 #define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
3906 #define FMPI2C_CR2_AUTOEND_Pos (25U)
3907 #define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
3908 #define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
3909 #define FMPI2C_CR2_PECBYTE_Pos (26U)
3910 #define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
3911 #define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
3912
3913 /******************* Bit definition for I2C_OAR1 register ******************/
3914 #define FMPI2C_OAR1_OA1_Pos (0U)
3915 #define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
3916 #define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
3917 #define FMPI2C_OAR1_OA1MODE_Pos (10U)
3918 #define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
3919 #define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
3920 #define FMPI2C_OAR1_OA1EN_Pos (15U)
3921 #define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
3922 #define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
3923
3924 /******************* Bit definition for I2C_OAR2 register ******************/
3925 #define FMPI2C_OAR2_OA2_Pos (1U)
3926 #define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
3927 #define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
3928 #define FMPI2C_OAR2_OA2MSK_Pos (8U)
3929 #define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
3930 #define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
3931 #define FMPI2C_OAR2_OA2EN_Pos (15U)
3932 #define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
3933 #define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
3934
3935 /******************* Bit definition for I2C_TIMINGR register *******************/
3936 #define FMPI2C_TIMINGR_SCLL_Pos (0U)
3937 #define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
3938 #define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
3939 #define FMPI2C_TIMINGR_SCLH_Pos (8U)
3940 #define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
3941 #define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
3942 #define FMPI2C_TIMINGR_SDADEL_Pos (16U)
3943 #define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
3944 #define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
3945 #define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
3946 #define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
3947 #define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
3948 #define FMPI2C_TIMINGR_PRESC_Pos (28U)
3949 #define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
3950 #define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
3951
3952 /******************* Bit definition for I2C_TIMEOUTR register *******************/
3953 #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
3954 #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
3955 #define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
3956 #define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
3957 #define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
3958 #define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
3959 #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
3960 #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
3961 #define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
3962 #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
3963 #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
3964 #define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
3965 #define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
3966 #define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
3967 #define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
3968
3969 /****************** Bit definition for I2C_ISR register *********************/
3970 #define FMPI2C_ISR_TXE_Pos (0U)
3971 #define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
3972 #define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
3973 #define FMPI2C_ISR_TXIS_Pos (1U)
3974 #define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
3975 #define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
3976 #define FMPI2C_ISR_RXNE_Pos (2U)
3977 #define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
3978 #define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
3979 #define FMPI2C_ISR_ADDR_Pos (3U)
3980 #define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
3981 #define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
3982 #define FMPI2C_ISR_NACKF_Pos (4U)
3983 #define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
3984 #define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
3985 #define FMPI2C_ISR_STOPF_Pos (5U)
3986 #define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
3987 #define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
3988 #define FMPI2C_ISR_TC_Pos (6U)
3989 #define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
3990 #define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
3991 #define FMPI2C_ISR_TCR_Pos (7U)
3992 #define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
3993 #define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
3994 #define FMPI2C_ISR_BERR_Pos (8U)
3995 #define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
3996 #define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
3997 #define FMPI2C_ISR_ARLO_Pos (9U)
3998 #define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
3999 #define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
4000 #define FMPI2C_ISR_OVR_Pos (10U)
4001 #define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
4002 #define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
4003 #define FMPI2C_ISR_PECERR_Pos (11U)
4004 #define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
4005 #define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
4006 #define FMPI2C_ISR_TIMEOUT_Pos (12U)
4007 #define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
4008 #define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
4009 #define FMPI2C_ISR_ALERT_Pos (13U)
4010 #define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
4011 #define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
4012 #define FMPI2C_ISR_BUSY_Pos (15U)
4013 #define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
4014 #define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
4015 #define FMPI2C_ISR_DIR_Pos (16U)
4016 #define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
4017 #define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
4018 #define FMPI2C_ISR_ADDCODE_Pos (17U)
4019 #define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
4020 #define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
4021
4022 /****************** Bit definition for I2C_ICR register *********************/
4023 #define FMPI2C_ICR_ADDRCF_Pos (3U)
4024 #define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
4025 #define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
4026 #define FMPI2C_ICR_NACKCF_Pos (4U)
4027 #define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
4028 #define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
4029 #define FMPI2C_ICR_STOPCF_Pos (5U)
4030 #define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
4031 #define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
4032 #define FMPI2C_ICR_BERRCF_Pos (8U)
4033 #define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
4034 #define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
4035 #define FMPI2C_ICR_ARLOCF_Pos (9U)
4036 #define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
4037 #define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
4038 #define FMPI2C_ICR_OVRCF_Pos (10U)
4039 #define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
4040 #define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
4041 #define FMPI2C_ICR_PECCF_Pos (11U)
4042 #define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
4043 #define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
4044 #define FMPI2C_ICR_TIMOUTCF_Pos (12U)
4045 #define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
4046 #define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
4047 #define FMPI2C_ICR_ALERTCF_Pos (13U)
4048 #define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
4049 #define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
4050
4051 /****************** Bit definition for I2C_PECR register *********************/
4052 #define FMPI2C_PECR_PEC_Pos (0U)
4053 #define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
4054 #define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
4055
4056 /****************** Bit definition for I2C_RXDR register *********************/
4057 #define FMPI2C_RXDR_RXDATA_Pos (0U)
4058 #define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
4059 #define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
4060
4061 /****************** Bit definition for I2C_TXDR register *********************/
4062 #define FMPI2C_TXDR_TXDATA_Pos (0U)
4063 #define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
4064 #define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
4065
4066
4067
4068 /******************************************************************************/
4069 /* */
4070 /* Independent WATCHDOG */
4071 /* */
4072 /******************************************************************************/
4073 /******************* Bit definition for IWDG_KR register ********************/
4074 #define IWDG_KR_KEY_Pos (0U)
4075 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
4076 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
4077
4078 /******************* Bit definition for IWDG_PR register ********************/
4079 #define IWDG_PR_PR_Pos (0U)
4080 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
4081 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
4082 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
4083 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
4084 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
4085
4086 /******************* Bit definition for IWDG_RLR register *******************/
4087 #define IWDG_RLR_RL_Pos (0U)
4088 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
4089 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
4090
4091 /******************* Bit definition for IWDG_SR register ********************/
4092 #define IWDG_SR_PVU_Pos (0U)
4093 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
4094 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
4095 #define IWDG_SR_RVU_Pos (1U)
4096 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
4097 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
4098
4099
4100
4101 /******************************************************************************/
4102 /* */
4103 /* Power Control */
4104 /* */
4105 /******************************************************************************/
4106 /******************** Bit definition for PWR_CR register ********************/
4107 #define PWR_CR_LPDS_Pos (0U)
4108 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
4109 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
4110 #define PWR_CR_PDDS_Pos (1U)
4111 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
4112 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
4113 #define PWR_CR_CWUF_Pos (2U)
4114 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
4115 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
4116 #define PWR_CR_CSBF_Pos (3U)
4117 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
4118 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
4119 #define PWR_CR_PVDE_Pos (4U)
4120 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
4121 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
4122
4123 #define PWR_CR_PLS_Pos (5U)
4124 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
4125 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
4126 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
4127 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
4128 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
4129
4130 /*!< PVD level configuration */
4131 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
4132 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
4133 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
4134 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
4135 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
4136 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
4137 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
4138 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
4139 #define PWR_CR_DBP_Pos (8U)
4140 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
4141 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
4142 #define PWR_CR_FPDS_Pos (9U)
4143 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
4144 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
4145 #define PWR_CR_LPLVDS_Pos (10U)
4146 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
4147 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
4148 #define PWR_CR_MRLVDS_Pos (11U)
4149 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
4150 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
4151 #define PWR_CR_ADCDC1_Pos (13U)
4152 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
4153 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
4154 #define PWR_CR_VOS_Pos (14U)
4155 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
4156 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
4157 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
4158 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
4159 #define PWR_CR_FMSSR_Pos (20U)
4160 #define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
4161 #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
4162 #define PWR_CR_FISSR_Pos (21U)
4163 #define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
4164 #define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
4165
4166 /* Legacy define */
4167 #define PWR_CR_PMODE PWR_CR_VOS
4168
4169 /******************* Bit definition for PWR_CSR register ********************/
4170 #define PWR_CSR_WUF_Pos (0U)
4171 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
4172 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
4173 #define PWR_CSR_SBF_Pos (1U)
4174 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
4175 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
4176 #define PWR_CSR_PVDO_Pos (2U)
4177 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
4178 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
4179 #define PWR_CSR_BRR_Pos (3U)
4180 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
4181 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
4182 #define PWR_CSR_EWUP3_Pos (6U)
4183 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
4184 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
4185 #define PWR_CSR_EWUP2_Pos (7U)
4186 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
4187 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
4188 #define PWR_CSR_EWUP1_Pos (8U)
4189 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
4190 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
4191 #define PWR_CSR_BRE_Pos (9U)
4192 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
4193 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
4194 #define PWR_CSR_VOSRDY_Pos (14U)
4195 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
4196 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
4197
4198 /* Legacy define */
4199 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
4200
4201 /******************************************************************************/
4202 /* */
4203 /* Reset and Clock Control */
4204 /* */
4205 /******************************************************************************/
4206 /******************** Bit definition for RCC_CR register ********************/
4207 #define RCC_CR_HSION_Pos (0U)
4208 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
4209 #define RCC_CR_HSION RCC_CR_HSION_Msk
4210 #define RCC_CR_HSIRDY_Pos (1U)
4211 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
4212 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
4213
4214 #define RCC_CR_HSITRIM_Pos (3U)
4215 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
4216 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
4217 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
4218 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
4219 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
4220 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
4221 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
4222
4223 #define RCC_CR_HSICAL_Pos (8U)
4224 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
4225 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
4226 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
4227 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
4228 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
4229 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
4230 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
4231 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
4232 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
4233 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
4234
4235 #define RCC_CR_HSEON_Pos (16U)
4236 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
4237 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
4238 #define RCC_CR_HSERDY_Pos (17U)
4239 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
4240 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
4241 #define RCC_CR_HSEBYP_Pos (18U)
4242 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
4243 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
4244 #define RCC_CR_CSSON_Pos (19U)
4245 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
4246 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
4247 #define RCC_CR_PLLON_Pos (24U)
4248 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
4249 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
4250 #define RCC_CR_PLLRDY_Pos (25U)
4251 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
4252 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
4253
4254 /******************** Bit definition for RCC_PLLCFGR register ***************/
4255 #define RCC_PLLCFGR_PLLM_Pos (0U)
4256 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
4257 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
4258 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
4259 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
4260 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
4261 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
4262 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
4263 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
4264
4265 #define RCC_PLLCFGR_PLLN_Pos (6U)
4266 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
4267 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
4268 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
4269 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
4270 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
4271 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
4272 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
4273 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
4274 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
4275 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
4276 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
4277
4278 #define RCC_PLLCFGR_PLLP_Pos (16U)
4279 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
4280 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
4281 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
4282 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
4283
4284 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
4285 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
4286 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
4287 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
4288 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
4289 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
4290 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
4291
4292 #define RCC_PLLCFGR_PLLQ_Pos (24U)
4293 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
4294 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
4295 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
4296 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
4297 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
4298 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
4299 /*
4300 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
4301 */
4302 #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
4303
4304 #define RCC_PLLCFGR_PLLR_Pos (28U)
4305 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
4306 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
4307 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
4308 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
4309 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
4310
4311 /******************** Bit definition for RCC_CFGR register ******************/
4312 /*!< SW configuration */
4313 #define RCC_CFGR_SW_Pos (0U)
4314 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
4315 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
4316 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
4317 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
4318
4319 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
4320 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
4321 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
4322
4323 /*!< SWS configuration */
4324 #define RCC_CFGR_SWS_Pos (2U)
4325 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
4326 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
4327 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
4328 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
4329
4330 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
4331 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
4332 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
4333
4334 /*!< HPRE configuration */
4335 #define RCC_CFGR_HPRE_Pos (4U)
4336 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
4337 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
4338 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
4339 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
4340 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
4341 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
4342
4343 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
4344 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
4345 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
4346 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
4347 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
4348 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
4349 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
4350 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
4351 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
4352 /*!< MCO1EN configuration */
4353 #define RCC_CFGR_MCO1EN_Pos (8U)
4354 #define RCC_CFGR_MCO1EN_Msk (0x1U << RCC_CFGR_MCO1EN_Pos) /*!< 0x00000100 */
4355 #define RCC_CFGR_MCO1EN RCC_CFGR_MCO1EN_Msk /*!< MCO1EN bit */
4356
4357 /*!< PPRE1 configuration */
4358 #define RCC_CFGR_PPRE1_Pos (10U)
4359 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
4360 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
4361 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
4362 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
4363 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
4364
4365 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
4366 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
4367 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
4368 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
4369 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
4370
4371 /*!< PPRE2 configuration */
4372 #define RCC_CFGR_PPRE2_Pos (13U)
4373 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
4374 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
4375 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
4376 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
4377 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
4378
4379 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
4380 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
4381 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
4382 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
4383 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
4384
4385 /*!< RTCPRE configuration */
4386 #define RCC_CFGR_RTCPRE_Pos (16U)
4387 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
4388 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
4389 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
4390 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
4391 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
4392 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
4393 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
4394
4395 /*!< MCO1 configuration */
4396 #define RCC_CFGR_MCO1_Pos (21U)
4397 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
4398 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
4399 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
4400 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
4401
4402
4403 #define RCC_CFGR_MCO1PRE_Pos (24U)
4404 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
4405 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
4406 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
4407 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
4408 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
4409
4410 #define RCC_CFGR_MCO2PRE_Pos (27U)
4411 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
4412 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
4413 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
4414 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
4415 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
4416
4417 #define RCC_CFGR_MCO2_Pos (30U)
4418 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
4419 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
4420 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
4421 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
4422
4423 /******************** Bit definition for RCC_CIR register *******************/
4424 #define RCC_CIR_LSIRDYF_Pos (0U)
4425 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
4426 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
4427 #define RCC_CIR_LSERDYF_Pos (1U)
4428 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
4429 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
4430 #define RCC_CIR_HSIRDYF_Pos (2U)
4431 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
4432 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
4433 #define RCC_CIR_HSERDYF_Pos (3U)
4434 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
4435 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
4436 #define RCC_CIR_PLLRDYF_Pos (4U)
4437 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
4438 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
4439
4440 #define RCC_CIR_CSSF_Pos (7U)
4441 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
4442 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
4443 #define RCC_CIR_LSIRDYIE_Pos (8U)
4444 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
4445 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
4446 #define RCC_CIR_LSERDYIE_Pos (9U)
4447 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
4448 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
4449 #define RCC_CIR_HSIRDYIE_Pos (10U)
4450 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
4451 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
4452 #define RCC_CIR_HSERDYIE_Pos (11U)
4453 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
4454 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
4455 #define RCC_CIR_PLLRDYIE_Pos (12U)
4456 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
4457 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
4458
4459 #define RCC_CIR_LSIRDYC_Pos (16U)
4460 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
4461 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
4462 #define RCC_CIR_LSERDYC_Pos (17U)
4463 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
4464 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
4465 #define RCC_CIR_HSIRDYC_Pos (18U)
4466 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
4467 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
4468 #define RCC_CIR_HSERDYC_Pos (19U)
4469 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
4470 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
4471 #define RCC_CIR_PLLRDYC_Pos (20U)
4472 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
4473 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
4474
4475 #define RCC_CIR_CSSC_Pos (23U)
4476 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
4477 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
4478
4479 /******************** Bit definition for RCC_AHB1RSTR register **************/
4480 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
4481 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
4482 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
4483 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
4484 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
4485 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
4486 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
4487 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
4488 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
4489 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
4490 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
4491 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
4492 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
4493 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
4494 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
4495 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
4496 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
4497 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
4498 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
4499 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
4500 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
4501 #define RCC_AHB1RSTR_RNGRST_Pos (31U)
4502 #define RCC_AHB1RSTR_RNGRST_Msk (0x1U << RCC_AHB1RSTR_RNGRST_Pos) /*!< 0x80000000 */
4503 #define RCC_AHB1RSTR_RNGRST RCC_AHB1RSTR_RNGRST_Msk
4504
4505
4506 /******************** Bit definition for RCC_APB1RSTR register **************/
4507 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
4508 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
4509 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
4510 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
4511 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
4512 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
4513 #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
4514 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
4515 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
4516 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
4517 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
4518 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
4519 #define RCC_APB1RSTR_USART2RST_Pos (17U)
4520 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
4521 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
4522 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
4523 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
4524 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
4525 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
4526 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
4527 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
4528 #define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
4529 #define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
4530 #define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
4531 #define RCC_APB1RSTR_PWRRST_Pos (28U)
4532 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
4533 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
4534 #define RCC_APB1RSTR_DACRST_Pos (29U)
4535 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
4536 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
4537
4538 /******************** Bit definition for RCC_APB2RSTR register **************/
4539 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
4540 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
4541 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
4542 #define RCC_APB2RSTR_USART1RST_Pos (4U)
4543 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
4544 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
4545 #define RCC_APB2RSTR_ADCRST_Pos (8U)
4546 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
4547 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
4548 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
4549 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
4550 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
4551 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
4552 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
4553 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
4554 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
4555 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
4556 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
4557 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
4558 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
4559 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
4560
4561 /******************** Bit definition for RCC_AHB1ENR register ***************/
4562 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
4563 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
4564 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
4565 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
4566 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
4567 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
4568 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
4569 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
4570 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
4571 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
4572 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
4573 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
4574 #define RCC_AHB1ENR_CRCEN_Pos (12U)
4575 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
4576 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
4577 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
4578 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
4579 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
4580 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
4581 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
4582 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
4583 #define RCC_AHB1ENR_RNGEN_Pos (31U)
4584 #define RCC_AHB1ENR_RNGEN_Msk (0x1U << RCC_AHB1ENR_RNGEN_Pos) /*!< 0x80000000 */
4585 #define RCC_AHB1ENR_RNGEN RCC_AHB1ENR_RNGEN_Msk
4586
4587 /******************** Bit definition for RCC_APB1ENR register ***************/
4588 #define RCC_APB1ENR_TIM5EN_Pos (3U)
4589 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
4590 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
4591 #define RCC_APB1ENR_TIM6EN_Pos (4U)
4592 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
4593 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
4594 #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
4595 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
4596 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
4597 #define RCC_APB1ENR_RTCAPBEN_Pos (10U)
4598 #define RCC_APB1ENR_RTCAPBEN_Msk (0x1U << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
4599 #define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
4600 #define RCC_APB1ENR_WWDGEN_Pos (11U)
4601 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
4602 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
4603 #define RCC_APB1ENR_USART2EN_Pos (17U)
4604 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
4605 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
4606 #define RCC_APB1ENR_I2C1EN_Pos (21U)
4607 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
4608 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
4609 #define RCC_APB1ENR_I2C2EN_Pos (22U)
4610 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
4611 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
4612 #define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
4613 #define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
4614 #define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
4615 #define RCC_APB1ENR_PWREN_Pos (28U)
4616 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
4617 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
4618 #define RCC_APB1ENR_DACEN_Pos (29U)
4619 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
4620 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
4621
4622 /******************** Bit definition for RCC_APB2ENR register ***************/
4623 #define RCC_APB2ENR_TIM1EN_Pos (0U)
4624 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
4625 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
4626 #define RCC_APB2ENR_USART1EN_Pos (4U)
4627 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
4628 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
4629 #define RCC_APB2ENR_ADC1EN_Pos (8U)
4630 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
4631 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
4632 #define RCC_APB2ENR_SPI1EN_Pos (12U)
4633 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
4634 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
4635 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
4636 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
4637 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
4638 #define RCC_APB2ENR_EXTITEN_Pos (15U)
4639 #define RCC_APB2ENR_EXTITEN_Msk (0x1U << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
4640 #define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
4641 #define RCC_APB2ENR_TIM9EN_Pos (16U)
4642 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
4643 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
4644 #define RCC_APB2ENR_TIM11EN_Pos (18U)
4645 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
4646 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
4647
4648 /******************** Bit definition for RCC_AHB1LPENR register *************/
4649 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
4650 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
4651 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
4652 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
4653 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
4654 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
4655 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
4656 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
4657 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
4658 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
4659 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
4660 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
4661 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
4662 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
4663 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
4664 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
4665 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
4666 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
4667 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
4668 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
4669 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
4670 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
4671 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
4672 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
4673 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
4674 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
4675 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
4676 #define RCC_AHB1LPENR_RNGLPEN_Pos (31U)
4677 #define RCC_AHB1LPENR_RNGLPEN_Msk (0x1U << RCC_AHB1LPENR_RNGLPEN_Pos) /*!< 0x80000000 */
4678 #define RCC_AHB1LPENR_RNGLPEN RCC_AHB1LPENR_RNGLPEN_Msk
4679
4680 /******************** Bit definition for RCC_APB1LPENR register *************/
4681 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
4682 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
4683 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
4684 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
4685 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
4686 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
4687 #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
4688 #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
4689 #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
4690 #define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
4691 #define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1U << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
4692 #define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
4693 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
4694 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
4695 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
4696 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
4697 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
4698 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
4699 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
4700 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
4701 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
4702 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
4703 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
4704 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
4705 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
4706 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
4707 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
4708 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
4709 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
4710 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
4711
4712 /******************** Bit definition for RCC_APB2LPENR register *************/
4713 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
4714 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
4715 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
4716 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
4717 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
4718 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
4719 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
4720 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
4721 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
4722 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
4723 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
4724 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
4725 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
4726 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
4727 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
4728 #define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
4729 #define RCC_APB2LPENR_EXTITLPEN_Msk (0x1U << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
4730 #define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
4731 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
4732 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
4733 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
4734 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
4735 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
4736 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
4737
4738 /******************** Bit definition for RCC_BDCR register ******************/
4739 #define RCC_BDCR_LSEON_Pos (0U)
4740 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
4741 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
4742 #define RCC_BDCR_LSERDY_Pos (1U)
4743 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
4744 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
4745 #define RCC_BDCR_LSEBYP_Pos (2U)
4746 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
4747 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
4748 #define RCC_BDCR_LSEMOD_Pos (3U)
4749 #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
4750 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
4751
4752 #define RCC_BDCR_RTCSEL_Pos (8U)
4753 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
4754 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
4755 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
4756 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
4757
4758 #define RCC_BDCR_RTCEN_Pos (15U)
4759 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
4760 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
4761 #define RCC_BDCR_BDRST_Pos (16U)
4762 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
4763 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
4764
4765 /******************** Bit definition for RCC_CSR register *******************/
4766 #define RCC_CSR_LSION_Pos (0U)
4767 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
4768 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
4769 #define RCC_CSR_LSIRDY_Pos (1U)
4770 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
4771 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
4772 #define RCC_CSR_RMVF_Pos (24U)
4773 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
4774 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
4775 #define RCC_CSR_BORRSTF_Pos (25U)
4776 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
4777 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
4778 #define RCC_CSR_PINRSTF_Pos (26U)
4779 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
4780 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
4781 #define RCC_CSR_PORRSTF_Pos (27U)
4782 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
4783 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
4784 #define RCC_CSR_SFTRSTF_Pos (28U)
4785 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
4786 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
4787 #define RCC_CSR_IWDGRSTF_Pos (29U)
4788 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
4789 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
4790 #define RCC_CSR_WWDGRSTF_Pos (30U)
4791 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
4792 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
4793 #define RCC_CSR_LPWRRSTF_Pos (31U)
4794 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
4795 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
4796 /* Legacy defines */
4797 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
4798 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
4799
4800 /******************** Bit definition for RCC_SSCGR register *****************/
4801 #define RCC_SSCGR_MODPER_Pos (0U)
4802 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
4803 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
4804 #define RCC_SSCGR_INCSTEP_Pos (13U)
4805 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
4806 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
4807 #define RCC_SSCGR_SPREADSEL_Pos (30U)
4808 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
4809 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
4810 #define RCC_SSCGR_SSCGEN_Pos (31U)
4811 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
4812 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
4813
4814 /******************** Bit definition for RCC_DCKCFGR register ***************/
4815
4816 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
4817 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
4818 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
4819 #define RCC_DCKCFGR_I2SSRC_Pos (25U)
4820 #define RCC_DCKCFGR_I2SSRC_Msk (0x3U << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x06000000 */
4821 #define RCC_DCKCFGR_I2SSRC RCC_DCKCFGR_I2SSRC_Msk
4822 #define RCC_DCKCFGR_I2SSRC_0 (0x1U << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x02000000 */
4823 #define RCC_DCKCFGR_I2SSRC_1 (0x2U << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x04000000 */
4824
4825 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
4826 #define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
4827 #define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
4828 #define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
4829 #define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
4830 #define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
4831 #define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
4832 #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
4833 #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
4834 #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
4835 #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
4836
4837
4838 /******************************************************************************/
4839 /* */
4840 /* RNG */
4841 /* */
4842 /******************************************************************************/
4843 /******************** Bits definition for RNG_CR register *******************/
4844 #define RNG_CR_RNGEN_Pos (2U)
4845 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
4846 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
4847 #define RNG_CR_IE_Pos (3U)
4848 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
4849 #define RNG_CR_IE RNG_CR_IE_Msk
4850
4851 /******************** Bits definition for RNG_SR register *******************/
4852 #define RNG_SR_DRDY_Pos (0U)
4853 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
4854 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
4855 #define RNG_SR_CECS_Pos (1U)
4856 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
4857 #define RNG_SR_CECS RNG_SR_CECS_Msk
4858 #define RNG_SR_SECS_Pos (2U)
4859 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
4860 #define RNG_SR_SECS RNG_SR_SECS_Msk
4861 #define RNG_SR_CEIS_Pos (5U)
4862 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
4863 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
4864 #define RNG_SR_SEIS_Pos (6U)
4865 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
4866 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
4867
4868 /******************************************************************************/
4869 /* */
4870 /* Real-Time Clock (RTC) */
4871 /* */
4872 /******************************************************************************/
4873 /*
4874 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
4875 */
4876 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
4877 /******************** Bits definition for RTC_TR register *******************/
4878 #define RTC_TR_PM_Pos (22U)
4879 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
4880 #define RTC_TR_PM RTC_TR_PM_Msk
4881 #define RTC_TR_HT_Pos (20U)
4882 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
4883 #define RTC_TR_HT RTC_TR_HT_Msk
4884 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
4885 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
4886 #define RTC_TR_HU_Pos (16U)
4887 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
4888 #define RTC_TR_HU RTC_TR_HU_Msk
4889 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
4890 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
4891 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
4892 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
4893 #define RTC_TR_MNT_Pos (12U)
4894 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
4895 #define RTC_TR_MNT RTC_TR_MNT_Msk
4896 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
4897 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
4898 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
4899 #define RTC_TR_MNU_Pos (8U)
4900 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
4901 #define RTC_TR_MNU RTC_TR_MNU_Msk
4902 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
4903 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
4904 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
4905 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
4906 #define RTC_TR_ST_Pos (4U)
4907 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
4908 #define RTC_TR_ST RTC_TR_ST_Msk
4909 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
4910 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
4911 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
4912 #define RTC_TR_SU_Pos (0U)
4913 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
4914 #define RTC_TR_SU RTC_TR_SU_Msk
4915 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
4916 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
4917 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
4918 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
4919
4920 /******************** Bits definition for RTC_DR register *******************/
4921 #define RTC_DR_YT_Pos (20U)
4922 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
4923 #define RTC_DR_YT RTC_DR_YT_Msk
4924 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
4925 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
4926 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
4927 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
4928 #define RTC_DR_YU_Pos (16U)
4929 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
4930 #define RTC_DR_YU RTC_DR_YU_Msk
4931 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
4932 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
4933 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
4934 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
4935 #define RTC_DR_WDU_Pos (13U)
4936 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
4937 #define RTC_DR_WDU RTC_DR_WDU_Msk
4938 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
4939 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
4940 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
4941 #define RTC_DR_MT_Pos (12U)
4942 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
4943 #define RTC_DR_MT RTC_DR_MT_Msk
4944 #define RTC_DR_MU_Pos (8U)
4945 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
4946 #define RTC_DR_MU RTC_DR_MU_Msk
4947 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
4948 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
4949 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
4950 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
4951 #define RTC_DR_DT_Pos (4U)
4952 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
4953 #define RTC_DR_DT RTC_DR_DT_Msk
4954 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
4955 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
4956 #define RTC_DR_DU_Pos (0U)
4957 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
4958 #define RTC_DR_DU RTC_DR_DU_Msk
4959 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
4960 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
4961 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
4962 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
4963
4964 /******************** Bits definition for RTC_CR register *******************/
4965 #define RTC_CR_COE_Pos (23U)
4966 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
4967 #define RTC_CR_COE RTC_CR_COE_Msk
4968 #define RTC_CR_OSEL_Pos (21U)
4969 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
4970 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
4971 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
4972 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
4973 #define RTC_CR_POL_Pos (20U)
4974 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
4975 #define RTC_CR_POL RTC_CR_POL_Msk
4976 #define RTC_CR_COSEL_Pos (19U)
4977 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
4978 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
4979 #define RTC_CR_BKP_Pos (18U)
4980 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
4981 #define RTC_CR_BKP RTC_CR_BKP_Msk
4982 #define RTC_CR_SUB1H_Pos (17U)
4983 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
4984 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
4985 #define RTC_CR_ADD1H_Pos (16U)
4986 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
4987 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
4988 #define RTC_CR_TSIE_Pos (15U)
4989 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
4990 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
4991 #define RTC_CR_WUTIE_Pos (14U)
4992 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
4993 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
4994 #define RTC_CR_ALRBIE_Pos (13U)
4995 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
4996 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
4997 #define RTC_CR_ALRAIE_Pos (12U)
4998 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
4999 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
5000 #define RTC_CR_TSE_Pos (11U)
5001 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
5002 #define RTC_CR_TSE RTC_CR_TSE_Msk
5003 #define RTC_CR_WUTE_Pos (10U)
5004 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
5005 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
5006 #define RTC_CR_ALRBE_Pos (9U)
5007 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
5008 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
5009 #define RTC_CR_ALRAE_Pos (8U)
5010 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
5011 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
5012 #define RTC_CR_DCE_Pos (7U)
5013 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
5014 #define RTC_CR_DCE RTC_CR_DCE_Msk
5015 #define RTC_CR_FMT_Pos (6U)
5016 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
5017 #define RTC_CR_FMT RTC_CR_FMT_Msk
5018 #define RTC_CR_BYPSHAD_Pos (5U)
5019 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
5020 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
5021 #define RTC_CR_REFCKON_Pos (4U)
5022 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
5023 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
5024 #define RTC_CR_TSEDGE_Pos (3U)
5025 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
5026 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
5027 #define RTC_CR_WUCKSEL_Pos (0U)
5028 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
5029 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
5030 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
5031 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
5032 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
5033
5034 /* Legacy defines */
5035 #define RTC_CR_BCK RTC_CR_BKP
5036
5037 /******************** Bits definition for RTC_ISR register ******************/
5038 #define RTC_ISR_RECALPF_Pos (16U)
5039 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
5040 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
5041 #define RTC_ISR_TAMP1F_Pos (13U)
5042 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
5043 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
5044 #define RTC_ISR_TAMP2F_Pos (14U)
5045 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
5046 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
5047 #define RTC_ISR_TSOVF_Pos (12U)
5048 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
5049 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
5050 #define RTC_ISR_TSF_Pos (11U)
5051 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
5052 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
5053 #define RTC_ISR_WUTF_Pos (10U)
5054 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
5055 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
5056 #define RTC_ISR_ALRBF_Pos (9U)
5057 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
5058 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
5059 #define RTC_ISR_ALRAF_Pos (8U)
5060 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
5061 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
5062 #define RTC_ISR_INIT_Pos (7U)
5063 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
5064 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
5065 #define RTC_ISR_INITF_Pos (6U)
5066 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
5067 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
5068 #define RTC_ISR_RSF_Pos (5U)
5069 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
5070 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
5071 #define RTC_ISR_INITS_Pos (4U)
5072 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
5073 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
5074 #define RTC_ISR_SHPF_Pos (3U)
5075 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
5076 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
5077 #define RTC_ISR_WUTWF_Pos (2U)
5078 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
5079 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
5080 #define RTC_ISR_ALRBWF_Pos (1U)
5081 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
5082 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
5083 #define RTC_ISR_ALRAWF_Pos (0U)
5084 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
5085 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
5086
5087 /******************** Bits definition for RTC_PRER register *****************/
5088 #define RTC_PRER_PREDIV_A_Pos (16U)
5089 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
5090 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
5091 #define RTC_PRER_PREDIV_S_Pos (0U)
5092 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
5093 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
5094
5095 /******************** Bits definition for RTC_WUTR register *****************/
5096 #define RTC_WUTR_WUT_Pos (0U)
5097 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
5098 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
5099
5100 /******************** Bits definition for RTC_CALIBR register ***************/
5101 #define RTC_CALIBR_DCS_Pos (7U)
5102 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
5103 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
5104 #define RTC_CALIBR_DC_Pos (0U)
5105 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
5106 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
5107
5108 /******************** Bits definition for RTC_ALRMAR register ***************/
5109 #define RTC_ALRMAR_MSK4_Pos (31U)
5110 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
5111 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
5112 #define RTC_ALRMAR_WDSEL_Pos (30U)
5113 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
5114 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
5115 #define RTC_ALRMAR_DT_Pos (28U)
5116 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
5117 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
5118 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
5119 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
5120 #define RTC_ALRMAR_DU_Pos (24U)
5121 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
5122 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
5123 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
5124 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
5125 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
5126 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
5127 #define RTC_ALRMAR_MSK3_Pos (23U)
5128 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
5129 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
5130 #define RTC_ALRMAR_PM_Pos (22U)
5131 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
5132 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
5133 #define RTC_ALRMAR_HT_Pos (20U)
5134 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
5135 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
5136 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
5137 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
5138 #define RTC_ALRMAR_HU_Pos (16U)
5139 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
5140 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
5141 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
5142 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
5143 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
5144 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
5145 #define RTC_ALRMAR_MSK2_Pos (15U)
5146 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
5147 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
5148 #define RTC_ALRMAR_MNT_Pos (12U)
5149 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
5150 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
5151 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
5152 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
5153 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
5154 #define RTC_ALRMAR_MNU_Pos (8U)
5155 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
5156 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
5157 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
5158 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
5159 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
5160 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
5161 #define RTC_ALRMAR_MSK1_Pos (7U)
5162 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
5163 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
5164 #define RTC_ALRMAR_ST_Pos (4U)
5165 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
5166 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
5167 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
5168 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
5169 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
5170 #define RTC_ALRMAR_SU_Pos (0U)
5171 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
5172 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
5173 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
5174 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
5175 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
5176 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
5177
5178 /******************** Bits definition for RTC_ALRMBR register ***************/
5179 #define RTC_ALRMBR_MSK4_Pos (31U)
5180 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
5181 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
5182 #define RTC_ALRMBR_WDSEL_Pos (30U)
5183 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
5184 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
5185 #define RTC_ALRMBR_DT_Pos (28U)
5186 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
5187 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
5188 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
5189 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
5190 #define RTC_ALRMBR_DU_Pos (24U)
5191 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
5192 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
5193 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
5194 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
5195 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
5196 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
5197 #define RTC_ALRMBR_MSK3_Pos (23U)
5198 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
5199 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
5200 #define RTC_ALRMBR_PM_Pos (22U)
5201 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
5202 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
5203 #define RTC_ALRMBR_HT_Pos (20U)
5204 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
5205 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
5206 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
5207 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
5208 #define RTC_ALRMBR_HU_Pos (16U)
5209 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
5210 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
5211 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
5212 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
5213 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
5214 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
5215 #define RTC_ALRMBR_MSK2_Pos (15U)
5216 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
5217 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
5218 #define RTC_ALRMBR_MNT_Pos (12U)
5219 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
5220 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
5221 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
5222 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
5223 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
5224 #define RTC_ALRMBR_MNU_Pos (8U)
5225 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
5226 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
5227 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
5228 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
5229 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
5230 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
5231 #define RTC_ALRMBR_MSK1_Pos (7U)
5232 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
5233 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
5234 #define RTC_ALRMBR_ST_Pos (4U)
5235 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
5236 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
5237 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
5238 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
5239 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
5240 #define RTC_ALRMBR_SU_Pos (0U)
5241 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
5242 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
5243 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
5244 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
5245 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
5246 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
5247
5248 /******************** Bits definition for RTC_WPR register ******************/
5249 #define RTC_WPR_KEY_Pos (0U)
5250 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
5251 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
5252
5253 /******************** Bits definition for RTC_SSR register ******************/
5254 #define RTC_SSR_SS_Pos (0U)
5255 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
5256 #define RTC_SSR_SS RTC_SSR_SS_Msk
5257
5258 /******************** Bits definition for RTC_SHIFTR register ***************/
5259 #define RTC_SHIFTR_SUBFS_Pos (0U)
5260 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
5261 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
5262 #define RTC_SHIFTR_ADD1S_Pos (31U)
5263 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
5264 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
5265
5266 /******************** Bits definition for RTC_TSTR register *****************/
5267 #define RTC_TSTR_PM_Pos (22U)
5268 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
5269 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
5270 #define RTC_TSTR_HT_Pos (20U)
5271 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
5272 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
5273 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
5274 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
5275 #define RTC_TSTR_HU_Pos (16U)
5276 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
5277 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
5278 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
5279 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
5280 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
5281 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
5282 #define RTC_TSTR_MNT_Pos (12U)
5283 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
5284 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
5285 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
5286 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
5287 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
5288 #define RTC_TSTR_MNU_Pos (8U)
5289 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
5290 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
5291 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
5292 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
5293 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
5294 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
5295 #define RTC_TSTR_ST_Pos (4U)
5296 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
5297 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
5298 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
5299 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
5300 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
5301 #define RTC_TSTR_SU_Pos (0U)
5302 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
5303 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
5304 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
5305 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
5306 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
5307 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
5308
5309 /******************** Bits definition for RTC_TSDR register *****************/
5310 #define RTC_TSDR_WDU_Pos (13U)
5311 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
5312 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
5313 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
5314 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
5315 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
5316 #define RTC_TSDR_MT_Pos (12U)
5317 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
5318 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
5319 #define RTC_TSDR_MU_Pos (8U)
5320 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
5321 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
5322 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
5323 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
5324 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
5325 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
5326 #define RTC_TSDR_DT_Pos (4U)
5327 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
5328 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
5329 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
5330 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
5331 #define RTC_TSDR_DU_Pos (0U)
5332 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
5333 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
5334 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
5335 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
5336 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
5337 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
5338
5339 /******************** Bits definition for RTC_TSSSR register ****************/
5340 #define RTC_TSSSR_SS_Pos (0U)
5341 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
5342 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
5343
5344 /******************** Bits definition for RTC_CAL register *****************/
5345 #define RTC_CALR_CALP_Pos (15U)
5346 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
5347 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
5348 #define RTC_CALR_CALW8_Pos (14U)
5349 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
5350 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
5351 #define RTC_CALR_CALW16_Pos (13U)
5352 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
5353 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
5354 #define RTC_CALR_CALM_Pos (0U)
5355 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
5356 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
5357 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
5358 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
5359 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
5360 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
5361 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
5362 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
5363 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
5364 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
5365 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
5366
5367 /******************** Bits definition for RTC_TAFCR register ****************/
5368 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
5369 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
5370 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
5371 #define RTC_TAFCR_TSINSEL_Pos (17U)
5372 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
5373 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
5374 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
5375 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
5376 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
5377 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
5378 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
5379 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
5380 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
5381 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
5382 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
5383 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
5384 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
5385 #define RTC_TAFCR_TAMPFLT_Pos (11U)
5386 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
5387 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
5388 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
5389 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
5390 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
5391 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
5392 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
5393 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
5394 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
5395 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
5396 #define RTC_TAFCR_TAMPTS_Pos (7U)
5397 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
5398 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
5399 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
5400 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
5401 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
5402 #define RTC_TAFCR_TAMP2E_Pos (3U)
5403 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
5404 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
5405 #define RTC_TAFCR_TAMPIE_Pos (2U)
5406 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
5407 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
5408 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
5409 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
5410 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
5411 #define RTC_TAFCR_TAMP1E_Pos (0U)
5412 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
5413 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
5414
5415 /* Legacy defines */
5416 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
5417
5418 /******************** Bits definition for RTC_ALRMASSR register *************/
5419 #define RTC_ALRMASSR_MASKSS_Pos (24U)
5420 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
5421 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
5422 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
5423 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
5424 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
5425 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
5426 #define RTC_ALRMASSR_SS_Pos (0U)
5427 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
5428 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
5429
5430 /******************** Bits definition for RTC_ALRMBSSR register *************/
5431 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
5432 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
5433 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
5434 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
5435 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
5436 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
5437 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
5438 #define RTC_ALRMBSSR_SS_Pos (0U)
5439 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
5440 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
5441
5442 /******************** Bits definition for RTC_BKP0R register ****************/
5443 #define RTC_BKP0R_Pos (0U)
5444 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
5445 #define RTC_BKP0R RTC_BKP0R_Msk
5446
5447 /******************** Bits definition for RTC_BKP1R register ****************/
5448 #define RTC_BKP1R_Pos (0U)
5449 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
5450 #define RTC_BKP1R RTC_BKP1R_Msk
5451
5452 /******************** Bits definition for RTC_BKP2R register ****************/
5453 #define RTC_BKP2R_Pos (0U)
5454 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
5455 #define RTC_BKP2R RTC_BKP2R_Msk
5456
5457 /******************** Bits definition for RTC_BKP3R register ****************/
5458 #define RTC_BKP3R_Pos (0U)
5459 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
5460 #define RTC_BKP3R RTC_BKP3R_Msk
5461
5462 /******************** Bits definition for RTC_BKP4R register ****************/
5463 #define RTC_BKP4R_Pos (0U)
5464 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
5465 #define RTC_BKP4R RTC_BKP4R_Msk
5466
5467 /******************** Bits definition for RTC_BKP5R register ****************/
5468 #define RTC_BKP5R_Pos (0U)
5469 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
5470 #define RTC_BKP5R RTC_BKP5R_Msk
5471
5472 /******************** Bits definition for RTC_BKP6R register ****************/
5473 #define RTC_BKP6R_Pos (0U)
5474 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
5475 #define RTC_BKP6R RTC_BKP6R_Msk
5476
5477 /******************** Bits definition for RTC_BKP7R register ****************/
5478 #define RTC_BKP7R_Pos (0U)
5479 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
5480 #define RTC_BKP7R RTC_BKP7R_Msk
5481
5482 /******************** Bits definition for RTC_BKP8R register ****************/
5483 #define RTC_BKP8R_Pos (0U)
5484 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
5485 #define RTC_BKP8R RTC_BKP8R_Msk
5486
5487 /******************** Bits definition for RTC_BKP9R register ****************/
5488 #define RTC_BKP9R_Pos (0U)
5489 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
5490 #define RTC_BKP9R RTC_BKP9R_Msk
5491
5492 /******************** Bits definition for RTC_BKP10R register ***************/
5493 #define RTC_BKP10R_Pos (0U)
5494 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
5495 #define RTC_BKP10R RTC_BKP10R_Msk
5496
5497 /******************** Bits definition for RTC_BKP11R register ***************/
5498 #define RTC_BKP11R_Pos (0U)
5499 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
5500 #define RTC_BKP11R RTC_BKP11R_Msk
5501
5502 /******************** Bits definition for RTC_BKP12R register ***************/
5503 #define RTC_BKP12R_Pos (0U)
5504 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
5505 #define RTC_BKP12R RTC_BKP12R_Msk
5506
5507 /******************** Bits definition for RTC_BKP13R register ***************/
5508 #define RTC_BKP13R_Pos (0U)
5509 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
5510 #define RTC_BKP13R RTC_BKP13R_Msk
5511
5512 /******************** Bits definition for RTC_BKP14R register ***************/
5513 #define RTC_BKP14R_Pos (0U)
5514 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
5515 #define RTC_BKP14R RTC_BKP14R_Msk
5516
5517 /******************** Bits definition for RTC_BKP15R register ***************/
5518 #define RTC_BKP15R_Pos (0U)
5519 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
5520 #define RTC_BKP15R RTC_BKP15R_Msk
5521
5522 /******************** Bits definition for RTC_BKP16R register ***************/
5523 #define RTC_BKP16R_Pos (0U)
5524 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
5525 #define RTC_BKP16R RTC_BKP16R_Msk
5526
5527 /******************** Bits definition for RTC_BKP17R register ***************/
5528 #define RTC_BKP17R_Pos (0U)
5529 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
5530 #define RTC_BKP17R RTC_BKP17R_Msk
5531
5532 /******************** Bits definition for RTC_BKP18R register ***************/
5533 #define RTC_BKP18R_Pos (0U)
5534 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
5535 #define RTC_BKP18R RTC_BKP18R_Msk
5536
5537 /******************** Bits definition for RTC_BKP19R register ***************/
5538 #define RTC_BKP19R_Pos (0U)
5539 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
5540 #define RTC_BKP19R RTC_BKP19R_Msk
5541
5542 /******************** Number of backup registers ******************************/
5543 #define RTC_BKP_NUMBER 0x000000014U
5544
5545 /******************************************************************************/
5546 /* */
5547 /* Serial Peripheral Interface */
5548 /* */
5549 /******************************************************************************/
5550
5551 /******************* Bit definition for SPI_CR1 register ********************/
5552 #define SPI_CR1_CPHA_Pos (0U)
5553 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
5554 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
5555 #define SPI_CR1_CPOL_Pos (1U)
5556 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
5557 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
5558 #define SPI_CR1_MSTR_Pos (2U)
5559 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
5560 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
5561
5562 #define SPI_CR1_BR_Pos (3U)
5563 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
5564 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
5565 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
5566 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
5567 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
5568
5569 #define SPI_CR1_SPE_Pos (6U)
5570 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
5571 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
5572 #define SPI_CR1_LSBFIRST_Pos (7U)
5573 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
5574 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
5575 #define SPI_CR1_SSI_Pos (8U)
5576 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
5577 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
5578 #define SPI_CR1_SSM_Pos (9U)
5579 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
5580 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
5581 #define SPI_CR1_RXONLY_Pos (10U)
5582 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
5583 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
5584 #define SPI_CR1_DFF_Pos (11U)
5585 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
5586 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
5587 #define SPI_CR1_CRCNEXT_Pos (12U)
5588 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
5589 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
5590 #define SPI_CR1_CRCEN_Pos (13U)
5591 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
5592 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
5593 #define SPI_CR1_BIDIOE_Pos (14U)
5594 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
5595 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
5596 #define SPI_CR1_BIDIMODE_Pos (15U)
5597 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
5598 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
5599
5600 /******************* Bit definition for SPI_CR2 register ********************/
5601 #define SPI_CR2_RXDMAEN_Pos (0U)
5602 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
5603 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
5604 #define SPI_CR2_TXDMAEN_Pos (1U)
5605 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
5606 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
5607 #define SPI_CR2_SSOE_Pos (2U)
5608 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
5609 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
5610 #define SPI_CR2_FRF_Pos (4U)
5611 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
5612 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
5613 #define SPI_CR2_ERRIE_Pos (5U)
5614 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
5615 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
5616 #define SPI_CR2_RXNEIE_Pos (6U)
5617 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
5618 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
5619 #define SPI_CR2_TXEIE_Pos (7U)
5620 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
5621 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
5622
5623 /******************** Bit definition for SPI_SR register ********************/
5624 #define SPI_SR_RXNE_Pos (0U)
5625 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
5626 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
5627 #define SPI_SR_TXE_Pos (1U)
5628 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
5629 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
5630 #define SPI_SR_CHSIDE_Pos (2U)
5631 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
5632 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
5633 #define SPI_SR_UDR_Pos (3U)
5634 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
5635 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
5636 #define SPI_SR_CRCERR_Pos (4U)
5637 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
5638 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
5639 #define SPI_SR_MODF_Pos (5U)
5640 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
5641 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
5642 #define SPI_SR_OVR_Pos (6U)
5643 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
5644 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
5645 #define SPI_SR_BSY_Pos (7U)
5646 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
5647 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
5648 #define SPI_SR_FRE_Pos (8U)
5649 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
5650 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
5651
5652 /******************** Bit definition for SPI_DR register ********************/
5653 #define SPI_DR_DR_Pos (0U)
5654 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
5655 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
5656
5657 /******************* Bit definition for SPI_CRCPR register ******************/
5658 #define SPI_CRCPR_CRCPOLY_Pos (0U)
5659 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
5660 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
5661
5662 /****************** Bit definition for SPI_RXCRCR register ******************/
5663 #define SPI_RXCRCR_RXCRC_Pos (0U)
5664 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
5665 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
5666
5667 /****************** Bit definition for SPI_TXCRCR register ******************/
5668 #define SPI_TXCRCR_TXCRC_Pos (0U)
5669 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
5670 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
5671
5672 /****************** Bit definition for SPI_I2SCFGR register *****************/
5673 #define SPI_I2SCFGR_CHLEN_Pos (0U)
5674 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
5675 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
5676
5677 #define SPI_I2SCFGR_DATLEN_Pos (1U)
5678 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
5679 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
5680 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
5681 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
5682
5683 #define SPI_I2SCFGR_CKPOL_Pos (3U)
5684 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
5685 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
5686
5687 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
5688 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
5689 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
5690 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
5691 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
5692
5693 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
5694 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
5695 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
5696
5697 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
5698 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
5699 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5700 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
5701 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
5702
5703 #define SPI_I2SCFGR_I2SE_Pos (10U)
5704 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
5705 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
5706 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
5707 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
5708 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
5709
5710 /****************** Bit definition for SPI_I2SPR register *******************/
5711 #define SPI_I2SPR_I2SDIV_Pos (0U)
5712 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
5713 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
5714 #define SPI_I2SPR_ODD_Pos (8U)
5715 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
5716 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
5717 #define SPI_I2SPR_MCKOE_Pos (9U)
5718 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
5719 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
5720
5721 /******************************************************************************/
5722 /* */
5723 /* SYSCFG */
5724 /* */
5725 /******************************************************************************/
5726 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
5727 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
5728 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
5729 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
5730 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
5731 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
5732 /****************** Bit definition for SYSCFG_PMC register ******************/
5733 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
5734 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
5735 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
5736
5737 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5738 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
5739 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
5740 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
5741 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
5742 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
5743 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
5744 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
5745 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
5746 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
5747 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
5748 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
5749 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
5750 /**
5751 * @brief EXTI0 configuration
5752 */
5753 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
5754 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
5755 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
5756 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
5757
5758 /**
5759 * @brief EXTI1 configuration
5760 */
5761 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
5762 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
5763 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
5764 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
5765
5766 /**
5767 * @brief EXTI2 configuration
5768 */
5769 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
5770 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
5771 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
5772 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
5773
5774 /**
5775 * @brief EXTI3 configuration
5776 */
5777 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
5778 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
5779 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
5780 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
5781
5782 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5783 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
5784 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
5785 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
5786 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
5787 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
5788 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
5789 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
5790 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
5791 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
5792 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
5793 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
5794 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
5795
5796 /**
5797 * @brief EXTI4 configuration
5798 */
5799 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
5800 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
5801 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
5802 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
5803
5804 /**
5805 * @brief EXTI5 configuration
5806 */
5807 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
5808 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
5809 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
5810 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
5811
5812 /**
5813 * @brief EXTI6 configuration
5814 */
5815 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
5816 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
5817 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
5818 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
5819
5820 /**
5821 * @brief EXTI7 configuration
5822 */
5823 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
5824 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
5825 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
5826 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
5827
5828 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5829 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
5830 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
5831 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
5832 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
5833 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
5834 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
5835 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
5836 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
5837 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
5838 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
5839 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
5840 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
5841
5842 /**
5843 * @brief EXTI8 configuration
5844 */
5845 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
5846 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
5847 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
5848 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
5849
5850 /**
5851 * @brief EXTI9 configuration
5852 */
5853 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
5854 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
5855 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
5856 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
5857
5858 /**
5859 * @brief EXTI10 configuration
5860 */
5861 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
5862 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
5863 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
5864 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
5865
5866 /**
5867 * @brief EXTI11 configuration
5868 */
5869 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
5870 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
5871 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
5872 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
5873
5874 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5875 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
5876 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
5877 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
5878 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
5879 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
5880 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
5881 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
5882 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
5883 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
5884 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
5885 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
5886 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
5887
5888 /**
5889 * @brief EXTI12 configuration
5890 */
5891 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
5892 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
5893 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
5894 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
5895
5896 /**
5897 * @brief EXTI13 configuration
5898 */
5899 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
5900 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
5901 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
5902 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
5903
5904 /**
5905 * @brief EXTI14 configuration
5906 */
5907 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
5908 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
5909 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
5910 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
5911
5912 /**
5913 * @brief EXTI15 configuration
5914 */
5915 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
5916 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
5917 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
5918 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
5919
5920 /****************** Bit definition for SYSCFG_CMPCR register ****************/
5921 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
5922 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
5923 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
5924 #define SYSCFG_CMPCR_READY_Pos (8U)
5925 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
5926 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
5927 /****************** Bit definition for SYSCFG_CFGR register *****************/
5928 #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
5929 #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
5930 #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
5931 #define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
5932 #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
5933 #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
5934
5935 /****************** Bit definition for SYSCFG_CFGR2 register *****************/
5936 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
5937 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
5938 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */
5939 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
5940 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
5941 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */
5942
5943 /******************************************************************************/
5944 /* */
5945 /* TIM */
5946 /* */
5947 /******************************************************************************/
5948 /******************* Bit definition for TIM_CR1 register ********************/
5949 #define TIM_CR1_CEN_Pos (0U)
5950 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
5951 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
5952 #define TIM_CR1_UDIS_Pos (1U)
5953 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
5954 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
5955 #define TIM_CR1_URS_Pos (2U)
5956 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
5957 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
5958 #define TIM_CR1_OPM_Pos (3U)
5959 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
5960 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
5961 #define TIM_CR1_DIR_Pos (4U)
5962 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
5963 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
5964
5965 #define TIM_CR1_CMS_Pos (5U)
5966 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
5967 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
5968 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
5969 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
5970
5971 #define TIM_CR1_ARPE_Pos (7U)
5972 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
5973 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
5974
5975 #define TIM_CR1_CKD_Pos (8U)
5976 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
5977 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
5978 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
5979 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
5980
5981 /******************* Bit definition for TIM_CR2 register ********************/
5982 #define TIM_CR2_CCPC_Pos (0U)
5983 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
5984 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
5985 #define TIM_CR2_CCUS_Pos (2U)
5986 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
5987 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
5988 #define TIM_CR2_CCDS_Pos (3U)
5989 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
5990 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
5991
5992 #define TIM_CR2_MMS_Pos (4U)
5993 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
5994 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
5995 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
5996 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
5997 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
5998
5999 #define TIM_CR2_TI1S_Pos (7U)
6000 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
6001 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
6002 #define TIM_CR2_OIS1_Pos (8U)
6003 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
6004 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
6005 #define TIM_CR2_OIS1N_Pos (9U)
6006 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
6007 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
6008 #define TIM_CR2_OIS2_Pos (10U)
6009 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
6010 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
6011 #define TIM_CR2_OIS2N_Pos (11U)
6012 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
6013 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
6014 #define TIM_CR2_OIS3_Pos (12U)
6015 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
6016 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
6017 #define TIM_CR2_OIS3N_Pos (13U)
6018 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
6019 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
6020 #define TIM_CR2_OIS4_Pos (14U)
6021 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
6022 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
6023
6024 /******************* Bit definition for TIM_SMCR register *******************/
6025 #define TIM_SMCR_SMS_Pos (0U)
6026 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
6027 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
6028 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
6029 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
6030 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
6031
6032 #define TIM_SMCR_TS_Pos (4U)
6033 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
6034 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
6035 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
6036 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
6037 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
6038
6039 #define TIM_SMCR_MSM_Pos (7U)
6040 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
6041 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
6042
6043 #define TIM_SMCR_ETF_Pos (8U)
6044 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
6045 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
6046 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
6047 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
6048 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
6049 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
6050
6051 #define TIM_SMCR_ETPS_Pos (12U)
6052 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
6053 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
6054 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
6055 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
6056
6057 #define TIM_SMCR_ECE_Pos (14U)
6058 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
6059 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
6060 #define TIM_SMCR_ETP_Pos (15U)
6061 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
6062 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
6063
6064 /******************* Bit definition for TIM_DIER register *******************/
6065 #define TIM_DIER_UIE_Pos (0U)
6066 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
6067 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
6068 #define TIM_DIER_CC1IE_Pos (1U)
6069 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
6070 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
6071 #define TIM_DIER_CC2IE_Pos (2U)
6072 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
6073 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
6074 #define TIM_DIER_CC3IE_Pos (3U)
6075 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
6076 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
6077 #define TIM_DIER_CC4IE_Pos (4U)
6078 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
6079 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
6080 #define TIM_DIER_COMIE_Pos (5U)
6081 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
6082 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
6083 #define TIM_DIER_TIE_Pos (6U)
6084 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
6085 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
6086 #define TIM_DIER_BIE_Pos (7U)
6087 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
6088 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
6089 #define TIM_DIER_UDE_Pos (8U)
6090 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
6091 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
6092 #define TIM_DIER_CC1DE_Pos (9U)
6093 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
6094 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
6095 #define TIM_DIER_CC2DE_Pos (10U)
6096 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
6097 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
6098 #define TIM_DIER_CC3DE_Pos (11U)
6099 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
6100 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
6101 #define TIM_DIER_CC4DE_Pos (12U)
6102 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
6103 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
6104 #define TIM_DIER_COMDE_Pos (13U)
6105 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
6106 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
6107 #define TIM_DIER_TDE_Pos (14U)
6108 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
6109 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
6110
6111 /******************** Bit definition for TIM_SR register ********************/
6112 #define TIM_SR_UIF_Pos (0U)
6113 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
6114 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
6115 #define TIM_SR_CC1IF_Pos (1U)
6116 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
6117 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
6118 #define TIM_SR_CC2IF_Pos (2U)
6119 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
6120 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
6121 #define TIM_SR_CC3IF_Pos (3U)
6122 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
6123 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
6124 #define TIM_SR_CC4IF_Pos (4U)
6125 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
6126 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
6127 #define TIM_SR_COMIF_Pos (5U)
6128 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
6129 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
6130 #define TIM_SR_TIF_Pos (6U)
6131 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
6132 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
6133 #define TIM_SR_BIF_Pos (7U)
6134 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
6135 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
6136 #define TIM_SR_CC1OF_Pos (9U)
6137 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
6138 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
6139 #define TIM_SR_CC2OF_Pos (10U)
6140 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
6141 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
6142 #define TIM_SR_CC3OF_Pos (11U)
6143 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
6144 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
6145 #define TIM_SR_CC4OF_Pos (12U)
6146 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
6147 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
6148
6149 /******************* Bit definition for TIM_EGR register ********************/
6150 #define TIM_EGR_UG_Pos (0U)
6151 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
6152 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
6153 #define TIM_EGR_CC1G_Pos (1U)
6154 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
6155 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
6156 #define TIM_EGR_CC2G_Pos (2U)
6157 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
6158 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
6159 #define TIM_EGR_CC3G_Pos (3U)
6160 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
6161 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
6162 #define TIM_EGR_CC4G_Pos (4U)
6163 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
6164 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
6165 #define TIM_EGR_COMG_Pos (5U)
6166 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
6167 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
6168 #define TIM_EGR_TG_Pos (6U)
6169 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
6170 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
6171 #define TIM_EGR_BG_Pos (7U)
6172 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
6173 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
6174
6175 /****************** Bit definition for TIM_CCMR1 register *******************/
6176 #define TIM_CCMR1_CC1S_Pos (0U)
6177 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
6178 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6179 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
6180 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
6181
6182 #define TIM_CCMR1_OC1FE_Pos (2U)
6183 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
6184 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
6185 #define TIM_CCMR1_OC1PE_Pos (3U)
6186 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
6187 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
6188
6189 #define TIM_CCMR1_OC1M_Pos (4U)
6190 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
6191 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6192 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
6193 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
6194 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
6195
6196 #define TIM_CCMR1_OC1CE_Pos (7U)
6197 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
6198 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
6199
6200 #define TIM_CCMR1_CC2S_Pos (8U)
6201 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
6202 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6203 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
6204 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
6205
6206 #define TIM_CCMR1_OC2FE_Pos (10U)
6207 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
6208 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
6209 #define TIM_CCMR1_OC2PE_Pos (11U)
6210 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
6211 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
6212
6213 #define TIM_CCMR1_OC2M_Pos (12U)
6214 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
6215 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6216 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
6217 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
6218 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
6219
6220 #define TIM_CCMR1_OC2CE_Pos (15U)
6221 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
6222 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
6223
6224 /*----------------------------------------------------------------------------*/
6225
6226 #define TIM_CCMR1_IC1PSC_Pos (2U)
6227 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
6228 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6229 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
6230 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
6231
6232 #define TIM_CCMR1_IC1F_Pos (4U)
6233 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
6234 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6235 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
6236 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
6237 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
6238 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
6239
6240 #define TIM_CCMR1_IC2PSC_Pos (10U)
6241 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
6242 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6243 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
6244 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
6245
6246 #define TIM_CCMR1_IC2F_Pos (12U)
6247 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
6248 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6249 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
6250 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
6251 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
6252 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
6253
6254 /****************** Bit definition for TIM_CCMR2 register *******************/
6255 #define TIM_CCMR2_CC3S_Pos (0U)
6256 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
6257 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6258 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
6259 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
6260
6261 #define TIM_CCMR2_OC3FE_Pos (2U)
6262 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
6263 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
6264 #define TIM_CCMR2_OC3PE_Pos (3U)
6265 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
6266 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
6267
6268 #define TIM_CCMR2_OC3M_Pos (4U)
6269 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
6270 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6271 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
6272 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
6273 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
6274
6275 #define TIM_CCMR2_OC3CE_Pos (7U)
6276 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
6277 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
6278
6279 #define TIM_CCMR2_CC4S_Pos (8U)
6280 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
6281 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6282 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
6283 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
6284
6285 #define TIM_CCMR2_OC4FE_Pos (10U)
6286 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
6287 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
6288 #define TIM_CCMR2_OC4PE_Pos (11U)
6289 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
6290 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
6291
6292 #define TIM_CCMR2_OC4M_Pos (12U)
6293 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
6294 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6295 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
6296 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
6297 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
6298
6299 #define TIM_CCMR2_OC4CE_Pos (15U)
6300 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
6301 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
6302
6303 /*----------------------------------------------------------------------------*/
6304
6305 #define TIM_CCMR2_IC3PSC_Pos (2U)
6306 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
6307 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6308 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
6309 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
6310
6311 #define TIM_CCMR2_IC3F_Pos (4U)
6312 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
6313 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6314 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
6315 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
6316 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
6317 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
6318
6319 #define TIM_CCMR2_IC4PSC_Pos (10U)
6320 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
6321 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6322 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
6323 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
6324
6325 #define TIM_CCMR2_IC4F_Pos (12U)
6326 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
6327 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6328 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
6329 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
6330 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
6331 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
6332
6333 /******************* Bit definition for TIM_CCER register *******************/
6334 #define TIM_CCER_CC1E_Pos (0U)
6335 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
6336 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
6337 #define TIM_CCER_CC1P_Pos (1U)
6338 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
6339 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
6340 #define TIM_CCER_CC1NE_Pos (2U)
6341 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
6342 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
6343 #define TIM_CCER_CC1NP_Pos (3U)
6344 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
6345 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
6346 #define TIM_CCER_CC2E_Pos (4U)
6347 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
6348 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
6349 #define TIM_CCER_CC2P_Pos (5U)
6350 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
6351 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
6352 #define TIM_CCER_CC2NE_Pos (6U)
6353 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
6354 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
6355 #define TIM_CCER_CC2NP_Pos (7U)
6356 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
6357 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
6358 #define TIM_CCER_CC3E_Pos (8U)
6359 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
6360 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
6361 #define TIM_CCER_CC3P_Pos (9U)
6362 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
6363 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
6364 #define TIM_CCER_CC3NE_Pos (10U)
6365 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
6366 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
6367 #define TIM_CCER_CC3NP_Pos (11U)
6368 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
6369 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
6370 #define TIM_CCER_CC4E_Pos (12U)
6371 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
6372 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
6373 #define TIM_CCER_CC4P_Pos (13U)
6374 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
6375 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
6376 #define TIM_CCER_CC4NP_Pos (15U)
6377 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
6378 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
6379
6380 /******************* Bit definition for TIM_CNT register ********************/
6381 #define TIM_CNT_CNT_Pos (0U)
6382 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
6383 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
6384
6385 /******************* Bit definition for TIM_PSC register ********************/
6386 #define TIM_PSC_PSC_Pos (0U)
6387 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
6388 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
6389
6390 /******************* Bit definition for TIM_ARR register ********************/
6391 #define TIM_ARR_ARR_Pos (0U)
6392 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
6393 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
6394
6395 /******************* Bit definition for TIM_RCR register ********************/
6396 #define TIM_RCR_REP_Pos (0U)
6397 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
6398 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
6399
6400 /******************* Bit definition for TIM_CCR1 register *******************/
6401 #define TIM_CCR1_CCR1_Pos (0U)
6402 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
6403 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
6404
6405 /******************* Bit definition for TIM_CCR2 register *******************/
6406 #define TIM_CCR2_CCR2_Pos (0U)
6407 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
6408 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
6409
6410 /******************* Bit definition for TIM_CCR3 register *******************/
6411 #define TIM_CCR3_CCR3_Pos (0U)
6412 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
6413 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
6414
6415 /******************* Bit definition for TIM_CCR4 register *******************/
6416 #define TIM_CCR4_CCR4_Pos (0U)
6417 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
6418 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
6419
6420 /******************* Bit definition for TIM_BDTR register *******************/
6421 #define TIM_BDTR_DTG_Pos (0U)
6422 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
6423 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6424 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
6425 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
6426 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
6427 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
6428 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
6429 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
6430 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
6431 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
6432
6433 #define TIM_BDTR_LOCK_Pos (8U)
6434 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
6435 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
6436 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
6437 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
6438
6439 #define TIM_BDTR_OSSI_Pos (10U)
6440 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
6441 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
6442 #define TIM_BDTR_OSSR_Pos (11U)
6443 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
6444 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
6445 #define TIM_BDTR_BKE_Pos (12U)
6446 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
6447 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
6448 #define TIM_BDTR_BKP_Pos (13U)
6449 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
6450 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
6451 #define TIM_BDTR_AOE_Pos (14U)
6452 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
6453 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
6454 #define TIM_BDTR_MOE_Pos (15U)
6455 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
6456 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
6457
6458 /******************* Bit definition for TIM_DCR register ********************/
6459 #define TIM_DCR_DBA_Pos (0U)
6460 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
6461 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
6462 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
6463 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
6464 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
6465 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
6466 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
6467
6468 #define TIM_DCR_DBL_Pos (8U)
6469 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
6470 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
6471 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
6472 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
6473 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
6474 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
6475 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
6476
6477 /******************* Bit definition for TIM_DMAR register *******************/
6478 #define TIM_DMAR_DMAB_Pos (0U)
6479 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
6480 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
6481
6482 /******************* Bit definition for TIM_OR register *********************/
6483 #define TIM_OR_TI1_RMP_Pos (0U)
6484 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
6485 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
6486 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
6487 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
6488
6489 #define TIM_OR_TI4_RMP_Pos (6U)
6490 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
6491 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
6492 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
6493 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
6494
6495 /******************************************************************************/
6496 /* */
6497 /* Low Power Timer (LPTIM) */
6498 /* */
6499 /******************************************************************************/
6500 /****************** Bit definition for LPTIM_ISR register *******************/
6501 #define LPTIM_ISR_CMPM_Pos (0U)
6502 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
6503 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
6504 #define LPTIM_ISR_ARRM_Pos (1U)
6505 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
6506 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
6507 #define LPTIM_ISR_EXTTRIG_Pos (2U)
6508 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
6509 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
6510 #define LPTIM_ISR_CMPOK_Pos (3U)
6511 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
6512 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
6513 #define LPTIM_ISR_ARROK_Pos (4U)
6514 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
6515 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
6516 #define LPTIM_ISR_UP_Pos (5U)
6517 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
6518 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
6519 #define LPTIM_ISR_DOWN_Pos (6U)
6520 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
6521 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
6522
6523 /****************** Bit definition for LPTIM_ICR register *******************/
6524 #define LPTIM_ICR_CMPMCF_Pos (0U)
6525 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
6526 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
6527 #define LPTIM_ICR_ARRMCF_Pos (1U)
6528 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
6529 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
6530 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
6531 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
6532 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
6533 #define LPTIM_ICR_CMPOKCF_Pos (3U)
6534 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
6535 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
6536 #define LPTIM_ICR_ARROKCF_Pos (4U)
6537 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
6538 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
6539 #define LPTIM_ICR_UPCF_Pos (5U)
6540 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
6541 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
6542 #define LPTIM_ICR_DOWNCF_Pos (6U)
6543 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
6544 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
6545
6546 /****************** Bit definition for LPTIM_IER register ********************/
6547 #define LPTIM_IER_CMPMIE_Pos (0U)
6548 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
6549 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
6550 #define LPTIM_IER_ARRMIE_Pos (1U)
6551 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
6552 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
6553 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
6554 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
6555 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
6556 #define LPTIM_IER_CMPOKIE_Pos (3U)
6557 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
6558 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
6559 #define LPTIM_IER_ARROKIE_Pos (4U)
6560 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
6561 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
6562 #define LPTIM_IER_UPIE_Pos (5U)
6563 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
6564 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
6565 #define LPTIM_IER_DOWNIE_Pos (6U)
6566 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
6567 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
6568
6569 /****************** Bit definition for LPTIM_CFGR register *******************/
6570 #define LPTIM_CFGR_CKSEL_Pos (0U)
6571 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
6572 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
6573
6574 #define LPTIM_CFGR_CKPOL_Pos (1U)
6575 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
6576 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
6577 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
6578 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
6579
6580 #define LPTIM_CFGR_CKFLT_Pos (3U)
6581 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
6582 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
6583 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
6584 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
6585
6586 #define LPTIM_CFGR_TRGFLT_Pos (6U)
6587 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
6588 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
6589 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
6590 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
6591
6592 #define LPTIM_CFGR_PRESC_Pos (9U)
6593 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
6594 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
6595 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
6596 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
6597 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
6598
6599 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
6600 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
6601 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
6602 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
6603 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
6604 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
6605
6606 #define LPTIM_CFGR_TRIGEN_Pos (17U)
6607 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
6608 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
6609 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
6610 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
6611
6612 #define LPTIM_CFGR_TIMOUT_Pos (19U)
6613 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
6614 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
6615 #define LPTIM_CFGR_WAVE_Pos (20U)
6616 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
6617 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
6618 #define LPTIM_CFGR_WAVPOL_Pos (21U)
6619 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
6620 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
6621 #define LPTIM_CFGR_PRELOAD_Pos (22U)
6622 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
6623 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
6624 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
6625 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
6626 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
6627 #define LPTIM_CFGR_ENC_Pos (24U)
6628 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
6629 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
6630
6631 /****************** Bit definition for LPTIM_CR register ********************/
6632 #define LPTIM_CR_ENABLE_Pos (0U)
6633 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
6634 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
6635 #define LPTIM_CR_SNGSTRT_Pos (1U)
6636 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
6637 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
6638 #define LPTIM_CR_CNTSTRT_Pos (2U)
6639 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
6640 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
6641
6642 /****************** Bit definition for LPTIM_CMP register *******************/
6643 #define LPTIM_CMP_CMP_Pos (0U)
6644 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
6645 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
6646
6647 /****************** Bit definition for LPTIM_ARR register *******************/
6648 #define LPTIM_ARR_ARR_Pos (0U)
6649 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
6650 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
6651
6652 /****************** Bit definition for LPTIM_CNT register *******************/
6653 #define LPTIM_CNT_CNT_Pos (0U)
6654 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
6655 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
6656
6657 /****************** Bit definition for LPTIM_OR register *******************/
6658 #define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
6659 #define LPTIM_OR_LPT_IN1_RMP_Msk (0x3U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000003 */
6660 #define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
6661 #define LPTIM_OR_LPT_IN1_RMP_0 (0x1U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000001 */
6662 #define LPTIM_OR_LPT_IN1_RMP_1 (0x2U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000002 */
6663
6664 /* Legacy Defines */
6665 #define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
6666 #define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
6667 #define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
6668
6669
6670 /******************************************************************************/
6671 /* */
6672 /* Universal Synchronous Asynchronous Receiver Transmitter */
6673 /* */
6674 /******************************************************************************/
6675 /******************* Bit definition for USART_SR register *******************/
6676 #define USART_SR_PE_Pos (0U)
6677 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
6678 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
6679 #define USART_SR_FE_Pos (1U)
6680 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
6681 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
6682 #define USART_SR_NE_Pos (2U)
6683 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
6684 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
6685 #define USART_SR_ORE_Pos (3U)
6686 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
6687 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
6688 #define USART_SR_IDLE_Pos (4U)
6689 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
6690 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
6691 #define USART_SR_RXNE_Pos (5U)
6692 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
6693 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
6694 #define USART_SR_TC_Pos (6U)
6695 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
6696 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
6697 #define USART_SR_TXE_Pos (7U)
6698 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
6699 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
6700 #define USART_SR_LBD_Pos (8U)
6701 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
6702 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
6703 #define USART_SR_CTS_Pos (9U)
6704 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
6705 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
6706
6707 /******************* Bit definition for USART_DR register *******************/
6708 #define USART_DR_DR_Pos (0U)
6709 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
6710 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
6711
6712 /****************** Bit definition for USART_BRR register *******************/
6713 #define USART_BRR_DIV_Fraction_Pos (0U)
6714 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
6715 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
6716 #define USART_BRR_DIV_Mantissa_Pos (4U)
6717 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
6718 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
6719
6720 /****************** Bit definition for USART_CR1 register *******************/
6721 #define USART_CR1_SBK_Pos (0U)
6722 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
6723 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
6724 #define USART_CR1_RWU_Pos (1U)
6725 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
6726 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
6727 #define USART_CR1_RE_Pos (2U)
6728 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
6729 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
6730 #define USART_CR1_TE_Pos (3U)
6731 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
6732 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
6733 #define USART_CR1_IDLEIE_Pos (4U)
6734 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
6735 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
6736 #define USART_CR1_RXNEIE_Pos (5U)
6737 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
6738 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
6739 #define USART_CR1_TCIE_Pos (6U)
6740 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
6741 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
6742 #define USART_CR1_TXEIE_Pos (7U)
6743 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
6744 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
6745 #define USART_CR1_PEIE_Pos (8U)
6746 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
6747 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
6748 #define USART_CR1_PS_Pos (9U)
6749 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
6750 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
6751 #define USART_CR1_PCE_Pos (10U)
6752 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
6753 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
6754 #define USART_CR1_WAKE_Pos (11U)
6755 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
6756 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
6757 #define USART_CR1_M_Pos (12U)
6758 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
6759 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
6760 #define USART_CR1_UE_Pos (13U)
6761 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
6762 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
6763 #define USART_CR1_OVER8_Pos (15U)
6764 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
6765 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
6766
6767 /****************** Bit definition for USART_CR2 register *******************/
6768 #define USART_CR2_ADD_Pos (0U)
6769 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
6770 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
6771 #define USART_CR2_LBDL_Pos (5U)
6772 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
6773 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
6774 #define USART_CR2_LBDIE_Pos (6U)
6775 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
6776 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
6777 #define USART_CR2_LBCL_Pos (8U)
6778 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
6779 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
6780 #define USART_CR2_CPHA_Pos (9U)
6781 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
6782 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
6783 #define USART_CR2_CPOL_Pos (10U)
6784 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
6785 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
6786 #define USART_CR2_CLKEN_Pos (11U)
6787 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
6788 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
6789
6790 #define USART_CR2_STOP_Pos (12U)
6791 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
6792 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
6793 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
6794 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
6795
6796 #define USART_CR2_LINEN_Pos (14U)
6797 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
6798 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
6799
6800 /****************** Bit definition for USART_CR3 register *******************/
6801 #define USART_CR3_EIE_Pos (0U)
6802 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
6803 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
6804 #define USART_CR3_IREN_Pos (1U)
6805 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
6806 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
6807 #define USART_CR3_IRLP_Pos (2U)
6808 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
6809 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
6810 #define USART_CR3_HDSEL_Pos (3U)
6811 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
6812 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
6813 #define USART_CR3_NACK_Pos (4U)
6814 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
6815 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
6816 #define USART_CR3_SCEN_Pos (5U)
6817 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
6818 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
6819 #define USART_CR3_DMAR_Pos (6U)
6820 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
6821 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
6822 #define USART_CR3_DMAT_Pos (7U)
6823 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
6824 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
6825 #define USART_CR3_RTSE_Pos (8U)
6826 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
6827 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
6828 #define USART_CR3_CTSE_Pos (9U)
6829 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
6830 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
6831 #define USART_CR3_CTSIE_Pos (10U)
6832 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
6833 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
6834 #define USART_CR3_ONEBIT_Pos (11U)
6835 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
6836 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
6837
6838 /****************** Bit definition for USART_GTPR register ******************/
6839 #define USART_GTPR_PSC_Pos (0U)
6840 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
6841 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
6842 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
6843 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
6844 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
6845 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
6846 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
6847 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
6848 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
6849 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
6850
6851 #define USART_GTPR_GT_Pos (8U)
6852 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
6853 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
6854
6855 /******************************************************************************/
6856 /* */
6857 /* Window WATCHDOG */
6858 /* */
6859 /******************************************************************************/
6860 /******************* Bit definition for WWDG_CR register ********************/
6861 #define WWDG_CR_T_Pos (0U)
6862 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
6863 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
6864 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
6865 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
6866 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
6867 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
6868 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
6869 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
6870 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
6871 /* Legacy defines */
6872 #define WWDG_CR_T0 WWDG_CR_T_0
6873 #define WWDG_CR_T1 WWDG_CR_T_1
6874 #define WWDG_CR_T2 WWDG_CR_T_2
6875 #define WWDG_CR_T3 WWDG_CR_T_3
6876 #define WWDG_CR_T4 WWDG_CR_T_4
6877 #define WWDG_CR_T5 WWDG_CR_T_5
6878 #define WWDG_CR_T6 WWDG_CR_T_6
6879
6880 #define WWDG_CR_WDGA_Pos (7U)
6881 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
6882 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
6883
6884 /******************* Bit definition for WWDG_CFR register *******************/
6885 #define WWDG_CFR_W_Pos (0U)
6886 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
6887 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
6888 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
6889 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
6890 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
6891 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
6892 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
6893 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
6894 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
6895 /* Legacy defines */
6896 #define WWDG_CFR_W0 WWDG_CFR_W_0
6897 #define WWDG_CFR_W1 WWDG_CFR_W_1
6898 #define WWDG_CFR_W2 WWDG_CFR_W_2
6899 #define WWDG_CFR_W3 WWDG_CFR_W_3
6900 #define WWDG_CFR_W4 WWDG_CFR_W_4
6901 #define WWDG_CFR_W5 WWDG_CFR_W_5
6902 #define WWDG_CFR_W6 WWDG_CFR_W_6
6903
6904 #define WWDG_CFR_WDGTB_Pos (7U)
6905 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
6906 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
6907 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
6908 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
6909 /* Legacy defines */
6910 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
6911 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
6912
6913 #define WWDG_CFR_EWI_Pos (9U)
6914 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
6915 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
6916
6917 /******************* Bit definition for WWDG_SR register ********************/
6918 #define WWDG_SR_EWIF_Pos (0U)
6919 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
6920 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
6921
6922
6923 /******************************************************************************/
6924 /* */
6925 /* DBG */
6926 /* */
6927 /******************************************************************************/
6928 /******************** Bit definition for DBGMCU_IDCODE register *************/
6929 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
6930 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
6931 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
6932 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
6933 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
6934 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
6935
6936 /******************** Bit definition for DBGMCU_CR register *****************/
6937 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
6938 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
6939 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
6940 #define DBGMCU_CR_DBG_STOP_Pos (1U)
6941 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
6942 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
6943 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
6944 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
6945 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
6946 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
6947 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
6948 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
6949
6950 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
6951 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
6952 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
6953 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
6954 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
6955
6956 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6957 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
6958 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
6959 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
6960 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
6961 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
6962 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
6963 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
6964 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
6965 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
6966 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
6967 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
6968 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
6969 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
6970 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
6971 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
6972 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
6973 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
6974 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
6975 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
6976 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
6977 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
6978 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
6979 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
6980 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
6981 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
6982 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
6983 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
6984 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
6985 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
6986 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
6987
6988 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6989 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
6990 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
6991 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
6992 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
6993 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
6994 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
6995 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
6996 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
6997 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
6998 /**
6999 * @}
7000 */
7001
7002 /**
7003 * @}
7004 */
7005
7006 /** @addtogroup Exported_macros
7007 * @{
7008 */
7009
7010 /******************************* ADC Instances ********************************/
7011 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
7012
7013 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
7014 /******************************* CRC Instances ********************************/
7015 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7016
7017 /******************************* DAC Instances ********************************/
7018 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
7019
7020
7021 /******************************** DMA Instances *******************************/
7022 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
7023 ((INSTANCE) == DMA1_Stream1) || \
7024 ((INSTANCE) == DMA1_Stream2) || \
7025 ((INSTANCE) == DMA1_Stream3) || \
7026 ((INSTANCE) == DMA1_Stream4) || \
7027 ((INSTANCE) == DMA1_Stream5) || \
7028 ((INSTANCE) == DMA1_Stream6) || \
7029 ((INSTANCE) == DMA1_Stream7) || \
7030 ((INSTANCE) == DMA2_Stream0) || \
7031 ((INSTANCE) == DMA2_Stream1) || \
7032 ((INSTANCE) == DMA2_Stream2) || \
7033 ((INSTANCE) == DMA2_Stream3) || \
7034 ((INSTANCE) == DMA2_Stream4) || \
7035 ((INSTANCE) == DMA2_Stream5) || \
7036 ((INSTANCE) == DMA2_Stream6) || \
7037 ((INSTANCE) == DMA2_Stream7))
7038
7039 /******************************* GPIO Instances *******************************/
7040 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7041 ((INSTANCE) == GPIOB) || \
7042 ((INSTANCE) == GPIOC) || \
7043 ((INSTANCE) == GPIOH))
7044
7045 /******************************** I2C Instances *******************************/
7046 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7047 ((INSTANCE) == I2C2))
7048
7049 /******************************* SMBUS Instances ******************************/
7050 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
7051
7052 /******************************** I2S Instances *******************************/
7053 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
7054
7055
7056 /******************************* LPTIM Instances ******************************/
7057 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
7058
7059 /******************************* RNG Instances ********************************/
7060 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
7061
7062
7063
7064 /****************************** RTC Instances *********************************/
7065 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7066
7067
7068 /******************************** SPI Instances *******************************/
7069 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
7070
7071
7072 /*************************** SPI Extended Instances ***************************/
7073 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) ((INSTANCE) == SPI1)
7074 /****************** TIM Instances : All supported instances *******************/
7075 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7076 ((INSTANCE) == TIM5) || \
7077 ((INSTANCE) == TIM6) || \
7078 ((INSTANCE) == TIM9) || \
7079 ((INSTANCE) == TIM11))
7080
7081 /************* TIM Instances : at least 1 capture/compare channel *************/
7082 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7083 ((INSTANCE) == TIM5) || \
7084 ((INSTANCE) == TIM9) || \
7085 ((INSTANCE) == TIM11))
7086
7087 /************ TIM Instances : at least 2 capture/compare channels *************/
7088 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7089 ((INSTANCE) == TIM5) || \
7090 ((INSTANCE) == TIM9))
7091
7092 /************ TIM Instances : at least 3 capture/compare channels *************/
7093 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7094 ((INSTANCE) == TIM5))
7095
7096 /************ TIM Instances : at least 4 capture/compare channels *************/
7097 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7098 ((INSTANCE) == TIM5))
7099
7100 /******************** TIM Instances : Advanced-control timers *****************/
7101 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
7102
7103 /******************* TIM Instances : Timer input XOR function *****************/
7104 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7105 ((INSTANCE) == TIM5))
7106
7107 /****************** TIM Instances : DMA requests generation (UDE) *************/
7108 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7109 ((INSTANCE) == TIM5) || \
7110 ((INSTANCE) == TIM6))
7111
7112 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
7113 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7114 ((INSTANCE) == TIM5))
7115
7116 /************ TIM Instances : DMA requests generation (COMDE) *****************/
7117 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7118 ((INSTANCE) == TIM5))
7119
7120 /******************** TIM Instances : DMA burst feature ***********************/
7121 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7122 ((INSTANCE) == TIM5))
7123
7124 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
7125 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7126 ((INSTANCE) == TIM5) || \
7127 ((INSTANCE) == TIM6))
7128
7129 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
7130 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7131 ((INSTANCE) == TIM5) || \
7132 ((INSTANCE) == TIM9))
7133
7134 /********************** TIM Instances : 32 bit Counter ************************/
7135 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5)
7136
7137 /***************** TIM Instances : external trigger input availabe ************/
7138 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7139 ((INSTANCE) == TIM5))
7140
7141 /****************** TIM Instances : remapping capability **********************/
7142 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
7143 ((INSTANCE) == TIM11))
7144
7145 /******************* TIM Instances : output(s) available **********************/
7146 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7147 ((((INSTANCE) == TIM1) && \
7148 (((CHANNEL) == TIM_CHANNEL_1) || \
7149 ((CHANNEL) == TIM_CHANNEL_2) || \
7150 ((CHANNEL) == TIM_CHANNEL_3) || \
7151 ((CHANNEL) == TIM_CHANNEL_4))) \
7152 || \
7153 (((INSTANCE) == TIM5) && \
7154 (((CHANNEL) == TIM_CHANNEL_1) || \
7155 ((CHANNEL) == TIM_CHANNEL_2) || \
7156 ((CHANNEL) == TIM_CHANNEL_3) || \
7157 ((CHANNEL) == TIM_CHANNEL_4))) \
7158 || \
7159 (((INSTANCE) == TIM9) && \
7160 (((CHANNEL) == TIM_CHANNEL_1) || \
7161 ((CHANNEL) == TIM_CHANNEL_2))) \
7162 || \
7163 (((INSTANCE) == TIM11) && \
7164 (((CHANNEL) == TIM_CHANNEL_1))))
7165
7166 /************ TIM Instances : complementary output(s) available ***************/
7167 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
7168 ((((INSTANCE) == TIM1) && \
7169 (((CHANNEL) == TIM_CHANNEL_1) || \
7170 ((CHANNEL) == TIM_CHANNEL_2) || \
7171 ((CHANNEL) == TIM_CHANNEL_3))))
7172
7173 /****************** TIM Instances : supporting counting mode selection ********/
7174 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7175 ((INSTANCE) == TIM5))
7176
7177 /****************** TIM Instances : supporting clock division *****************/
7178 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7179 ((INSTANCE) == TIM5) || \
7180 ((INSTANCE) == TIM9) || \
7181 ((INSTANCE) == TIM11))
7182
7183 /****************** TIM Instances : supporting commutation event generation ***/
7184
7185 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
7186
7187 /****************** TIM Instances : supporting OCxREF clear *******************/
7188 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7189 ((INSTANCE) == TIM5))
7190
7191 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
7192 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7193 ((INSTANCE) == TIM5) || \
7194 ((INSTANCE) == TIM9))
7195
7196 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
7197 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7198 ((INSTANCE) == TIM5))
7199
7200 /****************** TIM Instances : supporting repetition counter *************/
7201 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
7202
7203 /****************** TIM Instances : supporting encoder interface **************/
7204 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7205 ((INSTANCE) == TIM5) || \
7206 ((INSTANCE) == TIM9))
7207 /****************** TIM Instances : supporting Hall sensor interface **********/
7208 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7209 ((INSTANCE) == TIM5))
7210 /****************** TIM Instances : supporting the break function *************/
7211 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
7212
7213 /******************** USART Instances : Synchronous mode **********************/
7214 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7215 ((INSTANCE) == USART2))
7216
7217 /******************** UART Instances : Half-Duplex mode **********************/
7218 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7219 ((INSTANCE) == USART2))
7220
7221 /* Legacy defines */
7222 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
7223
7224 /****************** UART Instances : Hardware Flow control ********************/
7225 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7226 ((INSTANCE) == USART2))
7227 /******************** UART Instances : LIN mode **********************/
7228 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
7229
7230 /********************* UART Instances : Smart card mode ***********************/
7231 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7232 ((INSTANCE) == USART2))
7233
7234 /*********************** UART Instances : IRDA mode ***************************/
7235 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7236 ((INSTANCE) == USART2))
7237
7238 /****************************** IWDG Instances ********************************/
7239 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
7240
7241 /****************************** WWDG Instances ********************************/
7242 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
7243
7244
7245 /***************************** FMPI2C Instances *******************************/
7246 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
7247
7248 /*
7249 * @brief Specific devices reset values definitions
7250 */
7251 #define RCC_PLLCFGR_RST_VALUE 0x7F003010U
7252 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
7253
7254 #define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
7255 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
7256 #define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
7257 #define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
7258 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
7259 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
7260 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
7261 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
7262
7263 #define RCC_PLLN_MIN_VALUE 50U
7264 #define RCC_PLLN_MAX_VALUE 432U
7265
7266 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
7267 #define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
7268 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
7269
7270 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
7271 #define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
7272
7273 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
7274 #define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
7275
7276
7277 /**
7278 * @}
7279 */
7280
7281 /**
7282 * @}
7283 */
7284
7285 /**
7286 * @}
7287 */
7288
7289 #ifdef __cplusplus
7290 }
7291 #endif /* __cplusplus */
7292
7293 #endif /* __STM32F410Tx_H */
7294
7295
7296
7297 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/