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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f407xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - peripherals registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f407xx
47 * @{
48 */
49
50 #ifndef __STM32F407xx_H
51 #define __STM32F407xx_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #define __FPU_PRESENT 1U /*!< FPU present */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78 /**
79 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
87 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
88 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
89 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
91 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
92 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
93 /****** STM32 specific Interrupt Numbers **********************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
99 RCC_IRQn = 5, /*!< RCC global Interrupt */
100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
112 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
113 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
114 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
115 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
116 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
133 USART3_IRQn = 39, /*!< USART3 global Interrupt */
134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
137 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
138 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
139 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
140 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
141 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
142 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
143 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
144 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
149 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
150 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
151 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
152 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
153 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
154 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
155 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
156 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
157 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
158 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
159 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
160 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
162 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
163 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
164 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
165 USART6_IRQn = 71, /*!< USART6 global interrupt */
166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
168 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
169 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
170 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
171 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
172 DCMI_IRQn = 78, /*!< DCMI global interrupt */
173 RNG_IRQn = 80, /*!< RNG global Interrupt */
174 FPU_IRQn = 81 /*!< FPU global interrupt */
175 } IRQn_Type;
176 /* Legacy define */
177 #define HASH_RNG_IRQn RNG_IRQn
178
179 /**
180 * @}
181 */
182
183 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
184 #include "system_stm32f4xx.h"
185 #include <stdint.h>
186
187 /** @addtogroup Peripheral_registers_structures
188 * @{
189 */
190
191 /**
192 * @brief Analog to Digital Converter
193 */
194
195 typedef struct
196 {
197 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
198 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
199 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
200 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
201 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
202 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
203 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
204 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
205 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
206 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
207 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
208 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
209 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
210 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
211 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
212 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
213 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
214 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
215 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
216 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
217 } ADC_TypeDef;
218
219 typedef struct
220 {
221 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
222 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
223 __IO uint32_t CDR; /*!< ADC common regular data register for dual
224 AND triple modes, Address offset: ADC1 base address + 0x308 */
225 } ADC_Common_TypeDef;
226
227
228 /**
229 * @brief Controller Area Network TxMailBox
230 */
231
232 typedef struct
233 {
234 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
235 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
236 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
237 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
238 } CAN_TxMailBox_TypeDef;
239
240 /**
241 * @brief Controller Area Network FIFOMailBox
242 */
243
244 typedef struct
245 {
246 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
247 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
248 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
249 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
250 } CAN_FIFOMailBox_TypeDef;
251
252 /**
253 * @brief Controller Area Network FilterRegister
254 */
255
256 typedef struct
257 {
258 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
259 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
260 } CAN_FilterRegister_TypeDef;
261
262 /**
263 * @brief Controller Area Network
264 */
265
266 typedef struct
267 {
268 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
269 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
270 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
271 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
272 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
273 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
274 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
275 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
276 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
277 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
278 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
279 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
280 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
281 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
282 uint32_t RESERVED2; /*!< Reserved, 0x208 */
283 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
284 uint32_t RESERVED3; /*!< Reserved, 0x210 */
285 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
286 uint32_t RESERVED4; /*!< Reserved, 0x218 */
287 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
288 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
289 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
290 } CAN_TypeDef;
291
292 /**
293 * @brief CRC calculation unit
294 */
295
296 typedef struct
297 {
298 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
299 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
300 uint8_t RESERVED0; /*!< Reserved, 0x05 */
301 uint16_t RESERVED1; /*!< Reserved, 0x06 */
302 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
303 } CRC_TypeDef;
304
305 /**
306 * @brief Digital to Analog Converter
307 */
308
309 typedef struct
310 {
311 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
312 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
313 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
314 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
315 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
316 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
317 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
318 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
319 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
320 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
321 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
322 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
323 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
324 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
325 } DAC_TypeDef;
326
327 /**
328 * @brief Debug MCU
329 */
330
331 typedef struct
332 {
333 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
334 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
335 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
336 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
337 }DBGMCU_TypeDef;
338
339 /**
340 * @brief DCMI
341 */
342
343 typedef struct
344 {
345 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
346 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
347 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
348 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
349 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
350 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
351 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
352 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
353 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
354 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
355 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
356 } DCMI_TypeDef;
357
358 /**
359 * @brief DMA Controller
360 */
361
362 typedef struct
363 {
364 __IO uint32_t CR; /*!< DMA stream x configuration register */
365 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
366 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
367 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
368 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
369 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
370 } DMA_Stream_TypeDef;
371
372 typedef struct
373 {
374 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
375 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
376 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
377 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
378 } DMA_TypeDef;
379
380 /**
381 * @brief Ethernet MAC
382 */
383
384 typedef struct
385 {
386 __IO uint32_t MACCR;
387 __IO uint32_t MACFFR;
388 __IO uint32_t MACHTHR;
389 __IO uint32_t MACHTLR;
390 __IO uint32_t MACMIIAR;
391 __IO uint32_t MACMIIDR;
392 __IO uint32_t MACFCR;
393 __IO uint32_t MACVLANTR; /* 8 */
394 uint32_t RESERVED0[2];
395 __IO uint32_t MACRWUFFR; /* 11 */
396 __IO uint32_t MACPMTCSR;
397 uint32_t RESERVED1;
398 __IO uint32_t MACDBGR;
399 __IO uint32_t MACSR; /* 15 */
400 __IO uint32_t MACIMR;
401 __IO uint32_t MACA0HR;
402 __IO uint32_t MACA0LR;
403 __IO uint32_t MACA1HR;
404 __IO uint32_t MACA1LR;
405 __IO uint32_t MACA2HR;
406 __IO uint32_t MACA2LR;
407 __IO uint32_t MACA3HR;
408 __IO uint32_t MACA3LR; /* 24 */
409 uint32_t RESERVED2[40];
410 __IO uint32_t MMCCR; /* 65 */
411 __IO uint32_t MMCRIR;
412 __IO uint32_t MMCTIR;
413 __IO uint32_t MMCRIMR;
414 __IO uint32_t MMCTIMR; /* 69 */
415 uint32_t RESERVED3[14];
416 __IO uint32_t MMCTGFSCCR; /* 84 */
417 __IO uint32_t MMCTGFMSCCR;
418 uint32_t RESERVED4[5];
419 __IO uint32_t MMCTGFCR;
420 uint32_t RESERVED5[10];
421 __IO uint32_t MMCRFCECR;
422 __IO uint32_t MMCRFAECR;
423 uint32_t RESERVED6[10];
424 __IO uint32_t MMCRGUFCR;
425 uint32_t RESERVED7[334];
426 __IO uint32_t PTPTSCR;
427 __IO uint32_t PTPSSIR;
428 __IO uint32_t PTPTSHR;
429 __IO uint32_t PTPTSLR;
430 __IO uint32_t PTPTSHUR;
431 __IO uint32_t PTPTSLUR;
432 __IO uint32_t PTPTSAR;
433 __IO uint32_t PTPTTHR;
434 __IO uint32_t PTPTTLR;
435 __IO uint32_t RESERVED8;
436 __IO uint32_t PTPTSSR;
437 uint32_t RESERVED9[565];
438 __IO uint32_t DMABMR;
439 __IO uint32_t DMATPDR;
440 __IO uint32_t DMARPDR;
441 __IO uint32_t DMARDLAR;
442 __IO uint32_t DMATDLAR;
443 __IO uint32_t DMASR;
444 __IO uint32_t DMAOMR;
445 __IO uint32_t DMAIER;
446 __IO uint32_t DMAMFBOCR;
447 __IO uint32_t DMARSWTR;
448 uint32_t RESERVED10[8];
449 __IO uint32_t DMACHTDR;
450 __IO uint32_t DMACHRDR;
451 __IO uint32_t DMACHTBAR;
452 __IO uint32_t DMACHRBAR;
453 } ETH_TypeDef;
454
455 /**
456 * @brief External Interrupt/Event Controller
457 */
458
459 typedef struct
460 {
461 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
462 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
463 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
464 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
465 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
466 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
467 } EXTI_TypeDef;
468
469 /**
470 * @brief FLASH Registers
471 */
472
473 typedef struct
474 {
475 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
476 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
477 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
478 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
479 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
480 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
481 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
482 } FLASH_TypeDef;
483
484
485
486 /**
487 * @brief Flexible Static Memory Controller
488 */
489
490 typedef struct
491 {
492 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
493 } FSMC_Bank1_TypeDef;
494
495 /**
496 * @brief Flexible Static Memory Controller Bank1E
497 */
498
499 typedef struct
500 {
501 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
502 } FSMC_Bank1E_TypeDef;
503
504 /**
505 * @brief Flexible Static Memory Controller Bank2
506 */
507
508 typedef struct
509 {
510 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
511 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
512 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
513 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
514 uint32_t RESERVED0; /*!< Reserved, 0x70 */
515 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
516 uint32_t RESERVED1; /*!< Reserved, 0x78 */
517 uint32_t RESERVED2; /*!< Reserved, 0x7C */
518 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
519 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
520 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
521 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
522 uint32_t RESERVED3; /*!< Reserved, 0x90 */
523 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
524 } FSMC_Bank2_3_TypeDef;
525
526 /**
527 * @brief Flexible Static Memory Controller Bank4
528 */
529
530 typedef struct
531 {
532 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
533 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
534 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
535 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
536 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
537 } FSMC_Bank4_TypeDef;
538
539 /**
540 * @brief General Purpose I/O
541 */
542
543 typedef struct
544 {
545 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
546 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
547 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
548 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
549 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
550 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
551 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
552 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
553 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
554 } GPIO_TypeDef;
555
556 /**
557 * @brief System configuration controller
558 */
559
560 typedef struct
561 {
562 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
563 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
564 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
565 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
566 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
567 } SYSCFG_TypeDef;
568
569 /**
570 * @brief Inter-integrated Circuit Interface
571 */
572
573 typedef struct
574 {
575 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
576 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
577 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
578 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
579 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
580 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
581 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
582 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
583 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
584 } I2C_TypeDef;
585
586 /**
587 * @brief Independent WATCHDOG
588 */
589
590 typedef struct
591 {
592 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
593 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
594 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
595 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
596 } IWDG_TypeDef;
597
598
599 /**
600 * @brief Power Control
601 */
602
603 typedef struct
604 {
605 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
606 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
607 } PWR_TypeDef;
608
609 /**
610 * @brief Reset and Clock Control
611 */
612
613 typedef struct
614 {
615 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
616 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
617 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
618 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
619 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
620 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
621 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
622 uint32_t RESERVED0; /*!< Reserved, 0x1C */
623 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
624 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
625 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
626 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
627 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
628 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
629 uint32_t RESERVED2; /*!< Reserved, 0x3C */
630 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
631 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
632 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
633 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
634 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
635 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
636 uint32_t RESERVED4; /*!< Reserved, 0x5C */
637 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
638 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
639 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
640 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
641 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
642 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
643 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
644 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
645 } RCC_TypeDef;
646
647 /**
648 * @brief Real-Time Clock
649 */
650
651 typedef struct
652 {
653 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
654 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
655 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
656 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
657 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
658 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
659 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
660 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
661 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
662 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
663 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
664 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
665 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
666 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
667 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
668 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
669 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
670 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
671 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
672 uint32_t RESERVED7; /*!< Reserved, 0x4C */
673 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
674 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
675 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
676 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
677 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
678 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
679 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
680 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
681 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
682 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
683 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
684 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
685 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
686 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
687 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
688 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
689 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
690 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
691 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
692 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
693 } RTC_TypeDef;
694
695 /**
696 * @brief SD host Interface
697 */
698
699 typedef struct
700 {
701 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
702 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
703 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
704 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
705 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
706 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
707 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
708 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
709 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
710 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
711 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
712 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
713 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
714 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
715 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
716 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
717 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
718 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
719 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
720 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
721 } SDIO_TypeDef;
722
723 /**
724 * @brief Serial Peripheral Interface
725 */
726
727 typedef struct
728 {
729 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
730 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
731 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
732 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
733 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
734 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
735 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
736 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
737 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
738 } SPI_TypeDef;
739
740
741 /**
742 * @brief TIM
743 */
744
745 typedef struct
746 {
747 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
748 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
749 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
750 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
751 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
752 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
753 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
754 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
755 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
756 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
757 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
758 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
759 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
760 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
761 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
762 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
763 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
764 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
765 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
766 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
767 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
768 } TIM_TypeDef;
769
770 /**
771 * @brief Universal Synchronous Asynchronous Receiver Transmitter
772 */
773
774 typedef struct
775 {
776 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
777 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
778 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
779 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
780 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
781 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
782 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
783 } USART_TypeDef;
784
785 /**
786 * @brief Window WATCHDOG
787 */
788
789 typedef struct
790 {
791 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
792 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
793 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
794 } WWDG_TypeDef;
795
796 /**
797 * @brief RNG
798 */
799
800 typedef struct
801 {
802 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
803 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
804 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
805 } RNG_TypeDef;
806
807 /**
808 * @brief USB_OTG_Core_Registers
809 */
810 typedef struct
811 {
812 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
813 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
814 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
815 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
816 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
817 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
818 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
819 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
820 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
821 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
822 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
823 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
824 uint32_t Reserved30[2]; /*!< Reserved 030h */
825 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
826 __IO uint32_t CID; /*!< User ID Register 03Ch */
827 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
828 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
829 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
830 } USB_OTG_GlobalTypeDef;
831
832 /**
833 * @brief USB_OTG_device_Registers
834 */
835 typedef struct
836 {
837 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
838 __IO uint32_t DCTL; /*!< dev Control Register 804h */
839 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
840 uint32_t Reserved0C; /*!< Reserved 80Ch */
841 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
842 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
843 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
844 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
845 uint32_t Reserved20; /*!< Reserved 820h */
846 uint32_t Reserved9; /*!< Reserved 824h */
847 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
848 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
849 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
850 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
851 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
852 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
853 uint32_t Reserved40; /*!< dedicated EP mask 840h */
854 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
855 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
856 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
857 } USB_OTG_DeviceTypeDef;
858
859 /**
860 * @brief USB_OTG_IN_Endpoint-Specific_Register
861 */
862 typedef struct
863 {
864 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
865 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
866 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
867 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
868 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
869 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
870 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
871 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
872 } USB_OTG_INEndpointTypeDef;
873
874 /**
875 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
876 */
877 typedef struct
878 {
879 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
880 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
881 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
882 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
883 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
884 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
885 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
886 } USB_OTG_OUTEndpointTypeDef;
887
888 /**
889 * @brief USB_OTG_Host_Mode_Register_Structures
890 */
891 typedef struct
892 {
893 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
894 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
895 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
896 uint32_t Reserved40C; /*!< Reserved 40Ch */
897 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
898 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
899 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
900 } USB_OTG_HostTypeDef;
901
902 /**
903 * @brief USB_OTG_Host_Channel_Specific_Registers
904 */
905 typedef struct
906 {
907 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
908 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
909 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
910 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
911 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
912 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
913 uint32_t Reserved[2]; /*!< Reserved */
914 } USB_OTG_HostChannelTypeDef;
915
916 /**
917 * @}
918 */
919
920 /** @addtogroup Peripheral_memory_map
921 * @{
922 */
923 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
924 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
925 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
926 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
927 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
928 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
929 #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
930 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
931 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
932 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
933 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
934 #define FLASH_END 0x080FFFFFU /*!< FLASH end address */
935 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
936 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
937 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
938
939 /* Legacy defines */
940 #define SRAM_BASE SRAM1_BASE
941 #define SRAM_BB_BASE SRAM1_BB_BASE
942
943 /*!< Peripheral memory map */
944 #define APB1PERIPH_BASE PERIPH_BASE
945 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
946 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
947 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
948
949 /*!< APB1 peripherals */
950 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
951 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
952 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
953 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
954 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
955 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
956 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
957 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
958 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
959 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
960 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
961 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
962 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
963 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
964 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
965 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
966 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
967 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
968 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
969 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
970 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
971 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
972 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
973 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
974 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
975 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
976 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
977
978 /*!< APB2 peripherals */
979 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
980 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
981 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
982 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
983 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
984 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
985 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
986 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
987 /* Legacy define */
988 #define ADC_BASE ADC123_COMMON_BASE
989 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
990 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
991 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
992 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
993 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
994 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
995 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
996
997 /*!< AHB1 peripherals */
998 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
999 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1000 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1001 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1002 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1003 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1004 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1005 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1006 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1007 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1008 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1009 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1010 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1011 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1012 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1013 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1014 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1015 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1016 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1017 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1018 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1019 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1020 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1021 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1022 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1023 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1024 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1025 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1026 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1027 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1028 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1029 #define ETH_MAC_BASE (ETH_BASE)
1030 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1031 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1032 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1033
1034 /*!< AHB2 peripherals */
1035 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1036 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1037
1038 /*!< FSMC Bankx registers base address */
1039 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
1040 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
1041 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
1042 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
1043
1044
1045 /*!< Debug MCU registers base address */
1046 #define DBGMCU_BASE 0xE0042000U
1047 /*!< USB registers base address */
1048 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1049 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1050
1051 #define USB_OTG_GLOBAL_BASE 0x000U
1052 #define USB_OTG_DEVICE_BASE 0x800U
1053 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1054 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1055 #define USB_OTG_EP_REG_SIZE 0x20U
1056 #define USB_OTG_HOST_BASE 0x400U
1057 #define USB_OTG_HOST_PORT_BASE 0x440U
1058 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1059 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1060 #define USB_OTG_PCGCCTL_BASE 0xE00U
1061 #define USB_OTG_FIFO_BASE 0x1000U
1062 #define USB_OTG_FIFO_SIZE 0x1000U
1063
1064 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
1065 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
1066 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1067 /**
1068 * @}
1069 */
1070
1071 /** @addtogroup Peripheral_declaration
1072 * @{
1073 */
1074 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1075 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1076 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1077 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1078 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1079 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1080 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1081 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1082 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1083 #define RTC ((RTC_TypeDef *) RTC_BASE)
1084 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1085 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1086 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1087 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1088 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1089 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1090 #define USART2 ((USART_TypeDef *) USART2_BASE)
1091 #define USART3 ((USART_TypeDef *) USART3_BASE)
1092 #define UART4 ((USART_TypeDef *) UART4_BASE)
1093 #define UART5 ((USART_TypeDef *) UART5_BASE)
1094 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1095 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1096 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1097 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1098 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1099 #define PWR ((PWR_TypeDef *) PWR_BASE)
1100 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1101 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1102 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1103 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1104 #define USART1 ((USART_TypeDef *) USART1_BASE)
1105 #define USART6 ((USART_TypeDef *) USART6_BASE)
1106 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1107 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1108 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1109 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1110 /* Legacy define */
1111 #define ADC ADC123_COMMON
1112 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1113 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1114 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1115 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1116 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1117 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1118 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1119 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1120 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1121 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1122 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1123 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1124 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1125 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1126 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1127 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1128 #define CRC ((CRC_TypeDef *) CRC_BASE)
1129 #define RCC ((RCC_TypeDef *) RCC_BASE)
1130 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1131 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1132 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1133 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1134 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1135 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1136 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1137 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1138 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1139 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1140 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1141 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1142 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1143 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1144 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1145 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1146 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1147 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1148 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1149 #define ETH ((ETH_TypeDef *) ETH_BASE)
1150 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1151 #define RNG ((RNG_TypeDef *) RNG_BASE)
1152 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1153 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1154 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1155 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1156 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1157 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1158 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1159
1160 /**
1161 * @}
1162 */
1163
1164 /** @addtogroup Exported_constants
1165 * @{
1166 */
1167
1168 /** @addtogroup Peripheral_Registers_Bits_Definition
1169 * @{
1170 */
1171
1172 /******************************************************************************/
1173 /* Peripheral Registers_Bits_Definition */
1174 /******************************************************************************/
1175
1176 /******************************************************************************/
1177 /* */
1178 /* Analog to Digital Converter */
1179 /* */
1180 /******************************************************************************/
1181 /*
1182 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1183 */
1184 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
1185
1186 /******************** Bit definition for ADC_SR register ********************/
1187 #define ADC_SR_AWD_Pos (0U)
1188 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1189 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1190 #define ADC_SR_EOC_Pos (1U)
1191 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1192 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1193 #define ADC_SR_JEOC_Pos (2U)
1194 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1195 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1196 #define ADC_SR_JSTRT_Pos (3U)
1197 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1198 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1199 #define ADC_SR_STRT_Pos (4U)
1200 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1201 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1202 #define ADC_SR_OVR_Pos (5U)
1203 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1204 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1205
1206 /******************* Bit definition for ADC_CR1 register ********************/
1207 #define ADC_CR1_AWDCH_Pos (0U)
1208 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1209 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1210 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1211 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1212 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1213 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1214 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1215 #define ADC_CR1_EOCIE_Pos (5U)
1216 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1217 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1218 #define ADC_CR1_AWDIE_Pos (6U)
1219 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1220 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1221 #define ADC_CR1_JEOCIE_Pos (7U)
1222 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1223 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1224 #define ADC_CR1_SCAN_Pos (8U)
1225 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1226 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1227 #define ADC_CR1_AWDSGL_Pos (9U)
1228 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1229 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1230 #define ADC_CR1_JAUTO_Pos (10U)
1231 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1232 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1233 #define ADC_CR1_DISCEN_Pos (11U)
1234 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1235 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1236 #define ADC_CR1_JDISCEN_Pos (12U)
1237 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1238 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1239 #define ADC_CR1_DISCNUM_Pos (13U)
1240 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1241 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1242 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1243 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1244 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1245 #define ADC_CR1_JAWDEN_Pos (22U)
1246 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1247 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1248 #define ADC_CR1_AWDEN_Pos (23U)
1249 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1250 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1251 #define ADC_CR1_RES_Pos (24U)
1252 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1253 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1254 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1255 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1256 #define ADC_CR1_OVRIE_Pos (26U)
1257 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1258 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1259
1260 /******************* Bit definition for ADC_CR2 register ********************/
1261 #define ADC_CR2_ADON_Pos (0U)
1262 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1263 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1264 #define ADC_CR2_CONT_Pos (1U)
1265 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1266 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1267 #define ADC_CR2_DMA_Pos (8U)
1268 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1269 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1270 #define ADC_CR2_DDS_Pos (9U)
1271 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1272 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1273 #define ADC_CR2_EOCS_Pos (10U)
1274 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1275 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1276 #define ADC_CR2_ALIGN_Pos (11U)
1277 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1278 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1279 #define ADC_CR2_JEXTSEL_Pos (16U)
1280 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1281 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1282 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1283 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1284 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1285 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1286 #define ADC_CR2_JEXTEN_Pos (20U)
1287 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1288 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1289 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1290 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1291 #define ADC_CR2_JSWSTART_Pos (22U)
1292 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1293 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1294 #define ADC_CR2_EXTSEL_Pos (24U)
1295 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1296 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1297 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1298 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1299 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1300 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1301 #define ADC_CR2_EXTEN_Pos (28U)
1302 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1303 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1304 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1305 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1306 #define ADC_CR2_SWSTART_Pos (30U)
1307 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1308 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1309
1310 /****************** Bit definition for ADC_SMPR1 register *******************/
1311 #define ADC_SMPR1_SMP10_Pos (0U)
1312 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1313 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1314 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1315 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1316 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1317 #define ADC_SMPR1_SMP11_Pos (3U)
1318 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1319 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1320 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1321 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1322 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1323 #define ADC_SMPR1_SMP12_Pos (6U)
1324 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1325 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1326 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1327 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1328 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1329 #define ADC_SMPR1_SMP13_Pos (9U)
1330 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1331 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1332 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1333 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1334 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1335 #define ADC_SMPR1_SMP14_Pos (12U)
1336 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1337 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1338 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1339 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1340 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1341 #define ADC_SMPR1_SMP15_Pos (15U)
1342 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1343 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1344 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1345 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1346 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1347 #define ADC_SMPR1_SMP16_Pos (18U)
1348 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1349 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1350 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1351 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1352 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1353 #define ADC_SMPR1_SMP17_Pos (21U)
1354 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1355 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1356 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1357 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1358 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1359 #define ADC_SMPR1_SMP18_Pos (24U)
1360 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1361 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1362 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1363 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1364 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1365
1366 /****************** Bit definition for ADC_SMPR2 register *******************/
1367 #define ADC_SMPR2_SMP0_Pos (0U)
1368 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1369 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1370 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1371 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1372 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1373 #define ADC_SMPR2_SMP1_Pos (3U)
1374 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1375 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1376 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1377 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1378 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1379 #define ADC_SMPR2_SMP2_Pos (6U)
1380 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1381 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1382 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1383 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1384 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1385 #define ADC_SMPR2_SMP3_Pos (9U)
1386 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1387 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1388 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1389 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1390 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1391 #define ADC_SMPR2_SMP4_Pos (12U)
1392 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1393 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1394 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1395 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1396 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1397 #define ADC_SMPR2_SMP5_Pos (15U)
1398 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1399 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1400 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1401 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1402 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1403 #define ADC_SMPR2_SMP6_Pos (18U)
1404 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1405 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1406 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1407 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1408 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1409 #define ADC_SMPR2_SMP7_Pos (21U)
1410 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1411 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1412 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1413 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1414 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1415 #define ADC_SMPR2_SMP8_Pos (24U)
1416 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1417 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1418 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1419 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1420 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1421 #define ADC_SMPR2_SMP9_Pos (27U)
1422 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1423 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1424 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1425 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1426 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1427
1428 /****************** Bit definition for ADC_JOFR1 register *******************/
1429 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1430 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1431 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1432
1433 /****************** Bit definition for ADC_JOFR2 register *******************/
1434 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1435 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1436 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1437
1438 /****************** Bit definition for ADC_JOFR3 register *******************/
1439 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1440 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1441 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1442
1443 /****************** Bit definition for ADC_JOFR4 register *******************/
1444 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1445 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1446 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1447
1448 /******************* Bit definition for ADC_HTR register ********************/
1449 #define ADC_HTR_HT_Pos (0U)
1450 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1451 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1452
1453 /******************* Bit definition for ADC_LTR register ********************/
1454 #define ADC_LTR_LT_Pos (0U)
1455 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1456 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1457
1458 /******************* Bit definition for ADC_SQR1 register *******************/
1459 #define ADC_SQR1_SQ13_Pos (0U)
1460 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1461 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1462 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1463 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1464 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1465 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1466 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1467 #define ADC_SQR1_SQ14_Pos (5U)
1468 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1469 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1470 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1471 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1472 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1473 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1474 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1475 #define ADC_SQR1_SQ15_Pos (10U)
1476 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1477 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1478 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1479 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1480 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1481 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1482 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1483 #define ADC_SQR1_SQ16_Pos (15U)
1484 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1485 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1486 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1487 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1488 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1489 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1490 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1491 #define ADC_SQR1_L_Pos (20U)
1492 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1493 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1494 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1495 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1496 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1497 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1498
1499 /******************* Bit definition for ADC_SQR2 register *******************/
1500 #define ADC_SQR2_SQ7_Pos (0U)
1501 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1502 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1503 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1504 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1505 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1506 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1507 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1508 #define ADC_SQR2_SQ8_Pos (5U)
1509 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1510 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1511 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1512 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1513 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1514 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1515 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1516 #define ADC_SQR2_SQ9_Pos (10U)
1517 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1518 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1519 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1520 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1521 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1522 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1523 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1524 #define ADC_SQR2_SQ10_Pos (15U)
1525 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1526 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1527 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1528 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1529 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1530 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1531 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1532 #define ADC_SQR2_SQ11_Pos (20U)
1533 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1534 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1535 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1536 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1537 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1538 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1539 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1540 #define ADC_SQR2_SQ12_Pos (25U)
1541 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1542 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1543 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1544 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1545 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1546 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1547 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1548
1549 /******************* Bit definition for ADC_SQR3 register *******************/
1550 #define ADC_SQR3_SQ1_Pos (0U)
1551 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1552 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1553 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1554 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1555 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1556 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1557 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1558 #define ADC_SQR3_SQ2_Pos (5U)
1559 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1560 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1561 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1562 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1563 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1564 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1565 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1566 #define ADC_SQR3_SQ3_Pos (10U)
1567 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1568 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1569 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1570 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1571 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1572 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1573 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1574 #define ADC_SQR3_SQ4_Pos (15U)
1575 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1576 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1577 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1578 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1579 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1580 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1581 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1582 #define ADC_SQR3_SQ5_Pos (20U)
1583 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1584 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1585 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1586 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1587 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1588 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1589 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1590 #define ADC_SQR3_SQ6_Pos (25U)
1591 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1592 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1593 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1594 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1595 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1596 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1597 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1598
1599 /******************* Bit definition for ADC_JSQR register *******************/
1600 #define ADC_JSQR_JSQ1_Pos (0U)
1601 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1602 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1603 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1604 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1605 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1606 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1607 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1608 #define ADC_JSQR_JSQ2_Pos (5U)
1609 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1610 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1611 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1612 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1613 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1614 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1615 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1616 #define ADC_JSQR_JSQ3_Pos (10U)
1617 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1618 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1619 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1620 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1621 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1622 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1623 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1624 #define ADC_JSQR_JSQ4_Pos (15U)
1625 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1626 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1627 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1628 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1629 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1630 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1631 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1632 #define ADC_JSQR_JL_Pos (20U)
1633 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1634 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1635 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1636 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1637
1638 /******************* Bit definition for ADC_JDR1 register *******************/
1639 #define ADC_JDR1_JDATA_Pos (0U)
1640 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1641 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1642
1643 /******************* Bit definition for ADC_JDR2 register *******************/
1644 #define ADC_JDR2_JDATA_Pos (0U)
1645 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1646 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1647
1648 /******************* Bit definition for ADC_JDR3 register *******************/
1649 #define ADC_JDR3_JDATA_Pos (0U)
1650 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1651 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1652
1653 /******************* Bit definition for ADC_JDR4 register *******************/
1654 #define ADC_JDR4_JDATA_Pos (0U)
1655 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1656 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1657
1658 /******************** Bit definition for ADC_DR register ********************/
1659 #define ADC_DR_DATA_Pos (0U)
1660 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1661 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1662 #define ADC_DR_ADC2DATA_Pos (16U)
1663 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1664 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1665
1666 /******************* Bit definition for ADC_CSR register ********************/
1667 #define ADC_CSR_AWD1_Pos (0U)
1668 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1669 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1670 #define ADC_CSR_EOC1_Pos (1U)
1671 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1672 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1673 #define ADC_CSR_JEOC1_Pos (2U)
1674 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1675 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1676 #define ADC_CSR_JSTRT1_Pos (3U)
1677 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1678 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1679 #define ADC_CSR_STRT1_Pos (4U)
1680 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1681 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1682 #define ADC_CSR_OVR1_Pos (5U)
1683 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1684 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1685 #define ADC_CSR_AWD2_Pos (8U)
1686 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
1687 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
1688 #define ADC_CSR_EOC2_Pos (9U)
1689 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
1690 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
1691 #define ADC_CSR_JEOC2_Pos (10U)
1692 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
1693 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
1694 #define ADC_CSR_JSTRT2_Pos (11U)
1695 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
1696 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
1697 #define ADC_CSR_STRT2_Pos (12U)
1698 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
1699 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
1700 #define ADC_CSR_OVR2_Pos (13U)
1701 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
1702 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
1703 #define ADC_CSR_AWD3_Pos (16U)
1704 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
1705 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
1706 #define ADC_CSR_EOC3_Pos (17U)
1707 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
1708 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
1709 #define ADC_CSR_JEOC3_Pos (18U)
1710 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
1711 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
1712 #define ADC_CSR_JSTRT3_Pos (19U)
1713 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
1714 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
1715 #define ADC_CSR_STRT3_Pos (20U)
1716 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
1717 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
1718 #define ADC_CSR_OVR3_Pos (21U)
1719 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
1720 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
1721
1722 /* Legacy defines */
1723 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1724 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1725 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1726
1727 /******************* Bit definition for ADC_CCR register ********************/
1728 #define ADC_CCR_MULTI_Pos (0U)
1729 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1730 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1731 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1732 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1733 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1734 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1735 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1736 #define ADC_CCR_DELAY_Pos (8U)
1737 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1738 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1739 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1740 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1741 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1742 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1743 #define ADC_CCR_DDS_Pos (13U)
1744 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1745 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1746 #define ADC_CCR_DMA_Pos (14U)
1747 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1748 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1749 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1750 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1751 #define ADC_CCR_ADCPRE_Pos (16U)
1752 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1753 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1754 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1755 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1756 #define ADC_CCR_VBATE_Pos (22U)
1757 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1758 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1759 #define ADC_CCR_TSVREFE_Pos (23U)
1760 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1761 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1762
1763 /******************* Bit definition for ADC_CDR register ********************/
1764 #define ADC_CDR_DATA1_Pos (0U)
1765 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1766 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1767 #define ADC_CDR_DATA2_Pos (16U)
1768 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1769 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1770
1771 /* Legacy defines */
1772 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1773 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1774
1775 /******************************************************************************/
1776 /* */
1777 /* Controller Area Network */
1778 /* */
1779 /******************************************************************************/
1780 /*!<CAN control and status registers */
1781 /******************* Bit definition for CAN_MCR register ********************/
1782 #define CAN_MCR_INRQ_Pos (0U)
1783 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
1784 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
1785 #define CAN_MCR_SLEEP_Pos (1U)
1786 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
1787 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
1788 #define CAN_MCR_TXFP_Pos (2U)
1789 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
1790 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
1791 #define CAN_MCR_RFLM_Pos (3U)
1792 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
1793 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
1794 #define CAN_MCR_NART_Pos (4U)
1795 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
1796 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
1797 #define CAN_MCR_AWUM_Pos (5U)
1798 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
1799 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
1800 #define CAN_MCR_ABOM_Pos (6U)
1801 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
1802 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
1803 #define CAN_MCR_TTCM_Pos (7U)
1804 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
1805 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
1806 #define CAN_MCR_RESET_Pos (15U)
1807 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
1808 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
1809 #define CAN_MCR_DBF_Pos (16U)
1810 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
1811 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
1812 /******************* Bit definition for CAN_MSR register ********************/
1813 #define CAN_MSR_INAK_Pos (0U)
1814 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
1815 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
1816 #define CAN_MSR_SLAK_Pos (1U)
1817 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
1818 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
1819 #define CAN_MSR_ERRI_Pos (2U)
1820 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
1821 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
1822 #define CAN_MSR_WKUI_Pos (3U)
1823 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
1824 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
1825 #define CAN_MSR_SLAKI_Pos (4U)
1826 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
1827 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
1828 #define CAN_MSR_TXM_Pos (8U)
1829 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
1830 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
1831 #define CAN_MSR_RXM_Pos (9U)
1832 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
1833 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
1834 #define CAN_MSR_SAMP_Pos (10U)
1835 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
1836 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
1837 #define CAN_MSR_RX_Pos (11U)
1838 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
1839 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
1840
1841 /******************* Bit definition for CAN_TSR register ********************/
1842 #define CAN_TSR_RQCP0_Pos (0U)
1843 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
1844 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
1845 #define CAN_TSR_TXOK0_Pos (1U)
1846 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
1847 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
1848 #define CAN_TSR_ALST0_Pos (2U)
1849 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
1850 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
1851 #define CAN_TSR_TERR0_Pos (3U)
1852 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
1853 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
1854 #define CAN_TSR_ABRQ0_Pos (7U)
1855 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
1856 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
1857 #define CAN_TSR_RQCP1_Pos (8U)
1858 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
1859 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
1860 #define CAN_TSR_TXOK1_Pos (9U)
1861 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
1862 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
1863 #define CAN_TSR_ALST1_Pos (10U)
1864 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
1865 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
1866 #define CAN_TSR_TERR1_Pos (11U)
1867 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
1868 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
1869 #define CAN_TSR_ABRQ1_Pos (15U)
1870 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
1871 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
1872 #define CAN_TSR_RQCP2_Pos (16U)
1873 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
1874 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
1875 #define CAN_TSR_TXOK2_Pos (17U)
1876 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
1877 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
1878 #define CAN_TSR_ALST2_Pos (18U)
1879 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
1880 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
1881 #define CAN_TSR_TERR2_Pos (19U)
1882 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
1883 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
1884 #define CAN_TSR_ABRQ2_Pos (23U)
1885 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
1886 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
1887 #define CAN_TSR_CODE_Pos (24U)
1888 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
1889 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
1890
1891 #define CAN_TSR_TME_Pos (26U)
1892 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
1893 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
1894 #define CAN_TSR_TME0_Pos (26U)
1895 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
1896 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
1897 #define CAN_TSR_TME1_Pos (27U)
1898 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
1899 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
1900 #define CAN_TSR_TME2_Pos (28U)
1901 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
1902 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
1903
1904 #define CAN_TSR_LOW_Pos (29U)
1905 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
1906 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
1907 #define CAN_TSR_LOW0_Pos (29U)
1908 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
1909 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
1910 #define CAN_TSR_LOW1_Pos (30U)
1911 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
1912 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
1913 #define CAN_TSR_LOW2_Pos (31U)
1914 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
1915 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
1916
1917 /******************* Bit definition for CAN_RF0R register *******************/
1918 #define CAN_RF0R_FMP0_Pos (0U)
1919 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
1920 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
1921 #define CAN_RF0R_FULL0_Pos (3U)
1922 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
1923 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
1924 #define CAN_RF0R_FOVR0_Pos (4U)
1925 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
1926 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
1927 #define CAN_RF0R_RFOM0_Pos (5U)
1928 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
1929 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
1930
1931 /******************* Bit definition for CAN_RF1R register *******************/
1932 #define CAN_RF1R_FMP1_Pos (0U)
1933 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
1934 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
1935 #define CAN_RF1R_FULL1_Pos (3U)
1936 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
1937 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
1938 #define CAN_RF1R_FOVR1_Pos (4U)
1939 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
1940 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
1941 #define CAN_RF1R_RFOM1_Pos (5U)
1942 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
1943 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
1944
1945 /******************** Bit definition for CAN_IER register *******************/
1946 #define CAN_IER_TMEIE_Pos (0U)
1947 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
1948 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
1949 #define CAN_IER_FMPIE0_Pos (1U)
1950 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
1951 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
1952 #define CAN_IER_FFIE0_Pos (2U)
1953 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
1954 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
1955 #define CAN_IER_FOVIE0_Pos (3U)
1956 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
1957 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
1958 #define CAN_IER_FMPIE1_Pos (4U)
1959 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
1960 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
1961 #define CAN_IER_FFIE1_Pos (5U)
1962 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
1963 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
1964 #define CAN_IER_FOVIE1_Pos (6U)
1965 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
1966 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
1967 #define CAN_IER_EWGIE_Pos (8U)
1968 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
1969 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
1970 #define CAN_IER_EPVIE_Pos (9U)
1971 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
1972 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
1973 #define CAN_IER_BOFIE_Pos (10U)
1974 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
1975 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
1976 #define CAN_IER_LECIE_Pos (11U)
1977 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
1978 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
1979 #define CAN_IER_ERRIE_Pos (15U)
1980 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
1981 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
1982 #define CAN_IER_WKUIE_Pos (16U)
1983 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
1984 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
1985 #define CAN_IER_SLKIE_Pos (17U)
1986 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
1987 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
1988 #define CAN_IER_EWGIE_Pos (8U)
1989
1990 /******************** Bit definition for CAN_ESR register *******************/
1991 #define CAN_ESR_EWGF_Pos (0U)
1992 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
1993 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
1994 #define CAN_ESR_EPVF_Pos (1U)
1995 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
1996 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
1997 #define CAN_ESR_BOFF_Pos (2U)
1998 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
1999 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2000
2001 #define CAN_ESR_LEC_Pos (4U)
2002 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2003 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2004 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2005 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2006 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2007
2008 #define CAN_ESR_TEC_Pos (16U)
2009 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2010 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2011 #define CAN_ESR_REC_Pos (24U)
2012 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2013 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2014
2015 /******************* Bit definition for CAN_BTR register ********************/
2016 #define CAN_BTR_BRP_Pos (0U)
2017 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2018 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2019 #define CAN_BTR_TS1_Pos (16U)
2020 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2021 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2022 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2023 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2024 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2025 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2026 #define CAN_BTR_TS2_Pos (20U)
2027 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2028 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2029 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2030 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2031 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2032 #define CAN_BTR_SJW_Pos (24U)
2033 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2034 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2035 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2036 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2037 #define CAN_BTR_LBKM_Pos (30U)
2038 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2039 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2040 #define CAN_BTR_SILM_Pos (31U)
2041 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2042 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2043
2044
2045 /*!<Mailbox registers */
2046 /****************** Bit definition for CAN_TI0R register ********************/
2047 #define CAN_TI0R_TXRQ_Pos (0U)
2048 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2049 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2050 #define CAN_TI0R_RTR_Pos (1U)
2051 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2052 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2053 #define CAN_TI0R_IDE_Pos (2U)
2054 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2055 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2056 #define CAN_TI0R_EXID_Pos (3U)
2057 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2058 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2059 #define CAN_TI0R_STID_Pos (21U)
2060 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2061 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2062
2063 /****************** Bit definition for CAN_TDT0R register *******************/
2064 #define CAN_TDT0R_DLC_Pos (0U)
2065 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2066 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2067 #define CAN_TDT0R_TGT_Pos (8U)
2068 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2069 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2070 #define CAN_TDT0R_TIME_Pos (16U)
2071 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2072 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2073
2074 /****************** Bit definition for CAN_TDL0R register *******************/
2075 #define CAN_TDL0R_DATA0_Pos (0U)
2076 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2077 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2078 #define CAN_TDL0R_DATA1_Pos (8U)
2079 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2080 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2081 #define CAN_TDL0R_DATA2_Pos (16U)
2082 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2083 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2084 #define CAN_TDL0R_DATA3_Pos (24U)
2085 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2086 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2087
2088 /****************** Bit definition for CAN_TDH0R register *******************/
2089 #define CAN_TDH0R_DATA4_Pos (0U)
2090 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2091 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2092 #define CAN_TDH0R_DATA5_Pos (8U)
2093 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2094 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2095 #define CAN_TDH0R_DATA6_Pos (16U)
2096 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2097 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2098 #define CAN_TDH0R_DATA7_Pos (24U)
2099 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2100 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2101
2102 /******************* Bit definition for CAN_TI1R register *******************/
2103 #define CAN_TI1R_TXRQ_Pos (0U)
2104 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2105 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2106 #define CAN_TI1R_RTR_Pos (1U)
2107 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2108 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2109 #define CAN_TI1R_IDE_Pos (2U)
2110 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2111 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2112 #define CAN_TI1R_EXID_Pos (3U)
2113 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2114 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2115 #define CAN_TI1R_STID_Pos (21U)
2116 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2117 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2118
2119 /******************* Bit definition for CAN_TDT1R register ******************/
2120 #define CAN_TDT1R_DLC_Pos (0U)
2121 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2122 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2123 #define CAN_TDT1R_TGT_Pos (8U)
2124 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2125 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2126 #define CAN_TDT1R_TIME_Pos (16U)
2127 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2128 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2129
2130 /******************* Bit definition for CAN_TDL1R register ******************/
2131 #define CAN_TDL1R_DATA0_Pos (0U)
2132 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2133 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2134 #define CAN_TDL1R_DATA1_Pos (8U)
2135 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2136 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2137 #define CAN_TDL1R_DATA2_Pos (16U)
2138 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2139 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2140 #define CAN_TDL1R_DATA3_Pos (24U)
2141 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2142 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2143
2144 /******************* Bit definition for CAN_TDH1R register ******************/
2145 #define CAN_TDH1R_DATA4_Pos (0U)
2146 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2147 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2148 #define CAN_TDH1R_DATA5_Pos (8U)
2149 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2150 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2151 #define CAN_TDH1R_DATA6_Pos (16U)
2152 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2153 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2154 #define CAN_TDH1R_DATA7_Pos (24U)
2155 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2156 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2157
2158 /******************* Bit definition for CAN_TI2R register *******************/
2159 #define CAN_TI2R_TXRQ_Pos (0U)
2160 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2161 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2162 #define CAN_TI2R_RTR_Pos (1U)
2163 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2164 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2165 #define CAN_TI2R_IDE_Pos (2U)
2166 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2167 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2168 #define CAN_TI2R_EXID_Pos (3U)
2169 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2170 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2171 #define CAN_TI2R_STID_Pos (21U)
2172 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2173 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2174
2175 /******************* Bit definition for CAN_TDT2R register ******************/
2176 #define CAN_TDT2R_DLC_Pos (0U)
2177 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2178 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2179 #define CAN_TDT2R_TGT_Pos (8U)
2180 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2181 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2182 #define CAN_TDT2R_TIME_Pos (16U)
2183 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2184 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2185
2186 /******************* Bit definition for CAN_TDL2R register ******************/
2187 #define CAN_TDL2R_DATA0_Pos (0U)
2188 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2189 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2190 #define CAN_TDL2R_DATA1_Pos (8U)
2191 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2192 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2193 #define CAN_TDL2R_DATA2_Pos (16U)
2194 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2195 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2196 #define CAN_TDL2R_DATA3_Pos (24U)
2197 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2198 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2199
2200 /******************* Bit definition for CAN_TDH2R register ******************/
2201 #define CAN_TDH2R_DATA4_Pos (0U)
2202 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2203 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2204 #define CAN_TDH2R_DATA5_Pos (8U)
2205 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2206 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2207 #define CAN_TDH2R_DATA6_Pos (16U)
2208 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2209 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2210 #define CAN_TDH2R_DATA7_Pos (24U)
2211 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2212 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2213
2214 /******************* Bit definition for CAN_RI0R register *******************/
2215 #define CAN_RI0R_RTR_Pos (1U)
2216 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2217 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2218 #define CAN_RI0R_IDE_Pos (2U)
2219 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2220 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2221 #define CAN_RI0R_EXID_Pos (3U)
2222 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2223 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2224 #define CAN_RI0R_STID_Pos (21U)
2225 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2226 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2227
2228 /******************* Bit definition for CAN_RDT0R register ******************/
2229 #define CAN_RDT0R_DLC_Pos (0U)
2230 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2231 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2232 #define CAN_RDT0R_FMI_Pos (8U)
2233 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2234 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2235 #define CAN_RDT0R_TIME_Pos (16U)
2236 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2237 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2238
2239 /******************* Bit definition for CAN_RDL0R register ******************/
2240 #define CAN_RDL0R_DATA0_Pos (0U)
2241 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2242 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2243 #define CAN_RDL0R_DATA1_Pos (8U)
2244 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2245 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2246 #define CAN_RDL0R_DATA2_Pos (16U)
2247 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2248 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2249 #define CAN_RDL0R_DATA3_Pos (24U)
2250 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2251 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2252
2253 /******************* Bit definition for CAN_RDH0R register ******************/
2254 #define CAN_RDH0R_DATA4_Pos (0U)
2255 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2256 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2257 #define CAN_RDH0R_DATA5_Pos (8U)
2258 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2259 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2260 #define CAN_RDH0R_DATA6_Pos (16U)
2261 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2262 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2263 #define CAN_RDH0R_DATA7_Pos (24U)
2264 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2265 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2266
2267 /******************* Bit definition for CAN_RI1R register *******************/
2268 #define CAN_RI1R_RTR_Pos (1U)
2269 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2270 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2271 #define CAN_RI1R_IDE_Pos (2U)
2272 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2273 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2274 #define CAN_RI1R_EXID_Pos (3U)
2275 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2276 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2277 #define CAN_RI1R_STID_Pos (21U)
2278 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2279 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2280
2281 /******************* Bit definition for CAN_RDT1R register ******************/
2282 #define CAN_RDT1R_DLC_Pos (0U)
2283 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2284 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2285 #define CAN_RDT1R_FMI_Pos (8U)
2286 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2287 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2288 #define CAN_RDT1R_TIME_Pos (16U)
2289 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2290 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2291
2292 /******************* Bit definition for CAN_RDL1R register ******************/
2293 #define CAN_RDL1R_DATA0_Pos (0U)
2294 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2295 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2296 #define CAN_RDL1R_DATA1_Pos (8U)
2297 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2298 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2299 #define CAN_RDL1R_DATA2_Pos (16U)
2300 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2301 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2302 #define CAN_RDL1R_DATA3_Pos (24U)
2303 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2304 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2305
2306 /******************* Bit definition for CAN_RDH1R register ******************/
2307 #define CAN_RDH1R_DATA4_Pos (0U)
2308 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2309 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2310 #define CAN_RDH1R_DATA5_Pos (8U)
2311 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2312 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2313 #define CAN_RDH1R_DATA6_Pos (16U)
2314 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2315 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2316 #define CAN_RDH1R_DATA7_Pos (24U)
2317 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2318 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2319
2320 /*!<CAN filter registers */
2321 /******************* Bit definition for CAN_FMR register ********************/
2322 #define CAN_FMR_FINIT_Pos (0U)
2323 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2324 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2325 #define CAN_FMR_CAN2SB_Pos (8U)
2326 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2327 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2328
2329 /******************* Bit definition for CAN_FM1R register *******************/
2330 #define CAN_FM1R_FBM_Pos (0U)
2331 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2332 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2333 #define CAN_FM1R_FBM0_Pos (0U)
2334 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2335 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2336 #define CAN_FM1R_FBM1_Pos (1U)
2337 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2338 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2339 #define CAN_FM1R_FBM2_Pos (2U)
2340 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2341 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2342 #define CAN_FM1R_FBM3_Pos (3U)
2343 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2344 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2345 #define CAN_FM1R_FBM4_Pos (4U)
2346 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2347 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2348 #define CAN_FM1R_FBM5_Pos (5U)
2349 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2350 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2351 #define CAN_FM1R_FBM6_Pos (6U)
2352 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2353 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2354 #define CAN_FM1R_FBM7_Pos (7U)
2355 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2356 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2357 #define CAN_FM1R_FBM8_Pos (8U)
2358 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2359 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2360 #define CAN_FM1R_FBM9_Pos (9U)
2361 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2362 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2363 #define CAN_FM1R_FBM10_Pos (10U)
2364 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2365 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2366 #define CAN_FM1R_FBM11_Pos (11U)
2367 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2368 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2369 #define CAN_FM1R_FBM12_Pos (12U)
2370 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2371 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2372 #define CAN_FM1R_FBM13_Pos (13U)
2373 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2374 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2375 #define CAN_FM1R_FBM14_Pos (14U)
2376 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2377 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2378 #define CAN_FM1R_FBM15_Pos (15U)
2379 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2380 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2381 #define CAN_FM1R_FBM16_Pos (16U)
2382 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2383 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2384 #define CAN_FM1R_FBM17_Pos (17U)
2385 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2386 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2387 #define CAN_FM1R_FBM18_Pos (18U)
2388 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2389 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2390 #define CAN_FM1R_FBM19_Pos (19U)
2391 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2392 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2393 #define CAN_FM1R_FBM20_Pos (20U)
2394 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2395 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2396 #define CAN_FM1R_FBM21_Pos (21U)
2397 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2398 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2399 #define CAN_FM1R_FBM22_Pos (22U)
2400 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2401 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2402 #define CAN_FM1R_FBM23_Pos (23U)
2403 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2404 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2405 #define CAN_FM1R_FBM24_Pos (24U)
2406 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2407 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2408 #define CAN_FM1R_FBM25_Pos (25U)
2409 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2410 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2411 #define CAN_FM1R_FBM26_Pos (26U)
2412 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2413 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2414 #define CAN_FM1R_FBM27_Pos (27U)
2415 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2416 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2417
2418 /******************* Bit definition for CAN_FS1R register *******************/
2419 #define CAN_FS1R_FSC_Pos (0U)
2420 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2421 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2422 #define CAN_FS1R_FSC0_Pos (0U)
2423 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2424 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2425 #define CAN_FS1R_FSC1_Pos (1U)
2426 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2427 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2428 #define CAN_FS1R_FSC2_Pos (2U)
2429 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2430 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2431 #define CAN_FS1R_FSC3_Pos (3U)
2432 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2433 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2434 #define CAN_FS1R_FSC4_Pos (4U)
2435 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2436 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2437 #define CAN_FS1R_FSC5_Pos (5U)
2438 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2439 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2440 #define CAN_FS1R_FSC6_Pos (6U)
2441 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2442 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2443 #define CAN_FS1R_FSC7_Pos (7U)
2444 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2445 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2446 #define CAN_FS1R_FSC8_Pos (8U)
2447 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2448 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2449 #define CAN_FS1R_FSC9_Pos (9U)
2450 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2451 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2452 #define CAN_FS1R_FSC10_Pos (10U)
2453 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2454 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2455 #define CAN_FS1R_FSC11_Pos (11U)
2456 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2457 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2458 #define CAN_FS1R_FSC12_Pos (12U)
2459 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2460 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2461 #define CAN_FS1R_FSC13_Pos (13U)
2462 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2463 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2464 #define CAN_FS1R_FSC14_Pos (14U)
2465 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2466 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2467 #define CAN_FS1R_FSC15_Pos (15U)
2468 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2469 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2470 #define CAN_FS1R_FSC16_Pos (16U)
2471 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2472 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2473 #define CAN_FS1R_FSC17_Pos (17U)
2474 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2475 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2476 #define CAN_FS1R_FSC18_Pos (18U)
2477 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2478 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2479 #define CAN_FS1R_FSC19_Pos (19U)
2480 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2481 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2482 #define CAN_FS1R_FSC20_Pos (20U)
2483 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2484 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2485 #define CAN_FS1R_FSC21_Pos (21U)
2486 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2487 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2488 #define CAN_FS1R_FSC22_Pos (22U)
2489 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2490 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2491 #define CAN_FS1R_FSC23_Pos (23U)
2492 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2493 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2494 #define CAN_FS1R_FSC24_Pos (24U)
2495 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2496 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2497 #define CAN_FS1R_FSC25_Pos (25U)
2498 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2499 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2500 #define CAN_FS1R_FSC26_Pos (26U)
2501 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2502 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2503 #define CAN_FS1R_FSC27_Pos (27U)
2504 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2505 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2506
2507 /****************** Bit definition for CAN_FFA1R register *******************/
2508 #define CAN_FFA1R_FFA_Pos (0U)
2509 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2510 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2511 #define CAN_FFA1R_FFA0_Pos (0U)
2512 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2513 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2514 #define CAN_FFA1R_FFA1_Pos (1U)
2515 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2516 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2517 #define CAN_FFA1R_FFA2_Pos (2U)
2518 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2519 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2520 #define CAN_FFA1R_FFA3_Pos (3U)
2521 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2522 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2523 #define CAN_FFA1R_FFA4_Pos (4U)
2524 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2525 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2526 #define CAN_FFA1R_FFA5_Pos (5U)
2527 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2528 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2529 #define CAN_FFA1R_FFA6_Pos (6U)
2530 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2531 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2532 #define CAN_FFA1R_FFA7_Pos (7U)
2533 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2534 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2535 #define CAN_FFA1R_FFA8_Pos (8U)
2536 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2537 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2538 #define CAN_FFA1R_FFA9_Pos (9U)
2539 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2540 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2541 #define CAN_FFA1R_FFA10_Pos (10U)
2542 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2543 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2544 #define CAN_FFA1R_FFA11_Pos (11U)
2545 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2546 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2547 #define CAN_FFA1R_FFA12_Pos (12U)
2548 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2549 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2550 #define CAN_FFA1R_FFA13_Pos (13U)
2551 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2552 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2553 #define CAN_FFA1R_FFA14_Pos (14U)
2554 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2555 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2556 #define CAN_FFA1R_FFA15_Pos (15U)
2557 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2558 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2559 #define CAN_FFA1R_FFA16_Pos (16U)
2560 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2561 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2562 #define CAN_FFA1R_FFA17_Pos (17U)
2563 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2564 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2565 #define CAN_FFA1R_FFA18_Pos (18U)
2566 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2567 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2568 #define CAN_FFA1R_FFA19_Pos (19U)
2569 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2570 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2571 #define CAN_FFA1R_FFA20_Pos (20U)
2572 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2573 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2574 #define CAN_FFA1R_FFA21_Pos (21U)
2575 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2576 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2577 #define CAN_FFA1R_FFA22_Pos (22U)
2578 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2579 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2580 #define CAN_FFA1R_FFA23_Pos (23U)
2581 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2582 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2583 #define CAN_FFA1R_FFA24_Pos (24U)
2584 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2585 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2586 #define CAN_FFA1R_FFA25_Pos (25U)
2587 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2588 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2589 #define CAN_FFA1R_FFA26_Pos (26U)
2590 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2591 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2592 #define CAN_FFA1R_FFA27_Pos (27U)
2593 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2594 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2595
2596 /******************* Bit definition for CAN_FA1R register *******************/
2597 #define CAN_FA1R_FACT_Pos (0U)
2598 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2599 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2600 #define CAN_FA1R_FACT0_Pos (0U)
2601 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2602 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2603 #define CAN_FA1R_FACT1_Pos (1U)
2604 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2605 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2606 #define CAN_FA1R_FACT2_Pos (2U)
2607 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2608 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2609 #define CAN_FA1R_FACT3_Pos (3U)
2610 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2611 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2612 #define CAN_FA1R_FACT4_Pos (4U)
2613 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2614 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2615 #define CAN_FA1R_FACT5_Pos (5U)
2616 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2617 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2618 #define CAN_FA1R_FACT6_Pos (6U)
2619 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2620 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2621 #define CAN_FA1R_FACT7_Pos (7U)
2622 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2623 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2624 #define CAN_FA1R_FACT8_Pos (8U)
2625 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2626 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2627 #define CAN_FA1R_FACT9_Pos (9U)
2628 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2629 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2630 #define CAN_FA1R_FACT10_Pos (10U)
2631 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2632 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2633 #define CAN_FA1R_FACT11_Pos (11U)
2634 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2635 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2636 #define CAN_FA1R_FACT12_Pos (12U)
2637 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2638 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2639 #define CAN_FA1R_FACT13_Pos (13U)
2640 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2641 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2642 #define CAN_FA1R_FACT14_Pos (14U)
2643 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2644 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2645 #define CAN_FA1R_FACT15_Pos (15U)
2646 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2647 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2648 #define CAN_FA1R_FACT16_Pos (16U)
2649 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2650 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2651 #define CAN_FA1R_FACT17_Pos (17U)
2652 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2653 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2654 #define CAN_FA1R_FACT18_Pos (18U)
2655 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2656 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2657 #define CAN_FA1R_FACT19_Pos (19U)
2658 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2659 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2660 #define CAN_FA1R_FACT20_Pos (20U)
2661 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2662 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2663 #define CAN_FA1R_FACT21_Pos (21U)
2664 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2665 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2666 #define CAN_FA1R_FACT22_Pos (22U)
2667 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2668 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2669 #define CAN_FA1R_FACT23_Pos (23U)
2670 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2671 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2672 #define CAN_FA1R_FACT24_Pos (24U)
2673 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2674 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2675 #define CAN_FA1R_FACT25_Pos (25U)
2676 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2677 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2678 #define CAN_FA1R_FACT26_Pos (26U)
2679 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2680 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
2681 #define CAN_FA1R_FACT27_Pos (27U)
2682 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
2683 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
2684
2685
2686 /******************* Bit definition for CAN_F0R1 register *******************/
2687 #define CAN_F0R1_FB0_Pos (0U)
2688 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2689 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2690 #define CAN_F0R1_FB1_Pos (1U)
2691 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2692 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2693 #define CAN_F0R1_FB2_Pos (2U)
2694 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2695 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2696 #define CAN_F0R1_FB3_Pos (3U)
2697 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2698 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2699 #define CAN_F0R1_FB4_Pos (4U)
2700 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2701 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2702 #define CAN_F0R1_FB5_Pos (5U)
2703 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2704 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2705 #define CAN_F0R1_FB6_Pos (6U)
2706 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2707 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2708 #define CAN_F0R1_FB7_Pos (7U)
2709 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2710 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2711 #define CAN_F0R1_FB8_Pos (8U)
2712 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2713 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2714 #define CAN_F0R1_FB9_Pos (9U)
2715 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2716 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2717 #define CAN_F0R1_FB10_Pos (10U)
2718 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2719 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2720 #define CAN_F0R1_FB11_Pos (11U)
2721 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2722 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2723 #define CAN_F0R1_FB12_Pos (12U)
2724 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2725 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2726 #define CAN_F0R1_FB13_Pos (13U)
2727 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2728 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2729 #define CAN_F0R1_FB14_Pos (14U)
2730 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2731 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2732 #define CAN_F0R1_FB15_Pos (15U)
2733 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2734 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2735 #define CAN_F0R1_FB16_Pos (16U)
2736 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2737 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2738 #define CAN_F0R1_FB17_Pos (17U)
2739 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2740 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2741 #define CAN_F0R1_FB18_Pos (18U)
2742 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2743 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2744 #define CAN_F0R1_FB19_Pos (19U)
2745 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2746 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2747 #define CAN_F0R1_FB20_Pos (20U)
2748 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2749 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2750 #define CAN_F0R1_FB21_Pos (21U)
2751 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2752 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2753 #define CAN_F0R1_FB22_Pos (22U)
2754 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2755 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2756 #define CAN_F0R1_FB23_Pos (23U)
2757 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2758 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
2759 #define CAN_F0R1_FB24_Pos (24U)
2760 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
2761 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
2762 #define CAN_F0R1_FB25_Pos (25U)
2763 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
2764 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
2765 #define CAN_F0R1_FB26_Pos (26U)
2766 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
2767 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
2768 #define CAN_F0R1_FB27_Pos (27U)
2769 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
2770 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
2771 #define CAN_F0R1_FB28_Pos (28U)
2772 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
2773 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
2774 #define CAN_F0R1_FB29_Pos (29U)
2775 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
2776 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
2777 #define CAN_F0R1_FB30_Pos (30U)
2778 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
2779 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
2780 #define CAN_F0R1_FB31_Pos (31U)
2781 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
2782 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
2783
2784 /******************* Bit definition for CAN_F1R1 register *******************/
2785 #define CAN_F1R1_FB0_Pos (0U)
2786 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
2787 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
2788 #define CAN_F1R1_FB1_Pos (1U)
2789 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
2790 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
2791 #define CAN_F1R1_FB2_Pos (2U)
2792 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
2793 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
2794 #define CAN_F1R1_FB3_Pos (3U)
2795 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
2796 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
2797 #define CAN_F1R1_FB4_Pos (4U)
2798 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
2799 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
2800 #define CAN_F1R1_FB5_Pos (5U)
2801 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
2802 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
2803 #define CAN_F1R1_FB6_Pos (6U)
2804 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
2805 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
2806 #define CAN_F1R1_FB7_Pos (7U)
2807 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
2808 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
2809 #define CAN_F1R1_FB8_Pos (8U)
2810 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
2811 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
2812 #define CAN_F1R1_FB9_Pos (9U)
2813 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
2814 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
2815 #define CAN_F1R1_FB10_Pos (10U)
2816 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
2817 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
2818 #define CAN_F1R1_FB11_Pos (11U)
2819 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
2820 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
2821 #define CAN_F1R1_FB12_Pos (12U)
2822 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
2823 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
2824 #define CAN_F1R1_FB13_Pos (13U)
2825 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
2826 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
2827 #define CAN_F1R1_FB14_Pos (14U)
2828 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
2829 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
2830 #define CAN_F1R1_FB15_Pos (15U)
2831 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
2832 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
2833 #define CAN_F1R1_FB16_Pos (16U)
2834 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
2835 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
2836 #define CAN_F1R1_FB17_Pos (17U)
2837 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
2838 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
2839 #define CAN_F1R1_FB18_Pos (18U)
2840 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
2841 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
2842 #define CAN_F1R1_FB19_Pos (19U)
2843 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
2844 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
2845 #define CAN_F1R1_FB20_Pos (20U)
2846 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
2847 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
2848 #define CAN_F1R1_FB21_Pos (21U)
2849 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
2850 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
2851 #define CAN_F1R1_FB22_Pos (22U)
2852 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
2853 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
2854 #define CAN_F1R1_FB23_Pos (23U)
2855 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
2856 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
2857 #define CAN_F1R1_FB24_Pos (24U)
2858 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
2859 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
2860 #define CAN_F1R1_FB25_Pos (25U)
2861 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
2862 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
2863 #define CAN_F1R1_FB26_Pos (26U)
2864 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
2865 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
2866 #define CAN_F1R1_FB27_Pos (27U)
2867 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
2868 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
2869 #define CAN_F1R1_FB28_Pos (28U)
2870 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
2871 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
2872 #define CAN_F1R1_FB29_Pos (29U)
2873 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
2874 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
2875 #define CAN_F1R1_FB30_Pos (30U)
2876 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
2877 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
2878 #define CAN_F1R1_FB31_Pos (31U)
2879 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
2880 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
2881
2882 /******************* Bit definition for CAN_F2R1 register *******************/
2883 #define CAN_F2R1_FB0_Pos (0U)
2884 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
2885 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
2886 #define CAN_F2R1_FB1_Pos (1U)
2887 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
2888 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
2889 #define CAN_F2R1_FB2_Pos (2U)
2890 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
2891 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
2892 #define CAN_F2R1_FB3_Pos (3U)
2893 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
2894 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
2895 #define CAN_F2R1_FB4_Pos (4U)
2896 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
2897 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
2898 #define CAN_F2R1_FB5_Pos (5U)
2899 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
2900 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
2901 #define CAN_F2R1_FB6_Pos (6U)
2902 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
2903 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
2904 #define CAN_F2R1_FB7_Pos (7U)
2905 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
2906 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
2907 #define CAN_F2R1_FB8_Pos (8U)
2908 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
2909 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
2910 #define CAN_F2R1_FB9_Pos (9U)
2911 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
2912 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
2913 #define CAN_F2R1_FB10_Pos (10U)
2914 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
2915 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
2916 #define CAN_F2R1_FB11_Pos (11U)
2917 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
2918 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
2919 #define CAN_F2R1_FB12_Pos (12U)
2920 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
2921 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
2922 #define CAN_F2R1_FB13_Pos (13U)
2923 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
2924 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
2925 #define CAN_F2R1_FB14_Pos (14U)
2926 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
2927 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
2928 #define CAN_F2R1_FB15_Pos (15U)
2929 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
2930 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
2931 #define CAN_F2R1_FB16_Pos (16U)
2932 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
2933 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
2934 #define CAN_F2R1_FB17_Pos (17U)
2935 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
2936 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
2937 #define CAN_F2R1_FB18_Pos (18U)
2938 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
2939 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
2940 #define CAN_F2R1_FB19_Pos (19U)
2941 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
2942 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
2943 #define CAN_F2R1_FB20_Pos (20U)
2944 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
2945 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
2946 #define CAN_F2R1_FB21_Pos (21U)
2947 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
2948 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
2949 #define CAN_F2R1_FB22_Pos (22U)
2950 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
2951 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
2952 #define CAN_F2R1_FB23_Pos (23U)
2953 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
2954 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
2955 #define CAN_F2R1_FB24_Pos (24U)
2956 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
2957 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
2958 #define CAN_F2R1_FB25_Pos (25U)
2959 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
2960 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
2961 #define CAN_F2R1_FB26_Pos (26U)
2962 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
2963 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
2964 #define CAN_F2R1_FB27_Pos (27U)
2965 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
2966 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
2967 #define CAN_F2R1_FB28_Pos (28U)
2968 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
2969 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
2970 #define CAN_F2R1_FB29_Pos (29U)
2971 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
2972 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
2973 #define CAN_F2R1_FB30_Pos (30U)
2974 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
2975 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
2976 #define CAN_F2R1_FB31_Pos (31U)
2977 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
2978 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
2979
2980 /******************* Bit definition for CAN_F3R1 register *******************/
2981 #define CAN_F3R1_FB0_Pos (0U)
2982 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
2983 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
2984 #define CAN_F3R1_FB1_Pos (1U)
2985 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
2986 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
2987 #define CAN_F3R1_FB2_Pos (2U)
2988 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
2989 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
2990 #define CAN_F3R1_FB3_Pos (3U)
2991 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
2992 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
2993 #define CAN_F3R1_FB4_Pos (4U)
2994 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
2995 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
2996 #define CAN_F3R1_FB5_Pos (5U)
2997 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
2998 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
2999 #define CAN_F3R1_FB6_Pos (6U)
3000 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3001 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3002 #define CAN_F3R1_FB7_Pos (7U)
3003 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3004 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3005 #define CAN_F3R1_FB8_Pos (8U)
3006 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3007 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3008 #define CAN_F3R1_FB9_Pos (9U)
3009 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3010 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3011 #define CAN_F3R1_FB10_Pos (10U)
3012 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3013 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3014 #define CAN_F3R1_FB11_Pos (11U)
3015 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3016 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3017 #define CAN_F3R1_FB12_Pos (12U)
3018 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3019 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3020 #define CAN_F3R1_FB13_Pos (13U)
3021 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3022 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3023 #define CAN_F3R1_FB14_Pos (14U)
3024 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3025 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3026 #define CAN_F3R1_FB15_Pos (15U)
3027 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3028 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3029 #define CAN_F3R1_FB16_Pos (16U)
3030 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3031 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3032 #define CAN_F3R1_FB17_Pos (17U)
3033 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3034 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3035 #define CAN_F3R1_FB18_Pos (18U)
3036 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3037 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3038 #define CAN_F3R1_FB19_Pos (19U)
3039 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3040 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3041 #define CAN_F3R1_FB20_Pos (20U)
3042 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3043 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3044 #define CAN_F3R1_FB21_Pos (21U)
3045 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3046 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3047 #define CAN_F3R1_FB22_Pos (22U)
3048 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3049 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3050 #define CAN_F3R1_FB23_Pos (23U)
3051 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3052 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3053 #define CAN_F3R1_FB24_Pos (24U)
3054 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3055 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3056 #define CAN_F3R1_FB25_Pos (25U)
3057 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3058 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3059 #define CAN_F3R1_FB26_Pos (26U)
3060 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3061 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3062 #define CAN_F3R1_FB27_Pos (27U)
3063 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3064 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3065 #define CAN_F3R1_FB28_Pos (28U)
3066 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3067 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3068 #define CAN_F3R1_FB29_Pos (29U)
3069 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3070 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3071 #define CAN_F3R1_FB30_Pos (30U)
3072 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3073 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3074 #define CAN_F3R1_FB31_Pos (31U)
3075 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3076 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3077
3078 /******************* Bit definition for CAN_F4R1 register *******************/
3079 #define CAN_F4R1_FB0_Pos (0U)
3080 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3081 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3082 #define CAN_F4R1_FB1_Pos (1U)
3083 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3084 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3085 #define CAN_F4R1_FB2_Pos (2U)
3086 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3087 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3088 #define CAN_F4R1_FB3_Pos (3U)
3089 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3090 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3091 #define CAN_F4R1_FB4_Pos (4U)
3092 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3093 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3094 #define CAN_F4R1_FB5_Pos (5U)
3095 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3096 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3097 #define CAN_F4R1_FB6_Pos (6U)
3098 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3099 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3100 #define CAN_F4R1_FB7_Pos (7U)
3101 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3102 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3103 #define CAN_F4R1_FB8_Pos (8U)
3104 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3105 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3106 #define CAN_F4R1_FB9_Pos (9U)
3107 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3108 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3109 #define CAN_F4R1_FB10_Pos (10U)
3110 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3111 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3112 #define CAN_F4R1_FB11_Pos (11U)
3113 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3114 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3115 #define CAN_F4R1_FB12_Pos (12U)
3116 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3117 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3118 #define CAN_F4R1_FB13_Pos (13U)
3119 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3120 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3121 #define CAN_F4R1_FB14_Pos (14U)
3122 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3123 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3124 #define CAN_F4R1_FB15_Pos (15U)
3125 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3126 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3127 #define CAN_F4R1_FB16_Pos (16U)
3128 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3129 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3130 #define CAN_F4R1_FB17_Pos (17U)
3131 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3132 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3133 #define CAN_F4R1_FB18_Pos (18U)
3134 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3135 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3136 #define CAN_F4R1_FB19_Pos (19U)
3137 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3138 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3139 #define CAN_F4R1_FB20_Pos (20U)
3140 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3141 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3142 #define CAN_F4R1_FB21_Pos (21U)
3143 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3144 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3145 #define CAN_F4R1_FB22_Pos (22U)
3146 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3147 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3148 #define CAN_F4R1_FB23_Pos (23U)
3149 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3150 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3151 #define CAN_F4R1_FB24_Pos (24U)
3152 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3153 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3154 #define CAN_F4R1_FB25_Pos (25U)
3155 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3156 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3157 #define CAN_F4R1_FB26_Pos (26U)
3158 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3159 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3160 #define CAN_F4R1_FB27_Pos (27U)
3161 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3162 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3163 #define CAN_F4R1_FB28_Pos (28U)
3164 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3165 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3166 #define CAN_F4R1_FB29_Pos (29U)
3167 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3168 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3169 #define CAN_F4R1_FB30_Pos (30U)
3170 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3171 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3172 #define CAN_F4R1_FB31_Pos (31U)
3173 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3174 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3175
3176 /******************* Bit definition for CAN_F5R1 register *******************/
3177 #define CAN_F5R1_FB0_Pos (0U)
3178 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3179 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3180 #define CAN_F5R1_FB1_Pos (1U)
3181 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3182 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3183 #define CAN_F5R1_FB2_Pos (2U)
3184 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3185 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3186 #define CAN_F5R1_FB3_Pos (3U)
3187 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3188 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3189 #define CAN_F5R1_FB4_Pos (4U)
3190 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3191 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3192 #define CAN_F5R1_FB5_Pos (5U)
3193 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3194 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3195 #define CAN_F5R1_FB6_Pos (6U)
3196 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3197 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3198 #define CAN_F5R1_FB7_Pos (7U)
3199 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3200 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3201 #define CAN_F5R1_FB8_Pos (8U)
3202 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3203 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3204 #define CAN_F5R1_FB9_Pos (9U)
3205 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3206 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3207 #define CAN_F5R1_FB10_Pos (10U)
3208 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3209 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3210 #define CAN_F5R1_FB11_Pos (11U)
3211 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3212 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3213 #define CAN_F5R1_FB12_Pos (12U)
3214 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3215 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3216 #define CAN_F5R1_FB13_Pos (13U)
3217 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3218 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3219 #define CAN_F5R1_FB14_Pos (14U)
3220 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3221 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3222 #define CAN_F5R1_FB15_Pos (15U)
3223 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3224 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3225 #define CAN_F5R1_FB16_Pos (16U)
3226 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3227 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3228 #define CAN_F5R1_FB17_Pos (17U)
3229 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3230 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3231 #define CAN_F5R1_FB18_Pos (18U)
3232 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3233 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3234 #define CAN_F5R1_FB19_Pos (19U)
3235 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3236 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3237 #define CAN_F5R1_FB20_Pos (20U)
3238 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3239 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3240 #define CAN_F5R1_FB21_Pos (21U)
3241 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3242 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3243 #define CAN_F5R1_FB22_Pos (22U)
3244 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3245 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3246 #define CAN_F5R1_FB23_Pos (23U)
3247 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3248 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3249 #define CAN_F5R1_FB24_Pos (24U)
3250 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3251 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3252 #define CAN_F5R1_FB25_Pos (25U)
3253 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3254 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3255 #define CAN_F5R1_FB26_Pos (26U)
3256 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3257 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3258 #define CAN_F5R1_FB27_Pos (27U)
3259 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3260 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3261 #define CAN_F5R1_FB28_Pos (28U)
3262 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3263 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3264 #define CAN_F5R1_FB29_Pos (29U)
3265 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3266 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3267 #define CAN_F5R1_FB30_Pos (30U)
3268 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3269 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3270 #define CAN_F5R1_FB31_Pos (31U)
3271 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3272 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3273
3274 /******************* Bit definition for CAN_F6R1 register *******************/
3275 #define CAN_F6R1_FB0_Pos (0U)
3276 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3277 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3278 #define CAN_F6R1_FB1_Pos (1U)
3279 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3280 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3281 #define CAN_F6R1_FB2_Pos (2U)
3282 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3283 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3284 #define CAN_F6R1_FB3_Pos (3U)
3285 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3286 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3287 #define CAN_F6R1_FB4_Pos (4U)
3288 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3289 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3290 #define CAN_F6R1_FB5_Pos (5U)
3291 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3292 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3293 #define CAN_F6R1_FB6_Pos (6U)
3294 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3295 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3296 #define CAN_F6R1_FB7_Pos (7U)
3297 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3298 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3299 #define CAN_F6R1_FB8_Pos (8U)
3300 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3301 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3302 #define CAN_F6R1_FB9_Pos (9U)
3303 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3304 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3305 #define CAN_F6R1_FB10_Pos (10U)
3306 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3307 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3308 #define CAN_F6R1_FB11_Pos (11U)
3309 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3310 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3311 #define CAN_F6R1_FB12_Pos (12U)
3312 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3313 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3314 #define CAN_F6R1_FB13_Pos (13U)
3315 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3316 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3317 #define CAN_F6R1_FB14_Pos (14U)
3318 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3319 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3320 #define CAN_F6R1_FB15_Pos (15U)
3321 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3322 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3323 #define CAN_F6R1_FB16_Pos (16U)
3324 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3325 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3326 #define CAN_F6R1_FB17_Pos (17U)
3327 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3328 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3329 #define CAN_F6R1_FB18_Pos (18U)
3330 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3331 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3332 #define CAN_F6R1_FB19_Pos (19U)
3333 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3334 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3335 #define CAN_F6R1_FB20_Pos (20U)
3336 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3337 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3338 #define CAN_F6R1_FB21_Pos (21U)
3339 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3340 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3341 #define CAN_F6R1_FB22_Pos (22U)
3342 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3343 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3344 #define CAN_F6R1_FB23_Pos (23U)
3345 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3346 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3347 #define CAN_F6R1_FB24_Pos (24U)
3348 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3349 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3350 #define CAN_F6R1_FB25_Pos (25U)
3351 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3352 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3353 #define CAN_F6R1_FB26_Pos (26U)
3354 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3355 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3356 #define CAN_F6R1_FB27_Pos (27U)
3357 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3358 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3359 #define CAN_F6R1_FB28_Pos (28U)
3360 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3361 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3362 #define CAN_F6R1_FB29_Pos (29U)
3363 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3364 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3365 #define CAN_F6R1_FB30_Pos (30U)
3366 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3367 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3368 #define CAN_F6R1_FB31_Pos (31U)
3369 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3370 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3371
3372 /******************* Bit definition for CAN_F7R1 register *******************/
3373 #define CAN_F7R1_FB0_Pos (0U)
3374 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3375 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3376 #define CAN_F7R1_FB1_Pos (1U)
3377 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3378 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3379 #define CAN_F7R1_FB2_Pos (2U)
3380 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3381 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3382 #define CAN_F7R1_FB3_Pos (3U)
3383 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3384 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3385 #define CAN_F7R1_FB4_Pos (4U)
3386 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3387 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3388 #define CAN_F7R1_FB5_Pos (5U)
3389 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3390 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3391 #define CAN_F7R1_FB6_Pos (6U)
3392 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3393 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3394 #define CAN_F7R1_FB7_Pos (7U)
3395 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3396 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3397 #define CAN_F7R1_FB8_Pos (8U)
3398 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3399 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3400 #define CAN_F7R1_FB9_Pos (9U)
3401 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3402 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3403 #define CAN_F7R1_FB10_Pos (10U)
3404 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3405 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3406 #define CAN_F7R1_FB11_Pos (11U)
3407 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3408 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3409 #define CAN_F7R1_FB12_Pos (12U)
3410 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3411 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3412 #define CAN_F7R1_FB13_Pos (13U)
3413 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3414 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3415 #define CAN_F7R1_FB14_Pos (14U)
3416 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3417 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3418 #define CAN_F7R1_FB15_Pos (15U)
3419 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3420 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3421 #define CAN_F7R1_FB16_Pos (16U)
3422 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3423 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3424 #define CAN_F7R1_FB17_Pos (17U)
3425 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3426 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3427 #define CAN_F7R1_FB18_Pos (18U)
3428 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3429 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3430 #define CAN_F7R1_FB19_Pos (19U)
3431 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3432 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3433 #define CAN_F7R1_FB20_Pos (20U)
3434 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3435 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3436 #define CAN_F7R1_FB21_Pos (21U)
3437 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3438 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3439 #define CAN_F7R1_FB22_Pos (22U)
3440 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3441 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3442 #define CAN_F7R1_FB23_Pos (23U)
3443 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3444 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3445 #define CAN_F7R1_FB24_Pos (24U)
3446 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3447 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3448 #define CAN_F7R1_FB25_Pos (25U)
3449 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3450 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3451 #define CAN_F7R1_FB26_Pos (26U)
3452 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3453 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3454 #define CAN_F7R1_FB27_Pos (27U)
3455 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3456 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3457 #define CAN_F7R1_FB28_Pos (28U)
3458 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3459 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3460 #define CAN_F7R1_FB29_Pos (29U)
3461 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3462 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3463 #define CAN_F7R1_FB30_Pos (30U)
3464 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3465 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3466 #define CAN_F7R1_FB31_Pos (31U)
3467 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3468 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3469
3470 /******************* Bit definition for CAN_F8R1 register *******************/
3471 #define CAN_F8R1_FB0_Pos (0U)
3472 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3473 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3474 #define CAN_F8R1_FB1_Pos (1U)
3475 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3476 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3477 #define CAN_F8R1_FB2_Pos (2U)
3478 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3479 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3480 #define CAN_F8R1_FB3_Pos (3U)
3481 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3482 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3483 #define CAN_F8R1_FB4_Pos (4U)
3484 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3485 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3486 #define CAN_F8R1_FB5_Pos (5U)
3487 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3488 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3489 #define CAN_F8R1_FB6_Pos (6U)
3490 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3491 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3492 #define CAN_F8R1_FB7_Pos (7U)
3493 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3494 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3495 #define CAN_F8R1_FB8_Pos (8U)
3496 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3497 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3498 #define CAN_F8R1_FB9_Pos (9U)
3499 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3500 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3501 #define CAN_F8R1_FB10_Pos (10U)
3502 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3503 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3504 #define CAN_F8R1_FB11_Pos (11U)
3505 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3506 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3507 #define CAN_F8R1_FB12_Pos (12U)
3508 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3509 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3510 #define CAN_F8R1_FB13_Pos (13U)
3511 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3512 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3513 #define CAN_F8R1_FB14_Pos (14U)
3514 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3515 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3516 #define CAN_F8R1_FB15_Pos (15U)
3517 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3518 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3519 #define CAN_F8R1_FB16_Pos (16U)
3520 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3521 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3522 #define CAN_F8R1_FB17_Pos (17U)
3523 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3524 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3525 #define CAN_F8R1_FB18_Pos (18U)
3526 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3527 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3528 #define CAN_F8R1_FB19_Pos (19U)
3529 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3530 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3531 #define CAN_F8R1_FB20_Pos (20U)
3532 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3533 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3534 #define CAN_F8R1_FB21_Pos (21U)
3535 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3536 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3537 #define CAN_F8R1_FB22_Pos (22U)
3538 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3539 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3540 #define CAN_F8R1_FB23_Pos (23U)
3541 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3542 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3543 #define CAN_F8R1_FB24_Pos (24U)
3544 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3545 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3546 #define CAN_F8R1_FB25_Pos (25U)
3547 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3548 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3549 #define CAN_F8R1_FB26_Pos (26U)
3550 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3551 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3552 #define CAN_F8R1_FB27_Pos (27U)
3553 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3554 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3555 #define CAN_F8R1_FB28_Pos (28U)
3556 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3557 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3558 #define CAN_F8R1_FB29_Pos (29U)
3559 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3560 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3561 #define CAN_F8R1_FB30_Pos (30U)
3562 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3563 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3564 #define CAN_F8R1_FB31_Pos (31U)
3565 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3566 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3567
3568 /******************* Bit definition for CAN_F9R1 register *******************/
3569 #define CAN_F9R1_FB0_Pos (0U)
3570 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3571 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3572 #define CAN_F9R1_FB1_Pos (1U)
3573 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3574 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3575 #define CAN_F9R1_FB2_Pos (2U)
3576 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3577 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3578 #define CAN_F9R1_FB3_Pos (3U)
3579 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3580 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3581 #define CAN_F9R1_FB4_Pos (4U)
3582 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3583 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3584 #define CAN_F9R1_FB5_Pos (5U)
3585 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3586 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3587 #define CAN_F9R1_FB6_Pos (6U)
3588 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3589 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3590 #define CAN_F9R1_FB7_Pos (7U)
3591 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3592 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3593 #define CAN_F9R1_FB8_Pos (8U)
3594 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3595 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3596 #define CAN_F9R1_FB9_Pos (9U)
3597 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3598 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3599 #define CAN_F9R1_FB10_Pos (10U)
3600 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3601 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3602 #define CAN_F9R1_FB11_Pos (11U)
3603 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3604 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3605 #define CAN_F9R1_FB12_Pos (12U)
3606 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3607 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3608 #define CAN_F9R1_FB13_Pos (13U)
3609 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3610 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3611 #define CAN_F9R1_FB14_Pos (14U)
3612 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3613 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3614 #define CAN_F9R1_FB15_Pos (15U)
3615 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3616 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3617 #define CAN_F9R1_FB16_Pos (16U)
3618 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3619 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3620 #define CAN_F9R1_FB17_Pos (17U)
3621 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3622 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3623 #define CAN_F9R1_FB18_Pos (18U)
3624 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3625 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3626 #define CAN_F9R1_FB19_Pos (19U)
3627 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3628 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3629 #define CAN_F9R1_FB20_Pos (20U)
3630 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3631 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3632 #define CAN_F9R1_FB21_Pos (21U)
3633 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3634 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3635 #define CAN_F9R1_FB22_Pos (22U)
3636 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3637 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3638 #define CAN_F9R1_FB23_Pos (23U)
3639 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3640 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3641 #define CAN_F9R1_FB24_Pos (24U)
3642 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3643 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3644 #define CAN_F9R1_FB25_Pos (25U)
3645 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3646 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3647 #define CAN_F9R1_FB26_Pos (26U)
3648 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3649 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3650 #define CAN_F9R1_FB27_Pos (27U)
3651 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3652 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3653 #define CAN_F9R1_FB28_Pos (28U)
3654 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3655 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3656 #define CAN_F9R1_FB29_Pos (29U)
3657 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3658 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3659 #define CAN_F9R1_FB30_Pos (30U)
3660 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3661 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3662 #define CAN_F9R1_FB31_Pos (31U)
3663 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3664 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3665
3666 /******************* Bit definition for CAN_F10R1 register ******************/
3667 #define CAN_F10R1_FB0_Pos (0U)
3668 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3669 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3670 #define CAN_F10R1_FB1_Pos (1U)
3671 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3672 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3673 #define CAN_F10R1_FB2_Pos (2U)
3674 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3675 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3676 #define CAN_F10R1_FB3_Pos (3U)
3677 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3678 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3679 #define CAN_F10R1_FB4_Pos (4U)
3680 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3681 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3682 #define CAN_F10R1_FB5_Pos (5U)
3683 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3684 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3685 #define CAN_F10R1_FB6_Pos (6U)
3686 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3687 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3688 #define CAN_F10R1_FB7_Pos (7U)
3689 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3690 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3691 #define CAN_F10R1_FB8_Pos (8U)
3692 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3693 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3694 #define CAN_F10R1_FB9_Pos (9U)
3695 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3696 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3697 #define CAN_F10R1_FB10_Pos (10U)
3698 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3699 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3700 #define CAN_F10R1_FB11_Pos (11U)
3701 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3702 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3703 #define CAN_F10R1_FB12_Pos (12U)
3704 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3705 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3706 #define CAN_F10R1_FB13_Pos (13U)
3707 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3708 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3709 #define CAN_F10R1_FB14_Pos (14U)
3710 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3711 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3712 #define CAN_F10R1_FB15_Pos (15U)
3713 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3714 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3715 #define CAN_F10R1_FB16_Pos (16U)
3716 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3717 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3718 #define CAN_F10R1_FB17_Pos (17U)
3719 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3720 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3721 #define CAN_F10R1_FB18_Pos (18U)
3722 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3723 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3724 #define CAN_F10R1_FB19_Pos (19U)
3725 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3726 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3727 #define CAN_F10R1_FB20_Pos (20U)
3728 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3729 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3730 #define CAN_F10R1_FB21_Pos (21U)
3731 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3732 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
3733 #define CAN_F10R1_FB22_Pos (22U)
3734 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
3735 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
3736 #define CAN_F10R1_FB23_Pos (23U)
3737 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
3738 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
3739 #define CAN_F10R1_FB24_Pos (24U)
3740 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
3741 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
3742 #define CAN_F10R1_FB25_Pos (25U)
3743 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
3744 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
3745 #define CAN_F10R1_FB26_Pos (26U)
3746 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
3747 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
3748 #define CAN_F10R1_FB27_Pos (27U)
3749 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
3750 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
3751 #define CAN_F10R1_FB28_Pos (28U)
3752 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
3753 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
3754 #define CAN_F10R1_FB29_Pos (29U)
3755 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
3756 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
3757 #define CAN_F10R1_FB30_Pos (30U)
3758 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
3759 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
3760 #define CAN_F10R1_FB31_Pos (31U)
3761 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
3762 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
3763
3764 /******************* Bit definition for CAN_F11R1 register ******************/
3765 #define CAN_F11R1_FB0_Pos (0U)
3766 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
3767 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
3768 #define CAN_F11R1_FB1_Pos (1U)
3769 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
3770 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
3771 #define CAN_F11R1_FB2_Pos (2U)
3772 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
3773 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
3774 #define CAN_F11R1_FB3_Pos (3U)
3775 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
3776 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
3777 #define CAN_F11R1_FB4_Pos (4U)
3778 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
3779 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
3780 #define CAN_F11R1_FB5_Pos (5U)
3781 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
3782 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
3783 #define CAN_F11R1_FB6_Pos (6U)
3784 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
3785 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
3786 #define CAN_F11R1_FB7_Pos (7U)
3787 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
3788 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
3789 #define CAN_F11R1_FB8_Pos (8U)
3790 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
3791 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
3792 #define CAN_F11R1_FB9_Pos (9U)
3793 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
3794 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
3795 #define CAN_F11R1_FB10_Pos (10U)
3796 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
3797 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
3798 #define CAN_F11R1_FB11_Pos (11U)
3799 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
3800 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
3801 #define CAN_F11R1_FB12_Pos (12U)
3802 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
3803 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
3804 #define CAN_F11R1_FB13_Pos (13U)
3805 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
3806 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
3807 #define CAN_F11R1_FB14_Pos (14U)
3808 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
3809 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
3810 #define CAN_F11R1_FB15_Pos (15U)
3811 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
3812 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
3813 #define CAN_F11R1_FB16_Pos (16U)
3814 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
3815 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
3816 #define CAN_F11R1_FB17_Pos (17U)
3817 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
3818 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
3819 #define CAN_F11R1_FB18_Pos (18U)
3820 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
3821 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
3822 #define CAN_F11R1_FB19_Pos (19U)
3823 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
3824 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
3825 #define CAN_F11R1_FB20_Pos (20U)
3826 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
3827 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
3828 #define CAN_F11R1_FB21_Pos (21U)
3829 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
3830 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
3831 #define CAN_F11R1_FB22_Pos (22U)
3832 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
3833 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
3834 #define CAN_F11R1_FB23_Pos (23U)
3835 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
3836 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
3837 #define CAN_F11R1_FB24_Pos (24U)
3838 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
3839 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
3840 #define CAN_F11R1_FB25_Pos (25U)
3841 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
3842 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
3843 #define CAN_F11R1_FB26_Pos (26U)
3844 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
3845 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
3846 #define CAN_F11R1_FB27_Pos (27U)
3847 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
3848 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
3849 #define CAN_F11R1_FB28_Pos (28U)
3850 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
3851 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
3852 #define CAN_F11R1_FB29_Pos (29U)
3853 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
3854 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
3855 #define CAN_F11R1_FB30_Pos (30U)
3856 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
3857 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
3858 #define CAN_F11R1_FB31_Pos (31U)
3859 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
3860 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
3861
3862 /******************* Bit definition for CAN_F12R1 register ******************/
3863 #define CAN_F12R1_FB0_Pos (0U)
3864 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
3865 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
3866 #define CAN_F12R1_FB1_Pos (1U)
3867 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
3868 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
3869 #define CAN_F12R1_FB2_Pos (2U)
3870 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
3871 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
3872 #define CAN_F12R1_FB3_Pos (3U)
3873 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
3874 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
3875 #define CAN_F12R1_FB4_Pos (4U)
3876 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
3877 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
3878 #define CAN_F12R1_FB5_Pos (5U)
3879 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
3880 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
3881 #define CAN_F12R1_FB6_Pos (6U)
3882 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
3883 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
3884 #define CAN_F12R1_FB7_Pos (7U)
3885 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
3886 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
3887 #define CAN_F12R1_FB8_Pos (8U)
3888 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
3889 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
3890 #define CAN_F12R1_FB9_Pos (9U)
3891 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
3892 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
3893 #define CAN_F12R1_FB10_Pos (10U)
3894 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
3895 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
3896 #define CAN_F12R1_FB11_Pos (11U)
3897 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
3898 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
3899 #define CAN_F12R1_FB12_Pos (12U)
3900 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
3901 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
3902 #define CAN_F12R1_FB13_Pos (13U)
3903 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
3904 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
3905 #define CAN_F12R1_FB14_Pos (14U)
3906 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
3907 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
3908 #define CAN_F12R1_FB15_Pos (15U)
3909 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
3910 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
3911 #define CAN_F12R1_FB16_Pos (16U)
3912 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
3913 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
3914 #define CAN_F12R1_FB17_Pos (17U)
3915 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
3916 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
3917 #define CAN_F12R1_FB18_Pos (18U)
3918 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
3919 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
3920 #define CAN_F12R1_FB19_Pos (19U)
3921 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
3922 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
3923 #define CAN_F12R1_FB20_Pos (20U)
3924 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
3925 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
3926 #define CAN_F12R1_FB21_Pos (21U)
3927 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
3928 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
3929 #define CAN_F12R1_FB22_Pos (22U)
3930 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
3931 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
3932 #define CAN_F12R1_FB23_Pos (23U)
3933 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
3934 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
3935 #define CAN_F12R1_FB24_Pos (24U)
3936 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
3937 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
3938 #define CAN_F12R1_FB25_Pos (25U)
3939 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
3940 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
3941 #define CAN_F12R1_FB26_Pos (26U)
3942 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
3943 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
3944 #define CAN_F12R1_FB27_Pos (27U)
3945 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
3946 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
3947 #define CAN_F12R1_FB28_Pos (28U)
3948 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
3949 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
3950 #define CAN_F12R1_FB29_Pos (29U)
3951 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
3952 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
3953 #define CAN_F12R1_FB30_Pos (30U)
3954 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
3955 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
3956 #define CAN_F12R1_FB31_Pos (31U)
3957 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
3958 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
3959
3960 /******************* Bit definition for CAN_F13R1 register ******************/
3961 #define CAN_F13R1_FB0_Pos (0U)
3962 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
3963 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
3964 #define CAN_F13R1_FB1_Pos (1U)
3965 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
3966 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
3967 #define CAN_F13R1_FB2_Pos (2U)
3968 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
3969 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
3970 #define CAN_F13R1_FB3_Pos (3U)
3971 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
3972 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
3973 #define CAN_F13R1_FB4_Pos (4U)
3974 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
3975 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
3976 #define CAN_F13R1_FB5_Pos (5U)
3977 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
3978 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
3979 #define CAN_F13R1_FB6_Pos (6U)
3980 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
3981 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
3982 #define CAN_F13R1_FB7_Pos (7U)
3983 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
3984 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
3985 #define CAN_F13R1_FB8_Pos (8U)
3986 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
3987 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
3988 #define CAN_F13R1_FB9_Pos (9U)
3989 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
3990 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
3991 #define CAN_F13R1_FB10_Pos (10U)
3992 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
3993 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
3994 #define CAN_F13R1_FB11_Pos (11U)
3995 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
3996 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
3997 #define CAN_F13R1_FB12_Pos (12U)
3998 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
3999 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4000 #define CAN_F13R1_FB13_Pos (13U)
4001 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4002 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4003 #define CAN_F13R1_FB14_Pos (14U)
4004 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4005 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4006 #define CAN_F13R1_FB15_Pos (15U)
4007 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4008 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4009 #define CAN_F13R1_FB16_Pos (16U)
4010 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4011 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4012 #define CAN_F13R1_FB17_Pos (17U)
4013 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4014 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4015 #define CAN_F13R1_FB18_Pos (18U)
4016 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4017 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4018 #define CAN_F13R1_FB19_Pos (19U)
4019 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4020 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4021 #define CAN_F13R1_FB20_Pos (20U)
4022 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4023 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4024 #define CAN_F13R1_FB21_Pos (21U)
4025 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4026 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4027 #define CAN_F13R1_FB22_Pos (22U)
4028 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4029 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4030 #define CAN_F13R1_FB23_Pos (23U)
4031 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4032 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4033 #define CAN_F13R1_FB24_Pos (24U)
4034 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4035 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4036 #define CAN_F13R1_FB25_Pos (25U)
4037 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4038 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4039 #define CAN_F13R1_FB26_Pos (26U)
4040 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4041 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4042 #define CAN_F13R1_FB27_Pos (27U)
4043 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4044 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4045 #define CAN_F13R1_FB28_Pos (28U)
4046 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4047 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4048 #define CAN_F13R1_FB29_Pos (29U)
4049 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4050 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4051 #define CAN_F13R1_FB30_Pos (30U)
4052 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4053 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4054 #define CAN_F13R1_FB31_Pos (31U)
4055 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4056 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4057
4058 /******************* Bit definition for CAN_F0R2 register *******************/
4059 #define CAN_F0R2_FB0_Pos (0U)
4060 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4061 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4062 #define CAN_F0R2_FB1_Pos (1U)
4063 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4064 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4065 #define CAN_F0R2_FB2_Pos (2U)
4066 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4067 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4068 #define CAN_F0R2_FB3_Pos (3U)
4069 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4070 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4071 #define CAN_F0R2_FB4_Pos (4U)
4072 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4073 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4074 #define CAN_F0R2_FB5_Pos (5U)
4075 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4076 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4077 #define CAN_F0R2_FB6_Pos (6U)
4078 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4079 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4080 #define CAN_F0R2_FB7_Pos (7U)
4081 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4082 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4083 #define CAN_F0R2_FB8_Pos (8U)
4084 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4085 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4086 #define CAN_F0R2_FB9_Pos (9U)
4087 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4088 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4089 #define CAN_F0R2_FB10_Pos (10U)
4090 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4091 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4092 #define CAN_F0R2_FB11_Pos (11U)
4093 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4094 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4095 #define CAN_F0R2_FB12_Pos (12U)
4096 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4097 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4098 #define CAN_F0R2_FB13_Pos (13U)
4099 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4100 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4101 #define CAN_F0R2_FB14_Pos (14U)
4102 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4103 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4104 #define CAN_F0R2_FB15_Pos (15U)
4105 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4106 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4107 #define CAN_F0R2_FB16_Pos (16U)
4108 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4109 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4110 #define CAN_F0R2_FB17_Pos (17U)
4111 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4112 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4113 #define CAN_F0R2_FB18_Pos (18U)
4114 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4115 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4116 #define CAN_F0R2_FB19_Pos (19U)
4117 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4118 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4119 #define CAN_F0R2_FB20_Pos (20U)
4120 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4121 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4122 #define CAN_F0R2_FB21_Pos (21U)
4123 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4124 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4125 #define CAN_F0R2_FB22_Pos (22U)
4126 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4127 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4128 #define CAN_F0R2_FB23_Pos (23U)
4129 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4130 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4131 #define CAN_F0R2_FB24_Pos (24U)
4132 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4133 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4134 #define CAN_F0R2_FB25_Pos (25U)
4135 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4136 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4137 #define CAN_F0R2_FB26_Pos (26U)
4138 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4139 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4140 #define CAN_F0R2_FB27_Pos (27U)
4141 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4142 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4143 #define CAN_F0R2_FB28_Pos (28U)
4144 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4145 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4146 #define CAN_F0R2_FB29_Pos (29U)
4147 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4148 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4149 #define CAN_F0R2_FB30_Pos (30U)
4150 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4151 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4152 #define CAN_F0R2_FB31_Pos (31U)
4153 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4154 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4155
4156 /******************* Bit definition for CAN_F1R2 register *******************/
4157 #define CAN_F1R2_FB0_Pos (0U)
4158 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4159 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4160 #define CAN_F1R2_FB1_Pos (1U)
4161 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4162 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4163 #define CAN_F1R2_FB2_Pos (2U)
4164 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4165 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4166 #define CAN_F1R2_FB3_Pos (3U)
4167 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4168 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4169 #define CAN_F1R2_FB4_Pos (4U)
4170 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4171 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4172 #define CAN_F1R2_FB5_Pos (5U)
4173 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4174 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4175 #define CAN_F1R2_FB6_Pos (6U)
4176 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4177 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4178 #define CAN_F1R2_FB7_Pos (7U)
4179 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4180 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4181 #define CAN_F1R2_FB8_Pos (8U)
4182 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4183 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4184 #define CAN_F1R2_FB9_Pos (9U)
4185 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4186 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4187 #define CAN_F1R2_FB10_Pos (10U)
4188 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4189 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4190 #define CAN_F1R2_FB11_Pos (11U)
4191 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4192 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4193 #define CAN_F1R2_FB12_Pos (12U)
4194 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4195 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4196 #define CAN_F1R2_FB13_Pos (13U)
4197 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4198 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4199 #define CAN_F1R2_FB14_Pos (14U)
4200 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4201 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4202 #define CAN_F1R2_FB15_Pos (15U)
4203 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4204 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4205 #define CAN_F1R2_FB16_Pos (16U)
4206 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4207 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4208 #define CAN_F1R2_FB17_Pos (17U)
4209 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4210 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4211 #define CAN_F1R2_FB18_Pos (18U)
4212 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4213 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4214 #define CAN_F1R2_FB19_Pos (19U)
4215 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4216 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4217 #define CAN_F1R2_FB20_Pos (20U)
4218 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4219 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4220 #define CAN_F1R2_FB21_Pos (21U)
4221 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4222 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4223 #define CAN_F1R2_FB22_Pos (22U)
4224 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4225 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4226 #define CAN_F1R2_FB23_Pos (23U)
4227 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4228 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4229 #define CAN_F1R2_FB24_Pos (24U)
4230 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4231 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4232 #define CAN_F1R2_FB25_Pos (25U)
4233 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4234 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4235 #define CAN_F1R2_FB26_Pos (26U)
4236 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4237 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4238 #define CAN_F1R2_FB27_Pos (27U)
4239 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4240 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4241 #define CAN_F1R2_FB28_Pos (28U)
4242 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4243 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4244 #define CAN_F1R2_FB29_Pos (29U)
4245 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4246 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4247 #define CAN_F1R2_FB30_Pos (30U)
4248 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4249 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4250 #define CAN_F1R2_FB31_Pos (31U)
4251 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4252 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4253
4254 /******************* Bit definition for CAN_F2R2 register *******************/
4255 #define CAN_F2R2_FB0_Pos (0U)
4256 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4257 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4258 #define CAN_F2R2_FB1_Pos (1U)
4259 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4260 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4261 #define CAN_F2R2_FB2_Pos (2U)
4262 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4263 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4264 #define CAN_F2R2_FB3_Pos (3U)
4265 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4266 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4267 #define CAN_F2R2_FB4_Pos (4U)
4268 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4269 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4270 #define CAN_F2R2_FB5_Pos (5U)
4271 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4272 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4273 #define CAN_F2R2_FB6_Pos (6U)
4274 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4275 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4276 #define CAN_F2R2_FB7_Pos (7U)
4277 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4278 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4279 #define CAN_F2R2_FB8_Pos (8U)
4280 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4281 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4282 #define CAN_F2R2_FB9_Pos (9U)
4283 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4284 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4285 #define CAN_F2R2_FB10_Pos (10U)
4286 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4287 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4288 #define CAN_F2R2_FB11_Pos (11U)
4289 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4290 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4291 #define CAN_F2R2_FB12_Pos (12U)
4292 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4293 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4294 #define CAN_F2R2_FB13_Pos (13U)
4295 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4296 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4297 #define CAN_F2R2_FB14_Pos (14U)
4298 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4299 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4300 #define CAN_F2R2_FB15_Pos (15U)
4301 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4302 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4303 #define CAN_F2R2_FB16_Pos (16U)
4304 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4305 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4306 #define CAN_F2R2_FB17_Pos (17U)
4307 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4308 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4309 #define CAN_F2R2_FB18_Pos (18U)
4310 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4311 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4312 #define CAN_F2R2_FB19_Pos (19U)
4313 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4314 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4315 #define CAN_F2R2_FB20_Pos (20U)
4316 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4317 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4318 #define CAN_F2R2_FB21_Pos (21U)
4319 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4320 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4321 #define CAN_F2R2_FB22_Pos (22U)
4322 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4323 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4324 #define CAN_F2R2_FB23_Pos (23U)
4325 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4326 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4327 #define CAN_F2R2_FB24_Pos (24U)
4328 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4329 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4330 #define CAN_F2R2_FB25_Pos (25U)
4331 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4332 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4333 #define CAN_F2R2_FB26_Pos (26U)
4334 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4335 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4336 #define CAN_F2R2_FB27_Pos (27U)
4337 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4338 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4339 #define CAN_F2R2_FB28_Pos (28U)
4340 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4341 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4342 #define CAN_F2R2_FB29_Pos (29U)
4343 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4344 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4345 #define CAN_F2R2_FB30_Pos (30U)
4346 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4347 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4348 #define CAN_F2R2_FB31_Pos (31U)
4349 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4350 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4351
4352 /******************* Bit definition for CAN_F3R2 register *******************/
4353 #define CAN_F3R2_FB0_Pos (0U)
4354 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4355 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4356 #define CAN_F3R2_FB1_Pos (1U)
4357 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4358 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4359 #define CAN_F3R2_FB2_Pos (2U)
4360 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4361 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4362 #define CAN_F3R2_FB3_Pos (3U)
4363 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4364 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4365 #define CAN_F3R2_FB4_Pos (4U)
4366 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4367 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4368 #define CAN_F3R2_FB5_Pos (5U)
4369 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4370 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4371 #define CAN_F3R2_FB6_Pos (6U)
4372 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4373 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4374 #define CAN_F3R2_FB7_Pos (7U)
4375 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4376 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4377 #define CAN_F3R2_FB8_Pos (8U)
4378 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4379 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4380 #define CAN_F3R2_FB9_Pos (9U)
4381 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4382 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4383 #define CAN_F3R2_FB10_Pos (10U)
4384 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4385 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4386 #define CAN_F3R2_FB11_Pos (11U)
4387 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4388 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4389 #define CAN_F3R2_FB12_Pos (12U)
4390 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4391 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4392 #define CAN_F3R2_FB13_Pos (13U)
4393 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4394 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4395 #define CAN_F3R2_FB14_Pos (14U)
4396 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4397 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4398 #define CAN_F3R2_FB15_Pos (15U)
4399 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4400 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4401 #define CAN_F3R2_FB16_Pos (16U)
4402 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4403 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4404 #define CAN_F3R2_FB17_Pos (17U)
4405 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4406 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4407 #define CAN_F3R2_FB18_Pos (18U)
4408 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4409 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4410 #define CAN_F3R2_FB19_Pos (19U)
4411 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4412 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4413 #define CAN_F3R2_FB20_Pos (20U)
4414 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4415 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4416 #define CAN_F3R2_FB21_Pos (21U)
4417 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4418 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4419 #define CAN_F3R2_FB22_Pos (22U)
4420 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4421 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4422 #define CAN_F3R2_FB23_Pos (23U)
4423 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4424 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4425 #define CAN_F3R2_FB24_Pos (24U)
4426 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4427 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4428 #define CAN_F3R2_FB25_Pos (25U)
4429 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4430 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4431 #define CAN_F3R2_FB26_Pos (26U)
4432 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4433 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4434 #define CAN_F3R2_FB27_Pos (27U)
4435 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4436 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4437 #define CAN_F3R2_FB28_Pos (28U)
4438 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4439 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4440 #define CAN_F3R2_FB29_Pos (29U)
4441 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4442 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4443 #define CAN_F3R2_FB30_Pos (30U)
4444 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4445 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4446 #define CAN_F3R2_FB31_Pos (31U)
4447 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4448 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4449
4450 /******************* Bit definition for CAN_F4R2 register *******************/
4451 #define CAN_F4R2_FB0_Pos (0U)
4452 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4453 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4454 #define CAN_F4R2_FB1_Pos (1U)
4455 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4456 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4457 #define CAN_F4R2_FB2_Pos (2U)
4458 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4459 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4460 #define CAN_F4R2_FB3_Pos (3U)
4461 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4462 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4463 #define CAN_F4R2_FB4_Pos (4U)
4464 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4465 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4466 #define CAN_F4R2_FB5_Pos (5U)
4467 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4468 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4469 #define CAN_F4R2_FB6_Pos (6U)
4470 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4471 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4472 #define CAN_F4R2_FB7_Pos (7U)
4473 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4474 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4475 #define CAN_F4R2_FB8_Pos (8U)
4476 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4477 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4478 #define CAN_F4R2_FB9_Pos (9U)
4479 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4480 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4481 #define CAN_F4R2_FB10_Pos (10U)
4482 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4483 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4484 #define CAN_F4R2_FB11_Pos (11U)
4485 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4486 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4487 #define CAN_F4R2_FB12_Pos (12U)
4488 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4489 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4490 #define CAN_F4R2_FB13_Pos (13U)
4491 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4492 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4493 #define CAN_F4R2_FB14_Pos (14U)
4494 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4495 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4496 #define CAN_F4R2_FB15_Pos (15U)
4497 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4498 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4499 #define CAN_F4R2_FB16_Pos (16U)
4500 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4501 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4502 #define CAN_F4R2_FB17_Pos (17U)
4503 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4504 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4505 #define CAN_F4R2_FB18_Pos (18U)
4506 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4507 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4508 #define CAN_F4R2_FB19_Pos (19U)
4509 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4510 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4511 #define CAN_F4R2_FB20_Pos (20U)
4512 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4513 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4514 #define CAN_F4R2_FB21_Pos (21U)
4515 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4516 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4517 #define CAN_F4R2_FB22_Pos (22U)
4518 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4519 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4520 #define CAN_F4R2_FB23_Pos (23U)
4521 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4522 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4523 #define CAN_F4R2_FB24_Pos (24U)
4524 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4525 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4526 #define CAN_F4R2_FB25_Pos (25U)
4527 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4528 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4529 #define CAN_F4R2_FB26_Pos (26U)
4530 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4531 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4532 #define CAN_F4R2_FB27_Pos (27U)
4533 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4534 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4535 #define CAN_F4R2_FB28_Pos (28U)
4536 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4537 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4538 #define CAN_F4R2_FB29_Pos (29U)
4539 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4540 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4541 #define CAN_F4R2_FB30_Pos (30U)
4542 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4543 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4544 #define CAN_F4R2_FB31_Pos (31U)
4545 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4546 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4547
4548 /******************* Bit definition for CAN_F5R2 register *******************/
4549 #define CAN_F5R2_FB0_Pos (0U)
4550 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4551 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4552 #define CAN_F5R2_FB1_Pos (1U)
4553 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4554 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4555 #define CAN_F5R2_FB2_Pos (2U)
4556 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4557 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4558 #define CAN_F5R2_FB3_Pos (3U)
4559 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4560 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4561 #define CAN_F5R2_FB4_Pos (4U)
4562 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4563 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4564 #define CAN_F5R2_FB5_Pos (5U)
4565 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4566 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4567 #define CAN_F5R2_FB6_Pos (6U)
4568 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4569 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4570 #define CAN_F5R2_FB7_Pos (7U)
4571 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4572 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4573 #define CAN_F5R2_FB8_Pos (8U)
4574 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4575 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4576 #define CAN_F5R2_FB9_Pos (9U)
4577 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4578 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4579 #define CAN_F5R2_FB10_Pos (10U)
4580 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4581 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4582 #define CAN_F5R2_FB11_Pos (11U)
4583 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4584 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4585 #define CAN_F5R2_FB12_Pos (12U)
4586 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4587 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4588 #define CAN_F5R2_FB13_Pos (13U)
4589 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4590 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4591 #define CAN_F5R2_FB14_Pos (14U)
4592 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4593 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4594 #define CAN_F5R2_FB15_Pos (15U)
4595 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4596 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4597 #define CAN_F5R2_FB16_Pos (16U)
4598 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4599 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4600 #define CAN_F5R2_FB17_Pos (17U)
4601 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4602 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4603 #define CAN_F5R2_FB18_Pos (18U)
4604 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4605 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4606 #define CAN_F5R2_FB19_Pos (19U)
4607 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4608 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4609 #define CAN_F5R2_FB20_Pos (20U)
4610 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4611 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4612 #define CAN_F5R2_FB21_Pos (21U)
4613 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4614 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4615 #define CAN_F5R2_FB22_Pos (22U)
4616 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4617 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4618 #define CAN_F5R2_FB23_Pos (23U)
4619 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4620 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4621 #define CAN_F5R2_FB24_Pos (24U)
4622 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4623 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4624 #define CAN_F5R2_FB25_Pos (25U)
4625 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4626 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4627 #define CAN_F5R2_FB26_Pos (26U)
4628 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4629 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4630 #define CAN_F5R2_FB27_Pos (27U)
4631 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4632 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4633 #define CAN_F5R2_FB28_Pos (28U)
4634 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4635 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4636 #define CAN_F5R2_FB29_Pos (29U)
4637 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4638 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4639 #define CAN_F5R2_FB30_Pos (30U)
4640 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4641 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4642 #define CAN_F5R2_FB31_Pos (31U)
4643 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4644 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4645
4646 /******************* Bit definition for CAN_F6R2 register *******************/
4647 #define CAN_F6R2_FB0_Pos (0U)
4648 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4649 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4650 #define CAN_F6R2_FB1_Pos (1U)
4651 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4652 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4653 #define CAN_F6R2_FB2_Pos (2U)
4654 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4655 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4656 #define CAN_F6R2_FB3_Pos (3U)
4657 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4658 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4659 #define CAN_F6R2_FB4_Pos (4U)
4660 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4661 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4662 #define CAN_F6R2_FB5_Pos (5U)
4663 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4664 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4665 #define CAN_F6R2_FB6_Pos (6U)
4666 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4667 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4668 #define CAN_F6R2_FB7_Pos (7U)
4669 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4670 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4671 #define CAN_F6R2_FB8_Pos (8U)
4672 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4673 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4674 #define CAN_F6R2_FB9_Pos (9U)
4675 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4676 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4677 #define CAN_F6R2_FB10_Pos (10U)
4678 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4679 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4680 #define CAN_F6R2_FB11_Pos (11U)
4681 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4682 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4683 #define CAN_F6R2_FB12_Pos (12U)
4684 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4685 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4686 #define CAN_F6R2_FB13_Pos (13U)
4687 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4688 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4689 #define CAN_F6R2_FB14_Pos (14U)
4690 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4691 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4692 #define CAN_F6R2_FB15_Pos (15U)
4693 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4694 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4695 #define CAN_F6R2_FB16_Pos (16U)
4696 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4697 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4698 #define CAN_F6R2_FB17_Pos (17U)
4699 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4700 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4701 #define CAN_F6R2_FB18_Pos (18U)
4702 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4703 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4704 #define CAN_F6R2_FB19_Pos (19U)
4705 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4706 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4707 #define CAN_F6R2_FB20_Pos (20U)
4708 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4709 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4710 #define CAN_F6R2_FB21_Pos (21U)
4711 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4712 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4713 #define CAN_F6R2_FB22_Pos (22U)
4714 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4715 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4716 #define CAN_F6R2_FB23_Pos (23U)
4717 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4718 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4719 #define CAN_F6R2_FB24_Pos (24U)
4720 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4721 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4722 #define CAN_F6R2_FB25_Pos (25U)
4723 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4724 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4725 #define CAN_F6R2_FB26_Pos (26U)
4726 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4727 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4728 #define CAN_F6R2_FB27_Pos (27U)
4729 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4730 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4731 #define CAN_F6R2_FB28_Pos (28U)
4732 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
4733 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
4734 #define CAN_F6R2_FB29_Pos (29U)
4735 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
4736 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
4737 #define CAN_F6R2_FB30_Pos (30U)
4738 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
4739 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
4740 #define CAN_F6R2_FB31_Pos (31U)
4741 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
4742 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
4743
4744 /******************* Bit definition for CAN_F7R2 register *******************/
4745 #define CAN_F7R2_FB0_Pos (0U)
4746 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
4747 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
4748 #define CAN_F7R2_FB1_Pos (1U)
4749 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
4750 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
4751 #define CAN_F7R2_FB2_Pos (2U)
4752 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
4753 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
4754 #define CAN_F7R2_FB3_Pos (3U)
4755 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
4756 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
4757 #define CAN_F7R2_FB4_Pos (4U)
4758 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
4759 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
4760 #define CAN_F7R2_FB5_Pos (5U)
4761 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
4762 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
4763 #define CAN_F7R2_FB6_Pos (6U)
4764 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
4765 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
4766 #define CAN_F7R2_FB7_Pos (7U)
4767 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
4768 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
4769 #define CAN_F7R2_FB8_Pos (8U)
4770 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
4771 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
4772 #define CAN_F7R2_FB9_Pos (9U)
4773 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
4774 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
4775 #define CAN_F7R2_FB10_Pos (10U)
4776 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
4777 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
4778 #define CAN_F7R2_FB11_Pos (11U)
4779 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
4780 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
4781 #define CAN_F7R2_FB12_Pos (12U)
4782 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
4783 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
4784 #define CAN_F7R2_FB13_Pos (13U)
4785 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
4786 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
4787 #define CAN_F7R2_FB14_Pos (14U)
4788 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
4789 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
4790 #define CAN_F7R2_FB15_Pos (15U)
4791 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
4792 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
4793 #define CAN_F7R2_FB16_Pos (16U)
4794 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
4795 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
4796 #define CAN_F7R2_FB17_Pos (17U)
4797 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
4798 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
4799 #define CAN_F7R2_FB18_Pos (18U)
4800 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
4801 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
4802 #define CAN_F7R2_FB19_Pos (19U)
4803 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
4804 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
4805 #define CAN_F7R2_FB20_Pos (20U)
4806 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
4807 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
4808 #define CAN_F7R2_FB21_Pos (21U)
4809 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
4810 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
4811 #define CAN_F7R2_FB22_Pos (22U)
4812 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
4813 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
4814 #define CAN_F7R2_FB23_Pos (23U)
4815 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
4816 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
4817 #define CAN_F7R2_FB24_Pos (24U)
4818 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
4819 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
4820 #define CAN_F7R2_FB25_Pos (25U)
4821 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
4822 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
4823 #define CAN_F7R2_FB26_Pos (26U)
4824 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
4825 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
4826 #define CAN_F7R2_FB27_Pos (27U)
4827 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
4828 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
4829 #define CAN_F7R2_FB28_Pos (28U)
4830 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
4831 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
4832 #define CAN_F7R2_FB29_Pos (29U)
4833 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
4834 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
4835 #define CAN_F7R2_FB30_Pos (30U)
4836 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
4837 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
4838 #define CAN_F7R2_FB31_Pos (31U)
4839 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
4840 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
4841
4842 /******************* Bit definition for CAN_F8R2 register *******************/
4843 #define CAN_F8R2_FB0_Pos (0U)
4844 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
4845 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
4846 #define CAN_F8R2_FB1_Pos (1U)
4847 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
4848 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
4849 #define CAN_F8R2_FB2_Pos (2U)
4850 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
4851 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
4852 #define CAN_F8R2_FB3_Pos (3U)
4853 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
4854 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
4855 #define CAN_F8R2_FB4_Pos (4U)
4856 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
4857 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
4858 #define CAN_F8R2_FB5_Pos (5U)
4859 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
4860 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
4861 #define CAN_F8R2_FB6_Pos (6U)
4862 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
4863 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
4864 #define CAN_F8R2_FB7_Pos (7U)
4865 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
4866 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
4867 #define CAN_F8R2_FB8_Pos (8U)
4868 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
4869 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
4870 #define CAN_F8R2_FB9_Pos (9U)
4871 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
4872 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
4873 #define CAN_F8R2_FB10_Pos (10U)
4874 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
4875 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
4876 #define CAN_F8R2_FB11_Pos (11U)
4877 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
4878 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
4879 #define CAN_F8R2_FB12_Pos (12U)
4880 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
4881 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
4882 #define CAN_F8R2_FB13_Pos (13U)
4883 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
4884 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
4885 #define CAN_F8R2_FB14_Pos (14U)
4886 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
4887 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
4888 #define CAN_F8R2_FB15_Pos (15U)
4889 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
4890 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
4891 #define CAN_F8R2_FB16_Pos (16U)
4892 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
4893 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
4894 #define CAN_F8R2_FB17_Pos (17U)
4895 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
4896 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
4897 #define CAN_F8R2_FB18_Pos (18U)
4898 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
4899 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
4900 #define CAN_F8R2_FB19_Pos (19U)
4901 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
4902 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
4903 #define CAN_F8R2_FB20_Pos (20U)
4904 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
4905 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
4906 #define CAN_F8R2_FB21_Pos (21U)
4907 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
4908 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
4909 #define CAN_F8R2_FB22_Pos (22U)
4910 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
4911 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
4912 #define CAN_F8R2_FB23_Pos (23U)
4913 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
4914 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
4915 #define CAN_F8R2_FB24_Pos (24U)
4916 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
4917 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
4918 #define CAN_F8R2_FB25_Pos (25U)
4919 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
4920 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
4921 #define CAN_F8R2_FB26_Pos (26U)
4922 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
4923 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
4924 #define CAN_F8R2_FB27_Pos (27U)
4925 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
4926 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
4927 #define CAN_F8R2_FB28_Pos (28U)
4928 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
4929 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
4930 #define CAN_F8R2_FB29_Pos (29U)
4931 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
4932 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
4933 #define CAN_F8R2_FB30_Pos (30U)
4934 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
4935 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
4936 #define CAN_F8R2_FB31_Pos (31U)
4937 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
4938 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
4939
4940 /******************* Bit definition for CAN_F9R2 register *******************/
4941 #define CAN_F9R2_FB0_Pos (0U)
4942 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
4943 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
4944 #define CAN_F9R2_FB1_Pos (1U)
4945 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
4946 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
4947 #define CAN_F9R2_FB2_Pos (2U)
4948 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
4949 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
4950 #define CAN_F9R2_FB3_Pos (3U)
4951 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
4952 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
4953 #define CAN_F9R2_FB4_Pos (4U)
4954 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
4955 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
4956 #define CAN_F9R2_FB5_Pos (5U)
4957 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
4958 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
4959 #define CAN_F9R2_FB6_Pos (6U)
4960 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
4961 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
4962 #define CAN_F9R2_FB7_Pos (7U)
4963 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
4964 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
4965 #define CAN_F9R2_FB8_Pos (8U)
4966 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
4967 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
4968 #define CAN_F9R2_FB9_Pos (9U)
4969 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
4970 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
4971 #define CAN_F9R2_FB10_Pos (10U)
4972 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
4973 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
4974 #define CAN_F9R2_FB11_Pos (11U)
4975 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
4976 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
4977 #define CAN_F9R2_FB12_Pos (12U)
4978 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
4979 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
4980 #define CAN_F9R2_FB13_Pos (13U)
4981 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
4982 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
4983 #define CAN_F9R2_FB14_Pos (14U)
4984 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
4985 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
4986 #define CAN_F9R2_FB15_Pos (15U)
4987 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
4988 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
4989 #define CAN_F9R2_FB16_Pos (16U)
4990 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
4991 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
4992 #define CAN_F9R2_FB17_Pos (17U)
4993 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
4994 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
4995 #define CAN_F9R2_FB18_Pos (18U)
4996 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
4997 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
4998 #define CAN_F9R2_FB19_Pos (19U)
4999 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5000 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5001 #define CAN_F9R2_FB20_Pos (20U)
5002 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5003 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5004 #define CAN_F9R2_FB21_Pos (21U)
5005 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5006 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5007 #define CAN_F9R2_FB22_Pos (22U)
5008 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5009 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5010 #define CAN_F9R2_FB23_Pos (23U)
5011 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5012 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5013 #define CAN_F9R2_FB24_Pos (24U)
5014 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5015 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5016 #define CAN_F9R2_FB25_Pos (25U)
5017 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5018 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5019 #define CAN_F9R2_FB26_Pos (26U)
5020 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5021 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5022 #define CAN_F9R2_FB27_Pos (27U)
5023 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5024 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5025 #define CAN_F9R2_FB28_Pos (28U)
5026 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5027 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5028 #define CAN_F9R2_FB29_Pos (29U)
5029 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5030 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5031 #define CAN_F9R2_FB30_Pos (30U)
5032 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5033 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5034 #define CAN_F9R2_FB31_Pos (31U)
5035 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5036 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5037
5038 /******************* Bit definition for CAN_F10R2 register ******************/
5039 #define CAN_F10R2_FB0_Pos (0U)
5040 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5041 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5042 #define CAN_F10R2_FB1_Pos (1U)
5043 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5044 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5045 #define CAN_F10R2_FB2_Pos (2U)
5046 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5047 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5048 #define CAN_F10R2_FB3_Pos (3U)
5049 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5050 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5051 #define CAN_F10R2_FB4_Pos (4U)
5052 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5053 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5054 #define CAN_F10R2_FB5_Pos (5U)
5055 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5056 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5057 #define CAN_F10R2_FB6_Pos (6U)
5058 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5059 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5060 #define CAN_F10R2_FB7_Pos (7U)
5061 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5062 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5063 #define CAN_F10R2_FB8_Pos (8U)
5064 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5065 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5066 #define CAN_F10R2_FB9_Pos (9U)
5067 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5068 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5069 #define CAN_F10R2_FB10_Pos (10U)
5070 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5071 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5072 #define CAN_F10R2_FB11_Pos (11U)
5073 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5074 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5075 #define CAN_F10R2_FB12_Pos (12U)
5076 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5077 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5078 #define CAN_F10R2_FB13_Pos (13U)
5079 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5080 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5081 #define CAN_F10R2_FB14_Pos (14U)
5082 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5083 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5084 #define CAN_F10R2_FB15_Pos (15U)
5085 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5086 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5087 #define CAN_F10R2_FB16_Pos (16U)
5088 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5089 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5090 #define CAN_F10R2_FB17_Pos (17U)
5091 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5092 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5093 #define CAN_F10R2_FB18_Pos (18U)
5094 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5095 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5096 #define CAN_F10R2_FB19_Pos (19U)
5097 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5098 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5099 #define CAN_F10R2_FB20_Pos (20U)
5100 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5101 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5102 #define CAN_F10R2_FB21_Pos (21U)
5103 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5104 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5105 #define CAN_F10R2_FB22_Pos (22U)
5106 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5107 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5108 #define CAN_F10R2_FB23_Pos (23U)
5109 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5110 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5111 #define CAN_F10R2_FB24_Pos (24U)
5112 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5113 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5114 #define CAN_F10R2_FB25_Pos (25U)
5115 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5116 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5117 #define CAN_F10R2_FB26_Pos (26U)
5118 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5119 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5120 #define CAN_F10R2_FB27_Pos (27U)
5121 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5122 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5123 #define CAN_F10R2_FB28_Pos (28U)
5124 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5125 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5126 #define CAN_F10R2_FB29_Pos (29U)
5127 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5128 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5129 #define CAN_F10R2_FB30_Pos (30U)
5130 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5131 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5132 #define CAN_F10R2_FB31_Pos (31U)
5133 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5134 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5135
5136 /******************* Bit definition for CAN_F11R2 register ******************/
5137 #define CAN_F11R2_FB0_Pos (0U)
5138 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5139 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5140 #define CAN_F11R2_FB1_Pos (1U)
5141 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5142 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5143 #define CAN_F11R2_FB2_Pos (2U)
5144 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5145 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5146 #define CAN_F11R2_FB3_Pos (3U)
5147 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5148 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5149 #define CAN_F11R2_FB4_Pos (4U)
5150 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5151 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5152 #define CAN_F11R2_FB5_Pos (5U)
5153 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5154 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5155 #define CAN_F11R2_FB6_Pos (6U)
5156 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5157 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5158 #define CAN_F11R2_FB7_Pos (7U)
5159 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5160 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5161 #define CAN_F11R2_FB8_Pos (8U)
5162 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5163 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5164 #define CAN_F11R2_FB9_Pos (9U)
5165 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5166 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5167 #define CAN_F11R2_FB10_Pos (10U)
5168 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5169 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5170 #define CAN_F11R2_FB11_Pos (11U)
5171 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5172 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5173 #define CAN_F11R2_FB12_Pos (12U)
5174 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5175 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5176 #define CAN_F11R2_FB13_Pos (13U)
5177 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5178 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5179 #define CAN_F11R2_FB14_Pos (14U)
5180 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5181 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5182 #define CAN_F11R2_FB15_Pos (15U)
5183 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5184 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5185 #define CAN_F11R2_FB16_Pos (16U)
5186 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5187 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5188 #define CAN_F11R2_FB17_Pos (17U)
5189 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5190 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5191 #define CAN_F11R2_FB18_Pos (18U)
5192 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5193 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5194 #define CAN_F11R2_FB19_Pos (19U)
5195 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5196 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5197 #define CAN_F11R2_FB20_Pos (20U)
5198 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5199 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5200 #define CAN_F11R2_FB21_Pos (21U)
5201 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5202 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5203 #define CAN_F11R2_FB22_Pos (22U)
5204 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5205 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5206 #define CAN_F11R2_FB23_Pos (23U)
5207 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5208 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5209 #define CAN_F11R2_FB24_Pos (24U)
5210 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5211 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5212 #define CAN_F11R2_FB25_Pos (25U)
5213 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5214 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5215 #define CAN_F11R2_FB26_Pos (26U)
5216 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5217 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5218 #define CAN_F11R2_FB27_Pos (27U)
5219 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5220 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5221 #define CAN_F11R2_FB28_Pos (28U)
5222 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5223 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5224 #define CAN_F11R2_FB29_Pos (29U)
5225 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5226 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5227 #define CAN_F11R2_FB30_Pos (30U)
5228 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5229 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5230 #define CAN_F11R2_FB31_Pos (31U)
5231 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5232 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5233
5234 /******************* Bit definition for CAN_F12R2 register ******************/
5235 #define CAN_F12R2_FB0_Pos (0U)
5236 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5237 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5238 #define CAN_F12R2_FB1_Pos (1U)
5239 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5240 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5241 #define CAN_F12R2_FB2_Pos (2U)
5242 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5243 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5244 #define CAN_F12R2_FB3_Pos (3U)
5245 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5246 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5247 #define CAN_F12R2_FB4_Pos (4U)
5248 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5249 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5250 #define CAN_F12R2_FB5_Pos (5U)
5251 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5252 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5253 #define CAN_F12R2_FB6_Pos (6U)
5254 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5255 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5256 #define CAN_F12R2_FB7_Pos (7U)
5257 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5258 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5259 #define CAN_F12R2_FB8_Pos (8U)
5260 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5261 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5262 #define CAN_F12R2_FB9_Pos (9U)
5263 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5264 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5265 #define CAN_F12R2_FB10_Pos (10U)
5266 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5267 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5268 #define CAN_F12R2_FB11_Pos (11U)
5269 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5270 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5271 #define CAN_F12R2_FB12_Pos (12U)
5272 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5273 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5274 #define CAN_F12R2_FB13_Pos (13U)
5275 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5276 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5277 #define CAN_F12R2_FB14_Pos (14U)
5278 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5279 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5280 #define CAN_F12R2_FB15_Pos (15U)
5281 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5282 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5283 #define CAN_F12R2_FB16_Pos (16U)
5284 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5285 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5286 #define CAN_F12R2_FB17_Pos (17U)
5287 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5288 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5289 #define CAN_F12R2_FB18_Pos (18U)
5290 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5291 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5292 #define CAN_F12R2_FB19_Pos (19U)
5293 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5294 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5295 #define CAN_F12R2_FB20_Pos (20U)
5296 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5297 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5298 #define CAN_F12R2_FB21_Pos (21U)
5299 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5300 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5301 #define CAN_F12R2_FB22_Pos (22U)
5302 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5303 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5304 #define CAN_F12R2_FB23_Pos (23U)
5305 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5306 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5307 #define CAN_F12R2_FB24_Pos (24U)
5308 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5309 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5310 #define CAN_F12R2_FB25_Pos (25U)
5311 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5312 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5313 #define CAN_F12R2_FB26_Pos (26U)
5314 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5315 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5316 #define CAN_F12R2_FB27_Pos (27U)
5317 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5318 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5319 #define CAN_F12R2_FB28_Pos (28U)
5320 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5321 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5322 #define CAN_F12R2_FB29_Pos (29U)
5323 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5324 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5325 #define CAN_F12R2_FB30_Pos (30U)
5326 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5327 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5328 #define CAN_F12R2_FB31_Pos (31U)
5329 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5330 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5331
5332 /******************* Bit definition for CAN_F13R2 register ******************/
5333 #define CAN_F13R2_FB0_Pos (0U)
5334 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5335 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5336 #define CAN_F13R2_FB1_Pos (1U)
5337 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5338 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5339 #define CAN_F13R2_FB2_Pos (2U)
5340 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5341 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5342 #define CAN_F13R2_FB3_Pos (3U)
5343 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5344 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5345 #define CAN_F13R2_FB4_Pos (4U)
5346 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5347 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5348 #define CAN_F13R2_FB5_Pos (5U)
5349 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5350 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5351 #define CAN_F13R2_FB6_Pos (6U)
5352 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5353 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5354 #define CAN_F13R2_FB7_Pos (7U)
5355 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5356 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5357 #define CAN_F13R2_FB8_Pos (8U)
5358 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5359 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5360 #define CAN_F13R2_FB9_Pos (9U)
5361 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5362 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5363 #define CAN_F13R2_FB10_Pos (10U)
5364 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5365 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5366 #define CAN_F13R2_FB11_Pos (11U)
5367 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5368 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5369 #define CAN_F13R2_FB12_Pos (12U)
5370 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5371 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5372 #define CAN_F13R2_FB13_Pos (13U)
5373 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5374 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5375 #define CAN_F13R2_FB14_Pos (14U)
5376 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5377 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5378 #define CAN_F13R2_FB15_Pos (15U)
5379 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5380 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5381 #define CAN_F13R2_FB16_Pos (16U)
5382 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5383 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5384 #define CAN_F13R2_FB17_Pos (17U)
5385 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5386 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5387 #define CAN_F13R2_FB18_Pos (18U)
5388 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5389 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5390 #define CAN_F13R2_FB19_Pos (19U)
5391 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5392 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5393 #define CAN_F13R2_FB20_Pos (20U)
5394 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5395 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5396 #define CAN_F13R2_FB21_Pos (21U)
5397 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5398 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5399 #define CAN_F13R2_FB22_Pos (22U)
5400 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5401 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5402 #define CAN_F13R2_FB23_Pos (23U)
5403 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5404 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5405 #define CAN_F13R2_FB24_Pos (24U)
5406 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5407 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5408 #define CAN_F13R2_FB25_Pos (25U)
5409 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5410 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5411 #define CAN_F13R2_FB26_Pos (26U)
5412 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5413 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5414 #define CAN_F13R2_FB27_Pos (27U)
5415 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5416 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5417 #define CAN_F13R2_FB28_Pos (28U)
5418 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5419 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5420 #define CAN_F13R2_FB29_Pos (29U)
5421 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5422 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5423 #define CAN_F13R2_FB30_Pos (30U)
5424 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5425 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5426 #define CAN_F13R2_FB31_Pos (31U)
5427 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5428 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5429
5430 /******************************************************************************/
5431 /* */
5432 /* CRC calculation unit */
5433 /* */
5434 /******************************************************************************/
5435 /******************* Bit definition for CRC_DR register *********************/
5436 #define CRC_DR_DR_Pos (0U)
5437 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5438 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5439
5440
5441 /******************* Bit definition for CRC_IDR register ********************/
5442 #define CRC_IDR_IDR_Pos (0U)
5443 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5444 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5445
5446
5447 /******************** Bit definition for CRC_CR register ********************/
5448 #define CRC_CR_RESET_Pos (0U)
5449 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5450 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5451
5452 /******************************************************************************/
5453 /* */
5454 /* Digital to Analog Converter */
5455 /* */
5456 /******************************************************************************/
5457 /*
5458 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5459 */
5460 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5461 /******************** Bit definition for DAC_CR register ********************/
5462 #define DAC_CR_EN1_Pos (0U)
5463 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5464 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5465 #define DAC_CR_BOFF1_Pos (1U)
5466 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5467 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5468 #define DAC_CR_TEN1_Pos (2U)
5469 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5470 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5471
5472 #define DAC_CR_TSEL1_Pos (3U)
5473 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5474 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5475 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5476 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5477 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5478
5479 #define DAC_CR_WAVE1_Pos (6U)
5480 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5481 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5482 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5483 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5484
5485 #define DAC_CR_MAMP1_Pos (8U)
5486 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5487 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5488 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5489 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5490 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5491 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5492
5493 #define DAC_CR_DMAEN1_Pos (12U)
5494 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5495 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5496 #define DAC_CR_DMAUDRIE1_Pos (13U)
5497 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5498 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5499 #define DAC_CR_EN2_Pos (16U)
5500 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5501 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5502 #define DAC_CR_BOFF2_Pos (17U)
5503 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5504 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5505 #define DAC_CR_TEN2_Pos (18U)
5506 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5507 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5508
5509 #define DAC_CR_TSEL2_Pos (19U)
5510 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5511 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5512 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5513 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5514 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5515
5516 #define DAC_CR_WAVE2_Pos (22U)
5517 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5518 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5519 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5520 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5521
5522 #define DAC_CR_MAMP2_Pos (24U)
5523 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5524 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5525 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5526 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5527 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5528 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5529
5530 #define DAC_CR_DMAEN2_Pos (28U)
5531 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5532 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5533 #define DAC_CR_DMAUDRIE2_Pos (29U)
5534 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5535 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5536
5537 /***************** Bit definition for DAC_SWTRIGR register ******************/
5538 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5539 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5540 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5541 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5542 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5543 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5544
5545 /***************** Bit definition for DAC_DHR12R1 register ******************/
5546 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5547 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5548 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5549
5550 /***************** Bit definition for DAC_DHR12L1 register ******************/
5551 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5552 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5553 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5554
5555 /****************** Bit definition for DAC_DHR8R1 register ******************/
5556 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5557 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5558 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5559
5560 /***************** Bit definition for DAC_DHR12R2 register ******************/
5561 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5562 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5563 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5564
5565 /***************** Bit definition for DAC_DHR12L2 register ******************/
5566 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5567 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5568 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5569
5570 /****************** Bit definition for DAC_DHR8R2 register ******************/
5571 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5572 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5573 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5574
5575 /***************** Bit definition for DAC_DHR12RD register ******************/
5576 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5577 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5578 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5579 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5580 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5581 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5582
5583 /***************** Bit definition for DAC_DHR12LD register ******************/
5584 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5585 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5586 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5587 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5588 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5589 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5590
5591 /****************** Bit definition for DAC_DHR8RD register ******************/
5592 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5593 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5594 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5595 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5596 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5597 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5598
5599 /******************* Bit definition for DAC_DOR1 register *******************/
5600 #define DAC_DOR1_DACC1DOR_Pos (0U)
5601 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5602 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5603
5604 /******************* Bit definition for DAC_DOR2 register *******************/
5605 #define DAC_DOR2_DACC2DOR_Pos (0U)
5606 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5607 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5608
5609 /******************** Bit definition for DAC_SR register ********************/
5610 #define DAC_SR_DMAUDR1_Pos (13U)
5611 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5612 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5613 #define DAC_SR_DMAUDR2_Pos (29U)
5614 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5615 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5616
5617 /******************************************************************************/
5618 /* */
5619 /* DCMI */
5620 /* */
5621 /******************************************************************************/
5622 /******************** Bits definition for DCMI_CR register ******************/
5623 #define DCMI_CR_CAPTURE_Pos (0U)
5624 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5625 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5626 #define DCMI_CR_CM_Pos (1U)
5627 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5628 #define DCMI_CR_CM DCMI_CR_CM_Msk
5629 #define DCMI_CR_CROP_Pos (2U)
5630 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5631 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
5632 #define DCMI_CR_JPEG_Pos (3U)
5633 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5634 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5635 #define DCMI_CR_ESS_Pos (4U)
5636 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5637 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
5638 #define DCMI_CR_PCKPOL_Pos (5U)
5639 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5640 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5641 #define DCMI_CR_HSPOL_Pos (6U)
5642 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5643 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5644 #define DCMI_CR_VSPOL_Pos (7U)
5645 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5646 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5647 #define DCMI_CR_FCRC_0 0x00000100U
5648 #define DCMI_CR_FCRC_1 0x00000200U
5649 #define DCMI_CR_EDM_0 0x00000400U
5650 #define DCMI_CR_EDM_1 0x00000800U
5651 #define DCMI_CR_CRE_Pos (12U)
5652 #define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
5653 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
5654 #define DCMI_CR_ENABLE_Pos (14U)
5655 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5656 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5657
5658 /******************** Bits definition for DCMI_SR register ******************/
5659 #define DCMI_SR_HSYNC_Pos (0U)
5660 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
5661 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5662 #define DCMI_SR_VSYNC_Pos (1U)
5663 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
5664 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5665 #define DCMI_SR_FNE_Pos (2U)
5666 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
5667 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
5668
5669 /******************** Bits definition for DCMI_RIS register *****************/
5670 #define DCMI_RIS_FRAME_RIS_Pos (0U)
5671 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
5672 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5673 #define DCMI_RIS_OVR_RIS_Pos (1U)
5674 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
5675 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5676 #define DCMI_RIS_ERR_RIS_Pos (2U)
5677 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
5678 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5679 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
5680 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
5681 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5682 #define DCMI_RIS_LINE_RIS_Pos (4U)
5683 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
5684 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5685 /* Legacy defines */
5686 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5687 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5688 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5689 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5690 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5691 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5692
5693 /******************** Bits definition for DCMI_IER register *****************/
5694 #define DCMI_IER_FRAME_IE_Pos (0U)
5695 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
5696 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5697 #define DCMI_IER_OVR_IE_Pos (1U)
5698 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
5699 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5700 #define DCMI_IER_ERR_IE_Pos (2U)
5701 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
5702 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5703 #define DCMI_IER_VSYNC_IE_Pos (3U)
5704 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
5705 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5706 #define DCMI_IER_LINE_IE_Pos (4U)
5707 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
5708 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5709 /* Legacy defines */
5710 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5711
5712 /******************** Bits definition for DCMI_MIS register *****************/
5713 #define DCMI_MIS_FRAME_MIS_Pos (0U)
5714 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
5715 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5716 #define DCMI_MIS_OVR_MIS_Pos (1U)
5717 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
5718 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5719 #define DCMI_MIS_ERR_MIS_Pos (2U)
5720 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
5721 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5722 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
5723 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
5724 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5725 #define DCMI_MIS_LINE_MIS_Pos (4U)
5726 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
5727 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5728
5729 /* Legacy defines */
5730 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5731 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5732 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5733 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5734 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5735
5736 /******************** Bits definition for DCMI_ICR register *****************/
5737 #define DCMI_ICR_FRAME_ISC_Pos (0U)
5738 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
5739 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5740 #define DCMI_ICR_OVR_ISC_Pos (1U)
5741 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
5742 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5743 #define DCMI_ICR_ERR_ISC_Pos (2U)
5744 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
5745 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5746 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
5747 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
5748 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5749 #define DCMI_ICR_LINE_ISC_Pos (4U)
5750 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
5751 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5752
5753 /* Legacy defines */
5754 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5755
5756 /******************** Bits definition for DCMI_ESCR register ******************/
5757 #define DCMI_ESCR_FSC_Pos (0U)
5758 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
5759 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5760 #define DCMI_ESCR_LSC_Pos (8U)
5761 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
5762 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5763 #define DCMI_ESCR_LEC_Pos (16U)
5764 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
5765 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5766 #define DCMI_ESCR_FEC_Pos (24U)
5767 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
5768 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5769
5770 /******************** Bits definition for DCMI_ESUR register ******************/
5771 #define DCMI_ESUR_FSU_Pos (0U)
5772 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
5773 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5774 #define DCMI_ESUR_LSU_Pos (8U)
5775 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
5776 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5777 #define DCMI_ESUR_LEU_Pos (16U)
5778 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
5779 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5780 #define DCMI_ESUR_FEU_Pos (24U)
5781 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
5782 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5783
5784 /******************** Bits definition for DCMI_CWSTRT register ******************/
5785 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5786 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
5787 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5788 #define DCMI_CWSTRT_VST_Pos (16U)
5789 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
5790 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5791
5792 /******************** Bits definition for DCMI_CWSIZE register ******************/
5793 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
5794 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
5795 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5796 #define DCMI_CWSIZE_VLINE_Pos (16U)
5797 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
5798 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5799
5800 /******************** Bits definition for DCMI_DR register *********************/
5801 #define DCMI_DR_BYTE0_Pos (0U)
5802 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
5803 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5804 #define DCMI_DR_BYTE1_Pos (8U)
5805 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
5806 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5807 #define DCMI_DR_BYTE2_Pos (16U)
5808 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
5809 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5810 #define DCMI_DR_BYTE3_Pos (24U)
5811 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
5812 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5813
5814 /******************************************************************************/
5815 /* */
5816 /* DMA Controller */
5817 /* */
5818 /******************************************************************************/
5819 /******************** Bits definition for DMA_SxCR register *****************/
5820 #define DMA_SxCR_CHSEL_Pos (25U)
5821 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
5822 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5823 #define DMA_SxCR_CHSEL_0 0x02000000U
5824 #define DMA_SxCR_CHSEL_1 0x04000000U
5825 #define DMA_SxCR_CHSEL_2 0x08000000U
5826 #define DMA_SxCR_MBURST_Pos (23U)
5827 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
5828 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5829 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
5830 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
5831 #define DMA_SxCR_PBURST_Pos (21U)
5832 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
5833 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5834 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
5835 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
5836 #define DMA_SxCR_CT_Pos (19U)
5837 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
5838 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
5839 #define DMA_SxCR_DBM_Pos (18U)
5840 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
5841 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5842 #define DMA_SxCR_PL_Pos (16U)
5843 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
5844 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
5845 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
5846 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
5847 #define DMA_SxCR_PINCOS_Pos (15U)
5848 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
5849 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5850 #define DMA_SxCR_MSIZE_Pos (13U)
5851 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
5852 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5853 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
5854 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
5855 #define DMA_SxCR_PSIZE_Pos (11U)
5856 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
5857 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5858 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
5859 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
5860 #define DMA_SxCR_MINC_Pos (10U)
5861 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5862 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5863 #define DMA_SxCR_PINC_Pos (9U)
5864 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
5865 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5866 #define DMA_SxCR_CIRC_Pos (8U)
5867 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
5868 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5869 #define DMA_SxCR_DIR_Pos (6U)
5870 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
5871 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5872 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
5873 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
5874 #define DMA_SxCR_PFCTRL_Pos (5U)
5875 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
5876 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5877 #define DMA_SxCR_TCIE_Pos (4U)
5878 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
5879 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5880 #define DMA_SxCR_HTIE_Pos (3U)
5881 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
5882 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5883 #define DMA_SxCR_TEIE_Pos (2U)
5884 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
5885 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5886 #define DMA_SxCR_DMEIE_Pos (1U)
5887 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
5888 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5889 #define DMA_SxCR_EN_Pos (0U)
5890 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
5891 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
5892
5893 /* Legacy defines */
5894 #define DMA_SxCR_ACK_Pos (20U)
5895 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
5896 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
5897
5898 /******************** Bits definition for DMA_SxCNDTR register **************/
5899 #define DMA_SxNDT_Pos (0U)
5900 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
5901 #define DMA_SxNDT DMA_SxNDT_Msk
5902 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
5903 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
5904 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
5905 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
5906 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
5907 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
5908 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
5909 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
5910 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
5911 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
5912 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
5913 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
5914 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
5915 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
5916 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
5917 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
5918
5919 /******************** Bits definition for DMA_SxFCR register ****************/
5920 #define DMA_SxFCR_FEIE_Pos (7U)
5921 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
5922 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
5923 #define DMA_SxFCR_FS_Pos (3U)
5924 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
5925 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
5926 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
5927 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
5928 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
5929 #define DMA_SxFCR_DMDIS_Pos (2U)
5930 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
5931 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
5932 #define DMA_SxFCR_FTH_Pos (0U)
5933 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
5934 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
5935 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
5936 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
5937
5938 /******************** Bits definition for DMA_LISR register *****************/
5939 #define DMA_LISR_TCIF3_Pos (27U)
5940 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
5941 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
5942 #define DMA_LISR_HTIF3_Pos (26U)
5943 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
5944 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
5945 #define DMA_LISR_TEIF3_Pos (25U)
5946 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
5947 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
5948 #define DMA_LISR_DMEIF3_Pos (24U)
5949 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
5950 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
5951 #define DMA_LISR_FEIF3_Pos (22U)
5952 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
5953 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
5954 #define DMA_LISR_TCIF2_Pos (21U)
5955 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
5956 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
5957 #define DMA_LISR_HTIF2_Pos (20U)
5958 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
5959 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
5960 #define DMA_LISR_TEIF2_Pos (19U)
5961 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
5962 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
5963 #define DMA_LISR_DMEIF2_Pos (18U)
5964 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
5965 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
5966 #define DMA_LISR_FEIF2_Pos (16U)
5967 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
5968 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
5969 #define DMA_LISR_TCIF1_Pos (11U)
5970 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
5971 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
5972 #define DMA_LISR_HTIF1_Pos (10U)
5973 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
5974 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
5975 #define DMA_LISR_TEIF1_Pos (9U)
5976 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
5977 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
5978 #define DMA_LISR_DMEIF1_Pos (8U)
5979 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
5980 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
5981 #define DMA_LISR_FEIF1_Pos (6U)
5982 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
5983 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
5984 #define DMA_LISR_TCIF0_Pos (5U)
5985 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
5986 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
5987 #define DMA_LISR_HTIF0_Pos (4U)
5988 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
5989 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
5990 #define DMA_LISR_TEIF0_Pos (3U)
5991 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
5992 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
5993 #define DMA_LISR_DMEIF0_Pos (2U)
5994 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
5995 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
5996 #define DMA_LISR_FEIF0_Pos (0U)
5997 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
5998 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
5999
6000 /******************** Bits definition for DMA_HISR register *****************/
6001 #define DMA_HISR_TCIF7_Pos (27U)
6002 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6003 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6004 #define DMA_HISR_HTIF7_Pos (26U)
6005 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6006 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6007 #define DMA_HISR_TEIF7_Pos (25U)
6008 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6009 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6010 #define DMA_HISR_DMEIF7_Pos (24U)
6011 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6012 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6013 #define DMA_HISR_FEIF7_Pos (22U)
6014 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6015 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6016 #define DMA_HISR_TCIF6_Pos (21U)
6017 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6018 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6019 #define DMA_HISR_HTIF6_Pos (20U)
6020 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6021 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6022 #define DMA_HISR_TEIF6_Pos (19U)
6023 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6024 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6025 #define DMA_HISR_DMEIF6_Pos (18U)
6026 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6027 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6028 #define DMA_HISR_FEIF6_Pos (16U)
6029 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6030 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6031 #define DMA_HISR_TCIF5_Pos (11U)
6032 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6033 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6034 #define DMA_HISR_HTIF5_Pos (10U)
6035 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6036 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6037 #define DMA_HISR_TEIF5_Pos (9U)
6038 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6039 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6040 #define DMA_HISR_DMEIF5_Pos (8U)
6041 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6042 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6043 #define DMA_HISR_FEIF5_Pos (6U)
6044 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6045 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6046 #define DMA_HISR_TCIF4_Pos (5U)
6047 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6048 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6049 #define DMA_HISR_HTIF4_Pos (4U)
6050 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6051 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6052 #define DMA_HISR_TEIF4_Pos (3U)
6053 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6054 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6055 #define DMA_HISR_DMEIF4_Pos (2U)
6056 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6057 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6058 #define DMA_HISR_FEIF4_Pos (0U)
6059 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6060 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6061
6062 /******************** Bits definition for DMA_LIFCR register ****************/
6063 #define DMA_LIFCR_CTCIF3_Pos (27U)
6064 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6065 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6066 #define DMA_LIFCR_CHTIF3_Pos (26U)
6067 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6068 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6069 #define DMA_LIFCR_CTEIF3_Pos (25U)
6070 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6071 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6072 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6073 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6074 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6075 #define DMA_LIFCR_CFEIF3_Pos (22U)
6076 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6077 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6078 #define DMA_LIFCR_CTCIF2_Pos (21U)
6079 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6080 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6081 #define DMA_LIFCR_CHTIF2_Pos (20U)
6082 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6083 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6084 #define DMA_LIFCR_CTEIF2_Pos (19U)
6085 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6086 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6087 #define DMA_LIFCR_CDMEIF2_Pos (18U)
6088 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6089 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6090 #define DMA_LIFCR_CFEIF2_Pos (16U)
6091 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6092 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6093 #define DMA_LIFCR_CTCIF1_Pos (11U)
6094 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6095 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6096 #define DMA_LIFCR_CHTIF1_Pos (10U)
6097 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6098 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6099 #define DMA_LIFCR_CTEIF1_Pos (9U)
6100 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6101 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6102 #define DMA_LIFCR_CDMEIF1_Pos (8U)
6103 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6104 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6105 #define DMA_LIFCR_CFEIF1_Pos (6U)
6106 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6107 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6108 #define DMA_LIFCR_CTCIF0_Pos (5U)
6109 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6110 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6111 #define DMA_LIFCR_CHTIF0_Pos (4U)
6112 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6113 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6114 #define DMA_LIFCR_CTEIF0_Pos (3U)
6115 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6116 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6117 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6118 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6119 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6120 #define DMA_LIFCR_CFEIF0_Pos (0U)
6121 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6122 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6123
6124 /******************** Bits definition for DMA_HIFCR register ****************/
6125 #define DMA_HIFCR_CTCIF7_Pos (27U)
6126 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6127 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6128 #define DMA_HIFCR_CHTIF7_Pos (26U)
6129 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6130 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6131 #define DMA_HIFCR_CTEIF7_Pos (25U)
6132 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6133 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6134 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6135 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6136 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6137 #define DMA_HIFCR_CFEIF7_Pos (22U)
6138 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6139 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6140 #define DMA_HIFCR_CTCIF6_Pos (21U)
6141 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6142 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6143 #define DMA_HIFCR_CHTIF6_Pos (20U)
6144 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6145 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6146 #define DMA_HIFCR_CTEIF6_Pos (19U)
6147 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6148 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6149 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6150 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6151 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6152 #define DMA_HIFCR_CFEIF6_Pos (16U)
6153 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6154 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6155 #define DMA_HIFCR_CTCIF5_Pos (11U)
6156 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6157 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6158 #define DMA_HIFCR_CHTIF5_Pos (10U)
6159 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6160 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6161 #define DMA_HIFCR_CTEIF5_Pos (9U)
6162 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6163 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6164 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6165 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6166 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6167 #define DMA_HIFCR_CFEIF5_Pos (6U)
6168 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6169 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6170 #define DMA_HIFCR_CTCIF4_Pos (5U)
6171 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6172 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6173 #define DMA_HIFCR_CHTIF4_Pos (4U)
6174 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6175 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6176 #define DMA_HIFCR_CTEIF4_Pos (3U)
6177 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6178 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6179 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6180 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6181 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6182 #define DMA_HIFCR_CFEIF4_Pos (0U)
6183 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6184 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6185
6186 /****************** Bit definition for DMA_SxPAR register ********************/
6187 #define DMA_SxPAR_PA_Pos (0U)
6188 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6189 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6190
6191 /****************** Bit definition for DMA_SxM0AR register ********************/
6192 #define DMA_SxM0AR_M0A_Pos (0U)
6193 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6194 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6195
6196 /****************** Bit definition for DMA_SxM1AR register ********************/
6197 #define DMA_SxM1AR_M1A_Pos (0U)
6198 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6199 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6200
6201
6202 /******************************************************************************/
6203 /* */
6204 /* External Interrupt/Event Controller */
6205 /* */
6206 /******************************************************************************/
6207 /******************* Bit definition for EXTI_IMR register *******************/
6208 #define EXTI_IMR_MR0_Pos (0U)
6209 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
6210 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
6211 #define EXTI_IMR_MR1_Pos (1U)
6212 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
6213 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
6214 #define EXTI_IMR_MR2_Pos (2U)
6215 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
6216 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
6217 #define EXTI_IMR_MR3_Pos (3U)
6218 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
6219 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
6220 #define EXTI_IMR_MR4_Pos (4U)
6221 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
6222 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
6223 #define EXTI_IMR_MR5_Pos (5U)
6224 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
6225 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
6226 #define EXTI_IMR_MR6_Pos (6U)
6227 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
6228 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
6229 #define EXTI_IMR_MR7_Pos (7U)
6230 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
6231 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
6232 #define EXTI_IMR_MR8_Pos (8U)
6233 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
6234 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
6235 #define EXTI_IMR_MR9_Pos (9U)
6236 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
6237 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
6238 #define EXTI_IMR_MR10_Pos (10U)
6239 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
6240 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
6241 #define EXTI_IMR_MR11_Pos (11U)
6242 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
6243 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
6244 #define EXTI_IMR_MR12_Pos (12U)
6245 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
6246 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
6247 #define EXTI_IMR_MR13_Pos (13U)
6248 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
6249 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
6250 #define EXTI_IMR_MR14_Pos (14U)
6251 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
6252 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
6253 #define EXTI_IMR_MR15_Pos (15U)
6254 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
6255 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
6256 #define EXTI_IMR_MR16_Pos (16U)
6257 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
6258 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
6259 #define EXTI_IMR_MR17_Pos (17U)
6260 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
6261 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
6262 #define EXTI_IMR_MR18_Pos (18U)
6263 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
6264 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
6265 #define EXTI_IMR_MR19_Pos (19U)
6266 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
6267 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
6268 #define EXTI_IMR_MR20_Pos (20U)
6269 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
6270 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
6271 #define EXTI_IMR_MR21_Pos (21U)
6272 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
6273 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
6274 #define EXTI_IMR_MR22_Pos (22U)
6275 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
6276 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
6277
6278 /* Reference Defines */
6279 #define EXTI_IMR_IM0 EXTI_IMR_MR0
6280 #define EXTI_IMR_IM1 EXTI_IMR_MR1
6281 #define EXTI_IMR_IM2 EXTI_IMR_MR2
6282 #define EXTI_IMR_IM3 EXTI_IMR_MR3
6283 #define EXTI_IMR_IM4 EXTI_IMR_MR4
6284 #define EXTI_IMR_IM5 EXTI_IMR_MR5
6285 #define EXTI_IMR_IM6 EXTI_IMR_MR6
6286 #define EXTI_IMR_IM7 EXTI_IMR_MR7
6287 #define EXTI_IMR_IM8 EXTI_IMR_MR8
6288 #define EXTI_IMR_IM9 EXTI_IMR_MR9
6289 #define EXTI_IMR_IM10 EXTI_IMR_MR10
6290 #define EXTI_IMR_IM11 EXTI_IMR_MR11
6291 #define EXTI_IMR_IM12 EXTI_IMR_MR12
6292 #define EXTI_IMR_IM13 EXTI_IMR_MR13
6293 #define EXTI_IMR_IM14 EXTI_IMR_MR14
6294 #define EXTI_IMR_IM15 EXTI_IMR_MR15
6295 #define EXTI_IMR_IM16 EXTI_IMR_MR16
6296 #define EXTI_IMR_IM17 EXTI_IMR_MR17
6297 #define EXTI_IMR_IM18 EXTI_IMR_MR18
6298 #define EXTI_IMR_IM19 EXTI_IMR_MR19
6299 #define EXTI_IMR_IM20 EXTI_IMR_MR20
6300 #define EXTI_IMR_IM21 EXTI_IMR_MR21
6301 #define EXTI_IMR_IM22 EXTI_IMR_MR22
6302 #define EXTI_IMR_IM_Pos (0U)
6303 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
6304 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
6305
6306 /******************* Bit definition for EXTI_EMR register *******************/
6307 #define EXTI_EMR_MR0_Pos (0U)
6308 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
6309 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
6310 #define EXTI_EMR_MR1_Pos (1U)
6311 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
6312 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
6313 #define EXTI_EMR_MR2_Pos (2U)
6314 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
6315 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
6316 #define EXTI_EMR_MR3_Pos (3U)
6317 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
6318 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
6319 #define EXTI_EMR_MR4_Pos (4U)
6320 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
6321 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
6322 #define EXTI_EMR_MR5_Pos (5U)
6323 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
6324 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
6325 #define EXTI_EMR_MR6_Pos (6U)
6326 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
6327 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
6328 #define EXTI_EMR_MR7_Pos (7U)
6329 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
6330 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
6331 #define EXTI_EMR_MR8_Pos (8U)
6332 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
6333 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
6334 #define EXTI_EMR_MR9_Pos (9U)
6335 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
6336 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
6337 #define EXTI_EMR_MR10_Pos (10U)
6338 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
6339 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
6340 #define EXTI_EMR_MR11_Pos (11U)
6341 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
6342 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
6343 #define EXTI_EMR_MR12_Pos (12U)
6344 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
6345 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
6346 #define EXTI_EMR_MR13_Pos (13U)
6347 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
6348 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
6349 #define EXTI_EMR_MR14_Pos (14U)
6350 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
6351 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
6352 #define EXTI_EMR_MR15_Pos (15U)
6353 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
6354 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
6355 #define EXTI_EMR_MR16_Pos (16U)
6356 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
6357 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
6358 #define EXTI_EMR_MR17_Pos (17U)
6359 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
6360 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
6361 #define EXTI_EMR_MR18_Pos (18U)
6362 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
6363 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
6364 #define EXTI_EMR_MR19_Pos (19U)
6365 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
6366 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
6367 #define EXTI_EMR_MR20_Pos (20U)
6368 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
6369 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
6370 #define EXTI_EMR_MR21_Pos (21U)
6371 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
6372 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
6373 #define EXTI_EMR_MR22_Pos (22U)
6374 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
6375 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
6376
6377 /* Reference Defines */
6378 #define EXTI_EMR_EM0 EXTI_EMR_MR0
6379 #define EXTI_EMR_EM1 EXTI_EMR_MR1
6380 #define EXTI_EMR_EM2 EXTI_EMR_MR2
6381 #define EXTI_EMR_EM3 EXTI_EMR_MR3
6382 #define EXTI_EMR_EM4 EXTI_EMR_MR4
6383 #define EXTI_EMR_EM5 EXTI_EMR_MR5
6384 #define EXTI_EMR_EM6 EXTI_EMR_MR6
6385 #define EXTI_EMR_EM7 EXTI_EMR_MR7
6386 #define EXTI_EMR_EM8 EXTI_EMR_MR8
6387 #define EXTI_EMR_EM9 EXTI_EMR_MR9
6388 #define EXTI_EMR_EM10 EXTI_EMR_MR10
6389 #define EXTI_EMR_EM11 EXTI_EMR_MR11
6390 #define EXTI_EMR_EM12 EXTI_EMR_MR12
6391 #define EXTI_EMR_EM13 EXTI_EMR_MR13
6392 #define EXTI_EMR_EM14 EXTI_EMR_MR14
6393 #define EXTI_EMR_EM15 EXTI_EMR_MR15
6394 #define EXTI_EMR_EM16 EXTI_EMR_MR16
6395 #define EXTI_EMR_EM17 EXTI_EMR_MR17
6396 #define EXTI_EMR_EM18 EXTI_EMR_MR18
6397 #define EXTI_EMR_EM19 EXTI_EMR_MR19
6398 #define EXTI_EMR_EM20 EXTI_EMR_MR20
6399 #define EXTI_EMR_EM21 EXTI_EMR_MR21
6400 #define EXTI_EMR_EM22 EXTI_EMR_MR22
6401
6402 /****************** Bit definition for EXTI_RTSR register *******************/
6403 #define EXTI_RTSR_TR0_Pos (0U)
6404 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
6405 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
6406 #define EXTI_RTSR_TR1_Pos (1U)
6407 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
6408 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
6409 #define EXTI_RTSR_TR2_Pos (2U)
6410 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
6411 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
6412 #define EXTI_RTSR_TR3_Pos (3U)
6413 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
6414 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
6415 #define EXTI_RTSR_TR4_Pos (4U)
6416 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
6417 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
6418 #define EXTI_RTSR_TR5_Pos (5U)
6419 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
6420 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
6421 #define EXTI_RTSR_TR6_Pos (6U)
6422 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
6423 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
6424 #define EXTI_RTSR_TR7_Pos (7U)
6425 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
6426 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
6427 #define EXTI_RTSR_TR8_Pos (8U)
6428 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
6429 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
6430 #define EXTI_RTSR_TR9_Pos (9U)
6431 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
6432 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
6433 #define EXTI_RTSR_TR10_Pos (10U)
6434 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
6435 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
6436 #define EXTI_RTSR_TR11_Pos (11U)
6437 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
6438 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
6439 #define EXTI_RTSR_TR12_Pos (12U)
6440 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
6441 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
6442 #define EXTI_RTSR_TR13_Pos (13U)
6443 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
6444 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
6445 #define EXTI_RTSR_TR14_Pos (14U)
6446 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
6447 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
6448 #define EXTI_RTSR_TR15_Pos (15U)
6449 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
6450 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
6451 #define EXTI_RTSR_TR16_Pos (16U)
6452 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
6453 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
6454 #define EXTI_RTSR_TR17_Pos (17U)
6455 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
6456 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
6457 #define EXTI_RTSR_TR18_Pos (18U)
6458 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
6459 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
6460 #define EXTI_RTSR_TR19_Pos (19U)
6461 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
6462 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
6463 #define EXTI_RTSR_TR20_Pos (20U)
6464 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
6465 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
6466 #define EXTI_RTSR_TR21_Pos (21U)
6467 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
6468 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
6469 #define EXTI_RTSR_TR22_Pos (22U)
6470 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
6471 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
6472
6473 /****************** Bit definition for EXTI_FTSR register *******************/
6474 #define EXTI_FTSR_TR0_Pos (0U)
6475 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
6476 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
6477 #define EXTI_FTSR_TR1_Pos (1U)
6478 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
6479 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
6480 #define EXTI_FTSR_TR2_Pos (2U)
6481 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
6482 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
6483 #define EXTI_FTSR_TR3_Pos (3U)
6484 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
6485 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
6486 #define EXTI_FTSR_TR4_Pos (4U)
6487 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
6488 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
6489 #define EXTI_FTSR_TR5_Pos (5U)
6490 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
6491 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
6492 #define EXTI_FTSR_TR6_Pos (6U)
6493 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
6494 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
6495 #define EXTI_FTSR_TR7_Pos (7U)
6496 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
6497 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
6498 #define EXTI_FTSR_TR8_Pos (8U)
6499 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
6500 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
6501 #define EXTI_FTSR_TR9_Pos (9U)
6502 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
6503 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
6504 #define EXTI_FTSR_TR10_Pos (10U)
6505 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
6506 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
6507 #define EXTI_FTSR_TR11_Pos (11U)
6508 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
6509 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
6510 #define EXTI_FTSR_TR12_Pos (12U)
6511 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
6512 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
6513 #define EXTI_FTSR_TR13_Pos (13U)
6514 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
6515 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
6516 #define EXTI_FTSR_TR14_Pos (14U)
6517 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
6518 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
6519 #define EXTI_FTSR_TR15_Pos (15U)
6520 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
6521 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
6522 #define EXTI_FTSR_TR16_Pos (16U)
6523 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
6524 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
6525 #define EXTI_FTSR_TR17_Pos (17U)
6526 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
6527 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
6528 #define EXTI_FTSR_TR18_Pos (18U)
6529 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
6530 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
6531 #define EXTI_FTSR_TR19_Pos (19U)
6532 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
6533 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
6534 #define EXTI_FTSR_TR20_Pos (20U)
6535 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
6536 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
6537 #define EXTI_FTSR_TR21_Pos (21U)
6538 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
6539 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
6540 #define EXTI_FTSR_TR22_Pos (22U)
6541 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
6542 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
6543
6544 /****************** Bit definition for EXTI_SWIER register ******************/
6545 #define EXTI_SWIER_SWIER0_Pos (0U)
6546 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
6547 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
6548 #define EXTI_SWIER_SWIER1_Pos (1U)
6549 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
6550 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
6551 #define EXTI_SWIER_SWIER2_Pos (2U)
6552 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
6553 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
6554 #define EXTI_SWIER_SWIER3_Pos (3U)
6555 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
6556 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
6557 #define EXTI_SWIER_SWIER4_Pos (4U)
6558 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
6559 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
6560 #define EXTI_SWIER_SWIER5_Pos (5U)
6561 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
6562 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
6563 #define EXTI_SWIER_SWIER6_Pos (6U)
6564 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
6565 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
6566 #define EXTI_SWIER_SWIER7_Pos (7U)
6567 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
6568 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
6569 #define EXTI_SWIER_SWIER8_Pos (8U)
6570 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
6571 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
6572 #define EXTI_SWIER_SWIER9_Pos (9U)
6573 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
6574 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
6575 #define EXTI_SWIER_SWIER10_Pos (10U)
6576 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
6577 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
6578 #define EXTI_SWIER_SWIER11_Pos (11U)
6579 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
6580 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
6581 #define EXTI_SWIER_SWIER12_Pos (12U)
6582 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
6583 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
6584 #define EXTI_SWIER_SWIER13_Pos (13U)
6585 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
6586 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
6587 #define EXTI_SWIER_SWIER14_Pos (14U)
6588 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
6589 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
6590 #define EXTI_SWIER_SWIER15_Pos (15U)
6591 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
6592 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
6593 #define EXTI_SWIER_SWIER16_Pos (16U)
6594 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
6595 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
6596 #define EXTI_SWIER_SWIER17_Pos (17U)
6597 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
6598 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
6599 #define EXTI_SWIER_SWIER18_Pos (18U)
6600 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
6601 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
6602 #define EXTI_SWIER_SWIER19_Pos (19U)
6603 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
6604 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
6605 #define EXTI_SWIER_SWIER20_Pos (20U)
6606 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
6607 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
6608 #define EXTI_SWIER_SWIER21_Pos (21U)
6609 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
6610 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
6611 #define EXTI_SWIER_SWIER22_Pos (22U)
6612 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
6613 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
6614
6615 /******************* Bit definition for EXTI_PR register ********************/
6616 #define EXTI_PR_PR0_Pos (0U)
6617 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
6618 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
6619 #define EXTI_PR_PR1_Pos (1U)
6620 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
6621 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
6622 #define EXTI_PR_PR2_Pos (2U)
6623 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
6624 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
6625 #define EXTI_PR_PR3_Pos (3U)
6626 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
6627 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
6628 #define EXTI_PR_PR4_Pos (4U)
6629 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
6630 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
6631 #define EXTI_PR_PR5_Pos (5U)
6632 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
6633 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
6634 #define EXTI_PR_PR6_Pos (6U)
6635 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
6636 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
6637 #define EXTI_PR_PR7_Pos (7U)
6638 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
6639 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
6640 #define EXTI_PR_PR8_Pos (8U)
6641 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
6642 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
6643 #define EXTI_PR_PR9_Pos (9U)
6644 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
6645 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
6646 #define EXTI_PR_PR10_Pos (10U)
6647 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
6648 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
6649 #define EXTI_PR_PR11_Pos (11U)
6650 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
6651 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
6652 #define EXTI_PR_PR12_Pos (12U)
6653 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
6654 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
6655 #define EXTI_PR_PR13_Pos (13U)
6656 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
6657 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
6658 #define EXTI_PR_PR14_Pos (14U)
6659 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
6660 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
6661 #define EXTI_PR_PR15_Pos (15U)
6662 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
6663 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
6664 #define EXTI_PR_PR16_Pos (16U)
6665 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
6666 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
6667 #define EXTI_PR_PR17_Pos (17U)
6668 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
6669 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
6670 #define EXTI_PR_PR18_Pos (18U)
6671 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
6672 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
6673 #define EXTI_PR_PR19_Pos (19U)
6674 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
6675 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
6676 #define EXTI_PR_PR20_Pos (20U)
6677 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
6678 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
6679 #define EXTI_PR_PR21_Pos (21U)
6680 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
6681 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
6682 #define EXTI_PR_PR22_Pos (22U)
6683 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
6684 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
6685
6686 /******************************************************************************/
6687 /* */
6688 /* FLASH */
6689 /* */
6690 /******************************************************************************/
6691 /******************* Bits definition for FLASH_ACR register *****************/
6692 #define FLASH_ACR_LATENCY_Pos (0U)
6693 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
6694 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6695 #define FLASH_ACR_LATENCY_0WS 0x00000000U
6696 #define FLASH_ACR_LATENCY_1WS 0x00000001U
6697 #define FLASH_ACR_LATENCY_2WS 0x00000002U
6698 #define FLASH_ACR_LATENCY_3WS 0x00000003U
6699 #define FLASH_ACR_LATENCY_4WS 0x00000004U
6700 #define FLASH_ACR_LATENCY_5WS 0x00000005U
6701 #define FLASH_ACR_LATENCY_6WS 0x00000006U
6702 #define FLASH_ACR_LATENCY_7WS 0x00000007U
6703
6704 #define FLASH_ACR_PRFTEN_Pos (8U)
6705 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
6706 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6707 #define FLASH_ACR_ICEN_Pos (9U)
6708 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
6709 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6710 #define FLASH_ACR_DCEN_Pos (10U)
6711 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
6712 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6713 #define FLASH_ACR_ICRST_Pos (11U)
6714 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
6715 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6716 #define FLASH_ACR_DCRST_Pos (12U)
6717 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
6718 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6719 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6720 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
6721 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6722 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6723 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
6724 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6725
6726 /******************* Bits definition for FLASH_SR register ******************/
6727 #define FLASH_SR_EOP_Pos (0U)
6728 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
6729 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
6730 #define FLASH_SR_SOP_Pos (1U)
6731 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
6732 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
6733 #define FLASH_SR_WRPERR_Pos (4U)
6734 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
6735 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6736 #define FLASH_SR_PGAERR_Pos (5U)
6737 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
6738 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6739 #define FLASH_SR_PGPERR_Pos (6U)
6740 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
6741 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6742 #define FLASH_SR_PGSERR_Pos (7U)
6743 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
6744 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6745 #define FLASH_SR_BSY_Pos (16U)
6746 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
6747 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
6748
6749 /******************* Bits definition for FLASH_CR register ******************/
6750 #define FLASH_CR_PG_Pos (0U)
6751 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
6752 #define FLASH_CR_PG FLASH_CR_PG_Msk
6753 #define FLASH_CR_SER_Pos (1U)
6754 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
6755 #define FLASH_CR_SER FLASH_CR_SER_Msk
6756 #define FLASH_CR_MER_Pos (2U)
6757 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
6758 #define FLASH_CR_MER FLASH_CR_MER_Msk
6759 #define FLASH_CR_SNB_Pos (3U)
6760 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
6761 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
6762 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
6763 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
6764 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
6765 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
6766 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
6767 #define FLASH_CR_PSIZE_Pos (8U)
6768 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
6769 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6770 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
6771 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
6772 #define FLASH_CR_STRT_Pos (16U)
6773 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
6774 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
6775 #define FLASH_CR_EOPIE_Pos (24U)
6776 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
6777 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6778 #define FLASH_CR_LOCK_Pos (31U)
6779 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
6780 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6781
6782 /******************* Bits definition for FLASH_OPTCR register ***************/
6783 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
6784 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
6785 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6786 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
6787 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
6788 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6789
6790 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6791 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6792 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
6793 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
6794 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6795 #define FLASH_OPTCR_WDG_SW_Pos (5U)
6796 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
6797 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6798 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
6799 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
6800 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6801 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6802 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
6803 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6804 #define FLASH_OPTCR_RDP_Pos (8U)
6805 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
6806 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6807 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
6808 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
6809 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
6810 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
6811 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
6812 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
6813 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
6814 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
6815 #define FLASH_OPTCR_nWRP_Pos (16U)
6816 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
6817 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6818 #define FLASH_OPTCR_nWRP_0 0x00010000U
6819 #define FLASH_OPTCR_nWRP_1 0x00020000U
6820 #define FLASH_OPTCR_nWRP_2 0x00040000U
6821 #define FLASH_OPTCR_nWRP_3 0x00080000U
6822 #define FLASH_OPTCR_nWRP_4 0x00100000U
6823 #define FLASH_OPTCR_nWRP_5 0x00200000U
6824 #define FLASH_OPTCR_nWRP_6 0x00400000U
6825 #define FLASH_OPTCR_nWRP_7 0x00800000U
6826 #define FLASH_OPTCR_nWRP_8 0x01000000U
6827 #define FLASH_OPTCR_nWRP_9 0x02000000U
6828 #define FLASH_OPTCR_nWRP_10 0x04000000U
6829 #define FLASH_OPTCR_nWRP_11 0x08000000U
6830
6831 /****************** Bits definition for FLASH_OPTCR1 register ***************/
6832 #define FLASH_OPTCR1_nWRP_Pos (16U)
6833 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
6834 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
6835 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
6836 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
6837 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
6838 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
6839 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
6840 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
6841 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
6842 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
6843 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
6844 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
6845 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
6846 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
6847
6848 /******************************************************************************/
6849 /* */
6850 /* Flexible Static Memory Controller */
6851 /* */
6852 /******************************************************************************/
6853 /****************** Bit definition for FSMC_BCR1 register *******************/
6854 #define FSMC_BCR1_MBKEN_Pos (0U)
6855 #define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
6856 #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
6857 #define FSMC_BCR1_MUXEN_Pos (1U)
6858 #define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
6859 #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6860
6861 #define FSMC_BCR1_MTYP_Pos (2U)
6862 #define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
6863 #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6864 #define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
6865 #define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
6866
6867 #define FSMC_BCR1_MWID_Pos (4U)
6868 #define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
6869 #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6870 #define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
6871 #define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
6872
6873 #define FSMC_BCR1_FACCEN_Pos (6U)
6874 #define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
6875 #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
6876 #define FSMC_BCR1_BURSTEN_Pos (8U)
6877 #define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
6878 #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
6879 #define FSMC_BCR1_WAITPOL_Pos (9U)
6880 #define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
6881 #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
6882 #define FSMC_BCR1_WRAPMOD_Pos (10U)
6883 #define FSMC_BCR1_WRAPMOD_Msk (0x1U << FSMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
6884 #define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
6885 #define FSMC_BCR1_WAITCFG_Pos (11U)
6886 #define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
6887 #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
6888 #define FSMC_BCR1_WREN_Pos (12U)
6889 #define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
6890 #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
6891 #define FSMC_BCR1_WAITEN_Pos (13U)
6892 #define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
6893 #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
6894 #define FSMC_BCR1_EXTMOD_Pos (14U)
6895 #define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
6896 #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
6897 #define FSMC_BCR1_ASYNCWAIT_Pos (15U)
6898 #define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
6899 #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
6900 #define FSMC_BCR1_CPSIZE_Pos (16U)
6901 #define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
6902 #define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
6903 #define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
6904 #define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
6905 #define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
6906 #define FSMC_BCR1_CBURSTRW_Pos (19U)
6907 #define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
6908 #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
6909
6910 /****************** Bit definition for FSMC_BCR2 register *******************/
6911 #define FSMC_BCR2_MBKEN_Pos (0U)
6912 #define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
6913 #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
6914 #define FSMC_BCR2_MUXEN_Pos (1U)
6915 #define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
6916 #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6917
6918 #define FSMC_BCR2_MTYP_Pos (2U)
6919 #define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6920 #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6921 #define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6922 #define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
6923
6924 #define FSMC_BCR2_MWID_Pos (4U)
6925 #define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6926 #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6927 #define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6928 #define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
6929
6930 #define FSMC_BCR2_FACCEN_Pos (6U)
6931 #define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
6932 #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
6933 #define FSMC_BCR2_BURSTEN_Pos (8U)
6934 #define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
6935 #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
6936 #define FSMC_BCR2_WAITPOL_Pos (9U)
6937 #define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
6938 #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
6939 #define FSMC_BCR2_WRAPMOD_Pos (10U)
6940 #define FSMC_BCR2_WRAPMOD_Msk (0x1U << FSMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
6941 #define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
6942 #define FSMC_BCR2_WAITCFG_Pos (11U)
6943 #define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
6944 #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
6945 #define FSMC_BCR2_WREN_Pos (12U)
6946 #define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
6947 #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
6948 #define FSMC_BCR2_WAITEN_Pos (13U)
6949 #define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
6950 #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
6951 #define FSMC_BCR2_EXTMOD_Pos (14U)
6952 #define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
6953 #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
6954 #define FSMC_BCR2_ASYNCWAIT_Pos (15U)
6955 #define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
6956 #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
6957 #define FSMC_BCR2_CPSIZE_Pos (16U)
6958 #define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
6959 #define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
6960 #define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
6961 #define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
6962 #define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
6963 #define FSMC_BCR2_CBURSTRW_Pos (19U)
6964 #define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
6965 #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
6966
6967 /****************** Bit definition for FSMC_BCR3 register *******************/
6968 #define FSMC_BCR3_MBKEN_Pos (0U)
6969 #define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
6970 #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
6971 #define FSMC_BCR3_MUXEN_Pos (1U)
6972 #define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
6973 #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6974
6975 #define FSMC_BCR3_MTYP_Pos (2U)
6976 #define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6977 #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6978 #define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6979 #define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
6980
6981 #define FSMC_BCR3_MWID_Pos (4U)
6982 #define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
6983 #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6984 #define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
6985 #define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
6986
6987 #define FSMC_BCR3_FACCEN_Pos (6U)
6988 #define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
6989 #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
6990 #define FSMC_BCR3_BURSTEN_Pos (8U)
6991 #define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
6992 #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
6993 #define FSMC_BCR3_WAITPOL_Pos (9U)
6994 #define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
6995 #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
6996 #define FSMC_BCR3_WRAPMOD_Pos (10U)
6997 #define FSMC_BCR3_WRAPMOD_Msk (0x1U << FSMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
6998 #define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
6999 #define FSMC_BCR3_WAITCFG_Pos (11U)
7000 #define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
7001 #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
7002 #define FSMC_BCR3_WREN_Pos (12U)
7003 #define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
7004 #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
7005 #define FSMC_BCR3_WAITEN_Pos (13U)
7006 #define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
7007 #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
7008 #define FSMC_BCR3_EXTMOD_Pos (14U)
7009 #define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
7010 #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
7011 #define FSMC_BCR3_ASYNCWAIT_Pos (15U)
7012 #define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
7013 #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
7014 #define FSMC_BCR3_CPSIZE_Pos (16U)
7015 #define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
7016 #define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
7017 #define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
7018 #define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
7019 #define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
7020 #define FSMC_BCR3_CBURSTRW_Pos (19U)
7021 #define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
7022 #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
7023
7024 /****************** Bit definition for FSMC_BCR4 register *******************/
7025 #define FSMC_BCR4_MBKEN_Pos (0U)
7026 #define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
7027 #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
7028 #define FSMC_BCR4_MUXEN_Pos (1U)
7029 #define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
7030 #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7031
7032 #define FSMC_BCR4_MTYP_Pos (2U)
7033 #define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
7034 #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7035 #define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
7036 #define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
7037
7038 #define FSMC_BCR4_MWID_Pos (4U)
7039 #define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
7040 #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7041 #define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
7042 #define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
7043
7044 #define FSMC_BCR4_FACCEN_Pos (6U)
7045 #define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
7046 #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
7047 #define FSMC_BCR4_BURSTEN_Pos (8U)
7048 #define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
7049 #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
7050 #define FSMC_BCR4_WAITPOL_Pos (9U)
7051 #define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
7052 #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
7053 #define FSMC_BCR4_WRAPMOD_Pos (10U)
7054 #define FSMC_BCR4_WRAPMOD_Msk (0x1U << FSMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
7055 #define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
7056 #define FSMC_BCR4_WAITCFG_Pos (11U)
7057 #define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
7058 #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
7059 #define FSMC_BCR4_WREN_Pos (12U)
7060 #define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
7061 #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
7062 #define FSMC_BCR4_WAITEN_Pos (13U)
7063 #define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
7064 #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
7065 #define FSMC_BCR4_EXTMOD_Pos (14U)
7066 #define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
7067 #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
7068 #define FSMC_BCR4_ASYNCWAIT_Pos (15U)
7069 #define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
7070 #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
7071 #define FSMC_BCR4_CPSIZE_Pos (16U)
7072 #define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
7073 #define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
7074 #define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
7075 #define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
7076 #define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
7077 #define FSMC_BCR4_CBURSTRW_Pos (19U)
7078 #define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
7079 #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
7080
7081 /****************** Bit definition for FSMC_BTR1 register ******************/
7082 #define FSMC_BTR1_ADDSET_Pos (0U)
7083 #define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7084 #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7085 #define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7086 #define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7087 #define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7088 #define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
7089
7090 #define FSMC_BTR1_ADDHLD_Pos (4U)
7091 #define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7092 #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7093 #define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
7094 #define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
7095 #define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
7096 #define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
7097
7098 #define FSMC_BTR1_DATAST_Pos (8U)
7099 #define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
7100 #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7101 #define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
7102 #define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
7103 #define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
7104 #define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
7105 #define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
7106 #define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
7107 #define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
7108 #define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
7109
7110 #define FSMC_BTR1_BUSTURN_Pos (16U)
7111 #define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7112 #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7113 #define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
7114 #define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
7115 #define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
7116 #define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
7117
7118 #define FSMC_BTR1_CLKDIV_Pos (20U)
7119 #define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
7120 #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7121 #define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
7122 #define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
7123 #define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
7124 #define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
7125
7126 #define FSMC_BTR1_DATLAT_Pos (24U)
7127 #define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
7128 #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7129 #define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
7130 #define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
7131 #define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
7132 #define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
7133
7134 #define FSMC_BTR1_ACCMOD_Pos (28U)
7135 #define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
7136 #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7137 #define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
7138 #define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
7139
7140 /****************** Bit definition for FSMC_BTR2 register *******************/
7141 #define FSMC_BTR2_ADDSET_Pos (0U)
7142 #define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
7143 #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7144 #define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
7145 #define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
7146 #define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
7147 #define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
7148
7149 #define FSMC_BTR2_ADDHLD_Pos (4U)
7150 #define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7151 #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7152 #define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
7153 #define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
7154 #define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
7155 #define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7156
7157 #define FSMC_BTR2_DATAST_Pos (8U)
7158 #define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
7159 #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7160 #define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
7161 #define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
7162 #define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
7163 #define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
7164 #define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
7165 #define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
7166 #define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
7167 #define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
7168
7169 #define FSMC_BTR2_BUSTURN_Pos (16U)
7170 #define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7171 #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7172 #define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
7173 #define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
7174 #define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
7175 #define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
7176
7177 #define FSMC_BTR2_CLKDIV_Pos (20U)
7178 #define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
7179 #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7180 #define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
7181 #define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
7182 #define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
7183 #define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
7184
7185 #define FSMC_BTR2_DATLAT_Pos (24U)
7186 #define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
7187 #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7188 #define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
7189 #define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
7190 #define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
7191 #define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
7192
7193 #define FSMC_BTR2_ACCMOD_Pos (28U)
7194 #define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
7195 #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7196 #define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
7197 #define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
7198
7199 /******************* Bit definition for FSMC_BTR3 register *******************/
7200 #define FSMC_BTR3_ADDSET_Pos (0U)
7201 #define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7202 #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7203 #define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7204 #define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7205 #define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7206 #define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7207
7208 #define FSMC_BTR3_ADDHLD_Pos (4U)
7209 #define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7210 #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7211 #define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7212 #define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7213 #define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7214 #define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
7215
7216 #define FSMC_BTR3_DATAST_Pos (8U)
7217 #define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
7218 #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7219 #define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
7220 #define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
7221 #define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
7222 #define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
7223 #define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
7224 #define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
7225 #define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
7226 #define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
7227
7228 #define FSMC_BTR3_BUSTURN_Pos (16U)
7229 #define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7230 #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7231 #define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
7232 #define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
7233 #define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
7234 #define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
7235
7236 #define FSMC_BTR3_CLKDIV_Pos (20U)
7237 #define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
7238 #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7239 #define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
7240 #define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
7241 #define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
7242 #define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
7243
7244 #define FSMC_BTR3_DATLAT_Pos (24U)
7245 #define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
7246 #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7247 #define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
7248 #define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
7249 #define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
7250 #define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
7251
7252 #define FSMC_BTR3_ACCMOD_Pos (28U)
7253 #define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
7254 #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7255 #define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
7256 #define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
7257
7258 /****************** Bit definition for FSMC_BTR4 register *******************/
7259 #define FSMC_BTR4_ADDSET_Pos (0U)
7260 #define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
7261 #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7262 #define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
7263 #define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
7264 #define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
7265 #define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7266
7267 #define FSMC_BTR4_ADDHLD_Pos (4U)
7268 #define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7269 #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7270 #define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
7271 #define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
7272 #define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
7273 #define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
7274
7275 #define FSMC_BTR4_DATAST_Pos (8U)
7276 #define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
7277 #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7278 #define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
7279 #define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
7280 #define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
7281 #define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
7282 #define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
7283 #define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
7284 #define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
7285 #define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
7286
7287 #define FSMC_BTR4_BUSTURN_Pos (16U)
7288 #define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7289 #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7290 #define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
7291 #define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
7292 #define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
7293 #define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
7294
7295 #define FSMC_BTR4_CLKDIV_Pos (20U)
7296 #define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
7297 #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7298 #define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
7299 #define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
7300 #define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
7301 #define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
7302
7303 #define FSMC_BTR4_DATLAT_Pos (24U)
7304 #define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
7305 #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7306 #define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
7307 #define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
7308 #define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
7309 #define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
7310
7311 #define FSMC_BTR4_ACCMOD_Pos (28U)
7312 #define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
7313 #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7314 #define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
7315 #define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
7316
7317 /****************** Bit definition for FSMC_BWTR1 register ******************/
7318 #define FSMC_BWTR1_ADDSET_Pos (0U)
7319 #define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
7320 #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7321 #define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
7322 #define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
7323 #define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
7324 #define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
7325
7326 #define FSMC_BWTR1_ADDHLD_Pos (4U)
7327 #define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7328 #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7329 #define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
7330 #define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
7331 #define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
7332 #define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
7333
7334 #define FSMC_BWTR1_DATAST_Pos (8U)
7335 #define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
7336 #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7337 #define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
7338 #define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
7339 #define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
7340 #define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
7341 #define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
7342 #define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
7343 #define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
7344 #define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
7345
7346 #define FSMC_BWTR1_BUSTURN_Pos (16U)
7347 #define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7348 #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7349 #define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
7350 #define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
7351 #define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
7352 #define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
7353
7354 #define FSMC_BWTR1_ACCMOD_Pos (28U)
7355 #define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
7356 #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7357 #define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
7358 #define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
7359
7360 /****************** Bit definition for FSMC_BWTR2 register ******************/
7361 #define FSMC_BWTR2_ADDSET_Pos (0U)
7362 #define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7363 #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7364 #define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7365 #define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7366 #define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7367 #define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7368
7369 #define FSMC_BWTR2_ADDHLD_Pos (4U)
7370 #define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7371 #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7372 #define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
7373 #define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
7374 #define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
7375 #define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
7376
7377 #define FSMC_BWTR2_DATAST_Pos (8U)
7378 #define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
7379 #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7380 #define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
7381 #define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
7382 #define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
7383 #define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
7384 #define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
7385 #define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
7386 #define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
7387 #define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
7388
7389 #define FSMC_BWTR2_BUSTURN_Pos (16U)
7390 #define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7391 #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7392 #define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
7393 #define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
7394 #define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
7395 #define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
7396
7397 #define FSMC_BWTR2_ACCMOD_Pos (28U)
7398 #define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
7399 #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7400 #define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
7401 #define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
7402
7403 /****************** Bit definition for FSMC_BWTR3 register ******************/
7404 #define FSMC_BWTR3_ADDSET_Pos (0U)
7405 #define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
7406 #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7407 #define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
7408 #define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
7409 #define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
7410 #define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7411
7412 #define FSMC_BWTR3_ADDHLD_Pos (4U)
7413 #define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7414 #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7415 #define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
7416 #define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
7417 #define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
7418 #define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
7419
7420 #define FSMC_BWTR3_DATAST_Pos (8U)
7421 #define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
7422 #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7423 #define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
7424 #define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
7425 #define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
7426 #define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
7427 #define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
7428 #define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
7429 #define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
7430 #define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
7431
7432 #define FSMC_BWTR3_BUSTURN_Pos (16U)
7433 #define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7434 #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7435 #define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
7436 #define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
7437 #define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
7438 #define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
7439
7440 #define FSMC_BWTR3_ACCMOD_Pos (28U)
7441 #define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
7442 #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7443 #define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
7444 #define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
7445
7446 /****************** Bit definition for FSMC_BWTR4 register ******************/
7447 #define FSMC_BWTR4_ADDSET_Pos (0U)
7448 #define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
7449 #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7450 #define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
7451 #define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
7452 #define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
7453 #define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
7454
7455 #define FSMC_BWTR4_ADDHLD_Pos (4U)
7456 #define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7457 #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7458 #define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
7459 #define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
7460 #define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
7461 #define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
7462
7463 #define FSMC_BWTR4_DATAST_Pos (8U)
7464 #define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
7465 #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7466 #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
7467 #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
7468 #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
7469 #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
7470 #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
7471 #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
7472 #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
7473 #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
7474
7475 #define FSMC_BWTR4_BUSTURN_Pos (16U)
7476 #define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7477 #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7478 #define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
7479 #define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
7480 #define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
7481 #define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
7482
7483 #define FSMC_BWTR4_ACCMOD_Pos (28U)
7484 #define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
7485 #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7486 #define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
7487 #define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
7488
7489 /****************** Bit definition for FSMC_PCR2 register *******************/
7490 #define FSMC_PCR2_PWAITEN_Pos (1U)
7491 #define FSMC_PCR2_PWAITEN_Msk (0x1U << FSMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
7492 #define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
7493 #define FSMC_PCR2_PBKEN_Pos (2U)
7494 #define FSMC_PCR2_PBKEN_Msk (0x1U << FSMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
7495 #define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7496 #define FSMC_PCR2_PTYP_Pos (3U)
7497 #define FSMC_PCR2_PTYP_Msk (0x1U << FSMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
7498 #define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk /*!<Memory type */
7499
7500 #define FSMC_PCR2_PWID_Pos (4U)
7501 #define FSMC_PCR2_PWID_Msk (0x3U << FSMC_PCR2_PWID_Pos) /*!< 0x00000030 */
7502 #define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7503 #define FSMC_PCR2_PWID_0 (0x1U << FSMC_PCR2_PWID_Pos) /*!< 0x00000010 */
7504 #define FSMC_PCR2_PWID_1 (0x2U << FSMC_PCR2_PWID_Pos) /*!< 0x00000020 */
7505
7506 #define FSMC_PCR2_ECCEN_Pos (6U)
7507 #define FSMC_PCR2_ECCEN_Msk (0x1U << FSMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
7508 #define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
7509
7510 #define FSMC_PCR2_TCLR_Pos (9U)
7511 #define FSMC_PCR2_TCLR_Msk (0xFU << FSMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
7512 #define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7513 #define FSMC_PCR2_TCLR_0 (0x1U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
7514 #define FSMC_PCR2_TCLR_1 (0x2U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
7515 #define FSMC_PCR2_TCLR_2 (0x4U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
7516 #define FSMC_PCR2_TCLR_3 (0x8U << FSMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
7517
7518 #define FSMC_PCR2_TAR_Pos (13U)
7519 #define FSMC_PCR2_TAR_Msk (0xFU << FSMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
7520 #define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7521 #define FSMC_PCR2_TAR_0 (0x1U << FSMC_PCR2_TAR_Pos) /*!< 0x00002000 */
7522 #define FSMC_PCR2_TAR_1 (0x2U << FSMC_PCR2_TAR_Pos) /*!< 0x00004000 */
7523 #define FSMC_PCR2_TAR_2 (0x4U << FSMC_PCR2_TAR_Pos) /*!< 0x00008000 */
7524 #define FSMC_PCR2_TAR_3 (0x8U << FSMC_PCR2_TAR_Pos) /*!< 0x00010000 */
7525
7526 #define FSMC_PCR2_ECCPS_Pos (17U)
7527 #define FSMC_PCR2_ECCPS_Msk (0x7U << FSMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
7528 #define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
7529 #define FSMC_PCR2_ECCPS_0 (0x1U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
7530 #define FSMC_PCR2_ECCPS_1 (0x2U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
7531 #define FSMC_PCR2_ECCPS_2 (0x4U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
7532
7533 /****************** Bit definition for FSMC_PCR3 register *******************/
7534 #define FSMC_PCR3_PWAITEN_Pos (1U)
7535 #define FSMC_PCR3_PWAITEN_Msk (0x1U << FSMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
7536 #define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
7537 #define FSMC_PCR3_PBKEN_Pos (2U)
7538 #define FSMC_PCR3_PBKEN_Msk (0x1U << FSMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
7539 #define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7540 #define FSMC_PCR3_PTYP_Pos (3U)
7541 #define FSMC_PCR3_PTYP_Msk (0x1U << FSMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
7542 #define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk /*!<Memory type */
7543
7544 #define FSMC_PCR3_PWID_Pos (4U)
7545 #define FSMC_PCR3_PWID_Msk (0x3U << FSMC_PCR3_PWID_Pos) /*!< 0x00000030 */
7546 #define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7547 #define FSMC_PCR3_PWID_0 (0x1U << FSMC_PCR3_PWID_Pos) /*!< 0x00000010 */
7548 #define FSMC_PCR3_PWID_1 (0x2U << FSMC_PCR3_PWID_Pos) /*!< 0x00000020 */
7549
7550 #define FSMC_PCR3_ECCEN_Pos (6U)
7551 #define FSMC_PCR3_ECCEN_Msk (0x1U << FSMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
7552 #define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
7553
7554 #define FSMC_PCR3_TCLR_Pos (9U)
7555 #define FSMC_PCR3_TCLR_Msk (0xFU << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7556 #define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7557 #define FSMC_PCR3_TCLR_0 (0x1U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7558 #define FSMC_PCR3_TCLR_1 (0x2U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7559 #define FSMC_PCR3_TCLR_2 (0x4U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7560 #define FSMC_PCR3_TCLR_3 (0x8U << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
7561
7562 #define FSMC_PCR3_TAR_Pos (13U)
7563 #define FSMC_PCR3_TAR_Msk (0xFU << FSMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
7564 #define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7565 #define FSMC_PCR3_TAR_0 (0x1U << FSMC_PCR3_TAR_Pos) /*!< 0x00002000 */
7566 #define FSMC_PCR3_TAR_1 (0x2U << FSMC_PCR3_TAR_Pos) /*!< 0x00004000 */
7567 #define FSMC_PCR3_TAR_2 (0x4U << FSMC_PCR3_TAR_Pos) /*!< 0x00008000 */
7568 #define FSMC_PCR3_TAR_3 (0x8U << FSMC_PCR3_TAR_Pos) /*!< 0x00010000 */
7569
7570 #define FSMC_PCR3_ECCPS_Pos (17U)
7571 #define FSMC_PCR3_ECCPS_Msk (0x7U << FSMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
7572 #define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
7573 #define FSMC_PCR3_ECCPS_0 (0x1U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
7574 #define FSMC_PCR3_ECCPS_1 (0x2U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
7575 #define FSMC_PCR3_ECCPS_2 (0x4U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
7576
7577 /****************** Bit definition for FSMC_PCR4 register *******************/
7578 #define FSMC_PCR4_PWAITEN_Pos (1U)
7579 #define FSMC_PCR4_PWAITEN_Msk (0x1U << FSMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
7580 #define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
7581 #define FSMC_PCR4_PBKEN_Pos (2U)
7582 #define FSMC_PCR4_PBKEN_Msk (0x1U << FSMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
7583 #define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7584 #define FSMC_PCR4_PTYP_Pos (3U)
7585 #define FSMC_PCR4_PTYP_Msk (0x1U << FSMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
7586 #define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk /*!<Memory type */
7587
7588 #define FSMC_PCR4_PWID_Pos (4U)
7589 #define FSMC_PCR4_PWID_Msk (0x3U << FSMC_PCR4_PWID_Pos) /*!< 0x00000030 */
7590 #define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7591 #define FSMC_PCR4_PWID_0 (0x1U << FSMC_PCR4_PWID_Pos) /*!< 0x00000010 */
7592 #define FSMC_PCR4_PWID_1 (0x2U << FSMC_PCR4_PWID_Pos) /*!< 0x00000020 */
7593
7594 #define FSMC_PCR4_ECCEN_Pos (6U)
7595 #define FSMC_PCR4_ECCEN_Msk (0x1U << FSMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
7596 #define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
7597
7598 #define FSMC_PCR4_TCLR_Pos (9U)
7599 #define FSMC_PCR4_TCLR_Msk (0xFU << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
7600 #define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7601 #define FSMC_PCR4_TCLR_0 (0x1U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
7602 #define FSMC_PCR4_TCLR_1 (0x2U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
7603 #define FSMC_PCR4_TCLR_2 (0x4U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
7604 #define FSMC_PCR4_TCLR_3 (0x8U << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7605
7606 #define FSMC_PCR4_TAR_Pos (13U)
7607 #define FSMC_PCR4_TAR_Msk (0xFU << FSMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
7608 #define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7609 #define FSMC_PCR4_TAR_0 (0x1U << FSMC_PCR4_TAR_Pos) /*!< 0x00002000 */
7610 #define FSMC_PCR4_TAR_1 (0x2U << FSMC_PCR4_TAR_Pos) /*!< 0x00004000 */
7611 #define FSMC_PCR4_TAR_2 (0x4U << FSMC_PCR4_TAR_Pos) /*!< 0x00008000 */
7612 #define FSMC_PCR4_TAR_3 (0x8U << FSMC_PCR4_TAR_Pos) /*!< 0x00010000 */
7613
7614 #define FSMC_PCR4_ECCPS_Pos (17U)
7615 #define FSMC_PCR4_ECCPS_Msk (0x7U << FSMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
7616 #define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
7617 #define FSMC_PCR4_ECCPS_0 (0x1U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
7618 #define FSMC_PCR4_ECCPS_1 (0x2U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
7619 #define FSMC_PCR4_ECCPS_2 (0x4U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
7620
7621 /******************* Bit definition for FSMC_SR2 register *******************/
7622 #define FSMC_SR2_IRS_Pos (0U)
7623 #define FSMC_SR2_IRS_Msk (0x1U << FSMC_SR2_IRS_Pos) /*!< 0x00000001 */
7624 #define FSMC_SR2_IRS FSMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
7625 #define FSMC_SR2_ILS_Pos (1U)
7626 #define FSMC_SR2_ILS_Msk (0x1U << FSMC_SR2_ILS_Pos) /*!< 0x00000002 */
7627 #define FSMC_SR2_ILS FSMC_SR2_ILS_Msk /*!<Interrupt Level status */
7628 #define FSMC_SR2_IFS_Pos (2U)
7629 #define FSMC_SR2_IFS_Msk (0x1U << FSMC_SR2_IFS_Pos) /*!< 0x00000004 */
7630 #define FSMC_SR2_IFS FSMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
7631 #define FSMC_SR2_IREN_Pos (3U)
7632 #define FSMC_SR2_IREN_Msk (0x1U << FSMC_SR2_IREN_Pos) /*!< 0x00000008 */
7633 #define FSMC_SR2_IREN FSMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7634 #define FSMC_SR2_ILEN_Pos (4U)
7635 #define FSMC_SR2_ILEN_Msk (0x1U << FSMC_SR2_ILEN_Pos) /*!< 0x00000010 */
7636 #define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7637 #define FSMC_SR2_IFEN_Pos (5U)
7638 #define FSMC_SR2_IFEN_Msk (0x1U << FSMC_SR2_IFEN_Pos) /*!< 0x00000020 */
7639 #define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7640 #define FSMC_SR2_FEMPT_Pos (6U)
7641 #define FSMC_SR2_FEMPT_Msk (0x1U << FSMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
7642 #define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk /*!<FIFO empty */
7643
7644 /******************* Bit definition for FSMC_SR3 register *******************/
7645 #define FSMC_SR3_IRS_Pos (0U)
7646 #define FSMC_SR3_IRS_Msk (0x1U << FSMC_SR3_IRS_Pos) /*!< 0x00000001 */
7647 #define FSMC_SR3_IRS FSMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
7648 #define FSMC_SR3_ILS_Pos (1U)
7649 #define FSMC_SR3_ILS_Msk (0x1U << FSMC_SR3_ILS_Pos) /*!< 0x00000002 */
7650 #define FSMC_SR3_ILS FSMC_SR3_ILS_Msk /*!<Interrupt Level status */
7651 #define FSMC_SR3_IFS_Pos (2U)
7652 #define FSMC_SR3_IFS_Msk (0x1U << FSMC_SR3_IFS_Pos) /*!< 0x00000004 */
7653 #define FSMC_SR3_IFS FSMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
7654 #define FSMC_SR3_IREN_Pos (3U)
7655 #define FSMC_SR3_IREN_Msk (0x1U << FSMC_SR3_IREN_Pos) /*!< 0x00000008 */
7656 #define FSMC_SR3_IREN FSMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7657 #define FSMC_SR3_ILEN_Pos (4U)
7658 #define FSMC_SR3_ILEN_Msk (0x1U << FSMC_SR3_ILEN_Pos) /*!< 0x00000010 */
7659 #define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7660 #define FSMC_SR3_IFEN_Pos (5U)
7661 #define FSMC_SR3_IFEN_Msk (0x1U << FSMC_SR3_IFEN_Pos) /*!< 0x00000020 */
7662 #define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7663 #define FSMC_SR3_FEMPT_Pos (6U)
7664 #define FSMC_SR3_FEMPT_Msk (0x1U << FSMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
7665 #define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk /*!<FIFO empty */
7666
7667 /******************* Bit definition for FSMC_SR4 register *******************/
7668 #define FSMC_SR4_IRS_Pos (0U)
7669 #define FSMC_SR4_IRS_Msk (0x1U << FSMC_SR4_IRS_Pos) /*!< 0x00000001 */
7670 #define FSMC_SR4_IRS FSMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
7671 #define FSMC_SR4_ILS_Pos (1U)
7672 #define FSMC_SR4_ILS_Msk (0x1U << FSMC_SR4_ILS_Pos) /*!< 0x00000002 */
7673 #define FSMC_SR4_ILS FSMC_SR4_ILS_Msk /*!<Interrupt Level status */
7674 #define FSMC_SR4_IFS_Pos (2U)
7675 #define FSMC_SR4_IFS_Msk (0x1U << FSMC_SR4_IFS_Pos) /*!< 0x00000004 */
7676 #define FSMC_SR4_IFS FSMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
7677 #define FSMC_SR4_IREN_Pos (3U)
7678 #define FSMC_SR4_IREN_Msk (0x1U << FSMC_SR4_IREN_Pos) /*!< 0x00000008 */
7679 #define FSMC_SR4_IREN FSMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7680 #define FSMC_SR4_ILEN_Pos (4U)
7681 #define FSMC_SR4_ILEN_Msk (0x1U << FSMC_SR4_ILEN_Pos) /*!< 0x00000010 */
7682 #define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7683 #define FSMC_SR4_IFEN_Pos (5U)
7684 #define FSMC_SR4_IFEN_Msk (0x1U << FSMC_SR4_IFEN_Pos) /*!< 0x00000020 */
7685 #define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7686 #define FSMC_SR4_FEMPT_Pos (6U)
7687 #define FSMC_SR4_FEMPT_Msk (0x1U << FSMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
7688 #define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk /*!<FIFO empty */
7689
7690 /****************** Bit definition for FSMC_PMEM2 register ******************/
7691 #define FSMC_PMEM2_MEMSET2_Pos (0U)
7692 #define FSMC_PMEM2_MEMSET2_Msk (0xFFU << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
7693 #define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
7694 #define FSMC_PMEM2_MEMSET2_0 (0x01U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
7695 #define FSMC_PMEM2_MEMSET2_1 (0x02U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
7696 #define FSMC_PMEM2_MEMSET2_2 (0x04U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
7697 #define FSMC_PMEM2_MEMSET2_3 (0x08U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
7698 #define FSMC_PMEM2_MEMSET2_4 (0x10U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
7699 #define FSMC_PMEM2_MEMSET2_5 (0x20U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
7700 #define FSMC_PMEM2_MEMSET2_6 (0x40U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
7701 #define FSMC_PMEM2_MEMSET2_7 (0x80U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
7702
7703 #define FSMC_PMEM2_MEMWAIT2_Pos (8U)
7704 #define FSMC_PMEM2_MEMWAIT2_Msk (0xFFU << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
7705 #define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
7706 #define FSMC_PMEM2_MEMWAIT2_0 (0x01U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
7707 #define FSMC_PMEM2_MEMWAIT2_1 (0x02U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
7708 #define FSMC_PMEM2_MEMWAIT2_2 (0x04U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
7709 #define FSMC_PMEM2_MEMWAIT2_3 (0x08U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
7710 #define FSMC_PMEM2_MEMWAIT2_4 (0x10U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
7711 #define FSMC_PMEM2_MEMWAIT2_5 (0x20U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
7712 #define FSMC_PMEM2_MEMWAIT2_6 (0x40U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
7713 #define FSMC_PMEM2_MEMWAIT2_7 (0x80U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
7714
7715 #define FSMC_PMEM2_MEMHOLD2_Pos (16U)
7716 #define FSMC_PMEM2_MEMHOLD2_Msk (0xFFU << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
7717 #define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
7718 #define FSMC_PMEM2_MEMHOLD2_0 (0x01U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
7719 #define FSMC_PMEM2_MEMHOLD2_1 (0x02U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
7720 #define FSMC_PMEM2_MEMHOLD2_2 (0x04U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
7721 #define FSMC_PMEM2_MEMHOLD2_3 (0x08U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
7722 #define FSMC_PMEM2_MEMHOLD2_4 (0x10U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
7723 #define FSMC_PMEM2_MEMHOLD2_5 (0x20U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
7724 #define FSMC_PMEM2_MEMHOLD2_6 (0x40U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
7725 #define FSMC_PMEM2_MEMHOLD2_7 (0x80U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
7726
7727 #define FSMC_PMEM2_MEMHIZ2_Pos (24U)
7728 #define FSMC_PMEM2_MEMHIZ2_Msk (0xFFU << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
7729 #define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
7730 #define FSMC_PMEM2_MEMHIZ2_0 (0x01U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
7731 #define FSMC_PMEM2_MEMHIZ2_1 (0x02U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
7732 #define FSMC_PMEM2_MEMHIZ2_2 (0x04U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
7733 #define FSMC_PMEM2_MEMHIZ2_3 (0x08U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
7734 #define FSMC_PMEM2_MEMHIZ2_4 (0x10U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
7735 #define FSMC_PMEM2_MEMHIZ2_5 (0x20U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
7736 #define FSMC_PMEM2_MEMHIZ2_6 (0x40U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
7737 #define FSMC_PMEM2_MEMHIZ2_7 (0x80U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
7738
7739 /****************** Bit definition for FSMC_PMEM3 register ******************/
7740 #define FSMC_PMEM3_MEMSET3_Pos (0U)
7741 #define FSMC_PMEM3_MEMSET3_Msk (0xFFU << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
7742 #define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
7743 #define FSMC_PMEM3_MEMSET3_0 (0x01U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
7744 #define FSMC_PMEM3_MEMSET3_1 (0x02U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
7745 #define FSMC_PMEM3_MEMSET3_2 (0x04U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
7746 #define FSMC_PMEM3_MEMSET3_3 (0x08U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
7747 #define FSMC_PMEM3_MEMSET3_4 (0x10U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
7748 #define FSMC_PMEM3_MEMSET3_5 (0x20U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
7749 #define FSMC_PMEM3_MEMSET3_6 (0x40U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
7750 #define FSMC_PMEM3_MEMSET3_7 (0x80U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
7751
7752 #define FSMC_PMEM3_MEMWAIT3_Pos (8U)
7753 #define FSMC_PMEM3_MEMWAIT3_Msk (0xFFU << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
7754 #define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
7755 #define FSMC_PMEM3_MEMWAIT3_0 (0x01U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
7756 #define FSMC_PMEM3_MEMWAIT3_1 (0x02U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
7757 #define FSMC_PMEM3_MEMWAIT3_2 (0x04U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
7758 #define FSMC_PMEM3_MEMWAIT3_3 (0x08U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
7759 #define FSMC_PMEM3_MEMWAIT3_4 (0x10U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
7760 #define FSMC_PMEM3_MEMWAIT3_5 (0x20U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
7761 #define FSMC_PMEM3_MEMWAIT3_6 (0x40U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
7762 #define FSMC_PMEM3_MEMWAIT3_7 (0x80U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
7763
7764 #define FSMC_PMEM3_MEMHOLD3_Pos (16U)
7765 #define FSMC_PMEM3_MEMHOLD3_Msk (0xFFU << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
7766 #define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
7767 #define FSMC_PMEM3_MEMHOLD3_0 (0x01U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
7768 #define FSMC_PMEM3_MEMHOLD3_1 (0x02U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
7769 #define FSMC_PMEM3_MEMHOLD3_2 (0x04U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
7770 #define FSMC_PMEM3_MEMHOLD3_3 (0x08U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
7771 #define FSMC_PMEM3_MEMHOLD3_4 (0x10U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
7772 #define FSMC_PMEM3_MEMHOLD3_5 (0x20U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
7773 #define FSMC_PMEM3_MEMHOLD3_6 (0x40U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
7774 #define FSMC_PMEM3_MEMHOLD3_7 (0x80U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
7775
7776 #define FSMC_PMEM3_MEMHIZ3_Pos (24U)
7777 #define FSMC_PMEM3_MEMHIZ3_Msk (0xFFU << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
7778 #define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
7779 #define FSMC_PMEM3_MEMHIZ3_0 (0x01U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
7780 #define FSMC_PMEM3_MEMHIZ3_1 (0x02U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
7781 #define FSMC_PMEM3_MEMHIZ3_2 (0x04U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
7782 #define FSMC_PMEM3_MEMHIZ3_3 (0x08U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
7783 #define FSMC_PMEM3_MEMHIZ3_4 (0x10U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
7784 #define FSMC_PMEM3_MEMHIZ3_5 (0x20U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
7785 #define FSMC_PMEM3_MEMHIZ3_6 (0x40U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
7786 #define FSMC_PMEM3_MEMHIZ3_7 (0x80U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
7787
7788 /****************** Bit definition for FSMC_PMEM4 register ******************/
7789 #define FSMC_PMEM4_MEMSET4_Pos (0U)
7790 #define FSMC_PMEM4_MEMSET4_Msk (0xFFU << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
7791 #define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
7792 #define FSMC_PMEM4_MEMSET4_0 (0x01U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
7793 #define FSMC_PMEM4_MEMSET4_1 (0x02U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
7794 #define FSMC_PMEM4_MEMSET4_2 (0x04U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
7795 #define FSMC_PMEM4_MEMSET4_3 (0x08U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
7796 #define FSMC_PMEM4_MEMSET4_4 (0x10U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
7797 #define FSMC_PMEM4_MEMSET4_5 (0x20U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
7798 #define FSMC_PMEM4_MEMSET4_6 (0x40U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
7799 #define FSMC_PMEM4_MEMSET4_7 (0x80U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
7800
7801 #define FSMC_PMEM4_MEMWAIT4_Pos (8U)
7802 #define FSMC_PMEM4_MEMWAIT4_Msk (0xFFU << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
7803 #define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
7804 #define FSMC_PMEM4_MEMWAIT4_0 (0x01U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
7805 #define FSMC_PMEM4_MEMWAIT4_1 (0x02U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
7806 #define FSMC_PMEM4_MEMWAIT4_2 (0x04U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
7807 #define FSMC_PMEM4_MEMWAIT4_3 (0x08U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
7808 #define FSMC_PMEM4_MEMWAIT4_4 (0x10U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
7809 #define FSMC_PMEM4_MEMWAIT4_5 (0x20U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
7810 #define FSMC_PMEM4_MEMWAIT4_6 (0x40U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
7811 #define FSMC_PMEM4_MEMWAIT4_7 (0x80U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
7812
7813 #define FSMC_PMEM4_MEMHOLD4_Pos (16U)
7814 #define FSMC_PMEM4_MEMHOLD4_Msk (0xFFU << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
7815 #define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
7816 #define FSMC_PMEM4_MEMHOLD4_0 (0x01U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
7817 #define FSMC_PMEM4_MEMHOLD4_1 (0x02U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
7818 #define FSMC_PMEM4_MEMHOLD4_2 (0x04U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
7819 #define FSMC_PMEM4_MEMHOLD4_3 (0x08U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
7820 #define FSMC_PMEM4_MEMHOLD4_4 (0x10U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
7821 #define FSMC_PMEM4_MEMHOLD4_5 (0x20U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
7822 #define FSMC_PMEM4_MEMHOLD4_6 (0x40U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
7823 #define FSMC_PMEM4_MEMHOLD4_7 (0x80U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
7824
7825 #define FSMC_PMEM4_MEMHIZ4_Pos (24U)
7826 #define FSMC_PMEM4_MEMHIZ4_Msk (0xFFU << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
7827 #define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
7828 #define FSMC_PMEM4_MEMHIZ4_0 (0x01U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
7829 #define FSMC_PMEM4_MEMHIZ4_1 (0x02U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
7830 #define FSMC_PMEM4_MEMHIZ4_2 (0x04U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
7831 #define FSMC_PMEM4_MEMHIZ4_3 (0x08U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
7832 #define FSMC_PMEM4_MEMHIZ4_4 (0x10U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
7833 #define FSMC_PMEM4_MEMHIZ4_5 (0x20U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
7834 #define FSMC_PMEM4_MEMHIZ4_6 (0x40U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
7835 #define FSMC_PMEM4_MEMHIZ4_7 (0x80U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
7836
7837 /****************** Bit definition for FSMC_PATT2 register ******************/
7838 #define FSMC_PATT2_ATTSET2_Pos (0U)
7839 #define FSMC_PATT2_ATTSET2_Msk (0xFFU << FSMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
7840 #define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
7841 #define FSMC_PATT2_ATTSET2_0 (0x01U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
7842 #define FSMC_PATT2_ATTSET2_1 (0x02U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
7843 #define FSMC_PATT2_ATTSET2_2 (0x04U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
7844 #define FSMC_PATT2_ATTSET2_3 (0x08U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
7845 #define FSMC_PATT2_ATTSET2_4 (0x10U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
7846 #define FSMC_PATT2_ATTSET2_5 (0x20U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
7847 #define FSMC_PATT2_ATTSET2_6 (0x40U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
7848 #define FSMC_PATT2_ATTSET2_7 (0x80U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
7849
7850 #define FSMC_PATT2_ATTWAIT2_Pos (8U)
7851 #define FSMC_PATT2_ATTWAIT2_Msk (0xFFU << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
7852 #define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
7853 #define FSMC_PATT2_ATTWAIT2_0 (0x01U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
7854 #define FSMC_PATT2_ATTWAIT2_1 (0x02U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
7855 #define FSMC_PATT2_ATTWAIT2_2 (0x04U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
7856 #define FSMC_PATT2_ATTWAIT2_3 (0x08U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
7857 #define FSMC_PATT2_ATTWAIT2_4 (0x10U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
7858 #define FSMC_PATT2_ATTWAIT2_5 (0x20U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
7859 #define FSMC_PATT2_ATTWAIT2_6 (0x40U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
7860 #define FSMC_PATT2_ATTWAIT2_7 (0x80U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
7861
7862 #define FSMC_PATT2_ATTHOLD2_Pos (16U)
7863 #define FSMC_PATT2_ATTHOLD2_Msk (0xFFU << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
7864 #define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
7865 #define FSMC_PATT2_ATTHOLD2_0 (0x01U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
7866 #define FSMC_PATT2_ATTHOLD2_1 (0x02U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
7867 #define FSMC_PATT2_ATTHOLD2_2 (0x04U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
7868 #define FSMC_PATT2_ATTHOLD2_3 (0x08U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
7869 #define FSMC_PATT2_ATTHOLD2_4 (0x10U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
7870 #define FSMC_PATT2_ATTHOLD2_5 (0x20U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
7871 #define FSMC_PATT2_ATTHOLD2_6 (0x40U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
7872 #define FSMC_PATT2_ATTHOLD2_7 (0x80U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
7873
7874 #define FSMC_PATT2_ATTHIZ2_Pos (24U)
7875 #define FSMC_PATT2_ATTHIZ2_Msk (0xFFU << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
7876 #define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
7877 #define FSMC_PATT2_ATTHIZ2_0 (0x01U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
7878 #define FSMC_PATT2_ATTHIZ2_1 (0x02U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
7879 #define FSMC_PATT2_ATTHIZ2_2 (0x04U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
7880 #define FSMC_PATT2_ATTHIZ2_3 (0x08U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
7881 #define FSMC_PATT2_ATTHIZ2_4 (0x10U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
7882 #define FSMC_PATT2_ATTHIZ2_5 (0x20U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
7883 #define FSMC_PATT2_ATTHIZ2_6 (0x40U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
7884 #define FSMC_PATT2_ATTHIZ2_7 (0x80U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
7885
7886 /****************** Bit definition for FSMC_PATT3 register ******************/
7887 #define FSMC_PATT3_ATTSET3_Pos (0U)
7888 #define FSMC_PATT3_ATTSET3_Msk (0xFFU << FSMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
7889 #define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
7890 #define FSMC_PATT3_ATTSET3_0 (0x01U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
7891 #define FSMC_PATT3_ATTSET3_1 (0x02U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
7892 #define FSMC_PATT3_ATTSET3_2 (0x04U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
7893 #define FSMC_PATT3_ATTSET3_3 (0x08U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
7894 #define FSMC_PATT3_ATTSET3_4 (0x10U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
7895 #define FSMC_PATT3_ATTSET3_5 (0x20U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
7896 #define FSMC_PATT3_ATTSET3_6 (0x40U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
7897 #define FSMC_PATT3_ATTSET3_7 (0x80U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
7898
7899 #define FSMC_PATT3_ATTWAIT3_Pos (8U)
7900 #define FSMC_PATT3_ATTWAIT3_Msk (0xFFU << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
7901 #define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
7902 #define FSMC_PATT3_ATTWAIT3_0 (0x01U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
7903 #define FSMC_PATT3_ATTWAIT3_1 (0x02U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
7904 #define FSMC_PATT3_ATTWAIT3_2 (0x04U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
7905 #define FSMC_PATT3_ATTWAIT3_3 (0x08U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
7906 #define FSMC_PATT3_ATTWAIT3_4 (0x10U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
7907 #define FSMC_PATT3_ATTWAIT3_5 (0x20U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
7908 #define FSMC_PATT3_ATTWAIT3_6 (0x40U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
7909 #define FSMC_PATT3_ATTWAIT3_7 (0x80U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
7910
7911 #define FSMC_PATT3_ATTHOLD3_Pos (16U)
7912 #define FSMC_PATT3_ATTHOLD3_Msk (0xFFU << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
7913 #define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
7914 #define FSMC_PATT3_ATTHOLD3_0 (0x01U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
7915 #define FSMC_PATT3_ATTHOLD3_1 (0x02U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
7916 #define FSMC_PATT3_ATTHOLD3_2 (0x04U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
7917 #define FSMC_PATT3_ATTHOLD3_3 (0x08U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
7918 #define FSMC_PATT3_ATTHOLD3_4 (0x10U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
7919 #define FSMC_PATT3_ATTHOLD3_5 (0x20U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
7920 #define FSMC_PATT3_ATTHOLD3_6 (0x40U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
7921 #define FSMC_PATT3_ATTHOLD3_7 (0x80U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
7922
7923 #define FSMC_PATT3_ATTHIZ3_Pos (24U)
7924 #define FSMC_PATT3_ATTHIZ3_Msk (0xFFU << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
7925 #define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
7926 #define FSMC_PATT3_ATTHIZ3_0 (0x01U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
7927 #define FSMC_PATT3_ATTHIZ3_1 (0x02U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
7928 #define FSMC_PATT3_ATTHIZ3_2 (0x04U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
7929 #define FSMC_PATT3_ATTHIZ3_3 (0x08U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
7930 #define FSMC_PATT3_ATTHIZ3_4 (0x10U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
7931 #define FSMC_PATT3_ATTHIZ3_5 (0x20U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
7932 #define FSMC_PATT3_ATTHIZ3_6 (0x40U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
7933 #define FSMC_PATT3_ATTHIZ3_7 (0x80U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
7934
7935 /****************** Bit definition for FSMC_PATT4 register ******************/
7936 #define FSMC_PATT4_ATTSET4_Pos (0U)
7937 #define FSMC_PATT4_ATTSET4_Msk (0xFFU << FSMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
7938 #define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
7939 #define FSMC_PATT4_ATTSET4_0 (0x01U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
7940 #define FSMC_PATT4_ATTSET4_1 (0x02U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
7941 #define FSMC_PATT4_ATTSET4_2 (0x04U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
7942 #define FSMC_PATT4_ATTSET4_3 (0x08U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
7943 #define FSMC_PATT4_ATTSET4_4 (0x10U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
7944 #define FSMC_PATT4_ATTSET4_5 (0x20U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
7945 #define FSMC_PATT4_ATTSET4_6 (0x40U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
7946 #define FSMC_PATT4_ATTSET4_7 (0x80U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
7947
7948 #define FSMC_PATT4_ATTWAIT4_Pos (8U)
7949 #define FSMC_PATT4_ATTWAIT4_Msk (0xFFU << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
7950 #define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
7951 #define FSMC_PATT4_ATTWAIT4_0 (0x01U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
7952 #define FSMC_PATT4_ATTWAIT4_1 (0x02U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
7953 #define FSMC_PATT4_ATTWAIT4_2 (0x04U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
7954 #define FSMC_PATT4_ATTWAIT4_3 (0x08U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
7955 #define FSMC_PATT4_ATTWAIT4_4 (0x10U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
7956 #define FSMC_PATT4_ATTWAIT4_5 (0x20U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
7957 #define FSMC_PATT4_ATTWAIT4_6 (0x40U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
7958 #define FSMC_PATT4_ATTWAIT4_7 (0x80U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
7959
7960 #define FSMC_PATT4_ATTHOLD4_Pos (16U)
7961 #define FSMC_PATT4_ATTHOLD4_Msk (0xFFU << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
7962 #define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
7963 #define FSMC_PATT4_ATTHOLD4_0 (0x01U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
7964 #define FSMC_PATT4_ATTHOLD4_1 (0x02U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
7965 #define FSMC_PATT4_ATTHOLD4_2 (0x04U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
7966 #define FSMC_PATT4_ATTHOLD4_3 (0x08U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
7967 #define FSMC_PATT4_ATTHOLD4_4 (0x10U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
7968 #define FSMC_PATT4_ATTHOLD4_5 (0x20U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
7969 #define FSMC_PATT4_ATTHOLD4_6 (0x40U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
7970 #define FSMC_PATT4_ATTHOLD4_7 (0x80U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
7971
7972 #define FSMC_PATT4_ATTHIZ4_Pos (24U)
7973 #define FSMC_PATT4_ATTHIZ4_Msk (0xFFU << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
7974 #define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
7975 #define FSMC_PATT4_ATTHIZ4_0 (0x01U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
7976 #define FSMC_PATT4_ATTHIZ4_1 (0x02U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
7977 #define FSMC_PATT4_ATTHIZ4_2 (0x04U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
7978 #define FSMC_PATT4_ATTHIZ4_3 (0x08U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
7979 #define FSMC_PATT4_ATTHIZ4_4 (0x10U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
7980 #define FSMC_PATT4_ATTHIZ4_5 (0x20U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
7981 #define FSMC_PATT4_ATTHIZ4_6 (0x40U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
7982 #define FSMC_PATT4_ATTHIZ4_7 (0x80U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
7983
7984 /****************** Bit definition for FSMC_PIO4 register *******************/
7985 #define FSMC_PIO4_IOSET4_Pos (0U)
7986 #define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
7987 #define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
7988 #define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
7989 #define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
7990 #define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
7991 #define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
7992 #define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
7993 #define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
7994 #define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
7995 #define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
7996
7997 #define FSMC_PIO4_IOWAIT4_Pos (8U)
7998 #define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
7999 #define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
8000 #define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
8001 #define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
8002 #define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
8003 #define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
8004 #define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
8005 #define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
8006 #define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
8007 #define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
8008
8009 #define FSMC_PIO4_IOHOLD4_Pos (16U)
8010 #define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
8011 #define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
8012 #define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
8013 #define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
8014 #define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
8015 #define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
8016 #define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
8017 #define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
8018 #define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
8019 #define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
8020
8021 #define FSMC_PIO4_IOHIZ4_Pos (24U)
8022 #define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
8023 #define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
8024 #define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
8025 #define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
8026 #define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
8027 #define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
8028 #define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
8029 #define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
8030 #define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
8031 #define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
8032
8033 /****************** Bit definition for FSMC_ECCR2 register ******************/
8034 #define FSMC_ECCR2_ECC2_Pos (0U)
8035 #define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
8036 #define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!<ECC result */
8037
8038 /****************** Bit definition for FSMC_ECCR3 register ******************/
8039 #define FSMC_ECCR3_ECC3_Pos (0U)
8040 #define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
8041 #define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!<ECC result */
8042
8043 /******************************************************************************/
8044 /* */
8045 /* General Purpose I/O */
8046 /* */
8047 /******************************************************************************/
8048 /****************** Bits definition for GPIO_MODER register *****************/
8049 #define GPIO_MODER_MODE0_Pos (0U)
8050 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
8051 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
8052 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
8053 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
8054 #define GPIO_MODER_MODE1_Pos (2U)
8055 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
8056 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
8057 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
8058 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
8059 #define GPIO_MODER_MODE2_Pos (4U)
8060 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
8061 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
8062 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
8063 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
8064 #define GPIO_MODER_MODE3_Pos (6U)
8065 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
8066 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
8067 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
8068 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
8069 #define GPIO_MODER_MODE4_Pos (8U)
8070 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
8071 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
8072 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
8073 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
8074 #define GPIO_MODER_MODE5_Pos (10U)
8075 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
8076 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
8077 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
8078 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
8079 #define GPIO_MODER_MODE6_Pos (12U)
8080 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
8081 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
8082 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
8083 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
8084 #define GPIO_MODER_MODE7_Pos (14U)
8085 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
8086 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
8087 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
8088 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
8089 #define GPIO_MODER_MODE8_Pos (16U)
8090 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
8091 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
8092 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
8093 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
8094 #define GPIO_MODER_MODE9_Pos (18U)
8095 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
8096 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
8097 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
8098 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
8099 #define GPIO_MODER_MODE10_Pos (20U)
8100 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
8101 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
8102 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
8103 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
8104 #define GPIO_MODER_MODE11_Pos (22U)
8105 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
8106 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
8107 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
8108 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
8109 #define GPIO_MODER_MODE12_Pos (24U)
8110 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
8111 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
8112 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
8113 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
8114 #define GPIO_MODER_MODE13_Pos (26U)
8115 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
8116 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
8117 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
8118 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
8119 #define GPIO_MODER_MODE14_Pos (28U)
8120 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
8121 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8122 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
8123 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
8124 #define GPIO_MODER_MODE15_Pos (30U)
8125 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
8126 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8127 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
8128 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
8129
8130 /* Legacy defines */
8131 #define GPIO_MODER_MODER0_Pos (0U)
8132 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
8133 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8134 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
8135 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
8136 #define GPIO_MODER_MODER1_Pos (2U)
8137 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
8138 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8139 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
8140 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
8141 #define GPIO_MODER_MODER2_Pos (4U)
8142 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
8143 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8144 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
8145 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
8146 #define GPIO_MODER_MODER3_Pos (6U)
8147 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
8148 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8149 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
8150 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
8151 #define GPIO_MODER_MODER4_Pos (8U)
8152 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
8153 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8154 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
8155 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
8156 #define GPIO_MODER_MODER5_Pos (10U)
8157 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
8158 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8159 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
8160 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
8161 #define GPIO_MODER_MODER6_Pos (12U)
8162 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
8163 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8164 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
8165 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
8166 #define GPIO_MODER_MODER7_Pos (14U)
8167 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
8168 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8169 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
8170 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
8171 #define GPIO_MODER_MODER8_Pos (16U)
8172 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
8173 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8174 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
8175 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
8176 #define GPIO_MODER_MODER9_Pos (18U)
8177 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
8178 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8179 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
8180 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
8181 #define GPIO_MODER_MODER10_Pos (20U)
8182 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
8183 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8184 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
8185 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
8186 #define GPIO_MODER_MODER11_Pos (22U)
8187 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
8188 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8189 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
8190 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
8191 #define GPIO_MODER_MODER12_Pos (24U)
8192 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
8193 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8194 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
8195 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
8196 #define GPIO_MODER_MODER13_Pos (26U)
8197 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
8198 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8199 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
8200 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
8201 #define GPIO_MODER_MODER14_Pos (28U)
8202 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
8203 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8204 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
8205 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
8206 #define GPIO_MODER_MODER15_Pos (30U)
8207 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
8208 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8209 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
8210 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
8211
8212 /****************** Bits definition for GPIO_OTYPER register ****************/
8213 #define GPIO_OTYPER_OT0_Pos (0U)
8214 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
8215 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8216 #define GPIO_OTYPER_OT1_Pos (1U)
8217 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
8218 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8219 #define GPIO_OTYPER_OT2_Pos (2U)
8220 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
8221 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8222 #define GPIO_OTYPER_OT3_Pos (3U)
8223 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
8224 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8225 #define GPIO_OTYPER_OT4_Pos (4U)
8226 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
8227 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8228 #define GPIO_OTYPER_OT5_Pos (5U)
8229 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
8230 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8231 #define GPIO_OTYPER_OT6_Pos (6U)
8232 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
8233 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8234 #define GPIO_OTYPER_OT7_Pos (7U)
8235 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
8236 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8237 #define GPIO_OTYPER_OT8_Pos (8U)
8238 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
8239 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8240 #define GPIO_OTYPER_OT9_Pos (9U)
8241 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
8242 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8243 #define GPIO_OTYPER_OT10_Pos (10U)
8244 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
8245 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8246 #define GPIO_OTYPER_OT11_Pos (11U)
8247 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
8248 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8249 #define GPIO_OTYPER_OT12_Pos (12U)
8250 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
8251 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8252 #define GPIO_OTYPER_OT13_Pos (13U)
8253 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
8254 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8255 #define GPIO_OTYPER_OT14_Pos (14U)
8256 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
8257 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8258 #define GPIO_OTYPER_OT15_Pos (15U)
8259 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
8260 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8261
8262 /* Legacy defines */
8263 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8264 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8265 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8266 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8267 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8268 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8269 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8270 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8271 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8272 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8273 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8274 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8275 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8276 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8277 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8278 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8279
8280 /****************** Bits definition for GPIO_OSPEEDR register ***************/
8281 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8282 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
8283 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8284 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
8285 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
8286 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8287 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
8288 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8289 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
8290 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
8291 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8292 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
8293 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8294 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
8295 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
8296 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8297 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
8298 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8299 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
8300 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
8301 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8302 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
8303 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8304 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
8305 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
8306 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8307 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
8308 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8309 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
8310 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
8311 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8312 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
8313 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8314 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
8315 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
8316 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8317 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
8318 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8319 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
8320 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
8321 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8322 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
8323 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8324 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
8325 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
8326 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8327 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
8328 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8329 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
8330 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
8331 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8332 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
8333 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8334 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
8335 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
8336 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8337 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
8338 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8339 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
8340 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
8341 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8342 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
8343 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8344 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
8345 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
8346 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8347 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
8348 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8349 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
8350 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
8351 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8352 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
8353 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8354 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
8355 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
8356 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8357 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
8358 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8359 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
8360 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
8361
8362 /* Legacy defines */
8363 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8364 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8365 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8366 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8367 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8368 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8369 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8370 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8371 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8372 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8373 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8374 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8375 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8376 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8377 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8378 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8379 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8380 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8381 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8382 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8383 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8384 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8385 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8386 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8387 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8388 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8389 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8390 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8391 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8392 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8393 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8394 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8395 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8396 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8397 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8398 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8399 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8400 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8401 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8402 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8403 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8404 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8405 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8406 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8407 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8408 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8409 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8410 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8411
8412 /****************** Bits definition for GPIO_PUPDR register *****************/
8413 #define GPIO_PUPDR_PUPD0_Pos (0U)
8414 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
8415 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8416 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
8417 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
8418 #define GPIO_PUPDR_PUPD1_Pos (2U)
8419 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
8420 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8421 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
8422 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
8423 #define GPIO_PUPDR_PUPD2_Pos (4U)
8424 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
8425 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8426 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
8427 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
8428 #define GPIO_PUPDR_PUPD3_Pos (6U)
8429 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
8430 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8431 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
8432 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
8433 #define GPIO_PUPDR_PUPD4_Pos (8U)
8434 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
8435 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8436 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
8437 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
8438 #define GPIO_PUPDR_PUPD5_Pos (10U)
8439 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
8440 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8441 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
8442 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
8443 #define GPIO_PUPDR_PUPD6_Pos (12U)
8444 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
8445 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8446 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
8447 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
8448 #define GPIO_PUPDR_PUPD7_Pos (14U)
8449 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
8450 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8451 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
8452 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
8453 #define GPIO_PUPDR_PUPD8_Pos (16U)
8454 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
8455 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8456 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
8457 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
8458 #define GPIO_PUPDR_PUPD9_Pos (18U)
8459 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
8460 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8461 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
8462 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
8463 #define GPIO_PUPDR_PUPD10_Pos (20U)
8464 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
8465 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8466 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
8467 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
8468 #define GPIO_PUPDR_PUPD11_Pos (22U)
8469 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
8470 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8471 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
8472 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
8473 #define GPIO_PUPDR_PUPD12_Pos (24U)
8474 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
8475 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8476 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
8477 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
8478 #define GPIO_PUPDR_PUPD13_Pos (26U)
8479 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
8480 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8481 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
8482 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
8483 #define GPIO_PUPDR_PUPD14_Pos (28U)
8484 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
8485 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8486 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
8487 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
8488 #define GPIO_PUPDR_PUPD15_Pos (30U)
8489 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
8490 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8491 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
8492 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
8493
8494 /* Legacy defines */
8495 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8496 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8497 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8498 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8499 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8500 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8501 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8502 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8503 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8504 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8505 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8506 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8507 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8508 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8509 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8510 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8511 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8512 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8513 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8514 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8515 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8516 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8517 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8518 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8519 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8520 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8521 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8522 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8523 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8524 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8525 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8526 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8527 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8528 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8529 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8530 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8531 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8532 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8533 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8534 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8535 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8536 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8537 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8538 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8539 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8540 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8541 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8542 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8543
8544 /****************** Bits definition for GPIO_IDR register *******************/
8545 #define GPIO_IDR_ID0_Pos (0U)
8546 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
8547 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8548 #define GPIO_IDR_ID1_Pos (1U)
8549 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
8550 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8551 #define GPIO_IDR_ID2_Pos (2U)
8552 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
8553 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8554 #define GPIO_IDR_ID3_Pos (3U)
8555 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
8556 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8557 #define GPIO_IDR_ID4_Pos (4U)
8558 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
8559 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8560 #define GPIO_IDR_ID5_Pos (5U)
8561 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
8562 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8563 #define GPIO_IDR_ID6_Pos (6U)
8564 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
8565 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8566 #define GPIO_IDR_ID7_Pos (7U)
8567 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
8568 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8569 #define GPIO_IDR_ID8_Pos (8U)
8570 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
8571 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8572 #define GPIO_IDR_ID9_Pos (9U)
8573 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
8574 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8575 #define GPIO_IDR_ID10_Pos (10U)
8576 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
8577 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8578 #define GPIO_IDR_ID11_Pos (11U)
8579 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
8580 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8581 #define GPIO_IDR_ID12_Pos (12U)
8582 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
8583 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8584 #define GPIO_IDR_ID13_Pos (13U)
8585 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
8586 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8587 #define GPIO_IDR_ID14_Pos (14U)
8588 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
8589 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8590 #define GPIO_IDR_ID15_Pos (15U)
8591 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
8592 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8593
8594 /* Legacy defines */
8595 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8596 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8597 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8598 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8599 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8600 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8601 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8602 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8603 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8604 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8605 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8606 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8607 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8608 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8609 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8610 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8611
8612 /****************** Bits definition for GPIO_ODR register *******************/
8613 #define GPIO_ODR_OD0_Pos (0U)
8614 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
8615 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8616 #define GPIO_ODR_OD1_Pos (1U)
8617 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
8618 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8619 #define GPIO_ODR_OD2_Pos (2U)
8620 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
8621 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8622 #define GPIO_ODR_OD3_Pos (3U)
8623 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
8624 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8625 #define GPIO_ODR_OD4_Pos (4U)
8626 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
8627 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8628 #define GPIO_ODR_OD5_Pos (5U)
8629 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
8630 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8631 #define GPIO_ODR_OD6_Pos (6U)
8632 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
8633 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8634 #define GPIO_ODR_OD7_Pos (7U)
8635 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
8636 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8637 #define GPIO_ODR_OD8_Pos (8U)
8638 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
8639 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8640 #define GPIO_ODR_OD9_Pos (9U)
8641 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
8642 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8643 #define GPIO_ODR_OD10_Pos (10U)
8644 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
8645 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8646 #define GPIO_ODR_OD11_Pos (11U)
8647 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
8648 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8649 #define GPIO_ODR_OD12_Pos (12U)
8650 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
8651 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8652 #define GPIO_ODR_OD13_Pos (13U)
8653 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
8654 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8655 #define GPIO_ODR_OD14_Pos (14U)
8656 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
8657 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8658 #define GPIO_ODR_OD15_Pos (15U)
8659 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
8660 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8661 /* Legacy defines */
8662 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8663 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8664 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8665 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8666 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8667 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8668 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8669 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8670 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8671 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8672 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8673 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8674 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8675 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8676 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8677 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8678
8679 /****************** Bits definition for GPIO_BSRR register ******************/
8680 #define GPIO_BSRR_BS0_Pos (0U)
8681 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
8682 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8683 #define GPIO_BSRR_BS1_Pos (1U)
8684 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
8685 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8686 #define GPIO_BSRR_BS2_Pos (2U)
8687 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
8688 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8689 #define GPIO_BSRR_BS3_Pos (3U)
8690 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
8691 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8692 #define GPIO_BSRR_BS4_Pos (4U)
8693 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
8694 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8695 #define GPIO_BSRR_BS5_Pos (5U)
8696 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
8697 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8698 #define GPIO_BSRR_BS6_Pos (6U)
8699 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
8700 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8701 #define GPIO_BSRR_BS7_Pos (7U)
8702 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
8703 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8704 #define GPIO_BSRR_BS8_Pos (8U)
8705 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
8706 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8707 #define GPIO_BSRR_BS9_Pos (9U)
8708 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
8709 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8710 #define GPIO_BSRR_BS10_Pos (10U)
8711 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
8712 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8713 #define GPIO_BSRR_BS11_Pos (11U)
8714 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
8715 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8716 #define GPIO_BSRR_BS12_Pos (12U)
8717 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
8718 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8719 #define GPIO_BSRR_BS13_Pos (13U)
8720 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
8721 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8722 #define GPIO_BSRR_BS14_Pos (14U)
8723 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
8724 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8725 #define GPIO_BSRR_BS15_Pos (15U)
8726 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
8727 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8728 #define GPIO_BSRR_BR0_Pos (16U)
8729 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
8730 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8731 #define GPIO_BSRR_BR1_Pos (17U)
8732 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
8733 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8734 #define GPIO_BSRR_BR2_Pos (18U)
8735 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
8736 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8737 #define GPIO_BSRR_BR3_Pos (19U)
8738 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
8739 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8740 #define GPIO_BSRR_BR4_Pos (20U)
8741 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
8742 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8743 #define GPIO_BSRR_BR5_Pos (21U)
8744 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
8745 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8746 #define GPIO_BSRR_BR6_Pos (22U)
8747 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
8748 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8749 #define GPIO_BSRR_BR7_Pos (23U)
8750 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
8751 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8752 #define GPIO_BSRR_BR8_Pos (24U)
8753 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
8754 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8755 #define GPIO_BSRR_BR9_Pos (25U)
8756 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
8757 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8758 #define GPIO_BSRR_BR10_Pos (26U)
8759 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
8760 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8761 #define GPIO_BSRR_BR11_Pos (27U)
8762 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
8763 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8764 #define GPIO_BSRR_BR12_Pos (28U)
8765 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
8766 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8767 #define GPIO_BSRR_BR13_Pos (29U)
8768 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
8769 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8770 #define GPIO_BSRR_BR14_Pos (30U)
8771 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
8772 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8773 #define GPIO_BSRR_BR15_Pos (31U)
8774 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
8775 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8776
8777 /* Legacy defines */
8778 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8779 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8780 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8781 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8782 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8783 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8784 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8785 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8786 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8787 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8788 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8789 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8790 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8791 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8792 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8793 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8794 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8795 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8796 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8797 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8798 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8799 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8800 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8801 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8802 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8803 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8804 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8805 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8806 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8807 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8808 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8809 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8810 /****************** Bit definition for GPIO_LCKR register *********************/
8811 #define GPIO_LCKR_LCK0_Pos (0U)
8812 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
8813 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8814 #define GPIO_LCKR_LCK1_Pos (1U)
8815 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
8816 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8817 #define GPIO_LCKR_LCK2_Pos (2U)
8818 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
8819 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8820 #define GPIO_LCKR_LCK3_Pos (3U)
8821 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
8822 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8823 #define GPIO_LCKR_LCK4_Pos (4U)
8824 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
8825 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8826 #define GPIO_LCKR_LCK5_Pos (5U)
8827 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
8828 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8829 #define GPIO_LCKR_LCK6_Pos (6U)
8830 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
8831 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8832 #define GPIO_LCKR_LCK7_Pos (7U)
8833 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
8834 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8835 #define GPIO_LCKR_LCK8_Pos (8U)
8836 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
8837 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8838 #define GPIO_LCKR_LCK9_Pos (9U)
8839 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
8840 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8841 #define GPIO_LCKR_LCK10_Pos (10U)
8842 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
8843 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8844 #define GPIO_LCKR_LCK11_Pos (11U)
8845 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
8846 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8847 #define GPIO_LCKR_LCK12_Pos (12U)
8848 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
8849 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8850 #define GPIO_LCKR_LCK13_Pos (13U)
8851 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
8852 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8853 #define GPIO_LCKR_LCK14_Pos (14U)
8854 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
8855 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8856 #define GPIO_LCKR_LCK15_Pos (15U)
8857 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
8858 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8859 #define GPIO_LCKR_LCKK_Pos (16U)
8860 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
8861 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8862 /****************** Bit definition for GPIO_AFRL register *********************/
8863 #define GPIO_AFRL_AFSEL0_Pos (0U)
8864 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
8865 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8866 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
8867 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
8868 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
8869 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
8870 #define GPIO_AFRL_AFSEL1_Pos (4U)
8871 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
8872 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8873 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
8874 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
8875 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
8876 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
8877 #define GPIO_AFRL_AFSEL2_Pos (8U)
8878 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
8879 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8880 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
8881 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
8882 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
8883 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
8884 #define GPIO_AFRL_AFSEL3_Pos (12U)
8885 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
8886 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8887 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
8888 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
8889 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
8890 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
8891 #define GPIO_AFRL_AFSEL4_Pos (16U)
8892 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
8893 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8894 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
8895 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
8896 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
8897 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
8898 #define GPIO_AFRL_AFSEL5_Pos (20U)
8899 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
8900 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8901 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
8902 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
8903 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
8904 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
8905 #define GPIO_AFRL_AFSEL6_Pos (24U)
8906 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
8907 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8908 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
8909 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
8910 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
8911 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
8912 #define GPIO_AFRL_AFSEL7_Pos (28U)
8913 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
8914 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8915 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
8916 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
8917 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
8918 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
8919
8920 /* Legacy defines */
8921 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8922 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8923 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8924 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8925 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8926 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8927 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8928 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8929 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8930 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8931 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8932 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8933 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8934 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8935 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8936 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8937 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8938 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8939 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8940 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8941 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8942 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8943 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8944 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8945 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8946 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8947 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8948 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8949 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8950 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8951 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8952 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8953 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8954 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8955 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8956 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8957 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
8958 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
8959 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
8960 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
8961
8962 /****************** Bit definition for GPIO_AFRH register *********************/
8963 #define GPIO_AFRH_AFSEL8_Pos (0U)
8964 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
8965 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8966 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
8967 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
8968 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
8969 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
8970 #define GPIO_AFRH_AFSEL9_Pos (4U)
8971 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
8972 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8973 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
8974 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
8975 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
8976 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
8977 #define GPIO_AFRH_AFSEL10_Pos (8U)
8978 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
8979 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8980 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
8981 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
8982 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
8983 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
8984 #define GPIO_AFRH_AFSEL11_Pos (12U)
8985 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
8986 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8987 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
8988 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
8989 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
8990 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
8991 #define GPIO_AFRH_AFSEL12_Pos (16U)
8992 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
8993 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8994 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
8995 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
8996 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
8997 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
8998 #define GPIO_AFRH_AFSEL13_Pos (20U)
8999 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
9000 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9001 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
9002 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
9003 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
9004 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
9005 #define GPIO_AFRH_AFSEL14_Pos (24U)
9006 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
9007 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9008 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
9009 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
9010 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
9011 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
9012 #define GPIO_AFRH_AFSEL15_Pos (28U)
9013 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
9014 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9015 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
9016 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
9017 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
9018 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
9019
9020 /* Legacy defines */
9021 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9022 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
9023 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
9024 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
9025 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
9026 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9027 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
9028 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
9029 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
9030 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
9031 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9032 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
9033 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
9034 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
9035 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
9036 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9037 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
9038 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
9039 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
9040 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
9041 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9042 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
9043 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
9044 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
9045 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
9046 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9047 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
9048 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
9049 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
9050 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
9051 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9052 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
9053 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
9054 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
9055 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
9056 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9057 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
9058 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
9059 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
9060 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
9061
9062 /****************** Bits definition for GPIO_BRR register ******************/
9063 #define GPIO_BRR_BR0_Pos (0U)
9064 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
9065 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
9066 #define GPIO_BRR_BR1_Pos (1U)
9067 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
9068 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
9069 #define GPIO_BRR_BR2_Pos (2U)
9070 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
9071 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
9072 #define GPIO_BRR_BR3_Pos (3U)
9073 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
9074 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
9075 #define GPIO_BRR_BR4_Pos (4U)
9076 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
9077 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
9078 #define GPIO_BRR_BR5_Pos (5U)
9079 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
9080 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
9081 #define GPIO_BRR_BR6_Pos (6U)
9082 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
9083 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
9084 #define GPIO_BRR_BR7_Pos (7U)
9085 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
9086 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
9087 #define GPIO_BRR_BR8_Pos (8U)
9088 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
9089 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
9090 #define GPIO_BRR_BR9_Pos (9U)
9091 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
9092 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
9093 #define GPIO_BRR_BR10_Pos (10U)
9094 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
9095 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
9096 #define GPIO_BRR_BR11_Pos (11U)
9097 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
9098 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
9099 #define GPIO_BRR_BR12_Pos (12U)
9100 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
9101 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
9102 #define GPIO_BRR_BR13_Pos (13U)
9103 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
9104 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
9105 #define GPIO_BRR_BR14_Pos (14U)
9106 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
9107 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
9108 #define GPIO_BRR_BR15_Pos (15U)
9109 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
9110 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
9111
9112
9113 /******************************************************************************/
9114 /* */
9115 /* Inter-integrated Circuit Interface */
9116 /* */
9117 /******************************************************************************/
9118 /******************* Bit definition for I2C_CR1 register ********************/
9119 #define I2C_CR1_PE_Pos (0U)
9120 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
9121 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
9122 #define I2C_CR1_SMBUS_Pos (1U)
9123 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
9124 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
9125 #define I2C_CR1_SMBTYPE_Pos (3U)
9126 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
9127 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
9128 #define I2C_CR1_ENARP_Pos (4U)
9129 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
9130 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
9131 #define I2C_CR1_ENPEC_Pos (5U)
9132 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
9133 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
9134 #define I2C_CR1_ENGC_Pos (6U)
9135 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
9136 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
9137 #define I2C_CR1_NOSTRETCH_Pos (7U)
9138 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
9139 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
9140 #define I2C_CR1_START_Pos (8U)
9141 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
9142 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
9143 #define I2C_CR1_STOP_Pos (9U)
9144 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
9145 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
9146 #define I2C_CR1_ACK_Pos (10U)
9147 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
9148 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
9149 #define I2C_CR1_POS_Pos (11U)
9150 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
9151 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
9152 #define I2C_CR1_PEC_Pos (12U)
9153 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
9154 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
9155 #define I2C_CR1_ALERT_Pos (13U)
9156 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
9157 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
9158 #define I2C_CR1_SWRST_Pos (15U)
9159 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
9160 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
9161
9162 /******************* Bit definition for I2C_CR2 register ********************/
9163 #define I2C_CR2_FREQ_Pos (0U)
9164 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
9165 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
9166 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
9167 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
9168 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
9169 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
9170 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
9171 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
9172
9173 #define I2C_CR2_ITERREN_Pos (8U)
9174 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
9175 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
9176 #define I2C_CR2_ITEVTEN_Pos (9U)
9177 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
9178 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
9179 #define I2C_CR2_ITBUFEN_Pos (10U)
9180 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
9181 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
9182 #define I2C_CR2_DMAEN_Pos (11U)
9183 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
9184 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
9185 #define I2C_CR2_LAST_Pos (12U)
9186 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
9187 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
9188
9189 /******************* Bit definition for I2C_OAR1 register *******************/
9190 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
9191 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
9192
9193 #define I2C_OAR1_ADD0_Pos (0U)
9194 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
9195 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
9196 #define I2C_OAR1_ADD1_Pos (1U)
9197 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
9198 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
9199 #define I2C_OAR1_ADD2_Pos (2U)
9200 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
9201 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
9202 #define I2C_OAR1_ADD3_Pos (3U)
9203 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
9204 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
9205 #define I2C_OAR1_ADD4_Pos (4U)
9206 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
9207 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
9208 #define I2C_OAR1_ADD5_Pos (5U)
9209 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
9210 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
9211 #define I2C_OAR1_ADD6_Pos (6U)
9212 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
9213 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
9214 #define I2C_OAR1_ADD7_Pos (7U)
9215 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
9216 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
9217 #define I2C_OAR1_ADD8_Pos (8U)
9218 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
9219 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
9220 #define I2C_OAR1_ADD9_Pos (9U)
9221 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
9222 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
9223
9224 #define I2C_OAR1_ADDMODE_Pos (15U)
9225 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
9226 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
9227
9228 /******************* Bit definition for I2C_OAR2 register *******************/
9229 #define I2C_OAR2_ENDUAL_Pos (0U)
9230 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
9231 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
9232 #define I2C_OAR2_ADD2_Pos (1U)
9233 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
9234 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
9235
9236 /******************** Bit definition for I2C_DR register ********************/
9237 #define I2C_DR_DR_Pos (0U)
9238 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
9239 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
9240
9241 /******************* Bit definition for I2C_SR1 register ********************/
9242 #define I2C_SR1_SB_Pos (0U)
9243 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
9244 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
9245 #define I2C_SR1_ADDR_Pos (1U)
9246 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
9247 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
9248 #define I2C_SR1_BTF_Pos (2U)
9249 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
9250 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
9251 #define I2C_SR1_ADD10_Pos (3U)
9252 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
9253 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
9254 #define I2C_SR1_STOPF_Pos (4U)
9255 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
9256 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
9257 #define I2C_SR1_RXNE_Pos (6U)
9258 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
9259 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
9260 #define I2C_SR1_TXE_Pos (7U)
9261 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
9262 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
9263 #define I2C_SR1_BERR_Pos (8U)
9264 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
9265 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
9266 #define I2C_SR1_ARLO_Pos (9U)
9267 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
9268 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
9269 #define I2C_SR1_AF_Pos (10U)
9270 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
9271 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
9272 #define I2C_SR1_OVR_Pos (11U)
9273 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
9274 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
9275 #define I2C_SR1_PECERR_Pos (12U)
9276 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
9277 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
9278 #define I2C_SR1_TIMEOUT_Pos (14U)
9279 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
9280 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
9281 #define I2C_SR1_SMBALERT_Pos (15U)
9282 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
9283 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
9284
9285 /******************* Bit definition for I2C_SR2 register ********************/
9286 #define I2C_SR2_MSL_Pos (0U)
9287 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
9288 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
9289 #define I2C_SR2_BUSY_Pos (1U)
9290 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
9291 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
9292 #define I2C_SR2_TRA_Pos (2U)
9293 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
9294 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
9295 #define I2C_SR2_GENCALL_Pos (4U)
9296 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
9297 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
9298 #define I2C_SR2_SMBDEFAULT_Pos (5U)
9299 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
9300 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
9301 #define I2C_SR2_SMBHOST_Pos (6U)
9302 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
9303 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
9304 #define I2C_SR2_DUALF_Pos (7U)
9305 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
9306 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
9307 #define I2C_SR2_PEC_Pos (8U)
9308 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
9309 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
9310
9311 /******************* Bit definition for I2C_CCR register ********************/
9312 #define I2C_CCR_CCR_Pos (0U)
9313 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
9314 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
9315 #define I2C_CCR_DUTY_Pos (14U)
9316 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
9317 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
9318 #define I2C_CCR_FS_Pos (15U)
9319 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
9320 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
9321
9322 /****************** Bit definition for I2C_TRISE register *******************/
9323 #define I2C_TRISE_TRISE_Pos (0U)
9324 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
9325 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
9326
9327
9328 /******************************************************************************/
9329 /* */
9330 /* Independent WATCHDOG */
9331 /* */
9332 /******************************************************************************/
9333 /******************* Bit definition for IWDG_KR register ********************/
9334 #define IWDG_KR_KEY_Pos (0U)
9335 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
9336 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
9337
9338 /******************* Bit definition for IWDG_PR register ********************/
9339 #define IWDG_PR_PR_Pos (0U)
9340 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
9341 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
9342 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
9343 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
9344 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
9345
9346 /******************* Bit definition for IWDG_RLR register *******************/
9347 #define IWDG_RLR_RL_Pos (0U)
9348 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
9349 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
9350
9351 /******************* Bit definition for IWDG_SR register ********************/
9352 #define IWDG_SR_PVU_Pos (0U)
9353 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
9354 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
9355 #define IWDG_SR_RVU_Pos (1U)
9356 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
9357 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
9358
9359
9360
9361 /******************************************************************************/
9362 /* */
9363 /* Power Control */
9364 /* */
9365 /******************************************************************************/
9366 /******************** Bit definition for PWR_CR register ********************/
9367 #define PWR_CR_LPDS_Pos (0U)
9368 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
9369 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
9370 #define PWR_CR_PDDS_Pos (1U)
9371 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
9372 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
9373 #define PWR_CR_CWUF_Pos (2U)
9374 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
9375 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
9376 #define PWR_CR_CSBF_Pos (3U)
9377 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
9378 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
9379 #define PWR_CR_PVDE_Pos (4U)
9380 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
9381 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
9382
9383 #define PWR_CR_PLS_Pos (5U)
9384 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
9385 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
9386 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
9387 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
9388 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
9389
9390 /*!< PVD level configuration */
9391 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
9392 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
9393 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
9394 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
9395 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
9396 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
9397 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
9398 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
9399 #define PWR_CR_DBP_Pos (8U)
9400 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
9401 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
9402 #define PWR_CR_FPDS_Pos (9U)
9403 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
9404 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
9405 #define PWR_CR_VOS_Pos (14U)
9406 #define PWR_CR_VOS_Msk (0x1U << PWR_CR_VOS_Pos) /*!< 0x00004000 */
9407 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS bit (Regulator voltage scaling output selection) */
9408
9409 /* Legacy define */
9410 #define PWR_CR_PMODE PWR_CR_VOS
9411
9412 /******************* Bit definition for PWR_CSR register ********************/
9413 #define PWR_CSR_WUF_Pos (0U)
9414 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
9415 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
9416 #define PWR_CSR_SBF_Pos (1U)
9417 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
9418 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
9419 #define PWR_CSR_PVDO_Pos (2U)
9420 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
9421 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
9422 #define PWR_CSR_BRR_Pos (3U)
9423 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
9424 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
9425 #define PWR_CSR_EWUP_Pos (8U)
9426 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
9427 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
9428 #define PWR_CSR_BRE_Pos (9U)
9429 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
9430 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
9431 #define PWR_CSR_VOSRDY_Pos (14U)
9432 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
9433 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
9434
9435 /* Legacy define */
9436 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
9437
9438 /******************************************************************************/
9439 /* */
9440 /* Reset and Clock Control */
9441 /* */
9442 /******************************************************************************/
9443 /******************** Bit definition for RCC_CR register ********************/
9444 #define RCC_CR_HSION_Pos (0U)
9445 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
9446 #define RCC_CR_HSION RCC_CR_HSION_Msk
9447 #define RCC_CR_HSIRDY_Pos (1U)
9448 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
9449 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9450
9451 #define RCC_CR_HSITRIM_Pos (3U)
9452 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
9453 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9454 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
9455 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
9456 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
9457 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
9458 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
9459
9460 #define RCC_CR_HSICAL_Pos (8U)
9461 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
9462 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9463 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
9464 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
9465 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
9466 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
9467 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
9468 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
9469 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
9470 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
9471
9472 #define RCC_CR_HSEON_Pos (16U)
9473 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
9474 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
9475 #define RCC_CR_HSERDY_Pos (17U)
9476 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
9477 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9478 #define RCC_CR_HSEBYP_Pos (18U)
9479 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
9480 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9481 #define RCC_CR_CSSON_Pos (19U)
9482 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
9483 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
9484 #define RCC_CR_PLLON_Pos (24U)
9485 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
9486 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
9487 #define RCC_CR_PLLRDY_Pos (25U)
9488 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
9489 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9490 /*
9491 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9492 */
9493 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
9494
9495 #define RCC_CR_PLLI2SON_Pos (26U)
9496 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
9497 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9498 #define RCC_CR_PLLI2SRDY_Pos (27U)
9499 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
9500 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9501
9502 /******************** Bit definition for RCC_PLLCFGR register ***************/
9503 #define RCC_PLLCFGR_PLLM_Pos (0U)
9504 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
9505 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9506 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
9507 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
9508 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
9509 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
9510 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
9511 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
9512
9513 #define RCC_PLLCFGR_PLLN_Pos (6U)
9514 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
9515 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9516 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
9517 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
9518 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
9519 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
9520 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
9521 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
9522 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
9523 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
9524 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
9525
9526 #define RCC_PLLCFGR_PLLP_Pos (16U)
9527 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
9528 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9529 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
9530 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
9531
9532 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
9533 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
9534 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9535 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9536 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
9537 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9538 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9539
9540 #define RCC_PLLCFGR_PLLQ_Pos (24U)
9541 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
9542 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9543 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
9544 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
9545 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
9546 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
9547
9548
9549 /******************** Bit definition for RCC_CFGR register ******************/
9550 /*!< SW configuration */
9551 #define RCC_CFGR_SW_Pos (0U)
9552 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
9553 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
9554 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
9555 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
9556
9557 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
9558 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
9559 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
9560
9561 /*!< SWS configuration */
9562 #define RCC_CFGR_SWS_Pos (2U)
9563 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
9564 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
9565 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
9566 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
9567
9568 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
9569 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
9570 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
9571
9572 /*!< HPRE configuration */
9573 #define RCC_CFGR_HPRE_Pos (4U)
9574 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
9575 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
9576 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
9577 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
9578 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
9579 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
9580
9581 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
9582 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
9583 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
9584 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
9585 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
9586 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
9587 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
9588 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
9589 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
9590
9591 /*!< PPRE1 configuration */
9592 #define RCC_CFGR_PPRE1_Pos (10U)
9593 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
9594 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
9595 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
9596 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
9597 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
9598
9599 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
9600 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
9601 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
9602 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
9603 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
9604
9605 /*!< PPRE2 configuration */
9606 #define RCC_CFGR_PPRE2_Pos (13U)
9607 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
9608 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
9609 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
9610 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
9611 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
9612
9613 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
9614 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
9615 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
9616 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
9617 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
9618
9619 /*!< RTCPRE configuration */
9620 #define RCC_CFGR_RTCPRE_Pos (16U)
9621 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
9622 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9623 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
9624 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
9625 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
9626 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
9627 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
9628
9629 /*!< MCO1 configuration */
9630 #define RCC_CFGR_MCO1_Pos (21U)
9631 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
9632 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9633 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
9634 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
9635
9636 #define RCC_CFGR_I2SSRC_Pos (23U)
9637 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
9638 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
9639
9640 #define RCC_CFGR_MCO1PRE_Pos (24U)
9641 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
9642 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9643 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
9644 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
9645 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
9646
9647 #define RCC_CFGR_MCO2PRE_Pos (27U)
9648 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
9649 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9650 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
9651 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
9652 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
9653
9654 #define RCC_CFGR_MCO2_Pos (30U)
9655 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
9656 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9657 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
9658 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
9659
9660 /******************** Bit definition for RCC_CIR register *******************/
9661 #define RCC_CIR_LSIRDYF_Pos (0U)
9662 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
9663 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9664 #define RCC_CIR_LSERDYF_Pos (1U)
9665 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
9666 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9667 #define RCC_CIR_HSIRDYF_Pos (2U)
9668 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
9669 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9670 #define RCC_CIR_HSERDYF_Pos (3U)
9671 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
9672 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9673 #define RCC_CIR_PLLRDYF_Pos (4U)
9674 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
9675 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9676 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
9677 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
9678 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9679
9680 #define RCC_CIR_CSSF_Pos (7U)
9681 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
9682 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9683 #define RCC_CIR_LSIRDYIE_Pos (8U)
9684 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
9685 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9686 #define RCC_CIR_LSERDYIE_Pos (9U)
9687 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
9688 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9689 #define RCC_CIR_HSIRDYIE_Pos (10U)
9690 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
9691 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9692 #define RCC_CIR_HSERDYIE_Pos (11U)
9693 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
9694 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9695 #define RCC_CIR_PLLRDYIE_Pos (12U)
9696 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
9697 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9698 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9699 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
9700 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9701
9702 #define RCC_CIR_LSIRDYC_Pos (16U)
9703 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
9704 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9705 #define RCC_CIR_LSERDYC_Pos (17U)
9706 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
9707 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9708 #define RCC_CIR_HSIRDYC_Pos (18U)
9709 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
9710 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9711 #define RCC_CIR_HSERDYC_Pos (19U)
9712 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
9713 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9714 #define RCC_CIR_PLLRDYC_Pos (20U)
9715 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
9716 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9717 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
9718 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
9719 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9720
9721 #define RCC_CIR_CSSC_Pos (23U)
9722 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
9723 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9724
9725 /******************** Bit definition for RCC_AHB1RSTR register **************/
9726 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9727 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
9728 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9729 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9730 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
9731 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9732 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9733 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
9734 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9735 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9736 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
9737 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9738 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9739 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
9740 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9741 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9742 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
9743 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9744 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9745 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
9746 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9747 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9748 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
9749 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9750 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
9751 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
9752 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
9753 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
9754 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
9755 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9756 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9757 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
9758 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9759 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9760 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
9761 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9762 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
9763 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
9764 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
9765 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
9766 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
9767 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
9768
9769 /******************** Bit definition for RCC_AHB2RSTR register **************/
9770 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
9771 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
9772 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
9773 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
9774 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
9775 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9776 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9777 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
9778 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9779 /******************** Bit definition for RCC_AHB3RSTR register **************/
9780 #define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9781 #define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
9782 #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9783
9784
9785 /******************** Bit definition for RCC_APB1RSTR register **************/
9786 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
9787 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
9788 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9789 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
9790 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
9791 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9792 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
9793 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
9794 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9795 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
9796 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
9797 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9798 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
9799 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
9800 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9801 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
9802 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
9803 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9804 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
9805 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
9806 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9807 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
9808 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
9809 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9810 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
9811 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
9812 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9813 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
9814 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
9815 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9816 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
9817 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
9818 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9819 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
9820 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
9821 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9822 #define RCC_APB1RSTR_USART2RST_Pos (17U)
9823 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
9824 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9825 #define RCC_APB1RSTR_USART3RST_Pos (18U)
9826 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
9827 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9828 #define RCC_APB1RSTR_UART4RST_Pos (19U)
9829 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
9830 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9831 #define RCC_APB1RSTR_UART5RST_Pos (20U)
9832 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
9833 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9834 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
9835 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
9836 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9837 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
9838 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
9839 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9840 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
9841 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
9842 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9843 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
9844 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
9845 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9846 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
9847 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
9848 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9849 #define RCC_APB1RSTR_PWRRST_Pos (28U)
9850 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
9851 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9852 #define RCC_APB1RSTR_DACRST_Pos (29U)
9853 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
9854 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9855
9856 /******************** Bit definition for RCC_APB2RSTR register **************/
9857 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
9858 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
9859 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9860 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
9861 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
9862 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9863 #define RCC_APB2RSTR_USART1RST_Pos (4U)
9864 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
9865 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9866 #define RCC_APB2RSTR_USART6RST_Pos (5U)
9867 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
9868 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9869 #define RCC_APB2RSTR_ADCRST_Pos (8U)
9870 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
9871 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9872 #define RCC_APB2RSTR_SDIORST_Pos (11U)
9873 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
9874 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9875 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
9876 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
9877 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9878 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9879 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
9880 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9881 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
9882 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
9883 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9884 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
9885 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
9886 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9887 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
9888 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
9889 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9890
9891 /* Old SPI1RST bit definition, maintained for legacy purpose */
9892 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
9893
9894 /******************** Bit definition for RCC_AHB1ENR register ***************/
9895 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9896 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
9897 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9898 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9899 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
9900 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9901 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9902 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
9903 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9904 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
9905 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
9906 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9907 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9908 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
9909 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9910 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9911 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
9912 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
9913 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
9914 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
9915 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
9916 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9917 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
9918 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9919 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
9920 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
9921 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
9922 #define RCC_AHB1ENR_CRCEN_Pos (12U)
9923 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
9924 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9925 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
9926 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
9927 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
9928 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
9929 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
9930 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
9931 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
9932 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
9933 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9934 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
9935 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
9936 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9937 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
9938 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
9939 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
9940 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
9941 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
9942 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
9943 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
9944 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
9945 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
9946 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
9947 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
9948 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
9949 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
9950 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
9951 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
9952 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
9953 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
9954 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
9955 /******************** Bit definition for RCC_AHB2ENR register ***************/
9956 /*
9957 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9958 */
9959 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
9960
9961 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
9962 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
9963 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
9964 #define RCC_AHB2ENR_RNGEN_Pos (6U)
9965 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
9966 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9967 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9968 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
9969 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9970
9971 /******************** Bit definition for RCC_AHB3ENR register ***************/
9972 /*
9973 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9974 */
9975 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
9976
9977 #define RCC_AHB3ENR_FSMCEN_Pos (0U)
9978 #define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
9979 #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
9980
9981 /******************** Bit definition for RCC_APB1ENR register ***************/
9982 #define RCC_APB1ENR_TIM2EN_Pos (0U)
9983 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
9984 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
9985 #define RCC_APB1ENR_TIM3EN_Pos (1U)
9986 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
9987 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
9988 #define RCC_APB1ENR_TIM4EN_Pos (2U)
9989 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
9990 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
9991 #define RCC_APB1ENR_TIM5EN_Pos (3U)
9992 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
9993 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
9994 #define RCC_APB1ENR_TIM6EN_Pos (4U)
9995 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
9996 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
9997 #define RCC_APB1ENR_TIM7EN_Pos (5U)
9998 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
9999 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
10000 #define RCC_APB1ENR_TIM12EN_Pos (6U)
10001 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
10002 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
10003 #define RCC_APB1ENR_TIM13EN_Pos (7U)
10004 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
10005 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
10006 #define RCC_APB1ENR_TIM14EN_Pos (8U)
10007 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
10008 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
10009 #define RCC_APB1ENR_WWDGEN_Pos (11U)
10010 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
10011 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
10012 #define RCC_APB1ENR_SPI2EN_Pos (14U)
10013 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
10014 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
10015 #define RCC_APB1ENR_SPI3EN_Pos (15U)
10016 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
10017 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
10018 #define RCC_APB1ENR_USART2EN_Pos (17U)
10019 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
10020 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
10021 #define RCC_APB1ENR_USART3EN_Pos (18U)
10022 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
10023 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
10024 #define RCC_APB1ENR_UART4EN_Pos (19U)
10025 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
10026 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
10027 #define RCC_APB1ENR_UART5EN_Pos (20U)
10028 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
10029 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
10030 #define RCC_APB1ENR_I2C1EN_Pos (21U)
10031 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
10032 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
10033 #define RCC_APB1ENR_I2C2EN_Pos (22U)
10034 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
10035 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
10036 #define RCC_APB1ENR_I2C3EN_Pos (23U)
10037 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
10038 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
10039 #define RCC_APB1ENR_CAN1EN_Pos (25U)
10040 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
10041 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
10042 #define RCC_APB1ENR_CAN2EN_Pos (26U)
10043 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
10044 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
10045 #define RCC_APB1ENR_PWREN_Pos (28U)
10046 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
10047 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
10048 #define RCC_APB1ENR_DACEN_Pos (29U)
10049 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
10050 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
10051
10052 /******************** Bit definition for RCC_APB2ENR register ***************/
10053 #define RCC_APB2ENR_TIM1EN_Pos (0U)
10054 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
10055 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10056 #define RCC_APB2ENR_TIM8EN_Pos (1U)
10057 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
10058 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
10059 #define RCC_APB2ENR_USART1EN_Pos (4U)
10060 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
10061 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10062 #define RCC_APB2ENR_USART6EN_Pos (5U)
10063 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
10064 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
10065 #define RCC_APB2ENR_ADC1EN_Pos (8U)
10066 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
10067 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
10068 #define RCC_APB2ENR_ADC2EN_Pos (9U)
10069 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
10070 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
10071 #define RCC_APB2ENR_ADC3EN_Pos (10U)
10072 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
10073 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
10074 #define RCC_APB2ENR_SDIOEN_Pos (11U)
10075 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
10076 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
10077 #define RCC_APB2ENR_SPI1EN_Pos (12U)
10078 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
10079 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10080 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
10081 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
10082 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10083 #define RCC_APB2ENR_TIM9EN_Pos (16U)
10084 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
10085 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
10086 #define RCC_APB2ENR_TIM10EN_Pos (17U)
10087 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
10088 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
10089 #define RCC_APB2ENR_TIM11EN_Pos (18U)
10090 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
10091 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
10092
10093 /******************** Bit definition for RCC_AHB1LPENR register *************/
10094 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
10095 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
10096 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
10097 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
10098 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
10099 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
10100 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
10101 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
10102 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
10103 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
10104 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
10105 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
10106 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
10107 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
10108 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
10109 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
10110 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
10111 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
10112 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
10113 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
10114 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
10115 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
10116 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
10117 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
10118 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
10119 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
10120 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
10121 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
10122 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
10123 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
10124 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
10125 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
10126 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
10127 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
10128 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
10129 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
10130 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
10131 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
10132 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
10133 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
10134 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
10135 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
10136 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
10137 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
10138 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
10139 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
10140 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
10141 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
10142
10143 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
10144 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
10145 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
10146 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
10147 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
10148 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
10149 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
10150 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
10151 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
10152 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
10153 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
10154 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
10155 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
10156 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
10157 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
10158 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
10159 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
10160 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
10161
10162 /******************** Bit definition for RCC_AHB2LPENR register *************/
10163 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
10164 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
10165 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
10166 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
10167 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
10168 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
10169 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
10170 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
10171 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
10172
10173 /******************** Bit definition for RCC_AHB3LPENR register *************/
10174 #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
10175 #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
10176 #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
10177
10178 /******************** Bit definition for RCC_APB1LPENR register *************/
10179 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
10180 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
10181 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
10182 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
10183 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
10184 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
10185 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
10186 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
10187 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
10188 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
10189 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
10190 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
10191 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
10192 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
10193 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
10194 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
10195 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
10196 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
10197 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
10198 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
10199 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
10200 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
10201 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
10202 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
10203 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
10204 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
10205 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
10206 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
10207 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
10208 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
10209 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
10210 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
10211 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
10212 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
10213 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
10214 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
10215 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
10216 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
10217 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
10218 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
10219 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
10220 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
10221 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
10222 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
10223 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
10224 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
10225 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
10226 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
10227 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
10228 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
10229 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
10230 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
10231 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
10232 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
10233 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
10234 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
10235 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
10236 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10237 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
10238 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10239 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10240 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
10241 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10242 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10243 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
10244 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10245 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
10246 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
10247 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10248
10249 /******************** Bit definition for RCC_APB2LPENR register *************/
10250 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10251 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
10252 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10253 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10254 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
10255 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10256 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10257 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
10258 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10259 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10260 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
10261 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10262 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10263 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
10264 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10265 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
10266 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
10267 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
10268 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
10269 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
10270 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
10271 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
10272 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
10273 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
10274 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10275 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
10276 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10277 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10278 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
10279 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10280 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10281 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
10282 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10283 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10284 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
10285 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10286 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10287 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
10288 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10289
10290 /******************** Bit definition for RCC_BDCR register ******************/
10291 #define RCC_BDCR_LSEON_Pos (0U)
10292 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
10293 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10294 #define RCC_BDCR_LSERDY_Pos (1U)
10295 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
10296 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10297 #define RCC_BDCR_LSEBYP_Pos (2U)
10298 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
10299 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10300
10301 #define RCC_BDCR_RTCSEL_Pos (8U)
10302 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
10303 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10304 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
10305 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
10306
10307 #define RCC_BDCR_RTCEN_Pos (15U)
10308 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
10309 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10310 #define RCC_BDCR_BDRST_Pos (16U)
10311 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
10312 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10313
10314 /******************** Bit definition for RCC_CSR register *******************/
10315 #define RCC_CSR_LSION_Pos (0U)
10316 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
10317 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
10318 #define RCC_CSR_LSIRDY_Pos (1U)
10319 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
10320 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10321 #define RCC_CSR_RMVF_Pos (24U)
10322 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
10323 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10324 #define RCC_CSR_BORRSTF_Pos (25U)
10325 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
10326 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10327 #define RCC_CSR_PINRSTF_Pos (26U)
10328 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
10329 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10330 #define RCC_CSR_PORRSTF_Pos (27U)
10331 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
10332 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10333 #define RCC_CSR_SFTRSTF_Pos (28U)
10334 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
10335 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10336 #define RCC_CSR_IWDGRSTF_Pos (29U)
10337 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
10338 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10339 #define RCC_CSR_WWDGRSTF_Pos (30U)
10340 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
10341 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10342 #define RCC_CSR_LPWRRSTF_Pos (31U)
10343 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
10344 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10345 /* Legacy defines */
10346 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10347 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10348
10349 /******************** Bit definition for RCC_SSCGR register *****************/
10350 #define RCC_SSCGR_MODPER_Pos (0U)
10351 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
10352 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10353 #define RCC_SSCGR_INCSTEP_Pos (13U)
10354 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
10355 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10356 #define RCC_SSCGR_SPREADSEL_Pos (30U)
10357 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
10358 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10359 #define RCC_SSCGR_SSCGEN_Pos (31U)
10360 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
10361 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10362
10363 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
10364 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10365 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
10366 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10367 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
10368 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
10369 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
10370 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
10371 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
10372 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
10373 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
10374 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
10375 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
10376
10377 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10378 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
10379 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10380 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
10381 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
10382 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
10383
10384
10385 /******************************************************************************/
10386 /* */
10387 /* RNG */
10388 /* */
10389 /******************************************************************************/
10390 /******************** Bits definition for RNG_CR register *******************/
10391 #define RNG_CR_RNGEN_Pos (2U)
10392 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
10393 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10394 #define RNG_CR_IE_Pos (3U)
10395 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
10396 #define RNG_CR_IE RNG_CR_IE_Msk
10397
10398 /******************** Bits definition for RNG_SR register *******************/
10399 #define RNG_SR_DRDY_Pos (0U)
10400 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
10401 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
10402 #define RNG_SR_CECS_Pos (1U)
10403 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
10404 #define RNG_SR_CECS RNG_SR_CECS_Msk
10405 #define RNG_SR_SECS_Pos (2U)
10406 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
10407 #define RNG_SR_SECS RNG_SR_SECS_Msk
10408 #define RNG_SR_CEIS_Pos (5U)
10409 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
10410 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
10411 #define RNG_SR_SEIS_Pos (6U)
10412 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
10413 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
10414
10415 /******************************************************************************/
10416 /* */
10417 /* Real-Time Clock (RTC) */
10418 /* */
10419 /******************************************************************************/
10420 /*
10421 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10422 */
10423 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
10424 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
10425 /******************** Bits definition for RTC_TR register *******************/
10426 #define RTC_TR_PM_Pos (22U)
10427 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
10428 #define RTC_TR_PM RTC_TR_PM_Msk
10429 #define RTC_TR_HT_Pos (20U)
10430 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
10431 #define RTC_TR_HT RTC_TR_HT_Msk
10432 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
10433 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
10434 #define RTC_TR_HU_Pos (16U)
10435 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
10436 #define RTC_TR_HU RTC_TR_HU_Msk
10437 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
10438 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
10439 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
10440 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
10441 #define RTC_TR_MNT_Pos (12U)
10442 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
10443 #define RTC_TR_MNT RTC_TR_MNT_Msk
10444 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
10445 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
10446 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
10447 #define RTC_TR_MNU_Pos (8U)
10448 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
10449 #define RTC_TR_MNU RTC_TR_MNU_Msk
10450 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
10451 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
10452 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
10453 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
10454 #define RTC_TR_ST_Pos (4U)
10455 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
10456 #define RTC_TR_ST RTC_TR_ST_Msk
10457 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
10458 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
10459 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
10460 #define RTC_TR_SU_Pos (0U)
10461 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
10462 #define RTC_TR_SU RTC_TR_SU_Msk
10463 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
10464 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
10465 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
10466 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
10467
10468 /******************** Bits definition for RTC_DR register *******************/
10469 #define RTC_DR_YT_Pos (20U)
10470 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
10471 #define RTC_DR_YT RTC_DR_YT_Msk
10472 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
10473 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
10474 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
10475 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
10476 #define RTC_DR_YU_Pos (16U)
10477 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
10478 #define RTC_DR_YU RTC_DR_YU_Msk
10479 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
10480 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
10481 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
10482 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
10483 #define RTC_DR_WDU_Pos (13U)
10484 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
10485 #define RTC_DR_WDU RTC_DR_WDU_Msk
10486 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
10487 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
10488 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
10489 #define RTC_DR_MT_Pos (12U)
10490 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
10491 #define RTC_DR_MT RTC_DR_MT_Msk
10492 #define RTC_DR_MU_Pos (8U)
10493 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
10494 #define RTC_DR_MU RTC_DR_MU_Msk
10495 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
10496 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
10497 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
10498 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
10499 #define RTC_DR_DT_Pos (4U)
10500 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
10501 #define RTC_DR_DT RTC_DR_DT_Msk
10502 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
10503 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
10504 #define RTC_DR_DU_Pos (0U)
10505 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
10506 #define RTC_DR_DU RTC_DR_DU_Msk
10507 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
10508 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
10509 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
10510 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
10511
10512 /******************** Bits definition for RTC_CR register *******************/
10513 #define RTC_CR_COE_Pos (23U)
10514 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
10515 #define RTC_CR_COE RTC_CR_COE_Msk
10516 #define RTC_CR_OSEL_Pos (21U)
10517 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
10518 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
10519 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
10520 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
10521 #define RTC_CR_POL_Pos (20U)
10522 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
10523 #define RTC_CR_POL RTC_CR_POL_Msk
10524 #define RTC_CR_COSEL_Pos (19U)
10525 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
10526 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
10527 #define RTC_CR_BKP_Pos (18U)
10528 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
10529 #define RTC_CR_BKP RTC_CR_BKP_Msk
10530 #define RTC_CR_SUB1H_Pos (17U)
10531 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
10532 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10533 #define RTC_CR_ADD1H_Pos (16U)
10534 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
10535 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10536 #define RTC_CR_TSIE_Pos (15U)
10537 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
10538 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
10539 #define RTC_CR_WUTIE_Pos (14U)
10540 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
10541 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10542 #define RTC_CR_ALRBIE_Pos (13U)
10543 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
10544 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10545 #define RTC_CR_ALRAIE_Pos (12U)
10546 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
10547 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10548 #define RTC_CR_TSE_Pos (11U)
10549 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
10550 #define RTC_CR_TSE RTC_CR_TSE_Msk
10551 #define RTC_CR_WUTE_Pos (10U)
10552 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
10553 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
10554 #define RTC_CR_ALRBE_Pos (9U)
10555 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
10556 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10557 #define RTC_CR_ALRAE_Pos (8U)
10558 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
10559 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10560 #define RTC_CR_DCE_Pos (7U)
10561 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
10562 #define RTC_CR_DCE RTC_CR_DCE_Msk
10563 #define RTC_CR_FMT_Pos (6U)
10564 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
10565 #define RTC_CR_FMT RTC_CR_FMT_Msk
10566 #define RTC_CR_BYPSHAD_Pos (5U)
10567 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
10568 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10569 #define RTC_CR_REFCKON_Pos (4U)
10570 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
10571 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10572 #define RTC_CR_TSEDGE_Pos (3U)
10573 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
10574 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10575 #define RTC_CR_WUCKSEL_Pos (0U)
10576 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
10577 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10578 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
10579 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
10580 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
10581
10582 /* Legacy defines */
10583 #define RTC_CR_BCK RTC_CR_BKP
10584
10585 /******************** Bits definition for RTC_ISR register ******************/
10586 #define RTC_ISR_RECALPF_Pos (16U)
10587 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
10588 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10589 #define RTC_ISR_TAMP1F_Pos (13U)
10590 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
10591 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10592 #define RTC_ISR_TAMP2F_Pos (14U)
10593 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
10594 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10595 #define RTC_ISR_TSOVF_Pos (12U)
10596 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
10597 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10598 #define RTC_ISR_TSF_Pos (11U)
10599 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
10600 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
10601 #define RTC_ISR_WUTF_Pos (10U)
10602 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
10603 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10604 #define RTC_ISR_ALRBF_Pos (9U)
10605 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
10606 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10607 #define RTC_ISR_ALRAF_Pos (8U)
10608 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
10609 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10610 #define RTC_ISR_INIT_Pos (7U)
10611 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
10612 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
10613 #define RTC_ISR_INITF_Pos (6U)
10614 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
10615 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
10616 #define RTC_ISR_RSF_Pos (5U)
10617 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
10618 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
10619 #define RTC_ISR_INITS_Pos (4U)
10620 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
10621 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
10622 #define RTC_ISR_SHPF_Pos (3U)
10623 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
10624 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10625 #define RTC_ISR_WUTWF_Pos (2U)
10626 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
10627 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10628 #define RTC_ISR_ALRBWF_Pos (1U)
10629 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
10630 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10631 #define RTC_ISR_ALRAWF_Pos (0U)
10632 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
10633 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10634
10635 /******************** Bits definition for RTC_PRER register *****************/
10636 #define RTC_PRER_PREDIV_A_Pos (16U)
10637 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
10638 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10639 #define RTC_PRER_PREDIV_S_Pos (0U)
10640 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
10641 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10642
10643 /******************** Bits definition for RTC_WUTR register *****************/
10644 #define RTC_WUTR_WUT_Pos (0U)
10645 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
10646 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10647
10648 /******************** Bits definition for RTC_CALIBR register ***************/
10649 #define RTC_CALIBR_DCS_Pos (7U)
10650 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
10651 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10652 #define RTC_CALIBR_DC_Pos (0U)
10653 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
10654 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10655
10656 /******************** Bits definition for RTC_ALRMAR register ***************/
10657 #define RTC_ALRMAR_MSK4_Pos (31U)
10658 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
10659 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10660 #define RTC_ALRMAR_WDSEL_Pos (30U)
10661 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
10662 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10663 #define RTC_ALRMAR_DT_Pos (28U)
10664 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
10665 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10666 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
10667 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
10668 #define RTC_ALRMAR_DU_Pos (24U)
10669 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
10670 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10671 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
10672 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
10673 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
10674 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
10675 #define RTC_ALRMAR_MSK3_Pos (23U)
10676 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
10677 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10678 #define RTC_ALRMAR_PM_Pos (22U)
10679 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
10680 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10681 #define RTC_ALRMAR_HT_Pos (20U)
10682 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
10683 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10684 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
10685 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
10686 #define RTC_ALRMAR_HU_Pos (16U)
10687 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
10688 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10689 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
10690 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
10691 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
10692 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
10693 #define RTC_ALRMAR_MSK2_Pos (15U)
10694 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
10695 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10696 #define RTC_ALRMAR_MNT_Pos (12U)
10697 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
10698 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10699 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
10700 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
10701 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
10702 #define RTC_ALRMAR_MNU_Pos (8U)
10703 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
10704 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10705 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
10706 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
10707 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
10708 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
10709 #define RTC_ALRMAR_MSK1_Pos (7U)
10710 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
10711 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10712 #define RTC_ALRMAR_ST_Pos (4U)
10713 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
10714 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10715 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
10716 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
10717 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
10718 #define RTC_ALRMAR_SU_Pos (0U)
10719 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
10720 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10721 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
10722 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
10723 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
10724 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
10725
10726 /******************** Bits definition for RTC_ALRMBR register ***************/
10727 #define RTC_ALRMBR_MSK4_Pos (31U)
10728 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
10729 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10730 #define RTC_ALRMBR_WDSEL_Pos (30U)
10731 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
10732 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10733 #define RTC_ALRMBR_DT_Pos (28U)
10734 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
10735 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10736 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
10737 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
10738 #define RTC_ALRMBR_DU_Pos (24U)
10739 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
10740 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10741 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
10742 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
10743 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
10744 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
10745 #define RTC_ALRMBR_MSK3_Pos (23U)
10746 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
10747 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10748 #define RTC_ALRMBR_PM_Pos (22U)
10749 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
10750 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10751 #define RTC_ALRMBR_HT_Pos (20U)
10752 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
10753 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10754 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
10755 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
10756 #define RTC_ALRMBR_HU_Pos (16U)
10757 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
10758 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10759 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
10760 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
10761 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
10762 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
10763 #define RTC_ALRMBR_MSK2_Pos (15U)
10764 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
10765 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10766 #define RTC_ALRMBR_MNT_Pos (12U)
10767 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
10768 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10769 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
10770 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
10771 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
10772 #define RTC_ALRMBR_MNU_Pos (8U)
10773 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
10774 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10775 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
10776 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
10777 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
10778 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
10779 #define RTC_ALRMBR_MSK1_Pos (7U)
10780 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
10781 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10782 #define RTC_ALRMBR_ST_Pos (4U)
10783 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
10784 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10785 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
10786 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
10787 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
10788 #define RTC_ALRMBR_SU_Pos (0U)
10789 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
10790 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10791 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
10792 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
10793 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
10794 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
10795
10796 /******************** Bits definition for RTC_WPR register ******************/
10797 #define RTC_WPR_KEY_Pos (0U)
10798 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
10799 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
10800
10801 /******************** Bits definition for RTC_SSR register ******************/
10802 #define RTC_SSR_SS_Pos (0U)
10803 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
10804 #define RTC_SSR_SS RTC_SSR_SS_Msk
10805
10806 /******************** Bits definition for RTC_SHIFTR register ***************/
10807 #define RTC_SHIFTR_SUBFS_Pos (0U)
10808 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
10809 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10810 #define RTC_SHIFTR_ADD1S_Pos (31U)
10811 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
10812 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10813
10814 /******************** Bits definition for RTC_TSTR register *****************/
10815 #define RTC_TSTR_PM_Pos (22U)
10816 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
10817 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
10818 #define RTC_TSTR_HT_Pos (20U)
10819 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
10820 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
10821 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
10822 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
10823 #define RTC_TSTR_HU_Pos (16U)
10824 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
10825 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
10826 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
10827 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
10828 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
10829 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
10830 #define RTC_TSTR_MNT_Pos (12U)
10831 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
10832 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10833 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
10834 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
10835 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
10836 #define RTC_TSTR_MNU_Pos (8U)
10837 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
10838 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10839 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
10840 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
10841 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
10842 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
10843 #define RTC_TSTR_ST_Pos (4U)
10844 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
10845 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
10846 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
10847 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
10848 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
10849 #define RTC_TSTR_SU_Pos (0U)
10850 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
10851 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
10852 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
10853 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
10854 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
10855 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
10856
10857 /******************** Bits definition for RTC_TSDR register *****************/
10858 #define RTC_TSDR_WDU_Pos (13U)
10859 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
10860 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10861 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
10862 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
10863 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
10864 #define RTC_TSDR_MT_Pos (12U)
10865 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
10866 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
10867 #define RTC_TSDR_MU_Pos (8U)
10868 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
10869 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
10870 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
10871 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
10872 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
10873 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
10874 #define RTC_TSDR_DT_Pos (4U)
10875 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
10876 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
10877 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
10878 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
10879 #define RTC_TSDR_DU_Pos (0U)
10880 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
10881 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
10882 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
10883 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
10884 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
10885 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
10886
10887 /******************** Bits definition for RTC_TSSSR register ****************/
10888 #define RTC_TSSSR_SS_Pos (0U)
10889 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
10890 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10891
10892 /******************** Bits definition for RTC_CAL register *****************/
10893 #define RTC_CALR_CALP_Pos (15U)
10894 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
10895 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
10896 #define RTC_CALR_CALW8_Pos (14U)
10897 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
10898 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10899 #define RTC_CALR_CALW16_Pos (13U)
10900 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
10901 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10902 #define RTC_CALR_CALM_Pos (0U)
10903 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
10904 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
10905 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
10906 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
10907 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
10908 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
10909 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
10910 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
10911 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
10912 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
10913 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
10914
10915 /******************** Bits definition for RTC_TAFCR register ****************/
10916 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
10917 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
10918 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
10919 #define RTC_TAFCR_TSINSEL_Pos (17U)
10920 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
10921 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
10922 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
10923 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
10924 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
10925 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
10926 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
10927 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
10928 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
10929 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
10930 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
10931 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
10932 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
10933 #define RTC_TAFCR_TAMPFLT_Pos (11U)
10934 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
10935 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
10936 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
10937 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
10938 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
10939 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
10940 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
10941 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
10942 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
10943 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
10944 #define RTC_TAFCR_TAMPTS_Pos (7U)
10945 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
10946 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
10947 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
10948 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
10949 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
10950 #define RTC_TAFCR_TAMP2E_Pos (3U)
10951 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
10952 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
10953 #define RTC_TAFCR_TAMPIE_Pos (2U)
10954 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
10955 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
10956 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
10957 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
10958 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
10959 #define RTC_TAFCR_TAMP1E_Pos (0U)
10960 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
10961 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
10962
10963 /* Legacy defines */
10964 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
10965
10966 /******************** Bits definition for RTC_ALRMASSR register *************/
10967 #define RTC_ALRMASSR_MASKSS_Pos (24U)
10968 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
10969 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10970 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
10971 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
10972 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
10973 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
10974 #define RTC_ALRMASSR_SS_Pos (0U)
10975 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
10976 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10977
10978 /******************** Bits definition for RTC_ALRMBSSR register *************/
10979 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
10980 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
10981 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
10982 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
10983 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
10984 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
10985 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
10986 #define RTC_ALRMBSSR_SS_Pos (0U)
10987 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
10988 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
10989
10990 /******************** Bits definition for RTC_BKP0R register ****************/
10991 #define RTC_BKP0R_Pos (0U)
10992 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
10993 #define RTC_BKP0R RTC_BKP0R_Msk
10994
10995 /******************** Bits definition for RTC_BKP1R register ****************/
10996 #define RTC_BKP1R_Pos (0U)
10997 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
10998 #define RTC_BKP1R RTC_BKP1R_Msk
10999
11000 /******************** Bits definition for RTC_BKP2R register ****************/
11001 #define RTC_BKP2R_Pos (0U)
11002 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
11003 #define RTC_BKP2R RTC_BKP2R_Msk
11004
11005 /******************** Bits definition for RTC_BKP3R register ****************/
11006 #define RTC_BKP3R_Pos (0U)
11007 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
11008 #define RTC_BKP3R RTC_BKP3R_Msk
11009
11010 /******************** Bits definition for RTC_BKP4R register ****************/
11011 #define RTC_BKP4R_Pos (0U)
11012 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
11013 #define RTC_BKP4R RTC_BKP4R_Msk
11014
11015 /******************** Bits definition for RTC_BKP5R register ****************/
11016 #define RTC_BKP5R_Pos (0U)
11017 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
11018 #define RTC_BKP5R RTC_BKP5R_Msk
11019
11020 /******************** Bits definition for RTC_BKP6R register ****************/
11021 #define RTC_BKP6R_Pos (0U)
11022 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
11023 #define RTC_BKP6R RTC_BKP6R_Msk
11024
11025 /******************** Bits definition for RTC_BKP7R register ****************/
11026 #define RTC_BKP7R_Pos (0U)
11027 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
11028 #define RTC_BKP7R RTC_BKP7R_Msk
11029
11030 /******************** Bits definition for RTC_BKP8R register ****************/
11031 #define RTC_BKP8R_Pos (0U)
11032 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
11033 #define RTC_BKP8R RTC_BKP8R_Msk
11034
11035 /******************** Bits definition for RTC_BKP9R register ****************/
11036 #define RTC_BKP9R_Pos (0U)
11037 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
11038 #define RTC_BKP9R RTC_BKP9R_Msk
11039
11040 /******************** Bits definition for RTC_BKP10R register ***************/
11041 #define RTC_BKP10R_Pos (0U)
11042 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
11043 #define RTC_BKP10R RTC_BKP10R_Msk
11044
11045 /******************** Bits definition for RTC_BKP11R register ***************/
11046 #define RTC_BKP11R_Pos (0U)
11047 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
11048 #define RTC_BKP11R RTC_BKP11R_Msk
11049
11050 /******************** Bits definition for RTC_BKP12R register ***************/
11051 #define RTC_BKP12R_Pos (0U)
11052 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
11053 #define RTC_BKP12R RTC_BKP12R_Msk
11054
11055 /******************** Bits definition for RTC_BKP13R register ***************/
11056 #define RTC_BKP13R_Pos (0U)
11057 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
11058 #define RTC_BKP13R RTC_BKP13R_Msk
11059
11060 /******************** Bits definition for RTC_BKP14R register ***************/
11061 #define RTC_BKP14R_Pos (0U)
11062 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
11063 #define RTC_BKP14R RTC_BKP14R_Msk
11064
11065 /******************** Bits definition for RTC_BKP15R register ***************/
11066 #define RTC_BKP15R_Pos (0U)
11067 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
11068 #define RTC_BKP15R RTC_BKP15R_Msk
11069
11070 /******************** Bits definition for RTC_BKP16R register ***************/
11071 #define RTC_BKP16R_Pos (0U)
11072 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
11073 #define RTC_BKP16R RTC_BKP16R_Msk
11074
11075 /******************** Bits definition for RTC_BKP17R register ***************/
11076 #define RTC_BKP17R_Pos (0U)
11077 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
11078 #define RTC_BKP17R RTC_BKP17R_Msk
11079
11080 /******************** Bits definition for RTC_BKP18R register ***************/
11081 #define RTC_BKP18R_Pos (0U)
11082 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
11083 #define RTC_BKP18R RTC_BKP18R_Msk
11084
11085 /******************** Bits definition for RTC_BKP19R register ***************/
11086 #define RTC_BKP19R_Pos (0U)
11087 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
11088 #define RTC_BKP19R RTC_BKP19R_Msk
11089
11090 /******************** Number of backup registers ******************************/
11091 #define RTC_BKP_NUMBER 0x000000014U
11092
11093
11094 /******************************************************************************/
11095 /* */
11096 /* SD host Interface */
11097 /* */
11098 /******************************************************************************/
11099 /****************** Bit definition for SDIO_POWER register ******************/
11100 #define SDIO_POWER_PWRCTRL_Pos (0U)
11101 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
11102 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
11103 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
11104 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
11105
11106 /****************** Bit definition for SDIO_CLKCR register ******************/
11107 #define SDIO_CLKCR_CLKDIV_Pos (0U)
11108 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
11109 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
11110 #define SDIO_CLKCR_CLKEN_Pos (8U)
11111 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
11112 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
11113 #define SDIO_CLKCR_PWRSAV_Pos (9U)
11114 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
11115 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
11116 #define SDIO_CLKCR_BYPASS_Pos (10U)
11117 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
11118 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
11119
11120 #define SDIO_CLKCR_WIDBUS_Pos (11U)
11121 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
11122 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
11123 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
11124 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
11125
11126 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
11127 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
11128 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
11129 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
11130 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
11131 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
11132
11133 /******************* Bit definition for SDIO_ARG register *******************/
11134 #define SDIO_ARG_CMDARG_Pos (0U)
11135 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
11136 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
11137
11138 /******************* Bit definition for SDIO_CMD register *******************/
11139 #define SDIO_CMD_CMDINDEX_Pos (0U)
11140 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
11141 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
11142
11143 #define SDIO_CMD_WAITRESP_Pos (6U)
11144 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
11145 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
11146 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
11147 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
11148
11149 #define SDIO_CMD_WAITINT_Pos (8U)
11150 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
11151 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
11152 #define SDIO_CMD_WAITPEND_Pos (9U)
11153 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
11154 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
11155 #define SDIO_CMD_CPSMEN_Pos (10U)
11156 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
11157 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
11158 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
11159 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
11160 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
11161 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
11162 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
11163 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
11164 #define SDIO_CMD_NIEN_Pos (13U)
11165 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
11166 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
11167 #define SDIO_CMD_CEATACMD_Pos (14U)
11168 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
11169 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
11170
11171 /***************** Bit definition for SDIO_RESPCMD register *****************/
11172 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
11173 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
11174 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
11175
11176 /****************** Bit definition for SDIO_RESP0 register ******************/
11177 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
11178 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
11179 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
11180
11181 /****************** Bit definition for SDIO_RESP1 register ******************/
11182 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
11183 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
11184 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
11185
11186 /****************** Bit definition for SDIO_RESP2 register ******************/
11187 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
11188 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
11189 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
11190
11191 /****************** Bit definition for SDIO_RESP3 register ******************/
11192 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
11193 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
11194 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
11195
11196 /****************** Bit definition for SDIO_RESP4 register ******************/
11197 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
11198 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
11199 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
11200
11201 /****************** Bit definition for SDIO_DTIMER register *****************/
11202 #define SDIO_DTIMER_DATATIME_Pos (0U)
11203 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
11204 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
11205
11206 /****************** Bit definition for SDIO_DLEN register *******************/
11207 #define SDIO_DLEN_DATALENGTH_Pos (0U)
11208 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
11209 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
11210
11211 /****************** Bit definition for SDIO_DCTRL register ******************/
11212 #define SDIO_DCTRL_DTEN_Pos (0U)
11213 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
11214 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
11215 #define SDIO_DCTRL_DTDIR_Pos (1U)
11216 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
11217 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
11218 #define SDIO_DCTRL_DTMODE_Pos (2U)
11219 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
11220 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
11221 #define SDIO_DCTRL_DMAEN_Pos (3U)
11222 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
11223 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
11224
11225 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
11226 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
11227 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
11228 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
11229 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
11230 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
11231 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
11232
11233 #define SDIO_DCTRL_RWSTART_Pos (8U)
11234 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
11235 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
11236 #define SDIO_DCTRL_RWSTOP_Pos (9U)
11237 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
11238 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
11239 #define SDIO_DCTRL_RWMOD_Pos (10U)
11240 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
11241 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
11242 #define SDIO_DCTRL_SDIOEN_Pos (11U)
11243 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
11244 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
11245
11246 /****************** Bit definition for SDIO_DCOUNT register *****************/
11247 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
11248 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
11249 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
11250
11251 /****************** Bit definition for SDIO_STA register ********************/
11252 #define SDIO_STA_CCRCFAIL_Pos (0U)
11253 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
11254 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
11255 #define SDIO_STA_DCRCFAIL_Pos (1U)
11256 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
11257 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
11258 #define SDIO_STA_CTIMEOUT_Pos (2U)
11259 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
11260 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
11261 #define SDIO_STA_DTIMEOUT_Pos (3U)
11262 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
11263 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
11264 #define SDIO_STA_TXUNDERR_Pos (4U)
11265 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
11266 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
11267 #define SDIO_STA_RXOVERR_Pos (5U)
11268 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
11269 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
11270 #define SDIO_STA_CMDREND_Pos (6U)
11271 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
11272 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
11273 #define SDIO_STA_CMDSENT_Pos (7U)
11274 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
11275 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
11276 #define SDIO_STA_DATAEND_Pos (8U)
11277 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
11278 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
11279 #define SDIO_STA_STBITERR_Pos (9U)
11280 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
11281 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
11282 #define SDIO_STA_DBCKEND_Pos (10U)
11283 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
11284 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
11285 #define SDIO_STA_CMDACT_Pos (11U)
11286 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
11287 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
11288 #define SDIO_STA_TXACT_Pos (12U)
11289 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
11290 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
11291 #define SDIO_STA_RXACT_Pos (13U)
11292 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
11293 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
11294 #define SDIO_STA_TXFIFOHE_Pos (14U)
11295 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
11296 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
11297 #define SDIO_STA_RXFIFOHF_Pos (15U)
11298 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
11299 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
11300 #define SDIO_STA_TXFIFOF_Pos (16U)
11301 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
11302 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
11303 #define SDIO_STA_RXFIFOF_Pos (17U)
11304 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
11305 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
11306 #define SDIO_STA_TXFIFOE_Pos (18U)
11307 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
11308 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
11309 #define SDIO_STA_RXFIFOE_Pos (19U)
11310 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
11311 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
11312 #define SDIO_STA_TXDAVL_Pos (20U)
11313 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
11314 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
11315 #define SDIO_STA_RXDAVL_Pos (21U)
11316 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
11317 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
11318 #define SDIO_STA_SDIOIT_Pos (22U)
11319 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
11320 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
11321 #define SDIO_STA_CEATAEND_Pos (23U)
11322 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
11323 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
11324
11325 /******************* Bit definition for SDIO_ICR register *******************/
11326 #define SDIO_ICR_CCRCFAILC_Pos (0U)
11327 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
11328 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
11329 #define SDIO_ICR_DCRCFAILC_Pos (1U)
11330 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11331 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
11332 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
11333 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
11334 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
11335 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
11336 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
11337 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
11338 #define SDIO_ICR_TXUNDERRC_Pos (4U)
11339 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
11340 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
11341 #define SDIO_ICR_RXOVERRC_Pos (5U)
11342 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
11343 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
11344 #define SDIO_ICR_CMDRENDC_Pos (6U)
11345 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
11346 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
11347 #define SDIO_ICR_CMDSENTC_Pos (7U)
11348 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
11349 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
11350 #define SDIO_ICR_DATAENDC_Pos (8U)
11351 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
11352 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
11353 #define SDIO_ICR_STBITERRC_Pos (9U)
11354 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
11355 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
11356 #define SDIO_ICR_DBCKENDC_Pos (10U)
11357 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
11358 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
11359 #define SDIO_ICR_SDIOITC_Pos (22U)
11360 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
11361 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
11362 #define SDIO_ICR_CEATAENDC_Pos (23U)
11363 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
11364 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
11365
11366 /****************** Bit definition for SDIO_MASK register *******************/
11367 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
11368 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
11369 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
11370 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
11371 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
11372 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
11373 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
11374 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
11375 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
11376 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
11377 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
11378 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
11379 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
11380 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
11381 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
11382 #define SDIO_MASK_RXOVERRIE_Pos (5U)
11383 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
11384 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
11385 #define SDIO_MASK_CMDRENDIE_Pos (6U)
11386 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
11387 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
11388 #define SDIO_MASK_CMDSENTIE_Pos (7U)
11389 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
11390 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
11391 #define SDIO_MASK_DATAENDIE_Pos (8U)
11392 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
11393 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
11394 #define SDIO_MASK_STBITERRIE_Pos (9U)
11395 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
11396 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
11397 #define SDIO_MASK_DBCKENDIE_Pos (10U)
11398 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
11399 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
11400 #define SDIO_MASK_CMDACTIE_Pos (11U)
11401 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
11402 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
11403 #define SDIO_MASK_TXACTIE_Pos (12U)
11404 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
11405 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
11406 #define SDIO_MASK_RXACTIE_Pos (13U)
11407 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
11408 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
11409 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
11410 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
11411 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
11412 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
11413 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
11414 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
11415 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
11416 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
11417 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
11418 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
11419 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
11420 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
11421 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
11422 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
11423 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
11424 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
11425 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
11426 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
11427 #define SDIO_MASK_TXDAVLIE_Pos (20U)
11428 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
11429 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
11430 #define SDIO_MASK_RXDAVLIE_Pos (21U)
11431 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
11432 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
11433 #define SDIO_MASK_SDIOITIE_Pos (22U)
11434 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
11435 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
11436 #define SDIO_MASK_CEATAENDIE_Pos (23U)
11437 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
11438 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
11439
11440 /***************** Bit definition for SDIO_FIFOCNT register *****************/
11441 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
11442 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
11443 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
11444
11445 /****************** Bit definition for SDIO_FIFO register *******************/
11446 #define SDIO_FIFO_FIFODATA_Pos (0U)
11447 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
11448 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
11449
11450 /******************************************************************************/
11451 /* */
11452 /* Serial Peripheral Interface */
11453 /* */
11454 /******************************************************************************/
11455 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
11456
11457 /******************* Bit definition for SPI_CR1 register ********************/
11458 #define SPI_CR1_CPHA_Pos (0U)
11459 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
11460 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
11461 #define SPI_CR1_CPOL_Pos (1U)
11462 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
11463 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
11464 #define SPI_CR1_MSTR_Pos (2U)
11465 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
11466 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
11467
11468 #define SPI_CR1_BR_Pos (3U)
11469 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
11470 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
11471 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
11472 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
11473 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
11474
11475 #define SPI_CR1_SPE_Pos (6U)
11476 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
11477 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
11478 #define SPI_CR1_LSBFIRST_Pos (7U)
11479 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
11480 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
11481 #define SPI_CR1_SSI_Pos (8U)
11482 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
11483 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
11484 #define SPI_CR1_SSM_Pos (9U)
11485 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
11486 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
11487 #define SPI_CR1_RXONLY_Pos (10U)
11488 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
11489 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
11490 #define SPI_CR1_DFF_Pos (11U)
11491 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
11492 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
11493 #define SPI_CR1_CRCNEXT_Pos (12U)
11494 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
11495 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
11496 #define SPI_CR1_CRCEN_Pos (13U)
11497 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
11498 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
11499 #define SPI_CR1_BIDIOE_Pos (14U)
11500 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
11501 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
11502 #define SPI_CR1_BIDIMODE_Pos (15U)
11503 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
11504 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
11505
11506 /******************* Bit definition for SPI_CR2 register ********************/
11507 #define SPI_CR2_RXDMAEN_Pos (0U)
11508 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
11509 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
11510 #define SPI_CR2_TXDMAEN_Pos (1U)
11511 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
11512 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
11513 #define SPI_CR2_SSOE_Pos (2U)
11514 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
11515 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
11516 #define SPI_CR2_FRF_Pos (4U)
11517 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
11518 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
11519 #define SPI_CR2_ERRIE_Pos (5U)
11520 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
11521 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
11522 #define SPI_CR2_RXNEIE_Pos (6U)
11523 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
11524 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
11525 #define SPI_CR2_TXEIE_Pos (7U)
11526 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
11527 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
11528
11529 /******************** Bit definition for SPI_SR register ********************/
11530 #define SPI_SR_RXNE_Pos (0U)
11531 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
11532 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
11533 #define SPI_SR_TXE_Pos (1U)
11534 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
11535 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
11536 #define SPI_SR_CHSIDE_Pos (2U)
11537 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
11538 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
11539 #define SPI_SR_UDR_Pos (3U)
11540 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
11541 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
11542 #define SPI_SR_CRCERR_Pos (4U)
11543 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
11544 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
11545 #define SPI_SR_MODF_Pos (5U)
11546 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
11547 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
11548 #define SPI_SR_OVR_Pos (6U)
11549 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
11550 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
11551 #define SPI_SR_BSY_Pos (7U)
11552 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
11553 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
11554 #define SPI_SR_FRE_Pos (8U)
11555 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
11556 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
11557
11558 /******************** Bit definition for SPI_DR register ********************/
11559 #define SPI_DR_DR_Pos (0U)
11560 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
11561 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
11562
11563 /******************* Bit definition for SPI_CRCPR register ******************/
11564 #define SPI_CRCPR_CRCPOLY_Pos (0U)
11565 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
11566 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
11567
11568 /****************** Bit definition for SPI_RXCRCR register ******************/
11569 #define SPI_RXCRCR_RXCRC_Pos (0U)
11570 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
11571 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
11572
11573 /****************** Bit definition for SPI_TXCRCR register ******************/
11574 #define SPI_TXCRCR_TXCRC_Pos (0U)
11575 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
11576 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
11577
11578 /****************** Bit definition for SPI_I2SCFGR register *****************/
11579 #define SPI_I2SCFGR_CHLEN_Pos (0U)
11580 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
11581 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
11582
11583 #define SPI_I2SCFGR_DATLEN_Pos (1U)
11584 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
11585 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
11586 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
11587 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
11588
11589 #define SPI_I2SCFGR_CKPOL_Pos (3U)
11590 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
11591 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
11592
11593 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
11594 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
11595 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
11596 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
11597 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
11598
11599 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11600 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
11601 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
11602
11603 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
11604 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
11605 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
11606 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
11607 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
11608
11609 #define SPI_I2SCFGR_I2SE_Pos (10U)
11610 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
11611 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
11612 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
11613 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
11614 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
11615
11616 /****************** Bit definition for SPI_I2SPR register *******************/
11617 #define SPI_I2SPR_I2SDIV_Pos (0U)
11618 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
11619 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
11620 #define SPI_I2SPR_ODD_Pos (8U)
11621 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
11622 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
11623 #define SPI_I2SPR_MCKOE_Pos (9U)
11624 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
11625 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
11626
11627 /******************************************************************************/
11628 /* */
11629 /* SYSCFG */
11630 /* */
11631 /******************************************************************************/
11632 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
11633 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11634 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
11635 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
11636 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
11637 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
11638 /****************** Bit definition for SYSCFG_PMC register ******************/
11639 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
11640 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
11641 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
11642 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
11643 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
11644
11645 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
11646 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11647 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
11648 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
11649 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11650 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
11651 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
11652 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11653 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
11654 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
11655 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11656 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
11657 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
11658 /**
11659 * @brief EXTI0 configuration
11660 */
11661 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
11662 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
11663 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
11664 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
11665 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
11666 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
11667 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
11668 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
11669 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
11670
11671 /**
11672 * @brief EXTI1 configuration
11673 */
11674 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
11675 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
11676 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
11677 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
11678 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
11679 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
11680 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
11681 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
11682 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
11683
11684 /**
11685 * @brief EXTI2 configuration
11686 */
11687 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
11688 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
11689 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
11690 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
11691 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
11692 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
11693 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
11694 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
11695 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
11696
11697 /**
11698 * @brief EXTI3 configuration
11699 */
11700 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
11701 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
11702 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
11703 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
11704 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
11705 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
11706 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
11707 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
11708 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
11709
11710 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
11711 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11712 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
11713 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
11714 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11715 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
11716 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
11717 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11718 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
11719 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
11720 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11721 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
11722 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
11723
11724 /**
11725 * @brief EXTI4 configuration
11726 */
11727 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
11728 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
11729 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
11730 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
11731 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
11732 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
11733 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
11734 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
11735 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
11736
11737 /**
11738 * @brief EXTI5 configuration
11739 */
11740 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
11741 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
11742 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
11743 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
11744 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
11745 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
11746 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
11747 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
11748 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
11749
11750 /**
11751 * @brief EXTI6 configuration
11752 */
11753 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
11754 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
11755 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
11756 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
11757 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
11758 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
11759 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
11760 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
11761 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
11762
11763 /**
11764 * @brief EXTI7 configuration
11765 */
11766 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
11767 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
11768 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
11769 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
11770 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
11771 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
11772 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
11773 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
11774 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
11775
11776 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
11777 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
11778 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
11779 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
11780 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
11781 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
11782 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
11783 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
11784 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
11785 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
11786 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
11787 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
11788 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
11789
11790 /**
11791 * @brief EXTI8 configuration
11792 */
11793 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
11794 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
11795 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
11796 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
11797 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
11798 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
11799 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
11800 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
11801 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
11802
11803 /**
11804 * @brief EXTI9 configuration
11805 */
11806 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
11807 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
11808 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
11809 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
11810 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
11811 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
11812 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
11813 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
11814 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
11815
11816 /**
11817 * @brief EXTI10 configuration
11818 */
11819 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
11820 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
11821 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
11822 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
11823 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
11824 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
11825 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
11826 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
11827 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
11828
11829 /**
11830 * @brief EXTI11 configuration
11831 */
11832 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
11833 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
11834 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
11835 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
11836 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
11837 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
11838 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
11839 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
11840 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
11841
11842 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
11843 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
11844 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
11845 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
11846 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
11847 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
11848 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
11849 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
11850 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
11851 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
11852 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
11853 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
11854 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
11855
11856 /**
11857 * @brief EXTI12 configuration
11858 */
11859 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
11860 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
11861 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
11862 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
11863 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
11864 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
11865 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
11866 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
11867
11868 /**
11869 * @brief EXTI13 configuration
11870 */
11871 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
11872 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
11873 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
11874 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
11875 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
11876 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
11877 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
11878 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
11879
11880 /**
11881 * @brief EXTI14 configuration
11882 */
11883 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
11884 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
11885 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
11886 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
11887 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
11888 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
11889 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
11890 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
11891
11892 /**
11893 * @brief EXTI15 configuration
11894 */
11895 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
11896 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
11897 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
11898 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
11899 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
11900 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
11901 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
11902 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
11903
11904 /****************** Bit definition for SYSCFG_CMPCR register ****************/
11905 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
11906 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
11907 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
11908 #define SYSCFG_CMPCR_READY_Pos (8U)
11909 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
11910 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
11911
11912 /******************************************************************************/
11913 /* */
11914 /* TIM */
11915 /* */
11916 /******************************************************************************/
11917 /******************* Bit definition for TIM_CR1 register ********************/
11918 #define TIM_CR1_CEN_Pos (0U)
11919 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
11920 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
11921 #define TIM_CR1_UDIS_Pos (1U)
11922 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
11923 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
11924 #define TIM_CR1_URS_Pos (2U)
11925 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
11926 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
11927 #define TIM_CR1_OPM_Pos (3U)
11928 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
11929 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
11930 #define TIM_CR1_DIR_Pos (4U)
11931 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
11932 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
11933
11934 #define TIM_CR1_CMS_Pos (5U)
11935 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
11936 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
11937 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
11938 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
11939
11940 #define TIM_CR1_ARPE_Pos (7U)
11941 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
11942 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
11943
11944 #define TIM_CR1_CKD_Pos (8U)
11945 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
11946 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
11947 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
11948 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
11949
11950 /******************* Bit definition for TIM_CR2 register ********************/
11951 #define TIM_CR2_CCPC_Pos (0U)
11952 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
11953 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
11954 #define TIM_CR2_CCUS_Pos (2U)
11955 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
11956 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
11957 #define TIM_CR2_CCDS_Pos (3U)
11958 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
11959 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
11960
11961 #define TIM_CR2_MMS_Pos (4U)
11962 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
11963 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
11964 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
11965 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
11966 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
11967
11968 #define TIM_CR2_TI1S_Pos (7U)
11969 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
11970 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
11971 #define TIM_CR2_OIS1_Pos (8U)
11972 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
11973 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
11974 #define TIM_CR2_OIS1N_Pos (9U)
11975 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
11976 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
11977 #define TIM_CR2_OIS2_Pos (10U)
11978 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
11979 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
11980 #define TIM_CR2_OIS2N_Pos (11U)
11981 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
11982 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
11983 #define TIM_CR2_OIS3_Pos (12U)
11984 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
11985 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
11986 #define TIM_CR2_OIS3N_Pos (13U)
11987 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
11988 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
11989 #define TIM_CR2_OIS4_Pos (14U)
11990 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
11991 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
11992
11993 /******************* Bit definition for TIM_SMCR register *******************/
11994 #define TIM_SMCR_SMS_Pos (0U)
11995 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
11996 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
11997 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
11998 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
11999 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
12000
12001 #define TIM_SMCR_TS_Pos (4U)
12002 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
12003 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
12004 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
12005 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
12006 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
12007
12008 #define TIM_SMCR_MSM_Pos (7U)
12009 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
12010 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
12011
12012 #define TIM_SMCR_ETF_Pos (8U)
12013 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
12014 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
12015 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
12016 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
12017 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
12018 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
12019
12020 #define TIM_SMCR_ETPS_Pos (12U)
12021 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
12022 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
12023 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
12024 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
12025
12026 #define TIM_SMCR_ECE_Pos (14U)
12027 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
12028 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
12029 #define TIM_SMCR_ETP_Pos (15U)
12030 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
12031 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
12032
12033 /******************* Bit definition for TIM_DIER register *******************/
12034 #define TIM_DIER_UIE_Pos (0U)
12035 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
12036 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
12037 #define TIM_DIER_CC1IE_Pos (1U)
12038 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
12039 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
12040 #define TIM_DIER_CC2IE_Pos (2U)
12041 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
12042 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
12043 #define TIM_DIER_CC3IE_Pos (3U)
12044 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
12045 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
12046 #define TIM_DIER_CC4IE_Pos (4U)
12047 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
12048 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
12049 #define TIM_DIER_COMIE_Pos (5U)
12050 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
12051 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
12052 #define TIM_DIER_TIE_Pos (6U)
12053 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
12054 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
12055 #define TIM_DIER_BIE_Pos (7U)
12056 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
12057 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
12058 #define TIM_DIER_UDE_Pos (8U)
12059 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
12060 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
12061 #define TIM_DIER_CC1DE_Pos (9U)
12062 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
12063 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
12064 #define TIM_DIER_CC2DE_Pos (10U)
12065 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
12066 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
12067 #define TIM_DIER_CC3DE_Pos (11U)
12068 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
12069 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
12070 #define TIM_DIER_CC4DE_Pos (12U)
12071 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
12072 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
12073 #define TIM_DIER_COMDE_Pos (13U)
12074 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
12075 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
12076 #define TIM_DIER_TDE_Pos (14U)
12077 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
12078 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
12079
12080 /******************** Bit definition for TIM_SR register ********************/
12081 #define TIM_SR_UIF_Pos (0U)
12082 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
12083 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
12084 #define TIM_SR_CC1IF_Pos (1U)
12085 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
12086 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
12087 #define TIM_SR_CC2IF_Pos (2U)
12088 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
12089 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
12090 #define TIM_SR_CC3IF_Pos (3U)
12091 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
12092 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
12093 #define TIM_SR_CC4IF_Pos (4U)
12094 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
12095 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
12096 #define TIM_SR_COMIF_Pos (5U)
12097 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
12098 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
12099 #define TIM_SR_TIF_Pos (6U)
12100 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
12101 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
12102 #define TIM_SR_BIF_Pos (7U)
12103 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
12104 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
12105 #define TIM_SR_CC1OF_Pos (9U)
12106 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
12107 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
12108 #define TIM_SR_CC2OF_Pos (10U)
12109 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
12110 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
12111 #define TIM_SR_CC3OF_Pos (11U)
12112 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
12113 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
12114 #define TIM_SR_CC4OF_Pos (12U)
12115 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
12116 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
12117
12118 /******************* Bit definition for TIM_EGR register ********************/
12119 #define TIM_EGR_UG_Pos (0U)
12120 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
12121 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
12122 #define TIM_EGR_CC1G_Pos (1U)
12123 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
12124 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
12125 #define TIM_EGR_CC2G_Pos (2U)
12126 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
12127 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
12128 #define TIM_EGR_CC3G_Pos (3U)
12129 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
12130 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
12131 #define TIM_EGR_CC4G_Pos (4U)
12132 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
12133 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
12134 #define TIM_EGR_COMG_Pos (5U)
12135 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
12136 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
12137 #define TIM_EGR_TG_Pos (6U)
12138 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
12139 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
12140 #define TIM_EGR_BG_Pos (7U)
12141 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
12142 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
12143
12144 /****************** Bit definition for TIM_CCMR1 register *******************/
12145 #define TIM_CCMR1_CC1S_Pos (0U)
12146 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
12147 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
12148 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
12149 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
12150
12151 #define TIM_CCMR1_OC1FE_Pos (2U)
12152 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
12153 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
12154 #define TIM_CCMR1_OC1PE_Pos (3U)
12155 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
12156 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
12157
12158 #define TIM_CCMR1_OC1M_Pos (4U)
12159 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
12160 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
12161 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
12162 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
12163 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
12164
12165 #define TIM_CCMR1_OC1CE_Pos (7U)
12166 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
12167 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
12168
12169 #define TIM_CCMR1_CC2S_Pos (8U)
12170 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
12171 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
12172 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
12173 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
12174
12175 #define TIM_CCMR1_OC2FE_Pos (10U)
12176 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
12177 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
12178 #define TIM_CCMR1_OC2PE_Pos (11U)
12179 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
12180 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
12181
12182 #define TIM_CCMR1_OC2M_Pos (12U)
12183 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
12184 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
12185 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
12186 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
12187 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
12188
12189 #define TIM_CCMR1_OC2CE_Pos (15U)
12190 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
12191 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
12192
12193 /*----------------------------------------------------------------------------*/
12194
12195 #define TIM_CCMR1_IC1PSC_Pos (2U)
12196 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
12197 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
12198 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
12199 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
12200
12201 #define TIM_CCMR1_IC1F_Pos (4U)
12202 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
12203 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
12204 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
12205 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
12206 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
12207 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
12208
12209 #define TIM_CCMR1_IC2PSC_Pos (10U)
12210 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
12211 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
12212 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
12213 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
12214
12215 #define TIM_CCMR1_IC2F_Pos (12U)
12216 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
12217 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
12218 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
12219 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
12220 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
12221 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
12222
12223 /****************** Bit definition for TIM_CCMR2 register *******************/
12224 #define TIM_CCMR2_CC3S_Pos (0U)
12225 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
12226 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
12227 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
12228 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
12229
12230 #define TIM_CCMR2_OC3FE_Pos (2U)
12231 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
12232 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
12233 #define TIM_CCMR2_OC3PE_Pos (3U)
12234 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
12235 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
12236
12237 #define TIM_CCMR2_OC3M_Pos (4U)
12238 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
12239 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
12240 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
12241 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
12242 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
12243
12244 #define TIM_CCMR2_OC3CE_Pos (7U)
12245 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
12246 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
12247
12248 #define TIM_CCMR2_CC4S_Pos (8U)
12249 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
12250 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
12251 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
12252 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
12253
12254 #define TIM_CCMR2_OC4FE_Pos (10U)
12255 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
12256 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
12257 #define TIM_CCMR2_OC4PE_Pos (11U)
12258 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
12259 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
12260
12261 #define TIM_CCMR2_OC4M_Pos (12U)
12262 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
12263 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
12264 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
12265 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
12266 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
12267
12268 #define TIM_CCMR2_OC4CE_Pos (15U)
12269 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
12270 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
12271
12272 /*----------------------------------------------------------------------------*/
12273
12274 #define TIM_CCMR2_IC3PSC_Pos (2U)
12275 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
12276 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
12277 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
12278 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
12279
12280 #define TIM_CCMR2_IC3F_Pos (4U)
12281 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
12282 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
12283 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
12284 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
12285 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
12286 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
12287
12288 #define TIM_CCMR2_IC4PSC_Pos (10U)
12289 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
12290 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
12291 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
12292 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
12293
12294 #define TIM_CCMR2_IC4F_Pos (12U)
12295 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
12296 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
12297 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
12298 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
12299 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
12300 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
12301
12302 /******************* Bit definition for TIM_CCER register *******************/
12303 #define TIM_CCER_CC1E_Pos (0U)
12304 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
12305 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
12306 #define TIM_CCER_CC1P_Pos (1U)
12307 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
12308 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
12309 #define TIM_CCER_CC1NE_Pos (2U)
12310 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
12311 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
12312 #define TIM_CCER_CC1NP_Pos (3U)
12313 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
12314 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
12315 #define TIM_CCER_CC2E_Pos (4U)
12316 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
12317 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
12318 #define TIM_CCER_CC2P_Pos (5U)
12319 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
12320 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
12321 #define TIM_CCER_CC2NE_Pos (6U)
12322 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
12323 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
12324 #define TIM_CCER_CC2NP_Pos (7U)
12325 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
12326 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
12327 #define TIM_CCER_CC3E_Pos (8U)
12328 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
12329 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
12330 #define TIM_CCER_CC3P_Pos (9U)
12331 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
12332 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
12333 #define TIM_CCER_CC3NE_Pos (10U)
12334 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
12335 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
12336 #define TIM_CCER_CC3NP_Pos (11U)
12337 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
12338 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
12339 #define TIM_CCER_CC4E_Pos (12U)
12340 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
12341 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
12342 #define TIM_CCER_CC4P_Pos (13U)
12343 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
12344 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
12345 #define TIM_CCER_CC4NP_Pos (15U)
12346 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
12347 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
12348
12349 /******************* Bit definition for TIM_CNT register ********************/
12350 #define TIM_CNT_CNT_Pos (0U)
12351 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
12352 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
12353
12354 /******************* Bit definition for TIM_PSC register ********************/
12355 #define TIM_PSC_PSC_Pos (0U)
12356 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
12357 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
12358
12359 /******************* Bit definition for TIM_ARR register ********************/
12360 #define TIM_ARR_ARR_Pos (0U)
12361 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
12362 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
12363
12364 /******************* Bit definition for TIM_RCR register ********************/
12365 #define TIM_RCR_REP_Pos (0U)
12366 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
12367 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
12368
12369 /******************* Bit definition for TIM_CCR1 register *******************/
12370 #define TIM_CCR1_CCR1_Pos (0U)
12371 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
12372 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
12373
12374 /******************* Bit definition for TIM_CCR2 register *******************/
12375 #define TIM_CCR2_CCR2_Pos (0U)
12376 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
12377 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
12378
12379 /******************* Bit definition for TIM_CCR3 register *******************/
12380 #define TIM_CCR3_CCR3_Pos (0U)
12381 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
12382 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
12383
12384 /******************* Bit definition for TIM_CCR4 register *******************/
12385 #define TIM_CCR4_CCR4_Pos (0U)
12386 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
12387 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
12388
12389 /******************* Bit definition for TIM_BDTR register *******************/
12390 #define TIM_BDTR_DTG_Pos (0U)
12391 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
12392 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
12393 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
12394 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
12395 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
12396 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
12397 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
12398 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
12399 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
12400 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
12401
12402 #define TIM_BDTR_LOCK_Pos (8U)
12403 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
12404 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
12405 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
12406 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
12407
12408 #define TIM_BDTR_OSSI_Pos (10U)
12409 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
12410 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
12411 #define TIM_BDTR_OSSR_Pos (11U)
12412 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
12413 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
12414 #define TIM_BDTR_BKE_Pos (12U)
12415 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
12416 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
12417 #define TIM_BDTR_BKP_Pos (13U)
12418 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
12419 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
12420 #define TIM_BDTR_AOE_Pos (14U)
12421 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
12422 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
12423 #define TIM_BDTR_MOE_Pos (15U)
12424 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
12425 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
12426
12427 /******************* Bit definition for TIM_DCR register ********************/
12428 #define TIM_DCR_DBA_Pos (0U)
12429 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
12430 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
12431 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
12432 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
12433 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
12434 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
12435 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
12436
12437 #define TIM_DCR_DBL_Pos (8U)
12438 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
12439 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
12440 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
12441 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
12442 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
12443 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
12444 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
12445
12446 /******************* Bit definition for TIM_DMAR register *******************/
12447 #define TIM_DMAR_DMAB_Pos (0U)
12448 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
12449 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
12450
12451 /******************* Bit definition for TIM_OR register *********************/
12452 #define TIM_OR_TI1_RMP_Pos (0U)
12453 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
12454 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
12455 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
12456 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
12457
12458 #define TIM_OR_TI4_RMP_Pos (6U)
12459 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
12460 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
12461 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
12462 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
12463 #define TIM_OR_ITR1_RMP_Pos (10U)
12464 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
12465 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
12466 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
12467 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
12468
12469
12470 /******************************************************************************/
12471 /* */
12472 /* Universal Synchronous Asynchronous Receiver Transmitter */
12473 /* */
12474 /******************************************************************************/
12475 /******************* Bit definition for USART_SR register *******************/
12476 #define USART_SR_PE_Pos (0U)
12477 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
12478 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
12479 #define USART_SR_FE_Pos (1U)
12480 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
12481 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
12482 #define USART_SR_NE_Pos (2U)
12483 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
12484 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
12485 #define USART_SR_ORE_Pos (3U)
12486 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
12487 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
12488 #define USART_SR_IDLE_Pos (4U)
12489 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
12490 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
12491 #define USART_SR_RXNE_Pos (5U)
12492 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
12493 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
12494 #define USART_SR_TC_Pos (6U)
12495 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
12496 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
12497 #define USART_SR_TXE_Pos (7U)
12498 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
12499 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
12500 #define USART_SR_LBD_Pos (8U)
12501 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
12502 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
12503 #define USART_SR_CTS_Pos (9U)
12504 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
12505 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
12506
12507 /******************* Bit definition for USART_DR register *******************/
12508 #define USART_DR_DR_Pos (0U)
12509 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
12510 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
12511
12512 /****************** Bit definition for USART_BRR register *******************/
12513 #define USART_BRR_DIV_Fraction_Pos (0U)
12514 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
12515 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
12516 #define USART_BRR_DIV_Mantissa_Pos (4U)
12517 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
12518 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
12519
12520 /****************** Bit definition for USART_CR1 register *******************/
12521 #define USART_CR1_SBK_Pos (0U)
12522 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
12523 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
12524 #define USART_CR1_RWU_Pos (1U)
12525 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
12526 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
12527 #define USART_CR1_RE_Pos (2U)
12528 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
12529 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
12530 #define USART_CR1_TE_Pos (3U)
12531 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
12532 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
12533 #define USART_CR1_IDLEIE_Pos (4U)
12534 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
12535 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
12536 #define USART_CR1_RXNEIE_Pos (5U)
12537 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
12538 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
12539 #define USART_CR1_TCIE_Pos (6U)
12540 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
12541 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
12542 #define USART_CR1_TXEIE_Pos (7U)
12543 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
12544 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
12545 #define USART_CR1_PEIE_Pos (8U)
12546 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
12547 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
12548 #define USART_CR1_PS_Pos (9U)
12549 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
12550 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
12551 #define USART_CR1_PCE_Pos (10U)
12552 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
12553 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
12554 #define USART_CR1_WAKE_Pos (11U)
12555 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
12556 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
12557 #define USART_CR1_M_Pos (12U)
12558 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
12559 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
12560 #define USART_CR1_UE_Pos (13U)
12561 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
12562 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
12563 #define USART_CR1_OVER8_Pos (15U)
12564 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
12565 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
12566
12567 /****************** Bit definition for USART_CR2 register *******************/
12568 #define USART_CR2_ADD_Pos (0U)
12569 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
12570 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
12571 #define USART_CR2_LBDL_Pos (5U)
12572 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
12573 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
12574 #define USART_CR2_LBDIE_Pos (6U)
12575 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
12576 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
12577 #define USART_CR2_LBCL_Pos (8U)
12578 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
12579 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
12580 #define USART_CR2_CPHA_Pos (9U)
12581 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
12582 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
12583 #define USART_CR2_CPOL_Pos (10U)
12584 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
12585 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
12586 #define USART_CR2_CLKEN_Pos (11U)
12587 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
12588 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
12589
12590 #define USART_CR2_STOP_Pos (12U)
12591 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
12592 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
12593 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
12594 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
12595
12596 #define USART_CR2_LINEN_Pos (14U)
12597 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
12598 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
12599
12600 /****************** Bit definition for USART_CR3 register *******************/
12601 #define USART_CR3_EIE_Pos (0U)
12602 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
12603 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
12604 #define USART_CR3_IREN_Pos (1U)
12605 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
12606 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
12607 #define USART_CR3_IRLP_Pos (2U)
12608 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
12609 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
12610 #define USART_CR3_HDSEL_Pos (3U)
12611 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
12612 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
12613 #define USART_CR3_NACK_Pos (4U)
12614 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
12615 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
12616 #define USART_CR3_SCEN_Pos (5U)
12617 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
12618 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
12619 #define USART_CR3_DMAR_Pos (6U)
12620 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
12621 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
12622 #define USART_CR3_DMAT_Pos (7U)
12623 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
12624 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
12625 #define USART_CR3_RTSE_Pos (8U)
12626 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
12627 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
12628 #define USART_CR3_CTSE_Pos (9U)
12629 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
12630 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
12631 #define USART_CR3_CTSIE_Pos (10U)
12632 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
12633 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
12634 #define USART_CR3_ONEBIT_Pos (11U)
12635 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
12636 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
12637
12638 /****************** Bit definition for USART_GTPR register ******************/
12639 #define USART_GTPR_PSC_Pos (0U)
12640 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
12641 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
12642 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
12643 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
12644 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
12645 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
12646 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
12647 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
12648 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
12649 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
12650
12651 #define USART_GTPR_GT_Pos (8U)
12652 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
12653 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
12654
12655 /******************************************************************************/
12656 /* */
12657 /* Window WATCHDOG */
12658 /* */
12659 /******************************************************************************/
12660 /******************* Bit definition for WWDG_CR register ********************/
12661 #define WWDG_CR_T_Pos (0U)
12662 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
12663 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
12664 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
12665 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
12666 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
12667 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
12668 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
12669 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
12670 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
12671 /* Legacy defines */
12672 #define WWDG_CR_T0 WWDG_CR_T_0
12673 #define WWDG_CR_T1 WWDG_CR_T_1
12674 #define WWDG_CR_T2 WWDG_CR_T_2
12675 #define WWDG_CR_T3 WWDG_CR_T_3
12676 #define WWDG_CR_T4 WWDG_CR_T_4
12677 #define WWDG_CR_T5 WWDG_CR_T_5
12678 #define WWDG_CR_T6 WWDG_CR_T_6
12679
12680 #define WWDG_CR_WDGA_Pos (7U)
12681 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
12682 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
12683
12684 /******************* Bit definition for WWDG_CFR register *******************/
12685 #define WWDG_CFR_W_Pos (0U)
12686 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
12687 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
12688 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
12689 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
12690 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
12691 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
12692 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
12693 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
12694 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
12695 /* Legacy defines */
12696 #define WWDG_CFR_W0 WWDG_CFR_W_0
12697 #define WWDG_CFR_W1 WWDG_CFR_W_1
12698 #define WWDG_CFR_W2 WWDG_CFR_W_2
12699 #define WWDG_CFR_W3 WWDG_CFR_W_3
12700 #define WWDG_CFR_W4 WWDG_CFR_W_4
12701 #define WWDG_CFR_W5 WWDG_CFR_W_5
12702 #define WWDG_CFR_W6 WWDG_CFR_W_6
12703
12704 #define WWDG_CFR_WDGTB_Pos (7U)
12705 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
12706 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
12707 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
12708 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
12709 /* Legacy defines */
12710 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
12711 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
12712
12713 #define WWDG_CFR_EWI_Pos (9U)
12714 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
12715 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
12716
12717 /******************* Bit definition for WWDG_SR register ********************/
12718 #define WWDG_SR_EWIF_Pos (0U)
12719 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
12720 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
12721
12722
12723 /******************************************************************************/
12724 /* */
12725 /* DBG */
12726 /* */
12727 /******************************************************************************/
12728 /******************** Bit definition for DBGMCU_IDCODE register *************/
12729 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
12730 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
12731 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
12732 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
12733 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
12734 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
12735
12736 /******************** Bit definition for DBGMCU_CR register *****************/
12737 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
12738 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
12739 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
12740 #define DBGMCU_CR_DBG_STOP_Pos (1U)
12741 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
12742 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
12743 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
12744 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
12745 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
12746 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
12747 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
12748 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
12749
12750 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
12751 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
12752 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
12753 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
12754 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
12755
12756 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
12757 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
12758 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
12759 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
12760 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
12761 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
12762 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
12763 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
12764 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
12765 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
12766 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
12767 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
12768 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
12769 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
12770 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
12771 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
12772 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
12773 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
12774 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
12775 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
12776 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
12777 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
12778 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
12779 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
12780 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
12781 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
12782 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
12783 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
12784 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
12785 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
12786 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
12787 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
12788 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
12789 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
12790 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
12791 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
12792 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
12793 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
12794 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
12795 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
12796 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
12797 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
12798 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
12799 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
12800 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
12801 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
12802 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
12803 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
12804 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
12805 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
12806 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
12807 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
12808 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
12809 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
12810
12811 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
12812 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
12813 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
12814 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
12815 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
12816 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
12817 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
12818 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
12819 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
12820 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
12821 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
12822 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
12823 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
12824 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
12825 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
12826 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
12827
12828 /******************************************************************************/
12829 /* */
12830 /* Ethernet MAC Registers bits definitions */
12831 /* */
12832 /******************************************************************************/
12833 /* Bit definition for Ethernet MAC Control Register register */
12834 #define ETH_MACCR_WD_Pos (23U)
12835 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
12836 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
12837 #define ETH_MACCR_JD_Pos (22U)
12838 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
12839 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
12840 #define ETH_MACCR_IFG_Pos (17U)
12841 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
12842 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
12843 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
12844 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
12845 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
12846 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
12847 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
12848 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
12849 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
12850 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
12851 #define ETH_MACCR_CSD_Pos (16U)
12852 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
12853 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
12854 #define ETH_MACCR_FES_Pos (14U)
12855 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
12856 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
12857 #define ETH_MACCR_ROD_Pos (13U)
12858 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
12859 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
12860 #define ETH_MACCR_LM_Pos (12U)
12861 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
12862 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
12863 #define ETH_MACCR_DM_Pos (11U)
12864 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
12865 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
12866 #define ETH_MACCR_IPCO_Pos (10U)
12867 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
12868 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
12869 #define ETH_MACCR_RD_Pos (9U)
12870 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
12871 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
12872 #define ETH_MACCR_APCS_Pos (7U)
12873 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
12874 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
12875 #define ETH_MACCR_BL_Pos (5U)
12876 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
12877 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
12878 a transmission attempt during retries after a collision: 0 =< r <2^k */
12879 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
12880 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
12881 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
12882 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
12883 #define ETH_MACCR_DC_Pos (4U)
12884 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
12885 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
12886 #define ETH_MACCR_TE_Pos (3U)
12887 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
12888 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
12889 #define ETH_MACCR_RE_Pos (2U)
12890 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
12891 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
12892
12893 /* Bit definition for Ethernet MAC Frame Filter Register */
12894 #define ETH_MACFFR_RA_Pos (31U)
12895 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
12896 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
12897 #define ETH_MACFFR_HPF_Pos (10U)
12898 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
12899 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
12900 #define ETH_MACFFR_SAF_Pos (9U)
12901 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
12902 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
12903 #define ETH_MACFFR_SAIF_Pos (8U)
12904 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
12905 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
12906 #define ETH_MACFFR_PCF_Pos (6U)
12907 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
12908 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
12909 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
12910 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
12911 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
12912 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
12913 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
12914 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
12915 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
12916 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
12917 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
12918 #define ETH_MACFFR_BFD_Pos (5U)
12919 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
12920 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
12921 #define ETH_MACFFR_PAM_Pos (4U)
12922 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
12923 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
12924 #define ETH_MACFFR_DAIF_Pos (3U)
12925 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
12926 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
12927 #define ETH_MACFFR_HM_Pos (2U)
12928 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
12929 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
12930 #define ETH_MACFFR_HU_Pos (1U)
12931 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
12932 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
12933 #define ETH_MACFFR_PM_Pos (0U)
12934 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
12935 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
12936
12937 /* Bit definition for Ethernet MAC Hash Table High Register */
12938 #define ETH_MACHTHR_HTH_Pos (0U)
12939 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
12940 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
12941
12942 /* Bit definition for Ethernet MAC Hash Table Low Register */
12943 #define ETH_MACHTLR_HTL_Pos (0U)
12944 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
12945 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
12946
12947 /* Bit definition for Ethernet MAC MII Address Register */
12948 #define ETH_MACMIIAR_PA_Pos (11U)
12949 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
12950 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
12951 #define ETH_MACMIIAR_MR_Pos (6U)
12952 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
12953 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
12954 #define ETH_MACMIIAR_CR_Pos (2U)
12955 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
12956 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
12957 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
12958 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
12959 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
12960 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
12961 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
12962 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
12963 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
12964 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
12965 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
12966 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
12967 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
12968 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
12969 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
12970 #define ETH_MACMIIAR_MW_Pos (1U)
12971 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
12972 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
12973 #define ETH_MACMIIAR_MB_Pos (0U)
12974 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
12975 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
12976
12977 /* Bit definition for Ethernet MAC MII Data Register */
12978 #define ETH_MACMIIDR_MD_Pos (0U)
12979 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
12980 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
12981
12982 /* Bit definition for Ethernet MAC Flow Control Register */
12983 #define ETH_MACFCR_PT_Pos (16U)
12984 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
12985 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
12986 #define ETH_MACFCR_ZQPD_Pos (7U)
12987 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
12988 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
12989 #define ETH_MACFCR_PLT_Pos (4U)
12990 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
12991 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
12992 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
12993 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
12994 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
12995 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
12996 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
12997 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
12998 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
12999 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
13000 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
13001 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
13002 #define ETH_MACFCR_UPFD_Pos (3U)
13003 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
13004 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
13005 #define ETH_MACFCR_RFCE_Pos (2U)
13006 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
13007 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
13008 #define ETH_MACFCR_TFCE_Pos (1U)
13009 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
13010 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
13011 #define ETH_MACFCR_FCBBPA_Pos (0U)
13012 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
13013 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
13014
13015 /* Bit definition for Ethernet MAC VLAN Tag Register */
13016 #define ETH_MACVLANTR_VLANTC_Pos (16U)
13017 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
13018 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
13019 #define ETH_MACVLANTR_VLANTI_Pos (0U)
13020 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
13021 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
13022
13023 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
13024 #define ETH_MACRWUFFR_D_Pos (0U)
13025 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
13026 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
13027 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
13028 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
13029 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
13030 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
13031 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
13032 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
13033 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
13034 RSVD - Filter1 Command - RSVD - Filter0 Command
13035 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
13036 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
13037 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
13038
13039 /* Bit definition for Ethernet MAC PMT Control and Status Register */
13040 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
13041 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
13042 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
13043 #define ETH_MACPMTCSR_GU_Pos (9U)
13044 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
13045 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
13046 #define ETH_MACPMTCSR_WFR_Pos (6U)
13047 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
13048 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
13049 #define ETH_MACPMTCSR_MPR_Pos (5U)
13050 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
13051 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
13052 #define ETH_MACPMTCSR_WFE_Pos (2U)
13053 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
13054 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
13055 #define ETH_MACPMTCSR_MPE_Pos (1U)
13056 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
13057 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
13058 #define ETH_MACPMTCSR_PD_Pos (0U)
13059 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
13060 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
13061
13062 /* Bit definition for Ethernet MAC debug Register */
13063 #define ETH_MACDBGR_TFF_Pos (25U)
13064 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
13065 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
13066 #define ETH_MACDBGR_TFNE_Pos (24U)
13067 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
13068 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
13069 #define ETH_MACDBGR_TFWA_Pos (22U)
13070 #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
13071 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
13072 #define ETH_MACDBGR_TFRS_Pos (20U)
13073 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
13074 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
13075 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
13076 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
13077 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
13078 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
13079 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
13080 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
13081 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
13082 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
13083 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
13084 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
13085 #define ETH_MACDBGR_MTP_Pos (19U)
13086 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
13087 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
13088 #define ETH_MACDBGR_MTFCS_Pos (17U)
13089 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
13090 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
13091 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
13092 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
13093 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
13094 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
13095 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
13096 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
13097 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
13098 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
13099 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
13100 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
13101 #define ETH_MACDBGR_MMTEA_Pos (16U)
13102 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
13103 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
13104 #define ETH_MACDBGR_RFFL_Pos (8U)
13105 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
13106 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
13107 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
13108 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
13109 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
13110 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
13111 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
13112 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
13113 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
13114 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
13115 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
13116 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
13117 #define ETH_MACDBGR_RFRCS_Pos (5U)
13118 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
13119 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
13120 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
13121 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
13122 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
13123 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
13124 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
13125 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
13126 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
13127 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
13128 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
13129 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
13130 #define ETH_MACDBGR_RFWRA_Pos (4U)
13131 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
13132 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
13133 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
13134 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
13135 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
13136 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
13137 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
13138 #define ETH_MACDBGR_MMRPEA_Pos (0U)
13139 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
13140 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
13141
13142 /* Bit definition for Ethernet MAC Status Register */
13143 #define ETH_MACSR_TSTS_Pos (9U)
13144 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
13145 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
13146 #define ETH_MACSR_MMCTS_Pos (6U)
13147 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
13148 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
13149 #define ETH_MACSR_MMMCRS_Pos (5U)
13150 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
13151 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
13152 #define ETH_MACSR_MMCS_Pos (4U)
13153 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
13154 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
13155 #define ETH_MACSR_PMTS_Pos (3U)
13156 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
13157 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
13158
13159 /* Bit definition for Ethernet MAC Interrupt Mask Register */
13160 #define ETH_MACIMR_TSTIM_Pos (9U)
13161 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
13162 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
13163 #define ETH_MACIMR_PMTIM_Pos (3U)
13164 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
13165 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
13166
13167 /* Bit definition for Ethernet MAC Address0 High Register */
13168 #define ETH_MACA0HR_MACA0H_Pos (0U)
13169 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
13170 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
13171
13172 /* Bit definition for Ethernet MAC Address0 Low Register */
13173 #define ETH_MACA0LR_MACA0L_Pos (0U)
13174 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
13175 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
13176
13177 /* Bit definition for Ethernet MAC Address1 High Register */
13178 #define ETH_MACA1HR_AE_Pos (31U)
13179 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
13180 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
13181 #define ETH_MACA1HR_SA_Pos (30U)
13182 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
13183 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
13184 #define ETH_MACA1HR_MBC_Pos (24U)
13185 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
13186 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
13187 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13188 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13189 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13190 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13191 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13192 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
13193 #define ETH_MACA1HR_MACA1H_Pos (0U)
13194 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
13195 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
13196
13197 /* Bit definition for Ethernet MAC Address1 Low Register */
13198 #define ETH_MACA1LR_MACA1L_Pos (0U)
13199 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
13200 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
13201
13202 /* Bit definition for Ethernet MAC Address2 High Register */
13203 #define ETH_MACA2HR_AE_Pos (31U)
13204 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
13205 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
13206 #define ETH_MACA2HR_SA_Pos (30U)
13207 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
13208 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
13209 #define ETH_MACA2HR_MBC_Pos (24U)
13210 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
13211 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
13212 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13213 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13214 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13215 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13216 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13217 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
13218 #define ETH_MACA2HR_MACA2H_Pos (0U)
13219 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
13220 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
13221
13222 /* Bit definition for Ethernet MAC Address2 Low Register */
13223 #define ETH_MACA2LR_MACA2L_Pos (0U)
13224 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
13225 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
13226
13227 /* Bit definition for Ethernet MAC Address3 High Register */
13228 #define ETH_MACA3HR_AE_Pos (31U)
13229 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
13230 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
13231 #define ETH_MACA3HR_SA_Pos (30U)
13232 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
13233 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
13234 #define ETH_MACA3HR_MBC_Pos (24U)
13235 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
13236 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
13237 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13238 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13239 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13240 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13241 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13242 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
13243 #define ETH_MACA3HR_MACA3H_Pos (0U)
13244 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
13245 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
13246
13247 /* Bit definition for Ethernet MAC Address3 Low Register */
13248 #define ETH_MACA3LR_MACA3L_Pos (0U)
13249 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
13250 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
13251
13252 /******************************************************************************/
13253 /* Ethernet MMC Registers bits definition */
13254 /******************************************************************************/
13255
13256 /* Bit definition for Ethernet MMC Contol Register */
13257 #define ETH_MMCCR_MCFHP_Pos (5U)
13258 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
13259 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
13260 #define ETH_MMCCR_MCP_Pos (4U)
13261 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
13262 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
13263 #define ETH_MMCCR_MCF_Pos (3U)
13264 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
13265 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
13266 #define ETH_MMCCR_ROR_Pos (2U)
13267 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
13268 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
13269 #define ETH_MMCCR_CSR_Pos (1U)
13270 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
13271 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
13272 #define ETH_MMCCR_CR_Pos (0U)
13273 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
13274 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
13275
13276 /* Bit definition for Ethernet MMC Receive Interrupt Register */
13277 #define ETH_MMCRIR_RGUFS_Pos (17U)
13278 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
13279 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
13280 #define ETH_MMCRIR_RFAES_Pos (6U)
13281 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
13282 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
13283 #define ETH_MMCRIR_RFCES_Pos (5U)
13284 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
13285 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
13286
13287 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
13288 #define ETH_MMCTIR_TGFS_Pos (21U)
13289 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
13290 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
13291 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
13292 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
13293 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
13294 #define ETH_MMCTIR_TGFSCS_Pos (14U)
13295 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
13296 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
13297
13298 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
13299 #define ETH_MMCRIMR_RGUFM_Pos (17U)
13300 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
13301 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
13302 #define ETH_MMCRIMR_RFAEM_Pos (6U)
13303 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
13304 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
13305 #define ETH_MMCRIMR_RFCEM_Pos (5U)
13306 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
13307 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
13308
13309 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
13310 #define ETH_MMCTIMR_TGFM_Pos (21U)
13311 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
13312 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
13313 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
13314 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
13315 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
13316 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
13317 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
13318 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
13319
13320 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
13321 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
13322 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
13323 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
13324
13325 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
13326 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
13327 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
13328 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
13329
13330 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
13331 #define ETH_MMCTGFCR_TGFC_Pos (0U)
13332 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
13333 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
13334
13335 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
13336 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
13337 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
13338 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
13339
13340 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
13341 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
13342 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
13343 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
13344
13345 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
13346 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
13347 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
13348 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
13349
13350 /******************************************************************************/
13351 /* Ethernet PTP Registers bits definition */
13352 /******************************************************************************/
13353
13354 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
13355 #define ETH_PTPTSCR_TSCNT_Pos (16U)
13356 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
13357 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
13358 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
13359 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
13360 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
13361 #define ETH_PTPTSSR_TSSEME_Pos (14U)
13362 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
13363 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
13364 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
13365 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
13366 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
13367 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
13368 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
13369 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
13370 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
13371 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
13372 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
13373 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
13374 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
13375 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
13376 #define ETH_PTPTSSR_TSSSR_Pos (9U)
13377 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
13378 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
13379 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
13380 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
13381 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
13382
13383 #define ETH_PTPTSCR_TSARU_Pos (5U)
13384 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
13385 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
13386 #define ETH_PTPTSCR_TSITE_Pos (4U)
13387 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
13388 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
13389 #define ETH_PTPTSCR_TSSTU_Pos (3U)
13390 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
13391 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
13392 #define ETH_PTPTSCR_TSSTI_Pos (2U)
13393 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
13394 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
13395 #define ETH_PTPTSCR_TSFCU_Pos (1U)
13396 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
13397 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
13398 #define ETH_PTPTSCR_TSE_Pos (0U)
13399 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
13400 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
13401
13402 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
13403 #define ETH_PTPSSIR_STSSI_Pos (0U)
13404 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
13405 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
13406
13407 /* Bit definition for Ethernet PTP Time Stamp High Register */
13408 #define ETH_PTPTSHR_STS_Pos (0U)
13409 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
13410 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
13411
13412 /* Bit definition for Ethernet PTP Time Stamp Low Register */
13413 #define ETH_PTPTSLR_STPNS_Pos (31U)
13414 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
13415 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
13416 #define ETH_PTPTSLR_STSS_Pos (0U)
13417 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
13418 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
13419
13420 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
13421 #define ETH_PTPTSHUR_TSUS_Pos (0U)
13422 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
13423 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
13424
13425 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
13426 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
13427 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
13428 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
13429 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
13430 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
13431 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
13432
13433 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
13434 #define ETH_PTPTSAR_TSA_Pos (0U)
13435 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
13436 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
13437
13438 /* Bit definition for Ethernet PTP Target Time High Register */
13439 #define ETH_PTPTTHR_TTSH_Pos (0U)
13440 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
13441 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
13442
13443 /* Bit definition for Ethernet PTP Target Time Low Register */
13444 #define ETH_PTPTTLR_TTSL_Pos (0U)
13445 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
13446 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
13447
13448 /* Bit definition for Ethernet PTP Time Stamp Status Register */
13449 #define ETH_PTPTSSR_TSTTR_Pos (5U)
13450 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
13451 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
13452 #define ETH_PTPTSSR_TSSO_Pos (4U)
13453 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
13454 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
13455
13456 /******************************************************************************/
13457 /* Ethernet DMA Registers bits definition */
13458 /******************************************************************************/
13459
13460 /* Bit definition for Ethernet DMA Bus Mode Register */
13461 #define ETH_DMABMR_AAB_Pos (25U)
13462 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
13463 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
13464 #define ETH_DMABMR_FPM_Pos (24U)
13465 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
13466 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
13467 #define ETH_DMABMR_USP_Pos (23U)
13468 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
13469 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
13470 #define ETH_DMABMR_RDP_Pos (17U)
13471 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
13472 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
13473 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
13474 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
13475 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13476 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13477 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13478 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13479 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13480 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13481 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13482 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13483 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
13484 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
13485 #define ETH_DMABMR_FB_Pos (16U)
13486 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
13487 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
13488 #define ETH_DMABMR_RTPR_Pos (14U)
13489 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
13490 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
13491 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
13492 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
13493 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
13494 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
13495 #define ETH_DMABMR_PBL_Pos (8U)
13496 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
13497 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
13498 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
13499 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
13500 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13501 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13502 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13503 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13504 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13505 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13506 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13507 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13508 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
13509 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
13510 #define ETH_DMABMR_EDE_Pos (7U)
13511 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
13512 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
13513 #define ETH_DMABMR_DSL_Pos (2U)
13514 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
13515 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
13516 #define ETH_DMABMR_DA_Pos (1U)
13517 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
13518 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
13519 #define ETH_DMABMR_SR_Pos (0U)
13520 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
13521 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
13522
13523 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
13524 #define ETH_DMATPDR_TPD_Pos (0U)
13525 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
13526 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
13527
13528 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
13529 #define ETH_DMARPDR_RPD_Pos (0U)
13530 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
13531 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
13532
13533 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
13534 #define ETH_DMARDLAR_SRL_Pos (0U)
13535 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
13536 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
13537
13538 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
13539 #define ETH_DMATDLAR_STL_Pos (0U)
13540 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
13541 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
13542
13543 /* Bit definition for Ethernet DMA Status Register */
13544 #define ETH_DMASR_TSTS_Pos (29U)
13545 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
13546 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
13547 #define ETH_DMASR_PMTS_Pos (28U)
13548 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
13549 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
13550 #define ETH_DMASR_MMCS_Pos (27U)
13551 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
13552 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
13553 #define ETH_DMASR_EBS_Pos (23U)
13554 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
13555 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
13556 /* combination with EBS[2:0] for GetFlagStatus function */
13557 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
13558 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
13559 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
13560 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
13561 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
13562 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
13563 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
13564 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
13565 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
13566 #define ETH_DMASR_TPS_Pos (20U)
13567 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
13568 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
13569 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
13570 #define ETH_DMASR_TPS_Fetching_Pos (20U)
13571 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
13572 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
13573 #define ETH_DMASR_TPS_Waiting_Pos (21U)
13574 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
13575 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
13576 #define ETH_DMASR_TPS_Reading_Pos (20U)
13577 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
13578 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
13579 #define ETH_DMASR_TPS_Suspended_Pos (21U)
13580 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
13581 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
13582 #define ETH_DMASR_TPS_Closing_Pos (20U)
13583 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
13584 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
13585 #define ETH_DMASR_RPS_Pos (17U)
13586 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
13587 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
13588 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
13589 #define ETH_DMASR_RPS_Fetching_Pos (17U)
13590 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
13591 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
13592 #define ETH_DMASR_RPS_Waiting_Pos (17U)
13593 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
13594 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
13595 #define ETH_DMASR_RPS_Suspended_Pos (19U)
13596 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
13597 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
13598 #define ETH_DMASR_RPS_Closing_Pos (17U)
13599 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
13600 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
13601 #define ETH_DMASR_RPS_Queuing_Pos (17U)
13602 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
13603 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
13604 #define ETH_DMASR_NIS_Pos (16U)
13605 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
13606 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
13607 #define ETH_DMASR_AIS_Pos (15U)
13608 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
13609 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
13610 #define ETH_DMASR_ERS_Pos (14U)
13611 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
13612 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
13613 #define ETH_DMASR_FBES_Pos (13U)
13614 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
13615 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
13616 #define ETH_DMASR_ETS_Pos (10U)
13617 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
13618 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
13619 #define ETH_DMASR_RWTS_Pos (9U)
13620 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
13621 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
13622 #define ETH_DMASR_RPSS_Pos (8U)
13623 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
13624 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
13625 #define ETH_DMASR_RBUS_Pos (7U)
13626 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
13627 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
13628 #define ETH_DMASR_RS_Pos (6U)
13629 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
13630 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
13631 #define ETH_DMASR_TUS_Pos (5U)
13632 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
13633 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
13634 #define ETH_DMASR_ROS_Pos (4U)
13635 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
13636 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
13637 #define ETH_DMASR_TJTS_Pos (3U)
13638 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
13639 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
13640 #define ETH_DMASR_TBUS_Pos (2U)
13641 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
13642 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
13643 #define ETH_DMASR_TPSS_Pos (1U)
13644 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
13645 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
13646 #define ETH_DMASR_TS_Pos (0U)
13647 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
13648 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
13649
13650 /* Bit definition for Ethernet DMA Operation Mode Register */
13651 #define ETH_DMAOMR_DTCEFD_Pos (26U)
13652 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
13653 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
13654 #define ETH_DMAOMR_RSF_Pos (25U)
13655 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
13656 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
13657 #define ETH_DMAOMR_DFRF_Pos (24U)
13658 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
13659 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
13660 #define ETH_DMAOMR_TSF_Pos (21U)
13661 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
13662 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
13663 #define ETH_DMAOMR_FTF_Pos (20U)
13664 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
13665 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
13666 #define ETH_DMAOMR_TTC_Pos (14U)
13667 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
13668 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
13669 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
13670 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
13671 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
13672 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
13673 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
13674 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
13675 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
13676 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
13677 #define ETH_DMAOMR_ST_Pos (13U)
13678 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
13679 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
13680 #define ETH_DMAOMR_FEF_Pos (7U)
13681 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
13682 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
13683 #define ETH_DMAOMR_FUGF_Pos (6U)
13684 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
13685 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
13686 #define ETH_DMAOMR_RTC_Pos (3U)
13687 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
13688 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
13689 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
13690 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
13691 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
13692 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
13693 #define ETH_DMAOMR_OSF_Pos (2U)
13694 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
13695 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
13696 #define ETH_DMAOMR_SR_Pos (1U)
13697 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
13698 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
13699
13700 /* Bit definition for Ethernet DMA Interrupt Enable Register */
13701 #define ETH_DMAIER_NISE_Pos (16U)
13702 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
13703 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
13704 #define ETH_DMAIER_AISE_Pos (15U)
13705 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
13706 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
13707 #define ETH_DMAIER_ERIE_Pos (14U)
13708 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
13709 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
13710 #define ETH_DMAIER_FBEIE_Pos (13U)
13711 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
13712 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
13713 #define ETH_DMAIER_ETIE_Pos (10U)
13714 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
13715 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
13716 #define ETH_DMAIER_RWTIE_Pos (9U)
13717 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
13718 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
13719 #define ETH_DMAIER_RPSIE_Pos (8U)
13720 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
13721 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
13722 #define ETH_DMAIER_RBUIE_Pos (7U)
13723 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
13724 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
13725 #define ETH_DMAIER_RIE_Pos (6U)
13726 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
13727 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
13728 #define ETH_DMAIER_TUIE_Pos (5U)
13729 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
13730 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
13731 #define ETH_DMAIER_ROIE_Pos (4U)
13732 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
13733 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
13734 #define ETH_DMAIER_TJTIE_Pos (3U)
13735 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
13736 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
13737 #define ETH_DMAIER_TBUIE_Pos (2U)
13738 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
13739 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
13740 #define ETH_DMAIER_TPSIE_Pos (1U)
13741 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
13742 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
13743 #define ETH_DMAIER_TIE_Pos (0U)
13744 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
13745 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
13746
13747 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
13748 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
13749 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
13750 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
13751 #define ETH_DMAMFBOCR_MFA_Pos (17U)
13752 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
13753 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
13754 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
13755 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
13756 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
13757 #define ETH_DMAMFBOCR_MFC_Pos (0U)
13758 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
13759 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
13760
13761 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
13762 #define ETH_DMACHTDR_HTDAP_Pos (0U)
13763 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
13764 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
13765
13766 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
13767 #define ETH_DMACHRDR_HRDAP_Pos (0U)
13768 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
13769 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
13770
13771 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
13772 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
13773 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
13774 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
13775
13776 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
13777 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
13778 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
13779 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
13780
13781 /******************************************************************************/
13782 /* */
13783 /* USB_OTG */
13784 /* */
13785 /******************************************************************************/
13786 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
13787 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
13788 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
13789 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
13790 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
13791 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
13792 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
13793 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
13794 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
13795 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
13796 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
13797 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
13798 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
13799 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
13800 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
13801 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
13802 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
13803 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
13804 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
13805 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
13806 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
13807 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
13808 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
13809 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
13810 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
13811 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
13812 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
13813 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
13814 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
13815 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
13816 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
13817
13818 /******************** Bit definition forUSB_OTG_HCFG register ********************/
13819
13820 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
13821 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
13822 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
13823 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
13824 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
13825 #define USB_OTG_HCFG_FSLSS_Pos (2U)
13826 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
13827 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
13828
13829 /******************** Bit definition for USB_OTG_DCFG register ********************/
13830
13831 #define USB_OTG_DCFG_DSPD_Pos (0U)
13832 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
13833 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
13834 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
13835 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
13836 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
13837 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
13838 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
13839
13840 #define USB_OTG_DCFG_DAD_Pos (4U)
13841 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
13842 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
13843 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
13844 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
13845 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
13846 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
13847 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
13848 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
13849 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
13850
13851 #define USB_OTG_DCFG_PFIVL_Pos (11U)
13852 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
13853 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
13854 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
13855 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
13856
13857 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
13858 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
13859 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
13860 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
13861 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
13862
13863 /******************** Bit definition for USB_OTG_PCGCR register ********************/
13864 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
13865 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
13866 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
13867 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
13868 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
13869 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
13870 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
13871 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
13872 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
13873
13874 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
13875 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
13876 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
13877 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
13878 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
13879 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
13880 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
13881 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
13882 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
13883 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
13884 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
13885 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
13886 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
13887 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
13888 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
13889 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
13890 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
13891 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
13892 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
13893
13894 /******************** Bit definition for USB_OTG_DCTL register ********************/
13895 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
13896 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
13897 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
13898 #define USB_OTG_DCTL_SDIS_Pos (1U)
13899 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
13900 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
13901 #define USB_OTG_DCTL_GINSTS_Pos (2U)
13902 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
13903 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
13904 #define USB_OTG_DCTL_GONSTS_Pos (3U)
13905 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
13906 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
13907
13908 #define USB_OTG_DCTL_TCTL_Pos (4U)
13909 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
13910 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
13911 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
13912 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
13913 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
13914 #define USB_OTG_DCTL_SGINAK_Pos (7U)
13915 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
13916 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
13917 #define USB_OTG_DCTL_CGINAK_Pos (8U)
13918 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
13919 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
13920 #define USB_OTG_DCTL_SGONAK_Pos (9U)
13921 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
13922 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
13923 #define USB_OTG_DCTL_CGONAK_Pos (10U)
13924 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
13925 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
13926 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
13927 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
13928 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
13929
13930 /******************** Bit definition for USB_OTG_HFIR register ********************/
13931 #define USB_OTG_HFIR_FRIVL_Pos (0U)
13932 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
13933 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
13934
13935 /******************** Bit definition for USB_OTG_HFNUM register ********************/
13936 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
13937 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
13938 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
13939 #define USB_OTG_HFNUM_FTREM_Pos (16U)
13940 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
13941 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
13942
13943 /******************** Bit definition for USB_OTG_DSTS register ********************/
13944 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
13945 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
13946 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
13947
13948 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
13949 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
13950 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
13951 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
13952 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
13953 #define USB_OTG_DSTS_EERR_Pos (3U)
13954 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
13955 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
13956 #define USB_OTG_DSTS_FNSOF_Pos (8U)
13957 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
13958 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
13959
13960 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
13961 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
13962 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
13963 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
13964 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
13965 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
13966 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
13967 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
13968 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
13969 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
13970 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
13971 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
13972 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
13973 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
13974 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
13975 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
13976 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
13977 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
13978 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
13979 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
13980 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
13981
13982 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
13983
13984 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
13985 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
13986 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
13987 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
13988 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
13989 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
13990 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
13991 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
13992 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
13993 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
13994 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
13995 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
13996 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
13997 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
13998 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
13999 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
14000 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
14001 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
14002 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
14003 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
14004 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
14005 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
14006 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
14007 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
14008 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
14009 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
14010 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
14011 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
14012 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
14013 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
14014 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
14015 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
14016 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
14017 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
14018 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
14019 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
14020 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
14021 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
14022 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
14023 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
14024 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
14025 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
14026 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
14027 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
14028 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
14029 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
14030 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
14031 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
14032 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
14033 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
14034 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
14035 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
14036 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
14037 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
14038 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
14039 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
14040 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
14041 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
14042 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
14043 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
14044 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
14045
14046 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
14047 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
14048 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
14049 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
14050 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
14051 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
14052 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
14053 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
14054 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
14055 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
14056 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
14057 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
14058 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
14059 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
14060 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
14061 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
14062
14063
14064 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
14065 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
14066 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
14067 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
14068 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
14069 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
14070 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
14071 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
14072 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
14073 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
14074 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
14075 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
14076 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
14077 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
14078
14079 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
14080 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
14081 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
14082 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
14083 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
14084 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
14085 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14086 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
14087 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
14088 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
14089 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
14090 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
14091 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
14092 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
14093 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
14094 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
14095 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
14096 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
14097 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
14098 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
14099 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
14100 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
14101 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
14102 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
14103 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
14104
14105 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
14106 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
14107 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
14108 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
14109 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
14110 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
14111 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
14112 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
14113 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
14114 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
14115 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
14116 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
14117 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
14118 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
14119 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
14120
14121 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
14122 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
14123 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
14124 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
14125 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
14126 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
14127 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
14128 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
14129 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
14130 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
14131 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
14132
14133 /******************** Bit definition for USB_OTG_HAINT register ********************/
14134 #define USB_OTG_HAINT_HAINT_Pos (0U)
14135 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
14136 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
14137
14138 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
14139 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
14140 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
14141 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
14142 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
14143 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
14144 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14145 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
14146 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
14147 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
14148 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
14149 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
14150 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
14151 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
14152 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
14153 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
14154 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
14155 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
14156 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
14157 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
14158 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
14159 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
14160
14161 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
14162 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
14163 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
14164 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
14165 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
14166 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
14167 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
14168 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
14169 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
14170 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
14171 #define USB_OTG_GINTSTS_SOF_Pos (3U)
14172 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
14173 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
14174 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
14175 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
14176 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
14177 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
14178 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
14179 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
14180 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
14181 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
14182 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
14183 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
14184 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
14185 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
14186 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
14187 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
14188 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
14189 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
14190 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
14191 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
14192 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
14193 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
14194 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
14195 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
14196 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
14197 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
14198 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
14199 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
14200 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
14201 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
14202 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
14203 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
14204 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
14205 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
14206 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
14207 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
14208 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
14209 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
14210 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
14211 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
14212 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
14213 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
14214 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
14215 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
14216 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
14217 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
14218 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
14219 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
14220 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
14221 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
14222 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
14223 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
14224 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
14225 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
14226 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
14227 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
14228 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
14229 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
14230 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
14231 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
14232 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
14233 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
14234 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
14235 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
14236 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
14237 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
14238 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
14239 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
14240
14241 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
14242 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
14243 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
14244 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
14245 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
14246 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
14247 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
14248 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
14249 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
14250 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
14251 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
14252 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
14253 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
14254 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
14255 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
14256 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
14257 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
14258 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
14259 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
14260 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
14261 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
14262 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
14263 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
14264 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
14265 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
14266 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
14267 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
14268 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
14269 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
14270 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
14271 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
14272 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
14273 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
14274 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
14275 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
14276 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
14277 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
14278 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
14279 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
14280 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
14281 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
14282 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
14283 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
14284 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
14285 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
14286 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
14287 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
14288 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
14289 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
14290 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
14291 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
14292 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
14293 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
14294 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
14295 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
14296 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
14297 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
14298 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
14299 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
14300 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
14301 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
14302 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
14303 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
14304 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
14305 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
14306 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
14307 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
14308 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
14309 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
14310 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
14311 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
14312 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
14313 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
14314 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
14315 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
14316 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
14317 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
14318 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
14319 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
14320
14321 /******************** Bit definition for USB_OTG_DAINT register ********************/
14322 #define USB_OTG_DAINT_IEPINT_Pos (0U)
14323 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
14324 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
14325 #define USB_OTG_DAINT_OEPINT_Pos (16U)
14326 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
14327 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
14328
14329 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
14330 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
14331 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
14332 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
14333
14334 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
14335 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
14336 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
14337 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
14338 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
14339 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
14340 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
14341 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
14342 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
14343 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
14344 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
14345 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
14346 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
14347
14348 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
14349 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
14350 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
14351 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
14352 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
14353 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
14354 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
14355
14356 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
14357 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
14358 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
14359 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
14360
14361 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
14362 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
14363 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
14364 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
14365
14366 /******************** Bit definition for OTG register ********************/
14367 #define USB_OTG_NPTXFSA_Pos (0U)
14368 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
14369 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
14370 #define USB_OTG_NPTXFD_Pos (16U)
14371 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
14372 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
14373 #define USB_OTG_TX0FSA_Pos (0U)
14374 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
14375 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
14376 #define USB_OTG_TX0FD_Pos (16U)
14377 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
14378 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
14379
14380 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
14381 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
14382 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
14383 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
14384
14385 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
14386 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
14387 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
14388 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
14389
14390 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
14391 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
14392 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
14393 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
14394 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
14395 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
14396 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
14397 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
14398 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
14399 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
14400 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
14401
14402 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
14403 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
14404 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
14405 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
14406 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
14407 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
14408 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
14409 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
14410 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
14411 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
14412
14413 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14414 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14415 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
14416 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
14417 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14418 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
14419 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
14420
14421 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14422 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
14423 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
14424 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
14425 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
14426 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
14427 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
14428 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
14429 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
14430 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
14431 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
14432 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
14433 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14434 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
14435 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
14436
14437 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14438 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
14439 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
14440 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
14441 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
14442 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
14443 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
14444 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
14445 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
14446 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
14447 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
14448 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
14449 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14450 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
14451 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
14452
14453 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14454 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14455 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
14456 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
14457
14458 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
14459 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14460 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
14461 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
14462 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14463 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
14464 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
14465
14466 /******************** Bit definition for USB_OTG_GCCFG register ********************/
14467 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14468 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
14469 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
14470 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
14471 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
14472 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
14473 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
14474 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
14475 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
14476 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
14477 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
14478 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
14479 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
14480 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
14481 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
14482 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
14483 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
14484 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
14485
14486 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
14487 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14488 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
14489 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
14490 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14491 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
14492 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
14493
14494 /******************** Bit definition for USB_OTG_CID register ********************/
14495 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14496 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
14497 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
14498
14499 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14500 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14501 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14502 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
14503 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14504 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14505 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14506 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14507 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14508 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
14509 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14510 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14511 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
14512 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14513 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14514 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
14515 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14516 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14517 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
14518 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14519 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14520 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
14521 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14522 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14523 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
14524 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14525 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14526 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
14527
14528 /******************** Bit definition for USB_OTG_HPRT register ********************/
14529 #define USB_OTG_HPRT_PCSTS_Pos (0U)
14530 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
14531 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
14532 #define USB_OTG_HPRT_PCDET_Pos (1U)
14533 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
14534 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
14535 #define USB_OTG_HPRT_PENA_Pos (2U)
14536 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
14537 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
14538 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
14539 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
14540 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
14541 #define USB_OTG_HPRT_POCA_Pos (4U)
14542 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
14543 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
14544 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
14545 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
14546 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
14547 #define USB_OTG_HPRT_PRES_Pos (6U)
14548 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
14549 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
14550 #define USB_OTG_HPRT_PSUSP_Pos (7U)
14551 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
14552 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
14553 #define USB_OTG_HPRT_PRST_Pos (8U)
14554 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
14555 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
14556
14557 #define USB_OTG_HPRT_PLSTS_Pos (10U)
14558 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
14559 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
14560 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
14561 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
14562 #define USB_OTG_HPRT_PPWR_Pos (12U)
14563 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
14564 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
14565
14566 #define USB_OTG_HPRT_PTCTL_Pos (13U)
14567 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
14568 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
14569 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
14570 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
14571 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
14572 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
14573
14574 #define USB_OTG_HPRT_PSPD_Pos (17U)
14575 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
14576 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
14577 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
14578 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
14579
14580 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
14581 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14582 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14583 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
14584 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14585 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14586 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14587 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14588 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14589 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
14590 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14591 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14592 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
14593 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14594 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14595 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
14596 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14597 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14598 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
14599 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14600 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14601 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
14602 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14603 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14604 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
14605 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14606 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
14607 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
14608 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14609 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14610 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
14611 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14612 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
14613 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
14614
14615 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
14616 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14617 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
14618 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
14619 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14620 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
14621 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
14622
14623 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
14624 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14625 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
14626 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
14627 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14628 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
14629 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
14630 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14631 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
14632 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
14633 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
14634 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
14635 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
14636
14637 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
14638 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
14639 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
14640 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
14641 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
14642 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
14643 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
14644 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
14645
14646 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
14647 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
14648 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
14649 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
14650 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
14651 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
14652 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
14653 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
14654 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
14655 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
14656 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
14657 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
14658 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
14659 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
14660 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
14661 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
14662 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
14663 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
14664 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
14665 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
14666 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
14667 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
14668 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
14669 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
14670 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
14671
14672 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
14673 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
14674 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
14675 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
14676
14677 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
14678 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
14679 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
14680 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
14681 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
14682 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
14683 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
14684 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
14685 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
14686 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
14687 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
14688 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
14689 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
14690
14691 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
14692 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
14693 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
14694 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
14695 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
14696
14697 #define USB_OTG_HCCHAR_MC_Pos (20U)
14698 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
14699 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
14700 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
14701 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
14702
14703 #define USB_OTG_HCCHAR_DAD_Pos (22U)
14704 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
14705 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
14706 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
14707 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
14708 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
14709 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
14710 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
14711 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
14712 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
14713 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
14714 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
14715 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
14716 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
14717 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
14718 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
14719 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
14720 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
14721 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
14722
14723 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
14724
14725 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
14726 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
14727 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
14728 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
14729 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
14730 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
14731 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
14732 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
14733 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
14734 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
14735
14736 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
14737 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
14738 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
14739 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
14740 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
14741 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
14742 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
14743 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
14744 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
14745 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
14746
14747 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
14748 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
14749 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
14750 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
14751 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
14752 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
14753 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
14754 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
14755 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
14756 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
14757 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
14758
14759 /******************** Bit definition for USB_OTG_HCINT register ********************/
14760 #define USB_OTG_HCINT_XFRC_Pos (0U)
14761 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
14762 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
14763 #define USB_OTG_HCINT_CHH_Pos (1U)
14764 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
14765 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
14766 #define USB_OTG_HCINT_AHBERR_Pos (2U)
14767 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
14768 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
14769 #define USB_OTG_HCINT_STALL_Pos (3U)
14770 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
14771 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
14772 #define USB_OTG_HCINT_NAK_Pos (4U)
14773 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
14774 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
14775 #define USB_OTG_HCINT_ACK_Pos (5U)
14776 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
14777 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
14778 #define USB_OTG_HCINT_NYET_Pos (6U)
14779 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
14780 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
14781 #define USB_OTG_HCINT_TXERR_Pos (7U)
14782 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
14783 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
14784 #define USB_OTG_HCINT_BBERR_Pos (8U)
14785 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
14786 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
14787 #define USB_OTG_HCINT_FRMOR_Pos (9U)
14788 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
14789 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
14790 #define USB_OTG_HCINT_DTERR_Pos (10U)
14791 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
14792 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
14793
14794 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
14795 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
14796 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
14797 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
14798 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
14799 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
14800 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
14801 #define USB_OTG_DIEPINT_TOC_Pos (3U)
14802 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
14803 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
14804 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
14805 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
14806 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
14807 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
14808 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
14809 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
14810 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
14811 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
14812 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
14813 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
14814 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
14815 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
14816 #define USB_OTG_DIEPINT_BNA_Pos (9U)
14817 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
14818 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
14819 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
14820 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
14821 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
14822 #define USB_OTG_DIEPINT_BERR_Pos (12U)
14823 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
14824 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
14825 #define USB_OTG_DIEPINT_NAK_Pos (13U)
14826 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
14827 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
14828
14829 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
14830 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
14831 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
14832 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
14833 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
14834 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
14835 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
14836 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
14837 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
14838 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
14839 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
14840 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
14841 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
14842 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
14843 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
14844 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
14845 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
14846 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
14847 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
14848 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
14849 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
14850 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
14851 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
14852 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
14853 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
14854 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
14855 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
14856 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
14857 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
14858 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
14859 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
14860 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
14861 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
14862 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
14863
14864 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
14865
14866 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
14867 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14868 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
14869 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
14870 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14871 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
14872 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
14873 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
14874 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
14875 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
14876 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
14877 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14878 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
14879 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
14880 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14881 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
14882 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
14883 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
14884 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
14885 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
14886 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
14887 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
14888 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
14889 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
14890
14891 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
14892 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
14893 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
14894 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
14895
14896 /******************** Bit definition for USB_OTG_HCDMA register ********************/
14897 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
14898 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
14899 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
14900
14901 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
14902 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
14903 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
14904 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
14905
14906 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
14907 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
14908 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
14909 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
14910 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
14911 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
14912 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
14913
14914 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
14915
14916 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
14917 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
14918 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
14919 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
14920 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
14921 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
14922 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
14923 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
14924 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
14925 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
14926 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
14927 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
14928 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
14929 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
14930 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
14931 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
14932 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
14933 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
14934 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
14935 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
14936 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
14937 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
14938 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
14939 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
14940 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
14941 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
14942 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
14943 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
14944 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
14945 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
14946 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
14947 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
14948 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
14949 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
14950 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
14951 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
14952 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
14953 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
14954
14955 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
14956 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
14957 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
14958 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
14959 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
14960 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
14961 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
14962 #define USB_OTG_DOEPINT_STUP_Pos (3U)
14963 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
14964 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
14965 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
14966 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
14967 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
14968 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
14969 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
14970 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
14971 #define USB_OTG_DOEPINT_NYET_Pos (14U)
14972 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
14973 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
14974
14975 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
14976
14977 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
14978 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14979 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
14980 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
14981 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14982 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
14983
14984 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
14985 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
14986 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
14987 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
14988 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
14989
14990 /******************** Bit definition for PCGCCTL register ********************/
14991 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
14992 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
14993 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
14994 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
14995 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
14996 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
14997 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
14998 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
14999 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
15000
15001 /* Legacy define */
15002 /******************** Bit definition for OTG register ********************/
15003 #define USB_OTG_CHNUM_Pos (0U)
15004 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
15005 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
15006 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
15007 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
15008 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
15009 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
15010 #define USB_OTG_BCNT_Pos (4U)
15011 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
15012 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
15013
15014 #define USB_OTG_DPID_Pos (15U)
15015 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
15016 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
15017 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
15018 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
15019
15020 #define USB_OTG_PKTSTS_Pos (17U)
15021 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
15022 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
15023 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
15024 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
15025 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
15026 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
15027
15028 #define USB_OTG_EPNUM_Pos (0U)
15029 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
15030 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
15031 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
15032 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
15033 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
15034 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
15035
15036 #define USB_OTG_FRMNUM_Pos (21U)
15037 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
15038 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
15039 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
15040 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
15041 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
15042 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
15043 /**
15044 * @}
15045 */
15046
15047 /**
15048 * @}
15049 */
15050
15051 /** @addtogroup Exported_macros
15052 * @{
15053 */
15054
15055 /******************************* ADC Instances ********************************/
15056 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
15057 ((INSTANCE) == ADC2) || \
15058 ((INSTANCE) == ADC3))
15059
15060 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
15061
15062 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
15063
15064 /******************************* CAN Instances ********************************/
15065 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
15066 ((INSTANCE) == CAN2))
15067 /******************************* CRC Instances ********************************/
15068 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
15069
15070 /******************************* DAC Instances ********************************/
15071 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
15072
15073 /******************************* DCMI Instances *******************************/
15074 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
15075
15076 /******************************** DMA Instances *******************************/
15077 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
15078 ((INSTANCE) == DMA1_Stream1) || \
15079 ((INSTANCE) == DMA1_Stream2) || \
15080 ((INSTANCE) == DMA1_Stream3) || \
15081 ((INSTANCE) == DMA1_Stream4) || \
15082 ((INSTANCE) == DMA1_Stream5) || \
15083 ((INSTANCE) == DMA1_Stream6) || \
15084 ((INSTANCE) == DMA1_Stream7) || \
15085 ((INSTANCE) == DMA2_Stream0) || \
15086 ((INSTANCE) == DMA2_Stream1) || \
15087 ((INSTANCE) == DMA2_Stream2) || \
15088 ((INSTANCE) == DMA2_Stream3) || \
15089 ((INSTANCE) == DMA2_Stream4) || \
15090 ((INSTANCE) == DMA2_Stream5) || \
15091 ((INSTANCE) == DMA2_Stream6) || \
15092 ((INSTANCE) == DMA2_Stream7))
15093
15094 /******************************* GPIO Instances *******************************/
15095 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
15096 ((INSTANCE) == GPIOB) || \
15097 ((INSTANCE) == GPIOC) || \
15098 ((INSTANCE) == GPIOD) || \
15099 ((INSTANCE) == GPIOE) || \
15100 ((INSTANCE) == GPIOF) || \
15101 ((INSTANCE) == GPIOG) || \
15102 ((INSTANCE) == GPIOH) || \
15103 ((INSTANCE) == GPIOI))
15104
15105 /******************************** I2C Instances *******************************/
15106 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15107 ((INSTANCE) == I2C2) || \
15108 ((INSTANCE) == I2C3))
15109
15110 /******************************* SMBUS Instances ******************************/
15111 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
15112
15113 /******************************** I2S Instances *******************************/
15114
15115 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
15116 ((INSTANCE) == SPI3))
15117
15118 /*************************** I2S Extended Instances ***************************/
15119 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
15120 ((INSTANCE) == I2S3ext))
15121 /* Legacy Defines */
15122 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
15123
15124 /******************************* RNG Instances ********************************/
15125 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
15126
15127 /****************************** RTC Instances *********************************/
15128 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
15129
15130
15131 /******************************** SPI Instances *******************************/
15132 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15133 ((INSTANCE) == SPI2) || \
15134 ((INSTANCE) == SPI3))
15135
15136
15137 /****************** TIM Instances : All supported instances *******************/
15138 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15139 ((INSTANCE) == TIM2) || \
15140 ((INSTANCE) == TIM3) || \
15141 ((INSTANCE) == TIM4) || \
15142 ((INSTANCE) == TIM5) || \
15143 ((INSTANCE) == TIM6) || \
15144 ((INSTANCE) == TIM7) || \
15145 ((INSTANCE) == TIM8) || \
15146 ((INSTANCE) == TIM9) || \
15147 ((INSTANCE) == TIM10)|| \
15148 ((INSTANCE) == TIM11)|| \
15149 ((INSTANCE) == TIM12)|| \
15150 ((INSTANCE) == TIM13)|| \
15151 ((INSTANCE) == TIM14))
15152
15153 /************* TIM Instances : at least 1 capture/compare channel *************/
15154 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15155 ((INSTANCE) == TIM2) || \
15156 ((INSTANCE) == TIM3) || \
15157 ((INSTANCE) == TIM4) || \
15158 ((INSTANCE) == TIM5) || \
15159 ((INSTANCE) == TIM8) || \
15160 ((INSTANCE) == TIM9) || \
15161 ((INSTANCE) == TIM10) || \
15162 ((INSTANCE) == TIM11) || \
15163 ((INSTANCE) == TIM12) || \
15164 ((INSTANCE) == TIM13) || \
15165 ((INSTANCE) == TIM14))
15166
15167 /************ TIM Instances : at least 2 capture/compare channels *************/
15168 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15169 ((INSTANCE) == TIM2) || \
15170 ((INSTANCE) == TIM3) || \
15171 ((INSTANCE) == TIM4) || \
15172 ((INSTANCE) == TIM5) || \
15173 ((INSTANCE) == TIM8) || \
15174 ((INSTANCE) == TIM9) || \
15175 ((INSTANCE) == TIM12))
15176
15177 /************ TIM Instances : at least 3 capture/compare channels *************/
15178 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15179 ((INSTANCE) == TIM2) || \
15180 ((INSTANCE) == TIM3) || \
15181 ((INSTANCE) == TIM4) || \
15182 ((INSTANCE) == TIM5) || \
15183 ((INSTANCE) == TIM8))
15184
15185 /************ TIM Instances : at least 4 capture/compare channels *************/
15186 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15187 ((INSTANCE) == TIM2) || \
15188 ((INSTANCE) == TIM3) || \
15189 ((INSTANCE) == TIM4) || \
15190 ((INSTANCE) == TIM5) || \
15191 ((INSTANCE) == TIM8))
15192
15193 /******************** TIM Instances : Advanced-control timers *****************/
15194 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15195 ((INSTANCE) == TIM8))
15196
15197 /******************* TIM Instances : Timer input XOR function *****************/
15198 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15199 ((INSTANCE) == TIM2) || \
15200 ((INSTANCE) == TIM3) || \
15201 ((INSTANCE) == TIM4) || \
15202 ((INSTANCE) == TIM5) || \
15203 ((INSTANCE) == TIM8))
15204
15205 /****************** TIM Instances : DMA requests generation (UDE) *************/
15206 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15207 ((INSTANCE) == TIM2) || \
15208 ((INSTANCE) == TIM3) || \
15209 ((INSTANCE) == TIM4) || \
15210 ((INSTANCE) == TIM5) || \
15211 ((INSTANCE) == TIM6) || \
15212 ((INSTANCE) == TIM7) || \
15213 ((INSTANCE) == TIM8))
15214
15215 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
15216 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15217 ((INSTANCE) == TIM2) || \
15218 ((INSTANCE) == TIM3) || \
15219 ((INSTANCE) == TIM4) || \
15220 ((INSTANCE) == TIM5) || \
15221 ((INSTANCE) == TIM8))
15222
15223 /************ TIM Instances : DMA requests generation (COMDE) *****************/
15224 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15225 ((INSTANCE) == TIM2) || \
15226 ((INSTANCE) == TIM3) || \
15227 ((INSTANCE) == TIM4) || \
15228 ((INSTANCE) == TIM5) || \
15229 ((INSTANCE) == TIM8))
15230
15231 /******************** TIM Instances : DMA burst feature ***********************/
15232 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15233 ((INSTANCE) == TIM2) || \
15234 ((INSTANCE) == TIM3) || \
15235 ((INSTANCE) == TIM4) || \
15236 ((INSTANCE) == TIM5) || \
15237 ((INSTANCE) == TIM8))
15238
15239 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15240 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15241 ((INSTANCE) == TIM2) || \
15242 ((INSTANCE) == TIM3) || \
15243 ((INSTANCE) == TIM4) || \
15244 ((INSTANCE) == TIM5) || \
15245 ((INSTANCE) == TIM6) || \
15246 ((INSTANCE) == TIM7) || \
15247 ((INSTANCE) == TIM8))
15248
15249 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15250 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15251 ((INSTANCE) == TIM2) || \
15252 ((INSTANCE) == TIM3) || \
15253 ((INSTANCE) == TIM4) || \
15254 ((INSTANCE) == TIM5) || \
15255 ((INSTANCE) == TIM8) || \
15256 ((INSTANCE) == TIM9) || \
15257 ((INSTANCE) == TIM12))
15258
15259 /********************** TIM Instances : 32 bit Counter ************************/
15260 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15261 ((INSTANCE) == TIM5))
15262
15263 /***************** TIM Instances : external trigger input availabe ************/
15264 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15265 ((INSTANCE) == TIM2) || \
15266 ((INSTANCE) == TIM3) || \
15267 ((INSTANCE) == TIM4) || \
15268 ((INSTANCE) == TIM5) || \
15269 ((INSTANCE) == TIM8))
15270
15271 /****************** TIM Instances : remapping capability **********************/
15272 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
15273 ((INSTANCE) == TIM5) || \
15274 ((INSTANCE) == TIM11))
15275
15276 /******************* TIM Instances : output(s) available **********************/
15277 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15278 ((((INSTANCE) == TIM1) && \
15279 (((CHANNEL) == TIM_CHANNEL_1) || \
15280 ((CHANNEL) == TIM_CHANNEL_2) || \
15281 ((CHANNEL) == TIM_CHANNEL_3) || \
15282 ((CHANNEL) == TIM_CHANNEL_4))) \
15283 || \
15284 (((INSTANCE) == TIM2) && \
15285 (((CHANNEL) == TIM_CHANNEL_1) || \
15286 ((CHANNEL) == TIM_CHANNEL_2) || \
15287 ((CHANNEL) == TIM_CHANNEL_3) || \
15288 ((CHANNEL) == TIM_CHANNEL_4))) \
15289 || \
15290 (((INSTANCE) == TIM3) && \
15291 (((CHANNEL) == TIM_CHANNEL_1) || \
15292 ((CHANNEL) == TIM_CHANNEL_2) || \
15293 ((CHANNEL) == TIM_CHANNEL_3) || \
15294 ((CHANNEL) == TIM_CHANNEL_4))) \
15295 || \
15296 (((INSTANCE) == TIM4) && \
15297 (((CHANNEL) == TIM_CHANNEL_1) || \
15298 ((CHANNEL) == TIM_CHANNEL_2) || \
15299 ((CHANNEL) == TIM_CHANNEL_3) || \
15300 ((CHANNEL) == TIM_CHANNEL_4))) \
15301 || \
15302 (((INSTANCE) == TIM5) && \
15303 (((CHANNEL) == TIM_CHANNEL_1) || \
15304 ((CHANNEL) == TIM_CHANNEL_2) || \
15305 ((CHANNEL) == TIM_CHANNEL_3) || \
15306 ((CHANNEL) == TIM_CHANNEL_4))) \
15307 || \
15308 (((INSTANCE) == TIM8) && \
15309 (((CHANNEL) == TIM_CHANNEL_1) || \
15310 ((CHANNEL) == TIM_CHANNEL_2) || \
15311 ((CHANNEL) == TIM_CHANNEL_3) || \
15312 ((CHANNEL) == TIM_CHANNEL_4))) \
15313 || \
15314 (((INSTANCE) == TIM9) && \
15315 (((CHANNEL) == TIM_CHANNEL_1) || \
15316 ((CHANNEL) == TIM_CHANNEL_2))) \
15317 || \
15318 (((INSTANCE) == TIM10) && \
15319 (((CHANNEL) == TIM_CHANNEL_1))) \
15320 || \
15321 (((INSTANCE) == TIM11) && \
15322 (((CHANNEL) == TIM_CHANNEL_1))) \
15323 || \
15324 (((INSTANCE) == TIM12) && \
15325 (((CHANNEL) == TIM_CHANNEL_1) || \
15326 ((CHANNEL) == TIM_CHANNEL_2))) \
15327 || \
15328 (((INSTANCE) == TIM13) && \
15329 (((CHANNEL) == TIM_CHANNEL_1))) \
15330 || \
15331 (((INSTANCE) == TIM14) && \
15332 (((CHANNEL) == TIM_CHANNEL_1))))
15333
15334 /************ TIM Instances : complementary output(s) available ***************/
15335 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15336 ((((INSTANCE) == TIM1) && \
15337 (((CHANNEL) == TIM_CHANNEL_1) || \
15338 ((CHANNEL) == TIM_CHANNEL_2) || \
15339 ((CHANNEL) == TIM_CHANNEL_3))) \
15340 || \
15341 (((INSTANCE) == TIM8) && \
15342 (((CHANNEL) == TIM_CHANNEL_1) || \
15343 ((CHANNEL) == TIM_CHANNEL_2) || \
15344 ((CHANNEL) == TIM_CHANNEL_3))))
15345
15346 /****************** TIM Instances : supporting counting mode selection ********/
15347 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15348 ((INSTANCE) == TIM2) || \
15349 ((INSTANCE) == TIM3) || \
15350 ((INSTANCE) == TIM4) || \
15351 ((INSTANCE) == TIM5) || \
15352 ((INSTANCE) == TIM8))
15353
15354 /****************** TIM Instances : supporting clock division *****************/
15355 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15356 ((INSTANCE) == TIM2) || \
15357 ((INSTANCE) == TIM3) || \
15358 ((INSTANCE) == TIM4) || \
15359 ((INSTANCE) == TIM5) || \
15360 ((INSTANCE) == TIM8) || \
15361 ((INSTANCE) == TIM9) || \
15362 ((INSTANCE) == TIM10)|| \
15363 ((INSTANCE) == TIM11)|| \
15364 ((INSTANCE) == TIM12)|| \
15365 ((INSTANCE) == TIM13)|| \
15366 ((INSTANCE) == TIM14))
15367
15368 /****************** TIM Instances : supporting commutation event generation ***/
15369 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15370 ((INSTANCE) == TIM8))
15371
15372
15373 /****************** TIM Instances : supporting OCxREF clear *******************/
15374 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15375 ((INSTANCE) == TIM2) || \
15376 ((INSTANCE) == TIM3) || \
15377 ((INSTANCE) == TIM4) || \
15378 ((INSTANCE) == TIM5) || \
15379 ((INSTANCE) == TIM8))
15380
15381 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15382 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15383 ((INSTANCE) == TIM2) || \
15384 ((INSTANCE) == TIM3) || \
15385 ((INSTANCE) == TIM4) || \
15386 ((INSTANCE) == TIM5) || \
15387 ((INSTANCE) == TIM8) || \
15388 ((INSTANCE) == TIM9) || \
15389 ((INSTANCE) == TIM12))
15390
15391 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15392 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15393 ((INSTANCE) == TIM2) || \
15394 ((INSTANCE) == TIM3) || \
15395 ((INSTANCE) == TIM4) || \
15396 ((INSTANCE) == TIM5) || \
15397 ((INSTANCE) == TIM8))
15398
15399 /****************** TIM Instances : supporting repetition counter *************/
15400 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15401 ((INSTANCE) == TIM8))
15402
15403 /****************** TIM Instances : supporting encoder interface **************/
15404 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15405 ((INSTANCE) == TIM2) || \
15406 ((INSTANCE) == TIM3) || \
15407 ((INSTANCE) == TIM4) || \
15408 ((INSTANCE) == TIM5) || \
15409 ((INSTANCE) == TIM8) || \
15410 ((INSTANCE) == TIM9) || \
15411 ((INSTANCE) == TIM12))
15412 /****************** TIM Instances : supporting Hall sensor interface **********/
15413 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15414 ((INSTANCE) == TIM2) || \
15415 ((INSTANCE) == TIM3) || \
15416 ((INSTANCE) == TIM4) || \
15417 ((INSTANCE) == TIM5) || \
15418 ((INSTANCE) == TIM8))
15419 /****************** TIM Instances : supporting the break function *************/
15420 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15421 ((INSTANCE) == TIM8))
15422
15423 /******************** USART Instances : Synchronous mode **********************/
15424 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15425 ((INSTANCE) == USART2) || \
15426 ((INSTANCE) == USART3) || \
15427 ((INSTANCE) == USART6))
15428
15429 /******************** UART Instances : Half-Duplex mode **********************/
15430 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15431 ((INSTANCE) == USART2) || \
15432 ((INSTANCE) == USART3) || \
15433 ((INSTANCE) == UART4) || \
15434 ((INSTANCE) == UART5) || \
15435 ((INSTANCE) == USART6))
15436
15437 /* Legacy defines */
15438 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15439
15440 /****************** UART Instances : Hardware Flow control ********************/
15441 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15442 ((INSTANCE) == USART2) || \
15443 ((INSTANCE) == USART3) || \
15444 ((INSTANCE) == USART6))
15445 /******************** UART Instances : LIN mode **********************/
15446 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15447
15448 /********************* UART Instances : Smart card mode ***********************/
15449 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15450 ((INSTANCE) == USART2) || \
15451 ((INSTANCE) == USART3) || \
15452 ((INSTANCE) == USART6))
15453
15454 /*********************** UART Instances : IRDA mode ***************************/
15455 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15456 ((INSTANCE) == USART2) || \
15457 ((INSTANCE) == USART3) || \
15458 ((INSTANCE) == UART4) || \
15459 ((INSTANCE) == UART5) || \
15460 ((INSTANCE) == USART6))
15461
15462
15463 /*********************** PCD Instances ****************************************/
15464 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15465 ((INSTANCE) == USB_OTG_HS))
15466
15467 /*********************** HCD Instances ****************************************/
15468 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15469 ((INSTANCE) == USB_OTG_HS))
15470
15471 /****************************** SDIO Instances ********************************/
15472 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15473
15474 /****************************** IWDG Instances ********************************/
15475 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15476
15477 /****************************** WWDG Instances ********************************/
15478 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15479
15480 /****************************** USB Exported Constants ************************/
15481 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
15482 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
15483 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
15484 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
15485
15486 /*
15487 * @brief Specific devices reset values definitions
15488 */
15489 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
15490 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
15491
15492 #define RCC_MAX_FREQUENCY 168000000U /*!< Max frequency of family in Hz*/
15493 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
15494 #define RCC_MAX_FREQUENCY_SCALE2 144000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
15495 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
15496 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
15497 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
15498 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
15499
15500 #define RCC_PLLN_MIN_VALUE 50U
15501 #define RCC_PLLN_MAX_VALUE 432U
15502
15503 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
15504 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
15505 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
15506 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
15507 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
15508
15509 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
15510 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
15511 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
15512 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
15513
15514 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
15515 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
15516 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
15517 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
15518 /******************************************************************************/
15519 /* For a painless codes migration between the STM32F4xx device product */
15520 /* lines, the aliases defined below are put in place to overcome the */
15521 /* differences in the interrupt handlers and IRQn definitions. */
15522 /* No need to update developed interrupt code when moving across */
15523 /* product lines within the same STM32F4 Family */
15524 /******************************************************************************/
15525 /* Aliases for __IRQn */
15526 #define FMC_IRQn FSMC_IRQn
15527
15528 /* Aliases for __IRQHandler */
15529 #define FMC_IRQHandler FSMC_IRQHandler
15530
15531 /**
15532 * @}
15533 */
15534
15535 /**
15536 * @}
15537 */
15538
15539 /**
15540 * @}
15541 */
15542
15543 #ifdef __cplusplus
15544 }
15545 #endif /* __cplusplus */
15546
15547 #endif /* __STM32F407xx_H */
15548
15549
15550
15551 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/