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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f401xc.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F401xC Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - peripherals registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f401xc
47 * @{
48 */
49
50 #ifndef __STM32F401xC_H
51 #define __STM32F401xC_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #define __FPU_PRESENT 1U /*!< FPU present */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78 /**
79 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
87 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
88 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
89 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
91 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
92 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
93 /****** STM32 specific Interrupt Numbers **********************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
99 RCC_IRQn = 5, /*!< RCC global Interrupt */
100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
112 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
113 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
114 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
115 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
116 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
117 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
118 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
119 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
120 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
121 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
122 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
123 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
124 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
125 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
126 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
127 USART1_IRQn = 37, /*!< USART1 global Interrupt */
128 USART2_IRQn = 38, /*!< USART2 global Interrupt */
129 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
130 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
131 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
132 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
133 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
134 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
135 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
136 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
137 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
138 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
139 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
140 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
141 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
142 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
143 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
144 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
145 USART6_IRQn = 71, /*!< USART6 global interrupt */
146 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
147 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
148 FPU_IRQn = 81, /*!< FPU global interrupt */
149 SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
150 } IRQn_Type;
151
152 /**
153 * @}
154 */
155
156 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
157 #include "system_stm32f4xx.h"
158 #include <stdint.h>
159
160 /** @addtogroup Peripheral_registers_structures
161 * @{
162 */
163
164 /**
165 * @brief Analog to Digital Converter
166 */
167
168 typedef struct
169 {
170 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
171 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
172 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
173 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
174 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
175 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
176 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
177 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
178 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
179 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
180 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
181 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
182 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
183 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
184 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
185 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
186 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
187 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
188 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
189 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
190 } ADC_TypeDef;
191
192 typedef struct
193 {
194 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
195 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
196 __IO uint32_t CDR; /*!< ADC common regular data register for dual
197 AND triple modes, Address offset: ADC1 base address + 0x308 */
198 } ADC_Common_TypeDef;
199
200 /**
201 * @brief CRC calculation unit
202 */
203
204 typedef struct
205 {
206 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
207 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
208 uint8_t RESERVED0; /*!< Reserved, 0x05 */
209 uint16_t RESERVED1; /*!< Reserved, 0x06 */
210 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
211 } CRC_TypeDef;
212
213 /**
214 * @brief Debug MCU
215 */
216
217 typedef struct
218 {
219 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
220 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
221 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
222 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
223 }DBGMCU_TypeDef;
224
225
226 /**
227 * @brief DMA Controller
228 */
229
230 typedef struct
231 {
232 __IO uint32_t CR; /*!< DMA stream x configuration register */
233 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
234 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
235 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
236 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
237 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
238 } DMA_Stream_TypeDef;
239
240 typedef struct
241 {
242 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
243 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
244 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
245 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
246 } DMA_TypeDef;
247
248 /**
249 * @brief External Interrupt/Event Controller
250 */
251
252 typedef struct
253 {
254 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
255 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
256 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
257 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
258 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
259 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
260 } EXTI_TypeDef;
261
262 /**
263 * @brief FLASH Registers
264 */
265
266 typedef struct
267 {
268 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
269 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
270 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
271 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
272 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
273 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
274 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
275 } FLASH_TypeDef;
276
277 /**
278 * @brief General Purpose I/O
279 */
280
281 typedef struct
282 {
283 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
284 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
285 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
286 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
287 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
288 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
289 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
290 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
291 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
292 } GPIO_TypeDef;
293
294 /**
295 * @brief System configuration controller
296 */
297
298 typedef struct
299 {
300 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
301 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
302 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
303 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
304 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
305 } SYSCFG_TypeDef;
306
307 /**
308 * @brief Inter-integrated Circuit Interface
309 */
310
311 typedef struct
312 {
313 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
314 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
315 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
316 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
317 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
318 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
319 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
320 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
321 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
322 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
323 } I2C_TypeDef;
324
325 /**
326 * @brief Independent WATCHDOG
327 */
328
329 typedef struct
330 {
331 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
332 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
333 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
334 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
335 } IWDG_TypeDef;
336
337
338 /**
339 * @brief Power Control
340 */
341
342 typedef struct
343 {
344 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
345 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
346 } PWR_TypeDef;
347
348 /**
349 * @brief Reset and Clock Control
350 */
351
352 typedef struct
353 {
354 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
355 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
356 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
357 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
358 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
359 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
360 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
361 uint32_t RESERVED0; /*!< Reserved, 0x1C */
362 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
363 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
364 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
365 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
366 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
367 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
368 uint32_t RESERVED2; /*!< Reserved, 0x3C */
369 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
370 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
371 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
372 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
373 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
374 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
375 uint32_t RESERVED4; /*!< Reserved, 0x5C */
376 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
377 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
378 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
379 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
380 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
381 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
382 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
383 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
384 uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
385 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
386 } RCC_TypeDef;
387
388 /**
389 * @brief Real-Time Clock
390 */
391
392 typedef struct
393 {
394 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
395 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
396 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
397 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
398 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
399 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
400 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
401 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
402 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
403 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
404 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
405 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
406 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
407 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
408 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
409 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
410 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
411 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
412 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
413 uint32_t RESERVED7; /*!< Reserved, 0x4C */
414 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
415 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
416 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
417 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
418 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
419 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
420 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
421 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
422 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
423 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
424 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
425 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
426 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
427 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
428 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
429 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
430 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
431 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
432 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
433 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
434 } RTC_TypeDef;
435
436 /**
437 * @brief SD host Interface
438 */
439
440 typedef struct
441 {
442 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
443 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
444 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
445 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
446 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
447 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
448 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
449 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
450 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
451 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
452 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
453 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
454 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
455 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
456 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
457 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
458 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
459 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
460 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
461 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
462 } SDIO_TypeDef;
463
464 /**
465 * @brief Serial Peripheral Interface
466 */
467
468 typedef struct
469 {
470 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
471 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
472 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
473 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
474 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
475 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
476 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
477 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
478 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
479 } SPI_TypeDef;
480
481
482 /**
483 * @brief TIM
484 */
485
486 typedef struct
487 {
488 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
489 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
490 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
491 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
492 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
493 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
494 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
495 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
496 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
497 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
498 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
499 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
500 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
501 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
502 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
503 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
504 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
505 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
506 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
507 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
508 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
509 } TIM_TypeDef;
510
511 /**
512 * @brief Universal Synchronous Asynchronous Receiver Transmitter
513 */
514
515 typedef struct
516 {
517 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
518 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
519 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
520 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
521 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
522 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
523 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
524 } USART_TypeDef;
525
526 /**
527 * @brief Window WATCHDOG
528 */
529
530 typedef struct
531 {
532 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
533 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
534 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
535 } WWDG_TypeDef;
536 /**
537 * @brief USB_OTG_Core_Registers
538 */
539 typedef struct
540 {
541 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
542 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
543 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
544 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
545 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
546 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
547 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
548 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
549 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
550 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
551 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
552 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
553 uint32_t Reserved30[2]; /*!< Reserved 030h */
554 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
555 __IO uint32_t CID; /*!< User ID Register 03Ch */
556 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
557 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
558 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
559 } USB_OTG_GlobalTypeDef;
560
561 /**
562 * @brief USB_OTG_device_Registers
563 */
564 typedef struct
565 {
566 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
567 __IO uint32_t DCTL; /*!< dev Control Register 804h */
568 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
569 uint32_t Reserved0C; /*!< Reserved 80Ch */
570 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
571 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
572 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
573 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
574 uint32_t Reserved20; /*!< Reserved 820h */
575 uint32_t Reserved9; /*!< Reserved 824h */
576 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
577 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
578 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
579 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
580 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
581 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
582 uint32_t Reserved40; /*!< dedicated EP mask 840h */
583 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
584 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
585 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
586 } USB_OTG_DeviceTypeDef;
587
588 /**
589 * @brief USB_OTG_IN_Endpoint-Specific_Register
590 */
591 typedef struct
592 {
593 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
594 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
595 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
596 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
597 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
598 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
599 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
600 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
601 } USB_OTG_INEndpointTypeDef;
602
603 /**
604 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
605 */
606 typedef struct
607 {
608 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
609 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
610 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
611 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
612 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
613 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
614 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
615 } USB_OTG_OUTEndpointTypeDef;
616
617 /**
618 * @brief USB_OTG_Host_Mode_Register_Structures
619 */
620 typedef struct
621 {
622 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
623 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
624 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
625 uint32_t Reserved40C; /*!< Reserved 40Ch */
626 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
627 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
628 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
629 } USB_OTG_HostTypeDef;
630
631 /**
632 * @brief USB_OTG_Host_Channel_Specific_Registers
633 */
634 typedef struct
635 {
636 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
637 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
638 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
639 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
640 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
641 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
642 uint32_t Reserved[2]; /*!< Reserved */
643 } USB_OTG_HostChannelTypeDef;
644
645 /**
646 * @}
647 */
648
649 /** @addtogroup Peripheral_memory_map
650 * @{
651 */
652 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
653 #define SRAM1_BASE 0x20000000U /*!< SRAM1(64 KB) base address in the alias region */
654 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
655 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(64 KB) base address in the bit-band region */
656 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
657 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
658 #define FLASH_END 0x0803FFFFU /*!< FLASH end address */
659 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
660 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
661
662 /* Legacy defines */
663 #define SRAM_BASE SRAM1_BASE
664 #define SRAM_BB_BASE SRAM1_BB_BASE
665
666 /*!< Peripheral memory map */
667 #define APB1PERIPH_BASE PERIPH_BASE
668 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
669 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
670 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
671
672 /*!< APB1 peripherals */
673 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
674 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
675 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
676 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
677 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
678 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
679 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
680 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
681 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
682 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
683 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
684 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
685 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
686 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
687 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
688 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
689
690 /*!< APB2 peripherals */
691 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
692 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
693 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
694 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
695 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
696 /* Legacy define */
697 #define ADC_BASE ADC1_COMMON_BASE
698 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
699 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
700 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
701 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
702 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
703 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
704 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
705 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
706
707 /*!< AHB1 peripherals */
708 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
709 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
710 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
711 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
712 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
713 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
714 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
715 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
716 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
717 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
718 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
719 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
720 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
721 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
722 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
723 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
724 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
725 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
726 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
727 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
728 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
729 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
730 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
731 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
732 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
733 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
734 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
735
736
737 /*!< Debug MCU registers base address */
738 #define DBGMCU_BASE 0xE0042000U
739 /*!< USB registers base address */
740 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
741
742 #define USB_OTG_GLOBAL_BASE 0x000U
743 #define USB_OTG_DEVICE_BASE 0x800U
744 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
745 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
746 #define USB_OTG_EP_REG_SIZE 0x20U
747 #define USB_OTG_HOST_BASE 0x400U
748 #define USB_OTG_HOST_PORT_BASE 0x440U
749 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
750 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
751 #define USB_OTG_PCGCCTL_BASE 0xE00U
752 #define USB_OTG_FIFO_BASE 0x1000U
753 #define USB_OTG_FIFO_SIZE 0x1000U
754
755 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
756 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
757 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
758 /**
759 * @}
760 */
761
762 /** @addtogroup Peripheral_declaration
763 * @{
764 */
765 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
766 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
767 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
768 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
769 #define RTC ((RTC_TypeDef *) RTC_BASE)
770 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
771 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
772 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
773 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
774 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
775 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
776 #define USART2 ((USART_TypeDef *) USART2_BASE)
777 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
778 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
779 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
780 #define PWR ((PWR_TypeDef *) PWR_BASE)
781 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
782 #define USART1 ((USART_TypeDef *) USART1_BASE)
783 #define USART6 ((USART_TypeDef *) USART6_BASE)
784 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
785 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
786 /* Legacy define */
787 #define ADC ADC1_COMMON
788 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
789 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
790 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
791 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
792 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
793 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
794 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
795 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
796 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
797 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
798 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
799 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
800 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
801 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
802 #define CRC ((CRC_TypeDef *) CRC_BASE)
803 #define RCC ((RCC_TypeDef *) RCC_BASE)
804 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
805 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
806 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
807 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
808 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
809 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
810 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
811 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
812 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
813 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
814 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
815 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
816 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
817 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
818 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
819 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
820 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
821 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
822 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
823 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
824 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
825
826 /**
827 * @}
828 */
829
830 /** @addtogroup Exported_constants
831 * @{
832 */
833
834 /** @addtogroup Peripheral_Registers_Bits_Definition
835 * @{
836 */
837
838 /******************************************************************************/
839 /* Peripheral Registers_Bits_Definition */
840 /******************************************************************************/
841
842 /******************************************************************************/
843 /* */
844 /* Analog to Digital Converter */
845 /* */
846 /******************************************************************************/
847
848 /******************** Bit definition for ADC_SR register ********************/
849 #define ADC_SR_AWD_Pos (0U)
850 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
851 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
852 #define ADC_SR_EOC_Pos (1U)
853 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
854 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
855 #define ADC_SR_JEOC_Pos (2U)
856 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
857 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
858 #define ADC_SR_JSTRT_Pos (3U)
859 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
860 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
861 #define ADC_SR_STRT_Pos (4U)
862 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
863 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
864 #define ADC_SR_OVR_Pos (5U)
865 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
866 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
867
868 /******************* Bit definition for ADC_CR1 register ********************/
869 #define ADC_CR1_AWDCH_Pos (0U)
870 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
871 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
872 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
873 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
874 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
875 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
876 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
877 #define ADC_CR1_EOCIE_Pos (5U)
878 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
879 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
880 #define ADC_CR1_AWDIE_Pos (6U)
881 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
882 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
883 #define ADC_CR1_JEOCIE_Pos (7U)
884 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
885 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
886 #define ADC_CR1_SCAN_Pos (8U)
887 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
888 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
889 #define ADC_CR1_AWDSGL_Pos (9U)
890 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
891 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
892 #define ADC_CR1_JAUTO_Pos (10U)
893 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
894 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
895 #define ADC_CR1_DISCEN_Pos (11U)
896 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
897 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
898 #define ADC_CR1_JDISCEN_Pos (12U)
899 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
900 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
901 #define ADC_CR1_DISCNUM_Pos (13U)
902 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
903 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
904 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
905 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
906 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
907 #define ADC_CR1_JAWDEN_Pos (22U)
908 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
909 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
910 #define ADC_CR1_AWDEN_Pos (23U)
911 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
912 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
913 #define ADC_CR1_RES_Pos (24U)
914 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
915 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
916 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
917 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
918 #define ADC_CR1_OVRIE_Pos (26U)
919 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
920 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
921
922 /******************* Bit definition for ADC_CR2 register ********************/
923 #define ADC_CR2_ADON_Pos (0U)
924 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
925 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
926 #define ADC_CR2_CONT_Pos (1U)
927 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
928 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
929 #define ADC_CR2_DMA_Pos (8U)
930 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
931 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
932 #define ADC_CR2_DDS_Pos (9U)
933 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
934 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
935 #define ADC_CR2_EOCS_Pos (10U)
936 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
937 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
938 #define ADC_CR2_ALIGN_Pos (11U)
939 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
940 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
941 #define ADC_CR2_JEXTSEL_Pos (16U)
942 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
943 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
944 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
945 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
946 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
947 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
948 #define ADC_CR2_JEXTEN_Pos (20U)
949 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
950 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
951 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
952 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
953 #define ADC_CR2_JSWSTART_Pos (22U)
954 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
955 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
956 #define ADC_CR2_EXTSEL_Pos (24U)
957 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
958 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
959 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
960 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
961 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
962 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
963 #define ADC_CR2_EXTEN_Pos (28U)
964 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
965 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
966 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
967 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
968 #define ADC_CR2_SWSTART_Pos (30U)
969 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
970 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
971
972 /****************** Bit definition for ADC_SMPR1 register *******************/
973 #define ADC_SMPR1_SMP10_Pos (0U)
974 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
975 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
976 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
977 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
978 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
979 #define ADC_SMPR1_SMP11_Pos (3U)
980 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
981 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
982 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
983 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
984 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
985 #define ADC_SMPR1_SMP12_Pos (6U)
986 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
987 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
988 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
989 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
990 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
991 #define ADC_SMPR1_SMP13_Pos (9U)
992 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
993 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
994 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
995 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
996 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
997 #define ADC_SMPR1_SMP14_Pos (12U)
998 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
999 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1000 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1001 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1002 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1003 #define ADC_SMPR1_SMP15_Pos (15U)
1004 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1005 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1006 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1007 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1008 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1009 #define ADC_SMPR1_SMP16_Pos (18U)
1010 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1011 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1012 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1013 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1014 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1015 #define ADC_SMPR1_SMP17_Pos (21U)
1016 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1017 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1018 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1019 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1020 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1021 #define ADC_SMPR1_SMP18_Pos (24U)
1022 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1023 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1024 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1025 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1026 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1027
1028 /****************** Bit definition for ADC_SMPR2 register *******************/
1029 #define ADC_SMPR2_SMP0_Pos (0U)
1030 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1031 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1032 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1033 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1034 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1035 #define ADC_SMPR2_SMP1_Pos (3U)
1036 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1037 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1038 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1039 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1040 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1041 #define ADC_SMPR2_SMP2_Pos (6U)
1042 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1043 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1044 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1045 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1046 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1047 #define ADC_SMPR2_SMP3_Pos (9U)
1048 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1049 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1050 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1051 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1052 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1053 #define ADC_SMPR2_SMP4_Pos (12U)
1054 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1055 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1056 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1057 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1058 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1059 #define ADC_SMPR2_SMP5_Pos (15U)
1060 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1061 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1062 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1063 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1064 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1065 #define ADC_SMPR2_SMP6_Pos (18U)
1066 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1067 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1068 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1069 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1070 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1071 #define ADC_SMPR2_SMP7_Pos (21U)
1072 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1073 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1074 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1075 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1076 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1077 #define ADC_SMPR2_SMP8_Pos (24U)
1078 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1079 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1080 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1081 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1082 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1083 #define ADC_SMPR2_SMP9_Pos (27U)
1084 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1085 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1086 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1087 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1088 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1089
1090 /****************** Bit definition for ADC_JOFR1 register *******************/
1091 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1092 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1093 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1094
1095 /****************** Bit definition for ADC_JOFR2 register *******************/
1096 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1097 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1098 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1099
1100 /****************** Bit definition for ADC_JOFR3 register *******************/
1101 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1102 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1103 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1104
1105 /****************** Bit definition for ADC_JOFR4 register *******************/
1106 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1107 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1108 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1109
1110 /******************* Bit definition for ADC_HTR register ********************/
1111 #define ADC_HTR_HT_Pos (0U)
1112 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1113 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1114
1115 /******************* Bit definition for ADC_LTR register ********************/
1116 #define ADC_LTR_LT_Pos (0U)
1117 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1118 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1119
1120 /******************* Bit definition for ADC_SQR1 register *******************/
1121 #define ADC_SQR1_SQ13_Pos (0U)
1122 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1123 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1124 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1125 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1126 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1127 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1128 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1129 #define ADC_SQR1_SQ14_Pos (5U)
1130 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1131 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1132 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1133 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1134 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1135 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1136 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1137 #define ADC_SQR1_SQ15_Pos (10U)
1138 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1139 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1140 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1141 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1142 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1143 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1144 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1145 #define ADC_SQR1_SQ16_Pos (15U)
1146 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1147 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1148 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1149 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1150 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1151 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1152 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1153 #define ADC_SQR1_L_Pos (20U)
1154 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1155 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1156 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1157 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1158 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1159 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1160
1161 /******************* Bit definition for ADC_SQR2 register *******************/
1162 #define ADC_SQR2_SQ7_Pos (0U)
1163 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1164 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1165 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1166 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1167 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1168 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1169 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1170 #define ADC_SQR2_SQ8_Pos (5U)
1171 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1172 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1173 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1174 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1175 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1176 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1177 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1178 #define ADC_SQR2_SQ9_Pos (10U)
1179 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1180 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1181 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1182 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1183 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1184 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1185 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1186 #define ADC_SQR2_SQ10_Pos (15U)
1187 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1188 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1189 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1190 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1191 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1192 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1193 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1194 #define ADC_SQR2_SQ11_Pos (20U)
1195 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1196 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1197 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1198 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1199 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1200 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1201 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1202 #define ADC_SQR2_SQ12_Pos (25U)
1203 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1204 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1205 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1206 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1207 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1208 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1209 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1210
1211 /******************* Bit definition for ADC_SQR3 register *******************/
1212 #define ADC_SQR3_SQ1_Pos (0U)
1213 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1214 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1215 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1216 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1217 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1218 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1219 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1220 #define ADC_SQR3_SQ2_Pos (5U)
1221 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1222 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1223 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1224 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1225 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1226 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1227 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1228 #define ADC_SQR3_SQ3_Pos (10U)
1229 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1230 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1231 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1232 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1233 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1234 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1235 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1236 #define ADC_SQR3_SQ4_Pos (15U)
1237 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1238 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1239 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1240 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1241 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1242 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1243 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1244 #define ADC_SQR3_SQ5_Pos (20U)
1245 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1246 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1247 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1248 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1249 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1250 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1251 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1252 #define ADC_SQR3_SQ6_Pos (25U)
1253 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1254 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1255 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1256 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1257 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1258 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1259 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1260
1261 /******************* Bit definition for ADC_JSQR register *******************/
1262 #define ADC_JSQR_JSQ1_Pos (0U)
1263 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1264 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1265 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1266 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1267 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1268 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1269 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1270 #define ADC_JSQR_JSQ2_Pos (5U)
1271 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1272 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1273 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1274 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1275 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1276 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1277 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1278 #define ADC_JSQR_JSQ3_Pos (10U)
1279 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1280 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1281 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1282 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1283 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1284 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1285 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1286 #define ADC_JSQR_JSQ4_Pos (15U)
1287 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1288 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1289 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1290 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1291 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1292 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1293 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1294 #define ADC_JSQR_JL_Pos (20U)
1295 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1296 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1297 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1298 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1299
1300 /******************* Bit definition for ADC_JDR1 register *******************/
1301 #define ADC_JDR1_JDATA_Pos (0U)
1302 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1303 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1304
1305 /******************* Bit definition for ADC_JDR2 register *******************/
1306 #define ADC_JDR2_JDATA_Pos (0U)
1307 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1308 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1309
1310 /******************* Bit definition for ADC_JDR3 register *******************/
1311 #define ADC_JDR3_JDATA_Pos (0U)
1312 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1313 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1314
1315 /******************* Bit definition for ADC_JDR4 register *******************/
1316 #define ADC_JDR4_JDATA_Pos (0U)
1317 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1318 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1319
1320 /******************** Bit definition for ADC_DR register ********************/
1321 #define ADC_DR_DATA_Pos (0U)
1322 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1323 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1324 #define ADC_DR_ADC2DATA_Pos (16U)
1325 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1326 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1327
1328 /******************* Bit definition for ADC_CSR register ********************/
1329 #define ADC_CSR_AWD1_Pos (0U)
1330 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1331 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1332 #define ADC_CSR_EOC1_Pos (1U)
1333 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1334 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1335 #define ADC_CSR_JEOC1_Pos (2U)
1336 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1337 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1338 #define ADC_CSR_JSTRT1_Pos (3U)
1339 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1340 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1341 #define ADC_CSR_STRT1_Pos (4U)
1342 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1343 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1344 #define ADC_CSR_OVR1_Pos (5U)
1345 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1346 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1347
1348 /* Legacy defines */
1349 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1350
1351 /******************* Bit definition for ADC_CCR register ********************/
1352 #define ADC_CCR_MULTI_Pos (0U)
1353 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1354 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1355 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1356 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1357 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1358 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1359 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1360 #define ADC_CCR_DELAY_Pos (8U)
1361 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1362 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1363 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1364 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1365 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1366 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1367 #define ADC_CCR_DDS_Pos (13U)
1368 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1369 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1370 #define ADC_CCR_DMA_Pos (14U)
1371 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1372 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1373 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1374 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1375 #define ADC_CCR_ADCPRE_Pos (16U)
1376 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1377 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1378 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1379 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1380 #define ADC_CCR_VBATE_Pos (22U)
1381 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1382 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1383 #define ADC_CCR_TSVREFE_Pos (23U)
1384 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1385 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1386
1387 /******************* Bit definition for ADC_CDR register ********************/
1388 #define ADC_CDR_DATA1_Pos (0U)
1389 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1390 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1391 #define ADC_CDR_DATA2_Pos (16U)
1392 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1393 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1394
1395 /* Legacy defines */
1396 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1397 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1398
1399 /******************************************************************************/
1400 /* */
1401 /* CRC calculation unit */
1402 /* */
1403 /******************************************************************************/
1404 /******************* Bit definition for CRC_DR register *********************/
1405 #define CRC_DR_DR_Pos (0U)
1406 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1407 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1408
1409
1410 /******************* Bit definition for CRC_IDR register ********************/
1411 #define CRC_IDR_IDR_Pos (0U)
1412 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
1413 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
1414
1415
1416 /******************** Bit definition for CRC_CR register ********************/
1417 #define CRC_CR_RESET_Pos (0U)
1418 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1419 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
1420
1421
1422 /******************************************************************************/
1423 /* */
1424 /* DMA Controller */
1425 /* */
1426 /******************************************************************************/
1427 /******************** Bits definition for DMA_SxCR register *****************/
1428 #define DMA_SxCR_CHSEL_Pos (25U)
1429 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
1430 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
1431 #define DMA_SxCR_CHSEL_0 0x02000000U
1432 #define DMA_SxCR_CHSEL_1 0x04000000U
1433 #define DMA_SxCR_CHSEL_2 0x08000000U
1434 #define DMA_SxCR_MBURST_Pos (23U)
1435 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
1436 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
1437 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
1438 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
1439 #define DMA_SxCR_PBURST_Pos (21U)
1440 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
1441 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
1442 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
1443 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
1444 #define DMA_SxCR_CT_Pos (19U)
1445 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
1446 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
1447 #define DMA_SxCR_DBM_Pos (18U)
1448 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
1449 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
1450 #define DMA_SxCR_PL_Pos (16U)
1451 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
1452 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
1453 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
1454 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
1455 #define DMA_SxCR_PINCOS_Pos (15U)
1456 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
1457 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
1458 #define DMA_SxCR_MSIZE_Pos (13U)
1459 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
1460 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
1461 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
1462 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
1463 #define DMA_SxCR_PSIZE_Pos (11U)
1464 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
1465 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
1466 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
1467 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
1468 #define DMA_SxCR_MINC_Pos (10U)
1469 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
1470 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
1471 #define DMA_SxCR_PINC_Pos (9U)
1472 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
1473 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
1474 #define DMA_SxCR_CIRC_Pos (8U)
1475 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
1476 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
1477 #define DMA_SxCR_DIR_Pos (6U)
1478 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
1479 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
1480 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
1481 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
1482 #define DMA_SxCR_PFCTRL_Pos (5U)
1483 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
1484 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
1485 #define DMA_SxCR_TCIE_Pos (4U)
1486 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
1487 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
1488 #define DMA_SxCR_HTIE_Pos (3U)
1489 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
1490 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
1491 #define DMA_SxCR_TEIE_Pos (2U)
1492 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
1493 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
1494 #define DMA_SxCR_DMEIE_Pos (1U)
1495 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
1496 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
1497 #define DMA_SxCR_EN_Pos (0U)
1498 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
1499 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
1500
1501 /* Legacy defines */
1502 #define DMA_SxCR_ACK_Pos (20U)
1503 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
1504 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
1505
1506 /******************** Bits definition for DMA_SxCNDTR register **************/
1507 #define DMA_SxNDT_Pos (0U)
1508 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
1509 #define DMA_SxNDT DMA_SxNDT_Msk
1510 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
1511 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
1512 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
1513 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
1514 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
1515 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
1516 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
1517 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
1518 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
1519 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
1520 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
1521 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
1522 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
1523 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
1524 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
1525 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
1526
1527 /******************** Bits definition for DMA_SxFCR register ****************/
1528 #define DMA_SxFCR_FEIE_Pos (7U)
1529 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
1530 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
1531 #define DMA_SxFCR_FS_Pos (3U)
1532 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
1533 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
1534 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
1535 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
1536 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
1537 #define DMA_SxFCR_DMDIS_Pos (2U)
1538 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
1539 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
1540 #define DMA_SxFCR_FTH_Pos (0U)
1541 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
1542 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
1543 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
1544 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
1545
1546 /******************** Bits definition for DMA_LISR register *****************/
1547 #define DMA_LISR_TCIF3_Pos (27U)
1548 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
1549 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
1550 #define DMA_LISR_HTIF3_Pos (26U)
1551 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
1552 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
1553 #define DMA_LISR_TEIF3_Pos (25U)
1554 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
1555 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
1556 #define DMA_LISR_DMEIF3_Pos (24U)
1557 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
1558 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
1559 #define DMA_LISR_FEIF3_Pos (22U)
1560 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
1561 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
1562 #define DMA_LISR_TCIF2_Pos (21U)
1563 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
1564 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
1565 #define DMA_LISR_HTIF2_Pos (20U)
1566 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
1567 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
1568 #define DMA_LISR_TEIF2_Pos (19U)
1569 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
1570 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
1571 #define DMA_LISR_DMEIF2_Pos (18U)
1572 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
1573 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
1574 #define DMA_LISR_FEIF2_Pos (16U)
1575 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
1576 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
1577 #define DMA_LISR_TCIF1_Pos (11U)
1578 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
1579 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
1580 #define DMA_LISR_HTIF1_Pos (10U)
1581 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
1582 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
1583 #define DMA_LISR_TEIF1_Pos (9U)
1584 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
1585 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
1586 #define DMA_LISR_DMEIF1_Pos (8U)
1587 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
1588 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
1589 #define DMA_LISR_FEIF1_Pos (6U)
1590 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
1591 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
1592 #define DMA_LISR_TCIF0_Pos (5U)
1593 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
1594 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
1595 #define DMA_LISR_HTIF0_Pos (4U)
1596 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
1597 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
1598 #define DMA_LISR_TEIF0_Pos (3U)
1599 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
1600 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
1601 #define DMA_LISR_DMEIF0_Pos (2U)
1602 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
1603 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
1604 #define DMA_LISR_FEIF0_Pos (0U)
1605 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
1606 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
1607
1608 /******************** Bits definition for DMA_HISR register *****************/
1609 #define DMA_HISR_TCIF7_Pos (27U)
1610 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
1611 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
1612 #define DMA_HISR_HTIF7_Pos (26U)
1613 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
1614 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
1615 #define DMA_HISR_TEIF7_Pos (25U)
1616 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
1617 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
1618 #define DMA_HISR_DMEIF7_Pos (24U)
1619 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
1620 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
1621 #define DMA_HISR_FEIF7_Pos (22U)
1622 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
1623 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
1624 #define DMA_HISR_TCIF6_Pos (21U)
1625 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
1626 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
1627 #define DMA_HISR_HTIF6_Pos (20U)
1628 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
1629 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
1630 #define DMA_HISR_TEIF6_Pos (19U)
1631 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
1632 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
1633 #define DMA_HISR_DMEIF6_Pos (18U)
1634 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
1635 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
1636 #define DMA_HISR_FEIF6_Pos (16U)
1637 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
1638 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
1639 #define DMA_HISR_TCIF5_Pos (11U)
1640 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
1641 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
1642 #define DMA_HISR_HTIF5_Pos (10U)
1643 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
1644 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
1645 #define DMA_HISR_TEIF5_Pos (9U)
1646 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
1647 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
1648 #define DMA_HISR_DMEIF5_Pos (8U)
1649 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
1650 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
1651 #define DMA_HISR_FEIF5_Pos (6U)
1652 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
1653 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
1654 #define DMA_HISR_TCIF4_Pos (5U)
1655 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
1656 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
1657 #define DMA_HISR_HTIF4_Pos (4U)
1658 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
1659 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
1660 #define DMA_HISR_TEIF4_Pos (3U)
1661 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
1662 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
1663 #define DMA_HISR_DMEIF4_Pos (2U)
1664 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
1665 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
1666 #define DMA_HISR_FEIF4_Pos (0U)
1667 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
1668 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
1669
1670 /******************** Bits definition for DMA_LIFCR register ****************/
1671 #define DMA_LIFCR_CTCIF3_Pos (27U)
1672 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
1673 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
1674 #define DMA_LIFCR_CHTIF3_Pos (26U)
1675 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
1676 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
1677 #define DMA_LIFCR_CTEIF3_Pos (25U)
1678 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
1679 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
1680 #define DMA_LIFCR_CDMEIF3_Pos (24U)
1681 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
1682 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
1683 #define DMA_LIFCR_CFEIF3_Pos (22U)
1684 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
1685 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
1686 #define DMA_LIFCR_CTCIF2_Pos (21U)
1687 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
1688 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
1689 #define DMA_LIFCR_CHTIF2_Pos (20U)
1690 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
1691 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
1692 #define DMA_LIFCR_CTEIF2_Pos (19U)
1693 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
1694 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
1695 #define DMA_LIFCR_CDMEIF2_Pos (18U)
1696 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
1697 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
1698 #define DMA_LIFCR_CFEIF2_Pos (16U)
1699 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
1700 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
1701 #define DMA_LIFCR_CTCIF1_Pos (11U)
1702 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
1703 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
1704 #define DMA_LIFCR_CHTIF1_Pos (10U)
1705 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
1706 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
1707 #define DMA_LIFCR_CTEIF1_Pos (9U)
1708 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
1709 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
1710 #define DMA_LIFCR_CDMEIF1_Pos (8U)
1711 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
1712 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
1713 #define DMA_LIFCR_CFEIF1_Pos (6U)
1714 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
1715 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
1716 #define DMA_LIFCR_CTCIF0_Pos (5U)
1717 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
1718 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
1719 #define DMA_LIFCR_CHTIF0_Pos (4U)
1720 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
1721 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
1722 #define DMA_LIFCR_CTEIF0_Pos (3U)
1723 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
1724 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
1725 #define DMA_LIFCR_CDMEIF0_Pos (2U)
1726 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
1727 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
1728 #define DMA_LIFCR_CFEIF0_Pos (0U)
1729 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
1730 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
1731
1732 /******************** Bits definition for DMA_HIFCR register ****************/
1733 #define DMA_HIFCR_CTCIF7_Pos (27U)
1734 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
1735 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
1736 #define DMA_HIFCR_CHTIF7_Pos (26U)
1737 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
1738 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
1739 #define DMA_HIFCR_CTEIF7_Pos (25U)
1740 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
1741 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
1742 #define DMA_HIFCR_CDMEIF7_Pos (24U)
1743 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
1744 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
1745 #define DMA_HIFCR_CFEIF7_Pos (22U)
1746 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
1747 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
1748 #define DMA_HIFCR_CTCIF6_Pos (21U)
1749 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
1750 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
1751 #define DMA_HIFCR_CHTIF6_Pos (20U)
1752 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
1753 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
1754 #define DMA_HIFCR_CTEIF6_Pos (19U)
1755 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
1756 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
1757 #define DMA_HIFCR_CDMEIF6_Pos (18U)
1758 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
1759 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
1760 #define DMA_HIFCR_CFEIF6_Pos (16U)
1761 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
1762 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
1763 #define DMA_HIFCR_CTCIF5_Pos (11U)
1764 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
1765 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
1766 #define DMA_HIFCR_CHTIF5_Pos (10U)
1767 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
1768 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
1769 #define DMA_HIFCR_CTEIF5_Pos (9U)
1770 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
1771 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
1772 #define DMA_HIFCR_CDMEIF5_Pos (8U)
1773 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
1774 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
1775 #define DMA_HIFCR_CFEIF5_Pos (6U)
1776 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
1777 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
1778 #define DMA_HIFCR_CTCIF4_Pos (5U)
1779 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
1780 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
1781 #define DMA_HIFCR_CHTIF4_Pos (4U)
1782 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
1783 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
1784 #define DMA_HIFCR_CTEIF4_Pos (3U)
1785 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
1786 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
1787 #define DMA_HIFCR_CDMEIF4_Pos (2U)
1788 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
1789 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
1790 #define DMA_HIFCR_CFEIF4_Pos (0U)
1791 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
1792 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
1793
1794 /****************** Bit definition for DMA_SxPAR register ********************/
1795 #define DMA_SxPAR_PA_Pos (0U)
1796 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
1797 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
1798
1799 /****************** Bit definition for DMA_SxM0AR register ********************/
1800 #define DMA_SxM0AR_M0A_Pos (0U)
1801 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
1802 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
1803
1804 /****************** Bit definition for DMA_SxM1AR register ********************/
1805 #define DMA_SxM1AR_M1A_Pos (0U)
1806 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
1807 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
1808
1809
1810 /******************************************************************************/
1811 /* */
1812 /* External Interrupt/Event Controller */
1813 /* */
1814 /******************************************************************************/
1815 /******************* Bit definition for EXTI_IMR register *******************/
1816 #define EXTI_IMR_MR0_Pos (0U)
1817 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
1818 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
1819 #define EXTI_IMR_MR1_Pos (1U)
1820 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
1821 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
1822 #define EXTI_IMR_MR2_Pos (2U)
1823 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
1824 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
1825 #define EXTI_IMR_MR3_Pos (3U)
1826 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
1827 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
1828 #define EXTI_IMR_MR4_Pos (4U)
1829 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
1830 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
1831 #define EXTI_IMR_MR5_Pos (5U)
1832 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
1833 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
1834 #define EXTI_IMR_MR6_Pos (6U)
1835 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
1836 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
1837 #define EXTI_IMR_MR7_Pos (7U)
1838 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
1839 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
1840 #define EXTI_IMR_MR8_Pos (8U)
1841 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
1842 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
1843 #define EXTI_IMR_MR9_Pos (9U)
1844 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
1845 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
1846 #define EXTI_IMR_MR10_Pos (10U)
1847 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
1848 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
1849 #define EXTI_IMR_MR11_Pos (11U)
1850 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
1851 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
1852 #define EXTI_IMR_MR12_Pos (12U)
1853 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
1854 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
1855 #define EXTI_IMR_MR13_Pos (13U)
1856 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
1857 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
1858 #define EXTI_IMR_MR14_Pos (14U)
1859 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
1860 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
1861 #define EXTI_IMR_MR15_Pos (15U)
1862 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
1863 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
1864 #define EXTI_IMR_MR16_Pos (16U)
1865 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
1866 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
1867 #define EXTI_IMR_MR17_Pos (17U)
1868 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
1869 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
1870 #define EXTI_IMR_MR18_Pos (18U)
1871 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
1872 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
1873 #define EXTI_IMR_MR19_Pos (19U)
1874 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
1875 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
1876 #define EXTI_IMR_MR20_Pos (20U)
1877 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
1878 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
1879 #define EXTI_IMR_MR21_Pos (21U)
1880 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
1881 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
1882 #define EXTI_IMR_MR22_Pos (22U)
1883 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
1884 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
1885
1886 /* Reference Defines */
1887 #define EXTI_IMR_IM0 EXTI_IMR_MR0
1888 #define EXTI_IMR_IM1 EXTI_IMR_MR1
1889 #define EXTI_IMR_IM2 EXTI_IMR_MR2
1890 #define EXTI_IMR_IM3 EXTI_IMR_MR3
1891 #define EXTI_IMR_IM4 EXTI_IMR_MR4
1892 #define EXTI_IMR_IM5 EXTI_IMR_MR5
1893 #define EXTI_IMR_IM6 EXTI_IMR_MR6
1894 #define EXTI_IMR_IM7 EXTI_IMR_MR7
1895 #define EXTI_IMR_IM8 EXTI_IMR_MR8
1896 #define EXTI_IMR_IM9 EXTI_IMR_MR9
1897 #define EXTI_IMR_IM10 EXTI_IMR_MR10
1898 #define EXTI_IMR_IM11 EXTI_IMR_MR11
1899 #define EXTI_IMR_IM12 EXTI_IMR_MR12
1900 #define EXTI_IMR_IM13 EXTI_IMR_MR13
1901 #define EXTI_IMR_IM14 EXTI_IMR_MR14
1902 #define EXTI_IMR_IM15 EXTI_IMR_MR15
1903 #define EXTI_IMR_IM16 EXTI_IMR_MR16
1904 #define EXTI_IMR_IM17 EXTI_IMR_MR17
1905 #define EXTI_IMR_IM18 EXTI_IMR_MR18
1906 #define EXTI_IMR_IM19 EXTI_IMR_MR19
1907 #define EXTI_IMR_IM20 EXTI_IMR_MR20
1908 #define EXTI_IMR_IM21 EXTI_IMR_MR21
1909 #define EXTI_IMR_IM22 EXTI_IMR_MR22
1910 #define EXTI_IMR_IM_Pos (0U)
1911 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
1912 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
1913
1914 /******************* Bit definition for EXTI_EMR register *******************/
1915 #define EXTI_EMR_MR0_Pos (0U)
1916 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
1917 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
1918 #define EXTI_EMR_MR1_Pos (1U)
1919 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
1920 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
1921 #define EXTI_EMR_MR2_Pos (2U)
1922 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
1923 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
1924 #define EXTI_EMR_MR3_Pos (3U)
1925 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
1926 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
1927 #define EXTI_EMR_MR4_Pos (4U)
1928 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
1929 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
1930 #define EXTI_EMR_MR5_Pos (5U)
1931 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
1932 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
1933 #define EXTI_EMR_MR6_Pos (6U)
1934 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
1935 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
1936 #define EXTI_EMR_MR7_Pos (7U)
1937 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
1938 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
1939 #define EXTI_EMR_MR8_Pos (8U)
1940 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
1941 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
1942 #define EXTI_EMR_MR9_Pos (9U)
1943 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
1944 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
1945 #define EXTI_EMR_MR10_Pos (10U)
1946 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
1947 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
1948 #define EXTI_EMR_MR11_Pos (11U)
1949 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
1950 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
1951 #define EXTI_EMR_MR12_Pos (12U)
1952 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
1953 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
1954 #define EXTI_EMR_MR13_Pos (13U)
1955 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
1956 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
1957 #define EXTI_EMR_MR14_Pos (14U)
1958 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
1959 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
1960 #define EXTI_EMR_MR15_Pos (15U)
1961 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
1962 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
1963 #define EXTI_EMR_MR16_Pos (16U)
1964 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
1965 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
1966 #define EXTI_EMR_MR17_Pos (17U)
1967 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
1968 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
1969 #define EXTI_EMR_MR18_Pos (18U)
1970 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
1971 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
1972 #define EXTI_EMR_MR19_Pos (19U)
1973 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
1974 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
1975 #define EXTI_EMR_MR20_Pos (20U)
1976 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
1977 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
1978 #define EXTI_EMR_MR21_Pos (21U)
1979 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
1980 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
1981 #define EXTI_EMR_MR22_Pos (22U)
1982 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
1983 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
1984
1985 /* Reference Defines */
1986 #define EXTI_EMR_EM0 EXTI_EMR_MR0
1987 #define EXTI_EMR_EM1 EXTI_EMR_MR1
1988 #define EXTI_EMR_EM2 EXTI_EMR_MR2
1989 #define EXTI_EMR_EM3 EXTI_EMR_MR3
1990 #define EXTI_EMR_EM4 EXTI_EMR_MR4
1991 #define EXTI_EMR_EM5 EXTI_EMR_MR5
1992 #define EXTI_EMR_EM6 EXTI_EMR_MR6
1993 #define EXTI_EMR_EM7 EXTI_EMR_MR7
1994 #define EXTI_EMR_EM8 EXTI_EMR_MR8
1995 #define EXTI_EMR_EM9 EXTI_EMR_MR9
1996 #define EXTI_EMR_EM10 EXTI_EMR_MR10
1997 #define EXTI_EMR_EM11 EXTI_EMR_MR11
1998 #define EXTI_EMR_EM12 EXTI_EMR_MR12
1999 #define EXTI_EMR_EM13 EXTI_EMR_MR13
2000 #define EXTI_EMR_EM14 EXTI_EMR_MR14
2001 #define EXTI_EMR_EM15 EXTI_EMR_MR15
2002 #define EXTI_EMR_EM16 EXTI_EMR_MR16
2003 #define EXTI_EMR_EM17 EXTI_EMR_MR17
2004 #define EXTI_EMR_EM18 EXTI_EMR_MR18
2005 #define EXTI_EMR_EM19 EXTI_EMR_MR19
2006 #define EXTI_EMR_EM20 EXTI_EMR_MR20
2007 #define EXTI_EMR_EM21 EXTI_EMR_MR21
2008 #define EXTI_EMR_EM22 EXTI_EMR_MR22
2009
2010 /****************** Bit definition for EXTI_RTSR register *******************/
2011 #define EXTI_RTSR_TR0_Pos (0U)
2012 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
2013 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
2014 #define EXTI_RTSR_TR1_Pos (1U)
2015 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
2016 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
2017 #define EXTI_RTSR_TR2_Pos (2U)
2018 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
2019 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
2020 #define EXTI_RTSR_TR3_Pos (3U)
2021 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
2022 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
2023 #define EXTI_RTSR_TR4_Pos (4U)
2024 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
2025 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
2026 #define EXTI_RTSR_TR5_Pos (5U)
2027 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
2028 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
2029 #define EXTI_RTSR_TR6_Pos (6U)
2030 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
2031 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
2032 #define EXTI_RTSR_TR7_Pos (7U)
2033 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
2034 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
2035 #define EXTI_RTSR_TR8_Pos (8U)
2036 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
2037 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
2038 #define EXTI_RTSR_TR9_Pos (9U)
2039 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
2040 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
2041 #define EXTI_RTSR_TR10_Pos (10U)
2042 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
2043 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
2044 #define EXTI_RTSR_TR11_Pos (11U)
2045 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
2046 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
2047 #define EXTI_RTSR_TR12_Pos (12U)
2048 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
2049 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
2050 #define EXTI_RTSR_TR13_Pos (13U)
2051 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
2052 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
2053 #define EXTI_RTSR_TR14_Pos (14U)
2054 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
2055 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
2056 #define EXTI_RTSR_TR15_Pos (15U)
2057 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
2058 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
2059 #define EXTI_RTSR_TR16_Pos (16U)
2060 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
2061 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
2062 #define EXTI_RTSR_TR17_Pos (17U)
2063 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
2064 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
2065 #define EXTI_RTSR_TR18_Pos (18U)
2066 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
2067 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
2068 #define EXTI_RTSR_TR19_Pos (19U)
2069 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
2070 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
2071 #define EXTI_RTSR_TR20_Pos (20U)
2072 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
2073 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
2074 #define EXTI_RTSR_TR21_Pos (21U)
2075 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
2076 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
2077 #define EXTI_RTSR_TR22_Pos (22U)
2078 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
2079 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
2080
2081 /****************** Bit definition for EXTI_FTSR register *******************/
2082 #define EXTI_FTSR_TR0_Pos (0U)
2083 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
2084 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
2085 #define EXTI_FTSR_TR1_Pos (1U)
2086 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
2087 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
2088 #define EXTI_FTSR_TR2_Pos (2U)
2089 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
2090 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
2091 #define EXTI_FTSR_TR3_Pos (3U)
2092 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
2093 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
2094 #define EXTI_FTSR_TR4_Pos (4U)
2095 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
2096 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
2097 #define EXTI_FTSR_TR5_Pos (5U)
2098 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
2099 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
2100 #define EXTI_FTSR_TR6_Pos (6U)
2101 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
2102 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
2103 #define EXTI_FTSR_TR7_Pos (7U)
2104 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
2105 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
2106 #define EXTI_FTSR_TR8_Pos (8U)
2107 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
2108 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
2109 #define EXTI_FTSR_TR9_Pos (9U)
2110 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
2111 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
2112 #define EXTI_FTSR_TR10_Pos (10U)
2113 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
2114 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
2115 #define EXTI_FTSR_TR11_Pos (11U)
2116 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
2117 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
2118 #define EXTI_FTSR_TR12_Pos (12U)
2119 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
2120 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
2121 #define EXTI_FTSR_TR13_Pos (13U)
2122 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
2123 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
2124 #define EXTI_FTSR_TR14_Pos (14U)
2125 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
2126 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
2127 #define EXTI_FTSR_TR15_Pos (15U)
2128 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
2129 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
2130 #define EXTI_FTSR_TR16_Pos (16U)
2131 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
2132 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
2133 #define EXTI_FTSR_TR17_Pos (17U)
2134 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
2135 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
2136 #define EXTI_FTSR_TR18_Pos (18U)
2137 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
2138 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
2139 #define EXTI_FTSR_TR19_Pos (19U)
2140 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
2141 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
2142 #define EXTI_FTSR_TR20_Pos (20U)
2143 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
2144 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
2145 #define EXTI_FTSR_TR21_Pos (21U)
2146 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
2147 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
2148 #define EXTI_FTSR_TR22_Pos (22U)
2149 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
2150 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
2151
2152 /****************** Bit definition for EXTI_SWIER register ******************/
2153 #define EXTI_SWIER_SWIER0_Pos (0U)
2154 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
2155 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
2156 #define EXTI_SWIER_SWIER1_Pos (1U)
2157 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
2158 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
2159 #define EXTI_SWIER_SWIER2_Pos (2U)
2160 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
2161 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
2162 #define EXTI_SWIER_SWIER3_Pos (3U)
2163 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
2164 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
2165 #define EXTI_SWIER_SWIER4_Pos (4U)
2166 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
2167 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
2168 #define EXTI_SWIER_SWIER5_Pos (5U)
2169 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
2170 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
2171 #define EXTI_SWIER_SWIER6_Pos (6U)
2172 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
2173 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
2174 #define EXTI_SWIER_SWIER7_Pos (7U)
2175 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
2176 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
2177 #define EXTI_SWIER_SWIER8_Pos (8U)
2178 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
2179 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
2180 #define EXTI_SWIER_SWIER9_Pos (9U)
2181 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
2182 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
2183 #define EXTI_SWIER_SWIER10_Pos (10U)
2184 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
2185 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
2186 #define EXTI_SWIER_SWIER11_Pos (11U)
2187 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
2188 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
2189 #define EXTI_SWIER_SWIER12_Pos (12U)
2190 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
2191 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
2192 #define EXTI_SWIER_SWIER13_Pos (13U)
2193 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
2194 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
2195 #define EXTI_SWIER_SWIER14_Pos (14U)
2196 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
2197 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
2198 #define EXTI_SWIER_SWIER15_Pos (15U)
2199 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
2200 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
2201 #define EXTI_SWIER_SWIER16_Pos (16U)
2202 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
2203 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
2204 #define EXTI_SWIER_SWIER17_Pos (17U)
2205 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
2206 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
2207 #define EXTI_SWIER_SWIER18_Pos (18U)
2208 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
2209 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
2210 #define EXTI_SWIER_SWIER19_Pos (19U)
2211 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
2212 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
2213 #define EXTI_SWIER_SWIER20_Pos (20U)
2214 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
2215 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
2216 #define EXTI_SWIER_SWIER21_Pos (21U)
2217 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
2218 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
2219 #define EXTI_SWIER_SWIER22_Pos (22U)
2220 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
2221 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
2222
2223 /******************* Bit definition for EXTI_PR register ********************/
2224 #define EXTI_PR_PR0_Pos (0U)
2225 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
2226 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
2227 #define EXTI_PR_PR1_Pos (1U)
2228 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
2229 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
2230 #define EXTI_PR_PR2_Pos (2U)
2231 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
2232 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
2233 #define EXTI_PR_PR3_Pos (3U)
2234 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
2235 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
2236 #define EXTI_PR_PR4_Pos (4U)
2237 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
2238 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
2239 #define EXTI_PR_PR5_Pos (5U)
2240 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
2241 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
2242 #define EXTI_PR_PR6_Pos (6U)
2243 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
2244 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
2245 #define EXTI_PR_PR7_Pos (7U)
2246 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
2247 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
2248 #define EXTI_PR_PR8_Pos (8U)
2249 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
2250 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
2251 #define EXTI_PR_PR9_Pos (9U)
2252 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
2253 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
2254 #define EXTI_PR_PR10_Pos (10U)
2255 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
2256 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
2257 #define EXTI_PR_PR11_Pos (11U)
2258 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
2259 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
2260 #define EXTI_PR_PR12_Pos (12U)
2261 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
2262 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
2263 #define EXTI_PR_PR13_Pos (13U)
2264 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
2265 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
2266 #define EXTI_PR_PR14_Pos (14U)
2267 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
2268 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
2269 #define EXTI_PR_PR15_Pos (15U)
2270 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
2271 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
2272 #define EXTI_PR_PR16_Pos (16U)
2273 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
2274 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
2275 #define EXTI_PR_PR17_Pos (17U)
2276 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
2277 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
2278 #define EXTI_PR_PR18_Pos (18U)
2279 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
2280 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
2281 #define EXTI_PR_PR19_Pos (19U)
2282 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
2283 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
2284 #define EXTI_PR_PR20_Pos (20U)
2285 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
2286 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
2287 #define EXTI_PR_PR21_Pos (21U)
2288 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
2289 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
2290 #define EXTI_PR_PR22_Pos (22U)
2291 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
2292 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
2293
2294 /******************************************************************************/
2295 /* */
2296 /* FLASH */
2297 /* */
2298 /******************************************************************************/
2299 /******************* Bits definition for FLASH_ACR register *****************/
2300 #define FLASH_ACR_LATENCY_Pos (0U)
2301 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
2302 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
2303 #define FLASH_ACR_LATENCY_0WS 0x00000000U
2304 #define FLASH_ACR_LATENCY_1WS 0x00000001U
2305 #define FLASH_ACR_LATENCY_2WS 0x00000002U
2306 #define FLASH_ACR_LATENCY_3WS 0x00000003U
2307 #define FLASH_ACR_LATENCY_4WS 0x00000004U
2308 #define FLASH_ACR_LATENCY_5WS 0x00000005U
2309 #define FLASH_ACR_LATENCY_6WS 0x00000006U
2310 #define FLASH_ACR_LATENCY_7WS 0x00000007U
2311
2312 #define FLASH_ACR_PRFTEN_Pos (8U)
2313 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
2314 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
2315 #define FLASH_ACR_ICEN_Pos (9U)
2316 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
2317 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
2318 #define FLASH_ACR_DCEN_Pos (10U)
2319 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
2320 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
2321 #define FLASH_ACR_ICRST_Pos (11U)
2322 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
2323 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
2324 #define FLASH_ACR_DCRST_Pos (12U)
2325 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
2326 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
2327 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
2328 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
2329 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
2330 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
2331 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
2332 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
2333
2334 /******************* Bits definition for FLASH_SR register ******************/
2335 #define FLASH_SR_EOP_Pos (0U)
2336 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
2337 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
2338 #define FLASH_SR_SOP_Pos (1U)
2339 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
2340 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
2341 #define FLASH_SR_WRPERR_Pos (4U)
2342 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
2343 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
2344 #define FLASH_SR_PGAERR_Pos (5U)
2345 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
2346 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
2347 #define FLASH_SR_PGPERR_Pos (6U)
2348 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
2349 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
2350 #define FLASH_SR_PGSERR_Pos (7U)
2351 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
2352 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
2353 #define FLASH_SR_RDERR_Pos (8U)
2354 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
2355 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
2356 #define FLASH_SR_BSY_Pos (16U)
2357 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
2358 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
2359
2360 /******************* Bits definition for FLASH_CR register ******************/
2361 #define FLASH_CR_PG_Pos (0U)
2362 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
2363 #define FLASH_CR_PG FLASH_CR_PG_Msk
2364 #define FLASH_CR_SER_Pos (1U)
2365 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
2366 #define FLASH_CR_SER FLASH_CR_SER_Msk
2367 #define FLASH_CR_MER_Pos (2U)
2368 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
2369 #define FLASH_CR_MER FLASH_CR_MER_Msk
2370 #define FLASH_CR_SNB_Pos (3U)
2371 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
2372 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
2373 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
2374 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
2375 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
2376 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
2377 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
2378 #define FLASH_CR_PSIZE_Pos (8U)
2379 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
2380 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
2381 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
2382 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
2383 #define FLASH_CR_STRT_Pos (16U)
2384 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
2385 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
2386 #define FLASH_CR_EOPIE_Pos (24U)
2387 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
2388 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
2389 #define FLASH_CR_LOCK_Pos (31U)
2390 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
2391 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
2392
2393 /******************* Bits definition for FLASH_OPTCR register ***************/
2394 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
2395 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
2396 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
2397 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
2398 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
2399 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
2400
2401 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
2402 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
2403 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
2404 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
2405 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
2406 #define FLASH_OPTCR_WDG_SW_Pos (5U)
2407 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
2408 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
2409 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
2410 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
2411 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
2412 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
2413 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
2414 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
2415 #define FLASH_OPTCR_RDP_Pos (8U)
2416 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
2417 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
2418 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
2419 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
2420 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
2421 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
2422 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
2423 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
2424 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
2425 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
2426 #define FLASH_OPTCR_nWRP_Pos (16U)
2427 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
2428 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
2429 #define FLASH_OPTCR_nWRP_0 0x00010000U
2430 #define FLASH_OPTCR_nWRP_1 0x00020000U
2431 #define FLASH_OPTCR_nWRP_2 0x00040000U
2432 #define FLASH_OPTCR_nWRP_3 0x00080000U
2433 #define FLASH_OPTCR_nWRP_4 0x00100000U
2434 #define FLASH_OPTCR_nWRP_5 0x00200000U
2435 #define FLASH_OPTCR_nWRP_6 0x00400000U
2436 #define FLASH_OPTCR_nWRP_7 0x00800000U
2437 #define FLASH_OPTCR_nWRP_8 0x01000000U
2438 #define FLASH_OPTCR_nWRP_9 0x02000000U
2439 #define FLASH_OPTCR_nWRP_10 0x04000000U
2440 #define FLASH_OPTCR_nWRP_11 0x08000000U
2441
2442 /****************** Bits definition for FLASH_OPTCR1 register ***************/
2443 #define FLASH_OPTCR1_nWRP_Pos (16U)
2444 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
2445 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
2446 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
2447 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
2448 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
2449 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
2450 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
2451 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
2452 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
2453 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
2454 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
2455 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
2456 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
2457 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
2458
2459 /******************************************************************************/
2460 /* */
2461 /* General Purpose I/O */
2462 /* */
2463 /******************************************************************************/
2464 /****************** Bits definition for GPIO_MODER register *****************/
2465 #define GPIO_MODER_MODE0_Pos (0U)
2466 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
2467 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
2468 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
2469 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
2470 #define GPIO_MODER_MODE1_Pos (2U)
2471 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
2472 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
2473 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
2474 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
2475 #define GPIO_MODER_MODE2_Pos (4U)
2476 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
2477 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
2478 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
2479 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
2480 #define GPIO_MODER_MODE3_Pos (6U)
2481 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
2482 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
2483 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
2484 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
2485 #define GPIO_MODER_MODE4_Pos (8U)
2486 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
2487 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
2488 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
2489 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
2490 #define GPIO_MODER_MODE5_Pos (10U)
2491 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
2492 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
2493 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
2494 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
2495 #define GPIO_MODER_MODE6_Pos (12U)
2496 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
2497 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
2498 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
2499 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
2500 #define GPIO_MODER_MODE7_Pos (14U)
2501 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
2502 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
2503 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
2504 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
2505 #define GPIO_MODER_MODE8_Pos (16U)
2506 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
2507 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
2508 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
2509 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
2510 #define GPIO_MODER_MODE9_Pos (18U)
2511 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
2512 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
2513 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
2514 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
2515 #define GPIO_MODER_MODE10_Pos (20U)
2516 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
2517 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
2518 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
2519 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
2520 #define GPIO_MODER_MODE11_Pos (22U)
2521 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
2522 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
2523 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
2524 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
2525 #define GPIO_MODER_MODE12_Pos (24U)
2526 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
2527 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
2528 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
2529 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
2530 #define GPIO_MODER_MODE13_Pos (26U)
2531 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
2532 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
2533 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
2534 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
2535 #define GPIO_MODER_MODE14_Pos (28U)
2536 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
2537 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
2538 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
2539 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
2540 #define GPIO_MODER_MODE15_Pos (30U)
2541 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
2542 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
2543 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
2544 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
2545
2546 /* Legacy defines */
2547 #define GPIO_MODER_MODER0_Pos (0U)
2548 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
2549 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
2550 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
2551 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
2552 #define GPIO_MODER_MODER1_Pos (2U)
2553 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
2554 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
2555 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
2556 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
2557 #define GPIO_MODER_MODER2_Pos (4U)
2558 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
2559 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
2560 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
2561 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
2562 #define GPIO_MODER_MODER3_Pos (6U)
2563 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
2564 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
2565 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
2566 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
2567 #define GPIO_MODER_MODER4_Pos (8U)
2568 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
2569 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
2570 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
2571 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
2572 #define GPIO_MODER_MODER5_Pos (10U)
2573 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
2574 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
2575 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
2576 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
2577 #define GPIO_MODER_MODER6_Pos (12U)
2578 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
2579 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
2580 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
2581 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
2582 #define GPIO_MODER_MODER7_Pos (14U)
2583 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
2584 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
2585 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
2586 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
2587 #define GPIO_MODER_MODER8_Pos (16U)
2588 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
2589 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
2590 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
2591 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
2592 #define GPIO_MODER_MODER9_Pos (18U)
2593 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
2594 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
2595 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
2596 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
2597 #define GPIO_MODER_MODER10_Pos (20U)
2598 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
2599 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
2600 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
2601 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
2602 #define GPIO_MODER_MODER11_Pos (22U)
2603 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
2604 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
2605 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
2606 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
2607 #define GPIO_MODER_MODER12_Pos (24U)
2608 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
2609 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
2610 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
2611 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
2612 #define GPIO_MODER_MODER13_Pos (26U)
2613 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
2614 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
2615 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
2616 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
2617 #define GPIO_MODER_MODER14_Pos (28U)
2618 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
2619 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
2620 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
2621 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
2622 #define GPIO_MODER_MODER15_Pos (30U)
2623 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
2624 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
2625 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
2626 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
2627
2628 /****************** Bits definition for GPIO_OTYPER register ****************/
2629 #define GPIO_OTYPER_OT0_Pos (0U)
2630 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
2631 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
2632 #define GPIO_OTYPER_OT1_Pos (1U)
2633 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
2634 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
2635 #define GPIO_OTYPER_OT2_Pos (2U)
2636 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
2637 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
2638 #define GPIO_OTYPER_OT3_Pos (3U)
2639 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
2640 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
2641 #define GPIO_OTYPER_OT4_Pos (4U)
2642 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
2643 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
2644 #define GPIO_OTYPER_OT5_Pos (5U)
2645 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
2646 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
2647 #define GPIO_OTYPER_OT6_Pos (6U)
2648 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
2649 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
2650 #define GPIO_OTYPER_OT7_Pos (7U)
2651 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
2652 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
2653 #define GPIO_OTYPER_OT8_Pos (8U)
2654 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
2655 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
2656 #define GPIO_OTYPER_OT9_Pos (9U)
2657 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
2658 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
2659 #define GPIO_OTYPER_OT10_Pos (10U)
2660 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
2661 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
2662 #define GPIO_OTYPER_OT11_Pos (11U)
2663 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
2664 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
2665 #define GPIO_OTYPER_OT12_Pos (12U)
2666 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
2667 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
2668 #define GPIO_OTYPER_OT13_Pos (13U)
2669 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
2670 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
2671 #define GPIO_OTYPER_OT14_Pos (14U)
2672 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
2673 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
2674 #define GPIO_OTYPER_OT15_Pos (15U)
2675 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
2676 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
2677
2678 /* Legacy defines */
2679 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
2680 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
2681 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
2682 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
2683 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
2684 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
2685 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
2686 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
2687 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
2688 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
2689 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
2690 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
2691 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
2692 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
2693 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
2694 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
2695
2696 /****************** Bits definition for GPIO_OSPEEDR register ***************/
2697 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
2698 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
2699 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
2700 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
2701 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
2702 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
2703 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
2704 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
2705 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
2706 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
2707 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
2708 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
2709 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
2710 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
2711 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
2712 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
2713 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
2714 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
2715 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
2716 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
2717 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
2718 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
2719 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
2720 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
2721 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
2722 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
2723 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
2724 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
2725 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
2726 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
2727 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
2728 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
2729 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
2730 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
2731 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
2732 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
2733 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
2734 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
2735 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
2736 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
2737 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
2738 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
2739 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
2740 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
2741 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
2742 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
2743 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
2744 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
2745 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
2746 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
2747 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
2748 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
2749 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
2750 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
2751 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
2752 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
2753 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
2754 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
2755 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
2756 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
2757 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
2758 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
2759 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
2760 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
2761 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
2762 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
2763 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
2764 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
2765 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
2766 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
2767 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
2768 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
2769 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
2770 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
2771 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
2772 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
2773 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
2774 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
2775 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
2776 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
2777
2778 /* Legacy defines */
2779 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
2780 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
2781 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
2782 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
2783 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
2784 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
2785 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
2786 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
2787 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
2788 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
2789 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
2790 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
2791 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
2792 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
2793 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
2794 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
2795 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
2796 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
2797 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
2798 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
2799 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
2800 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
2801 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
2802 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
2803 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
2804 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
2805 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
2806 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
2807 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
2808 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
2809 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
2810 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
2811 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
2812 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
2813 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
2814 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
2815 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
2816 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
2817 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
2818 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
2819 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
2820 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
2821 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
2822 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
2823 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
2824 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
2825 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
2826 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
2827
2828 /****************** Bits definition for GPIO_PUPDR register *****************/
2829 #define GPIO_PUPDR_PUPD0_Pos (0U)
2830 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
2831 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
2832 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
2833 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
2834 #define GPIO_PUPDR_PUPD1_Pos (2U)
2835 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
2836 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
2837 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
2838 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
2839 #define GPIO_PUPDR_PUPD2_Pos (4U)
2840 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
2841 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
2842 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
2843 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
2844 #define GPIO_PUPDR_PUPD3_Pos (6U)
2845 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
2846 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
2847 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
2848 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
2849 #define GPIO_PUPDR_PUPD4_Pos (8U)
2850 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
2851 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
2852 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
2853 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
2854 #define GPIO_PUPDR_PUPD5_Pos (10U)
2855 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
2856 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
2857 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
2858 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
2859 #define GPIO_PUPDR_PUPD6_Pos (12U)
2860 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
2861 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
2862 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
2863 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
2864 #define GPIO_PUPDR_PUPD7_Pos (14U)
2865 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
2866 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
2867 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
2868 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
2869 #define GPIO_PUPDR_PUPD8_Pos (16U)
2870 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
2871 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
2872 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
2873 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
2874 #define GPIO_PUPDR_PUPD9_Pos (18U)
2875 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
2876 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
2877 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
2878 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
2879 #define GPIO_PUPDR_PUPD10_Pos (20U)
2880 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
2881 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
2882 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
2883 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
2884 #define GPIO_PUPDR_PUPD11_Pos (22U)
2885 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
2886 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
2887 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
2888 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
2889 #define GPIO_PUPDR_PUPD12_Pos (24U)
2890 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
2891 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
2892 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
2893 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
2894 #define GPIO_PUPDR_PUPD13_Pos (26U)
2895 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
2896 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
2897 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
2898 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
2899 #define GPIO_PUPDR_PUPD14_Pos (28U)
2900 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
2901 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
2902 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
2903 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
2904 #define GPIO_PUPDR_PUPD15_Pos (30U)
2905 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
2906 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
2907 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
2908 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
2909
2910 /* Legacy defines */
2911 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
2912 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
2913 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
2914 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
2915 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
2916 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
2917 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
2918 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
2919 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
2920 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
2921 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
2922 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
2923 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
2924 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
2925 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
2926 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
2927 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
2928 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
2929 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
2930 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
2931 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
2932 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
2933 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
2934 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
2935 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
2936 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
2937 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
2938 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
2939 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
2940 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
2941 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
2942 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
2943 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
2944 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
2945 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
2946 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
2947 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
2948 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
2949 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
2950 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
2951 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
2952 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
2953 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
2954 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
2955 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
2956 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
2957 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
2958 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
2959
2960 /****************** Bits definition for GPIO_IDR register *******************/
2961 #define GPIO_IDR_ID0_Pos (0U)
2962 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
2963 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
2964 #define GPIO_IDR_ID1_Pos (1U)
2965 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
2966 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
2967 #define GPIO_IDR_ID2_Pos (2U)
2968 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
2969 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
2970 #define GPIO_IDR_ID3_Pos (3U)
2971 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
2972 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
2973 #define GPIO_IDR_ID4_Pos (4U)
2974 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
2975 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
2976 #define GPIO_IDR_ID5_Pos (5U)
2977 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
2978 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
2979 #define GPIO_IDR_ID6_Pos (6U)
2980 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
2981 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
2982 #define GPIO_IDR_ID7_Pos (7U)
2983 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
2984 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
2985 #define GPIO_IDR_ID8_Pos (8U)
2986 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
2987 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
2988 #define GPIO_IDR_ID9_Pos (9U)
2989 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
2990 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
2991 #define GPIO_IDR_ID10_Pos (10U)
2992 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
2993 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
2994 #define GPIO_IDR_ID11_Pos (11U)
2995 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
2996 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
2997 #define GPIO_IDR_ID12_Pos (12U)
2998 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
2999 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
3000 #define GPIO_IDR_ID13_Pos (13U)
3001 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
3002 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
3003 #define GPIO_IDR_ID14_Pos (14U)
3004 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
3005 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
3006 #define GPIO_IDR_ID15_Pos (15U)
3007 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
3008 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
3009
3010 /* Legacy defines */
3011 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
3012 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
3013 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
3014 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
3015 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
3016 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
3017 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
3018 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
3019 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
3020 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
3021 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
3022 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
3023 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
3024 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
3025 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
3026 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
3027
3028 /****************** Bits definition for GPIO_ODR register *******************/
3029 #define GPIO_ODR_OD0_Pos (0U)
3030 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
3031 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
3032 #define GPIO_ODR_OD1_Pos (1U)
3033 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
3034 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
3035 #define GPIO_ODR_OD2_Pos (2U)
3036 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
3037 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
3038 #define GPIO_ODR_OD3_Pos (3U)
3039 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
3040 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
3041 #define GPIO_ODR_OD4_Pos (4U)
3042 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
3043 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
3044 #define GPIO_ODR_OD5_Pos (5U)
3045 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
3046 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
3047 #define GPIO_ODR_OD6_Pos (6U)
3048 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
3049 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
3050 #define GPIO_ODR_OD7_Pos (7U)
3051 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
3052 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
3053 #define GPIO_ODR_OD8_Pos (8U)
3054 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
3055 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
3056 #define GPIO_ODR_OD9_Pos (9U)
3057 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
3058 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
3059 #define GPIO_ODR_OD10_Pos (10U)
3060 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
3061 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
3062 #define GPIO_ODR_OD11_Pos (11U)
3063 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
3064 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
3065 #define GPIO_ODR_OD12_Pos (12U)
3066 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
3067 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
3068 #define GPIO_ODR_OD13_Pos (13U)
3069 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
3070 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
3071 #define GPIO_ODR_OD14_Pos (14U)
3072 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
3073 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
3074 #define GPIO_ODR_OD15_Pos (15U)
3075 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
3076 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
3077 /* Legacy defines */
3078 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
3079 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
3080 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
3081 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
3082 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
3083 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
3084 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
3085 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
3086 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
3087 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
3088 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
3089 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
3090 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
3091 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
3092 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
3093 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
3094
3095 /****************** Bits definition for GPIO_BSRR register ******************/
3096 #define GPIO_BSRR_BS0_Pos (0U)
3097 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
3098 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
3099 #define GPIO_BSRR_BS1_Pos (1U)
3100 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
3101 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
3102 #define GPIO_BSRR_BS2_Pos (2U)
3103 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
3104 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
3105 #define GPIO_BSRR_BS3_Pos (3U)
3106 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
3107 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
3108 #define GPIO_BSRR_BS4_Pos (4U)
3109 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
3110 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
3111 #define GPIO_BSRR_BS5_Pos (5U)
3112 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
3113 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
3114 #define GPIO_BSRR_BS6_Pos (6U)
3115 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
3116 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
3117 #define GPIO_BSRR_BS7_Pos (7U)
3118 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
3119 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
3120 #define GPIO_BSRR_BS8_Pos (8U)
3121 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
3122 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
3123 #define GPIO_BSRR_BS9_Pos (9U)
3124 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
3125 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
3126 #define GPIO_BSRR_BS10_Pos (10U)
3127 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
3128 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
3129 #define GPIO_BSRR_BS11_Pos (11U)
3130 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
3131 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
3132 #define GPIO_BSRR_BS12_Pos (12U)
3133 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
3134 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
3135 #define GPIO_BSRR_BS13_Pos (13U)
3136 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
3137 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
3138 #define GPIO_BSRR_BS14_Pos (14U)
3139 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
3140 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
3141 #define GPIO_BSRR_BS15_Pos (15U)
3142 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
3143 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
3144 #define GPIO_BSRR_BR0_Pos (16U)
3145 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
3146 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
3147 #define GPIO_BSRR_BR1_Pos (17U)
3148 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
3149 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
3150 #define GPIO_BSRR_BR2_Pos (18U)
3151 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
3152 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
3153 #define GPIO_BSRR_BR3_Pos (19U)
3154 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
3155 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
3156 #define GPIO_BSRR_BR4_Pos (20U)
3157 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
3158 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
3159 #define GPIO_BSRR_BR5_Pos (21U)
3160 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
3161 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
3162 #define GPIO_BSRR_BR6_Pos (22U)
3163 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
3164 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
3165 #define GPIO_BSRR_BR7_Pos (23U)
3166 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
3167 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
3168 #define GPIO_BSRR_BR8_Pos (24U)
3169 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
3170 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
3171 #define GPIO_BSRR_BR9_Pos (25U)
3172 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
3173 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
3174 #define GPIO_BSRR_BR10_Pos (26U)
3175 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
3176 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
3177 #define GPIO_BSRR_BR11_Pos (27U)
3178 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
3179 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
3180 #define GPIO_BSRR_BR12_Pos (28U)
3181 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
3182 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
3183 #define GPIO_BSRR_BR13_Pos (29U)
3184 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
3185 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
3186 #define GPIO_BSRR_BR14_Pos (30U)
3187 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
3188 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
3189 #define GPIO_BSRR_BR15_Pos (31U)
3190 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
3191 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
3192
3193 /* Legacy defines */
3194 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
3195 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
3196 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
3197 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
3198 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
3199 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
3200 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
3201 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
3202 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
3203 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
3204 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
3205 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
3206 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
3207 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
3208 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
3209 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
3210 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
3211 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
3212 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
3213 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
3214 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
3215 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
3216 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
3217 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
3218 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
3219 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
3220 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
3221 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
3222 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
3223 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
3224 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
3225 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
3226 /****************** Bit definition for GPIO_LCKR register *********************/
3227 #define GPIO_LCKR_LCK0_Pos (0U)
3228 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
3229 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
3230 #define GPIO_LCKR_LCK1_Pos (1U)
3231 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
3232 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
3233 #define GPIO_LCKR_LCK2_Pos (2U)
3234 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
3235 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
3236 #define GPIO_LCKR_LCK3_Pos (3U)
3237 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
3238 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
3239 #define GPIO_LCKR_LCK4_Pos (4U)
3240 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
3241 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
3242 #define GPIO_LCKR_LCK5_Pos (5U)
3243 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
3244 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
3245 #define GPIO_LCKR_LCK6_Pos (6U)
3246 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
3247 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
3248 #define GPIO_LCKR_LCK7_Pos (7U)
3249 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
3250 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
3251 #define GPIO_LCKR_LCK8_Pos (8U)
3252 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
3253 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
3254 #define GPIO_LCKR_LCK9_Pos (9U)
3255 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
3256 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
3257 #define GPIO_LCKR_LCK10_Pos (10U)
3258 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
3259 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
3260 #define GPIO_LCKR_LCK11_Pos (11U)
3261 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
3262 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
3263 #define GPIO_LCKR_LCK12_Pos (12U)
3264 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
3265 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
3266 #define GPIO_LCKR_LCK13_Pos (13U)
3267 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
3268 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
3269 #define GPIO_LCKR_LCK14_Pos (14U)
3270 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
3271 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
3272 #define GPIO_LCKR_LCK15_Pos (15U)
3273 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
3274 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
3275 #define GPIO_LCKR_LCKK_Pos (16U)
3276 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
3277 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
3278 /****************** Bit definition for GPIO_AFRL register *********************/
3279 #define GPIO_AFRL_AFSEL0_Pos (0U)
3280 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
3281 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
3282 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
3283 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
3284 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
3285 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
3286 #define GPIO_AFRL_AFSEL1_Pos (4U)
3287 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
3288 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
3289 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
3290 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
3291 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
3292 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
3293 #define GPIO_AFRL_AFSEL2_Pos (8U)
3294 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
3295 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
3296 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
3297 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
3298 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
3299 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
3300 #define GPIO_AFRL_AFSEL3_Pos (12U)
3301 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
3302 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
3303 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
3304 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
3305 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
3306 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
3307 #define GPIO_AFRL_AFSEL4_Pos (16U)
3308 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
3309 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
3310 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
3311 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
3312 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
3313 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
3314 #define GPIO_AFRL_AFSEL5_Pos (20U)
3315 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
3316 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
3317 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
3318 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
3319 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
3320 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
3321 #define GPIO_AFRL_AFSEL6_Pos (24U)
3322 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
3323 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
3324 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
3325 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
3326 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
3327 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
3328 #define GPIO_AFRL_AFSEL7_Pos (28U)
3329 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
3330 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
3331 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
3332 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
3333 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
3334 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
3335
3336 /* Legacy defines */
3337 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
3338 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
3339 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
3340 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
3341 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
3342 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
3343 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
3344 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
3345 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
3346 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
3347 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
3348 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
3349 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
3350 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
3351 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
3352 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
3353 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
3354 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
3355 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
3356 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
3357 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
3358 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
3359 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
3360 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
3361 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
3362 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
3363 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
3364 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
3365 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
3366 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
3367 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
3368 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
3369 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
3370 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
3371 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
3372 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
3373 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
3374 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
3375 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
3376 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
3377
3378 /****************** Bit definition for GPIO_AFRH register *********************/
3379 #define GPIO_AFRH_AFSEL8_Pos (0U)
3380 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
3381 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
3382 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
3383 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
3384 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
3385 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
3386 #define GPIO_AFRH_AFSEL9_Pos (4U)
3387 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
3388 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
3389 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
3390 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
3391 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
3392 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
3393 #define GPIO_AFRH_AFSEL10_Pos (8U)
3394 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
3395 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
3396 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
3397 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
3398 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
3399 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
3400 #define GPIO_AFRH_AFSEL11_Pos (12U)
3401 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
3402 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
3403 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
3404 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
3405 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
3406 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
3407 #define GPIO_AFRH_AFSEL12_Pos (16U)
3408 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
3409 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
3410 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
3411 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
3412 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
3413 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
3414 #define GPIO_AFRH_AFSEL13_Pos (20U)
3415 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
3416 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
3417 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
3418 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
3419 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
3420 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
3421 #define GPIO_AFRH_AFSEL14_Pos (24U)
3422 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
3423 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
3424 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
3425 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
3426 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
3427 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
3428 #define GPIO_AFRH_AFSEL15_Pos (28U)
3429 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
3430 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
3431 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
3432 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
3433 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
3434 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
3435
3436 /* Legacy defines */
3437 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
3438 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
3439 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
3440 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
3441 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
3442 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
3443 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
3444 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
3445 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
3446 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
3447 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
3448 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
3449 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
3450 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
3451 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
3452 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
3453 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
3454 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
3455 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
3456 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
3457 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
3458 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
3459 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
3460 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
3461 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
3462 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
3463 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
3464 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
3465 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
3466 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
3467 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
3468 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
3469 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
3470 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
3471 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
3472 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
3473 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
3474 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
3475 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
3476 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
3477
3478 /****************** Bits definition for GPIO_BRR register ******************/
3479 #define GPIO_BRR_BR0_Pos (0U)
3480 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
3481 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
3482 #define GPIO_BRR_BR1_Pos (1U)
3483 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
3484 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
3485 #define GPIO_BRR_BR2_Pos (2U)
3486 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
3487 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
3488 #define GPIO_BRR_BR3_Pos (3U)
3489 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
3490 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
3491 #define GPIO_BRR_BR4_Pos (4U)
3492 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
3493 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
3494 #define GPIO_BRR_BR5_Pos (5U)
3495 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
3496 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
3497 #define GPIO_BRR_BR6_Pos (6U)
3498 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
3499 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
3500 #define GPIO_BRR_BR7_Pos (7U)
3501 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
3502 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
3503 #define GPIO_BRR_BR8_Pos (8U)
3504 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
3505 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
3506 #define GPIO_BRR_BR9_Pos (9U)
3507 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
3508 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
3509 #define GPIO_BRR_BR10_Pos (10U)
3510 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
3511 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
3512 #define GPIO_BRR_BR11_Pos (11U)
3513 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
3514 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
3515 #define GPIO_BRR_BR12_Pos (12U)
3516 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
3517 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
3518 #define GPIO_BRR_BR13_Pos (13U)
3519 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
3520 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
3521 #define GPIO_BRR_BR14_Pos (14U)
3522 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
3523 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
3524 #define GPIO_BRR_BR15_Pos (15U)
3525 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
3526 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
3527
3528
3529 /******************************************************************************/
3530 /* */
3531 /* Inter-integrated Circuit Interface */
3532 /* */
3533 /******************************************************************************/
3534 /******************* Bit definition for I2C_CR1 register ********************/
3535 #define I2C_CR1_PE_Pos (0U)
3536 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
3537 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
3538 #define I2C_CR1_SMBUS_Pos (1U)
3539 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
3540 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
3541 #define I2C_CR1_SMBTYPE_Pos (3U)
3542 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
3543 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
3544 #define I2C_CR1_ENARP_Pos (4U)
3545 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
3546 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
3547 #define I2C_CR1_ENPEC_Pos (5U)
3548 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
3549 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
3550 #define I2C_CR1_ENGC_Pos (6U)
3551 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
3552 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
3553 #define I2C_CR1_NOSTRETCH_Pos (7U)
3554 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
3555 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
3556 #define I2C_CR1_START_Pos (8U)
3557 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
3558 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
3559 #define I2C_CR1_STOP_Pos (9U)
3560 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
3561 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
3562 #define I2C_CR1_ACK_Pos (10U)
3563 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
3564 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
3565 #define I2C_CR1_POS_Pos (11U)
3566 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
3567 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
3568 #define I2C_CR1_PEC_Pos (12U)
3569 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
3570 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
3571 #define I2C_CR1_ALERT_Pos (13U)
3572 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
3573 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
3574 #define I2C_CR1_SWRST_Pos (15U)
3575 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
3576 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
3577
3578 /******************* Bit definition for I2C_CR2 register ********************/
3579 #define I2C_CR2_FREQ_Pos (0U)
3580 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
3581 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
3582 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
3583 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
3584 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
3585 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
3586 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
3587 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
3588
3589 #define I2C_CR2_ITERREN_Pos (8U)
3590 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
3591 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
3592 #define I2C_CR2_ITEVTEN_Pos (9U)
3593 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
3594 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
3595 #define I2C_CR2_ITBUFEN_Pos (10U)
3596 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
3597 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
3598 #define I2C_CR2_DMAEN_Pos (11U)
3599 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
3600 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
3601 #define I2C_CR2_LAST_Pos (12U)
3602 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
3603 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
3604
3605 /******************* Bit definition for I2C_OAR1 register *******************/
3606 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
3607 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
3608
3609 #define I2C_OAR1_ADD0_Pos (0U)
3610 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
3611 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
3612 #define I2C_OAR1_ADD1_Pos (1U)
3613 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
3614 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
3615 #define I2C_OAR1_ADD2_Pos (2U)
3616 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
3617 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
3618 #define I2C_OAR1_ADD3_Pos (3U)
3619 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
3620 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
3621 #define I2C_OAR1_ADD4_Pos (4U)
3622 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
3623 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
3624 #define I2C_OAR1_ADD5_Pos (5U)
3625 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
3626 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
3627 #define I2C_OAR1_ADD6_Pos (6U)
3628 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
3629 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
3630 #define I2C_OAR1_ADD7_Pos (7U)
3631 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
3632 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
3633 #define I2C_OAR1_ADD8_Pos (8U)
3634 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
3635 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
3636 #define I2C_OAR1_ADD9_Pos (9U)
3637 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
3638 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
3639
3640 #define I2C_OAR1_ADDMODE_Pos (15U)
3641 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
3642 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
3643
3644 /******************* Bit definition for I2C_OAR2 register *******************/
3645 #define I2C_OAR2_ENDUAL_Pos (0U)
3646 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
3647 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
3648 #define I2C_OAR2_ADD2_Pos (1U)
3649 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
3650 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
3651
3652 /******************** Bit definition for I2C_DR register ********************/
3653 #define I2C_DR_DR_Pos (0U)
3654 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
3655 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
3656
3657 /******************* Bit definition for I2C_SR1 register ********************/
3658 #define I2C_SR1_SB_Pos (0U)
3659 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
3660 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
3661 #define I2C_SR1_ADDR_Pos (1U)
3662 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
3663 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
3664 #define I2C_SR1_BTF_Pos (2U)
3665 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
3666 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
3667 #define I2C_SR1_ADD10_Pos (3U)
3668 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
3669 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
3670 #define I2C_SR1_STOPF_Pos (4U)
3671 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
3672 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
3673 #define I2C_SR1_RXNE_Pos (6U)
3674 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
3675 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
3676 #define I2C_SR1_TXE_Pos (7U)
3677 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
3678 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
3679 #define I2C_SR1_BERR_Pos (8U)
3680 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
3681 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
3682 #define I2C_SR1_ARLO_Pos (9U)
3683 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
3684 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
3685 #define I2C_SR1_AF_Pos (10U)
3686 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
3687 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
3688 #define I2C_SR1_OVR_Pos (11U)
3689 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
3690 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
3691 #define I2C_SR1_PECERR_Pos (12U)
3692 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
3693 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
3694 #define I2C_SR1_TIMEOUT_Pos (14U)
3695 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
3696 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
3697 #define I2C_SR1_SMBALERT_Pos (15U)
3698 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
3699 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
3700
3701 /******************* Bit definition for I2C_SR2 register ********************/
3702 #define I2C_SR2_MSL_Pos (0U)
3703 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
3704 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
3705 #define I2C_SR2_BUSY_Pos (1U)
3706 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
3707 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
3708 #define I2C_SR2_TRA_Pos (2U)
3709 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
3710 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
3711 #define I2C_SR2_GENCALL_Pos (4U)
3712 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
3713 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
3714 #define I2C_SR2_SMBDEFAULT_Pos (5U)
3715 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
3716 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
3717 #define I2C_SR2_SMBHOST_Pos (6U)
3718 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
3719 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
3720 #define I2C_SR2_DUALF_Pos (7U)
3721 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
3722 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
3723 #define I2C_SR2_PEC_Pos (8U)
3724 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
3725 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
3726
3727 /******************* Bit definition for I2C_CCR register ********************/
3728 #define I2C_CCR_CCR_Pos (0U)
3729 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
3730 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
3731 #define I2C_CCR_DUTY_Pos (14U)
3732 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
3733 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
3734 #define I2C_CCR_FS_Pos (15U)
3735 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
3736 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
3737
3738 /****************** Bit definition for I2C_TRISE register *******************/
3739 #define I2C_TRISE_TRISE_Pos (0U)
3740 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
3741 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
3742
3743 /****************** Bit definition for I2C_FLTR register *******************/
3744 #define I2C_FLTR_DNF_Pos (0U)
3745 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
3746 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
3747 #define I2C_FLTR_ANOFF_Pos (4U)
3748 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
3749 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
3750
3751 /******************************************************************************/
3752 /* */
3753 /* Independent WATCHDOG */
3754 /* */
3755 /******************************************************************************/
3756 /******************* Bit definition for IWDG_KR register ********************/
3757 #define IWDG_KR_KEY_Pos (0U)
3758 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
3759 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
3760
3761 /******************* Bit definition for IWDG_PR register ********************/
3762 #define IWDG_PR_PR_Pos (0U)
3763 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
3764 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
3765 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
3766 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
3767 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
3768
3769 /******************* Bit definition for IWDG_RLR register *******************/
3770 #define IWDG_RLR_RL_Pos (0U)
3771 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
3772 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
3773
3774 /******************* Bit definition for IWDG_SR register ********************/
3775 #define IWDG_SR_PVU_Pos (0U)
3776 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
3777 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
3778 #define IWDG_SR_RVU_Pos (1U)
3779 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
3780 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
3781
3782
3783
3784 /******************************************************************************/
3785 /* */
3786 /* Power Control */
3787 /* */
3788 /******************************************************************************/
3789 /******************** Bit definition for PWR_CR register ********************/
3790 #define PWR_CR_LPDS_Pos (0U)
3791 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
3792 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
3793 #define PWR_CR_PDDS_Pos (1U)
3794 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
3795 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
3796 #define PWR_CR_CWUF_Pos (2U)
3797 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
3798 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
3799 #define PWR_CR_CSBF_Pos (3U)
3800 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
3801 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
3802 #define PWR_CR_PVDE_Pos (4U)
3803 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
3804 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
3805
3806 #define PWR_CR_PLS_Pos (5U)
3807 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
3808 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
3809 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
3810 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
3811 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
3812
3813 /*!< PVD level configuration */
3814 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
3815 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
3816 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
3817 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
3818 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
3819 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
3820 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
3821 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
3822 #define PWR_CR_DBP_Pos (8U)
3823 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
3824 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
3825 #define PWR_CR_FPDS_Pos (9U)
3826 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
3827 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
3828 #define PWR_CR_LPLVDS_Pos (10U)
3829 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
3830 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
3831 #define PWR_CR_MRLVDS_Pos (11U)
3832 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
3833 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
3834 #define PWR_CR_ADCDC1_Pos (13U)
3835 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
3836 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
3837 #define PWR_CR_VOS_Pos (14U)
3838 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
3839 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
3840 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
3841 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
3842
3843 /* Legacy define */
3844 #define PWR_CR_PMODE PWR_CR_VOS
3845
3846 /******************* Bit definition for PWR_CSR register ********************/
3847 #define PWR_CSR_WUF_Pos (0U)
3848 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
3849 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
3850 #define PWR_CSR_SBF_Pos (1U)
3851 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
3852 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
3853 #define PWR_CSR_PVDO_Pos (2U)
3854 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
3855 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
3856 #define PWR_CSR_BRR_Pos (3U)
3857 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
3858 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
3859 #define PWR_CSR_EWUP_Pos (8U)
3860 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
3861 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
3862 #define PWR_CSR_BRE_Pos (9U)
3863 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
3864 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
3865 #define PWR_CSR_VOSRDY_Pos (14U)
3866 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
3867 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
3868
3869 /* Legacy define */
3870 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
3871
3872 /******************************************************************************/
3873 /* */
3874 /* Reset and Clock Control */
3875 /* */
3876 /******************************************************************************/
3877 /******************** Bit definition for RCC_CR register ********************/
3878 #define RCC_CR_HSION_Pos (0U)
3879 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
3880 #define RCC_CR_HSION RCC_CR_HSION_Msk
3881 #define RCC_CR_HSIRDY_Pos (1U)
3882 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
3883 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
3884
3885 #define RCC_CR_HSITRIM_Pos (3U)
3886 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
3887 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
3888 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
3889 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
3890 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
3891 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
3892 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
3893
3894 #define RCC_CR_HSICAL_Pos (8U)
3895 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
3896 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
3897 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
3898 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
3899 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
3900 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
3901 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
3902 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
3903 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
3904 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
3905
3906 #define RCC_CR_HSEON_Pos (16U)
3907 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
3908 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
3909 #define RCC_CR_HSERDY_Pos (17U)
3910 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
3911 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
3912 #define RCC_CR_HSEBYP_Pos (18U)
3913 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
3914 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
3915 #define RCC_CR_CSSON_Pos (19U)
3916 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
3917 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
3918 #define RCC_CR_PLLON_Pos (24U)
3919 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
3920 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
3921 #define RCC_CR_PLLRDY_Pos (25U)
3922 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
3923 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
3924 /*
3925 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
3926 */
3927 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
3928
3929 #define RCC_CR_PLLI2SON_Pos (26U)
3930 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
3931 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
3932 #define RCC_CR_PLLI2SRDY_Pos (27U)
3933 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
3934 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
3935
3936 /******************** Bit definition for RCC_PLLCFGR register ***************/
3937 #define RCC_PLLCFGR_PLLM_Pos (0U)
3938 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
3939 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
3940 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
3941 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
3942 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
3943 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
3944 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
3945 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
3946
3947 #define RCC_PLLCFGR_PLLN_Pos (6U)
3948 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
3949 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
3950 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
3951 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
3952 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
3953 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
3954 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
3955 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
3956 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
3957 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
3958 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
3959
3960 #define RCC_PLLCFGR_PLLP_Pos (16U)
3961 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
3962 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
3963 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
3964 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
3965
3966 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
3967 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
3968 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
3969 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
3970 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
3971 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
3972 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
3973
3974 #define RCC_PLLCFGR_PLLQ_Pos (24U)
3975 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
3976 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
3977 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
3978 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
3979 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
3980 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
3981
3982
3983 /******************** Bit definition for RCC_CFGR register ******************/
3984 /*!< SW configuration */
3985 #define RCC_CFGR_SW_Pos (0U)
3986 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
3987 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
3988 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
3989 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
3990
3991 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
3992 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
3993 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
3994
3995 /*!< SWS configuration */
3996 #define RCC_CFGR_SWS_Pos (2U)
3997 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
3998 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
3999 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
4000 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
4001
4002 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
4003 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
4004 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
4005
4006 /*!< HPRE configuration */
4007 #define RCC_CFGR_HPRE_Pos (4U)
4008 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
4009 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
4010 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
4011 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
4012 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
4013 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
4014
4015 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
4016 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
4017 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
4018 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
4019 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
4020 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
4021 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
4022 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
4023 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
4024
4025 /*!< PPRE1 configuration */
4026 #define RCC_CFGR_PPRE1_Pos (10U)
4027 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
4028 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
4029 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
4030 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
4031 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
4032
4033 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
4034 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
4035 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
4036 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
4037 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
4038
4039 /*!< PPRE2 configuration */
4040 #define RCC_CFGR_PPRE2_Pos (13U)
4041 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
4042 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
4043 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
4044 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
4045 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
4046
4047 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
4048 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
4049 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
4050 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
4051 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
4052
4053 /*!< RTCPRE configuration */
4054 #define RCC_CFGR_RTCPRE_Pos (16U)
4055 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
4056 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
4057 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
4058 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
4059 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
4060 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
4061 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
4062
4063 /*!< MCO1 configuration */
4064 #define RCC_CFGR_MCO1_Pos (21U)
4065 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
4066 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
4067 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
4068 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
4069
4070 #define RCC_CFGR_I2SSRC_Pos (23U)
4071 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
4072 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
4073
4074 #define RCC_CFGR_MCO1PRE_Pos (24U)
4075 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
4076 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
4077 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
4078 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
4079 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
4080
4081 #define RCC_CFGR_MCO2PRE_Pos (27U)
4082 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
4083 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
4084 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
4085 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
4086 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
4087
4088 #define RCC_CFGR_MCO2_Pos (30U)
4089 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
4090 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
4091 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
4092 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
4093
4094 /******************** Bit definition for RCC_CIR register *******************/
4095 #define RCC_CIR_LSIRDYF_Pos (0U)
4096 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
4097 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
4098 #define RCC_CIR_LSERDYF_Pos (1U)
4099 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
4100 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
4101 #define RCC_CIR_HSIRDYF_Pos (2U)
4102 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
4103 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
4104 #define RCC_CIR_HSERDYF_Pos (3U)
4105 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
4106 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
4107 #define RCC_CIR_PLLRDYF_Pos (4U)
4108 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
4109 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
4110 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
4111 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
4112 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
4113
4114 #define RCC_CIR_CSSF_Pos (7U)
4115 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
4116 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
4117 #define RCC_CIR_LSIRDYIE_Pos (8U)
4118 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
4119 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
4120 #define RCC_CIR_LSERDYIE_Pos (9U)
4121 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
4122 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
4123 #define RCC_CIR_HSIRDYIE_Pos (10U)
4124 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
4125 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
4126 #define RCC_CIR_HSERDYIE_Pos (11U)
4127 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
4128 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
4129 #define RCC_CIR_PLLRDYIE_Pos (12U)
4130 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
4131 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
4132 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
4133 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
4134 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
4135
4136 #define RCC_CIR_LSIRDYC_Pos (16U)
4137 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
4138 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
4139 #define RCC_CIR_LSERDYC_Pos (17U)
4140 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
4141 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
4142 #define RCC_CIR_HSIRDYC_Pos (18U)
4143 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
4144 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
4145 #define RCC_CIR_HSERDYC_Pos (19U)
4146 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
4147 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
4148 #define RCC_CIR_PLLRDYC_Pos (20U)
4149 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
4150 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
4151 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
4152 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
4153 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
4154
4155 #define RCC_CIR_CSSC_Pos (23U)
4156 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
4157 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
4158
4159 /******************** Bit definition for RCC_AHB1RSTR register **************/
4160 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
4161 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
4162 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
4163 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
4164 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
4165 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
4166 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
4167 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
4168 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
4169 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
4170 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
4171 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
4172 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
4173 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
4174 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
4175 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
4176 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
4177 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
4178 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
4179 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
4180 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
4181 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
4182 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
4183 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
4184 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
4185 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
4186 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
4187
4188 /******************** Bit definition for RCC_AHB2RSTR register **************/
4189 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
4190 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
4191 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
4192 /******************** Bit definition for RCC_AHB3RSTR register **************/
4193
4194
4195 /******************** Bit definition for RCC_APB1RSTR register **************/
4196 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
4197 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
4198 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
4199 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
4200 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
4201 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
4202 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
4203 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
4204 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
4205 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
4206 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
4207 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
4208 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
4209 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
4210 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
4211 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
4212 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
4213 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
4214 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
4215 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
4216 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
4217 #define RCC_APB1RSTR_USART2RST_Pos (17U)
4218 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
4219 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
4220 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
4221 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
4222 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
4223 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
4224 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
4225 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
4226 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
4227 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
4228 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
4229 #define RCC_APB1RSTR_PWRRST_Pos (28U)
4230 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
4231 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
4232
4233 /******************** Bit definition for RCC_APB2RSTR register **************/
4234 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
4235 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
4236 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
4237 #define RCC_APB2RSTR_USART1RST_Pos (4U)
4238 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
4239 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
4240 #define RCC_APB2RSTR_USART6RST_Pos (5U)
4241 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
4242 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
4243 #define RCC_APB2RSTR_ADCRST_Pos (8U)
4244 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
4245 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
4246 #define RCC_APB2RSTR_SDIORST_Pos (11U)
4247 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
4248 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
4249 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
4250 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
4251 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
4252 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
4253 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
4254 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
4255 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
4256 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
4257 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
4258 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
4259 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
4260 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
4261 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
4262 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
4263 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
4264 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
4265 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
4266 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
4267
4268 /* Old SPI1RST bit definition, maintained for legacy purpose */
4269 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
4270
4271 /******************** Bit definition for RCC_AHB1ENR register ***************/
4272 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
4273 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
4274 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
4275 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
4276 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
4277 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
4278 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
4279 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
4280 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
4281 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
4282 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
4283 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
4284 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
4285 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
4286 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
4287 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
4288 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
4289 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
4290 #define RCC_AHB1ENR_CRCEN_Pos (12U)
4291 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
4292 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
4293 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
4294 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
4295 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
4296 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
4297 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
4298 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
4299 /******************** Bit definition for RCC_AHB2ENR register ***************/
4300 /*
4301 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
4302 */
4303 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
4304
4305 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
4306 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
4307 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
4308
4309 /******************** Bit definition for RCC_APB1ENR register ***************/
4310 #define RCC_APB1ENR_TIM2EN_Pos (0U)
4311 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
4312 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
4313 #define RCC_APB1ENR_TIM3EN_Pos (1U)
4314 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
4315 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
4316 #define RCC_APB1ENR_TIM4EN_Pos (2U)
4317 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
4318 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
4319 #define RCC_APB1ENR_TIM5EN_Pos (3U)
4320 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
4321 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
4322 #define RCC_APB1ENR_WWDGEN_Pos (11U)
4323 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
4324 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
4325 #define RCC_APB1ENR_SPI2EN_Pos (14U)
4326 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
4327 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
4328 #define RCC_APB1ENR_SPI3EN_Pos (15U)
4329 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
4330 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
4331 #define RCC_APB1ENR_USART2EN_Pos (17U)
4332 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
4333 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
4334 #define RCC_APB1ENR_I2C1EN_Pos (21U)
4335 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
4336 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
4337 #define RCC_APB1ENR_I2C2EN_Pos (22U)
4338 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
4339 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
4340 #define RCC_APB1ENR_I2C3EN_Pos (23U)
4341 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
4342 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
4343 #define RCC_APB1ENR_PWREN_Pos (28U)
4344 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
4345 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
4346
4347 /******************** Bit definition for RCC_APB2ENR register ***************/
4348 #define RCC_APB2ENR_TIM1EN_Pos (0U)
4349 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
4350 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
4351 #define RCC_APB2ENR_USART1EN_Pos (4U)
4352 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
4353 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
4354 #define RCC_APB2ENR_USART6EN_Pos (5U)
4355 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
4356 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
4357 #define RCC_APB2ENR_ADC1EN_Pos (8U)
4358 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
4359 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
4360 #define RCC_APB2ENR_SDIOEN_Pos (11U)
4361 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
4362 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
4363 #define RCC_APB2ENR_SPI1EN_Pos (12U)
4364 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
4365 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
4366 #define RCC_APB2ENR_SPI4EN_Pos (13U)
4367 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
4368 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
4369 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
4370 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
4371 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
4372 #define RCC_APB2ENR_TIM9EN_Pos (16U)
4373 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
4374 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
4375 #define RCC_APB2ENR_TIM10EN_Pos (17U)
4376 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
4377 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
4378 #define RCC_APB2ENR_TIM11EN_Pos (18U)
4379 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
4380 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
4381
4382 /******************** Bit definition for RCC_AHB1LPENR register *************/
4383 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
4384 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
4385 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
4386 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
4387 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
4388 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
4389 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
4390 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
4391 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
4392 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
4393 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
4394 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
4395 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
4396 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
4397 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
4398 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
4399 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
4400 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
4401 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
4402 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
4403 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
4404 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
4405 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
4406 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
4407 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
4408 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
4409 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
4410 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
4411 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
4412 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
4413 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
4414 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
4415 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
4416
4417
4418 /******************** Bit definition for RCC_AHB2LPENR register *************/
4419 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
4420 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
4421 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
4422
4423 /******************** Bit definition for RCC_AHB3LPENR register *************/
4424
4425 /******************** Bit definition for RCC_APB1LPENR register *************/
4426 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
4427 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
4428 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
4429 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
4430 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
4431 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
4432 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
4433 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
4434 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
4435 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
4436 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
4437 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
4438 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
4439 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
4440 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
4441 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
4442 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
4443 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
4444 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
4445 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
4446 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
4447 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
4448 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
4449 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
4450 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
4451 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
4452 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
4453 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
4454 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
4455 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
4456 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
4457 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
4458 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
4459 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
4460 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
4461 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
4462
4463 /******************** Bit definition for RCC_APB2LPENR register *************/
4464 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
4465 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
4466 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
4467 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
4468 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
4469 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
4470 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
4471 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
4472 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
4473 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
4474 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
4475 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
4476 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
4477 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
4478 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
4479 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
4480 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
4481 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
4482 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
4483 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
4484 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
4485 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
4486 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
4487 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
4488 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
4489 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
4490 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
4491 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
4492 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
4493 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
4494 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
4495 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
4496 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
4497
4498 /******************** Bit definition for RCC_BDCR register ******************/
4499 #define RCC_BDCR_LSEON_Pos (0U)
4500 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
4501 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
4502 #define RCC_BDCR_LSERDY_Pos (1U)
4503 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
4504 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
4505 #define RCC_BDCR_LSEBYP_Pos (2U)
4506 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
4507 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
4508
4509 #define RCC_BDCR_RTCSEL_Pos (8U)
4510 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
4511 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
4512 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
4513 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
4514
4515 #define RCC_BDCR_RTCEN_Pos (15U)
4516 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
4517 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
4518 #define RCC_BDCR_BDRST_Pos (16U)
4519 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
4520 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
4521
4522 /******************** Bit definition for RCC_CSR register *******************/
4523 #define RCC_CSR_LSION_Pos (0U)
4524 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
4525 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
4526 #define RCC_CSR_LSIRDY_Pos (1U)
4527 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
4528 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
4529 #define RCC_CSR_RMVF_Pos (24U)
4530 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
4531 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
4532 #define RCC_CSR_BORRSTF_Pos (25U)
4533 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
4534 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
4535 #define RCC_CSR_PINRSTF_Pos (26U)
4536 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
4537 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
4538 #define RCC_CSR_PORRSTF_Pos (27U)
4539 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
4540 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
4541 #define RCC_CSR_SFTRSTF_Pos (28U)
4542 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
4543 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
4544 #define RCC_CSR_IWDGRSTF_Pos (29U)
4545 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
4546 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
4547 #define RCC_CSR_WWDGRSTF_Pos (30U)
4548 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
4549 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
4550 #define RCC_CSR_LPWRRSTF_Pos (31U)
4551 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
4552 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
4553 /* Legacy defines */
4554 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
4555 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
4556
4557 /******************** Bit definition for RCC_SSCGR register *****************/
4558 #define RCC_SSCGR_MODPER_Pos (0U)
4559 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
4560 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
4561 #define RCC_SSCGR_INCSTEP_Pos (13U)
4562 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
4563 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
4564 #define RCC_SSCGR_SPREADSEL_Pos (30U)
4565 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
4566 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
4567 #define RCC_SSCGR_SSCGEN_Pos (31U)
4568 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
4569 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
4570
4571 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
4572 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
4573 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
4574 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
4575 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
4576 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
4577 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
4578 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
4579 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
4580 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
4581 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
4582 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
4583 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
4584
4585 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
4586 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
4587 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
4588 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
4589 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
4590 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
4591
4592 /******************** Bit definition for RCC_DCKCFGR register ***************/
4593
4594 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
4595 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
4596 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
4597
4598
4599 /******************************************************************************/
4600 /* */
4601 /* Real-Time Clock (RTC) */
4602 /* */
4603 /******************************************************************************/
4604 /******************** Bits definition for RTC_TR register *******************/
4605 #define RTC_TR_PM_Pos (22U)
4606 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
4607 #define RTC_TR_PM RTC_TR_PM_Msk
4608 #define RTC_TR_HT_Pos (20U)
4609 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
4610 #define RTC_TR_HT RTC_TR_HT_Msk
4611 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
4612 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
4613 #define RTC_TR_HU_Pos (16U)
4614 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
4615 #define RTC_TR_HU RTC_TR_HU_Msk
4616 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
4617 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
4618 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
4619 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
4620 #define RTC_TR_MNT_Pos (12U)
4621 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
4622 #define RTC_TR_MNT RTC_TR_MNT_Msk
4623 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
4624 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
4625 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
4626 #define RTC_TR_MNU_Pos (8U)
4627 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
4628 #define RTC_TR_MNU RTC_TR_MNU_Msk
4629 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
4630 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
4631 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
4632 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
4633 #define RTC_TR_ST_Pos (4U)
4634 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
4635 #define RTC_TR_ST RTC_TR_ST_Msk
4636 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
4637 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
4638 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
4639 #define RTC_TR_SU_Pos (0U)
4640 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
4641 #define RTC_TR_SU RTC_TR_SU_Msk
4642 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
4643 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
4644 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
4645 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
4646
4647 /******************** Bits definition for RTC_DR register *******************/
4648 #define RTC_DR_YT_Pos (20U)
4649 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
4650 #define RTC_DR_YT RTC_DR_YT_Msk
4651 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
4652 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
4653 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
4654 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
4655 #define RTC_DR_YU_Pos (16U)
4656 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
4657 #define RTC_DR_YU RTC_DR_YU_Msk
4658 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
4659 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
4660 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
4661 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
4662 #define RTC_DR_WDU_Pos (13U)
4663 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
4664 #define RTC_DR_WDU RTC_DR_WDU_Msk
4665 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
4666 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
4667 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
4668 #define RTC_DR_MT_Pos (12U)
4669 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
4670 #define RTC_DR_MT RTC_DR_MT_Msk
4671 #define RTC_DR_MU_Pos (8U)
4672 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
4673 #define RTC_DR_MU RTC_DR_MU_Msk
4674 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
4675 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
4676 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
4677 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
4678 #define RTC_DR_DT_Pos (4U)
4679 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
4680 #define RTC_DR_DT RTC_DR_DT_Msk
4681 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
4682 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
4683 #define RTC_DR_DU_Pos (0U)
4684 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
4685 #define RTC_DR_DU RTC_DR_DU_Msk
4686 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
4687 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
4688 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
4689 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
4690
4691 /******************** Bits definition for RTC_CR register *******************/
4692 #define RTC_CR_COE_Pos (23U)
4693 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
4694 #define RTC_CR_COE RTC_CR_COE_Msk
4695 #define RTC_CR_OSEL_Pos (21U)
4696 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
4697 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
4698 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
4699 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
4700 #define RTC_CR_POL_Pos (20U)
4701 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
4702 #define RTC_CR_POL RTC_CR_POL_Msk
4703 #define RTC_CR_COSEL_Pos (19U)
4704 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
4705 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
4706 #define RTC_CR_BKP_Pos (18U)
4707 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
4708 #define RTC_CR_BKP RTC_CR_BKP_Msk
4709 #define RTC_CR_SUB1H_Pos (17U)
4710 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
4711 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
4712 #define RTC_CR_ADD1H_Pos (16U)
4713 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
4714 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
4715 #define RTC_CR_TSIE_Pos (15U)
4716 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
4717 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
4718 #define RTC_CR_WUTIE_Pos (14U)
4719 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
4720 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
4721 #define RTC_CR_ALRBIE_Pos (13U)
4722 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
4723 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
4724 #define RTC_CR_ALRAIE_Pos (12U)
4725 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
4726 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
4727 #define RTC_CR_TSE_Pos (11U)
4728 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
4729 #define RTC_CR_TSE RTC_CR_TSE_Msk
4730 #define RTC_CR_WUTE_Pos (10U)
4731 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
4732 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
4733 #define RTC_CR_ALRBE_Pos (9U)
4734 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
4735 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
4736 #define RTC_CR_ALRAE_Pos (8U)
4737 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
4738 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
4739 #define RTC_CR_DCE_Pos (7U)
4740 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
4741 #define RTC_CR_DCE RTC_CR_DCE_Msk
4742 #define RTC_CR_FMT_Pos (6U)
4743 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
4744 #define RTC_CR_FMT RTC_CR_FMT_Msk
4745 #define RTC_CR_BYPSHAD_Pos (5U)
4746 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
4747 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
4748 #define RTC_CR_REFCKON_Pos (4U)
4749 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
4750 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
4751 #define RTC_CR_TSEDGE_Pos (3U)
4752 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
4753 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
4754 #define RTC_CR_WUCKSEL_Pos (0U)
4755 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
4756 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
4757 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
4758 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
4759 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
4760
4761 /* Legacy defines */
4762 #define RTC_CR_BCK RTC_CR_BKP
4763
4764 /******************** Bits definition for RTC_ISR register ******************/
4765 #define RTC_ISR_RECALPF_Pos (16U)
4766 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
4767 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
4768 #define RTC_ISR_TAMP1F_Pos (13U)
4769 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
4770 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
4771 #define RTC_ISR_TAMP2F_Pos (14U)
4772 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
4773 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
4774 #define RTC_ISR_TSOVF_Pos (12U)
4775 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
4776 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
4777 #define RTC_ISR_TSF_Pos (11U)
4778 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
4779 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
4780 #define RTC_ISR_WUTF_Pos (10U)
4781 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
4782 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
4783 #define RTC_ISR_ALRBF_Pos (9U)
4784 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
4785 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
4786 #define RTC_ISR_ALRAF_Pos (8U)
4787 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
4788 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
4789 #define RTC_ISR_INIT_Pos (7U)
4790 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
4791 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
4792 #define RTC_ISR_INITF_Pos (6U)
4793 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
4794 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
4795 #define RTC_ISR_RSF_Pos (5U)
4796 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
4797 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
4798 #define RTC_ISR_INITS_Pos (4U)
4799 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
4800 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
4801 #define RTC_ISR_SHPF_Pos (3U)
4802 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
4803 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
4804 #define RTC_ISR_WUTWF_Pos (2U)
4805 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
4806 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
4807 #define RTC_ISR_ALRBWF_Pos (1U)
4808 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
4809 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
4810 #define RTC_ISR_ALRAWF_Pos (0U)
4811 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
4812 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
4813
4814 /******************** Bits definition for RTC_PRER register *****************/
4815 #define RTC_PRER_PREDIV_A_Pos (16U)
4816 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
4817 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
4818 #define RTC_PRER_PREDIV_S_Pos (0U)
4819 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
4820 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
4821
4822 /******************** Bits definition for RTC_WUTR register *****************/
4823 #define RTC_WUTR_WUT_Pos (0U)
4824 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
4825 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
4826
4827 /******************** Bits definition for RTC_CALIBR register ***************/
4828 #define RTC_CALIBR_DCS_Pos (7U)
4829 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
4830 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
4831 #define RTC_CALIBR_DC_Pos (0U)
4832 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
4833 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
4834
4835 /******************** Bits definition for RTC_ALRMAR register ***************/
4836 #define RTC_ALRMAR_MSK4_Pos (31U)
4837 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
4838 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
4839 #define RTC_ALRMAR_WDSEL_Pos (30U)
4840 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
4841 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
4842 #define RTC_ALRMAR_DT_Pos (28U)
4843 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
4844 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
4845 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
4846 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
4847 #define RTC_ALRMAR_DU_Pos (24U)
4848 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
4849 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
4850 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
4851 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
4852 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
4853 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
4854 #define RTC_ALRMAR_MSK3_Pos (23U)
4855 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
4856 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
4857 #define RTC_ALRMAR_PM_Pos (22U)
4858 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
4859 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
4860 #define RTC_ALRMAR_HT_Pos (20U)
4861 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
4862 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
4863 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
4864 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
4865 #define RTC_ALRMAR_HU_Pos (16U)
4866 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
4867 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
4868 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
4869 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
4870 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
4871 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
4872 #define RTC_ALRMAR_MSK2_Pos (15U)
4873 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
4874 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
4875 #define RTC_ALRMAR_MNT_Pos (12U)
4876 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
4877 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
4878 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
4879 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
4880 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
4881 #define RTC_ALRMAR_MNU_Pos (8U)
4882 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
4883 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
4884 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
4885 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
4886 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
4887 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
4888 #define RTC_ALRMAR_MSK1_Pos (7U)
4889 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
4890 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
4891 #define RTC_ALRMAR_ST_Pos (4U)
4892 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
4893 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
4894 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
4895 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
4896 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
4897 #define RTC_ALRMAR_SU_Pos (0U)
4898 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
4899 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
4900 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
4901 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
4902 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
4903 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
4904
4905 /******************** Bits definition for RTC_ALRMBR register ***************/
4906 #define RTC_ALRMBR_MSK4_Pos (31U)
4907 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
4908 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
4909 #define RTC_ALRMBR_WDSEL_Pos (30U)
4910 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
4911 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
4912 #define RTC_ALRMBR_DT_Pos (28U)
4913 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
4914 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
4915 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
4916 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
4917 #define RTC_ALRMBR_DU_Pos (24U)
4918 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
4919 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
4920 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
4921 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
4922 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
4923 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
4924 #define RTC_ALRMBR_MSK3_Pos (23U)
4925 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
4926 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
4927 #define RTC_ALRMBR_PM_Pos (22U)
4928 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
4929 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
4930 #define RTC_ALRMBR_HT_Pos (20U)
4931 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
4932 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
4933 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
4934 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
4935 #define RTC_ALRMBR_HU_Pos (16U)
4936 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
4937 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
4938 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
4939 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
4940 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
4941 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
4942 #define RTC_ALRMBR_MSK2_Pos (15U)
4943 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
4944 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
4945 #define RTC_ALRMBR_MNT_Pos (12U)
4946 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
4947 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
4948 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
4949 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
4950 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
4951 #define RTC_ALRMBR_MNU_Pos (8U)
4952 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
4953 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
4954 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
4955 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
4956 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
4957 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
4958 #define RTC_ALRMBR_MSK1_Pos (7U)
4959 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
4960 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
4961 #define RTC_ALRMBR_ST_Pos (4U)
4962 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
4963 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
4964 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
4965 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
4966 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
4967 #define RTC_ALRMBR_SU_Pos (0U)
4968 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
4969 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
4970 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
4971 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
4972 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
4973 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
4974
4975 /******************** Bits definition for RTC_WPR register ******************/
4976 #define RTC_WPR_KEY_Pos (0U)
4977 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
4978 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
4979
4980 /******************** Bits definition for RTC_SSR register ******************/
4981 #define RTC_SSR_SS_Pos (0U)
4982 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
4983 #define RTC_SSR_SS RTC_SSR_SS_Msk
4984
4985 /******************** Bits definition for RTC_SHIFTR register ***************/
4986 #define RTC_SHIFTR_SUBFS_Pos (0U)
4987 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
4988 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
4989 #define RTC_SHIFTR_ADD1S_Pos (31U)
4990 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
4991 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
4992
4993 /******************** Bits definition for RTC_TSTR register *****************/
4994 #define RTC_TSTR_PM_Pos (22U)
4995 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
4996 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
4997 #define RTC_TSTR_HT_Pos (20U)
4998 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
4999 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
5000 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
5001 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
5002 #define RTC_TSTR_HU_Pos (16U)
5003 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
5004 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
5005 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
5006 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
5007 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
5008 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
5009 #define RTC_TSTR_MNT_Pos (12U)
5010 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
5011 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
5012 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
5013 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
5014 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
5015 #define RTC_TSTR_MNU_Pos (8U)
5016 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
5017 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
5018 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
5019 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
5020 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
5021 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
5022 #define RTC_TSTR_ST_Pos (4U)
5023 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
5024 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
5025 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
5026 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
5027 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
5028 #define RTC_TSTR_SU_Pos (0U)
5029 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
5030 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
5031 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
5032 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
5033 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
5034 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
5035
5036 /******************** Bits definition for RTC_TSDR register *****************/
5037 #define RTC_TSDR_WDU_Pos (13U)
5038 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
5039 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
5040 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
5041 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
5042 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
5043 #define RTC_TSDR_MT_Pos (12U)
5044 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
5045 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
5046 #define RTC_TSDR_MU_Pos (8U)
5047 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
5048 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
5049 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
5050 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
5051 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
5052 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
5053 #define RTC_TSDR_DT_Pos (4U)
5054 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
5055 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
5056 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
5057 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
5058 #define RTC_TSDR_DU_Pos (0U)
5059 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
5060 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
5061 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
5062 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
5063 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
5064 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
5065
5066 /******************** Bits definition for RTC_TSSSR register ****************/
5067 #define RTC_TSSSR_SS_Pos (0U)
5068 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
5069 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
5070
5071 /******************** Bits definition for RTC_CAL register *****************/
5072 #define RTC_CALR_CALP_Pos (15U)
5073 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
5074 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
5075 #define RTC_CALR_CALW8_Pos (14U)
5076 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
5077 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
5078 #define RTC_CALR_CALW16_Pos (13U)
5079 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
5080 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
5081 #define RTC_CALR_CALM_Pos (0U)
5082 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
5083 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
5084 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
5085 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
5086 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
5087 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
5088 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
5089 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
5090 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
5091 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
5092 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
5093
5094 /******************** Bits definition for RTC_TAFCR register ****************/
5095 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
5096 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
5097 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
5098 #define RTC_TAFCR_TSINSEL_Pos (17U)
5099 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
5100 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
5101 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
5102 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
5103 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
5104 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
5105 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
5106 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
5107 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
5108 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
5109 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
5110 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
5111 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
5112 #define RTC_TAFCR_TAMPFLT_Pos (11U)
5113 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
5114 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
5115 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
5116 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
5117 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
5118 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
5119 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
5120 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
5121 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
5122 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
5123 #define RTC_TAFCR_TAMPTS_Pos (7U)
5124 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
5125 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
5126 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
5127 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
5128 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
5129 #define RTC_TAFCR_TAMP2E_Pos (3U)
5130 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
5131 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
5132 #define RTC_TAFCR_TAMPIE_Pos (2U)
5133 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
5134 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
5135 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
5136 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
5137 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
5138 #define RTC_TAFCR_TAMP1E_Pos (0U)
5139 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
5140 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
5141
5142 /* Legacy defines */
5143 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
5144
5145 /******************** Bits definition for RTC_ALRMASSR register *************/
5146 #define RTC_ALRMASSR_MASKSS_Pos (24U)
5147 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
5148 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
5149 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
5150 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
5151 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
5152 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
5153 #define RTC_ALRMASSR_SS_Pos (0U)
5154 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
5155 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
5156
5157 /******************** Bits definition for RTC_ALRMBSSR register *************/
5158 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
5159 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
5160 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
5161 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
5162 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
5163 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
5164 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
5165 #define RTC_ALRMBSSR_SS_Pos (0U)
5166 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
5167 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
5168
5169 /******************** Bits definition for RTC_BKP0R register ****************/
5170 #define RTC_BKP0R_Pos (0U)
5171 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
5172 #define RTC_BKP0R RTC_BKP0R_Msk
5173
5174 /******************** Bits definition for RTC_BKP1R register ****************/
5175 #define RTC_BKP1R_Pos (0U)
5176 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
5177 #define RTC_BKP1R RTC_BKP1R_Msk
5178
5179 /******************** Bits definition for RTC_BKP2R register ****************/
5180 #define RTC_BKP2R_Pos (0U)
5181 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
5182 #define RTC_BKP2R RTC_BKP2R_Msk
5183
5184 /******************** Bits definition for RTC_BKP3R register ****************/
5185 #define RTC_BKP3R_Pos (0U)
5186 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
5187 #define RTC_BKP3R RTC_BKP3R_Msk
5188
5189 /******************** Bits definition for RTC_BKP4R register ****************/
5190 #define RTC_BKP4R_Pos (0U)
5191 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
5192 #define RTC_BKP4R RTC_BKP4R_Msk
5193
5194 /******************** Bits definition for RTC_BKP5R register ****************/
5195 #define RTC_BKP5R_Pos (0U)
5196 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
5197 #define RTC_BKP5R RTC_BKP5R_Msk
5198
5199 /******************** Bits definition for RTC_BKP6R register ****************/
5200 #define RTC_BKP6R_Pos (0U)
5201 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
5202 #define RTC_BKP6R RTC_BKP6R_Msk
5203
5204 /******************** Bits definition for RTC_BKP7R register ****************/
5205 #define RTC_BKP7R_Pos (0U)
5206 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
5207 #define RTC_BKP7R RTC_BKP7R_Msk
5208
5209 /******************** Bits definition for RTC_BKP8R register ****************/
5210 #define RTC_BKP8R_Pos (0U)
5211 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
5212 #define RTC_BKP8R RTC_BKP8R_Msk
5213
5214 /******************** Bits definition for RTC_BKP9R register ****************/
5215 #define RTC_BKP9R_Pos (0U)
5216 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
5217 #define RTC_BKP9R RTC_BKP9R_Msk
5218
5219 /******************** Bits definition for RTC_BKP10R register ***************/
5220 #define RTC_BKP10R_Pos (0U)
5221 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
5222 #define RTC_BKP10R RTC_BKP10R_Msk
5223
5224 /******************** Bits definition for RTC_BKP11R register ***************/
5225 #define RTC_BKP11R_Pos (0U)
5226 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
5227 #define RTC_BKP11R RTC_BKP11R_Msk
5228
5229 /******************** Bits definition for RTC_BKP12R register ***************/
5230 #define RTC_BKP12R_Pos (0U)
5231 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
5232 #define RTC_BKP12R RTC_BKP12R_Msk
5233
5234 /******************** Bits definition for RTC_BKP13R register ***************/
5235 #define RTC_BKP13R_Pos (0U)
5236 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
5237 #define RTC_BKP13R RTC_BKP13R_Msk
5238
5239 /******************** Bits definition for RTC_BKP14R register ***************/
5240 #define RTC_BKP14R_Pos (0U)
5241 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
5242 #define RTC_BKP14R RTC_BKP14R_Msk
5243
5244 /******************** Bits definition for RTC_BKP15R register ***************/
5245 #define RTC_BKP15R_Pos (0U)
5246 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
5247 #define RTC_BKP15R RTC_BKP15R_Msk
5248
5249 /******************** Bits definition for RTC_BKP16R register ***************/
5250 #define RTC_BKP16R_Pos (0U)
5251 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
5252 #define RTC_BKP16R RTC_BKP16R_Msk
5253
5254 /******************** Bits definition for RTC_BKP17R register ***************/
5255 #define RTC_BKP17R_Pos (0U)
5256 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
5257 #define RTC_BKP17R RTC_BKP17R_Msk
5258
5259 /******************** Bits definition for RTC_BKP18R register ***************/
5260 #define RTC_BKP18R_Pos (0U)
5261 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
5262 #define RTC_BKP18R RTC_BKP18R_Msk
5263
5264 /******************** Bits definition for RTC_BKP19R register ***************/
5265 #define RTC_BKP19R_Pos (0U)
5266 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
5267 #define RTC_BKP19R RTC_BKP19R_Msk
5268
5269 /******************** Number of backup registers ******************************/
5270 #define RTC_BKP_NUMBER 0x000000014U
5271
5272
5273 /******************************************************************************/
5274 /* */
5275 /* SD host Interface */
5276 /* */
5277 /******************************************************************************/
5278 /****************** Bit definition for SDIO_POWER register ******************/
5279 #define SDIO_POWER_PWRCTRL_Pos (0U)
5280 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
5281 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
5282 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
5283 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
5284
5285 /****************** Bit definition for SDIO_CLKCR register ******************/
5286 #define SDIO_CLKCR_CLKDIV_Pos (0U)
5287 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
5288 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
5289 #define SDIO_CLKCR_CLKEN_Pos (8U)
5290 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
5291 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
5292 #define SDIO_CLKCR_PWRSAV_Pos (9U)
5293 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
5294 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
5295 #define SDIO_CLKCR_BYPASS_Pos (10U)
5296 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
5297 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
5298
5299 #define SDIO_CLKCR_WIDBUS_Pos (11U)
5300 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
5301 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
5302 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
5303 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
5304
5305 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
5306 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
5307 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
5308 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
5309 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
5310 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
5311
5312 /******************* Bit definition for SDIO_ARG register *******************/
5313 #define SDIO_ARG_CMDARG_Pos (0U)
5314 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
5315 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
5316
5317 /******************* Bit definition for SDIO_CMD register *******************/
5318 #define SDIO_CMD_CMDINDEX_Pos (0U)
5319 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
5320 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
5321
5322 #define SDIO_CMD_WAITRESP_Pos (6U)
5323 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
5324 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
5325 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
5326 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
5327
5328 #define SDIO_CMD_WAITINT_Pos (8U)
5329 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
5330 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
5331 #define SDIO_CMD_WAITPEND_Pos (9U)
5332 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
5333 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
5334 #define SDIO_CMD_CPSMEN_Pos (10U)
5335 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
5336 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
5337 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
5338 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
5339 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
5340 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
5341 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
5342 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
5343 #define SDIO_CMD_NIEN_Pos (13U)
5344 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
5345 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
5346 #define SDIO_CMD_CEATACMD_Pos (14U)
5347 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
5348 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
5349
5350 /***************** Bit definition for SDIO_RESPCMD register *****************/
5351 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
5352 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
5353 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
5354
5355 /****************** Bit definition for SDIO_RESP0 register ******************/
5356 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
5357 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
5358 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
5359
5360 /****************** Bit definition for SDIO_RESP1 register ******************/
5361 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
5362 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
5363 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
5364
5365 /****************** Bit definition for SDIO_RESP2 register ******************/
5366 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
5367 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
5368 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
5369
5370 /****************** Bit definition for SDIO_RESP3 register ******************/
5371 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
5372 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
5373 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
5374
5375 /****************** Bit definition for SDIO_RESP4 register ******************/
5376 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
5377 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
5378 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
5379
5380 /****************** Bit definition for SDIO_DTIMER register *****************/
5381 #define SDIO_DTIMER_DATATIME_Pos (0U)
5382 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
5383 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
5384
5385 /****************** Bit definition for SDIO_DLEN register *******************/
5386 #define SDIO_DLEN_DATALENGTH_Pos (0U)
5387 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
5388 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
5389
5390 /****************** Bit definition for SDIO_DCTRL register ******************/
5391 #define SDIO_DCTRL_DTEN_Pos (0U)
5392 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
5393 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
5394 #define SDIO_DCTRL_DTDIR_Pos (1U)
5395 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
5396 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
5397 #define SDIO_DCTRL_DTMODE_Pos (2U)
5398 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
5399 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
5400 #define SDIO_DCTRL_DMAEN_Pos (3U)
5401 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
5402 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
5403
5404 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
5405 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
5406 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
5407 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
5408 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
5409 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
5410 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
5411
5412 #define SDIO_DCTRL_RWSTART_Pos (8U)
5413 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
5414 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
5415 #define SDIO_DCTRL_RWSTOP_Pos (9U)
5416 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
5417 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
5418 #define SDIO_DCTRL_RWMOD_Pos (10U)
5419 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
5420 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
5421 #define SDIO_DCTRL_SDIOEN_Pos (11U)
5422 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
5423 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
5424
5425 /****************** Bit definition for SDIO_DCOUNT register *****************/
5426 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
5427 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
5428 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
5429
5430 /****************** Bit definition for SDIO_STA register ********************/
5431 #define SDIO_STA_CCRCFAIL_Pos (0U)
5432 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
5433 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
5434 #define SDIO_STA_DCRCFAIL_Pos (1U)
5435 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
5436 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
5437 #define SDIO_STA_CTIMEOUT_Pos (2U)
5438 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
5439 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
5440 #define SDIO_STA_DTIMEOUT_Pos (3U)
5441 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
5442 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
5443 #define SDIO_STA_TXUNDERR_Pos (4U)
5444 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
5445 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
5446 #define SDIO_STA_RXOVERR_Pos (5U)
5447 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
5448 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
5449 #define SDIO_STA_CMDREND_Pos (6U)
5450 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
5451 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
5452 #define SDIO_STA_CMDSENT_Pos (7U)
5453 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
5454 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
5455 #define SDIO_STA_DATAEND_Pos (8U)
5456 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
5457 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
5458 #define SDIO_STA_STBITERR_Pos (9U)
5459 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
5460 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
5461 #define SDIO_STA_DBCKEND_Pos (10U)
5462 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
5463 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
5464 #define SDIO_STA_CMDACT_Pos (11U)
5465 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
5466 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
5467 #define SDIO_STA_TXACT_Pos (12U)
5468 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
5469 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
5470 #define SDIO_STA_RXACT_Pos (13U)
5471 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
5472 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
5473 #define SDIO_STA_TXFIFOHE_Pos (14U)
5474 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
5475 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5476 #define SDIO_STA_RXFIFOHF_Pos (15U)
5477 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
5478 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
5479 #define SDIO_STA_TXFIFOF_Pos (16U)
5480 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
5481 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
5482 #define SDIO_STA_RXFIFOF_Pos (17U)
5483 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
5484 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
5485 #define SDIO_STA_TXFIFOE_Pos (18U)
5486 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
5487 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
5488 #define SDIO_STA_RXFIFOE_Pos (19U)
5489 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
5490 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
5491 #define SDIO_STA_TXDAVL_Pos (20U)
5492 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
5493 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
5494 #define SDIO_STA_RXDAVL_Pos (21U)
5495 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
5496 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
5497 #define SDIO_STA_SDIOIT_Pos (22U)
5498 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
5499 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
5500 #define SDIO_STA_CEATAEND_Pos (23U)
5501 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
5502 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
5503
5504 /******************* Bit definition for SDIO_ICR register *******************/
5505 #define SDIO_ICR_CCRCFAILC_Pos (0U)
5506 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
5507 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
5508 #define SDIO_ICR_DCRCFAILC_Pos (1U)
5509 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
5510 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
5511 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
5512 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
5513 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
5514 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
5515 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
5516 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
5517 #define SDIO_ICR_TXUNDERRC_Pos (4U)
5518 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
5519 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
5520 #define SDIO_ICR_RXOVERRC_Pos (5U)
5521 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
5522 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
5523 #define SDIO_ICR_CMDRENDC_Pos (6U)
5524 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
5525 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
5526 #define SDIO_ICR_CMDSENTC_Pos (7U)
5527 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
5528 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
5529 #define SDIO_ICR_DATAENDC_Pos (8U)
5530 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
5531 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
5532 #define SDIO_ICR_STBITERRC_Pos (9U)
5533 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
5534 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
5535 #define SDIO_ICR_DBCKENDC_Pos (10U)
5536 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
5537 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
5538 #define SDIO_ICR_SDIOITC_Pos (22U)
5539 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
5540 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
5541 #define SDIO_ICR_CEATAENDC_Pos (23U)
5542 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
5543 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
5544
5545 /****************** Bit definition for SDIO_MASK register *******************/
5546 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
5547 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
5548 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
5549 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
5550 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
5551 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
5552 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
5553 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
5554 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
5555 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
5556 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
5557 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
5558 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
5559 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
5560 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
5561 #define SDIO_MASK_RXOVERRIE_Pos (5U)
5562 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
5563 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
5564 #define SDIO_MASK_CMDRENDIE_Pos (6U)
5565 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
5566 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
5567 #define SDIO_MASK_CMDSENTIE_Pos (7U)
5568 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
5569 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
5570 #define SDIO_MASK_DATAENDIE_Pos (8U)
5571 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
5572 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
5573 #define SDIO_MASK_STBITERRIE_Pos (9U)
5574 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
5575 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
5576 #define SDIO_MASK_DBCKENDIE_Pos (10U)
5577 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
5578 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
5579 #define SDIO_MASK_CMDACTIE_Pos (11U)
5580 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
5581 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
5582 #define SDIO_MASK_TXACTIE_Pos (12U)
5583 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
5584 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
5585 #define SDIO_MASK_RXACTIE_Pos (13U)
5586 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
5587 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
5588 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
5589 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
5590 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
5591 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
5592 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
5593 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
5594 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
5595 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
5596 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
5597 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
5598 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
5599 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
5600 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
5601 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
5602 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
5603 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
5604 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
5605 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
5606 #define SDIO_MASK_TXDAVLIE_Pos (20U)
5607 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
5608 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
5609 #define SDIO_MASK_RXDAVLIE_Pos (21U)
5610 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
5611 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
5612 #define SDIO_MASK_SDIOITIE_Pos (22U)
5613 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
5614 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
5615 #define SDIO_MASK_CEATAENDIE_Pos (23U)
5616 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
5617 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
5618
5619 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5620 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
5621 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
5622 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
5623
5624 /****************** Bit definition for SDIO_FIFO register *******************/
5625 #define SDIO_FIFO_FIFODATA_Pos (0U)
5626 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
5627 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
5628
5629 /******************************************************************************/
5630 /* */
5631 /* Serial Peripheral Interface */
5632 /* */
5633 /******************************************************************************/
5634 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
5635
5636 /******************* Bit definition for SPI_CR1 register ********************/
5637 #define SPI_CR1_CPHA_Pos (0U)
5638 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
5639 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
5640 #define SPI_CR1_CPOL_Pos (1U)
5641 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
5642 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
5643 #define SPI_CR1_MSTR_Pos (2U)
5644 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
5645 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
5646
5647 #define SPI_CR1_BR_Pos (3U)
5648 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
5649 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
5650 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
5651 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
5652 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
5653
5654 #define SPI_CR1_SPE_Pos (6U)
5655 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
5656 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
5657 #define SPI_CR1_LSBFIRST_Pos (7U)
5658 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
5659 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
5660 #define SPI_CR1_SSI_Pos (8U)
5661 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
5662 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
5663 #define SPI_CR1_SSM_Pos (9U)
5664 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
5665 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
5666 #define SPI_CR1_RXONLY_Pos (10U)
5667 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
5668 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
5669 #define SPI_CR1_DFF_Pos (11U)
5670 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
5671 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
5672 #define SPI_CR1_CRCNEXT_Pos (12U)
5673 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
5674 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
5675 #define SPI_CR1_CRCEN_Pos (13U)
5676 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
5677 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
5678 #define SPI_CR1_BIDIOE_Pos (14U)
5679 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
5680 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
5681 #define SPI_CR1_BIDIMODE_Pos (15U)
5682 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
5683 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
5684
5685 /******************* Bit definition for SPI_CR2 register ********************/
5686 #define SPI_CR2_RXDMAEN_Pos (0U)
5687 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
5688 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
5689 #define SPI_CR2_TXDMAEN_Pos (1U)
5690 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
5691 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
5692 #define SPI_CR2_SSOE_Pos (2U)
5693 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
5694 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
5695 #define SPI_CR2_FRF_Pos (4U)
5696 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
5697 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
5698 #define SPI_CR2_ERRIE_Pos (5U)
5699 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
5700 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
5701 #define SPI_CR2_RXNEIE_Pos (6U)
5702 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
5703 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
5704 #define SPI_CR2_TXEIE_Pos (7U)
5705 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
5706 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
5707
5708 /******************** Bit definition for SPI_SR register ********************/
5709 #define SPI_SR_RXNE_Pos (0U)
5710 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
5711 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
5712 #define SPI_SR_TXE_Pos (1U)
5713 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
5714 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
5715 #define SPI_SR_CHSIDE_Pos (2U)
5716 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
5717 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
5718 #define SPI_SR_UDR_Pos (3U)
5719 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
5720 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
5721 #define SPI_SR_CRCERR_Pos (4U)
5722 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
5723 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
5724 #define SPI_SR_MODF_Pos (5U)
5725 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
5726 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
5727 #define SPI_SR_OVR_Pos (6U)
5728 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
5729 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
5730 #define SPI_SR_BSY_Pos (7U)
5731 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
5732 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
5733 #define SPI_SR_FRE_Pos (8U)
5734 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
5735 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
5736
5737 /******************** Bit definition for SPI_DR register ********************/
5738 #define SPI_DR_DR_Pos (0U)
5739 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
5740 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
5741
5742 /******************* Bit definition for SPI_CRCPR register ******************/
5743 #define SPI_CRCPR_CRCPOLY_Pos (0U)
5744 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
5745 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
5746
5747 /****************** Bit definition for SPI_RXCRCR register ******************/
5748 #define SPI_RXCRCR_RXCRC_Pos (0U)
5749 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
5750 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
5751
5752 /****************** Bit definition for SPI_TXCRCR register ******************/
5753 #define SPI_TXCRCR_TXCRC_Pos (0U)
5754 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
5755 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
5756
5757 /****************** Bit definition for SPI_I2SCFGR register *****************/
5758 #define SPI_I2SCFGR_CHLEN_Pos (0U)
5759 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
5760 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
5761
5762 #define SPI_I2SCFGR_DATLEN_Pos (1U)
5763 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
5764 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
5765 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
5766 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
5767
5768 #define SPI_I2SCFGR_CKPOL_Pos (3U)
5769 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
5770 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
5771
5772 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
5773 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
5774 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
5775 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
5776 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
5777
5778 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
5779 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
5780 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
5781
5782 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
5783 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
5784 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5785 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
5786 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
5787
5788 #define SPI_I2SCFGR_I2SE_Pos (10U)
5789 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
5790 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
5791 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
5792 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
5793 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
5794
5795 /****************** Bit definition for SPI_I2SPR register *******************/
5796 #define SPI_I2SPR_I2SDIV_Pos (0U)
5797 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
5798 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
5799 #define SPI_I2SPR_ODD_Pos (8U)
5800 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
5801 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
5802 #define SPI_I2SPR_MCKOE_Pos (9U)
5803 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
5804 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
5805
5806 /******************************************************************************/
5807 /* */
5808 /* SYSCFG */
5809 /* */
5810 /******************************************************************************/
5811 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
5812 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
5813 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
5814 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
5815 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
5816 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
5817 /****************** Bit definition for SYSCFG_PMC register ******************/
5818 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
5819 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
5820 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
5821
5822 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5823 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
5824 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
5825 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
5826 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
5827 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
5828 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
5829 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
5830 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
5831 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
5832 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
5833 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
5834 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
5835 /**
5836 * @brief EXTI0 configuration
5837 */
5838 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
5839 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
5840 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
5841 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
5842 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
5843 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
5844
5845 /**
5846 * @brief EXTI1 configuration
5847 */
5848 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
5849 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
5850 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
5851 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
5852 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
5853 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
5854
5855 /**
5856 * @brief EXTI2 configuration
5857 */
5858 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
5859 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
5860 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
5861 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
5862 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
5863 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
5864
5865 /**
5866 * @brief EXTI3 configuration
5867 */
5868 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
5869 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
5870 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
5871 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
5872 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
5873 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
5874
5875 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5876 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
5877 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
5878 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
5879 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
5880 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
5881 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
5882 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
5883 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
5884 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
5885 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
5886 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
5887 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
5888
5889 /**
5890 * @brief EXTI4 configuration
5891 */
5892 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
5893 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
5894 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
5895 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
5896 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
5897 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
5898
5899 /**
5900 * @brief EXTI5 configuration
5901 */
5902 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
5903 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
5904 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
5905 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
5906 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
5907 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
5908
5909 /**
5910 * @brief EXTI6 configuration
5911 */
5912 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
5913 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
5914 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
5915 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
5916 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
5917 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
5918
5919 /**
5920 * @brief EXTI7 configuration
5921 */
5922 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
5923 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
5924 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
5925 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
5926 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
5927 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
5928
5929 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5930 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
5931 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
5932 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
5933 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
5934 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
5935 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
5936 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
5937 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
5938 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
5939 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
5940 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
5941 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
5942
5943 /**
5944 * @brief EXTI8 configuration
5945 */
5946 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
5947 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
5948 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
5949 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
5950 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
5951 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
5952
5953 /**
5954 * @brief EXTI9 configuration
5955 */
5956 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
5957 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
5958 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
5959 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
5960 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
5961 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
5962
5963 /**
5964 * @brief EXTI10 configuration
5965 */
5966 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
5967 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
5968 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
5969 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
5970 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
5971 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
5972
5973 /**
5974 * @brief EXTI11 configuration
5975 */
5976 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
5977 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
5978 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
5979 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
5980 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
5981 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
5982
5983 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5984 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
5985 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
5986 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
5987 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
5988 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
5989 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
5990 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
5991 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
5992 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
5993 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
5994 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
5995 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
5996
5997 /**
5998 * @brief EXTI12 configuration
5999 */
6000 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
6001 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
6002 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
6003 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
6004 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
6005 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
6006
6007 /**
6008 * @brief EXTI13 configuration
6009 */
6010 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
6011 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
6012 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
6013 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
6014 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
6015 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
6016
6017 /**
6018 * @brief EXTI14 configuration
6019 */
6020 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
6021 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
6022 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
6023 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
6024 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
6025 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
6026
6027 /**
6028 * @brief EXTI15 configuration
6029 */
6030 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
6031 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
6032 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
6033 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
6034 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
6035 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
6036
6037 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6038 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
6039 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
6040 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
6041 #define SYSCFG_CMPCR_READY_Pos (8U)
6042 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
6043 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
6044
6045 /******************************************************************************/
6046 /* */
6047 /* TIM */
6048 /* */
6049 /******************************************************************************/
6050 /******************* Bit definition for TIM_CR1 register ********************/
6051 #define TIM_CR1_CEN_Pos (0U)
6052 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
6053 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
6054 #define TIM_CR1_UDIS_Pos (1U)
6055 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
6056 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
6057 #define TIM_CR1_URS_Pos (2U)
6058 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
6059 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
6060 #define TIM_CR1_OPM_Pos (3U)
6061 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
6062 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
6063 #define TIM_CR1_DIR_Pos (4U)
6064 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
6065 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
6066
6067 #define TIM_CR1_CMS_Pos (5U)
6068 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
6069 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
6070 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
6071 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
6072
6073 #define TIM_CR1_ARPE_Pos (7U)
6074 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
6075 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
6076
6077 #define TIM_CR1_CKD_Pos (8U)
6078 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
6079 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
6080 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
6081 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
6082
6083 /******************* Bit definition for TIM_CR2 register ********************/
6084 #define TIM_CR2_CCPC_Pos (0U)
6085 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
6086 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
6087 #define TIM_CR2_CCUS_Pos (2U)
6088 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
6089 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
6090 #define TIM_CR2_CCDS_Pos (3U)
6091 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
6092 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
6093
6094 #define TIM_CR2_MMS_Pos (4U)
6095 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
6096 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
6097 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
6098 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
6099 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
6100
6101 #define TIM_CR2_TI1S_Pos (7U)
6102 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
6103 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
6104 #define TIM_CR2_OIS1_Pos (8U)
6105 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
6106 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
6107 #define TIM_CR2_OIS1N_Pos (9U)
6108 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
6109 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
6110 #define TIM_CR2_OIS2_Pos (10U)
6111 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
6112 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
6113 #define TIM_CR2_OIS2N_Pos (11U)
6114 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
6115 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
6116 #define TIM_CR2_OIS3_Pos (12U)
6117 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
6118 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
6119 #define TIM_CR2_OIS3N_Pos (13U)
6120 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
6121 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
6122 #define TIM_CR2_OIS4_Pos (14U)
6123 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
6124 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
6125
6126 /******************* Bit definition for TIM_SMCR register *******************/
6127 #define TIM_SMCR_SMS_Pos (0U)
6128 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
6129 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
6130 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
6131 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
6132 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
6133
6134 #define TIM_SMCR_TS_Pos (4U)
6135 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
6136 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
6137 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
6138 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
6139 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
6140
6141 #define TIM_SMCR_MSM_Pos (7U)
6142 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
6143 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
6144
6145 #define TIM_SMCR_ETF_Pos (8U)
6146 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
6147 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
6148 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
6149 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
6150 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
6151 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
6152
6153 #define TIM_SMCR_ETPS_Pos (12U)
6154 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
6155 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
6156 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
6157 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
6158
6159 #define TIM_SMCR_ECE_Pos (14U)
6160 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
6161 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
6162 #define TIM_SMCR_ETP_Pos (15U)
6163 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
6164 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
6165
6166 /******************* Bit definition for TIM_DIER register *******************/
6167 #define TIM_DIER_UIE_Pos (0U)
6168 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
6169 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
6170 #define TIM_DIER_CC1IE_Pos (1U)
6171 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
6172 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
6173 #define TIM_DIER_CC2IE_Pos (2U)
6174 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
6175 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
6176 #define TIM_DIER_CC3IE_Pos (3U)
6177 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
6178 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
6179 #define TIM_DIER_CC4IE_Pos (4U)
6180 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
6181 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
6182 #define TIM_DIER_COMIE_Pos (5U)
6183 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
6184 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
6185 #define TIM_DIER_TIE_Pos (6U)
6186 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
6187 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
6188 #define TIM_DIER_BIE_Pos (7U)
6189 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
6190 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
6191 #define TIM_DIER_UDE_Pos (8U)
6192 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
6193 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
6194 #define TIM_DIER_CC1DE_Pos (9U)
6195 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
6196 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
6197 #define TIM_DIER_CC2DE_Pos (10U)
6198 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
6199 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
6200 #define TIM_DIER_CC3DE_Pos (11U)
6201 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
6202 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
6203 #define TIM_DIER_CC4DE_Pos (12U)
6204 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
6205 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
6206 #define TIM_DIER_COMDE_Pos (13U)
6207 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
6208 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
6209 #define TIM_DIER_TDE_Pos (14U)
6210 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
6211 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
6212
6213 /******************** Bit definition for TIM_SR register ********************/
6214 #define TIM_SR_UIF_Pos (0U)
6215 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
6216 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
6217 #define TIM_SR_CC1IF_Pos (1U)
6218 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
6219 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
6220 #define TIM_SR_CC2IF_Pos (2U)
6221 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
6222 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
6223 #define TIM_SR_CC3IF_Pos (3U)
6224 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
6225 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
6226 #define TIM_SR_CC4IF_Pos (4U)
6227 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
6228 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
6229 #define TIM_SR_COMIF_Pos (5U)
6230 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
6231 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
6232 #define TIM_SR_TIF_Pos (6U)
6233 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
6234 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
6235 #define TIM_SR_BIF_Pos (7U)
6236 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
6237 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
6238 #define TIM_SR_CC1OF_Pos (9U)
6239 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
6240 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
6241 #define TIM_SR_CC2OF_Pos (10U)
6242 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
6243 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
6244 #define TIM_SR_CC3OF_Pos (11U)
6245 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
6246 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
6247 #define TIM_SR_CC4OF_Pos (12U)
6248 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
6249 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
6250
6251 /******************* Bit definition for TIM_EGR register ********************/
6252 #define TIM_EGR_UG_Pos (0U)
6253 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
6254 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
6255 #define TIM_EGR_CC1G_Pos (1U)
6256 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
6257 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
6258 #define TIM_EGR_CC2G_Pos (2U)
6259 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
6260 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
6261 #define TIM_EGR_CC3G_Pos (3U)
6262 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
6263 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
6264 #define TIM_EGR_CC4G_Pos (4U)
6265 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
6266 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
6267 #define TIM_EGR_COMG_Pos (5U)
6268 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
6269 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
6270 #define TIM_EGR_TG_Pos (6U)
6271 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
6272 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
6273 #define TIM_EGR_BG_Pos (7U)
6274 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
6275 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
6276
6277 /****************** Bit definition for TIM_CCMR1 register *******************/
6278 #define TIM_CCMR1_CC1S_Pos (0U)
6279 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
6280 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6281 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
6282 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
6283
6284 #define TIM_CCMR1_OC1FE_Pos (2U)
6285 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
6286 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
6287 #define TIM_CCMR1_OC1PE_Pos (3U)
6288 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
6289 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
6290
6291 #define TIM_CCMR1_OC1M_Pos (4U)
6292 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
6293 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6294 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
6295 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
6296 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
6297
6298 #define TIM_CCMR1_OC1CE_Pos (7U)
6299 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
6300 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
6301
6302 #define TIM_CCMR1_CC2S_Pos (8U)
6303 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
6304 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6305 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
6306 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
6307
6308 #define TIM_CCMR1_OC2FE_Pos (10U)
6309 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
6310 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
6311 #define TIM_CCMR1_OC2PE_Pos (11U)
6312 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
6313 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
6314
6315 #define TIM_CCMR1_OC2M_Pos (12U)
6316 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
6317 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6318 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
6319 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
6320 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
6321
6322 #define TIM_CCMR1_OC2CE_Pos (15U)
6323 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
6324 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
6325
6326 /*----------------------------------------------------------------------------*/
6327
6328 #define TIM_CCMR1_IC1PSC_Pos (2U)
6329 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
6330 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6331 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
6332 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
6333
6334 #define TIM_CCMR1_IC1F_Pos (4U)
6335 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
6336 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6337 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
6338 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
6339 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
6340 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
6341
6342 #define TIM_CCMR1_IC2PSC_Pos (10U)
6343 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
6344 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6345 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
6346 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
6347
6348 #define TIM_CCMR1_IC2F_Pos (12U)
6349 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
6350 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6351 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
6352 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
6353 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
6354 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
6355
6356 /****************** Bit definition for TIM_CCMR2 register *******************/
6357 #define TIM_CCMR2_CC3S_Pos (0U)
6358 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
6359 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6360 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
6361 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
6362
6363 #define TIM_CCMR2_OC3FE_Pos (2U)
6364 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
6365 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
6366 #define TIM_CCMR2_OC3PE_Pos (3U)
6367 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
6368 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
6369
6370 #define TIM_CCMR2_OC3M_Pos (4U)
6371 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
6372 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6373 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
6374 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
6375 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
6376
6377 #define TIM_CCMR2_OC3CE_Pos (7U)
6378 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
6379 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
6380
6381 #define TIM_CCMR2_CC4S_Pos (8U)
6382 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
6383 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6384 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
6385 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
6386
6387 #define TIM_CCMR2_OC4FE_Pos (10U)
6388 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
6389 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
6390 #define TIM_CCMR2_OC4PE_Pos (11U)
6391 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
6392 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
6393
6394 #define TIM_CCMR2_OC4M_Pos (12U)
6395 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
6396 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6397 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
6398 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
6399 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
6400
6401 #define TIM_CCMR2_OC4CE_Pos (15U)
6402 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
6403 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
6404
6405 /*----------------------------------------------------------------------------*/
6406
6407 #define TIM_CCMR2_IC3PSC_Pos (2U)
6408 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
6409 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6410 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
6411 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
6412
6413 #define TIM_CCMR2_IC3F_Pos (4U)
6414 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
6415 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6416 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
6417 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
6418 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
6419 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
6420
6421 #define TIM_CCMR2_IC4PSC_Pos (10U)
6422 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
6423 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6424 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
6425 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
6426
6427 #define TIM_CCMR2_IC4F_Pos (12U)
6428 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
6429 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6430 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
6431 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
6432 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
6433 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
6434
6435 /******************* Bit definition for TIM_CCER register *******************/
6436 #define TIM_CCER_CC1E_Pos (0U)
6437 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
6438 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
6439 #define TIM_CCER_CC1P_Pos (1U)
6440 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
6441 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
6442 #define TIM_CCER_CC1NE_Pos (2U)
6443 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
6444 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
6445 #define TIM_CCER_CC1NP_Pos (3U)
6446 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
6447 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
6448 #define TIM_CCER_CC2E_Pos (4U)
6449 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
6450 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
6451 #define TIM_CCER_CC2P_Pos (5U)
6452 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
6453 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
6454 #define TIM_CCER_CC2NE_Pos (6U)
6455 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
6456 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
6457 #define TIM_CCER_CC2NP_Pos (7U)
6458 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
6459 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
6460 #define TIM_CCER_CC3E_Pos (8U)
6461 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
6462 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
6463 #define TIM_CCER_CC3P_Pos (9U)
6464 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
6465 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
6466 #define TIM_CCER_CC3NE_Pos (10U)
6467 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
6468 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
6469 #define TIM_CCER_CC3NP_Pos (11U)
6470 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
6471 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
6472 #define TIM_CCER_CC4E_Pos (12U)
6473 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
6474 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
6475 #define TIM_CCER_CC4P_Pos (13U)
6476 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
6477 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
6478 #define TIM_CCER_CC4NP_Pos (15U)
6479 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
6480 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
6481
6482 /******************* Bit definition for TIM_CNT register ********************/
6483 #define TIM_CNT_CNT_Pos (0U)
6484 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
6485 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
6486
6487 /******************* Bit definition for TIM_PSC register ********************/
6488 #define TIM_PSC_PSC_Pos (0U)
6489 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
6490 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
6491
6492 /******************* Bit definition for TIM_ARR register ********************/
6493 #define TIM_ARR_ARR_Pos (0U)
6494 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
6495 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
6496
6497 /******************* Bit definition for TIM_RCR register ********************/
6498 #define TIM_RCR_REP_Pos (0U)
6499 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
6500 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
6501
6502 /******************* Bit definition for TIM_CCR1 register *******************/
6503 #define TIM_CCR1_CCR1_Pos (0U)
6504 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
6505 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
6506
6507 /******************* Bit definition for TIM_CCR2 register *******************/
6508 #define TIM_CCR2_CCR2_Pos (0U)
6509 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
6510 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
6511
6512 /******************* Bit definition for TIM_CCR3 register *******************/
6513 #define TIM_CCR3_CCR3_Pos (0U)
6514 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
6515 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
6516
6517 /******************* Bit definition for TIM_CCR4 register *******************/
6518 #define TIM_CCR4_CCR4_Pos (0U)
6519 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
6520 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
6521
6522 /******************* Bit definition for TIM_BDTR register *******************/
6523 #define TIM_BDTR_DTG_Pos (0U)
6524 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
6525 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6526 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
6527 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
6528 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
6529 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
6530 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
6531 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
6532 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
6533 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
6534
6535 #define TIM_BDTR_LOCK_Pos (8U)
6536 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
6537 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
6538 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
6539 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
6540
6541 #define TIM_BDTR_OSSI_Pos (10U)
6542 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
6543 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
6544 #define TIM_BDTR_OSSR_Pos (11U)
6545 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
6546 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
6547 #define TIM_BDTR_BKE_Pos (12U)
6548 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
6549 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
6550 #define TIM_BDTR_BKP_Pos (13U)
6551 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
6552 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
6553 #define TIM_BDTR_AOE_Pos (14U)
6554 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
6555 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
6556 #define TIM_BDTR_MOE_Pos (15U)
6557 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
6558 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
6559
6560 /******************* Bit definition for TIM_DCR register ********************/
6561 #define TIM_DCR_DBA_Pos (0U)
6562 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
6563 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
6564 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
6565 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
6566 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
6567 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
6568 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
6569
6570 #define TIM_DCR_DBL_Pos (8U)
6571 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
6572 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
6573 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
6574 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
6575 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
6576 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
6577 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
6578
6579 /******************* Bit definition for TIM_DMAR register *******************/
6580 #define TIM_DMAR_DMAB_Pos (0U)
6581 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
6582 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
6583
6584 /******************* Bit definition for TIM_OR register *********************/
6585 #define TIM_OR_TI1_RMP_Pos (0U)
6586 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
6587 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
6588 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
6589 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
6590
6591 #define TIM_OR_TI4_RMP_Pos (6U)
6592 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
6593 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
6594 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
6595 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
6596 #define TIM_OR_ITR1_RMP_Pos (10U)
6597 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
6598 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
6599 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
6600 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
6601
6602
6603 /******************************************************************************/
6604 /* */
6605 /* Universal Synchronous Asynchronous Receiver Transmitter */
6606 /* */
6607 /******************************************************************************/
6608 /******************* Bit definition for USART_SR register *******************/
6609 #define USART_SR_PE_Pos (0U)
6610 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
6611 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
6612 #define USART_SR_FE_Pos (1U)
6613 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
6614 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
6615 #define USART_SR_NE_Pos (2U)
6616 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
6617 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
6618 #define USART_SR_ORE_Pos (3U)
6619 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
6620 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
6621 #define USART_SR_IDLE_Pos (4U)
6622 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
6623 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
6624 #define USART_SR_RXNE_Pos (5U)
6625 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
6626 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
6627 #define USART_SR_TC_Pos (6U)
6628 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
6629 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
6630 #define USART_SR_TXE_Pos (7U)
6631 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
6632 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
6633 #define USART_SR_LBD_Pos (8U)
6634 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
6635 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
6636 #define USART_SR_CTS_Pos (9U)
6637 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
6638 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
6639
6640 /******************* Bit definition for USART_DR register *******************/
6641 #define USART_DR_DR_Pos (0U)
6642 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
6643 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
6644
6645 /****************** Bit definition for USART_BRR register *******************/
6646 #define USART_BRR_DIV_Fraction_Pos (0U)
6647 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
6648 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
6649 #define USART_BRR_DIV_Mantissa_Pos (4U)
6650 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
6651 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
6652
6653 /****************** Bit definition for USART_CR1 register *******************/
6654 #define USART_CR1_SBK_Pos (0U)
6655 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
6656 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
6657 #define USART_CR1_RWU_Pos (1U)
6658 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
6659 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
6660 #define USART_CR1_RE_Pos (2U)
6661 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
6662 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
6663 #define USART_CR1_TE_Pos (3U)
6664 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
6665 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
6666 #define USART_CR1_IDLEIE_Pos (4U)
6667 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
6668 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
6669 #define USART_CR1_RXNEIE_Pos (5U)
6670 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
6671 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
6672 #define USART_CR1_TCIE_Pos (6U)
6673 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
6674 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
6675 #define USART_CR1_TXEIE_Pos (7U)
6676 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
6677 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
6678 #define USART_CR1_PEIE_Pos (8U)
6679 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
6680 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
6681 #define USART_CR1_PS_Pos (9U)
6682 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
6683 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
6684 #define USART_CR1_PCE_Pos (10U)
6685 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
6686 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
6687 #define USART_CR1_WAKE_Pos (11U)
6688 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
6689 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
6690 #define USART_CR1_M_Pos (12U)
6691 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
6692 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
6693 #define USART_CR1_UE_Pos (13U)
6694 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
6695 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
6696 #define USART_CR1_OVER8_Pos (15U)
6697 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
6698 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
6699
6700 /****************** Bit definition for USART_CR2 register *******************/
6701 #define USART_CR2_ADD_Pos (0U)
6702 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
6703 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
6704 #define USART_CR2_LBDL_Pos (5U)
6705 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
6706 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
6707 #define USART_CR2_LBDIE_Pos (6U)
6708 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
6709 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
6710 #define USART_CR2_LBCL_Pos (8U)
6711 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
6712 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
6713 #define USART_CR2_CPHA_Pos (9U)
6714 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
6715 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
6716 #define USART_CR2_CPOL_Pos (10U)
6717 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
6718 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
6719 #define USART_CR2_CLKEN_Pos (11U)
6720 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
6721 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
6722
6723 #define USART_CR2_STOP_Pos (12U)
6724 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
6725 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
6726 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
6727 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
6728
6729 #define USART_CR2_LINEN_Pos (14U)
6730 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
6731 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
6732
6733 /****************** Bit definition for USART_CR3 register *******************/
6734 #define USART_CR3_EIE_Pos (0U)
6735 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
6736 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
6737 #define USART_CR3_IREN_Pos (1U)
6738 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
6739 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
6740 #define USART_CR3_IRLP_Pos (2U)
6741 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
6742 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
6743 #define USART_CR3_HDSEL_Pos (3U)
6744 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
6745 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
6746 #define USART_CR3_NACK_Pos (4U)
6747 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
6748 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
6749 #define USART_CR3_SCEN_Pos (5U)
6750 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
6751 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
6752 #define USART_CR3_DMAR_Pos (6U)
6753 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
6754 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
6755 #define USART_CR3_DMAT_Pos (7U)
6756 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
6757 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
6758 #define USART_CR3_RTSE_Pos (8U)
6759 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
6760 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
6761 #define USART_CR3_CTSE_Pos (9U)
6762 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
6763 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
6764 #define USART_CR3_CTSIE_Pos (10U)
6765 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
6766 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
6767 #define USART_CR3_ONEBIT_Pos (11U)
6768 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
6769 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
6770
6771 /****************** Bit definition for USART_GTPR register ******************/
6772 #define USART_GTPR_PSC_Pos (0U)
6773 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
6774 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
6775 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
6776 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
6777 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
6778 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
6779 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
6780 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
6781 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
6782 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
6783
6784 #define USART_GTPR_GT_Pos (8U)
6785 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
6786 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
6787
6788 /******************************************************************************/
6789 /* */
6790 /* Window WATCHDOG */
6791 /* */
6792 /******************************************************************************/
6793 /******************* Bit definition for WWDG_CR register ********************/
6794 #define WWDG_CR_T_Pos (0U)
6795 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
6796 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
6797 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
6798 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
6799 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
6800 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
6801 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
6802 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
6803 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
6804 /* Legacy defines */
6805 #define WWDG_CR_T0 WWDG_CR_T_0
6806 #define WWDG_CR_T1 WWDG_CR_T_1
6807 #define WWDG_CR_T2 WWDG_CR_T_2
6808 #define WWDG_CR_T3 WWDG_CR_T_3
6809 #define WWDG_CR_T4 WWDG_CR_T_4
6810 #define WWDG_CR_T5 WWDG_CR_T_5
6811 #define WWDG_CR_T6 WWDG_CR_T_6
6812
6813 #define WWDG_CR_WDGA_Pos (7U)
6814 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
6815 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
6816
6817 /******************* Bit definition for WWDG_CFR register *******************/
6818 #define WWDG_CFR_W_Pos (0U)
6819 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
6820 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
6821 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
6822 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
6823 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
6824 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
6825 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
6826 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
6827 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
6828 /* Legacy defines */
6829 #define WWDG_CFR_W0 WWDG_CFR_W_0
6830 #define WWDG_CFR_W1 WWDG_CFR_W_1
6831 #define WWDG_CFR_W2 WWDG_CFR_W_2
6832 #define WWDG_CFR_W3 WWDG_CFR_W_3
6833 #define WWDG_CFR_W4 WWDG_CFR_W_4
6834 #define WWDG_CFR_W5 WWDG_CFR_W_5
6835 #define WWDG_CFR_W6 WWDG_CFR_W_6
6836
6837 #define WWDG_CFR_WDGTB_Pos (7U)
6838 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
6839 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
6840 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
6841 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
6842 /* Legacy defines */
6843 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
6844 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
6845
6846 #define WWDG_CFR_EWI_Pos (9U)
6847 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
6848 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
6849
6850 /******************* Bit definition for WWDG_SR register ********************/
6851 #define WWDG_SR_EWIF_Pos (0U)
6852 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
6853 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
6854
6855
6856 /******************************************************************************/
6857 /* */
6858 /* DBG */
6859 /* */
6860 /******************************************************************************/
6861 /******************** Bit definition for DBGMCU_IDCODE register *************/
6862 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
6863 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
6864 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
6865 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
6866 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
6867 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
6868
6869 /******************** Bit definition for DBGMCU_CR register *****************/
6870 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
6871 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
6872 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
6873 #define DBGMCU_CR_DBG_STOP_Pos (1U)
6874 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
6875 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
6876 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
6877 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
6878 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
6879 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
6880 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
6881 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
6882
6883 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
6884 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
6885 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
6886 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
6887 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
6888
6889 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6890 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
6891 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
6892 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
6893 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
6894 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
6895 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
6896 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
6897 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
6898 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
6899 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
6900 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
6901 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
6902 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
6903 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
6904 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
6905 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
6906 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
6907 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
6908 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
6909 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
6910 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
6911 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
6912 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
6913 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
6914 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
6915 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
6916 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
6917 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
6918 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
6919 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
6920 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
6921 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
6922
6923 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6924 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
6925 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
6926 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
6927 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
6928 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
6929 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
6930 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
6931 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
6932 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
6933 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
6934 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
6935 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
6936
6937 /******************************************************************************/
6938 /* */
6939 /* USB_OTG */
6940 /* */
6941 /******************************************************************************/
6942 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
6943 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
6944 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
6945 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
6946 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
6947 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
6948 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
6949 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
6950 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
6951 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
6952 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
6953 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
6954 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
6955 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
6956 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
6957 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
6958 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
6959 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
6960 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
6961 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
6962 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
6963 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
6964 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
6965 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
6966 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
6967 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
6968 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
6969 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
6970 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
6971 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
6972 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
6973
6974 /******************** Bit definition forUSB_OTG_HCFG register ********************/
6975
6976 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
6977 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
6978 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
6979 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
6980 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
6981 #define USB_OTG_HCFG_FSLSS_Pos (2U)
6982 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
6983 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
6984
6985 /******************** Bit definition for USB_OTG_DCFG register ********************/
6986
6987 #define USB_OTG_DCFG_DSPD_Pos (0U)
6988 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
6989 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
6990 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
6991 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
6992 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
6993 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
6994 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
6995
6996 #define USB_OTG_DCFG_DAD_Pos (4U)
6997 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
6998 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
6999 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
7000 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
7001 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
7002 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
7003 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
7004 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
7005 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
7006
7007 #define USB_OTG_DCFG_PFIVL_Pos (11U)
7008 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
7009 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
7010 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
7011 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
7012
7013 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
7014 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
7015 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
7016 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
7017 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
7018
7019 /******************** Bit definition for USB_OTG_PCGCR register ********************/
7020 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
7021 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
7022 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
7023 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
7024 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
7025 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
7026 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
7027 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
7028 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
7029
7030 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
7031 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
7032 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
7033 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
7034 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
7035 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
7036 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
7037 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
7038 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
7039 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
7040 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
7041 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
7042 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
7043 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
7044 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
7045 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
7046 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
7047 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
7048 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
7049
7050 /******************** Bit definition for USB_OTG_DCTL register ********************/
7051 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
7052 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
7053 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
7054 #define USB_OTG_DCTL_SDIS_Pos (1U)
7055 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
7056 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
7057 #define USB_OTG_DCTL_GINSTS_Pos (2U)
7058 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
7059 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
7060 #define USB_OTG_DCTL_GONSTS_Pos (3U)
7061 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
7062 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
7063
7064 #define USB_OTG_DCTL_TCTL_Pos (4U)
7065 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
7066 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
7067 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
7068 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
7069 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
7070 #define USB_OTG_DCTL_SGINAK_Pos (7U)
7071 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
7072 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
7073 #define USB_OTG_DCTL_CGINAK_Pos (8U)
7074 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
7075 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
7076 #define USB_OTG_DCTL_SGONAK_Pos (9U)
7077 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
7078 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
7079 #define USB_OTG_DCTL_CGONAK_Pos (10U)
7080 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
7081 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
7082 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
7083 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
7084 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
7085
7086 /******************** Bit definition for USB_OTG_HFIR register ********************/
7087 #define USB_OTG_HFIR_FRIVL_Pos (0U)
7088 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
7089 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
7090
7091 /******************** Bit definition for USB_OTG_HFNUM register ********************/
7092 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
7093 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
7094 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
7095 #define USB_OTG_HFNUM_FTREM_Pos (16U)
7096 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
7097 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
7098
7099 /******************** Bit definition for USB_OTG_DSTS register ********************/
7100 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
7101 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
7102 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
7103
7104 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
7105 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
7106 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
7107 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
7108 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
7109 #define USB_OTG_DSTS_EERR_Pos (3U)
7110 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
7111 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
7112 #define USB_OTG_DSTS_FNSOF_Pos (8U)
7113 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
7114 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
7115
7116 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
7117 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
7118 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
7119 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
7120 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
7121 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
7122 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
7123 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
7124 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
7125 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
7126 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
7127 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
7128 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
7129 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
7130 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
7131 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
7132 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
7133 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
7134 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
7135 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
7136 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
7137
7138 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
7139
7140 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
7141 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
7142 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
7143 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
7144 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
7145 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
7146 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
7147 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
7148 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
7149 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
7150 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
7151 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
7152 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
7153 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
7154 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
7155 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
7156 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
7157 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
7158 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
7159 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
7160 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
7161 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
7162 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
7163 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
7164 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
7165 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
7166 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
7167 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
7168 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
7169 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
7170 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
7171 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
7172 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
7173 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
7174 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
7175 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
7176 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
7177 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
7178 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
7179 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
7180 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
7181 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
7182 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
7183 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
7184 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
7185 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
7186 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
7187 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
7188 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
7189 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
7190 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
7191 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
7192 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
7193 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
7194 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
7195 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
7196 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
7197 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
7198 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
7199 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
7200 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
7201
7202 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
7203 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
7204 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
7205 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
7206 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
7207 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
7208 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
7209 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
7210 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
7211 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
7212 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
7213 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
7214 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
7215 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
7216 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
7217 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
7218
7219
7220 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
7221 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
7222 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
7223 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
7224 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
7225 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
7226 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
7227 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
7228 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
7229 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
7230 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
7231 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
7232 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
7233 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
7234
7235 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
7236 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
7237 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
7238 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
7239 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
7240 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
7241 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
7242 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
7243 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
7244 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
7245 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
7246 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
7247 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
7248 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
7249 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
7250 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
7251 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
7252 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
7253 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
7254 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
7255 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
7256 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
7257 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
7258 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
7259 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
7260
7261 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
7262 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
7263 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
7264 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
7265 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
7266 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
7267 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
7268 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
7269 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
7270 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
7271 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
7272 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
7273 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
7274 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
7275 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
7276
7277 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
7278 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
7279 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
7280 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
7281 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
7282 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
7283 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
7284 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
7285 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
7286 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
7287 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
7288
7289 /******************** Bit definition for USB_OTG_HAINT register ********************/
7290 #define USB_OTG_HAINT_HAINT_Pos (0U)
7291 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
7292 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
7293
7294 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
7295 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
7296 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
7297 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
7298 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
7299 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
7300 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
7301 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
7302 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
7303 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
7304 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
7305 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
7306 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
7307 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
7308 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
7309 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
7310 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
7311 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
7312 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
7313 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
7314 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
7315 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
7316
7317 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
7318 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
7319 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
7320 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
7321 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
7322 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
7323 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
7324 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
7325 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
7326 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
7327 #define USB_OTG_GINTSTS_SOF_Pos (3U)
7328 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
7329 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
7330 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
7331 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
7332 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
7333 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
7334 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
7335 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
7336 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
7337 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
7338 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
7339 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
7340 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
7341 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
7342 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
7343 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
7344 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
7345 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
7346 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
7347 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
7348 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
7349 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
7350 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
7351 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
7352 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
7353 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
7354 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
7355 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
7356 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
7357 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
7358 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
7359 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
7360 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
7361 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
7362 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
7363 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
7364 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
7365 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
7366 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
7367 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
7368 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
7369 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
7370 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
7371 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
7372 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
7373 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
7374 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
7375 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
7376 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
7377 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
7378 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
7379 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
7380 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
7381 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
7382 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
7383 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
7384 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
7385 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
7386 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
7387 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
7388 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
7389 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
7390 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
7391 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
7392 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
7393 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
7394 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
7395 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
7396
7397 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
7398 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
7399 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
7400 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
7401 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
7402 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
7403 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
7404 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
7405 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
7406 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
7407 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
7408 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
7409 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
7410 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
7411 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
7412 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
7413 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
7414 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
7415 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
7416 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
7417 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
7418 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
7419 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
7420 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
7421 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
7422 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
7423 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
7424 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
7425 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
7426 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
7427 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
7428 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
7429 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
7430 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
7431 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
7432 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
7433 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
7434 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
7435 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
7436 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
7437 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
7438 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
7439 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
7440 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
7441 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
7442 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
7443 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
7444 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
7445 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
7446 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
7447 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
7448 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
7449 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
7450 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
7451 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
7452 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
7453 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
7454 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
7455 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
7456 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
7457 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
7458 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
7459 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
7460 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
7461 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
7462 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
7463 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
7464 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
7465 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
7466 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
7467 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
7468 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
7469 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
7470 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
7471 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
7472 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
7473 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
7474 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
7475 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
7476
7477 /******************** Bit definition for USB_OTG_DAINT register ********************/
7478 #define USB_OTG_DAINT_IEPINT_Pos (0U)
7479 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
7480 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
7481 #define USB_OTG_DAINT_OEPINT_Pos (16U)
7482 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
7483 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
7484
7485 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
7486 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
7487 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
7488 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
7489
7490 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
7491 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
7492 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
7493 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
7494 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
7495 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
7496 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
7497 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
7498 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
7499 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
7500 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
7501 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
7502 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
7503
7504 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
7505 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
7506 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
7507 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
7508 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
7509 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
7510 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
7511
7512 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
7513 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
7514 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
7515 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
7516
7517 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
7518 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
7519 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
7520 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
7521
7522 /******************** Bit definition for OTG register ********************/
7523 #define USB_OTG_NPTXFSA_Pos (0U)
7524 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
7525 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
7526 #define USB_OTG_NPTXFD_Pos (16U)
7527 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
7528 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
7529 #define USB_OTG_TX0FSA_Pos (0U)
7530 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
7531 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
7532 #define USB_OTG_TX0FD_Pos (16U)
7533 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
7534 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
7535
7536 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
7537 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
7538 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
7539 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
7540
7541 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
7542 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
7543 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
7544 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
7545
7546 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
7547 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
7548 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
7549 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
7550 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
7551 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
7552 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
7553 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
7554 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
7555 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
7556 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
7557
7558 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
7559 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
7560 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
7561 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
7562 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
7563 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
7564 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
7565 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
7566 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
7567 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
7568
7569 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
7570 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
7571 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
7572 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
7573 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
7574 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
7575 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
7576
7577 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
7578 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
7579 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
7580 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
7581 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
7582 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
7583 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
7584 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
7585 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
7586 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
7587 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
7588 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
7589 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
7590 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
7591 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
7592
7593 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
7594 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
7595 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
7596 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
7597 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
7598 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
7599 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
7600 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
7601 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
7602 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
7603 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
7604 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
7605 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
7606 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
7607 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
7608
7609 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
7610 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
7611 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
7612 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
7613
7614 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
7615 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
7616 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
7617 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
7618 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
7619 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
7620 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
7621
7622 /******************** Bit definition for USB_OTG_GCCFG register ********************/
7623 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
7624 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
7625 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
7626 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
7627 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
7628 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
7629 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
7630 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
7631 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
7632 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
7633 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
7634 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
7635 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
7636 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
7637 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
7638 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
7639 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
7640 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
7641
7642 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
7643 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
7644 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
7645 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
7646 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
7647 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
7648 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
7649
7650 /******************** Bit definition for USB_OTG_CID register ********************/
7651 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
7652 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
7653 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
7654
7655 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
7656 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
7657 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
7658 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
7659 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
7660 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
7661 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
7662 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
7663 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
7664 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
7665 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
7666 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
7667 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
7668 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
7669 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
7670 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
7671 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
7672 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
7673 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
7674 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
7675 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
7676 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
7677 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
7678 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
7679 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
7680 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
7681 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
7682 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
7683
7684 /******************** Bit definition for USB_OTG_HPRT register ********************/
7685 #define USB_OTG_HPRT_PCSTS_Pos (0U)
7686 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
7687 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
7688 #define USB_OTG_HPRT_PCDET_Pos (1U)
7689 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
7690 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
7691 #define USB_OTG_HPRT_PENA_Pos (2U)
7692 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
7693 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
7694 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
7695 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
7696 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
7697 #define USB_OTG_HPRT_POCA_Pos (4U)
7698 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
7699 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
7700 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
7701 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
7702 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
7703 #define USB_OTG_HPRT_PRES_Pos (6U)
7704 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
7705 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
7706 #define USB_OTG_HPRT_PSUSP_Pos (7U)
7707 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
7708 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
7709 #define USB_OTG_HPRT_PRST_Pos (8U)
7710 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
7711 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
7712
7713 #define USB_OTG_HPRT_PLSTS_Pos (10U)
7714 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
7715 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
7716 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
7717 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
7718 #define USB_OTG_HPRT_PPWR_Pos (12U)
7719 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
7720 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
7721
7722 #define USB_OTG_HPRT_PTCTL_Pos (13U)
7723 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
7724 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
7725 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
7726 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
7727 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
7728 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
7729
7730 #define USB_OTG_HPRT_PSPD_Pos (17U)
7731 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
7732 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
7733 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
7734 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
7735
7736 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
7737 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
7738 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
7739 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
7740 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
7741 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
7742 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
7743 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
7744 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
7745 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
7746 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
7747 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
7748 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
7749 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
7750 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
7751 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
7752 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
7753 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
7754 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
7755 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
7756 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
7757 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
7758 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
7759 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
7760 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
7761 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
7762 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
7763 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
7764 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
7765 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
7766 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
7767 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
7768 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
7769 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
7770
7771 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
7772 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
7773 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
7774 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
7775 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
7776 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
7777 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
7778
7779 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
7780 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
7781 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
7782 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
7783 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
7784 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
7785 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
7786 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
7787 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
7788 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
7789 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
7790 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
7791 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
7792
7793 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
7794 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
7795 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
7796 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
7797 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
7798 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
7799 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
7800 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
7801
7802 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
7803 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
7804 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
7805 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
7806 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
7807 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
7808 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
7809 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
7810 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
7811 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
7812 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
7813 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
7814 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
7815 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
7816 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
7817 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
7818 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
7819 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
7820 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
7821 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
7822 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
7823 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
7824 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
7825 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
7826 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
7827
7828 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
7829 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
7830 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
7831 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
7832
7833 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
7834 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
7835 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
7836 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
7837 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
7838 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
7839 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
7840 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
7841 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
7842 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
7843 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
7844 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
7845 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
7846
7847 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
7848 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
7849 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
7850 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
7851 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
7852
7853 #define USB_OTG_HCCHAR_MC_Pos (20U)
7854 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
7855 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
7856 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
7857 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
7858
7859 #define USB_OTG_HCCHAR_DAD_Pos (22U)
7860 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
7861 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
7862 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
7863 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
7864 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
7865 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
7866 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
7867 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
7868 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
7869 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
7870 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
7871 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
7872 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
7873 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
7874 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
7875 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
7876 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
7877 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
7878
7879 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
7880
7881 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
7882 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
7883 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
7884 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
7885 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
7886 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
7887 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
7888 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
7889 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
7890 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
7891
7892 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
7893 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
7894 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
7895 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
7896 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
7897 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
7898 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
7899 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
7900 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
7901 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
7902
7903 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
7904 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
7905 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
7906 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
7907 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
7908 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
7909 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
7910 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
7911 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
7912 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
7913 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
7914
7915 /******************** Bit definition for USB_OTG_HCINT register ********************/
7916 #define USB_OTG_HCINT_XFRC_Pos (0U)
7917 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
7918 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
7919 #define USB_OTG_HCINT_CHH_Pos (1U)
7920 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
7921 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
7922 #define USB_OTG_HCINT_AHBERR_Pos (2U)
7923 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
7924 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
7925 #define USB_OTG_HCINT_STALL_Pos (3U)
7926 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
7927 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
7928 #define USB_OTG_HCINT_NAK_Pos (4U)
7929 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
7930 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
7931 #define USB_OTG_HCINT_ACK_Pos (5U)
7932 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
7933 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
7934 #define USB_OTG_HCINT_NYET_Pos (6U)
7935 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
7936 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
7937 #define USB_OTG_HCINT_TXERR_Pos (7U)
7938 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
7939 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
7940 #define USB_OTG_HCINT_BBERR_Pos (8U)
7941 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
7942 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
7943 #define USB_OTG_HCINT_FRMOR_Pos (9U)
7944 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
7945 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
7946 #define USB_OTG_HCINT_DTERR_Pos (10U)
7947 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
7948 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
7949
7950 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
7951 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
7952 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
7953 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
7954 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
7955 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
7956 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
7957 #define USB_OTG_DIEPINT_TOC_Pos (3U)
7958 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
7959 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
7960 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
7961 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
7962 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
7963 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
7964 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
7965 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
7966 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
7967 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
7968 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
7969 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
7970 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
7971 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
7972 #define USB_OTG_DIEPINT_BNA_Pos (9U)
7973 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
7974 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
7975 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
7976 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
7977 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
7978 #define USB_OTG_DIEPINT_BERR_Pos (12U)
7979 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
7980 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
7981 #define USB_OTG_DIEPINT_NAK_Pos (13U)
7982 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
7983 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
7984
7985 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
7986 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
7987 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
7988 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
7989 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
7990 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
7991 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
7992 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
7993 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
7994 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
7995 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
7996 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
7997 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
7998 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
7999 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
8000 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
8001 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
8002 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
8003 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
8004 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
8005 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
8006 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
8007 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
8008 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
8009 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
8010 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
8011 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
8012 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
8013 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
8014 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
8015 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
8016 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
8017 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
8018 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
8019
8020 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8021
8022 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
8023 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
8024 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
8025 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
8026 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
8027 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
8028 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
8029 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
8030 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
8031 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
8032 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
8033 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
8034 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
8035 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
8036 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
8037 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
8038 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
8039 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
8040 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
8041 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
8042 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
8043 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
8044 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
8045 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
8046
8047 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
8048 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
8049 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
8050 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
8051
8052 /******************** Bit definition for USB_OTG_HCDMA register ********************/
8053 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
8054 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
8055 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
8056
8057 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
8058 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
8059 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
8060 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
8061
8062 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
8063 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
8064 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
8065 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
8066 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
8067 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
8068 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
8069
8070 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
8071
8072 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
8073 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
8074 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
8075 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
8076 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
8077 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
8078 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
8079 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
8080 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
8081 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
8082 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
8083 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
8084 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
8085 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
8086 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
8087 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
8088 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
8089 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
8090 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
8091 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
8092 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
8093 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
8094 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
8095 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
8096 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
8097 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
8098 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
8099 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
8100 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
8101 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
8102 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
8103 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
8104 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
8105 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
8106 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
8107 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
8108 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
8109 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
8110
8111 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
8112 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
8113 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
8114 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
8115 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
8116 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
8117 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
8118 #define USB_OTG_DOEPINT_STUP_Pos (3U)
8119 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
8120 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
8121 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
8122 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
8123 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
8124 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
8125 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
8126 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
8127 #define USB_OTG_DOEPINT_NYET_Pos (14U)
8128 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
8129 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
8130
8131 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
8132
8133 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
8134 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
8135 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
8136 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
8137 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
8138 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
8139
8140 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
8141 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
8142 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
8143 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
8144 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
8145
8146 /******************** Bit definition for PCGCCTL register ********************/
8147 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
8148 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
8149 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
8150 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
8151 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
8152 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
8153 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
8154 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
8155 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
8156
8157 /* Legacy define */
8158 /******************** Bit definition for OTG register ********************/
8159 #define USB_OTG_CHNUM_Pos (0U)
8160 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
8161 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
8162 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
8163 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
8164 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
8165 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
8166 #define USB_OTG_BCNT_Pos (4U)
8167 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
8168 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
8169
8170 #define USB_OTG_DPID_Pos (15U)
8171 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
8172 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
8173 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
8174 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
8175
8176 #define USB_OTG_PKTSTS_Pos (17U)
8177 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
8178 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
8179 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
8180 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
8181 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
8182 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
8183
8184 #define USB_OTG_EPNUM_Pos (0U)
8185 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
8186 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
8187 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
8188 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
8189 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
8190 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
8191
8192 #define USB_OTG_FRMNUM_Pos (21U)
8193 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
8194 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
8195 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
8196 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
8197 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
8198 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
8199 /**
8200 * @}
8201 */
8202
8203 /**
8204 * @}
8205 */
8206
8207 /** @addtogroup Exported_macros
8208 * @{
8209 */
8210
8211 /******************************* ADC Instances ********************************/
8212 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
8213
8214 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
8215 /******************************* CRC Instances ********************************/
8216 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
8217
8218
8219 /******************************** DMA Instances *******************************/
8220 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
8221 ((INSTANCE) == DMA1_Stream1) || \
8222 ((INSTANCE) == DMA1_Stream2) || \
8223 ((INSTANCE) == DMA1_Stream3) || \
8224 ((INSTANCE) == DMA1_Stream4) || \
8225 ((INSTANCE) == DMA1_Stream5) || \
8226 ((INSTANCE) == DMA1_Stream6) || \
8227 ((INSTANCE) == DMA1_Stream7) || \
8228 ((INSTANCE) == DMA2_Stream0) || \
8229 ((INSTANCE) == DMA2_Stream1) || \
8230 ((INSTANCE) == DMA2_Stream2) || \
8231 ((INSTANCE) == DMA2_Stream3) || \
8232 ((INSTANCE) == DMA2_Stream4) || \
8233 ((INSTANCE) == DMA2_Stream5) || \
8234 ((INSTANCE) == DMA2_Stream6) || \
8235 ((INSTANCE) == DMA2_Stream7))
8236
8237 /******************************* GPIO Instances *******************************/
8238 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
8239 ((INSTANCE) == GPIOB) || \
8240 ((INSTANCE) == GPIOC) || \
8241 ((INSTANCE) == GPIOD) || \
8242 ((INSTANCE) == GPIOE) || \
8243 ((INSTANCE) == GPIOH))
8244
8245 /******************************** I2C Instances *******************************/
8246 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
8247 ((INSTANCE) == I2C2) || \
8248 ((INSTANCE) == I2C3))
8249
8250 /******************************* SMBUS Instances ******************************/
8251 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
8252
8253 /******************************** I2S Instances *******************************/
8254
8255 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
8256 ((INSTANCE) == SPI3))
8257
8258 /*************************** I2S Extended Instances ***************************/
8259 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
8260 ((INSTANCE) == I2S3ext))
8261 /* Legacy Defines */
8262 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
8263
8264
8265 /****************************** RTC Instances *********************************/
8266 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
8267
8268
8269 /******************************** SPI Instances *******************************/
8270 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8271 ((INSTANCE) == SPI2) || \
8272 ((INSTANCE) == SPI3) || \
8273 ((INSTANCE) == SPI4))
8274
8275
8276 /****************** TIM Instances : All supported instances *******************/
8277 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8278 ((INSTANCE) == TIM2) || \
8279 ((INSTANCE) == TIM3) || \
8280 ((INSTANCE) == TIM4) || \
8281 ((INSTANCE) == TIM5) || \
8282 ((INSTANCE) == TIM9) || \
8283 ((INSTANCE) == TIM10) || \
8284 ((INSTANCE) == TIM11))
8285
8286
8287 /************* TIM Instances : at least 1 capture/compare channel *************/
8288 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8289 ((INSTANCE) == TIM2) || \
8290 ((INSTANCE) == TIM3) || \
8291 ((INSTANCE) == TIM4) || \
8292 ((INSTANCE) == TIM5) || \
8293 ((INSTANCE) == TIM9) || \
8294 ((INSTANCE) == TIM10) || \
8295 ((INSTANCE) == TIM11))
8296
8297 /************ TIM Instances : at least 2 capture/compare channels *************/
8298 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8299 ((INSTANCE) == TIM2) || \
8300 ((INSTANCE) == TIM3) || \
8301 ((INSTANCE) == TIM4) || \
8302 ((INSTANCE) == TIM5) || \
8303 ((INSTANCE) == TIM9))
8304
8305 /************ TIM Instances : at least 3 capture/compare channels *************/
8306 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8307 ((INSTANCE) == TIM2) || \
8308 ((INSTANCE) == TIM3) || \
8309 ((INSTANCE) == TIM4) || \
8310 ((INSTANCE) == TIM5))
8311
8312 /************ TIM Instances : at least 4 capture/compare channels *************/
8313 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8314 ((INSTANCE) == TIM2) || \
8315 ((INSTANCE) == TIM3) || \
8316 ((INSTANCE) == TIM4) || \
8317 ((INSTANCE) == TIM5))
8318
8319 /******************** TIM Instances : Advanced-control timers *****************/
8320 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
8321
8322 /******************* TIM Instances : Timer input XOR function *****************/
8323 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8324 ((INSTANCE) == TIM2) || \
8325 ((INSTANCE) == TIM3) || \
8326 ((INSTANCE) == TIM4) || \
8327 ((INSTANCE) == TIM5))
8328
8329 /****************** TIM Instances : DMA requests generation (UDE) *************/
8330 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8331 ((INSTANCE) == TIM2) || \
8332 ((INSTANCE) == TIM3) || \
8333 ((INSTANCE) == TIM4) || \
8334 ((INSTANCE) == TIM5))
8335
8336 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
8337 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8338 ((INSTANCE) == TIM2) || \
8339 ((INSTANCE) == TIM3) || \
8340 ((INSTANCE) == TIM4) || \
8341 ((INSTANCE) == TIM5))
8342
8343 /************ TIM Instances : DMA requests generation (COMDE) *****************/
8344 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8345 ((INSTANCE) == TIM2) || \
8346 ((INSTANCE) == TIM3) || \
8347 ((INSTANCE) == TIM4) || \
8348 ((INSTANCE) == TIM5))
8349
8350 /******************** TIM Instances : DMA burst feature ***********************/
8351 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8352 ((INSTANCE) == TIM2) || \
8353 ((INSTANCE) == TIM3) || \
8354 ((INSTANCE) == TIM4) || \
8355 ((INSTANCE) == TIM5))
8356
8357 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8358 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8359 ((INSTANCE) == TIM2) || \
8360 ((INSTANCE) == TIM3) || \
8361 ((INSTANCE) == TIM4) || \
8362 ((INSTANCE) == TIM5))
8363
8364 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8365 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8366 ((INSTANCE) == TIM2) || \
8367 ((INSTANCE) == TIM3) || \
8368 ((INSTANCE) == TIM4) || \
8369 ((INSTANCE) == TIM5) || \
8370 ((INSTANCE) == TIM9))
8371
8372 /********************** TIM Instances : 32 bit Counter ************************/
8373 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
8374 ((INSTANCE) == TIM5))
8375
8376 /***************** TIM Instances : external trigger input availabe ************/
8377 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8378 ((INSTANCE) == TIM2) || \
8379 ((INSTANCE) == TIM3) || \
8380 ((INSTANCE) == TIM4) || \
8381 ((INSTANCE) == TIM5))
8382
8383 /****************** TIM Instances : remapping capability **********************/
8384 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
8385 ((INSTANCE) == TIM5) || \
8386 ((INSTANCE) == TIM11))
8387
8388 /******************* TIM Instances : output(s) available **********************/
8389 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8390 ((((INSTANCE) == TIM1) && \
8391 (((CHANNEL) == TIM_CHANNEL_1) || \
8392 ((CHANNEL) == TIM_CHANNEL_2) || \
8393 ((CHANNEL) == TIM_CHANNEL_3) || \
8394 ((CHANNEL) == TIM_CHANNEL_4))) \
8395 || \
8396 (((INSTANCE) == TIM2) && \
8397 (((CHANNEL) == TIM_CHANNEL_1) || \
8398 ((CHANNEL) == TIM_CHANNEL_2) || \
8399 ((CHANNEL) == TIM_CHANNEL_3) || \
8400 ((CHANNEL) == TIM_CHANNEL_4))) \
8401 || \
8402 (((INSTANCE) == TIM3) && \
8403 (((CHANNEL) == TIM_CHANNEL_1) || \
8404 ((CHANNEL) == TIM_CHANNEL_2) || \
8405 ((CHANNEL) == TIM_CHANNEL_3) || \
8406 ((CHANNEL) == TIM_CHANNEL_4))) \
8407 || \
8408 (((INSTANCE) == TIM4) && \
8409 (((CHANNEL) == TIM_CHANNEL_1) || \
8410 ((CHANNEL) == TIM_CHANNEL_2) || \
8411 ((CHANNEL) == TIM_CHANNEL_3) || \
8412 ((CHANNEL) == TIM_CHANNEL_4))) \
8413 || \
8414 (((INSTANCE) == TIM5) && \
8415 (((CHANNEL) == TIM_CHANNEL_1) || \
8416 ((CHANNEL) == TIM_CHANNEL_2) || \
8417 ((CHANNEL) == TIM_CHANNEL_3) || \
8418 ((CHANNEL) == TIM_CHANNEL_4))) \
8419 || \
8420 (((INSTANCE) == TIM9) && \
8421 (((CHANNEL) == TIM_CHANNEL_1) || \
8422 ((CHANNEL) == TIM_CHANNEL_2))) \
8423 || \
8424 (((INSTANCE) == TIM10) && \
8425 (((CHANNEL) == TIM_CHANNEL_1))) \
8426 || \
8427 (((INSTANCE) == TIM11) && \
8428 (((CHANNEL) == TIM_CHANNEL_1))))
8429
8430 /************ TIM Instances : complementary output(s) available ***************/
8431 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8432 ((((INSTANCE) == TIM1) && \
8433 (((CHANNEL) == TIM_CHANNEL_1) || \
8434 ((CHANNEL) == TIM_CHANNEL_2) || \
8435 ((CHANNEL) == TIM_CHANNEL_3))))
8436
8437 /****************** TIM Instances : supporting counting mode selection ********/
8438 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8439 ((INSTANCE) == TIM2) || \
8440 ((INSTANCE) == TIM3) || \
8441 ((INSTANCE) == TIM4) || \
8442 ((INSTANCE) == TIM5))
8443
8444 /****************** TIM Instances : supporting clock division *****************/
8445 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8446 ((INSTANCE) == TIM2) || \
8447 ((INSTANCE) == TIM3) || \
8448 ((INSTANCE) == TIM4) || \
8449 ((INSTANCE) == TIM5) || \
8450 ((INSTANCE) == TIM9) || \
8451 ((INSTANCE) == TIM10) || \
8452 ((INSTANCE) == TIM11))
8453
8454
8455 /****************** TIM Instances : supporting commutation event generation ***/
8456
8457 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
8458
8459 /****************** TIM Instances : supporting OCxREF clear *******************/
8460 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8461 ((INSTANCE) == TIM2) || \
8462 ((INSTANCE) == TIM3) || \
8463 ((INSTANCE) == TIM4) || \
8464 ((INSTANCE) == TIM5))
8465
8466 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
8467 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8468 ((INSTANCE) == TIM2) || \
8469 ((INSTANCE) == TIM3) || \
8470 ((INSTANCE) == TIM4) || \
8471 ((INSTANCE) == TIM5) || \
8472 ((INSTANCE) == TIM9))
8473
8474 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
8475 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
8476 ((INSTANCE) == TIM2) || \
8477 ((INSTANCE) == TIM3) || \
8478 ((INSTANCE) == TIM4) || \
8479 ((INSTANCE) == TIM5))
8480
8481 /****************** TIM Instances : supporting repetition counter *************/
8482 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
8483
8484 /****************** TIM Instances : supporting encoder interface **************/
8485 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8486 ((INSTANCE) == TIM2) || \
8487 ((INSTANCE) == TIM3) || \
8488 ((INSTANCE) == TIM4) || \
8489 ((INSTANCE) == TIM5) || \
8490 ((INSTANCE) == TIM9))
8491 /****************** TIM Instances : supporting Hall sensor interface **********/
8492 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8493 ((INSTANCE) == TIM2) || \
8494 ((INSTANCE) == TIM3) || \
8495 ((INSTANCE) == TIM4) || \
8496 ((INSTANCE) == TIM5))
8497 /****************** TIM Instances : supporting the break function *************/
8498 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
8499
8500 /******************** USART Instances : Synchronous mode **********************/
8501 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8502 ((INSTANCE) == USART2) || \
8503 ((INSTANCE) == USART6))
8504
8505 /******************** UART Instances : Half-Duplex mode **********************/
8506 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8507 ((INSTANCE) == USART2) || \
8508 ((INSTANCE) == USART6))
8509
8510 /* Legacy defines */
8511 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
8512
8513 /****************** UART Instances : Hardware Flow control ********************/
8514 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8515 ((INSTANCE) == USART2) || \
8516 ((INSTANCE) == USART6))
8517 /******************** UART Instances : LIN mode **********************/
8518 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
8519
8520 /********************* UART Instances : Smart card mode ***********************/
8521 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8522 ((INSTANCE) == USART2) || \
8523 ((INSTANCE) == USART6))
8524
8525 /*********************** UART Instances : IRDA mode ***************************/
8526 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8527 ((INSTANCE) == USART2) || \
8528 ((INSTANCE) == USART6))
8529
8530 /*********************** PCD Instances ****************************************/
8531 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
8532
8533 /*********************** HCD Instances ****************************************/
8534 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
8535
8536 /****************************** SDIO Instances ********************************/
8537 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
8538
8539 /****************************** IWDG Instances ********************************/
8540 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
8541
8542 /****************************** WWDG Instances ********************************/
8543 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
8544
8545 /****************************** USB Exported Constants ************************/
8546 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
8547 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
8548 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
8549 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
8550
8551 /*
8552 * @brief Specific devices reset values definitions
8553 */
8554 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
8555 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
8556
8557 #define RCC_MAX_FREQUENCY 84000000U /*!< Max frequency of family in Hz*/
8558 #define RCC_MAX_FREQUENCY_SCALE3 60000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
8559 #define RCC_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale2, in Hz */
8560 #define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
8561 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
8562 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
8563 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
8564
8565 #define RCC_PLLN_MIN_VALUE 192U
8566 #define RCC_PLLN_MAX_VALUE 432U
8567
8568 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
8569 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
8570
8571 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
8572 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
8573
8574
8575 /**
8576 * @}
8577 */
8578
8579 /**
8580 * @}
8581 */
8582
8583 /**
8584 * @}
8585 */
8586
8587 #ifdef __cplusplus
8588 }
8589 #endif /* __cplusplus */
8590
8591 #endif /* __STM32F401xC_H */
8592
8593
8594
8595 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/