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comparison Common/Drivers/CMSIS/Include/core_sc300.h @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /**************************************************************************//** | |
2 * @file core_sc300.h | |
3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File | |
4 * @version V4.30 | |
5 * @date 20. October 2015 | |
6 ******************************************************************************/ | |
7 /* Copyright (c) 2009 - 2015 ARM LIMITED | |
8 | |
9 All rights reserved. | |
10 Redistribution and use in source and binary forms, with or without | |
11 modification, are permitted provided that the following conditions are met: | |
12 - Redistributions of source code must retain the above copyright | |
13 notice, this list of conditions and the following disclaimer. | |
14 - Redistributions in binary form must reproduce the above copyright | |
15 notice, this list of conditions and the following disclaimer in the | |
16 documentation and/or other materials provided with the distribution. | |
17 - Neither the name of ARM nor the names of its contributors may be used | |
18 to endorse or promote products derived from this software without | |
19 specific prior written permission. | |
20 * | |
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE | |
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
31 POSSIBILITY OF SUCH DAMAGE. | |
32 ---------------------------------------------------------------------------*/ | |
33 | |
34 | |
35 #if defined ( __ICCARM__ ) | |
36 #pragma system_include /* treat file as system include file for MISRA check */ | |
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) | |
38 #pragma clang system_header /* treat file as system include file */ | |
39 #endif | |
40 | |
41 #ifndef __CORE_SC300_H_GENERIC | |
42 #define __CORE_SC300_H_GENERIC | |
43 | |
44 #include <stdint.h> | |
45 | |
46 #ifdef __cplusplus | |
47 extern "C" { | |
48 #endif | |
49 | |
50 /** | |
51 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions | |
52 CMSIS violates the following MISRA-C:2004 rules: | |
53 | |
54 \li Required Rule 8.5, object/function definition in header file.<br> | |
55 Function definitions in header files are used to allow 'inlining'. | |
56 | |
57 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> | |
58 Unions are used for effective representation of core registers. | |
59 | |
60 \li Advisory Rule 19.7, Function-like macro defined.<br> | |
61 Function-like macros are used to allow more efficient code. | |
62 */ | |
63 | |
64 | |
65 /******************************************************************************* | |
66 * CMSIS definitions | |
67 ******************************************************************************/ | |
68 /** | |
69 \ingroup SC3000 | |
70 @{ | |
71 */ | |
72 | |
73 /* CMSIS SC300 definitions */ | |
74 #define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ | |
75 #define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ | |
76 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ | |
77 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ | |
78 | |
79 #define __CORTEX_SC (300U) /*!< Cortex secure core */ | |
80 | |
81 | |
82 #if defined ( __CC_ARM ) | |
83 #define __ASM __asm /*!< asm keyword for ARM Compiler */ | |
84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ | |
85 #define __STATIC_INLINE static __inline | |
86 | |
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) | |
88 #define __ASM __asm /*!< asm keyword for ARM Compiler */ | |
89 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ | |
90 #define __STATIC_INLINE static __inline | |
91 | |
92 #elif defined ( __GNUC__ ) | |
93 #define __ASM __asm /*!< asm keyword for GNU Compiler */ | |
94 #define __INLINE inline /*!< inline keyword for GNU Compiler */ | |
95 #define __STATIC_INLINE static inline | |
96 | |
97 #elif defined ( __ICCARM__ ) | |
98 #define __ASM __asm /*!< asm keyword for IAR Compiler */ | |
99 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ | |
100 #define __STATIC_INLINE static inline | |
101 | |
102 #elif defined ( __TMS470__ ) | |
103 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ | |
104 #define __STATIC_INLINE static inline | |
105 | |
106 #elif defined ( __TASKING__ ) | |
107 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ | |
108 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ | |
109 #define __STATIC_INLINE static inline | |
110 | |
111 #elif defined ( __CSMC__ ) | |
112 #define __packed | |
113 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ | |
114 #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ | |
115 #define __STATIC_INLINE static inline | |
116 | |
117 #else | |
118 #error Unknown compiler | |
119 #endif | |
120 | |
121 /** __FPU_USED indicates whether an FPU is used or not. | |
122 This core does not support an FPU at all | |
123 */ | |
124 #define __FPU_USED 0U | |
125 | |
126 #if defined ( __CC_ARM ) | |
127 #if defined __TARGET_FPU_VFP | |
128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" | |
129 #endif | |
130 | |
131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) | |
132 #if defined __ARM_PCS_VFP | |
133 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" | |
134 #endif | |
135 | |
136 #elif defined ( __GNUC__ ) | |
137 #if defined (__VFP_FP__) && !defined(__SOFTFP__) | |
138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" | |
139 #endif | |
140 | |
141 #elif defined ( __ICCARM__ ) | |
142 #if defined __ARMVFP__ | |
143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" | |
144 #endif | |
145 | |
146 #elif defined ( __TMS470__ ) | |
147 #if defined __TI_VFP_SUPPORT__ | |
148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" | |
149 #endif | |
150 | |
151 #elif defined ( __TASKING__ ) | |
152 #if defined __FPU_VFP__ | |
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" | |
154 #endif | |
155 | |
156 #elif defined ( __CSMC__ ) | |
157 #if ( __CSMC__ & 0x400U) | |
158 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" | |
159 #endif | |
160 | |
161 #endif | |
162 | |
163 #include "core_cmInstr.h" /* Core Instruction Access */ | |
164 #include "core_cmFunc.h" /* Core Function Access */ | |
165 | |
166 #ifdef __cplusplus | |
167 } | |
168 #endif | |
169 | |
170 #endif /* __CORE_SC300_H_GENERIC */ | |
171 | |
172 #ifndef __CMSIS_GENERIC | |
173 | |
174 #ifndef __CORE_SC300_H_DEPENDANT | |
175 #define __CORE_SC300_H_DEPENDANT | |
176 | |
177 #ifdef __cplusplus | |
178 extern "C" { | |
179 #endif | |
180 | |
181 /* check device defines and use defaults */ | |
182 #if defined __CHECK_DEVICE_DEFINES | |
183 #ifndef __SC300_REV | |
184 #define __SC300_REV 0x0000U | |
185 #warning "__SC300_REV not defined in device header file; using default!" | |
186 #endif | |
187 | |
188 #ifndef __MPU_PRESENT | |
189 #define __MPU_PRESENT 0U | |
190 #warning "__MPU_PRESENT not defined in device header file; using default!" | |
191 #endif | |
192 | |
193 #ifndef __NVIC_PRIO_BITS | |
194 #define __NVIC_PRIO_BITS 4U | |
195 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" | |
196 #endif | |
197 | |
198 #ifndef __Vendor_SysTickConfig | |
199 #define __Vendor_SysTickConfig 0U | |
200 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" | |
201 #endif | |
202 #endif | |
203 | |
204 /* IO definitions (access restrictions to peripheral registers) */ | |
205 /** | |
206 \defgroup CMSIS_glob_defs CMSIS Global Defines | |
207 | |
208 <strong>IO Type Qualifiers</strong> are used | |
209 \li to specify the access to peripheral variables. | |
210 \li for automatic generation of peripheral register debug information. | |
211 */ | |
212 #ifdef __cplusplus | |
213 #define __I volatile /*!< Defines 'read only' permissions */ | |
214 #else | |
215 #define __I volatile const /*!< Defines 'read only' permissions */ | |
216 #endif | |
217 #define __O volatile /*!< Defines 'write only' permissions */ | |
218 #define __IO volatile /*!< Defines 'read / write' permissions */ | |
219 | |
220 /* following defines should be used for structure members */ | |
221 #define __IM volatile const /*! Defines 'read only' structure member permissions */ | |
222 #define __OM volatile /*! Defines 'write only' structure member permissions */ | |
223 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ | |
224 | |
225 /*@} end of group SC300 */ | |
226 | |
227 | |
228 | |
229 /******************************************************************************* | |
230 * Register Abstraction | |
231 Core Register contain: | |
232 - Core Register | |
233 - Core NVIC Register | |
234 - Core SCB Register | |
235 - Core SysTick Register | |
236 - Core Debug Register | |
237 - Core MPU Register | |
238 ******************************************************************************/ | |
239 /** | |
240 \defgroup CMSIS_core_register Defines and Type Definitions | |
241 \brief Type definitions and defines for Cortex-M processor based devices. | |
242 */ | |
243 | |
244 /** | |
245 \ingroup CMSIS_core_register | |
246 \defgroup CMSIS_CORE Status and Control Registers | |
247 \brief Core Register type definitions. | |
248 @{ | |
249 */ | |
250 | |
251 /** | |
252 \brief Union type to access the Application Program Status Register (APSR). | |
253 */ | |
254 typedef union | |
255 { | |
256 struct | |
257 { | |
258 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ | |
259 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ | |
260 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ | |
261 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ | |
262 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ | |
263 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ | |
264 } b; /*!< Structure used for bit access */ | |
265 uint32_t w; /*!< Type used for word access */ | |
266 } APSR_Type; | |
267 | |
268 /* APSR Register Definitions */ | |
269 #define APSR_N_Pos 31U /*!< APSR: N Position */ | |
270 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ | |
271 | |
272 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ | |
273 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ | |
274 | |
275 #define APSR_C_Pos 29U /*!< APSR: C Position */ | |
276 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ | |
277 | |
278 #define APSR_V_Pos 28U /*!< APSR: V Position */ | |
279 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ | |
280 | |
281 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ | |
282 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ | |
283 | |
284 | |
285 /** | |
286 \brief Union type to access the Interrupt Program Status Register (IPSR). | |
287 */ | |
288 typedef union | |
289 { | |
290 struct | |
291 { | |
292 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ | |
293 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ | |
294 } b; /*!< Structure used for bit access */ | |
295 uint32_t w; /*!< Type used for word access */ | |
296 } IPSR_Type; | |
297 | |
298 /* IPSR Register Definitions */ | |
299 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ | |
300 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ | |
301 | |
302 | |
303 /** | |
304 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). | |
305 */ | |
306 typedef union | |
307 { | |
308 struct | |
309 { | |
310 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ | |
311 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ | |
312 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ | |
313 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ | |
314 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ | |
315 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ | |
316 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ | |
317 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ | |
318 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ | |
319 } b; /*!< Structure used for bit access */ | |
320 uint32_t w; /*!< Type used for word access */ | |
321 } xPSR_Type; | |
322 | |
323 /* xPSR Register Definitions */ | |
324 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ | |
325 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ | |
326 | |
327 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ | |
328 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ | |
329 | |
330 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ | |
331 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ | |
332 | |
333 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ | |
334 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ | |
335 | |
336 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ | |
337 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ | |
338 | |
339 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ | |
340 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ | |
341 | |
342 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ | |
343 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ | |
344 | |
345 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ | |
346 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ | |
347 | |
348 | |
349 /** | |
350 \brief Union type to access the Control Registers (CONTROL). | |
351 */ | |
352 typedef union | |
353 { | |
354 struct | |
355 { | |
356 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ | |
357 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ | |
358 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ | |
359 } b; /*!< Structure used for bit access */ | |
360 uint32_t w; /*!< Type used for word access */ | |
361 } CONTROL_Type; | |
362 | |
363 /* CONTROL Register Definitions */ | |
364 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ | |
365 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ | |
366 | |
367 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ | |
368 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ | |
369 | |
370 /*@} end of group CMSIS_CORE */ | |
371 | |
372 | |
373 /** | |
374 \ingroup CMSIS_core_register | |
375 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) | |
376 \brief Type definitions for the NVIC Registers | |
377 @{ | |
378 */ | |
379 | |
380 /** | |
381 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). | |
382 */ | |
383 typedef struct | |
384 { | |
385 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ | |
386 uint32_t RESERVED0[24U]; | |
387 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ | |
388 uint32_t RSERVED1[24U]; | |
389 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ | |
390 uint32_t RESERVED2[24U]; | |
391 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ | |
392 uint32_t RESERVED3[24U]; | |
393 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ | |
394 uint32_t RESERVED4[56U]; | |
395 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ | |
396 uint32_t RESERVED5[644U]; | |
397 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ | |
398 } NVIC_Type; | |
399 | |
400 /* Software Triggered Interrupt Register Definitions */ | |
401 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ | |
402 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ | |
403 | |
404 /*@} end of group CMSIS_NVIC */ | |
405 | |
406 | |
407 /** | |
408 \ingroup CMSIS_core_register | |
409 \defgroup CMSIS_SCB System Control Block (SCB) | |
410 \brief Type definitions for the System Control Block Registers | |
411 @{ | |
412 */ | |
413 | |
414 /** | |
415 \brief Structure type to access the System Control Block (SCB). | |
416 */ | |
417 typedef struct | |
418 { | |
419 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ | |
420 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ | |
421 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ | |
422 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ | |
423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ | |
424 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ | |
425 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ | |
426 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ | |
427 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ | |
428 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ | |
429 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ | |
430 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ | |
431 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ | |
432 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ | |
433 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ | |
434 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ | |
435 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ | |
436 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ | |
437 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ | |
438 uint32_t RESERVED0[5U]; | |
439 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ | |
440 uint32_t RESERVED1[129U]; | |
441 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ | |
442 } SCB_Type; | |
443 | |
444 /* SCB CPUID Register Definitions */ | |
445 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ | |
446 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ | |
447 | |
448 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ | |
449 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ | |
450 | |
451 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ | |
452 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ | |
453 | |
454 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ | |
455 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ | |
456 | |
457 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ | |
458 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ | |
459 | |
460 /* SCB Interrupt Control State Register Definitions */ | |
461 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ | |
462 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ | |
463 | |
464 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ | |
465 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ | |
466 | |
467 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ | |
468 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ | |
469 | |
470 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ | |
471 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ | |
472 | |
473 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ | |
474 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ | |
475 | |
476 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ | |
477 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ | |
478 | |
479 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ | |
480 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ | |
481 | |
482 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ | |
483 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ | |
484 | |
485 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ | |
486 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ | |
487 | |
488 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ | |
489 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ | |
490 | |
491 /* SCB Vector Table Offset Register Definitions */ | |
492 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ | |
493 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ | |
494 | |
495 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ | |
496 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ | |
497 | |
498 /* SCB Application Interrupt and Reset Control Register Definitions */ | |
499 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ | |
500 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ | |
501 | |
502 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ | |
503 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ | |
504 | |
505 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ | |
506 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ | |
507 | |
508 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ | |
509 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ | |
510 | |
511 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ | |
512 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ | |
513 | |
514 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ | |
515 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ | |
516 | |
517 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ | |
518 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ | |
519 | |
520 /* SCB System Control Register Definitions */ | |
521 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ | |
522 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ | |
523 | |
524 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ | |
525 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ | |
526 | |
527 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ | |
528 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ | |
529 | |
530 /* SCB Configuration Control Register Definitions */ | |
531 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ | |
532 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ | |
533 | |
534 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ | |
535 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ | |
536 | |
537 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ | |
538 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ | |
539 | |
540 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ | |
541 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ | |
542 | |
543 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ | |
544 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ | |
545 | |
546 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ | |
547 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ | |
548 | |
549 /* SCB System Handler Control and State Register Definitions */ | |
550 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ | |
551 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ | |
552 | |
553 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ | |
554 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ | |
555 | |
556 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ | |
557 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ | |
558 | |
559 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ | |
560 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ | |
561 | |
562 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ | |
563 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ | |
564 | |
565 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ | |
566 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ | |
567 | |
568 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ | |
569 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ | |
570 | |
571 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ | |
572 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ | |
573 | |
574 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ | |
575 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ | |
576 | |
577 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ | |
578 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ | |
579 | |
580 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ | |
581 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ | |
582 | |
583 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ | |
584 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ | |
585 | |
586 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ | |
587 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ | |
588 | |
589 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ | |
590 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ | |
591 | |
592 /* SCB Configurable Fault Status Register Definitions */ | |
593 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ | |
594 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ | |
595 | |
596 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ | |
597 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ | |
598 | |
599 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ | |
600 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ | |
601 | |
602 /* SCB Hard Fault Status Register Definitions */ | |
603 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ | |
604 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ | |
605 | |
606 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ | |
607 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ | |
608 | |
609 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ | |
610 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ | |
611 | |
612 /* SCB Debug Fault Status Register Definitions */ | |
613 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ | |
614 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ | |
615 | |
616 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ | |
617 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ | |
618 | |
619 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ | |
620 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ | |
621 | |
622 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ | |
623 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ | |
624 | |
625 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ | |
626 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ | |
627 | |
628 /*@} end of group CMSIS_SCB */ | |
629 | |
630 | |
631 /** | |
632 \ingroup CMSIS_core_register | |
633 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) | |
634 \brief Type definitions for the System Control and ID Register not in the SCB | |
635 @{ | |
636 */ | |
637 | |
638 /** | |
639 \brief Structure type to access the System Control and ID Register not in the SCB. | |
640 */ | |
641 typedef struct | |
642 { | |
643 uint32_t RESERVED0[1U]; | |
644 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ | |
645 uint32_t RESERVED1[1U]; | |
646 } SCnSCB_Type; | |
647 | |
648 /* Interrupt Controller Type Register Definitions */ | |
649 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ | |
650 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ | |
651 | |
652 /*@} end of group CMSIS_SCnotSCB */ | |
653 | |
654 | |
655 /** | |
656 \ingroup CMSIS_core_register | |
657 \defgroup CMSIS_SysTick System Tick Timer (SysTick) | |
658 \brief Type definitions for the System Timer Registers. | |
659 @{ | |
660 */ | |
661 | |
662 /** | |
663 \brief Structure type to access the System Timer (SysTick). | |
664 */ | |
665 typedef struct | |
666 { | |
667 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ | |
668 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ | |
669 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ | |
670 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ | |
671 } SysTick_Type; | |
672 | |
673 /* SysTick Control / Status Register Definitions */ | |
674 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ | |
675 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ | |
676 | |
677 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ | |
678 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ | |
679 | |
680 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ | |
681 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ | |
682 | |
683 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ | |
684 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ | |
685 | |
686 /* SysTick Reload Register Definitions */ | |
687 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ | |
688 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ | |
689 | |
690 /* SysTick Current Register Definitions */ | |
691 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ | |
692 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ | |
693 | |
694 /* SysTick Calibration Register Definitions */ | |
695 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ | |
696 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ | |
697 | |
698 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ | |
699 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ | |
700 | |
701 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ | |
702 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ | |
703 | |
704 /*@} end of group CMSIS_SysTick */ | |
705 | |
706 | |
707 /** | |
708 \ingroup CMSIS_core_register | |
709 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) | |
710 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) | |
711 @{ | |
712 */ | |
713 | |
714 /** | |
715 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). | |
716 */ | |
717 typedef struct | |
718 { | |
719 __OM union | |
720 { | |
721 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ | |
722 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ | |
723 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ | |
724 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ | |
725 uint32_t RESERVED0[864U]; | |
726 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ | |
727 uint32_t RESERVED1[15U]; | |
728 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ | |
729 uint32_t RESERVED2[15U]; | |
730 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ | |
731 uint32_t RESERVED3[29U]; | |
732 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ | |
733 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ | |
734 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ | |
735 uint32_t RESERVED4[43U]; | |
736 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ | |
737 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ | |
738 uint32_t RESERVED5[6U]; | |
739 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ | |
740 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ | |
741 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ | |
742 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ | |
743 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ | |
744 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ | |
745 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ | |
746 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ | |
747 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ | |
748 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ | |
749 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ | |
750 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ | |
751 } ITM_Type; | |
752 | |
753 /* ITM Trace Privilege Register Definitions */ | |
754 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ | |
755 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ | |
756 | |
757 /* ITM Trace Control Register Definitions */ | |
758 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ | |
759 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ | |
760 | |
761 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ | |
762 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ | |
763 | |
764 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ | |
765 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ | |
766 | |
767 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ | |
768 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ | |
769 | |
770 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ | |
771 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ | |
772 | |
773 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ | |
774 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ | |
775 | |
776 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ | |
777 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ | |
778 | |
779 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ | |
780 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ | |
781 | |
782 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ | |
783 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ | |
784 | |
785 /* ITM Integration Write Register Definitions */ | |
786 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ | |
787 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ | |
788 | |
789 /* ITM Integration Read Register Definitions */ | |
790 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ | |
791 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ | |
792 | |
793 /* ITM Integration Mode Control Register Definitions */ | |
794 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ | |
795 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ | |
796 | |
797 /* ITM Lock Status Register Definitions */ | |
798 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ | |
799 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ | |
800 | |
801 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ | |
802 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ | |
803 | |
804 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ | |
805 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ | |
806 | |
807 /*@}*/ /* end of group CMSIS_ITM */ | |
808 | |
809 | |
810 /** | |
811 \ingroup CMSIS_core_register | |
812 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) | |
813 \brief Type definitions for the Data Watchpoint and Trace (DWT) | |
814 @{ | |
815 */ | |
816 | |
817 /** | |
818 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). | |
819 */ | |
820 typedef struct | |
821 { | |
822 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ | |
823 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ | |
824 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ | |
825 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ | |
826 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ | |
827 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ | |
828 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ | |
829 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ | |
830 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ | |
831 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ | |
832 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ | |
833 uint32_t RESERVED0[1U]; | |
834 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ | |
835 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ | |
836 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ | |
837 uint32_t RESERVED1[1U]; | |
838 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ | |
839 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ | |
840 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ | |
841 uint32_t RESERVED2[1U]; | |
842 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ | |
843 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ | |
844 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ | |
845 } DWT_Type; | |
846 | |
847 /* DWT Control Register Definitions */ | |
848 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ | |
849 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ | |
850 | |
851 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ | |
852 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ | |
853 | |
854 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ | |
855 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ | |
856 | |
857 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ | |
858 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ | |
859 | |
860 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ | |
861 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ | |
862 | |
863 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ | |
864 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ | |
865 | |
866 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ | |
867 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ | |
868 | |
869 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ | |
870 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ | |
871 | |
872 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ | |
873 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ | |
874 | |
875 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ | |
876 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ | |
877 | |
878 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ | |
879 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ | |
880 | |
881 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ | |
882 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ | |
883 | |
884 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ | |
885 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ | |
886 | |
887 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ | |
888 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ | |
889 | |
890 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ | |
891 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ | |
892 | |
893 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ | |
894 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ | |
895 | |
896 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ | |
897 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ | |
898 | |
899 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ | |
900 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ | |
901 | |
902 /* DWT CPI Count Register Definitions */ | |
903 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ | |
904 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ | |
905 | |
906 /* DWT Exception Overhead Count Register Definitions */ | |
907 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ | |
908 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ | |
909 | |
910 /* DWT Sleep Count Register Definitions */ | |
911 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ | |
912 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ | |
913 | |
914 /* DWT LSU Count Register Definitions */ | |
915 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ | |
916 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ | |
917 | |
918 /* DWT Folded-instruction Count Register Definitions */ | |
919 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ | |
920 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ | |
921 | |
922 /* DWT Comparator Mask Register Definitions */ | |
923 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ | |
924 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ | |
925 | |
926 /* DWT Comparator Function Register Definitions */ | |
927 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ | |
928 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ | |
929 | |
930 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ | |
931 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ | |
932 | |
933 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ | |
934 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ | |
935 | |
936 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ | |
937 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ | |
938 | |
939 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ | |
940 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ | |
941 | |
942 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ | |
943 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ | |
944 | |
945 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ | |
946 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ | |
947 | |
948 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ | |
949 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ | |
950 | |
951 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ | |
952 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ | |
953 | |
954 /*@}*/ /* end of group CMSIS_DWT */ | |
955 | |
956 | |
957 /** | |
958 \ingroup CMSIS_core_register | |
959 \defgroup CMSIS_TPI Trace Port Interface (TPI) | |
960 \brief Type definitions for the Trace Port Interface (TPI) | |
961 @{ | |
962 */ | |
963 | |
964 /** | |
965 \brief Structure type to access the Trace Port Interface Register (TPI). | |
966 */ | |
967 typedef struct | |
968 { | |
969 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ | |
970 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ | |
971 uint32_t RESERVED0[2U]; | |
972 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ | |
973 uint32_t RESERVED1[55U]; | |
974 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ | |
975 uint32_t RESERVED2[131U]; | |
976 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ | |
977 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ | |
978 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ | |
979 uint32_t RESERVED3[759U]; | |
980 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ | |
981 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ | |
982 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ | |
983 uint32_t RESERVED4[1U]; | |
984 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ | |
985 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ | |
986 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ | |
987 uint32_t RESERVED5[39U]; | |
988 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ | |
989 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ | |
990 uint32_t RESERVED7[8U]; | |
991 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ | |
992 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ | |
993 } TPI_Type; | |
994 | |
995 /* TPI Asynchronous Clock Prescaler Register Definitions */ | |
996 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ | |
997 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ | |
998 | |
999 /* TPI Selected Pin Protocol Register Definitions */ | |
1000 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ | |
1001 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ | |
1002 | |
1003 /* TPI Formatter and Flush Status Register Definitions */ | |
1004 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ | |
1005 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ | |
1006 | |
1007 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ | |
1008 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ | |
1009 | |
1010 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ | |
1011 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ | |
1012 | |
1013 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ | |
1014 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ | |
1015 | |
1016 /* TPI Formatter and Flush Control Register Definitions */ | |
1017 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ | |
1018 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ | |
1019 | |
1020 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ | |
1021 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ | |
1022 | |
1023 /* TPI TRIGGER Register Definitions */ | |
1024 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ | |
1025 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ | |
1026 | |
1027 /* TPI Integration ETM Data Register Definitions (FIFO0) */ | |
1028 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ | |
1029 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ | |
1030 | |
1031 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ | |
1032 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ | |
1033 | |
1034 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ | |
1035 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ | |
1036 | |
1037 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ | |
1038 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ | |
1039 | |
1040 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ | |
1041 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ | |
1042 | |
1043 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ | |
1044 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ | |
1045 | |
1046 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ | |
1047 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ | |
1048 | |
1049 /* TPI ITATBCTR2 Register Definitions */ | |
1050 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ | |
1051 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ | |
1052 | |
1053 /* TPI Integration ITM Data Register Definitions (FIFO1) */ | |
1054 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ | |
1055 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ | |
1056 | |
1057 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ | |
1058 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ | |
1059 | |
1060 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ | |
1061 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ | |
1062 | |
1063 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ | |
1064 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ | |
1065 | |
1066 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ | |
1067 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ | |
1068 | |
1069 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ | |
1070 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ | |
1071 | |
1072 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ | |
1073 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ | |
1074 | |
1075 /* TPI ITATBCTR0 Register Definitions */ | |
1076 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ | |
1077 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ | |
1078 | |
1079 /* TPI Integration Mode Control Register Definitions */ | |
1080 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ | |
1081 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ | |
1082 | |
1083 /* TPI DEVID Register Definitions */ | |
1084 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ | |
1085 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ | |
1086 | |
1087 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ | |
1088 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ | |
1089 | |
1090 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ | |
1091 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ | |
1092 | |
1093 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ | |
1094 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ | |
1095 | |
1096 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ | |
1097 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ | |
1098 | |
1099 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ | |
1100 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ | |
1101 | |
1102 /* TPI DEVTYPE Register Definitions */ | |
1103 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ | |
1104 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ | |
1105 | |
1106 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ | |
1107 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ | |
1108 | |
1109 /*@}*/ /* end of group CMSIS_TPI */ | |
1110 | |
1111 | |
1112 #if (__MPU_PRESENT == 1U) | |
1113 /** | |
1114 \ingroup CMSIS_core_register | |
1115 \defgroup CMSIS_MPU Memory Protection Unit (MPU) | |
1116 \brief Type definitions for the Memory Protection Unit (MPU) | |
1117 @{ | |
1118 */ | |
1119 | |
1120 /** | |
1121 \brief Structure type to access the Memory Protection Unit (MPU). | |
1122 */ | |
1123 typedef struct | |
1124 { | |
1125 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ | |
1126 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ | |
1127 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ | |
1128 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ | |
1129 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ | |
1130 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ | |
1131 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ | |
1132 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ | |
1133 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ | |
1134 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ | |
1135 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ | |
1136 } MPU_Type; | |
1137 | |
1138 /* MPU Type Register Definitions */ | |
1139 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ | |
1140 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ | |
1141 | |
1142 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ | |
1143 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ | |
1144 | |
1145 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ | |
1146 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ | |
1147 | |
1148 /* MPU Control Register Definitions */ | |
1149 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ | |
1150 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ | |
1151 | |
1152 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ | |
1153 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ | |
1154 | |
1155 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ | |
1156 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ | |
1157 | |
1158 /* MPU Region Number Register Definitions */ | |
1159 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ | |
1160 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ | |
1161 | |
1162 /* MPU Region Base Address Register Definitions */ | |
1163 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ | |
1164 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ | |
1165 | |
1166 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ | |
1167 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ | |
1168 | |
1169 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ | |
1170 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ | |
1171 | |
1172 /* MPU Region Attribute and Size Register Definitions */ | |
1173 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ | |
1174 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ | |
1175 | |
1176 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ | |
1177 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ | |
1178 | |
1179 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ | |
1180 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ | |
1181 | |
1182 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ | |
1183 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ | |
1184 | |
1185 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ | |
1186 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ | |
1187 | |
1188 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ | |
1189 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ | |
1190 | |
1191 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ | |
1192 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ | |
1193 | |
1194 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ | |
1195 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ | |
1196 | |
1197 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ | |
1198 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ | |
1199 | |
1200 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ | |
1201 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ | |
1202 | |
1203 /*@} end of group CMSIS_MPU */ | |
1204 #endif | |
1205 | |
1206 | |
1207 /** | |
1208 \ingroup CMSIS_core_register | |
1209 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) | |
1210 \brief Type definitions for the Core Debug Registers | |
1211 @{ | |
1212 */ | |
1213 | |
1214 /** | |
1215 \brief Structure type to access the Core Debug Register (CoreDebug). | |
1216 */ | |
1217 typedef struct | |
1218 { | |
1219 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ | |
1220 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ | |
1221 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ | |
1222 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ | |
1223 } CoreDebug_Type; | |
1224 | |
1225 /* Debug Halting Control and Status Register Definitions */ | |
1226 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ | |
1227 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ | |
1228 | |
1229 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ | |
1230 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ | |
1231 | |
1232 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ | |
1233 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ | |
1234 | |
1235 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ | |
1236 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ | |
1237 | |
1238 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ | |
1239 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ | |
1240 | |
1241 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ | |
1242 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ | |
1243 | |
1244 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ | |
1245 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ | |
1246 | |
1247 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ | |
1248 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ | |
1249 | |
1250 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ | |
1251 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ | |
1252 | |
1253 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ | |
1254 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ | |
1255 | |
1256 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ | |
1257 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ | |
1258 | |
1259 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ | |
1260 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ | |
1261 | |
1262 /* Debug Core Register Selector Register Definitions */ | |
1263 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ | |
1264 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ | |
1265 | |
1266 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ | |
1267 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ | |
1268 | |
1269 /* Debug Exception and Monitor Control Register Definitions */ | |
1270 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ | |
1271 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ | |
1272 | |
1273 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ | |
1274 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ | |
1275 | |
1276 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ | |
1277 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ | |
1278 | |
1279 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ | |
1280 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ | |
1281 | |
1282 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ | |
1283 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ | |
1284 | |
1285 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ | |
1286 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ | |
1287 | |
1288 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ | |
1289 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ | |
1290 | |
1291 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ | |
1292 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ | |
1293 | |
1294 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ | |
1295 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ | |
1296 | |
1297 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ | |
1298 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ | |
1299 | |
1300 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ | |
1301 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ | |
1302 | |
1303 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ | |
1304 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ | |
1305 | |
1306 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ | |
1307 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ | |
1308 | |
1309 /*@} end of group CMSIS_CoreDebug */ | |
1310 | |
1311 | |
1312 /** | |
1313 \ingroup CMSIS_core_register | |
1314 \defgroup CMSIS_core_bitfield Core register bit field macros | |
1315 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). | |
1316 @{ | |
1317 */ | |
1318 | |
1319 /** | |
1320 \brief Mask and shift a bit field value for use in a register bit range. | |
1321 \param[in] field Name of the register bit field. | |
1322 \param[in] value Value of the bit field. | |
1323 \return Masked and shifted value. | |
1324 */ | |
1325 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) | |
1326 | |
1327 /** | |
1328 \brief Mask and shift a register value to extract a bit filed value. | |
1329 \param[in] field Name of the register bit field. | |
1330 \param[in] value Value of register. | |
1331 \return Masked and shifted bit field value. | |
1332 */ | |
1333 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) | |
1334 | |
1335 /*@} end of group CMSIS_core_bitfield */ | |
1336 | |
1337 | |
1338 /** | |
1339 \ingroup CMSIS_core_register | |
1340 \defgroup CMSIS_core_base Core Definitions | |
1341 \brief Definitions for base addresses, unions, and structures. | |
1342 @{ | |
1343 */ | |
1344 | |
1345 /* Memory mapping of Cortex-M3 Hardware */ | |
1346 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ | |
1347 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ | |
1348 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ | |
1349 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ | |
1350 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ | |
1351 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ | |
1352 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ | |
1353 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ | |
1354 | |
1355 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ | |
1356 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ | |
1357 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ | |
1358 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ | |
1359 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ | |
1360 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ | |
1361 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ | |
1362 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ | |
1363 | |
1364 #if (__MPU_PRESENT == 1U) | |
1365 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ | |
1366 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ | |
1367 #endif | |
1368 | |
1369 /*@} */ | |
1370 | |
1371 | |
1372 | |
1373 /******************************************************************************* | |
1374 * Hardware Abstraction Layer | |
1375 Core Function Interface contains: | |
1376 - Core NVIC Functions | |
1377 - Core SysTick Functions | |
1378 - Core Debug Functions | |
1379 - Core Register Access Functions | |
1380 ******************************************************************************/ | |
1381 /** | |
1382 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference | |
1383 */ | |
1384 | |
1385 | |
1386 | |
1387 /* ########################## NVIC functions #################################### */ | |
1388 /** | |
1389 \ingroup CMSIS_Core_FunctionInterface | |
1390 \defgroup CMSIS_Core_NVICFunctions NVIC Functions | |
1391 \brief Functions that manage interrupts and exceptions via the NVIC. | |
1392 @{ | |
1393 */ | |
1394 | |
1395 /** | |
1396 \brief Set Priority Grouping | |
1397 \details Sets the priority grouping field using the required unlock sequence. | |
1398 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. | |
1399 Only values from 0..7 are used. | |
1400 In case of a conflict between priority grouping and available | |
1401 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. | |
1402 \param [in] PriorityGroup Priority grouping field. | |
1403 */ | |
1404 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) | |
1405 { | |
1406 uint32_t reg_value; | |
1407 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ | |
1408 | |
1409 reg_value = SCB->AIRCR; /* read old register configuration */ | |
1410 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ | |
1411 reg_value = (reg_value | | |
1412 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | | |
1413 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ | |
1414 SCB->AIRCR = reg_value; | |
1415 } | |
1416 | |
1417 | |
1418 /** | |
1419 \brief Get Priority Grouping | |
1420 \details Reads the priority grouping field from the NVIC Interrupt Controller. | |
1421 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). | |
1422 */ | |
1423 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) | |
1424 { | |
1425 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); | |
1426 } | |
1427 | |
1428 | |
1429 /** | |
1430 \brief Enable External Interrupt | |
1431 \details Enables a device-specific interrupt in the NVIC interrupt controller. | |
1432 \param [in] IRQn External interrupt number. Value cannot be negative. | |
1433 */ | |
1434 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) | |
1435 { | |
1436 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); | |
1437 } | |
1438 | |
1439 | |
1440 /** | |
1441 \brief Disable External Interrupt | |
1442 \details Disables a device-specific interrupt in the NVIC interrupt controller. | |
1443 \param [in] IRQn External interrupt number. Value cannot be negative. | |
1444 */ | |
1445 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) | |
1446 { | |
1447 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); | |
1448 } | |
1449 | |
1450 | |
1451 /** | |
1452 \brief Get Pending Interrupt | |
1453 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. | |
1454 \param [in] IRQn Interrupt number. | |
1455 \return 0 Interrupt status is not pending. | |
1456 \return 1 Interrupt status is pending. | |
1457 */ | |
1458 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) | |
1459 { | |
1460 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); | |
1461 } | |
1462 | |
1463 | |
1464 /** | |
1465 \brief Set Pending Interrupt | |
1466 \details Sets the pending bit of an external interrupt. | |
1467 \param [in] IRQn Interrupt number. Value cannot be negative. | |
1468 */ | |
1469 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) | |
1470 { | |
1471 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); | |
1472 } | |
1473 | |
1474 | |
1475 /** | |
1476 \brief Clear Pending Interrupt | |
1477 \details Clears the pending bit of an external interrupt. | |
1478 \param [in] IRQn External interrupt number. Value cannot be negative. | |
1479 */ | |
1480 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) | |
1481 { | |
1482 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); | |
1483 } | |
1484 | |
1485 | |
1486 /** | |
1487 \brief Get Active Interrupt | |
1488 \details Reads the active register in NVIC and returns the active bit. | |
1489 \param [in] IRQn Interrupt number. | |
1490 \return 0 Interrupt status is not active. | |
1491 \return 1 Interrupt status is active. | |
1492 */ | |
1493 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) | |
1494 { | |
1495 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); | |
1496 } | |
1497 | |
1498 | |
1499 /** | |
1500 \brief Set Interrupt Priority | |
1501 \details Sets the priority of an interrupt. | |
1502 \note The priority cannot be set for every core interrupt. | |
1503 \param [in] IRQn Interrupt number. | |
1504 \param [in] priority Priority to set. | |
1505 */ | |
1506 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) | |
1507 { | |
1508 if ((int32_t)(IRQn) < 0) | |
1509 { | |
1510 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); | |
1511 } | |
1512 else | |
1513 { | |
1514 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); | |
1515 } | |
1516 } | |
1517 | |
1518 | |
1519 /** | |
1520 \brief Get Interrupt Priority | |
1521 \details Reads the priority of an interrupt. | |
1522 The interrupt number can be positive to specify an external (device specific) interrupt, | |
1523 or negative to specify an internal (core) interrupt. | |
1524 \param [in] IRQn Interrupt number. | |
1525 \return Interrupt Priority. | |
1526 Value is aligned automatically to the implemented priority bits of the microcontroller. | |
1527 */ | |
1528 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) | |
1529 { | |
1530 | |
1531 if ((int32_t)(IRQn) < 0) | |
1532 { | |
1533 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); | |
1534 } | |
1535 else | |
1536 { | |
1537 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); | |
1538 } | |
1539 } | |
1540 | |
1541 | |
1542 /** | |
1543 \brief Encode Priority | |
1544 \details Encodes the priority for an interrupt with the given priority group, | |
1545 preemptive priority value, and subpriority value. | |
1546 In case of a conflict between priority grouping and available | |
1547 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. | |
1548 \param [in] PriorityGroup Used priority group. | |
1549 \param [in] PreemptPriority Preemptive priority value (starting from 0). | |
1550 \param [in] SubPriority Subpriority value (starting from 0). | |
1551 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). | |
1552 */ | |
1553 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) | |
1554 { | |
1555 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ | |
1556 uint32_t PreemptPriorityBits; | |
1557 uint32_t SubPriorityBits; | |
1558 | |
1559 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); | |
1560 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); | |
1561 | |
1562 return ( | |
1563 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | | |
1564 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) | |
1565 ); | |
1566 } | |
1567 | |
1568 | |
1569 /** | |
1570 \brief Decode Priority | |
1571 \details Decodes an interrupt priority value with a given priority group to | |
1572 preemptive priority value and subpriority value. | |
1573 In case of a conflict between priority grouping and available | |
1574 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. | |
1575 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). | |
1576 \param [in] PriorityGroup Used priority group. | |
1577 \param [out] pPreemptPriority Preemptive priority value (starting from 0). | |
1578 \param [out] pSubPriority Subpriority value (starting from 0). | |
1579 */ | |
1580 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) | |
1581 { | |
1582 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ | |
1583 uint32_t PreemptPriorityBits; | |
1584 uint32_t SubPriorityBits; | |
1585 | |
1586 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); | |
1587 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); | |
1588 | |
1589 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); | |
1590 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); | |
1591 } | |
1592 | |
1593 | |
1594 /** | |
1595 \brief System Reset | |
1596 \details Initiates a system reset request to reset the MCU. | |
1597 */ | |
1598 __STATIC_INLINE void NVIC_SystemReset(void) | |
1599 { | |
1600 __DSB(); /* Ensure all outstanding memory accesses included | |
1601 buffered write are completed before reset */ | |
1602 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | | |
1603 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | | |
1604 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ | |
1605 __DSB(); /* Ensure completion of memory access */ | |
1606 | |
1607 for(;;) /* wait until reset */ | |
1608 { | |
1609 __NOP(); | |
1610 } | |
1611 } | |
1612 | |
1613 /*@} end of CMSIS_Core_NVICFunctions */ | |
1614 | |
1615 | |
1616 | |
1617 /* ################################## SysTick function ############################################ */ | |
1618 /** | |
1619 \ingroup CMSIS_Core_FunctionInterface | |
1620 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions | |
1621 \brief Functions that configure the System. | |
1622 @{ | |
1623 */ | |
1624 | |
1625 #if (__Vendor_SysTickConfig == 0U) | |
1626 | |
1627 /** | |
1628 \brief System Tick Configuration | |
1629 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. | |
1630 Counter is in free running mode to generate periodic interrupts. | |
1631 \param [in] ticks Number of ticks between two interrupts. | |
1632 \return 0 Function succeeded. | |
1633 \return 1 Function failed. | |
1634 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the | |
1635 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> | |
1636 must contain a vendor-specific implementation of this function. | |
1637 */ | |
1638 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) | |
1639 { | |
1640 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) | |
1641 { | |
1642 return (1UL); /* Reload value impossible */ | |
1643 } | |
1644 | |
1645 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ | |
1646 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ | |
1647 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ | |
1648 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | | |
1649 SysTick_CTRL_TICKINT_Msk | | |
1650 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ | |
1651 return (0UL); /* Function successful */ | |
1652 } | |
1653 | |
1654 #endif | |
1655 | |
1656 /*@} end of CMSIS_Core_SysTickFunctions */ | |
1657 | |
1658 | |
1659 | |
1660 /* ##################################### Debug In/Output function ########################################### */ | |
1661 /** | |
1662 \ingroup CMSIS_Core_FunctionInterface | |
1663 \defgroup CMSIS_core_DebugFunctions ITM Functions | |
1664 \brief Functions that access the ITM debug interface. | |
1665 @{ | |
1666 */ | |
1667 | |
1668 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ | |
1669 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ | |
1670 | |
1671 | |
1672 /** | |
1673 \brief ITM Send Character | |
1674 \details Transmits a character via the ITM channel 0, and | |
1675 \li Just returns when no debugger is connected that has booked the output. | |
1676 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. | |
1677 \param [in] ch Character to transmit. | |
1678 \returns Character to transmit. | |
1679 */ | |
1680 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) | |
1681 { | |
1682 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ | |
1683 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ | |
1684 { | |
1685 while (ITM->PORT[0U].u32 == 0UL) | |
1686 { | |
1687 __NOP(); | |
1688 } | |
1689 ITM->PORT[0U].u8 = (uint8_t)ch; | |
1690 } | |
1691 return (ch); | |
1692 } | |
1693 | |
1694 | |
1695 /** | |
1696 \brief ITM Receive Character | |
1697 \details Inputs a character via the external variable \ref ITM_RxBuffer. | |
1698 \return Received character. | |
1699 \return -1 No character pending. | |
1700 */ | |
1701 __STATIC_INLINE int32_t ITM_ReceiveChar (void) | |
1702 { | |
1703 int32_t ch = -1; /* no character available */ | |
1704 | |
1705 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) | |
1706 { | |
1707 ch = ITM_RxBuffer; | |
1708 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ | |
1709 } | |
1710 | |
1711 return (ch); | |
1712 } | |
1713 | |
1714 | |
1715 /** | |
1716 \brief ITM Check Character | |
1717 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. | |
1718 \return 0 No character available. | |
1719 \return 1 Character available. | |
1720 */ | |
1721 __STATIC_INLINE int32_t ITM_CheckChar (void) | |
1722 { | |
1723 | |
1724 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) | |
1725 { | |
1726 return (0); /* no character available */ | |
1727 } | |
1728 else | |
1729 { | |
1730 return (1); /* character available */ | |
1731 } | |
1732 } | |
1733 | |
1734 /*@} end of CMSIS_core_DebugFunctions */ | |
1735 | |
1736 | |
1737 | |
1738 | |
1739 #ifdef __cplusplus | |
1740 } | |
1741 #endif | |
1742 | |
1743 #endif /* __CORE_SC300_H_DEPENDANT */ | |
1744 | |
1745 #endif /* __CMSIS_GENERIC */ |