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author JeanDo
date Fri, 15 Dec 2017 02:06:18 +0100
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1 /**
2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 17-February-2017
7 * @brief - CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
8 * - This file is dedicated only for STM32F29 NUCLEO 144 boards.
9 *
10 * This file provides two functions and one global variable to be called from
11 * user application:
12 * - SystemInit(): This function is called at startup just after reset and
13 * before branch to main program. This call is made inside
14 * the "startup_stm32f4xx.s" file.
15 *
16 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
17 * by the user application to setup the SysTick
18 * timer or configure other parameters.
19 *
20 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
21 * be called whenever the core clock is changed
22 * during program execution.
23 *
24 *
25 ******************************************************************************
26 * @attention
27 *
28 * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
29 *
30 * Redistribution and use in source and binary forms, with or without modification,
31 * are permitted provided that the following conditions are met:
32 * 1. Redistributions of source code must retain the above copyright notice,
33 * this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following disclaimer in the documentation
36 * and/or other materials provided with the distribution.
37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 *
52 ******************************************************************************
53 */
54
55 /** @addtogroup CMSIS
56 * @{
57 */
58
59 /** @addtogroup stm32f4xx_system
60 * @{
61 */
62
63 /** @addtogroup STM32F4xx_System_Private_Includes
64 * @{
65 */
66
67
68 #include "stm32f4xx.h"
69
70 #if !defined (HSE_VALUE)
71 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
72 #endif /* HSE_VALUE */
73
74 #if !defined (HSI_VALUE)
75 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
76 #endif /* HSI_VALUE */
77
78 /**
79 * @}
80 */
81
82 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
83 * @{
84 */
85
86 /**
87 * @}
88 */
89
90 /** @addtogroup STM32F4xx_System_Private_Defines
91 * @{
92 */
93
94 /************************* Miscellaneous Configuration ************************/
95 /*!< Uncomment the following line if you need to relocate your vector Table in
96 Internal SRAM. */
97 /* #define VECT_TAB_SRAM */
98 #define VECT_TAB_OFFSET 0x40000 /*!< Vector Table base offset field.
99 This value must be a multiple of 0x200. */
100 /******************************************************************************/
101
102 /**
103 * @}
104 */
105
106 /** @addtogroup STM32F4xx_System_Private_Macros
107 * @{
108 */
109
110 /**
111 * @}
112 */
113
114 /** @addtogroup STM32F4xx_System_Private_Variables
115 * @{
116 */
117 /* This variable is updated in three ways:
118 1) by calling CMSIS function SystemCoreClockUpdate()
119 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
120 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
121 Note: If you use this function to configure the system clock; then there
122 is no need to call the 2 first functions listed above, since SystemCoreClock
123 variable is updated automatically.
124 */
125 uint32_t SystemCoreClock = 16000000;
126 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
127 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
128 /**
129 * @}
130 */
131
132
133 /** @addtogroup STM32F4xx_System_Private_Functions
134 * @{
135 */
136
137 /**
138 * @brief Setup the microcontroller system
139 * Initialize the FPU setting, vector table location and External memory
140 * configuration.
141 * @param None
142 * @retval None
143 */
144 void SystemInit(void)
145 {
146 /* FPU settings ------------------------------------------------------------*/
147 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
148 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
149 #endif
150 /* Reset the RCC clock configuration to the default reset state ------------*/
151 /* Set HSION bit */
152 RCC->CR |= (uint32_t)0x00000001;
153
154 /* Reset CFGR register */
155 RCC->CFGR = 0x00000000;
156
157 /* Reset HSEON, CSSON and PLLON bits */
158 RCC->CR &= (uint32_t)0xFEF6FFFF;
159
160 /* Reset PLLCFGR register */
161 RCC->PLLCFGR = 0x24003010;
162
163 /* Reset HSEBYP bit */
164 RCC->CR &= (uint32_t)0xFFFBFFFF;
165
166 /* Disable all interrupts */
167 RCC->CIR = 0x00000000;
168
169
170 /* Configure the Vector Table location add offset address ------------------*/
171 #ifdef VECT_TAB_SRAM
172 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
173 #else
174 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
175 #endif
176 }
177
178 /**
179 * @brief Update SystemCoreClock variable according to Clock Register Values.
180 * The SystemCoreClock variable contains the core clock (HCLK), it can
181 * be used by the user application to setup the SysTick timer or configure
182 * other parameters.
183 *
184 * @note Each time the core clock (HCLK) changes, this function must be called
185 * to update SystemCoreClock variable value. Otherwise, any configuration
186 * based on this variable will be incorrect.
187 *
188 * @note - The system frequency computed by this function is not the real
189 * frequency in the chip. It is calculated based on the predefined
190 * constant and the selected clock source:
191 *
192 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
193 *
194 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
195 *
196 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
197 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
198 *
199 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
200 * 16 MHz) but the real value may vary depending on the variations
201 * in voltage and temperature.
202 *
203 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
204 * depends on the application requirements), user has to ensure that HSE_VALUE
205 * is same as the real frequency of the crystal used. Otherwise, this function
206 * may have wrong result.
207 *
208 * - The result of this function could be not correct when using fractional
209 * value for HSE crystal.
210 *
211 * @param None
212 * @retval None
213 */
214 void SystemCoreClockUpdate(void)
215 {
216 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
217
218 /* Get SYSCLK source -------------------------------------------------------*/
219 tmp = RCC->CFGR & RCC_CFGR_SWS;
220
221 switch (tmp)
222 {
223 case 0x00: /* HSI used as system clock source */
224 SystemCoreClock = HSI_VALUE;
225 break;
226 case 0x04: /* HSE used as system clock source */
227 SystemCoreClock = HSE_VALUE;
228 break;
229 case 0x08: /* PLL used as system clock source */
230
231 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
232 SYSCLK = PLL_VCO / PLL_P
233 */
234 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
235 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
236
237 if (pllsource != 0)
238 {
239 /* HSE used as PLL clock source */
240 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
241 }
242 else
243 {
244 /* HSI used as PLL clock source */
245 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
246 }
247
248 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
249 SystemCoreClock = pllvco/pllp;
250 break;
251 default:
252 SystemCoreClock = HSI_VALUE;
253 break;
254 }
255 /* Compute HCLK frequency --------------------------------------------------*/
256 /* Get HCLK prescaler */
257 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
258 /* HCLK frequency */
259 SystemCoreClock >>= tmp;
260 }
261
262 /**
263 * @}
264 */
265
266 /**
267 * @}
268 */
269
270 /**
271 * @}
272 */
273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/