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comparison Small_CPU/Src/spi.c @ 85:923c4566a2a1 kittz

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increased interCPU baudrate, cpu2: i2c in SPI1 IRQ
author Dmitry Romanov <kitt@bk.ru>
date Wed, 21 Nov 2018 12:49:54 +0300
parents e6abbef57475
children 3db7389d49cc
comparison
equal deleted inserted replaced
84:e6abbef57475 85:923c4566a2a1
138 hspi1.Init.Direction = SPI_DIRECTION_2LINES; 138 hspi1.Init.Direction = SPI_DIRECTION_2LINES;
139 hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 139 hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
140 hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 140 hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
141 hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 141 hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
142 hspi1.Init.NSS = SPI_NSS_HARD_INPUT;//SPI_NSS_SOFT; 142 hspi1.Init.NSS = SPI_NSS_HARD_INPUT;//SPI_NSS_SOFT;
143 hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128; 143 hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
144 hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 144 hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
145 hspi1.Init.TIMode = SPI_TIMODE_DISABLED; 145 hspi1.Init.TIMode = SPI_TIMODE_DISABLED;
146 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;//_DISABLED; _ENABLED; 146 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;//_DISABLED; _ENABLED;
147 hspi1.Init.CRCPolynomial = 7; 147 hspi1.Init.CRCPolynomial = 7;
148 HAL_SPI_Init(&hspi1); 148 HAL_SPI_Init(&hspi1);
186 hdma_tx.Init.PeriphInc = DMA_PINC_DISABLE; 186 hdma_tx.Init.PeriphInc = DMA_PINC_DISABLE;
187 hdma_tx.Init.MemInc = DMA_MINC_ENABLE; 187 hdma_tx.Init.MemInc = DMA_MINC_ENABLE;
188 hdma_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 188 hdma_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
189 hdma_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 189 hdma_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
190 hdma_tx.Init.Mode = DMA_NORMAL; 190 hdma_tx.Init.Mode = DMA_NORMAL;
191 hdma_tx.Init.Priority = DMA_PRIORITY_LOW; 191 hdma_tx.Init.Priority = DMA_PRIORITY_VERY_HIGH;
192 hdma_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 192 hdma_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
193 hdma_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; 193 hdma_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
194 hdma_tx.Init.MemBurst = DMA_MBURST_INC4; 194 hdma_tx.Init.MemBurst = DMA_MBURST_INC4;
195 hdma_tx.Init.PeriphBurst = DMA_PBURST_INC4; 195 hdma_tx.Init.PeriphBurst = DMA_PBURST_INC4;
196 196
367 global.dataSendToSlaveIsValid = 0; 367 global.dataSendToSlaveIsValid = 0;
368 global.dataSendToSlaveIsNotValidCount++; 368 global.dataSendToSlaveIsNotValidCount++;
369 } 369 }
370 global.dataSendToMaster.power_on_reset = 0; 370 global.dataSendToMaster.power_on_reset = 0;
371 global.deviceDataSendToMaster.power_on_reset = 0; 371 global.deviceDataSendToMaster.power_on_reset = 0;
372 if(global.dataUpdateIsNeeded) 372 // if(global.dataUpdateIsNeeded)
373 { 373 // {
374 scheduleSpecial_Evaluate_DataSendToSlave(); 374 scheduleSpecial_Evaluate_DataSendToSlave();
375 global.dataUpdateIsNeeded=0; 375 // global.dataUpdateIsNeeded=0;
376 } 376 // }
377 SPI_Start_single_TxRx_with_Master(); 377 SPI_Start_single_TxRx_with_Master();
378 } 378 }
379 } 379 }
380 380
381 381