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author heinrichsweikamp
date Sat, 28 Apr 2018 11:52:34 +0200
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1 ///////////////////////////////////////////////////////////////////////////////
2 /// -*- coding: UTF-8 -*-
3 ///
4 /// \file Discovery/Src/system_stm32f4xx_special_plus_256k.c
5 /// \brief Manage system init and clocks.
6 /// \author Heinrichs Weikamp gmbh
7 /// \date 17-February-2017
8 ///
9 /// \details
10 /// From the CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
11 ///
12 /// This file provides two functions and one global variable to be called from
13 /// user application:
14 /// - SystemInit(): This function is called at startup just after reset and
15 /// before branch to main program. This call is made inside
16 /// the "startup_stm32f4xx.s" file.
17 ///
18 /// - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
19 /// by the user application to setup the SysTick
20 /// timer or configure other parameters.
21 ///
22 /// - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
23 /// be called whenever the core clock is changed
24 /// during program execution.
25 /// $Id$
26 ///////////////////////////////////////////////////////////////////////////////
27 /// \par Copyright (c) 2014-2018 Heinrichs Weikamp gmbh
28 ///
29 /// This program is free software: you can redistribute it and/or modify
30 /// it under the terms of the GNU General Public License as published by
31 /// the Free Software Foundation, either version 3 of the License, or
32 /// (at your option) any later version.
33 ///
34 /// This program is distributed in the hope that it will be useful,
35 /// but WITHOUT ANY WARRANTY; without even the implied warranty of
36 /// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 /// GNU General Public License for more details.
38 ///
39 /// You should have received a copy of the GNU General Public License
40 /// along with this program. If not, see <http://www.gnu.org/licenses/>.
41 //////////////////////////////////////////////////////////////////////////////
42 /// \par Copyright (c) 2017 STMicroelectronics
43 ///
44 /// Redistribution and use in source and binary forms, with or without modification,
45 /// are permitted provided that the following conditions are met:
46 /// 1. Redistributions of source code must retain the above copyright notice,
47 /// this list of conditions and the following disclaimer.
48 /// 2. Redistributions in binary form must reproduce the above copyright notice,
49 /// this list of conditions and the following disclaimer in the documentation
50 /// and/or other materials provided with the distribution.
51 /// 3. Neither the name of STMicroelectronics nor the names of its contributors
52 /// may be used to endorse or promote products derived from this software
53 /// without specific prior written permission.
54 ///
55 /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
56 /// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
57 /// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
58 /// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
59 /// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
60 /// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
61 /// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
62 /// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
63 /// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 /// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 //////////////////////////////////////////////////////////////////////////////
66
67 #include "stm32f4xx_hal.h"
68 #include "stm32f4xx.h"
69
70 #if !defined (HSE_VALUE)
71 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
72 #endif /* HSE_VALUE */
73
74 #if !defined (HSI_VALUE)
75 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
76 #endif /* HSI_VALUE */
77
78 /************************* Miscellaneous Configuration ************************/
79 /*!< Uncomment the following line if you need to relocate your vector Table in
80 Internal SRAM. */
81 /* #define VECT_TAB_SRAM */
82 #define VECT_TAB_OFFSET 0x40000 /*!< Vector Table base offset field.
83 This value must be a multiple of 0x200. */
84 /******************************************************************************/
85
86 /* This variable is updated in three ways:
87 1) by calling CMSIS function SystemCoreClockUpdate()
88 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
89 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
90 Note: If you use this function to configure the system clock; then there
91 is no need to call the 2 first functions listed above, since SystemCoreClock
92 variable is updated automatically.
93 */
94 uint32_t SystemCoreClock = 16000000;
95 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
96 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
97
98 /**
99 * @brief Setup the microcontroller system
100 * Initialize the FPU setting, vector table location and External memory
101 * configuration.
102 * @param None
103 * @retval None
104 */
105 void SystemInit(void)
106 {
107 /* FPU settings ------------------------------------------------------------*/
108 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
109 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
110 #endif
111 /* Reset the RCC clock configuration to the default reset state ------------*/
112 /* Set HSION bit */
113 RCC->CR |= (uint32_t)0x00000001;
114
115 /* Reset CFGR register */
116 RCC->CFGR = 0x00000000;
117
118 /* Reset HSEON, CSSON and PLLON bits */
119 RCC->CR &= (uint32_t)0xFEF6FFFF;
120
121 /* Reset PLLCFGR register */
122 RCC->PLLCFGR = 0x24003010;
123
124 /* Reset HSEBYP bit */
125 RCC->CR &= (uint32_t)0xFFFBFFFF;
126
127 /* Disable all interrupts */
128 RCC->CIR = 0x00000000;
129
130
131 /* Configure the Vector Table location add offset address ------------------*/
132 #ifdef VECT_TAB_SRAM
133 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
134 #else
135 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
136 #endif
137 }
138
139 /**
140 * @brief Update SystemCoreClock variable according to Clock Register Values.
141 * The SystemCoreClock variable contains the core clock (HCLK), it can
142 * be used by the user application to setup the SysTick timer or configure
143 * other parameters.
144 *
145 * @note Each time the core clock (HCLK) changes, this function must be called
146 * to update SystemCoreClock variable value. Otherwise, any configuration
147 * based on this variable will be incorrect.
148 *
149 * @note - The system frequency computed by this function is not the real
150 * frequency in the chip. It is calculated based on the predefined
151 * constant and the selected clock source:
152 *
153 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
154 *
155 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
156 *
157 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
158 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
159 *
160 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
161 * 16 MHz) but the real value may vary depending on the variations
162 * in voltage and temperature.
163 *
164 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
165 * depends on the application requirements), user has to ensure that HSE_VALUE
166 * is same as the real frequency of the crystal used. Otherwise, this function
167 * may have wrong result.
168 *
169 * - The result of this function could be not correct when using fractional
170 * value for HSE crystal.
171 *
172 * @param None
173 * @retval None
174 */
175 void SystemCoreClockUpdate(void)
176 {
177 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
178
179 /* Get SYSCLK source -------------------------------------------------------*/
180 tmp = RCC->CFGR & RCC_CFGR_SWS;
181
182 switch (tmp)
183 {
184 case 0x00: /* HSI used as system clock source */
185 SystemCoreClock = HSI_VALUE;
186 break;
187 case 0x04: /* HSE used as system clock source */
188 SystemCoreClock = HSE_VALUE;
189 break;
190 case 0x08: /* PLL used as system clock source */
191
192 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
193 SYSCLK = PLL_VCO / PLL_P
194 */
195 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
196 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
197
198 if (pllsource != 0)
199 {
200 /* HSE used as PLL clock source */
201 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
202 }
203 else
204 {
205 /* HSI used as PLL clock source */
206 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
207 }
208
209 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
210 SystemCoreClock = pllvco/pllp;
211 break;
212 default:
213 SystemCoreClock = HSI_VALUE;
214 break;
215 }
216 /* Compute HCLK frequency --------------------------------------------------*/
217 /* Get HCLK prescaler */
218 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
219 /* HCLK frequency */
220 SystemCoreClock >>= tmp;
221 }