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comparison Common/Drivers/STM32F4xx_v220/Source/Templates/gcc/startup_stm32f429xx.s @ 38:5f11787b4f42

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author heinrichsweikamp
date Sat, 28 Apr 2018 11:52:34 +0200
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37:ccc45c0e1ea2 38:5f11787b4f42
1 /**
2 ******************************************************************************
3 * @file startup_stm32f429xx.s
4 * @author MCD Application Team
5 * @version V2.2.0
6 * @date 15-December-2014
7 * @brief STM32F429xx Devices vector table for Atollic TrueSTUDIO toolchain.
8 * This module performs:
9 * - Set the initial SP
10 * - Set the initial PC == Reset_Handler,
11 * - Set the vector table entries with the exceptions ISR address
12 * - Branches to main in the C library (which eventually
13 * calls main()).
14 * After Reset the Cortex-M4 processor is in Thread mode,
15 * priority is Privileged, and the Stack is set to Main.
16 ******************************************************************************
17 * @attention
18 *
19 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
20 *
21 * Redistribution and use in source and binary forms, with or without modification,
22 * are permitted provided that the following conditions are met:
23 * 1. Redistributions of source code must retain the above copyright notice,
24 * this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials provided with the distribution.
28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ******************************************************************************
44 */
45
46 .syntax unified
47 .cpu cortex-m4
48 .fpu softvfp
49 .thumb
50
51 .global g_pfnVectors
52 .global Default_Handler
53
54 /* start address for the initialization values of the .data section.
55 defined in linker script */
56 .word _sidata
57 /* start address for the .data section. defined in linker script */
58 .word _sdata
59 /* end address for the .data section. defined in linker script */
60 .word _edata
61 /* start address for the .bss section. defined in linker script */
62 .word _sbss
63 /* end address for the .bss section. defined in linker script */
64 .word _ebss
65 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
66
67 /**
68 * @brief This is the code that gets called when the processor first
69 * starts execution following a reset event. Only the absolutely
70 * necessary set is performed, after which the application
71 * supplied main() routine is called.
72 * @param None
73 * @retval : None
74 */
75
76 .section .text.Reset_Handler
77 .weak Reset_Handler
78 .type Reset_Handler, %function
79 Reset_Handler:
80 ldr sp, =_estack /* set stack pointer */
81
82 /* Copy the data segment initializers from flash to SRAM */
83 movs r1, #0
84 b LoopCopyDataInit
85
86 CopyDataInit:
87 ldr r3, =_sidata
88 ldr r3, [r3, r1]
89 str r3, [r0, r1]
90 adds r1, r1, #4
91
92 LoopCopyDataInit:
93 ldr r0, =_sdata
94 ldr r3, =_edata
95 adds r2, r0, r1
96 cmp r2, r3
97 bcc CopyDataInit
98 ldr r2, =_sbss
99 b LoopFillZerobss
100 /* Zero fill the bss segment. */
101 FillZerobss:
102 movs r3, #0
103 str r3, [r2], #4
104
105 LoopFillZerobss:
106 ldr r3, = _ebss
107 cmp r2, r3
108 bcc FillZerobss
109
110 /* Call the clock system intitialization function.*/
111 bl SystemInit
112 /* Call static constructors */
113 bl __libc_init_array
114 /* Call the application's entry point.*/
115 bl main
116 bx lr
117 .size Reset_Handler, .-Reset_Handler
118
119 /**
120 * @brief This is the code that gets called when the processor receives an
121 * unexpected interrupt. This simply enters an infinite loop, preserving
122 * the system state for examination by a debugger.
123 * @param None
124 * @retval None
125 */
126 .section .text.Default_Handler,"ax",%progbits
127 Default_Handler:
128 Infinite_Loop:
129 b Infinite_Loop
130 .size Default_Handler, .-Default_Handler
131 /******************************************************************************
132 *
133 * The minimal vector table for a Cortex M3. Note that the proper constructs
134 * must be placed on this to ensure that it ends up at physical address
135 * 0x0000.0000.
136 *
137 *******************************************************************************/
138 .section .isr_vector,"a",%progbits
139 .type g_pfnVectors, %object
140 .size g_pfnVectors, .-g_pfnVectors
141
142 g_pfnVectors:
143 .word _estack
144 .word Reset_Handler
145
146 .word NMI_Handler
147 .word HardFault_Handler
148 .word MemManage_Handler
149 .word BusFault_Handler
150 .word UsageFault_Handler
151 .word 0
152 .word 0
153 .word 0
154 .word 0
155 .word SVC_Handler
156 .word DebugMon_Handler
157 .word 0
158 .word PendSV_Handler
159 .word SysTick_Handler
160
161 /* External Interrupts */
162 .word WWDG_IRQHandler /* Window WatchDog */
163 .word PVD_IRQHandler /* PVD through EXTI Line detection */
164 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
165 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
166 .word FLASH_IRQHandler /* FLASH */
167 .word RCC_IRQHandler /* RCC */
168 .word EXTI0_IRQHandler /* EXTI Line0 */
169 .word EXTI1_IRQHandler /* EXTI Line1 */
170 .word EXTI2_IRQHandler /* EXTI Line2 */
171 .word EXTI3_IRQHandler /* EXTI Line3 */
172 .word EXTI4_IRQHandler /* EXTI Line4 */
173 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
174 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
175 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
176 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
177 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
178 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
179 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
180 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
181 .word CAN1_TX_IRQHandler /* CAN1 TX */
182 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
183 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
184 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
185 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
186 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
187 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
188 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
189 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
190 .word TIM2_IRQHandler /* TIM2 */
191 .word TIM3_IRQHandler /* TIM3 */
192 .word TIM4_IRQHandler /* TIM4 */
193 .word I2C1_EV_IRQHandler /* I2C1 Event */
194 .word I2C1_ER_IRQHandler /* I2C1 Error */
195 .word I2C2_EV_IRQHandler /* I2C2 Event */
196 .word I2C2_ER_IRQHandler /* I2C2 Error */
197 .word SPI1_IRQHandler /* SPI1 */
198 .word SPI2_IRQHandler /* SPI2 */
199 .word USART1_IRQHandler /* USART1 */
200 .word USART2_IRQHandler /* USART2 */
201 .word USART3_IRQHandler /* USART3 */
202 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
203 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
204 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
205 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
206 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
207 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
208 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
209 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
210 .word FMC_IRQHandler /* FMC */
211 .word SDIO_IRQHandler /* SDIO */
212 .word TIM5_IRQHandler /* TIM5 */
213 .word SPI3_IRQHandler /* SPI3 */
214 .word UART4_IRQHandler /* UART4 */
215 .word UART5_IRQHandler /* UART5 */
216 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
217 .word TIM7_IRQHandler /* TIM7 */
218 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
219 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
220 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
221 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
222 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
223 .word ETH_IRQHandler /* Ethernet */
224 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
225 .word CAN2_TX_IRQHandler /* CAN2 TX */
226 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
227 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
228 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
229 .word OTG_FS_IRQHandler /* USB OTG FS */
230 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
231 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
232 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
233 .word USART6_IRQHandler /* USART6 */
234 .word I2C3_EV_IRQHandler /* I2C3 event */
235 .word I2C3_ER_IRQHandler /* I2C3 error */
236 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
237 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
238 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
239 .word OTG_HS_IRQHandler /* USB OTG HS */
240 .word DCMI_IRQHandler /* DCMI */
241 .word 0 /* Reserved */
242 .word HASH_RNG_IRQHandler /* Hash and Rng */
243 .word FPU_IRQHandler /* FPU */
244 .word UART7_IRQHandler /* UART7 */
245 .word UART8_IRQHandler /* UART8 */
246 .word SPI4_IRQHandler /* SPI4 */
247 .word SPI5_IRQHandler /* SPI5 */
248 .word SPI6_IRQHandler /* SPI6 */
249 .word SAI1_IRQHandler /* SAI1 */
250 .word LTDC_IRQHandler /* LTDC_IRQHandler */
251 .word LTDC_ER_IRQHandler /* LTDC_ER_IRQHandler */
252 .word DMA2D_IRQHandler /* DMA2D */
253
254 /*******************************************************************************
255 *
256 * Provide weak aliases for each Exception handler to the Default_Handler.
257 * As they are weak aliases, any function with the same name will override
258 * this definition.
259 *
260 *******************************************************************************/
261 .weak NMI_Handler
262 .thumb_set NMI_Handler,Default_Handler
263
264 .weak HardFault_Handler
265 .thumb_set HardFault_Handler,Default_Handler
266
267 .weak MemManage_Handler
268 .thumb_set MemManage_Handler,Default_Handler
269
270 .weak BusFault_Handler
271 .thumb_set BusFault_Handler,Default_Handler
272
273 .weak UsageFault_Handler
274 .thumb_set UsageFault_Handler,Default_Handler
275
276 .weak SVC_Handler
277 .thumb_set SVC_Handler,Default_Handler
278
279 .weak DebugMon_Handler
280 .thumb_set DebugMon_Handler,Default_Handler
281
282 .weak PendSV_Handler
283 .thumb_set PendSV_Handler,Default_Handler
284
285 .weak SysTick_Handler
286 .thumb_set SysTick_Handler,Default_Handler
287
288 .weak WWDG_IRQHandler
289 .thumb_set WWDG_IRQHandler,Default_Handler
290
291 .weak PVD_IRQHandler
292 .thumb_set PVD_IRQHandler,Default_Handler
293
294 .weak TAMP_STAMP_IRQHandler
295 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
296
297 .weak RTC_WKUP_IRQHandler
298 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
299
300 .weak FLASH_IRQHandler
301 .thumb_set FLASH_IRQHandler,Default_Handler
302
303 .weak RCC_IRQHandler
304 .thumb_set RCC_IRQHandler,Default_Handler
305
306 .weak EXTI0_IRQHandler
307 .thumb_set EXTI0_IRQHandler,Default_Handler
308
309 .weak EXTI1_IRQHandler
310 .thumb_set EXTI1_IRQHandler,Default_Handler
311
312 .weak EXTI2_IRQHandler
313 .thumb_set EXTI2_IRQHandler,Default_Handler
314
315 .weak EXTI3_IRQHandler
316 .thumb_set EXTI3_IRQHandler,Default_Handler
317
318 .weak EXTI4_IRQHandler
319 .thumb_set EXTI4_IRQHandler,Default_Handler
320
321 .weak DMA1_Stream0_IRQHandler
322 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
323
324 .weak DMA1_Stream1_IRQHandler
325 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
326
327 .weak DMA1_Stream2_IRQHandler
328 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
329
330 .weak DMA1_Stream3_IRQHandler
331 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
332
333 .weak DMA1_Stream4_IRQHandler
334 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
335
336 .weak DMA1_Stream5_IRQHandler
337 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
338
339 .weak DMA1_Stream6_IRQHandler
340 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
341
342 .weak ADC_IRQHandler
343 .thumb_set ADC_IRQHandler,Default_Handler
344
345 .weak CAN1_TX_IRQHandler
346 .thumb_set CAN1_TX_IRQHandler,Default_Handler
347
348 .weak CAN1_RX0_IRQHandler
349 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
350
351 .weak CAN1_RX1_IRQHandler
352 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
353
354 .weak CAN1_SCE_IRQHandler
355 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
356
357 .weak EXTI9_5_IRQHandler
358 .thumb_set EXTI9_5_IRQHandler,Default_Handler
359
360 .weak TIM1_BRK_TIM9_IRQHandler
361 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
362
363 .weak TIM1_UP_TIM10_IRQHandler
364 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
365
366 .weak TIM1_TRG_COM_TIM11_IRQHandler
367 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
368
369 .weak TIM1_CC_IRQHandler
370 .thumb_set TIM1_CC_IRQHandler,Default_Handler
371
372 .weak TIM2_IRQHandler
373 .thumb_set TIM2_IRQHandler,Default_Handler
374
375 .weak TIM3_IRQHandler
376 .thumb_set TIM3_IRQHandler,Default_Handler
377
378 .weak TIM4_IRQHandler
379 .thumb_set TIM4_IRQHandler,Default_Handler
380
381 .weak I2C1_EV_IRQHandler
382 .thumb_set I2C1_EV_IRQHandler,Default_Handler
383
384 .weak I2C1_ER_IRQHandler
385 .thumb_set I2C1_ER_IRQHandler,Default_Handler
386
387 .weak I2C2_EV_IRQHandler
388 .thumb_set I2C2_EV_IRQHandler,Default_Handler
389
390 .weak I2C2_ER_IRQHandler
391 .thumb_set I2C2_ER_IRQHandler,Default_Handler
392
393 .weak SPI1_IRQHandler
394 .thumb_set SPI1_IRQHandler,Default_Handler
395
396 .weak SPI2_IRQHandler
397 .thumb_set SPI2_IRQHandler,Default_Handler
398
399 .weak USART1_IRQHandler
400 .thumb_set USART1_IRQHandler,Default_Handler
401
402 .weak USART2_IRQHandler
403 .thumb_set USART2_IRQHandler,Default_Handler
404
405 .weak USART3_IRQHandler
406 .thumb_set USART3_IRQHandler,Default_Handler
407
408 .weak EXTI15_10_IRQHandler
409 .thumb_set EXTI15_10_IRQHandler,Default_Handler
410
411 .weak RTC_Alarm_IRQHandler
412 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
413
414 .weak OTG_FS_WKUP_IRQHandler
415 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
416
417 .weak TIM8_BRK_TIM12_IRQHandler
418 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
419
420 .weak TIM8_UP_TIM13_IRQHandler
421 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
422
423 .weak TIM8_TRG_COM_TIM14_IRQHandler
424 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
425
426 .weak TIM8_CC_IRQHandler
427 .thumb_set TIM8_CC_IRQHandler,Default_Handler
428
429 .weak DMA1_Stream7_IRQHandler
430 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
431
432 .weak FMC_IRQHandler
433 .thumb_set FMC_IRQHandler,Default_Handler
434
435 .weak SDIO_IRQHandler
436 .thumb_set SDIO_IRQHandler,Default_Handler
437
438 .weak TIM5_IRQHandler
439 .thumb_set TIM5_IRQHandler,Default_Handler
440
441 .weak SPI3_IRQHandler
442 .thumb_set SPI3_IRQHandler,Default_Handler
443
444 .weak UART4_IRQHandler
445 .thumb_set UART4_IRQHandler,Default_Handler
446
447 .weak UART5_IRQHandler
448 .thumb_set UART5_IRQHandler,Default_Handler
449
450 .weak TIM6_DAC_IRQHandler
451 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
452
453 .weak TIM7_IRQHandler
454 .thumb_set TIM7_IRQHandler,Default_Handler
455
456 .weak DMA2_Stream0_IRQHandler
457 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
458
459 .weak DMA2_Stream1_IRQHandler
460 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
461
462 .weak DMA2_Stream2_IRQHandler
463 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
464
465 .weak DMA2_Stream3_IRQHandler
466 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
467
468 .weak DMA2_Stream4_IRQHandler
469 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
470
471 .weak ETH_IRQHandler
472 .thumb_set ETH_IRQHandler,Default_Handler
473
474 .weak ETH_WKUP_IRQHandler
475 .thumb_set ETH_WKUP_IRQHandler,Default_Handler
476
477 .weak CAN2_TX_IRQHandler
478 .thumb_set CAN2_TX_IRQHandler,Default_Handler
479
480 .weak CAN2_RX0_IRQHandler
481 .thumb_set CAN2_RX0_IRQHandler,Default_Handler
482
483 .weak CAN2_RX1_IRQHandler
484 .thumb_set CAN2_RX1_IRQHandler,Default_Handler
485
486 .weak CAN2_SCE_IRQHandler
487 .thumb_set CAN2_SCE_IRQHandler,Default_Handler
488
489 .weak OTG_FS_IRQHandler
490 .thumb_set OTG_FS_IRQHandler,Default_Handler
491
492 .weak DMA2_Stream5_IRQHandler
493 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
494
495 .weak DMA2_Stream6_IRQHandler
496 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
497
498 .weak DMA2_Stream7_IRQHandler
499 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
500
501 .weak USART6_IRQHandler
502 .thumb_set USART6_IRQHandler,Default_Handler
503
504 .weak I2C3_EV_IRQHandler
505 .thumb_set I2C3_EV_IRQHandler,Default_Handler
506
507 .weak I2C3_ER_IRQHandler
508 .thumb_set I2C3_ER_IRQHandler,Default_Handler
509
510 .weak OTG_HS_EP1_OUT_IRQHandler
511 .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
512
513 .weak OTG_HS_EP1_IN_IRQHandler
514 .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
515
516 .weak OTG_HS_WKUP_IRQHandler
517 .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
518
519 .weak OTG_HS_IRQHandler
520 .thumb_set OTG_HS_IRQHandler,Default_Handler
521
522 .weak DCMI_IRQHandler
523 .thumb_set DCMI_IRQHandler,Default_Handler
524
525 .weak HASH_RNG_IRQHandler
526 .thumb_set HASH_RNG_IRQHandler,Default_Handler
527
528 .weak FPU_IRQHandler
529 .thumb_set FPU_IRQHandler,Default_Handler
530
531 .weak UART7_IRQHandler
532 .thumb_set UART7_IRQHandler,Default_Handler
533
534 .weak UART8_IRQHandler
535 .thumb_set UART8_IRQHandler,Default_Handler
536
537 .weak SPI4_IRQHandler
538 .thumb_set SPI4_IRQHandler,Default_Handler
539
540 .weak SPI5_IRQHandler
541 .thumb_set SPI5_IRQHandler,Default_Handler
542
543 .weak SPI6_IRQHandler
544 .thumb_set SPI6_IRQHandler,Default_Handler
545
546 .weak SAI1_IRQHandler
547 .thumb_set SAI1_IRQHandler,Default_Handler
548
549 .weak LTDC_IRQHandler
550 .thumb_set LTDC_IRQHandler,Default_Handler
551
552 .weak LTDC_ER_IRQHandler
553 .thumb_set LTDC_ER_IRQHandler,Default_Handler
554
555 .weak DMA2D_IRQHandler
556 .thumb_set DMA2D_IRQHandler,Default_Handler
557
558 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
559
560
561