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author heinrichsweikamp
date Sat, 28 Apr 2018 11:52:34 +0200
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1 /**
2 ******************************************************************************
3 * @file startup_stm32f407xx.s
4 * @author MCD Application Team
5 * @version V2.2.0
6 * @date 15-December-2014
7 * @brief STM32F407xx Devices vector table for Atollic TrueSTUDIO toolchain.
8 * This module performs:
9 * - Set the initial SP
10 * - Set the initial PC == Reset_Handler,
11 * - Set the vector table entries with the exceptions ISR address
12 * - Branches to main in the C library (which eventually
13 * calls main()).
14 * After Reset the Cortex-M4 processor is in Thread mode,
15 * priority is Privileged, and the Stack is set to Main.
16 ******************************************************************************
17 * @attention
18 *
19 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
20 *
21 * Redistribution and use in source and binary forms, with or without modification,
22 * are permitted provided that the following conditions are met:
23 * 1. Redistributions of source code must retain the above copyright notice,
24 * this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials provided with the distribution.
28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ******************************************************************************
44 */
45
46 .syntax unified
47 .cpu cortex-m4
48 .fpu softvfp
49 .thumb
50
51 .global g_pfnVectors
52 .global Default_Handler
53
54 /* start address for the initialization values of the .data section.
55 defined in linker script */
56 .word _sidata
57 /* start address for the .data section. defined in linker script */
58 .word _sdata
59 /* end address for the .data section. defined in linker script */
60 .word _edata
61 /* start address for the .bss section. defined in linker script */
62 .word _sbss
63 /* end address for the .bss section. defined in linker script */
64 .word _ebss
65 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
66
67 /**
68 * @brief This is the code that gets called when the processor first
69 * starts execution following a reset event. Only the absolutely
70 * necessary set is performed, after which the application
71 * supplied main() routine is called.
72 * @param None
73 * @retval : None
74 */
75
76 .section .text.Reset_Handler
77 .weak Reset_Handler
78 .type Reset_Handler, %function
79 Reset_Handler:
80 ldr sp, =_estack /* set stack pointer */
81
82 /* Copy the data segment initializers from flash to SRAM */
83 movs r1, #0
84 b LoopCopyDataInit
85
86 CopyDataInit:
87 ldr r3, =_sidata
88 ldr r3, [r3, r1]
89 str r3, [r0, r1]
90 adds r1, r1, #4
91
92 LoopCopyDataInit:
93 ldr r0, =_sdata
94 ldr r3, =_edata
95 adds r2, r0, r1
96 cmp r2, r3
97 bcc CopyDataInit
98 ldr r2, =_sbss
99 b LoopFillZerobss
100 /* Zero fill the bss segment. */
101 FillZerobss:
102 movs r3, #0
103 str r3, [r2], #4
104
105 LoopFillZerobss:
106 ldr r3, = _ebss
107 cmp r2, r3
108 bcc FillZerobss
109
110 /* Call the clock system intitialization function.*/
111 bl SystemInit
112 /* Call static constructors */
113 bl __libc_init_array
114 /* Call the application's entry point.*/
115 bl main
116 bx lr
117 .size Reset_Handler, .-Reset_Handler
118
119 /**
120 * @brief This is the code that gets called when the processor receives an
121 * unexpected interrupt. This simply enters an infinite loop, preserving
122 * the system state for examination by a debugger.
123 * @param None
124 * @retval None
125 */
126 .section .text.Default_Handler,"ax",%progbits
127 Default_Handler:
128 Infinite_Loop:
129 b Infinite_Loop
130 .size Default_Handler, .-Default_Handler
131 /******************************************************************************
132 *
133 * The minimal vector table for a Cortex M3. Note that the proper constructs
134 * must be placed on this to ensure that it ends up at physical address
135 * 0x0000.0000.
136 *
137 *******************************************************************************/
138 .section .isr_vector,"a",%progbits
139 .type g_pfnVectors, %object
140 .size g_pfnVectors, .-g_pfnVectors
141
142
143 g_pfnVectors:
144 .word _estack
145 .word Reset_Handler
146 .word NMI_Handler
147 .word HardFault_Handler
148 .word MemManage_Handler
149 .word BusFault_Handler
150 .word UsageFault_Handler
151 .word 0
152 .word 0
153 .word 0
154 .word 0
155 .word SVC_Handler
156 .word DebugMon_Handler
157 .word 0
158 .word PendSV_Handler
159 .word SysTick_Handler
160
161 /* External Interrupts */
162 .word WWDG_IRQHandler /* Window WatchDog */
163 .word PVD_IRQHandler /* PVD through EXTI Line detection */
164 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
165 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
166 .word FLASH_IRQHandler /* FLASH */
167 .word RCC_IRQHandler /* RCC */
168 .word EXTI0_IRQHandler /* EXTI Line0 */
169 .word EXTI1_IRQHandler /* EXTI Line1 */
170 .word EXTI2_IRQHandler /* EXTI Line2 */
171 .word EXTI3_IRQHandler /* EXTI Line3 */
172 .word EXTI4_IRQHandler /* EXTI Line4 */
173 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
174 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
175 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
176 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
177 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
178 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
179 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
180 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
181 .word CAN1_TX_IRQHandler /* CAN1 TX */
182 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
183 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
184 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
185 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
186 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
187 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
188 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
189 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
190 .word TIM2_IRQHandler /* TIM2 */
191 .word TIM3_IRQHandler /* TIM3 */
192 .word TIM4_IRQHandler /* TIM4 */
193 .word I2C1_EV_IRQHandler /* I2C1 Event */
194 .word I2C1_ER_IRQHandler /* I2C1 Error */
195 .word I2C2_EV_IRQHandler /* I2C2 Event */
196 .word I2C2_ER_IRQHandler /* I2C2 Error */
197 .word SPI1_IRQHandler /* SPI1 */
198 .word SPI2_IRQHandler /* SPI2 */
199 .word USART1_IRQHandler /* USART1 */
200 .word USART2_IRQHandler /* USART2 */
201 .word USART3_IRQHandler /* USART3 */
202 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
203 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
204 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
205 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
206 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
207 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
208 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
209 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
210 .word FSMC_IRQHandler /* FSMC */
211 .word SDIO_IRQHandler /* SDIO */
212 .word TIM5_IRQHandler /* TIM5 */
213 .word SPI3_IRQHandler /* SPI3 */
214 .word UART4_IRQHandler /* UART4 */
215 .word UART5_IRQHandler /* UART5 */
216 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
217 .word TIM7_IRQHandler /* TIM7 */
218 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
219 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
220 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
221 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
222 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
223 .word ETH_IRQHandler /* Ethernet */
224 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
225 .word CAN2_TX_IRQHandler /* CAN2 TX */
226 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
227 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
228 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
229 .word OTG_FS_IRQHandler /* USB OTG FS */
230 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
231 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
232 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
233 .word USART6_IRQHandler /* USART6 */
234 .word I2C3_EV_IRQHandler /* I2C3 event */
235 .word I2C3_ER_IRQHandler /* I2C3 error */
236 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
237 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
238 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
239 .word OTG_HS_IRQHandler /* USB OTG HS */
240 .word DCMI_IRQHandler /* DCMI */
241 .word 0 /* CRYP crypto */
242 .word HASH_RNG_IRQHandler /* Hash and Rng */
243 .word FPU_IRQHandler /* FPU */
244
245
246 /*******************************************************************************
247 *
248 * Provide weak aliases for each Exception handler to the Default_Handler.
249 * As they are weak aliases, any function with the same name will override
250 * this definition.
251 *
252 *******************************************************************************/
253 .weak NMI_Handler
254 .thumb_set NMI_Handler,Default_Handler
255
256 .weak HardFault_Handler
257 .thumb_set HardFault_Handler,Default_Handler
258
259 .weak MemManage_Handler
260 .thumb_set MemManage_Handler,Default_Handler
261
262 .weak BusFault_Handler
263 .thumb_set BusFault_Handler,Default_Handler
264
265 .weak UsageFault_Handler
266 .thumb_set UsageFault_Handler,Default_Handler
267
268 .weak SVC_Handler
269 .thumb_set SVC_Handler,Default_Handler
270
271 .weak DebugMon_Handler
272 .thumb_set DebugMon_Handler,Default_Handler
273
274 .weak PendSV_Handler
275 .thumb_set PendSV_Handler,Default_Handler
276
277 .weak SysTick_Handler
278 .thumb_set SysTick_Handler,Default_Handler
279
280 .weak WWDG_IRQHandler
281 .thumb_set WWDG_IRQHandler,Default_Handler
282
283 .weak PVD_IRQHandler
284 .thumb_set PVD_IRQHandler,Default_Handler
285
286 .weak TAMP_STAMP_IRQHandler
287 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
288
289 .weak RTC_WKUP_IRQHandler
290 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
291
292 .weak FLASH_IRQHandler
293 .thumb_set FLASH_IRQHandler,Default_Handler
294
295 .weak RCC_IRQHandler
296 .thumb_set RCC_IRQHandler,Default_Handler
297
298 .weak EXTI0_IRQHandler
299 .thumb_set EXTI0_IRQHandler,Default_Handler
300
301 .weak EXTI1_IRQHandler
302 .thumb_set EXTI1_IRQHandler,Default_Handler
303
304 .weak EXTI2_IRQHandler
305 .thumb_set EXTI2_IRQHandler,Default_Handler
306
307 .weak EXTI3_IRQHandler
308 .thumb_set EXTI3_IRQHandler,Default_Handler
309
310 .weak EXTI4_IRQHandler
311 .thumb_set EXTI4_IRQHandler,Default_Handler
312
313 .weak DMA1_Stream0_IRQHandler
314 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
315
316 .weak DMA1_Stream1_IRQHandler
317 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
318
319 .weak DMA1_Stream2_IRQHandler
320 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
321
322 .weak DMA1_Stream3_IRQHandler
323 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
324
325 .weak DMA1_Stream4_IRQHandler
326 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
327
328 .weak DMA1_Stream5_IRQHandler
329 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
330
331 .weak DMA1_Stream6_IRQHandler
332 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
333
334 .weak ADC_IRQHandler
335 .thumb_set ADC_IRQHandler,Default_Handler
336
337 .weak CAN1_TX_IRQHandler
338 .thumb_set CAN1_TX_IRQHandler,Default_Handler
339
340 .weak CAN1_RX0_IRQHandler
341 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
342
343 .weak CAN1_RX1_IRQHandler
344 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
345
346 .weak CAN1_SCE_IRQHandler
347 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
348
349 .weak EXTI9_5_IRQHandler
350 .thumb_set EXTI9_5_IRQHandler,Default_Handler
351
352 .weak TIM1_BRK_TIM9_IRQHandler
353 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
354
355 .weak TIM1_UP_TIM10_IRQHandler
356 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
357
358 .weak TIM1_TRG_COM_TIM11_IRQHandler
359 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
360
361 .weak TIM1_CC_IRQHandler
362 .thumb_set TIM1_CC_IRQHandler,Default_Handler
363
364 .weak TIM2_IRQHandler
365 .thumb_set TIM2_IRQHandler,Default_Handler
366
367 .weak TIM3_IRQHandler
368 .thumb_set TIM3_IRQHandler,Default_Handler
369
370 .weak TIM4_IRQHandler
371 .thumb_set TIM4_IRQHandler,Default_Handler
372
373 .weak I2C1_EV_IRQHandler
374 .thumb_set I2C1_EV_IRQHandler,Default_Handler
375
376 .weak I2C1_ER_IRQHandler
377 .thumb_set I2C1_ER_IRQHandler,Default_Handler
378
379 .weak I2C2_EV_IRQHandler
380 .thumb_set I2C2_EV_IRQHandler,Default_Handler
381
382 .weak I2C2_ER_IRQHandler
383 .thumb_set I2C2_ER_IRQHandler,Default_Handler
384
385 .weak SPI1_IRQHandler
386 .thumb_set SPI1_IRQHandler,Default_Handler
387
388 .weak SPI2_IRQHandler
389 .thumb_set SPI2_IRQHandler,Default_Handler
390
391 .weak USART1_IRQHandler
392 .thumb_set USART1_IRQHandler,Default_Handler
393
394 .weak USART2_IRQHandler
395 .thumb_set USART2_IRQHandler,Default_Handler
396
397 .weak USART3_IRQHandler
398 .thumb_set USART3_IRQHandler,Default_Handler
399
400 .weak EXTI15_10_IRQHandler
401 .thumb_set EXTI15_10_IRQHandler,Default_Handler
402
403 .weak RTC_Alarm_IRQHandler
404 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
405
406 .weak OTG_FS_WKUP_IRQHandler
407 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
408
409 .weak TIM8_BRK_TIM12_IRQHandler
410 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
411
412 .weak TIM8_UP_TIM13_IRQHandler
413 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
414
415 .weak TIM8_TRG_COM_TIM14_IRQHandler
416 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
417
418 .weak TIM8_CC_IRQHandler
419 .thumb_set TIM8_CC_IRQHandler,Default_Handler
420
421 .weak DMA1_Stream7_IRQHandler
422 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
423
424 .weak FSMC_IRQHandler
425 .thumb_set FSMC_IRQHandler,Default_Handler
426
427 .weak SDIO_IRQHandler
428 .thumb_set SDIO_IRQHandler,Default_Handler
429
430 .weak TIM5_IRQHandler
431 .thumb_set TIM5_IRQHandler,Default_Handler
432
433 .weak SPI3_IRQHandler
434 .thumb_set SPI3_IRQHandler,Default_Handler
435
436 .weak UART4_IRQHandler
437 .thumb_set UART4_IRQHandler,Default_Handler
438
439 .weak UART5_IRQHandler
440 .thumb_set UART5_IRQHandler,Default_Handler
441
442 .weak TIM6_DAC_IRQHandler
443 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
444
445 .weak TIM7_IRQHandler
446 .thumb_set TIM7_IRQHandler,Default_Handler
447
448 .weak DMA2_Stream0_IRQHandler
449 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
450
451 .weak DMA2_Stream1_IRQHandler
452 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
453
454 .weak DMA2_Stream2_IRQHandler
455 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
456
457 .weak DMA2_Stream3_IRQHandler
458 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
459
460 .weak DMA2_Stream4_IRQHandler
461 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
462
463 .weak ETH_IRQHandler
464 .thumb_set ETH_IRQHandler,Default_Handler
465
466 .weak ETH_WKUP_IRQHandler
467 .thumb_set ETH_WKUP_IRQHandler,Default_Handler
468
469 .weak CAN2_TX_IRQHandler
470 .thumb_set CAN2_TX_IRQHandler,Default_Handler
471
472 .weak CAN2_RX0_IRQHandler
473 .thumb_set CAN2_RX0_IRQHandler,Default_Handler
474
475 .weak CAN2_RX1_IRQHandler
476 .thumb_set CAN2_RX1_IRQHandler,Default_Handler
477
478 .weak CAN2_SCE_IRQHandler
479 .thumb_set CAN2_SCE_IRQHandler,Default_Handler
480
481 .weak OTG_FS_IRQHandler
482 .thumb_set OTG_FS_IRQHandler,Default_Handler
483
484 .weak DMA2_Stream5_IRQHandler
485 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
486
487 .weak DMA2_Stream6_IRQHandler
488 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
489
490 .weak DMA2_Stream7_IRQHandler
491 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
492
493 .weak USART6_IRQHandler
494 .thumb_set USART6_IRQHandler,Default_Handler
495
496 .weak I2C3_EV_IRQHandler
497 .thumb_set I2C3_EV_IRQHandler,Default_Handler
498
499 .weak I2C3_ER_IRQHandler
500 .thumb_set I2C3_ER_IRQHandler,Default_Handler
501
502 .weak OTG_HS_EP1_OUT_IRQHandler
503 .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
504
505 .weak OTG_HS_EP1_IN_IRQHandler
506 .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
507
508 .weak OTG_HS_WKUP_IRQHandler
509 .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
510
511 .weak OTG_HS_IRQHandler
512 .thumb_set OTG_HS_IRQHandler,Default_Handler
513
514 .weak DCMI_IRQHandler
515 .thumb_set DCMI_IRQHandler,Default_Handler
516
517 .weak HASH_RNG_IRQHandler
518 .thumb_set HASH_RNG_IRQHandler,Default_Handler
519
520 .weak FPU_IRQHandler
521 .thumb_set FPU_IRQHandler,Default_Handler
522
523 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/