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comparison Common/Drivers/STM32F4xx_v220/Source/Templates/arm/startup_stm32f437xx.s @ 38:5f11787b4f42

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author heinrichsweikamp
date Sat, 28 Apr 2018 11:52:34 +0200
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1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
2 ;* File Name : startup_stm32f437xx.s
3 ;* Author : MCD Application Team
4 ;* Version : V2.2.0
5 ;* Date : 15-December-2014
6 ;* Description : STM32F437x devices vector table for MDK-ARM toolchain.
7 ;* This module performs:
8 ;* - Set the initial SP
9 ;* - Set the initial PC == Reset_Handler
10 ;* - Set the vector table entries with the exceptions ISR address
11 ;* - Branches to __main in the C library (which eventually
12 ;* calls main()).
13 ;* After Reset the CortexM4 processor is in Thread mode,
14 ;* priority is Privileged, and the Stack is set to Main.
15 ;* <<< Use Configuration Wizard in Context Menu >>>
16 ;*******************************************************************************
17 ;
18 ;* Redistribution and use in source and binary forms, with or without modification,
19 ;* are permitted provided that the following conditions are met:
20 ;* 1. Redistributions of source code must retain the above copyright notice,
21 ;* this list of conditions and the following disclaimer.
22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
23 ;* this list of conditions and the following disclaimer in the documentation
24 ;* and/or other materials provided with the distribution.
25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
26 ;* may be used to endorse or promote products derived from this software
27 ;* without specific prior written permission.
28 ;*
29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 ;
40 ;*******************************************************************************
41
42 ; Amount of memory (in bytes) allocated for Stack
43 ; Tailor this value to your application needs
44 ; <h> Stack Configuration
45 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
46 ; </h>
47
48 Stack_Size EQU 0x00000400
49
50 AREA STACK, NOINIT, READWRITE, ALIGN=3
51 Stack_Mem SPACE Stack_Size
52 __initial_sp
53
54
55 ; <h> Heap Configuration
56 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
57 ; </h>
58
59 Heap_Size EQU 0x00000200
60
61 AREA HEAP, NOINIT, READWRITE, ALIGN=3
62 __heap_base
63 Heap_Mem SPACE Heap_Size
64 __heap_limit
65
66 PRESERVE8
67 THUMB
68
69
70 ; Vector Table Mapped to Address 0 at Reset
71 AREA RESET, DATA, READONLY
72 EXPORT __Vectors
73 EXPORT __Vectors_End
74 EXPORT __Vectors_Size
75
76 __Vectors DCD __initial_sp ; Top of Stack
77 DCD Reset_Handler ; Reset Handler
78 DCD NMI_Handler ; NMI Handler
79 DCD HardFault_Handler ; Hard Fault Handler
80 DCD MemManage_Handler ; MPU Fault Handler
81 DCD BusFault_Handler ; Bus Fault Handler
82 DCD UsageFault_Handler ; Usage Fault Handler
83 DCD 0 ; Reserved
84 DCD 0 ; Reserved
85 DCD 0 ; Reserved
86 DCD 0 ; Reserved
87 DCD SVC_Handler ; SVCall Handler
88 DCD DebugMon_Handler ; Debug Monitor Handler
89 DCD 0 ; Reserved
90 DCD PendSV_Handler ; PendSV Handler
91 DCD SysTick_Handler ; SysTick Handler
92
93 ; External Interrupts
94 DCD WWDG_IRQHandler ; Window WatchDog
95 DCD PVD_IRQHandler ; PVD through EXTI Line detection
96 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
97 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
98 DCD FLASH_IRQHandler ; FLASH
99 DCD RCC_IRQHandler ; RCC
100 DCD EXTI0_IRQHandler ; EXTI Line0
101 DCD EXTI1_IRQHandler ; EXTI Line1
102 DCD EXTI2_IRQHandler ; EXTI Line2
103 DCD EXTI3_IRQHandler ; EXTI Line3
104 DCD EXTI4_IRQHandler ; EXTI Line4
105 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
106 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
107 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
108 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
109 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
110 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
111 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
112 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
113 DCD CAN1_TX_IRQHandler ; CAN1 TX
114 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
115 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
116 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
117 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
118 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
119 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
120 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
121 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
122 DCD TIM2_IRQHandler ; TIM2
123 DCD TIM3_IRQHandler ; TIM3
124 DCD TIM4_IRQHandler ; TIM4
125 DCD I2C1_EV_IRQHandler ; I2C1 Event
126 DCD I2C1_ER_IRQHandler ; I2C1 Error
127 DCD I2C2_EV_IRQHandler ; I2C2 Event
128 DCD I2C2_ER_IRQHandler ; I2C2 Error
129 DCD SPI1_IRQHandler ; SPI1
130 DCD SPI2_IRQHandler ; SPI2
131 DCD USART1_IRQHandler ; USART1
132 DCD USART2_IRQHandler ; USART2
133 DCD USART3_IRQHandler ; USART3
134 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
135 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
136 DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
137 DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
138 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
139 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
140 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
141 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
142 DCD FMC_IRQHandler ; FMC
143 DCD SDIO_IRQHandler ; SDIO
144 DCD TIM5_IRQHandler ; TIM5
145 DCD SPI3_IRQHandler ; SPI3
146 DCD UART4_IRQHandler ; UART4
147 DCD UART5_IRQHandler ; UART5
148 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
149 DCD TIM7_IRQHandler ; TIM7
150 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
151 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
152 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
153 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
154 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
155 DCD ETH_IRQHandler ; Ethernet
156 DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
157 DCD CAN2_TX_IRQHandler ; CAN2 TX
158 DCD CAN2_RX0_IRQHandler ; CAN2 RX0
159 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
160 DCD CAN2_SCE_IRQHandler ; CAN2 SCE
161 DCD OTG_FS_IRQHandler ; USB OTG FS
162 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
163 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
164 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
165 DCD USART6_IRQHandler ; USART6
166 DCD I2C3_EV_IRQHandler ; I2C3 event
167 DCD I2C3_ER_IRQHandler ; I2C3 error
168 DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
169 DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
170 DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
171 DCD OTG_HS_IRQHandler ; USB OTG HS
172 DCD DCMI_IRQHandler ; DCMI
173 DCD CRYP_IRQHandler ; CRYPTO
174 DCD HASH_RNG_IRQHandler ; Hash and Rng
175 DCD FPU_IRQHandler ; FPU
176 DCD UART7_IRQHandler ; UART7
177 DCD UART8_IRQHandler ; UART8
178 DCD SPI4_IRQHandler ; SPI4
179 DCD SPI5_IRQHandler ; SPI5
180 DCD SPI6_IRQHandler ; SPI6
181 DCD SAI1_IRQHandler ; SAI1
182 DCD 0 ; Reserved
183 DCD 0 ; Reserved
184 DCD DMA2D_IRQHandler ; DMA2D
185
186 __Vectors_End
187
188 __Vectors_Size EQU __Vectors_End - __Vectors
189
190 AREA |.text|, CODE, READONLY
191
192 ; Reset handler
193 Reset_Handler PROC
194 EXPORT Reset_Handler [WEAK]
195 IMPORT SystemInit
196 IMPORT __main
197
198 LDR R0, =SystemInit
199 BLX R0
200 LDR R0, =__main
201 BX R0
202 ENDP
203
204 ; Dummy Exception Handlers (infinite loops which can be modified)
205
206 NMI_Handler PROC
207 EXPORT NMI_Handler [WEAK]
208 B .
209 ENDP
210 HardFault_Handler\
211 PROC
212 EXPORT HardFault_Handler [WEAK]
213 B .
214 ENDP
215 MemManage_Handler\
216 PROC
217 EXPORT MemManage_Handler [WEAK]
218 B .
219 ENDP
220 BusFault_Handler\
221 PROC
222 EXPORT BusFault_Handler [WEAK]
223 B .
224 ENDP
225 UsageFault_Handler\
226 PROC
227 EXPORT UsageFault_Handler [WEAK]
228 B .
229 ENDP
230 SVC_Handler PROC
231 EXPORT SVC_Handler [WEAK]
232 B .
233 ENDP
234 DebugMon_Handler\
235 PROC
236 EXPORT DebugMon_Handler [WEAK]
237 B .
238 ENDP
239 PendSV_Handler PROC
240 EXPORT PendSV_Handler [WEAK]
241 B .
242 ENDP
243 SysTick_Handler PROC
244 EXPORT SysTick_Handler [WEAK]
245 B .
246 ENDP
247
248 Default_Handler PROC
249
250 EXPORT WWDG_IRQHandler [WEAK]
251 EXPORT PVD_IRQHandler [WEAK]
252 EXPORT TAMP_STAMP_IRQHandler [WEAK]
253 EXPORT RTC_WKUP_IRQHandler [WEAK]
254 EXPORT FLASH_IRQHandler [WEAK]
255 EXPORT RCC_IRQHandler [WEAK]
256 EXPORT EXTI0_IRQHandler [WEAK]
257 EXPORT EXTI1_IRQHandler [WEAK]
258 EXPORT EXTI2_IRQHandler [WEAK]
259 EXPORT EXTI3_IRQHandler [WEAK]
260 EXPORT EXTI4_IRQHandler [WEAK]
261 EXPORT DMA1_Stream0_IRQHandler [WEAK]
262 EXPORT DMA1_Stream1_IRQHandler [WEAK]
263 EXPORT DMA1_Stream2_IRQHandler [WEAK]
264 EXPORT DMA1_Stream3_IRQHandler [WEAK]
265 EXPORT DMA1_Stream4_IRQHandler [WEAK]
266 EXPORT DMA1_Stream5_IRQHandler [WEAK]
267 EXPORT DMA1_Stream6_IRQHandler [WEAK]
268 EXPORT ADC_IRQHandler [WEAK]
269 EXPORT CAN1_TX_IRQHandler [WEAK]
270 EXPORT CAN1_RX0_IRQHandler [WEAK]
271 EXPORT CAN1_RX1_IRQHandler [WEAK]
272 EXPORT CAN1_SCE_IRQHandler [WEAK]
273 EXPORT EXTI9_5_IRQHandler [WEAK]
274 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
275 EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
276 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
277 EXPORT TIM1_CC_IRQHandler [WEAK]
278 EXPORT TIM2_IRQHandler [WEAK]
279 EXPORT TIM3_IRQHandler [WEAK]
280 EXPORT TIM4_IRQHandler [WEAK]
281 EXPORT I2C1_EV_IRQHandler [WEAK]
282 EXPORT I2C1_ER_IRQHandler [WEAK]
283 EXPORT I2C2_EV_IRQHandler [WEAK]
284 EXPORT I2C2_ER_IRQHandler [WEAK]
285 EXPORT SPI1_IRQHandler [WEAK]
286 EXPORT SPI2_IRQHandler [WEAK]
287 EXPORT USART1_IRQHandler [WEAK]
288 EXPORT USART2_IRQHandler [WEAK]
289 EXPORT USART3_IRQHandler [WEAK]
290 EXPORT EXTI15_10_IRQHandler [WEAK]
291 EXPORT RTC_Alarm_IRQHandler [WEAK]
292 EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
293 EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
294 EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
295 EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
296 EXPORT TIM8_CC_IRQHandler [WEAK]
297 EXPORT DMA1_Stream7_IRQHandler [WEAK]
298 EXPORT FMC_IRQHandler [WEAK]
299 EXPORT SDIO_IRQHandler [WEAK]
300 EXPORT TIM5_IRQHandler [WEAK]
301 EXPORT SPI3_IRQHandler [WEAK]
302 EXPORT UART4_IRQHandler [WEAK]
303 EXPORT UART5_IRQHandler [WEAK]
304 EXPORT TIM6_DAC_IRQHandler [WEAK]
305 EXPORT TIM7_IRQHandler [WEAK]
306 EXPORT DMA2_Stream0_IRQHandler [WEAK]
307 EXPORT DMA2_Stream1_IRQHandler [WEAK]
308 EXPORT DMA2_Stream2_IRQHandler [WEAK]
309 EXPORT DMA2_Stream3_IRQHandler [WEAK]
310 EXPORT DMA2_Stream4_IRQHandler [WEAK]
311 EXPORT ETH_IRQHandler [WEAK]
312 EXPORT ETH_WKUP_IRQHandler [WEAK]
313 EXPORT CAN2_TX_IRQHandler [WEAK]
314 EXPORT CAN2_RX0_IRQHandler [WEAK]
315 EXPORT CAN2_RX1_IRQHandler [WEAK]
316 EXPORT CAN2_SCE_IRQHandler [WEAK]
317 EXPORT OTG_FS_IRQHandler [WEAK]
318 EXPORT DMA2_Stream5_IRQHandler [WEAK]
319 EXPORT DMA2_Stream6_IRQHandler [WEAK]
320 EXPORT DMA2_Stream7_IRQHandler [WEAK]
321 EXPORT USART6_IRQHandler [WEAK]
322 EXPORT I2C3_EV_IRQHandler [WEAK]
323 EXPORT I2C3_ER_IRQHandler [WEAK]
324 EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
325 EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
326 EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
327 EXPORT OTG_HS_IRQHandler [WEAK]
328 EXPORT DCMI_IRQHandler [WEAK]
329 EXPORT CRYP_IRQHandler [WEAK]
330 EXPORT HASH_RNG_IRQHandler [WEAK]
331 EXPORT FPU_IRQHandler [WEAK]
332 EXPORT UART7_IRQHandler [WEAK]
333 EXPORT UART8_IRQHandler [WEAK]
334 EXPORT SPI4_IRQHandler [WEAK]
335 EXPORT SPI5_IRQHandler [WEAK]
336 EXPORT SPI6_IRQHandler [WEAK]
337 EXPORT SAI1_IRQHandler [WEAK]
338 EXPORT DMA2D_IRQHandler [WEAK]
339
340 WWDG_IRQHandler
341 PVD_IRQHandler
342 TAMP_STAMP_IRQHandler
343 RTC_WKUP_IRQHandler
344 FLASH_IRQHandler
345 RCC_IRQHandler
346 EXTI0_IRQHandler
347 EXTI1_IRQHandler
348 EXTI2_IRQHandler
349 EXTI3_IRQHandler
350 EXTI4_IRQHandler
351 DMA1_Stream0_IRQHandler
352 DMA1_Stream1_IRQHandler
353 DMA1_Stream2_IRQHandler
354 DMA1_Stream3_IRQHandler
355 DMA1_Stream4_IRQHandler
356 DMA1_Stream5_IRQHandler
357 DMA1_Stream6_IRQHandler
358 ADC_IRQHandler
359 CAN1_TX_IRQHandler
360 CAN1_RX0_IRQHandler
361 CAN1_RX1_IRQHandler
362 CAN1_SCE_IRQHandler
363 EXTI9_5_IRQHandler
364 TIM1_BRK_TIM9_IRQHandler
365 TIM1_UP_TIM10_IRQHandler
366 TIM1_TRG_COM_TIM11_IRQHandler
367 TIM1_CC_IRQHandler
368 TIM2_IRQHandler
369 TIM3_IRQHandler
370 TIM4_IRQHandler
371 I2C1_EV_IRQHandler
372 I2C1_ER_IRQHandler
373 I2C2_EV_IRQHandler
374 I2C2_ER_IRQHandler
375 SPI1_IRQHandler
376 SPI2_IRQHandler
377 USART1_IRQHandler
378 USART2_IRQHandler
379 USART3_IRQHandler
380 EXTI15_10_IRQHandler
381 RTC_Alarm_IRQHandler
382 OTG_FS_WKUP_IRQHandler
383 TIM8_BRK_TIM12_IRQHandler
384 TIM8_UP_TIM13_IRQHandler
385 TIM8_TRG_COM_TIM14_IRQHandler
386 TIM8_CC_IRQHandler
387 DMA1_Stream7_IRQHandler
388 FMC_IRQHandler
389 SDIO_IRQHandler
390 TIM5_IRQHandler
391 SPI3_IRQHandler
392 UART4_IRQHandler
393 UART5_IRQHandler
394 TIM6_DAC_IRQHandler
395 TIM7_IRQHandler
396 DMA2_Stream0_IRQHandler
397 DMA2_Stream1_IRQHandler
398 DMA2_Stream2_IRQHandler
399 DMA2_Stream3_IRQHandler
400 DMA2_Stream4_IRQHandler
401 ETH_IRQHandler
402 ETH_WKUP_IRQHandler
403 CAN2_TX_IRQHandler
404 CAN2_RX0_IRQHandler
405 CAN2_RX1_IRQHandler
406 CAN2_SCE_IRQHandler
407 OTG_FS_IRQHandler
408 DMA2_Stream5_IRQHandler
409 DMA2_Stream6_IRQHandler
410 DMA2_Stream7_IRQHandler
411 USART6_IRQHandler
412 I2C3_EV_IRQHandler
413 I2C3_ER_IRQHandler
414 OTG_HS_EP1_OUT_IRQHandler
415 OTG_HS_EP1_IN_IRQHandler
416 OTG_HS_WKUP_IRQHandler
417 OTG_HS_IRQHandler
418 DCMI_IRQHandler
419 CRYP_IRQHandler
420 HASH_RNG_IRQHandler
421 FPU_IRQHandler
422 UART7_IRQHandler
423 UART8_IRQHandler
424 SPI4_IRQHandler
425 SPI5_IRQHandler
426 SPI6_IRQHandler
427 SAI1_IRQHandler
428 DMA2D_IRQHandler
429 B .
430
431 ENDP
432
433 ALIGN
434
435 ;*******************************************************************************
436 ; User Stack and Heap initialization
437 ;*******************************************************************************
438 IF :DEF:__MICROLIB
439
440 EXPORT __initial_sp
441 EXPORT __heap_base
442 EXPORT __heap_limit
443
444 ELSE
445
446 IMPORT __use_two_region_memory
447 EXPORT __user_initial_stackheap
448
449 __user_initial_stackheap
450
451 LDR R0, = Heap_Mem
452 LDR R1, =(Stack_Mem + Stack_Size)
453 LDR R2, = (Heap_Mem + Heap_Size)
454 LDR R3, = Stack_Mem
455 BX LR
456
457 ALIGN
458
459 ENDIF
460
461 END
462
463 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****