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comparison Common/Drivers/STM32F4xx_v220/Source/Templates/arm/startup_stm32f427xx.s @ 38:5f11787b4f42

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author heinrichsweikamp
date Sat, 28 Apr 2018 11:52:34 +0200
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37:ccc45c0e1ea2 38:5f11787b4f42
1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
2 ;* File Name : startup_stm32f427xx.s
3 ;* Author : MCD Application Team
4 ;* Version : V2.2.0
5 ;* Date : 15-December-2014
6 ;* Description : STM32F427x devices vector table for MDK-ARM toolchain.
7 ;* This module performs:
8 ;* - Set the initial SP
9 ;* - Set the initial PC == Reset_Handler
10 ;* - Set the vector table entries with the exceptions ISR address
11 ;* After Reset the CortexM4 processor is in Thread mode,
12 ;* priority is Privileged, and the Stack is set to Main.
13 ;* <<< Use Configuration Wizard in Context Menu >>>
14 ;*******************************************************************************
15 ;
16 ;* Redistribution and use in source and binary forms, with or without modification,
17 ;* are permitted provided that the following conditions are met:
18 ;* 1. Redistributions of source code must retain the above copyright notice,
19 ;* this list of conditions and the following disclaimer.
20 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
21 ;* this list of conditions and the following disclaimer in the documentation
22 ;* and/or other materials provided with the distribution.
23 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
24 ;* may be used to endorse or promote products derived from this software
25 ;* without specific prior written permission.
26 ;*
27 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 ;
38 ;*******************************************************************************
39
40 ; Amount of memory (in bytes) allocated for Stack
41 ; Tailor this value to your application needs
42 ; <h> Stack Configuration
43 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
44 ; </h>
45
46 Stack_Size EQU 0x00000400
47
48 AREA STACK, NOINIT, READWRITE, ALIGN=3
49 Stack_Mem SPACE Stack_Size
50 __initial_sp
51
52
53 ; <h> Heap Configuration
54 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
55 ; </h>
56
57 Heap_Size EQU 0x00000200
58
59 AREA HEAP, NOINIT, READWRITE, ALIGN=3
60 __heap_base
61 Heap_Mem SPACE Heap_Size
62 __heap_limit
63
64 PRESERVE8
65 THUMB
66
67
68 ; Vector Table Mapped to Address 0 at Reset
69 AREA RESET, DATA, READONLY
70 EXPORT __Vectors
71 EXPORT __Vectors_End
72 EXPORT __Vectors_Size
73
74 __Vectors DCD __initial_sp ; Top of Stack
75 DCD Reset_Handler ; Reset Handler
76 DCD NMI_Handler ; NMI Handler
77 DCD HardFault_Handler ; Hard Fault Handler
78 DCD MemManage_Handler ; MPU Fault Handler
79 DCD BusFault_Handler ; Bus Fault Handler
80 DCD UsageFault_Handler ; Usage Fault Handler
81 DCD 0 ; Reserved
82 DCD 0 ; Reserved
83 DCD 0 ; Reserved
84 DCD 0 ; Reserved
85 DCD SVC_Handler ; SVCall Handler
86 DCD DebugMon_Handler ; Debug Monitor Handler
87 DCD 0 ; Reserved
88 DCD PendSV_Handler ; PendSV Handler
89 DCD SysTick_Handler ; SysTick Handler
90
91 ; External Interrupts
92 DCD WWDG_IRQHandler ; Window WatchDog
93 DCD PVD_IRQHandler ; PVD through EXTI Line detection
94 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
95 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
96 DCD FLASH_IRQHandler ; FLASH
97 DCD RCC_IRQHandler ; RCC
98 DCD EXTI0_IRQHandler ; EXTI Line0
99 DCD EXTI1_IRQHandler ; EXTI Line1
100 DCD EXTI2_IRQHandler ; EXTI Line2
101 DCD EXTI3_IRQHandler ; EXTI Line3
102 DCD EXTI4_IRQHandler ; EXTI Line4
103 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
104 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
105 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
106 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
107 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
108 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
109 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
110 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
111 DCD CAN1_TX_IRQHandler ; CAN1 TX
112 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
113 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
114 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
115 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
116 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
117 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
118 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
119 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
120 DCD TIM2_IRQHandler ; TIM2
121 DCD TIM3_IRQHandler ; TIM3
122 DCD TIM4_IRQHandler ; TIM4
123 DCD I2C1_EV_IRQHandler ; I2C1 Event
124 DCD I2C1_ER_IRQHandler ; I2C1 Error
125 DCD I2C2_EV_IRQHandler ; I2C2 Event
126 DCD I2C2_ER_IRQHandler ; I2C2 Error
127 DCD SPI1_IRQHandler ; SPI1
128 DCD SPI2_IRQHandler ; SPI2
129 DCD USART1_IRQHandler ; USART1
130 DCD USART2_IRQHandler ; USART2
131 DCD USART3_IRQHandler ; USART3
132 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
133 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
134 DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
135 DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
136 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
137 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
138 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
139 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
140 DCD FMC_IRQHandler ; FMC
141 DCD SDIO_IRQHandler ; SDIO
142 DCD TIM5_IRQHandler ; TIM5
143 DCD SPI3_IRQHandler ; SPI3
144 DCD UART4_IRQHandler ; UART4
145 DCD UART5_IRQHandler ; UART5
146 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
147 DCD TIM7_IRQHandler ; TIM7
148 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
149 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
150 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
151 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
152 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
153 DCD ETH_IRQHandler ; Ethernet
154 DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
155 DCD CAN2_TX_IRQHandler ; CAN2 TX
156 DCD CAN2_RX0_IRQHandler ; CAN2 RX0
157 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
158 DCD CAN2_SCE_IRQHandler ; CAN2 SCE
159 DCD OTG_FS_IRQHandler ; USB OTG FS
160 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
161 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
162 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
163 DCD USART6_IRQHandler ; USART6
164 DCD I2C3_EV_IRQHandler ; I2C3 event
165 DCD I2C3_ER_IRQHandler ; I2C3 error
166 DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
167 DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
168 DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
169 DCD OTG_HS_IRQHandler ; USB OTG HS
170 DCD DCMI_IRQHandler ; DCMI
171 DCD 0 ; Reserved
172 DCD HASH_RNG_IRQHandler ; Hash and Rng
173 DCD FPU_IRQHandler ; FPU
174 DCD UART7_IRQHandler ; UART7
175 DCD UART8_IRQHandler ; UART8
176 DCD SPI4_IRQHandler ; SPI4
177 DCD SPI5_IRQHandler ; SPI5
178 DCD SPI6_IRQHandler ; SPI6
179 DCD SAI1_IRQHandler ; SAI1
180 DCD 0 ; Reserved
181 DCD 0 ; Reserved
182 DCD DMA2D_IRQHandler ; DMA2D
183
184 __Vectors_End
185
186 __Vectors_Size EQU __Vectors_End - __Vectors
187
188 AREA |.text|, CODE, READONLY
189
190 ; Reset handler
191 Reset_Handler PROC
192 EXPORT Reset_Handler [WEAK]
193 IMPORT SystemInit
194 IMPORT __main
195
196 LDR R0, =SystemInit
197 BLX R0
198 LDR R0, =__main
199 BX R0
200 ENDP
201
202 ; Dummy Exception Handlers (infinite loops which can be modified)
203
204 NMI_Handler PROC
205 EXPORT NMI_Handler [WEAK]
206 B .
207 ENDP
208 HardFault_Handler\
209 PROC
210 EXPORT HardFault_Handler [WEAK]
211 B .
212 ENDP
213 MemManage_Handler\
214 PROC
215 EXPORT MemManage_Handler [WEAK]
216 B .
217 ENDP
218 BusFault_Handler\
219 PROC
220 EXPORT BusFault_Handler [WEAK]
221 B .
222 ENDP
223 UsageFault_Handler\
224 PROC
225 EXPORT UsageFault_Handler [WEAK]
226 B .
227 ENDP
228 SVC_Handler PROC
229 EXPORT SVC_Handler [WEAK]
230 B .
231 ENDP
232 DebugMon_Handler\
233 PROC
234 EXPORT DebugMon_Handler [WEAK]
235 B .
236 ENDP
237 PendSV_Handler PROC
238 EXPORT PendSV_Handler [WEAK]
239 B .
240 ENDP
241 SysTick_Handler PROC
242 EXPORT SysTick_Handler [WEAK]
243 B .
244 ENDP
245
246 Default_Handler PROC
247
248 EXPORT WWDG_IRQHandler [WEAK]
249 EXPORT PVD_IRQHandler [WEAK]
250 EXPORT TAMP_STAMP_IRQHandler [WEAK]
251 EXPORT RTC_WKUP_IRQHandler [WEAK]
252 EXPORT FLASH_IRQHandler [WEAK]
253 EXPORT RCC_IRQHandler [WEAK]
254 EXPORT EXTI0_IRQHandler [WEAK]
255 EXPORT EXTI1_IRQHandler [WEAK]
256 EXPORT EXTI2_IRQHandler [WEAK]
257 EXPORT EXTI3_IRQHandler [WEAK]
258 EXPORT EXTI4_IRQHandler [WEAK]
259 EXPORT DMA1_Stream0_IRQHandler [WEAK]
260 EXPORT DMA1_Stream1_IRQHandler [WEAK]
261 EXPORT DMA1_Stream2_IRQHandler [WEAK]
262 EXPORT DMA1_Stream3_IRQHandler [WEAK]
263 EXPORT DMA1_Stream4_IRQHandler [WEAK]
264 EXPORT DMA1_Stream5_IRQHandler [WEAK]
265 EXPORT DMA1_Stream6_IRQHandler [WEAK]
266 EXPORT ADC_IRQHandler [WEAK]
267 EXPORT CAN1_TX_IRQHandler [WEAK]
268 EXPORT CAN1_RX0_IRQHandler [WEAK]
269 EXPORT CAN1_RX1_IRQHandler [WEAK]
270 EXPORT CAN1_SCE_IRQHandler [WEAK]
271 EXPORT EXTI9_5_IRQHandler [WEAK]
272 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
273 EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
274 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
275 EXPORT TIM1_CC_IRQHandler [WEAK]
276 EXPORT TIM2_IRQHandler [WEAK]
277 EXPORT TIM3_IRQHandler [WEAK]
278 EXPORT TIM4_IRQHandler [WEAK]
279 EXPORT I2C1_EV_IRQHandler [WEAK]
280 EXPORT I2C1_ER_IRQHandler [WEAK]
281 EXPORT I2C2_EV_IRQHandler [WEAK]
282 EXPORT I2C2_ER_IRQHandler [WEAK]
283 EXPORT SPI1_IRQHandler [WEAK]
284 EXPORT SPI2_IRQHandler [WEAK]
285 EXPORT USART1_IRQHandler [WEAK]
286 EXPORT USART2_IRQHandler [WEAK]
287 EXPORT USART3_IRQHandler [WEAK]
288 EXPORT EXTI15_10_IRQHandler [WEAK]
289 EXPORT RTC_Alarm_IRQHandler [WEAK]
290 EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
291 EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
292 EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
293 EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
294 EXPORT TIM8_CC_IRQHandler [WEAK]
295 EXPORT DMA1_Stream7_IRQHandler [WEAK]
296 EXPORT FMC_IRQHandler [WEAK]
297 EXPORT SDIO_IRQHandler [WEAK]
298 EXPORT TIM5_IRQHandler [WEAK]
299 EXPORT SPI3_IRQHandler [WEAK]
300 EXPORT UART4_IRQHandler [WEAK]
301 EXPORT UART5_IRQHandler [WEAK]
302 EXPORT TIM6_DAC_IRQHandler [WEAK]
303 EXPORT TIM7_IRQHandler [WEAK]
304 EXPORT DMA2_Stream0_IRQHandler [WEAK]
305 EXPORT DMA2_Stream1_IRQHandler [WEAK]
306 EXPORT DMA2_Stream2_IRQHandler [WEAK]
307 EXPORT DMA2_Stream3_IRQHandler [WEAK]
308 EXPORT DMA2_Stream4_IRQHandler [WEAK]
309 EXPORT ETH_IRQHandler [WEAK]
310 EXPORT ETH_WKUP_IRQHandler [WEAK]
311 EXPORT CAN2_TX_IRQHandler [WEAK]
312 EXPORT CAN2_RX0_IRQHandler [WEAK]
313 EXPORT CAN2_RX1_IRQHandler [WEAK]
314 EXPORT CAN2_SCE_IRQHandler [WEAK]
315 EXPORT OTG_FS_IRQHandler [WEAK]
316 EXPORT DMA2_Stream5_IRQHandler [WEAK]
317 EXPORT DMA2_Stream6_IRQHandler [WEAK]
318 EXPORT DMA2_Stream7_IRQHandler [WEAK]
319 EXPORT USART6_IRQHandler [WEAK]
320 EXPORT I2C3_EV_IRQHandler [WEAK]
321 EXPORT I2C3_ER_IRQHandler [WEAK]
322 EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
323 EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
324 EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
325 EXPORT OTG_HS_IRQHandler [WEAK]
326 EXPORT DCMI_IRQHandler [WEAK]
327 EXPORT HASH_RNG_IRQHandler [WEAK]
328 EXPORT FPU_IRQHandler [WEAK]
329 EXPORT UART7_IRQHandler [WEAK]
330 EXPORT UART8_IRQHandler [WEAK]
331 EXPORT SPI4_IRQHandler [WEAK]
332 EXPORT SPI5_IRQHandler [WEAK]
333 EXPORT SPI6_IRQHandler [WEAK]
334 EXPORT SAI1_IRQHandler [WEAK]
335 EXPORT DMA2D_IRQHandler [WEAK]
336
337 WWDG_IRQHandler
338 PVD_IRQHandler
339 TAMP_STAMP_IRQHandler
340 RTC_WKUP_IRQHandler
341 FLASH_IRQHandler
342 RCC_IRQHandler
343 EXTI0_IRQHandler
344 EXTI1_IRQHandler
345 EXTI2_IRQHandler
346 EXTI3_IRQHandler
347 EXTI4_IRQHandler
348 DMA1_Stream0_IRQHandler
349 DMA1_Stream1_IRQHandler
350 DMA1_Stream2_IRQHandler
351 DMA1_Stream3_IRQHandler
352 DMA1_Stream4_IRQHandler
353 DMA1_Stream5_IRQHandler
354 DMA1_Stream6_IRQHandler
355 ADC_IRQHandler
356 CAN1_TX_IRQHandler
357 CAN1_RX0_IRQHandler
358 CAN1_RX1_IRQHandler
359 CAN1_SCE_IRQHandler
360 EXTI9_5_IRQHandler
361 TIM1_BRK_TIM9_IRQHandler
362 TIM1_UP_TIM10_IRQHandler
363 TIM1_TRG_COM_TIM11_IRQHandler
364 TIM1_CC_IRQHandler
365 TIM2_IRQHandler
366 TIM3_IRQHandler
367 TIM4_IRQHandler
368 I2C1_EV_IRQHandler
369 I2C1_ER_IRQHandler
370 I2C2_EV_IRQHandler
371 I2C2_ER_IRQHandler
372 SPI1_IRQHandler
373 SPI2_IRQHandler
374 USART1_IRQHandler
375 USART2_IRQHandler
376 USART3_IRQHandler
377 EXTI15_10_IRQHandler
378 RTC_Alarm_IRQHandler
379 OTG_FS_WKUP_IRQHandler
380 TIM8_BRK_TIM12_IRQHandler
381 TIM8_UP_TIM13_IRQHandler
382 TIM8_TRG_COM_TIM14_IRQHandler
383 TIM8_CC_IRQHandler
384 DMA1_Stream7_IRQHandler
385 FMC_IRQHandler
386 SDIO_IRQHandler
387 TIM5_IRQHandler
388 SPI3_IRQHandler
389 UART4_IRQHandler
390 UART5_IRQHandler
391 TIM6_DAC_IRQHandler
392 TIM7_IRQHandler
393 DMA2_Stream0_IRQHandler
394 DMA2_Stream1_IRQHandler
395 DMA2_Stream2_IRQHandler
396 DMA2_Stream3_IRQHandler
397 DMA2_Stream4_IRQHandler
398 ETH_IRQHandler
399 ETH_WKUP_IRQHandler
400 CAN2_TX_IRQHandler
401 CAN2_RX0_IRQHandler
402 CAN2_RX1_IRQHandler
403 CAN2_SCE_IRQHandler
404 OTG_FS_IRQHandler
405 DMA2_Stream5_IRQHandler
406 DMA2_Stream6_IRQHandler
407 DMA2_Stream7_IRQHandler
408 USART6_IRQHandler
409 I2C3_EV_IRQHandler
410 I2C3_ER_IRQHandler
411 OTG_HS_EP1_OUT_IRQHandler
412 OTG_HS_EP1_IN_IRQHandler
413 OTG_HS_WKUP_IRQHandler
414 OTG_HS_IRQHandler
415 DCMI_IRQHandler
416 HASH_RNG_IRQHandler
417 FPU_IRQHandler
418 UART7_IRQHandler
419 UART8_IRQHandler
420 SPI4_IRQHandler
421 SPI5_IRQHandler
422 SPI6_IRQHandler
423 SAI1_IRQHandler
424 DMA2D_IRQHandler
425 B .
426
427 ENDP
428
429 ALIGN
430
431 ;*******************************************************************************
432 ; User Stack and Heap initialization
433 ;*******************************************************************************
434 IF :DEF:__MICROLIB
435
436 EXPORT __initial_sp
437 EXPORT __heap_base
438 EXPORT __heap_limit
439
440 ELSE
441
442 IMPORT __use_two_region_memory
443 EXPORT __user_initial_stackheap
444
445 __user_initial_stackheap
446
447 LDR R0, = Heap_Mem
448 LDR R1, =(Stack_Mem + Stack_Size)
449 LDR R2, = (Heap_Mem + Heap_Size)
450 LDR R3, = Stack_Mem
451 BX LR
452
453 ALIGN
454
455 ENDIF
456
457 END
458
459 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****