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date Sat, 28 Apr 2018 11:52:34 +0200
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1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
2 ;* File Name : startup_stm32f401xe.s
3 ;* Author : MCD Application Team
4 ;* Version : V2.2.0
5 ;* Date : 15-December-2014
6 ;* Description : STM32F401xe devices vector table for MDK-ARM toolchain.
7 ;* This module performs:
8 ;* - Set the initial SP
9 ;* - Set the initial PC == Reset_Handler
10 ;* - Set the vector table entries with the exceptions ISR address
11 ;* - Branches to __main in the C library (which eventually
12 ;* calls main()).
13 ;* After Reset the CortexM4 processor is in Thread mode,
14 ;* priority is Privileged, and the Stack is set to Main.
15 ;* <<< Use Configuration Wizard in Context Menu >>>
16 ;*******************************************************************************
17 ;
18 ;* Redistribution and use in source and binary forms, with or without modification,
19 ;* are permitted provided that the following conditions are met:
20 ;* 1. Redistributions of source code must retain the above copyright notice,
21 ;* this list of conditions and the following disclaimer.
22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
23 ;* this list of conditions and the following disclaimer in the documentation
24 ;* and/or other materials provided with the distribution.
25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
26 ;* may be used to endorse or promote products derived from this software
27 ;* without specific prior written permission.
28 ;*
29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 ;
40 ;*******************************************************************************
41
42 ; Amount of memory (in bytes) allocated for Stack
43 ; Tailor this value to your application needs
44 ; <h> Stack Configuration
45 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
46 ; </h>
47
48 Stack_Size EQU 0x00000400
49
50 AREA STACK, NOINIT, READWRITE, ALIGN=3
51 Stack_Mem SPACE Stack_Size
52 __initial_sp
53
54
55 ; <h> Heap Configuration
56 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
57 ; </h>
58
59 Heap_Size EQU 0x00000200
60
61 AREA HEAP, NOINIT, READWRITE, ALIGN=3
62 __heap_base
63 Heap_Mem SPACE Heap_Size
64 __heap_limit
65
66 PRESERVE8
67 THUMB
68
69
70 ; Vector Table Mapped to Address 0 at Reset
71 AREA RESET, DATA, READONLY
72 EXPORT __Vectors
73 EXPORT __Vectors_End
74 EXPORT __Vectors_Size
75
76 __Vectors DCD __initial_sp ; Top of Stack
77 DCD Reset_Handler ; Reset Handler
78 DCD NMI_Handler ; NMI Handler
79 DCD HardFault_Handler ; Hard Fault Handler
80 DCD MemManage_Handler ; MPU Fault Handler
81 DCD BusFault_Handler ; Bus Fault Handler
82 DCD UsageFault_Handler ; Usage Fault Handler
83 DCD 0 ; Reserved
84 DCD 0 ; Reserved
85 DCD 0 ; Reserved
86 DCD 0 ; Reserved
87 DCD SVC_Handler ; SVCall Handler
88 DCD DebugMon_Handler ; Debug Monitor Handler
89 DCD 0 ; Reserved
90 DCD PendSV_Handler ; PendSV Handler
91 DCD SysTick_Handler ; SysTick Handler
92
93 ; External Interrupts
94 DCD WWDG_IRQHandler ; Window WatchDog
95 DCD PVD_IRQHandler ; PVD through EXTI Line detection
96 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
97 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
98 DCD FLASH_IRQHandler ; FLASH
99 DCD RCC_IRQHandler ; RCC
100 DCD EXTI0_IRQHandler ; EXTI Line0
101 DCD EXTI1_IRQHandler ; EXTI Line1
102 DCD EXTI2_IRQHandler ; EXTI Line2
103 DCD EXTI3_IRQHandler ; EXTI Line3
104 DCD EXTI4_IRQHandler ; EXTI Line4
105 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
106 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
107 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
108 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
109 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
110 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
111 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
112 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
113 DCD 0 ; Reserved
114 DCD 0 ; Reserved
115 DCD 0 ; Reserved
116 DCD 0 ; Reserved
117 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
118 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
119 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
120 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
121 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
122 DCD TIM2_IRQHandler ; TIM2
123 DCD TIM3_IRQHandler ; TIM3
124 DCD TIM4_IRQHandler ; TIM4
125 DCD I2C1_EV_IRQHandler ; I2C1 Event
126 DCD I2C1_ER_IRQHandler ; I2C1 Error
127 DCD I2C2_EV_IRQHandler ; I2C2 Event
128 DCD I2C2_ER_IRQHandler ; I2C2 Error
129 DCD SPI1_IRQHandler ; SPI1
130 DCD SPI2_IRQHandler ; SPI2
131 DCD USART1_IRQHandler ; USART1
132 DCD USART2_IRQHandler ; USART2
133 DCD 0 ; Reserved
134 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
135 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
136 DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
137 DCD 0 ; Reserved
138 DCD 0 ; Reserved
139 DCD 0 ; Reserved
140 DCD 0 ; Reserved
141 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
142 DCD 0 ; Reserved
143 DCD SDIO_IRQHandler ; SDIO
144 DCD TIM5_IRQHandler ; TIM5
145 DCD SPI3_IRQHandler ; SPI3
146 DCD 0 ; Reserved
147 DCD 0 ; Reserved
148 DCD 0 ; Reserved
149 DCD 0 ; Reserved
150 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
151 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
152 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
153 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
154 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
155 DCD 0 ; Reserved
156 DCD 0 ; Reserved
157 DCD 0 ; Reserved
158 DCD 0 ; Reserved
159 DCD 0 ; Reserved
160 DCD 0 ; Reserved
161 DCD OTG_FS_IRQHandler ; USB OTG FS
162 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
163 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
164 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
165 DCD USART6_IRQHandler ; USART6
166 DCD I2C3_EV_IRQHandler ; I2C3 event
167 DCD I2C3_ER_IRQHandler ; I2C3 error
168 DCD 0 ; Reserved
169 DCD 0 ; Reserved
170 DCD 0 ; Reserved
171 DCD 0 ; Reserved
172 DCD 0 ; Reserved
173 DCD 0 ; Reserved
174 DCD 0 ; Reserved
175 DCD FPU_IRQHandler ; FPU
176 DCD 0 ; Reserved
177 DCD 0 ; Reserved
178 DCD SPI4_IRQHandler ; SPI4
179
180 __Vectors_End
181
182 __Vectors_Size EQU __Vectors_End - __Vectors
183
184 AREA |.text|, CODE, READONLY
185
186 ; Reset handler
187 Reset_Handler PROC
188 EXPORT Reset_Handler [WEAK]
189 IMPORT SystemInit
190 IMPORT __main
191
192 LDR R0, =SystemInit
193 BLX R0
194 LDR R0, =__main
195 BX R0
196 ENDP
197
198 ; Dummy Exception Handlers (infinite loops which can be modified)
199
200 NMI_Handler PROC
201 EXPORT NMI_Handler [WEAK]
202 B .
203 ENDP
204 HardFault_Handler\
205 PROC
206 EXPORT HardFault_Handler [WEAK]
207 B .
208 ENDP
209 MemManage_Handler\
210 PROC
211 EXPORT MemManage_Handler [WEAK]
212 B .
213 ENDP
214 BusFault_Handler\
215 PROC
216 EXPORT BusFault_Handler [WEAK]
217 B .
218 ENDP
219 UsageFault_Handler\
220 PROC
221 EXPORT UsageFault_Handler [WEAK]
222 B .
223 ENDP
224 SVC_Handler PROC
225 EXPORT SVC_Handler [WEAK]
226 B .
227 ENDP
228 DebugMon_Handler\
229 PROC
230 EXPORT DebugMon_Handler [WEAK]
231 B .
232 ENDP
233 PendSV_Handler PROC
234 EXPORT PendSV_Handler [WEAK]
235 B .
236 ENDP
237 SysTick_Handler PROC
238 EXPORT SysTick_Handler [WEAK]
239 B .
240 ENDP
241
242 Default_Handler PROC
243
244 EXPORT WWDG_IRQHandler [WEAK]
245 EXPORT PVD_IRQHandler [WEAK]
246 EXPORT TAMP_STAMP_IRQHandler [WEAK]
247 EXPORT RTC_WKUP_IRQHandler [WEAK]
248 EXPORT FLASH_IRQHandler [WEAK]
249 EXPORT RCC_IRQHandler [WEAK]
250 EXPORT EXTI0_IRQHandler [WEAK]
251 EXPORT EXTI1_IRQHandler [WEAK]
252 EXPORT EXTI2_IRQHandler [WEAK]
253 EXPORT EXTI3_IRQHandler [WEAK]
254 EXPORT EXTI4_IRQHandler [WEAK]
255 EXPORT DMA1_Stream0_IRQHandler [WEAK]
256 EXPORT DMA1_Stream1_IRQHandler [WEAK]
257 EXPORT DMA1_Stream2_IRQHandler [WEAK]
258 EXPORT DMA1_Stream3_IRQHandler [WEAK]
259 EXPORT DMA1_Stream4_IRQHandler [WEAK]
260 EXPORT DMA1_Stream5_IRQHandler [WEAK]
261 EXPORT DMA1_Stream6_IRQHandler [WEAK]
262 EXPORT ADC_IRQHandler [WEAK]
263 EXPORT EXTI9_5_IRQHandler [WEAK]
264 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
265 EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
266 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
267 EXPORT TIM1_CC_IRQHandler [WEAK]
268 EXPORT TIM2_IRQHandler [WEAK]
269 EXPORT TIM3_IRQHandler [WEAK]
270 EXPORT TIM4_IRQHandler [WEAK]
271 EXPORT I2C1_EV_IRQHandler [WEAK]
272 EXPORT I2C1_ER_IRQHandler [WEAK]
273 EXPORT I2C2_EV_IRQHandler [WEAK]
274 EXPORT I2C2_ER_IRQHandler [WEAK]
275 EXPORT SPI1_IRQHandler [WEAK]
276 EXPORT SPI2_IRQHandler [WEAK]
277 EXPORT USART1_IRQHandler [WEAK]
278 EXPORT USART2_IRQHandler [WEAK]
279 EXPORT EXTI15_10_IRQHandler [WEAK]
280 EXPORT RTC_Alarm_IRQHandler [WEAK]
281 EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
282 EXPORT DMA1_Stream7_IRQHandler [WEAK]
283 EXPORT SDIO_IRQHandler [WEAK]
284 EXPORT TIM5_IRQHandler [WEAK]
285 EXPORT SPI3_IRQHandler [WEAK]
286 EXPORT DMA2_Stream0_IRQHandler [WEAK]
287 EXPORT DMA2_Stream1_IRQHandler [WEAK]
288 EXPORT DMA2_Stream2_IRQHandler [WEAK]
289 EXPORT DMA2_Stream3_IRQHandler [WEAK]
290 EXPORT DMA2_Stream4_IRQHandler [WEAK]
291 EXPORT OTG_FS_IRQHandler [WEAK]
292 EXPORT DMA2_Stream5_IRQHandler [WEAK]
293 EXPORT DMA2_Stream6_IRQHandler [WEAK]
294 EXPORT DMA2_Stream7_IRQHandler [WEAK]
295 EXPORT USART6_IRQHandler [WEAK]
296 EXPORT I2C3_EV_IRQHandler [WEAK]
297 EXPORT I2C3_ER_IRQHandler [WEAK]
298 EXPORT FPU_IRQHandler [WEAK]
299 EXPORT SPI4_IRQHandler [WEAK]
300
301 WWDG_IRQHandler
302 PVD_IRQHandler
303 TAMP_STAMP_IRQHandler
304 RTC_WKUP_IRQHandler
305 FLASH_IRQHandler
306 RCC_IRQHandler
307 EXTI0_IRQHandler
308 EXTI1_IRQHandler
309 EXTI2_IRQHandler
310 EXTI3_IRQHandler
311 EXTI4_IRQHandler
312 DMA1_Stream0_IRQHandler
313 DMA1_Stream1_IRQHandler
314 DMA1_Stream2_IRQHandler
315 DMA1_Stream3_IRQHandler
316 DMA1_Stream4_IRQHandler
317 DMA1_Stream5_IRQHandler
318 DMA1_Stream6_IRQHandler
319 ADC_IRQHandler
320 EXTI9_5_IRQHandler
321 TIM1_BRK_TIM9_IRQHandler
322 TIM1_UP_TIM10_IRQHandler
323 TIM1_TRG_COM_TIM11_IRQHandler
324 TIM1_CC_IRQHandler
325 TIM2_IRQHandler
326 TIM3_IRQHandler
327 TIM4_IRQHandler
328 I2C1_EV_IRQHandler
329 I2C1_ER_IRQHandler
330 I2C2_EV_IRQHandler
331 I2C2_ER_IRQHandler
332 SPI1_IRQHandler
333 SPI2_IRQHandler
334 USART1_IRQHandler
335 USART2_IRQHandler
336 EXTI15_10_IRQHandler
337 RTC_Alarm_IRQHandler
338 OTG_FS_WKUP_IRQHandler
339 DMA1_Stream7_IRQHandler
340 SDIO_IRQHandler
341 TIM5_IRQHandler
342 SPI3_IRQHandler
343 DMA2_Stream0_IRQHandler
344 DMA2_Stream1_IRQHandler
345 DMA2_Stream2_IRQHandler
346 DMA2_Stream3_IRQHandler
347 DMA2_Stream4_IRQHandler
348 OTG_FS_IRQHandler
349 DMA2_Stream5_IRQHandler
350 DMA2_Stream6_IRQHandler
351 DMA2_Stream7_IRQHandler
352 USART6_IRQHandler
353 I2C3_EV_IRQHandler
354 I2C3_ER_IRQHandler
355 FPU_IRQHandler
356 SPI4_IRQHandler
357
358 B .
359
360 ENDP
361
362 ALIGN
363
364 ;*******************************************************************************
365 ; User Stack and Heap initialization
366 ;*******************************************************************************
367 IF :DEF:__MICROLIB
368
369 EXPORT __initial_sp
370 EXPORT __heap_base
371 EXPORT __heap_limit
372
373 ELSE
374
375 IMPORT __use_two_region_memory
376 EXPORT __user_initial_stackheap
377
378 __user_initial_stackheap
379
380 LDR R0, = Heap_Mem
381 LDR R1, =(Stack_Mem + Stack_Size)
382 LDR R2, = (Heap_Mem + Heap_Size)
383 LDR R3, = Stack_Mem
384 BX LR
385
386 ALIGN
387
388 ENDIF
389
390 END
391
392 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****