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author heinrichsweikamp
date Sat, 28 Apr 2018 11:52:34 +0200
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1 /**
2 ******************************************************************************
3 * @file stm32f417xx.h
4 * @author MCD Application Team
5 * @version V2.2.0
6 * @date 15-December-2014
7 * @brief CMSIS STM32F417xx Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral’s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 /** @addtogroup CMSIS
45 * @{
46 */
47
48 /** @addtogroup stm32f417xx
49 * @{
50 */
51
52 #ifndef __STM32F417xx_H
53 #define __STM32F417xx_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif /* __cplusplus */
58
59
60 /** @addtogroup Configuration_section_for_CMSIS
61 * @{
62 */
63
64 /**
65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
66 */
67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
71 #define __FPU_PRESENT 1 /*!< FPU present */
72
73 /**
74 * @}
75 */
76
77 /** @addtogroup Peripheral_interrupt_number_definition
78 * @{
79 */
80
81 /**
82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
83 * in @ref Library_configuration_section
84 */
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
102 RCC_IRQn = 5, /*!< RCC global Interrupt */
103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
121 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
122 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
123 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
139 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
140 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
141 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
142 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
144 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
145 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
153 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
154 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
155 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
156 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
157 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
158 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
159 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
160 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
161 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
162 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
163 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
165 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
166 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
167 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
168 USART6_IRQn = 71, /*!< USART6 global interrupt */
169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
171 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
172 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
173 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
174 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
175 DCMI_IRQn = 78, /*!< DCMI global interrupt */
176 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
177 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
178 FPU_IRQn = 81 /*!< FPU global interrupt */
179 } IRQn_Type;
180
181 /**
182 * @}
183 */
184
185 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
186 #include "system_stm32f4xx.h"
187 #include <stdint.h>
188
189 /** @addtogroup Peripheral_registers_structures
190 * @{
191 */
192
193 /**
194 * @brief Analog to Digital Converter
195 */
196
197 typedef struct
198 {
199 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
200 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
201 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
202 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
203 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
204 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
205 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
206 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
207 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
208 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
209 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
210 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
211 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
212 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
213 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
214 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
215 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
216 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
217 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
218 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
219 } ADC_TypeDef;
220
221 typedef struct
222 {
223 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
224 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
225 __IO uint32_t CDR; /*!< ADC common regular data register for dual
226 AND triple modes, Address offset: ADC1 base address + 0x308 */
227 } ADC_Common_TypeDef;
228
229
230 /**
231 * @brief Controller Area Network TxMailBox
232 */
233
234 typedef struct
235 {
236 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
237 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
238 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
239 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
240 } CAN_TxMailBox_TypeDef;
241
242 /**
243 * @brief Controller Area Network FIFOMailBox
244 */
245
246 typedef struct
247 {
248 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
249 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
250 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
251 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
252 } CAN_FIFOMailBox_TypeDef;
253
254 /**
255 * @brief Controller Area Network FilterRegister
256 */
257
258 typedef struct
259 {
260 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
261 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
262 } CAN_FilterRegister_TypeDef;
263
264 /**
265 * @brief Controller Area Network
266 */
267
268 typedef struct
269 {
270 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
271 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
272 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
273 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
274 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
275 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
276 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
277 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
278 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
279 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
280 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
281 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
282 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
283 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
284 uint32_t RESERVED2; /*!< Reserved, 0x208 */
285 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
286 uint32_t RESERVED3; /*!< Reserved, 0x210 */
287 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
288 uint32_t RESERVED4; /*!< Reserved, 0x218 */
289 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
290 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
291 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
292 } CAN_TypeDef;
293
294 /**
295 * @brief CRC calculation unit
296 */
297
298 typedef struct
299 {
300 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
301 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
302 uint8_t RESERVED0; /*!< Reserved, 0x05 */
303 uint16_t RESERVED1; /*!< Reserved, 0x06 */
304 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
305 } CRC_TypeDef;
306
307 /**
308 * @brief Digital to Analog Converter
309 */
310
311 typedef struct
312 {
313 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
314 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
315 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
316 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
317 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
318 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
319 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
320 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
321 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
322 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
323 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
324 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
325 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
326 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
327 } DAC_TypeDef;
328
329 /**
330 * @brief Debug MCU
331 */
332
333 typedef struct
334 {
335 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
336 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
337 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
338 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
339 }DBGMCU_TypeDef;
340
341 /**
342 * @brief DCMI
343 */
344
345 typedef struct
346 {
347 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
348 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
349 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
350 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
351 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
352 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
353 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
354 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
355 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
356 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
357 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
358 } DCMI_TypeDef;
359
360 /**
361 * @brief DMA Controller
362 */
363
364 typedef struct
365 {
366 __IO uint32_t CR; /*!< DMA stream x configuration register */
367 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
368 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
369 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
370 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
371 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
372 } DMA_Stream_TypeDef;
373
374 typedef struct
375 {
376 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
377 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
378 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
379 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
380 } DMA_TypeDef;
381
382
383 /**
384 * @brief Ethernet MAC
385 */
386
387 typedef struct
388 {
389 __IO uint32_t MACCR;
390 __IO uint32_t MACFFR;
391 __IO uint32_t MACHTHR;
392 __IO uint32_t MACHTLR;
393 __IO uint32_t MACMIIAR;
394 __IO uint32_t MACMIIDR;
395 __IO uint32_t MACFCR;
396 __IO uint32_t MACVLANTR; /* 8 */
397 uint32_t RESERVED0[2];
398 __IO uint32_t MACRWUFFR; /* 11 */
399 __IO uint32_t MACPMTCSR;
400 uint32_t RESERVED1[2];
401 __IO uint32_t MACSR; /* 15 */
402 __IO uint32_t MACIMR;
403 __IO uint32_t MACA0HR;
404 __IO uint32_t MACA0LR;
405 __IO uint32_t MACA1HR;
406 __IO uint32_t MACA1LR;
407 __IO uint32_t MACA2HR;
408 __IO uint32_t MACA2LR;
409 __IO uint32_t MACA3HR;
410 __IO uint32_t MACA3LR; /* 24 */
411 uint32_t RESERVED2[40];
412 __IO uint32_t MMCCR; /* 65 */
413 __IO uint32_t MMCRIR;
414 __IO uint32_t MMCTIR;
415 __IO uint32_t MMCRIMR;
416 __IO uint32_t MMCTIMR; /* 69 */
417 uint32_t RESERVED3[14];
418 __IO uint32_t MMCTGFSCCR; /* 84 */
419 __IO uint32_t MMCTGFMSCCR;
420 uint32_t RESERVED4[5];
421 __IO uint32_t MMCTGFCR;
422 uint32_t RESERVED5[10];
423 __IO uint32_t MMCRFCECR;
424 __IO uint32_t MMCRFAECR;
425 uint32_t RESERVED6[10];
426 __IO uint32_t MMCRGUFCR;
427 uint32_t RESERVED7[334];
428 __IO uint32_t PTPTSCR;
429 __IO uint32_t PTPSSIR;
430 __IO uint32_t PTPTSHR;
431 __IO uint32_t PTPTSLR;
432 __IO uint32_t PTPTSHUR;
433 __IO uint32_t PTPTSLUR;
434 __IO uint32_t PTPTSAR;
435 __IO uint32_t PTPTTHR;
436 __IO uint32_t PTPTTLR;
437 __IO uint32_t RESERVED8;
438 __IO uint32_t PTPTSSR;
439 uint32_t RESERVED9[565];
440 __IO uint32_t DMABMR;
441 __IO uint32_t DMATPDR;
442 __IO uint32_t DMARPDR;
443 __IO uint32_t DMARDLAR;
444 __IO uint32_t DMATDLAR;
445 __IO uint32_t DMASR;
446 __IO uint32_t DMAOMR;
447 __IO uint32_t DMAIER;
448 __IO uint32_t DMAMFBOCR;
449 __IO uint32_t DMARSWTR;
450 uint32_t RESERVED10[8];
451 __IO uint32_t DMACHTDR;
452 __IO uint32_t DMACHRDR;
453 __IO uint32_t DMACHTBAR;
454 __IO uint32_t DMACHRBAR;
455 } ETH_TypeDef;
456
457 /**
458 * @brief External Interrupt/Event Controller
459 */
460
461 typedef struct
462 {
463 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
464 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
465 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
466 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
467 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
468 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
469 } EXTI_TypeDef;
470
471 /**
472 * @brief FLASH Registers
473 */
474
475 typedef struct
476 {
477 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
478 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
479 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
480 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
481 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
482 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
483 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
484 } FLASH_TypeDef;
485
486
487 /**
488 * @brief Flexible Static Memory Controller
489 */
490
491 typedef struct
492 {
493 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
494 } FSMC_Bank1_TypeDef;
495
496 /**
497 * @brief Flexible Static Memory Controller Bank1E
498 */
499
500 typedef struct
501 {
502 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
503 } FSMC_Bank1E_TypeDef;
504
505 /**
506 * @brief Flexible Static Memory Controller Bank2
507 */
508
509 typedef struct
510 {
511 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
512 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
513 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
514 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
515 uint32_t RESERVED0; /*!< Reserved, 0x70 */
516 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
517 uint32_t RESERVED1; /*!< Reserved, 0x78 */
518 uint32_t RESERVED2; /*!< Reserved, 0x7C */
519 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
520 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
521 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
522 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
523 uint32_t RESERVED3; /*!< Reserved, 0x90 */
524 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
525 } FSMC_Bank2_3_TypeDef;
526
527 /**
528 * @brief Flexible Static Memory Controller Bank4
529 */
530
531 typedef struct
532 {
533 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
534 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
535 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
536 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
537 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
538 } FSMC_Bank4_TypeDef;
539
540
541 /**
542 * @brief General Purpose I/O
543 */
544
545 typedef struct
546 {
547 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
548 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
549 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
550 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
551 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
552 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
553 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
554 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
555 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
556 } GPIO_TypeDef;
557
558 /**
559 * @brief System configuration controller
560 */
561
562 typedef struct
563 {
564 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
565 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
566 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
567 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
568 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
569 } SYSCFG_TypeDef;
570
571 /**
572 * @brief Inter-integrated Circuit Interface
573 */
574
575 typedef struct
576 {
577 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
578 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
579 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
580 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
581 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
582 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
583 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
584 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
585 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
586 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
587 } I2C_TypeDef;
588
589 /**
590 * @brief Independent WATCHDOG
591 */
592
593 typedef struct
594 {
595 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
596 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
597 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
598 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
599 } IWDG_TypeDef;
600
601 /**
602 * @brief Power Control
603 */
604
605 typedef struct
606 {
607 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
608 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
609 } PWR_TypeDef;
610
611 /**
612 * @brief Reset and Clock Control
613 */
614
615 typedef struct
616 {
617 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
618 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
619 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
620 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
621 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
622 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
623 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
624 uint32_t RESERVED0; /*!< Reserved, 0x1C */
625 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
626 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
627 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
628 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
629 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
630 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
631 uint32_t RESERVED2; /*!< Reserved, 0x3C */
632 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
633 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
634 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
635 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
636 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
637 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
638 uint32_t RESERVED4; /*!< Reserved, 0x5C */
639 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
640 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
641 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
642 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
643 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
644 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
645 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
646 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
647
648 } RCC_TypeDef;
649
650 /**
651 * @brief Real-Time Clock
652 */
653
654 typedef struct
655 {
656 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
657 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
658 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
659 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
660 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
661 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
662 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
663 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
664 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
665 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
666 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
667 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
668 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
669 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
670 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
671 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
672 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
673 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
674 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
675 uint32_t RESERVED7; /*!< Reserved, 0x4C */
676 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
677 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
678 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
679 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
680 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
681 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
682 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
683 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
684 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
685 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
686 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
687 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
688 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
689 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
690 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
691 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
692 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
693 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
694 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
695 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
696 } RTC_TypeDef;
697
698
699 /**
700 * @brief SD host Interface
701 */
702
703 typedef struct
704 {
705 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
706 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
707 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
708 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
709 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
710 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
711 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
712 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
713 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
714 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
715 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
716 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
717 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
718 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
719 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
720 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
721 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
722 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
723 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
724 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
725 } SDIO_TypeDef;
726
727 /**
728 * @brief Serial Peripheral Interface
729 */
730
731 typedef struct
732 {
733 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
734 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
735 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
736 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
737 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
738 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
739 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
740 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
741 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
742 } SPI_TypeDef;
743
744 /**
745 * @brief TIM
746 */
747
748 typedef struct
749 {
750 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
751 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
752 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
753 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
754 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
755 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
756 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
757 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
758 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
759 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
760 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
761 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
762 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
763 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
764 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
765 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
766 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
767 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
768 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
769 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
770 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
771 } TIM_TypeDef;
772
773 /**
774 * @brief Universal Synchronous Asynchronous Receiver Transmitter
775 */
776
777 typedef struct
778 {
779 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
780 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
781 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
782 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
783 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
784 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
785 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
786 } USART_TypeDef;
787
788 /**
789 * @brief Window WATCHDOG
790 */
791
792 typedef struct
793 {
794 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
795 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
796 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
797 } WWDG_TypeDef;
798
799 /**
800 * @brief Crypto Processor
801 */
802
803 typedef struct
804 {
805 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
806 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
807 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
808 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
809 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
810 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
811 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
812 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
813 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
814 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
815 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
816 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
817 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
818 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
819 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
820 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
821 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
822 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
823 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
824 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
825 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
826 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
827 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
828 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
829 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
830 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
831 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
832 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
833 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
834 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
835 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
836 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
837 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
838 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
839 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
840 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
841 } CRYP_TypeDef;
842
843 /**
844 * @brief HASH
845 */
846
847 typedef struct
848 {
849 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
850 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
851 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
852 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
853 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
854 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
855 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
856 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
857 } HASH_TypeDef;
858
859 /**
860 * @brief HASH_DIGEST
861 */
862
863 typedef struct
864 {
865 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
866 } HASH_DIGEST_TypeDef;
867
868 /**
869 * @brief RNG
870 */
871
872 typedef struct
873 {
874 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
875 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
876 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
877 } RNG_TypeDef;
878
879
880
881 /**
882 * @brief __USB_OTG_Core_register
883 */
884 typedef struct
885 {
886 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
887 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
888 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
889 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
890 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
891 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
892 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
893 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
894 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
895 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
896 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
897 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
898 uint32_t Reserved30[2]; /* Reserved 030h*/
899 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
900 __IO uint32_t CID; /* User ID Register 03Ch*/
901 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
902 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
903 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
904 }
905 USB_OTG_GlobalTypeDef;
906
907
908
909 /**
910 * @brief __device_Registers
911 */
912 typedef struct
913 {
914 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
915 __IO uint32_t DCTL; /* dev Control Register 804h*/
916 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
917 uint32_t Reserved0C; /* Reserved 80Ch*/
918 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
919 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
920 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
921 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
922 uint32_t Reserved20; /* Reserved 820h*/
923 uint32_t Reserved9; /* Reserved 824h*/
924 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
925 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
926 __IO uint32_t DTHRCTL; /* dev thr 830h*/
927 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
928 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
929 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
930 uint32_t Reserved40; /* dedicated EP mask 840h*/
931 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
932 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
933 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
934 }
935 USB_OTG_DeviceTypeDef;
936
937
938 /**
939 * @brief __IN_Endpoint-Specific_Register
940 */
941 typedef struct
942 {
943 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
944 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
945 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
946 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
947 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
948 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
949 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
950 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
951 }
952 USB_OTG_INEndpointTypeDef;
953
954
955 /**
956 * @brief __OUT_Endpoint-Specific_Registers
957 */
958 typedef struct
959 {
960 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
961 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
962 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
963 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
964 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
965 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
966 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
967 }
968 USB_OTG_OUTEndpointTypeDef;
969
970
971 /**
972 * @brief __Host_Mode_Register_Structures
973 */
974 typedef struct
975 {
976 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
977 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
978 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
979 uint32_t Reserved40C; /* Reserved 40Ch*/
980 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
981 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
982 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
983 }
984 USB_OTG_HostTypeDef;
985
986
987 /**
988 * @brief __Host_Channel_Specific_Registers
989 */
990 typedef struct
991 {
992 __IO uint32_t HCCHAR;
993 __IO uint32_t HCSPLT;
994 __IO uint32_t HCINT;
995 __IO uint32_t HCINTMSK;
996 __IO uint32_t HCTSIZ;
997 __IO uint32_t HCDMA;
998 uint32_t Reserved[2];
999 }
1000 USB_OTG_HostChannelTypeDef;
1001
1002
1003 /**
1004 * @brief Peripheral_memory_map
1005 */
1006 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
1007 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
1008 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
1009 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
1010 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
1011 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
1012 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
1013 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
1014 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
1015 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
1016 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
1017 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
1018 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
1019 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
1020 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
1021 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
1022
1023 /* Legacy defines */
1024 #define SRAM_BASE SRAM1_BASE
1025 #define SRAM_BB_BASE SRAM1_BB_BASE
1026
1027
1028 /*!< Peripheral memory map */
1029 #define APB1PERIPH_BASE PERIPH_BASE
1030 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
1031 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
1032 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
1033
1034 /*!< APB1 peripherals */
1035 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1036 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1037 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1038 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1039 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1040 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1041 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1042 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1043 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1044 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1045 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1046 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1047 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
1048 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1049 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1050 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
1051 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1052 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1053 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1054 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1055 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1056 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1057 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
1058 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1059 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1060 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1061 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1062
1063 /*!< APB2 peripherals */
1064 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
1065 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
1066 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
1067 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
1068 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
1069 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
1070 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
1071 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
1072 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
1073 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1074 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
1075 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
1076 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
1077 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
1078 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
1079
1080 /*!< AHB1 peripherals */
1081 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
1082 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
1083 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
1084 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
1085 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
1086 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
1087 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
1088 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
1089 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
1090 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
1091 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
1092 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
1093 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
1094 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
1095 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
1096 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
1097 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
1098 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
1099 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
1100 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
1101 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
1102 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
1103 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
1104 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
1105 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
1106 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
1107 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
1108 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
1109 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
1110 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
1111 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
1112 #define ETH_MAC_BASE (ETH_BASE)
1113 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
1114 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
1115 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
1116
1117 /*!< AHB2 peripherals */
1118 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
1119 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
1120 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
1121 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
1122 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
1123
1124 /*!< FSMC Bankx registers base address */
1125 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
1126 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
1127 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060)
1128 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
1129
1130 /* Debug MCU registers base address */
1131 #define DBGMCU_BASE ((uint32_t )0xE0042000)
1132
1133 /*!< USB registers base address */
1134 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
1135 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
1136
1137 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
1138 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
1139 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
1140 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
1141 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
1142 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
1143 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
1144 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
1145 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
1146 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
1147 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
1148 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
1149
1150 /**
1151 * @}
1152 */
1153
1154 /** @addtogroup Peripheral_declaration
1155 * @{
1156 */
1157 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1158 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1159 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1160 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1161 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1162 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1163 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1164 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1165 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1166 #define RTC ((RTC_TypeDef *) RTC_BASE)
1167 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1168 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1169 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1170 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1171 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1172 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1173 #define USART2 ((USART_TypeDef *) USART2_BASE)
1174 #define USART3 ((USART_TypeDef *) USART3_BASE)
1175 #define UART4 ((USART_TypeDef *) UART4_BASE)
1176 #define UART5 ((USART_TypeDef *) UART5_BASE)
1177 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1178 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1179 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1180 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1181 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1182 #define PWR ((PWR_TypeDef *) PWR_BASE)
1183 #define DAC ((DAC_TypeDef *) DAC_BASE)
1184 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1185 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1186 #define USART1 ((USART_TypeDef *) USART1_BASE)
1187 #define USART6 ((USART_TypeDef *) USART6_BASE)
1188 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1189 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1190 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1191 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1192 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1193 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1194 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1195 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1196 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1197 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1198 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1199 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1200 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1201 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1202 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1203 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1204 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1205 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1206 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1207 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1208 #define CRC ((CRC_TypeDef *) CRC_BASE)
1209 #define RCC ((RCC_TypeDef *) RCC_BASE)
1210 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1211 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1212 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1213 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1214 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1215 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1216 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1217 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1218 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1219 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1220 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1221 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1222 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1223 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1224 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1225 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1226 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1227 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1228 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1229 #define ETH ((ETH_TypeDef *) ETH_BASE)
1230 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1231 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1232 #define HASH ((HASH_TypeDef *) HASH_BASE)
1233 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1234 #define RNG ((RNG_TypeDef *) RNG_BASE)
1235 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1236 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1237 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1238 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1239
1240 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1241
1242 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1243 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1244
1245 /**
1246 * @}
1247 */
1248
1249 /** @addtogroup Exported_constants
1250 * @{
1251 */
1252
1253 /** @addtogroup Peripheral_Registers_Bits_Definition
1254 * @{
1255 */
1256
1257 /******************************************************************************/
1258 /* Peripheral Registers_Bits_Definition */
1259 /******************************************************************************/
1260
1261 /******************************************************************************/
1262 /* */
1263 /* Analog to Digital Converter */
1264 /* */
1265 /******************************************************************************/
1266 /******************** Bit definition for ADC_SR register ********************/
1267 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
1268 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
1269 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
1270 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
1271 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
1272 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
1273
1274 /******************* Bit definition for ADC_CR1 register ********************/
1275 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1276 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1277 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1278 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1279 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1280 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1281 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
1282 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
1283 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
1284 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
1285 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
1286 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
1287 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
1288 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
1289 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1290 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
1291 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
1292 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
1293 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
1294 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
1295 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
1296 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1297 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1298 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
1299
1300 /******************* Bit definition for ADC_CR2 register ********************/
1301 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
1302 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
1303 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
1304 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
1305 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
1306 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
1307 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1308 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1309 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1310 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1311 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1312 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1313 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1314 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1315 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
1316 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1317 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1318 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1319 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1320 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
1321 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1322 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
1323 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
1324 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
1325
1326 /****************** Bit definition for ADC_SMPR1 register *******************/
1327 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1328 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1329 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1330 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1331 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1332 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1333 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1334 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1335 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1336 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1337 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1338 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1339 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1340 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1341 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1342 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1343 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1344 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1345 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1346 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1347 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1348 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1349 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1350 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1351 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1352 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1353 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1354 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1355 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1356 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1357 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1358 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1359 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1360 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1361 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1362 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1363
1364 /****************** Bit definition for ADC_SMPR2 register *******************/
1365 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1366 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1367 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1368 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1369 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1370 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1371 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1372 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1373 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1374 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1375 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1376 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1377 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1378 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1379 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1380 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1381 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1382 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1383 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1384 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1385 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1386 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1387 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1388 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1389 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1390 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1391 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1392 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1393 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1394 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1395 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1396 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1397 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1398 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1399 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1400 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1401 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1402 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
1403 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
1404 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
1405
1406 /****************** Bit definition for ADC_JOFR1 register *******************/
1407 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
1408
1409 /****************** Bit definition for ADC_JOFR2 register *******************/
1410 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
1411
1412 /****************** Bit definition for ADC_JOFR3 register *******************/
1413 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
1414
1415 /****************** Bit definition for ADC_JOFR4 register *******************/
1416 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
1417
1418 /******************* Bit definition for ADC_HTR register ********************/
1419 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
1420
1421 /******************* Bit definition for ADC_LTR register ********************/
1422 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
1423
1424 /******************* Bit definition for ADC_SQR1 register *******************/
1425 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1426 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1427 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1428 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1429 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1430 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1431 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1432 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1433 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1434 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1435 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1436 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1437 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1438 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1439 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1440 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1441 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1442 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1443 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1444 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1445 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1446 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1447 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1448 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1449 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
1450 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1451 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1452 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1453 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1454
1455 /******************* Bit definition for ADC_SQR2 register *******************/
1456 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1457 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1458 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1459 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1460 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1461 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1462 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1463 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1464 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1465 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1466 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1467 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1468 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1469 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1470 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1471 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1472 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1473 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1474 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1475 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1476 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1477 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1478 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1479 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1480 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1481 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1482 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1483 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1484 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1485 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1486 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1487 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1488 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1489 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1490 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1491 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1492
1493 /******************* Bit definition for ADC_SQR3 register *******************/
1494 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1495 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1496 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1497 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1498 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1499 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1500 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1501 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1502 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1503 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1504 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1505 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1506 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1507 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1508 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1509 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1510 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1511 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1512 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1513 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1514 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1515 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1516 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1517 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1518 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1519 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1520 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1521 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1522 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1523 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1524 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1525 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1526 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1527 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1528 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1529 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1530
1531 /******************* Bit definition for ADC_JSQR register *******************/
1532 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1533 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1534 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1535 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1536 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1537 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1538 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1539 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1540 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1541 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1542 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1543 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1544 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1545 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1546 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1547 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1548 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1549 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1550 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1551 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1552 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1553 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1554 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1555 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1556 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
1557 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1558 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1559
1560 /******************* Bit definition for ADC_JDR1 register *******************/
1561 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
1562
1563 /******************* Bit definition for ADC_JDR2 register *******************/
1564 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
1565
1566 /******************* Bit definition for ADC_JDR3 register *******************/
1567 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
1568
1569 /******************* Bit definition for ADC_JDR4 register *******************/
1570 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
1571
1572 /******************** Bit definition for ADC_DR register ********************/
1573 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
1574 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
1575
1576 /******************* Bit definition for ADC_CSR register ********************/
1577 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
1578 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
1579 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
1580 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
1581 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
1582 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
1583 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
1584 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
1585 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
1586 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
1587 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
1588 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
1589 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
1590 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
1591 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
1592 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
1593 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
1594 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
1595
1596 /******************* Bit definition for ADC_CCR register ********************/
1597 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1598 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1599 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1600 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1601 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1602 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1603 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1604 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1605 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1606 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1607 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1608 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
1609 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1610 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
1611 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
1612 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
1613 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1614 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1615 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
1616 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
1617
1618 /******************* Bit definition for ADC_CDR register ********************/
1619 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
1620 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
1621
1622 /******************************************************************************/
1623 /* */
1624 /* Controller Area Network */
1625 /* */
1626 /******************************************************************************/
1627 /*!<CAN control and status registers */
1628 /******************* Bit definition for CAN_MCR register ********************/
1629 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
1630 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
1631 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
1632 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
1633 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
1634 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
1635 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
1636 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
1637 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
1638 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
1639 /******************* Bit definition for CAN_MSR register ********************/
1640 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
1641 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
1642 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
1643 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
1644 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
1645 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
1646 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
1647 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
1648 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
1649
1650 /******************* Bit definition for CAN_TSR register ********************/
1651 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
1652 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
1653 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
1654 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
1655 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
1656 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
1657 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
1658 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
1659 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
1660 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
1661 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
1662 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
1663 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
1664 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
1665 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
1666 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
1667
1668 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
1669 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
1670 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
1671 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
1672
1673 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
1674 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
1675 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
1676 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
1677
1678 /******************* Bit definition for CAN_RF0R register *******************/
1679 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
1680 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
1681 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
1682 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
1683
1684 /******************* Bit definition for CAN_RF1R register *******************/
1685 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
1686 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
1687 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
1688 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
1689
1690 /******************** Bit definition for CAN_IER register *******************/
1691 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
1692 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
1693 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
1694 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
1695 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
1696 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
1697 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
1698 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
1699 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
1700 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
1701 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
1702 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
1703 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
1704 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
1705 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
1706 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
1707 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
1708 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
1709 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
1710
1711
1712 /******************** Bit definition for CAN_ESR register *******************/
1713 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
1714 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
1715 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
1716
1717 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
1718 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
1719 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
1720 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
1721
1722 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
1723 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
1724
1725 /******************* Bit definition for CAN_BTR register ********************/
1726 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
1727 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
1728 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1729 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1730 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1731 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1732 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
1733 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1734 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1735 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1736 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
1737 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1738 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1739 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
1740 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
1741
1742
1743 /*!<Mailbox registers */
1744 /****************** Bit definition for CAN_TI0R register ********************/
1745 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1746 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1747 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1748 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1749 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1750
1751 /****************** Bit definition for CAN_TDT0R register *******************/
1752 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1753 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1754 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1755
1756 /****************** Bit definition for CAN_TDL0R register *******************/
1757 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1758 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1759 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1760 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1761
1762 /****************** Bit definition for CAN_TDH0R register *******************/
1763 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1764 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1765 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1766 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1767
1768 /******************* Bit definition for CAN_TI1R register *******************/
1769 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1770 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1771 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1772 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1773 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1774
1775 /******************* Bit definition for CAN_TDT1R register ******************/
1776 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1777 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1778 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1779
1780 /******************* Bit definition for CAN_TDL1R register ******************/
1781 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1782 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1783 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1784 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1785
1786 /******************* Bit definition for CAN_TDH1R register ******************/
1787 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1788 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1789 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1790 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1791
1792 /******************* Bit definition for CAN_TI2R register *******************/
1793 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1794 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1795 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1796 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1797 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1798
1799 /******************* Bit definition for CAN_TDT2R register ******************/
1800 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1801 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1802 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1803
1804 /******************* Bit definition for CAN_TDL2R register ******************/
1805 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1806 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1807 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1808 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1809
1810 /******************* Bit definition for CAN_TDH2R register ******************/
1811 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1812 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1813 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1814 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1815
1816 /******************* Bit definition for CAN_RI0R register *******************/
1817 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1818 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1819 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1820 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1821
1822 /******************* Bit definition for CAN_RDT0R register ******************/
1823 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1824 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1825 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1826
1827 /******************* Bit definition for CAN_RDL0R register ******************/
1828 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1829 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1830 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1831 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1832
1833 /******************* Bit definition for CAN_RDH0R register ******************/
1834 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1835 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1836 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1837 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1838
1839 /******************* Bit definition for CAN_RI1R register *******************/
1840 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1841 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1842 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1843 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1844
1845 /******************* Bit definition for CAN_RDT1R register ******************/
1846 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1847 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1848 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1849
1850 /******************* Bit definition for CAN_RDL1R register ******************/
1851 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1852 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1853 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1854 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1855
1856 /******************* Bit definition for CAN_RDH1R register ******************/
1857 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1858 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1859 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1860 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1861
1862 /*!<CAN filter registers */
1863 /******************* Bit definition for CAN_FMR register ********************/
1864 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
1865 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
1866
1867 /******************* Bit definition for CAN_FM1R register *******************/
1868 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
1869 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
1870 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
1871 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
1872 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
1873 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
1874 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
1875 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
1876 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
1877 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
1878 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
1879 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
1880 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
1881 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
1882 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
1883 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
1884 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
1885 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
1886 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
1887 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
1888 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
1889 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
1890 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
1891 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
1892 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
1893 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
1894 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
1895 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
1896 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
1897
1898 /******************* Bit definition for CAN_FS1R register *******************/
1899 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
1900 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
1901 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
1902 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
1903 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
1904 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
1905 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
1906 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
1907 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
1908 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
1909 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
1910 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
1911 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
1912 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
1913 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
1914 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
1915 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
1916 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
1917 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
1918 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
1919 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
1920 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
1921 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
1922 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
1923 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
1924 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
1925 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
1926 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
1927 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
1928
1929 /****************** Bit definition for CAN_FFA1R register *******************/
1930 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
1931 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
1932 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
1933 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
1934 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
1935 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
1936 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
1937 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
1938 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
1939 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
1940 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
1941 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
1942 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
1943 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
1944 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
1945 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
1946 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
1947 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
1948 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
1949 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
1950 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
1951 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
1952 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
1953 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
1954 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
1955 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
1956 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
1957 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
1958 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
1959
1960 /******************* Bit definition for CAN_FA1R register *******************/
1961 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
1962 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
1963 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
1964 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
1965 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
1966 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
1967 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
1968 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
1969 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
1970 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
1971 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
1972 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
1973 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
1974 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
1975 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
1976 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
1977 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
1978 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
1979 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
1980 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
1981 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
1982 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
1983 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
1984 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
1985 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
1986 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
1987 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
1988 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
1989 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
1990
1991 /******************* Bit definition for CAN_F0R1 register *******************/
1992 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1993 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1994 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1995 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1996 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1997 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1998 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1999 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2000 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2001 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2002 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2003 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2004 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2005 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2006 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2007 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2008 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2009 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2010 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2011 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2012 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2013 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2014 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2015 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2016 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2017 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2018 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2019 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2020 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2021 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2022 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2023 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2024
2025 /******************* Bit definition for CAN_F1R1 register *******************/
2026 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2027 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2028 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2029 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2030 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2031 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2032 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2033 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2034 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2035 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2036 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2037 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2038 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2039 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2040 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2041 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2042 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2043 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2044 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2045 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2046 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2047 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2048 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2049 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2050 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2051 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2052 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2053 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2054 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2055 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2056 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2057 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2058
2059 /******************* Bit definition for CAN_F2R1 register *******************/
2060 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2061 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2062 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2063 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2064 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2065 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2066 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2067 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2068 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2069 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2070 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2071 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2072 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2073 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2074 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2075 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2076 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2077 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2078 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2079 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2080 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2081 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2082 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2083 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2084 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2085 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2086 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2087 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2088 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2089 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2090 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2091 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2092
2093 /******************* Bit definition for CAN_F3R1 register *******************/
2094 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2095 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2096 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2097 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2098 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2099 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2100 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2101 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2102 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2103 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2104 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2105 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2106 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2107 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2108 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2109 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2110 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2111 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2112 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2113 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2114 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2115 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2116 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2117 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2118 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2119 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2120 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2121 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2122 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2123 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2124 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2125 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2126
2127 /******************* Bit definition for CAN_F4R1 register *******************/
2128 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2129 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2130 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2131 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2132 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2133 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2134 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2135 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2136 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2137 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2138 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2139 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2140 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2141 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2142 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2143 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2144 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2145 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2146 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2147 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2148 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2149 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2150 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2151 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2152 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2153 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2154 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2155 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2156 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2157 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2158 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2159 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2160
2161 /******************* Bit definition for CAN_F5R1 register *******************/
2162 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2163 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2164 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2165 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2166 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2167 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2168 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2169 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2170 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2171 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2172 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2173 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2174 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2175 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2176 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2177 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2178 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2179 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2180 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2181 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2182 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2183 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2184 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2185 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2186 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2187 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2188 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2189 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2190 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2191 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2192 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2193 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2194
2195 /******************* Bit definition for CAN_F6R1 register *******************/
2196 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2197 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2198 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2199 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2200 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2201 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2202 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2203 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2204 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2205 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2206 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2207 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2208 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2209 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2210 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2211 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2212 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2213 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2214 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2215 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2216 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2217 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2218 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2219 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2220 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2221 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2222 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2223 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2224 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2225 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2226 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2227 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2228
2229 /******************* Bit definition for CAN_F7R1 register *******************/
2230 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2231 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2232 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2233 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2234 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2235 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2236 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2237 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2238 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2239 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2240 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2241 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2242 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2243 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2244 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2245 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2246 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2247 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2248 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2249 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2250 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2251 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2252 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2253 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2254 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2255 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2256 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2257 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2258 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2259 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2260 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2261 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2262
2263 /******************* Bit definition for CAN_F8R1 register *******************/
2264 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2265 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2266 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2267 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2268 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2269 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2270 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2271 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2272 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2273 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2274 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2275 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2276 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2277 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2278 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2279 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2280 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2281 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2282 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2283 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2284 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2285 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2286 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2287 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2288 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2289 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2290 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2291 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2292 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2293 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2294 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2295 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2296
2297 /******************* Bit definition for CAN_F9R1 register *******************/
2298 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2299 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2300 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2301 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2302 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2303 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2304 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2305 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2306 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2307 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2308 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2309 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2310 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2311 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2312 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2313 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2314 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2315 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2316 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2317 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2318 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2319 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2320 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2321 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2322 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2323 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2324 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2325 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2326 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2327 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2328 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2329 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2330
2331 /******************* Bit definition for CAN_F10R1 register ******************/
2332 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2333 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2334 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2335 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2336 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2337 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2338 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2339 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2340 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2341 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2342 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2343 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2344 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2345 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2346 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2347 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2348 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2349 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2350 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2351 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2352 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2353 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2354 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2355 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2356 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2357 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2358 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2359 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2360 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2361 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2362 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2363 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2364
2365 /******************* Bit definition for CAN_F11R1 register ******************/
2366 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2367 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2368 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2369 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2370 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2371 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2372 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2373 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2374 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2375 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2376 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2377 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2378 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2379 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2380 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2381 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2382 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2383 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2384 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2385 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2386 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2387 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2388 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2389 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2390 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2391 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2392 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2393 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2394 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2395 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2396 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2397 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2398
2399 /******************* Bit definition for CAN_F12R1 register ******************/
2400 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2401 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2402 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2403 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2404 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2405 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2406 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2407 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2408 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2409 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2410 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2411 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2412 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2413 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2414 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2415 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2416 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2417 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2418 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2419 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2420 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2421 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2422 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2423 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2424 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2425 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2426 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2427 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2428 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2429 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2430 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2431 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2432
2433 /******************* Bit definition for CAN_F13R1 register ******************/
2434 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2435 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2436 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2437 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2438 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2439 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2440 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2441 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2442 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2443 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2444 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2445 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2446 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2447 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2448 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2449 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2450 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2451 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2452 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2453 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2454 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2455 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2456 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2457 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2458 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2459 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2460 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2461 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2462 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2463 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2464 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2465 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2466
2467 /******************* Bit definition for CAN_F0R2 register *******************/
2468 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2469 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2470 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2471 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2472 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2473 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2474 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2475 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2476 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2477 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2478 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2479 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2480 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2481 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2482 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2483 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2484 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2485 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2486 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2487 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2488 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2489 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2490 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2491 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2492 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2493 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2494 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2495 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2496 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2497 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2498 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2499 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2500
2501 /******************* Bit definition for CAN_F1R2 register *******************/
2502 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2503 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2504 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2505 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2506 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2507 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2508 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2509 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2510 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2511 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2512 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2513 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2514 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2515 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2516 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2517 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2518 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2519 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2520 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2521 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2522 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2523 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2524 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2525 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2526 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2527 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2528 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2529 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2530 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2531 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2532 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2533 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2534
2535 /******************* Bit definition for CAN_F2R2 register *******************/
2536 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2537 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2538 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2539 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2540 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2541 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2542 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2543 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2544 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2545 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2546 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2547 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2548 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2549 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2550 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2551 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2552 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2553 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2554 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2555 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2556 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2557 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2558 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2559 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2560 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2561 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2562 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2563 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2564 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2565 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2566 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2567 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2568
2569 /******************* Bit definition for CAN_F3R2 register *******************/
2570 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2571 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2572 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2573 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2574 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2575 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2576 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2577 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2578 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2579 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2580 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2581 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2582 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2583 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2584 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2585 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2586 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2587 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2588 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2589 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2590 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2591 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2592 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2593 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2594 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2595 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2596 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2597 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2598 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2599 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2600 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2601 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2602
2603 /******************* Bit definition for CAN_F4R2 register *******************/
2604 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2605 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2606 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2607 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2608 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2609 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2610 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2611 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2612 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2613 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2614 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2615 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2616 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2617 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2618 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2619 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2620 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2621 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2622 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2623 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2624 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2625 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2626 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2627 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2628 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2629 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2630 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2631 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2632 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2633 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2634 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2635 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2636
2637 /******************* Bit definition for CAN_F5R2 register *******************/
2638 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2639 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2640 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2641 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2642 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2643 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2644 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2645 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2646 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2647 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2648 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2649 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2650 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2651 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2652 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2653 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2654 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2655 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2656 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2657 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2658 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2659 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2660 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2661 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2662 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2663 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2664 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2665 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2666 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2667 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2668 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2669 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2670
2671 /******************* Bit definition for CAN_F6R2 register *******************/
2672 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2673 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2674 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2675 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2676 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2677 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2678 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2679 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2680 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2681 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2682 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2683 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2684 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2685 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2686 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2687 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2688 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2689 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2690 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2691 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2692 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2693 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2694 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2695 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2696 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2697 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2698 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2699 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2700 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2701 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2702 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2703 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2704
2705 /******************* Bit definition for CAN_F7R2 register *******************/
2706 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2707 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2708 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2709 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2710 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2711 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2712 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2713 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2714 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2715 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2716 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2717 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2718 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2719 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2720 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2721 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2722 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2723 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2724 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2725 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2726 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2727 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2728 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2729 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2730 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2731 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2732 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2733 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2734 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2735 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2736 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2737 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2738
2739 /******************* Bit definition for CAN_F8R2 register *******************/
2740 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2741 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2742 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2743 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2744 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2745 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2746 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2747 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2748 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2749 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2750 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2751 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2752 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2753 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2754 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2755 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2756 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2757 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2758 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2759 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2760 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2761 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2762 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2763 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2764 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2765 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2766 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2767 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2768 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2769 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2770 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2771 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2772
2773 /******************* Bit definition for CAN_F9R2 register *******************/
2774 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2775 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2776 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2777 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2778 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2779 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2780 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2781 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2782 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2783 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2784 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2785 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2786 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2787 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2788 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2789 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2790 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2791 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2792 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2793 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2794 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2795 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2796 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2797 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2798 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2799 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2800 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2801 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2802 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2803 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2804 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2805 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2806
2807 /******************* Bit definition for CAN_F10R2 register ******************/
2808 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2809 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2810 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2811 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2812 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2813 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2814 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2815 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2816 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2817 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2818 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2819 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2820 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2821 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2822 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2823 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2824 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2825 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2826 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2827 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2828 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2829 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2830 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2831 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2832 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2833 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2834 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2835 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2836 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2837 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2838 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2839 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2840
2841 /******************* Bit definition for CAN_F11R2 register ******************/
2842 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2843 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2844 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2845 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2846 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2847 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2848 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2849 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2850 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2851 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2852 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2853 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2854 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2855 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2856 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2857 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2858 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2859 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2860 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2861 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2862 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2863 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2864 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2865 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2866 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2867 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2868 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2869 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2870 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2871 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2872 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2873 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2874
2875 /******************* Bit definition for CAN_F12R2 register ******************/
2876 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2877 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2878 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2879 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2880 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2881 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2882 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2883 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2884 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2885 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2886 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2887 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2888 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2889 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2890 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2891 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2892 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2893 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2894 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2895 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2896 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2897 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2898 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2899 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2900 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2901 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2902 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2903 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2904 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2905 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2906 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2907 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2908
2909 /******************* Bit definition for CAN_F13R2 register ******************/
2910 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2911 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2912 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2913 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2914 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2915 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2916 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2917 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2918 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2919 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2920 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2921 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2922 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2923 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2924 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2925 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2926 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2927 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2928 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2929 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2930 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2931 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2932 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2933 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2934 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2935 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2936 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2937 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2938 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2939 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2940 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2941 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2942
2943 /******************************************************************************/
2944 /* */
2945 /* CRC calculation unit */
2946 /* */
2947 /******************************************************************************/
2948 /******************* Bit definition for CRC_DR register *********************/
2949 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
2950
2951
2952 /******************* Bit definition for CRC_IDR register ********************/
2953 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
2954
2955
2956 /******************** Bit definition for CRC_CR register ********************/
2957 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
2958
2959 /******************************************************************************/
2960 /* */
2961 /* Crypto Processor */
2962 /* */
2963 /******************************************************************************/
2964 /******************* Bits definition for CRYP_CR register ********************/
2965 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
2966
2967 #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
2968 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
2969 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
2970 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
2971 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
2972 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
2973 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
2974 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
2975 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
2976 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
2977 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
2978 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
2979
2980 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
2981 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
2982 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
2983 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
2984 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
2985 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
2986 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
2987 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
2988
2989 #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
2990 #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
2991 #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
2992 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
2993
2994 /****************** Bits definition for CRYP_SR register *********************/
2995 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
2996 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
2997 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
2998 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
2999 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
3000 /****************** Bits definition for CRYP_DMACR register ******************/
3001 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
3002 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
3003 /***************** Bits definition for CRYP_IMSCR register ******************/
3004 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
3005 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
3006 /****************** Bits definition for CRYP_RISR register *******************/
3007 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
3008 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
3009 /****************** Bits definition for CRYP_MISR register *******************/
3010 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
3011 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
3012
3013 /******************************************************************************/
3014 /* */
3015 /* Digital to Analog Converter */
3016 /* */
3017 /******************************************************************************/
3018 /******************** Bit definition for DAC_CR register ********************/
3019 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
3020 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
3021 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
3022
3023 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
3024 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3025 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3026 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
3027
3028 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3029 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
3030 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
3031
3032 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3033 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3034 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3035 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3036 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3037
3038 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
3039 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
3040 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
3041 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
3042
3043 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
3044 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
3045 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
3046 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
3047
3048 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3049 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
3050 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
3051
3052 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3053 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3054 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3055 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3056 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3057
3058 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
3059
3060 /***************** Bit definition for DAC_SWTRIGR register ******************/
3061 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
3062 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
3063
3064 /***************** Bit definition for DAC_DHR12R1 register ******************/
3065 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
3066
3067 /***************** Bit definition for DAC_DHR12L1 register ******************/
3068 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
3069
3070 /****************** Bit definition for DAC_DHR8R1 register ******************/
3071 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
3072
3073 /***************** Bit definition for DAC_DHR12R2 register ******************/
3074 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
3075
3076 /***************** Bit definition for DAC_DHR12L2 register ******************/
3077 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
3078
3079 /****************** Bit definition for DAC_DHR8R2 register ******************/
3080 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
3081
3082 /***************** Bit definition for DAC_DHR12RD register ******************/
3083 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
3084 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
3085
3086 /***************** Bit definition for DAC_DHR12LD register ******************/
3087 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
3088 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
3089
3090 /****************** Bit definition for DAC_DHR8RD register ******************/
3091 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
3092 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
3093
3094 /******************* Bit definition for DAC_DOR1 register *******************/
3095 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
3096
3097 /******************* Bit definition for DAC_DOR2 register *******************/
3098 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
3099
3100 /******************** Bit definition for DAC_SR register ********************/
3101 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
3102 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
3103
3104 /******************************************************************************/
3105 /* */
3106 /* Debug MCU */
3107 /* */
3108 /******************************************************************************/
3109
3110 /******************************************************************************/
3111 /* */
3112 /* DCMI */
3113 /* */
3114 /******************************************************************************/
3115 /******************** Bits definition for DCMI_CR register ******************/
3116 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
3117 #define DCMI_CR_CM ((uint32_t)0x00000002)
3118 #define DCMI_CR_CROP ((uint32_t)0x00000004)
3119 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
3120 #define DCMI_CR_ESS ((uint32_t)0x00000010)
3121 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
3122 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
3123 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
3124 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
3125 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
3126 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
3127 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
3128 #define DCMI_CR_CRE ((uint32_t)0x00001000)
3129 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
3130
3131 /******************** Bits definition for DCMI_SR register ******************/
3132 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
3133 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
3134 #define DCMI_SR_FNE ((uint32_t)0x00000004)
3135
3136 /******************** Bits definition for DCMI_RISR register ****************/
3137 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
3138 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
3139 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
3140 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
3141 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
3142
3143 /******************** Bits definition for DCMI_IER register *****************/
3144 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
3145 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
3146 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
3147 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
3148 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
3149
3150 /******************** Bits definition for DCMI_MISR register ****************/
3151 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
3152 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
3153 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
3154 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
3155 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
3156
3157 /******************** Bits definition for DCMI_ICR register *****************/
3158 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
3159 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
3160 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
3161 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
3162 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
3163
3164 /******************************************************************************/
3165 /* */
3166 /* DMA Controller */
3167 /* */
3168 /******************************************************************************/
3169 /******************** Bits definition for DMA_SxCR register *****************/
3170 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
3171 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
3172 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
3173 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
3174 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
3175 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
3176 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
3177 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
3178 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
3179 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
3180 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
3181 #define DMA_SxCR_CT ((uint32_t)0x00080000)
3182 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
3183 #define DMA_SxCR_PL ((uint32_t)0x00030000)
3184 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
3185 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
3186 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
3187 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
3188 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
3189 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
3190 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
3191 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
3192 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
3193 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
3194 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
3195 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
3196 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
3197 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
3198 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
3199 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
3200 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
3201 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
3202 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
3203 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
3204 #define DMA_SxCR_EN ((uint32_t)0x00000001)
3205
3206 /******************** Bits definition for DMA_SxCNDTR register **************/
3207 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
3208 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
3209 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
3210 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
3211 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
3212 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
3213 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
3214 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
3215 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
3216 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
3217 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
3218 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
3219 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
3220 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
3221 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
3222 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
3223 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
3224
3225 /******************** Bits definition for DMA_SxFCR register ****************/
3226 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
3227 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
3228 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
3229 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
3230 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
3231 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
3232 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
3233 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
3234 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
3235
3236 /******************** Bits definition for DMA_LISR register *****************/
3237 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
3238 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
3239 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
3240 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
3241 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
3242 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
3243 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
3244 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
3245 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
3246 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
3247 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
3248 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
3249 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
3250 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
3251 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
3252 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
3253 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
3254 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
3255 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
3256 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
3257
3258 /******************** Bits definition for DMA_HISR register *****************/
3259 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
3260 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
3261 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
3262 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
3263 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
3264 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
3265 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
3266 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
3267 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
3268 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
3269 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
3270 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
3271 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
3272 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
3273 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
3274 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
3275 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
3276 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
3277 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
3278 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
3279
3280 /******************** Bits definition for DMA_LIFCR register ****************/
3281 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
3282 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
3283 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
3284 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
3285 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
3286 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
3287 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
3288 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
3289 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
3290 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
3291 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
3292 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
3293 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
3294 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
3295 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
3296 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
3297 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
3298 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
3299 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
3300 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
3301
3302 /******************** Bits definition for DMA_HIFCR register ****************/
3303 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
3304 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
3305 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
3306 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
3307 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
3308 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
3309 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
3310 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
3311 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
3312 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
3313 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
3314 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
3315 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
3316 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
3317 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
3318 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
3319 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
3320 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
3321 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
3322 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
3323
3324
3325 /******************************************************************************/
3326 /* */
3327 /* External Interrupt/Event Controller */
3328 /* */
3329 /******************************************************************************/
3330 /******************* Bit definition for EXTI_IMR register *******************/
3331 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3332 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3333 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3334 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3335 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3336 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3337 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3338 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3339 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3340 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3341 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3342 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3343 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3344 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3345 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3346 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3347 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3348 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3349 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3350 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3351
3352 /******************* Bit definition for EXTI_EMR register *******************/
3353 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3354 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3355 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3356 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3357 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3358 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3359 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3360 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3361 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3362 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3363 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3364 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3365 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3366 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3367 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3368 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3369 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3370 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3371 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3372 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3373
3374 /****************** Bit definition for EXTI_RTSR register *******************/
3375 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3376 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3377 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3378 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3379 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3380 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3381 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3382 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3383 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3384 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3385 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3386 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3387 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3388 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3389 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3390 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3391 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3392 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3393 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3394 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3395
3396 /****************** Bit definition for EXTI_FTSR register *******************/
3397 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3398 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3399 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3400 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3401 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3402 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3403 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3404 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3405 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3406 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3407 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3408 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3409 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3410 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3411 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3412 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3413 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3414 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3415 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3416 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3417
3418 /****************** Bit definition for EXTI_SWIER register ******************/
3419 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3420 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3421 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3422 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3423 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3424 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3425 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3426 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3427 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3428 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3429 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3430 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3431 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3432 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3433 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3434 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3435 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3436 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3437 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3438 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3439
3440 /******************* Bit definition for EXTI_PR register ********************/
3441 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3442 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3443 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3444 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3445 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3446 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3447 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3448 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3449 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3450 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3451 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3452 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3453 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3454 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3455 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3456 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3457 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3458 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3459 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3460 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3461
3462 /******************************************************************************/
3463 /* */
3464 /* FLASH */
3465 /* */
3466 /******************************************************************************/
3467 /******************* Bits definition for FLASH_ACR register *****************/
3468 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
3469 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
3470 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
3471 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
3472 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
3473 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
3474 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
3475 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
3476 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
3477
3478 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
3479 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
3480 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
3481 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
3482 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
3483 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
3484 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
3485
3486 /******************* Bits definition for FLASH_SR register ******************/
3487 #define FLASH_SR_EOP ((uint32_t)0x00000001)
3488 #define FLASH_SR_SOP ((uint32_t)0x00000002)
3489 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
3490 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
3491 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
3492 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
3493 #define FLASH_SR_BSY ((uint32_t)0x00010000)
3494
3495 /******************* Bits definition for FLASH_CR register ******************/
3496 #define FLASH_CR_PG ((uint32_t)0x00000001)
3497 #define FLASH_CR_SER ((uint32_t)0x00000002)
3498 #define FLASH_CR_MER ((uint32_t)0x00000004)
3499 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
3500 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
3501 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
3502 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
3503 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
3504 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
3505 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
3506 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
3507 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
3508 #define FLASH_CR_STRT ((uint32_t)0x00010000)
3509 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
3510 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
3511
3512 /******************* Bits definition for FLASH_OPTCR register ***************/
3513 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
3514 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
3515 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
3516 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
3517 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
3518
3519 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
3520 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
3521 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
3522 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
3523 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
3524 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
3525 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
3526 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
3527 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
3528 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
3529 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
3530 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
3531 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
3532 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
3533 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
3534 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
3535 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
3536 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
3537 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
3538 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
3539 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
3540 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
3541 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
3542 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
3543 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
3544
3545 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3546 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
3547 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
3548 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
3549 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
3550 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
3551 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
3552 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
3553 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
3554 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
3555 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
3556 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
3557 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
3558 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
3559
3560 /******************************************************************************/
3561 /* */
3562 /* Flexible Static Memory Controller */
3563 /* */
3564 /******************************************************************************/
3565 /****************** Bit definition for FSMC_BCR1 register *******************/
3566 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3567 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3568
3569 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3570 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3571 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3572
3573 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3574 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3575 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3576
3577 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3578 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3579 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3580 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3581 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3582 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3583 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3584 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3585 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3586 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3587
3588 /****************** Bit definition for FSMC_BCR2 register *******************/
3589 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3590 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3591
3592 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3593 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3594 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3595
3596 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3597 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3598 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3599
3600 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3601 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3602 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3603 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3604 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3605 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3606 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3607 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3608 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3609 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3610
3611 /****************** Bit definition for FSMC_BCR3 register *******************/
3612 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3613 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3614
3615 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3616 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3617 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3618
3619 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3620 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3621 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3622
3623 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3624 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3625 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3626 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3627 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3628 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3629 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3630 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3631 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3632 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3633
3634 /****************** Bit definition for FSMC_BCR4 register *******************/
3635 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3636 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3637
3638 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3639 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3640 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3641
3642 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3643 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3644 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3645
3646 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3647 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3648 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3649 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3650 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3651 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3652 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3653 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3654 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3655 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3656
3657 /****************** Bit definition for FSMC_BTR1 register ******************/
3658 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3659 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3660 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3661 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3662 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3663
3664 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3665 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3666 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3667 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3668 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3669
3670 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3671 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3672 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3673 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3674 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3675
3676 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3677 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3678 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3679 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3680 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3681
3682 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3683 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3684 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3685 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3686 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3687
3688 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3689 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3690 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3691 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3692 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3693
3694 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3695 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3696 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3697
3698 /****************** Bit definition for FSMC_BTR2 register *******************/
3699 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3700 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3701 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3702 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3703 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3704
3705 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3706 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3707 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3708 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3709 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3710
3711 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3712 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3713 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3714 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3715 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3716
3717 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3718 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3719 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3720 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3721 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3722
3723 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3724 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3725 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3726 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3727 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3728
3729 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3730 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3731 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3732 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3733 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3734
3735 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3736 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3737 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3738
3739 /******************* Bit definition for FSMC_BTR3 register *******************/
3740 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3741 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3742 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3743 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3744 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3745
3746 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3747 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3748 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3749 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3750 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3751
3752 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3753 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3754 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3755 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3756 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3757
3758 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3759 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3760 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3761 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3762 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3763
3764 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3765 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3766 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3767 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3768 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3769
3770 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3771 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3772 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3773 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3774 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3775
3776 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3777 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3778 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3779
3780 /****************** Bit definition for FSMC_BTR4 register *******************/
3781 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3782 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3783 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3784 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3785 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3786
3787 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3788 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3789 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3790 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3791 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3792
3793 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3794 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3795 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3796 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3797 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3798
3799 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3800 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3801 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3802 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3803 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3804
3805 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3806 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3807 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3808 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3809 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3810
3811 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3812 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3813 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3814 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3815 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3816
3817 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3818 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3819 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3820
3821 /****************** Bit definition for FSMC_BWTR1 register ******************/
3822 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3823 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3824 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3825 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3826 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3827
3828 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3829 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3830 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3831 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3832 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3833
3834 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3835 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3836 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3837 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3838 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3839
3840 #define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
3841 #define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3842 #define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3843 #define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3844 #define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3845
3846 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3847 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3848 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3849 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3850 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3851
3852 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3853 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3854 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3855 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3856 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3857
3858 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3859 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3860 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3861
3862 /****************** Bit definition for FSMC_BWTR2 register ******************/
3863 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3864 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3865 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3866 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3867 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3868
3869 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3870 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3871 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3872 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3873 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3874
3875 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3876 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3877 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3878 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3879 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3880
3881 #define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
3882 #define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3883 #define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3884 #define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3885 #define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3886
3887 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3888 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3889 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
3890 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3891 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3892
3893 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3894 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3895 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3896 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3897 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3898
3899 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3900 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3901 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3902
3903 /****************** Bit definition for FSMC_BWTR3 register ******************/
3904 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3905 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3906 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3907 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3908 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3909
3910 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3911 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3912 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3913 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3914 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3915
3916 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3917 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3918 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3919 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3920 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3921
3922 #define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
3923 #define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3924 #define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3925 #define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3926 #define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3927
3928 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3929 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3930 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3931 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3932 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3933
3934 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3935 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3936 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3937 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3938 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3939
3940 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3941 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3942 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3943
3944 /****************** Bit definition for FSMC_BWTR4 register ******************/
3945 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3946 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3947 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3948 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3949 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3950
3951 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3952 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3953 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3954 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3955 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3956
3957 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3958 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3959 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3960 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3961 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3962
3963 #define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
3964 #define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3965 #define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3966 #define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3967 #define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3968
3969 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3970 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3971 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3972 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3973 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3974
3975 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3976 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3977 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3978 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3979 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3980
3981 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3982 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3983 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3984
3985 /****************** Bit definition for FSMC_PCR2 register *******************/
3986 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3987 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3988 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3989
3990 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3991 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3992 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3993
3994 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3995
3996 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3997 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3998 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3999 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4000 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4001
4002 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4003 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4004 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4005 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4006 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4007
4008 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
4009 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4010 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4011 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4012
4013 /****************** Bit definition for FSMC_PCR3 register *******************/
4014 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4015 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4016 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4017
4018 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4019 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4020 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4021
4022 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4023
4024 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4025 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4026 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4027 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4028 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4029
4030 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4031 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4032 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4033 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4034 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4035
4036 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4037 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4038 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4039 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4040
4041 /****************** Bit definition for FSMC_PCR4 register *******************/
4042 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4043 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4044 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4045
4046 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4047 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4048 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4049
4050 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4051
4052 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4053 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4054 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4055 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4056 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4057
4058 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4059 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4060 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4061 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4062 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4063
4064 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4065 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4066 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4067 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4068
4069 /******************* Bit definition for FSMC_SR2 register *******************/
4070 #define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4071 #define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4072 #define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4073 #define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4074 #define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4075 #define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4076 #define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4077
4078 /******************* Bit definition for FSMC_SR3 register *******************/
4079 #define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4080 #define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4081 #define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4082 #define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4083 #define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4084 #define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4085 #define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4086
4087 /******************* Bit definition for FSMC_SR4 register *******************/
4088 #define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4089 #define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4090 #define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4091 #define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4092 #define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4093 #define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4094 #define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4095
4096 /****************** Bit definition for FSMC_PMEM2 register ******************/
4097 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
4098 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4099 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4100 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4101 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4102 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4103 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4104 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4105 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4106
4107 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
4108 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4109 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4110 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4111 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4112 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4113 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4114 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4115 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4116
4117 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
4118 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4119 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4120 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4121 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4122 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4123 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4124 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4125 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4126
4127 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
4128 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4129 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4130 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4131 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4132 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4133 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4134 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4135 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4136
4137 /****************** Bit definition for FSMC_PMEM3 register ******************/
4138 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
4139 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4140 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4141 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4142 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4143 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4144 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4145 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4146 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4147
4148 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4149 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4150 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4151 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4152 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4153 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4154 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4155 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4156 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4157
4158 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4159 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4160 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4161 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4162 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4163 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4164 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4165 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4166 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4167
4168 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4169 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4170 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4171 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4172 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4173 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4174 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4175 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4176 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4177
4178 /****************** Bit definition for FSMC_PMEM4 register ******************/
4179 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
4180 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4181 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4182 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4183 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4184 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4185 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4186 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4187 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4188
4189 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
4190 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4191 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4192 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4193 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4194 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4195 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4196 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4197 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4198
4199 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
4200 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4201 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4202 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4203 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4204 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4205 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4206 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4207 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4208
4209 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
4210 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4211 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4212 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4213 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4214 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4215 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4216 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4217 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4218
4219 /****************** Bit definition for FSMC_PATT2 register ******************/
4220 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
4221 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4222 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4223 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4224 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4225 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4226 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4227 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4228 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4229
4230 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
4231 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4232 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4233 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4234 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4235 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4236 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4237 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4238 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4239
4240 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
4241 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4242 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4243 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4244 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4245 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4246 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4247 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4248 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4249
4250 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
4251 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4252 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4253 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4254 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4255 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4256 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4257 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4258 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4259
4260 /****************** Bit definition for FSMC_PATT3 register ******************/
4261 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4262 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4263 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4264 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4265 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4266 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4267 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4268 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4269 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4270
4271 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4272 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4273 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4274 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4275 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4276 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4277 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4278 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4279 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4280
4281 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4282 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4283 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4284 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4285 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4286 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4287 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4288 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4289 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4290
4291 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4292 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4293 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4294 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4295 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4296 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4297 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4298 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4299 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4300
4301 /****************** Bit definition for FSMC_PATT4 register ******************/
4302 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
4303 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4304 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4305 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4306 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4307 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4308 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4309 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4310 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4311
4312 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
4313 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4314 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4315 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4316 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4317 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4318 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4319 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4320 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4321
4322 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
4323 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4324 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4325 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4326 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4327 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4328 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4329 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4330 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4331
4332 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
4333 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4334 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4335 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4336 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4337 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4338 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4339 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4340 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4341
4342 /****************** Bit definition for FSMC_PIO4 register *******************/
4343 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
4344 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4345 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4346 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4347 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4348 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4349 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4350 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4351 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4352
4353 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
4354 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4355 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4356 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4357 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4358 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4359 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4360 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4361 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4362
4363 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
4364 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4365 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4366 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4367 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4368 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4369 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4370 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4371 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4372
4373 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
4374 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4375 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4376 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4377 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4378 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4379 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4380 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4381 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4382
4383 /****************** Bit definition for FSMC_ECCR2 register ******************/
4384 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4385
4386 /****************** Bit definition for FSMC_ECCR3 register ******************/
4387 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4388
4389 /******************************************************************************/
4390 /* */
4391 /* General Purpose I/O */
4392 /* */
4393 /******************************************************************************/
4394 /****************** Bits definition for GPIO_MODER register *****************/
4395 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
4396 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
4397 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
4398
4399 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
4400 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
4401 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
4402
4403 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
4404 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
4405 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
4406
4407 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
4408 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
4409 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
4410
4411 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
4412 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
4413 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
4414
4415 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
4416 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
4417 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
4418
4419 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
4420 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
4421 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
4422
4423 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
4424 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
4425 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
4426
4427 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
4428 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
4429 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
4430
4431 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
4432 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
4433 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
4434
4435 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
4436 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
4437 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
4438
4439 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
4440 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
4441 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
4442
4443 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
4444 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
4445 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
4446
4447 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
4448 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
4449 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
4450
4451 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
4452 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
4453 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
4454
4455 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
4456 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
4457 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
4458
4459 /****************** Bits definition for GPIO_OTYPER register ****************/
4460 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
4461 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
4462 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
4463 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
4464 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
4465 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
4466 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
4467 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
4468 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
4469 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
4470 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
4471 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
4472 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
4473 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
4474 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
4475 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
4476
4477 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4478 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
4479 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
4480 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
4481
4482 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
4483 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
4484 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
4485
4486 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
4487 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
4488 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
4489
4490 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
4491 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
4492 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
4493
4494 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
4495 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
4496 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
4497
4498 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
4499 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
4500 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
4501
4502 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
4503 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
4504 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
4505
4506 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
4507 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
4508 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
4509
4510 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
4511 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
4512 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
4513
4514 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
4515 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
4516 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
4517
4518 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
4519 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
4520 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
4521
4522 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
4523 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
4524 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
4525
4526 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
4527 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
4528 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
4529
4530 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
4531 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
4532 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
4533
4534 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
4535 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
4536 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
4537
4538 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
4539 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
4540 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
4541
4542 /****************** Bits definition for GPIO_PUPDR register *****************/
4543 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
4544 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
4545 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
4546
4547 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
4548 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
4549 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
4550
4551 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
4552 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
4553 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
4554
4555 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
4556 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
4557 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
4558
4559 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
4560 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
4561 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
4562
4563 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
4564 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
4565 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
4566
4567 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
4568 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
4569 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
4570
4571 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
4572 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
4573 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
4574
4575 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
4576 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
4577 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
4578
4579 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
4580 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
4581 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
4582
4583 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
4584 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
4585 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
4586
4587 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
4588 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
4589 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
4590
4591 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
4592 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
4593 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
4594
4595 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
4596 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
4597 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
4598
4599 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
4600 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
4601 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
4602
4603 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
4604 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
4605 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
4606
4607 /****************** Bits definition for GPIO_IDR register *******************/
4608 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
4609 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
4610 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
4611 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
4612 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
4613 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
4614 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
4615 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
4616 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
4617 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
4618 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
4619 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
4620 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
4621 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
4622 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
4623 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
4624 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4625 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
4626 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
4627 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
4628 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
4629 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
4630 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
4631 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
4632 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
4633 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
4634 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
4635 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
4636 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
4637 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
4638 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
4639 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
4640 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
4641
4642 /****************** Bits definition for GPIO_ODR register *******************/
4643 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
4644 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
4645 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
4646 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
4647 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
4648 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
4649 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
4650 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
4651 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
4652 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
4653 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
4654 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
4655 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
4656 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
4657 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
4658 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
4659 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4660 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
4661 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
4662 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
4663 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
4664 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
4665 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
4666 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
4667 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
4668 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
4669 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
4670 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
4671 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
4672 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
4673 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
4674 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
4675 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
4676
4677 /****************** Bits definition for GPIO_BSRR register ******************/
4678 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
4679 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
4680 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
4681 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
4682 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
4683 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
4684 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
4685 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
4686 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
4687 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
4688 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
4689 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
4690 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
4691 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
4692 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
4693 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
4694 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
4695 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
4696 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
4697 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
4698 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
4699 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
4700 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
4701 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
4702 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
4703 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
4704 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
4705 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
4706 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
4707 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
4708 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
4709 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
4710
4711 /****************** Bit definition for GPIO_LCKR register *********************/
4712 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
4713 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
4714 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
4715 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
4716 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
4717 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
4718 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
4719 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
4720 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
4721 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
4722 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
4723 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
4724 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
4725 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
4726 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
4727 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
4728 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
4729
4730 /******************************************************************************/
4731 /* */
4732 /* HASH */
4733 /* */
4734 /******************************************************************************/
4735 /****************** Bits definition for HASH_CR register ********************/
4736 #define HASH_CR_INIT ((uint32_t)0x00000004)
4737 #define HASH_CR_DMAE ((uint32_t)0x00000008)
4738 #define HASH_CR_DATATYPE ((uint32_t)0x00000030)
4739 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
4740 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
4741 #define HASH_CR_MODE ((uint32_t)0x00000040)
4742 #define HASH_CR_ALGO ((uint32_t)0x00040080)
4743 #define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
4744 #define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
4745 #define HASH_CR_NBW ((uint32_t)0x00000F00)
4746 #define HASH_CR_NBW_0 ((uint32_t)0x00000100)
4747 #define HASH_CR_NBW_1 ((uint32_t)0x00000200)
4748 #define HASH_CR_NBW_2 ((uint32_t)0x00000400)
4749 #define HASH_CR_NBW_3 ((uint32_t)0x00000800)
4750 #define HASH_CR_DINNE ((uint32_t)0x00001000)
4751 #define HASH_CR_MDMAT ((uint32_t)0x00002000)
4752 #define HASH_CR_LKEY ((uint32_t)0x00010000)
4753
4754 /****************** Bits definition for HASH_STR register *******************/
4755 #define HASH_STR_NBW ((uint32_t)0x0000001F)
4756 #define HASH_STR_NBW_0 ((uint32_t)0x00000001)
4757 #define HASH_STR_NBW_1 ((uint32_t)0x00000002)
4758 #define HASH_STR_NBW_2 ((uint32_t)0x00000004)
4759 #define HASH_STR_NBW_3 ((uint32_t)0x00000008)
4760 #define HASH_STR_NBW_4 ((uint32_t)0x00000010)
4761 #define HASH_STR_DCAL ((uint32_t)0x00000100)
4762
4763 /****************** Bits definition for HASH_IMR register *******************/
4764 #define HASH_IMR_DINIM ((uint32_t)0x00000001)
4765 #define HASH_IMR_DCIM ((uint32_t)0x00000002)
4766
4767 /****************** Bits definition for HASH_SR register ********************/
4768 #define HASH_SR_DINIS ((uint32_t)0x00000001)
4769 #define HASH_SR_DCIS ((uint32_t)0x00000002)
4770 #define HASH_SR_DMAS ((uint32_t)0x00000004)
4771 #define HASH_SR_BUSY ((uint32_t)0x00000008)
4772
4773 /******************************************************************************/
4774 /* */
4775 /* Inter-integrated Circuit Interface */
4776 /* */
4777 /******************************************************************************/
4778 /******************* Bit definition for I2C_CR1 register ********************/
4779 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
4780 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
4781 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
4782 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
4783 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
4784 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
4785 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
4786 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
4787 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
4788 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
4789 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
4790 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
4791 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
4792 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
4793
4794 /******************* Bit definition for I2C_CR2 register ********************/
4795 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
4796 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4797 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4798 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4799 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4800 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4801 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4802
4803 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
4804 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
4805 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
4806 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
4807 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
4808
4809 /******************* Bit definition for I2C_OAR1 register *******************/
4810 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
4811 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
4812
4813 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
4814 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
4815 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
4816 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
4817 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
4818 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
4819 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
4820 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
4821 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
4822 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
4823
4824 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
4825
4826 /******************* Bit definition for I2C_OAR2 register *******************/
4827 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
4828 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
4829
4830 /******************** Bit definition for I2C_DR register ********************/
4831 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
4832
4833 /******************* Bit definition for I2C_SR1 register ********************/
4834 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
4835 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
4836 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
4837 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
4838 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
4839 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
4840 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
4841 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
4842 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
4843 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
4844 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
4845 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
4846 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
4847 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
4848
4849 /******************* Bit definition for I2C_SR2 register ********************/
4850 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
4851 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
4852 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
4853 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
4854 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
4855 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
4856 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
4857 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
4858
4859 /******************* Bit definition for I2C_CCR register ********************/
4860 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
4861 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
4862 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
4863
4864 /****************** Bit definition for I2C_TRISE register *******************/
4865 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
4866
4867 /****************** Bit definition for I2C_FLTR register *******************/
4868 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
4869 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
4870
4871 /******************************************************************************/
4872 /* */
4873 /* Independent WATCHDOG */
4874 /* */
4875 /******************************************************************************/
4876 /******************* Bit definition for IWDG_KR register ********************/
4877 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
4878
4879 /******************* Bit definition for IWDG_PR register ********************/
4880 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
4881 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
4882 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
4883 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
4884
4885 /******************* Bit definition for IWDG_RLR register *******************/
4886 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
4887
4888 /******************* Bit definition for IWDG_SR register ********************/
4889 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
4890 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
4891
4892
4893 /******************************************************************************/
4894 /* */
4895 /* Power Control */
4896 /* */
4897 /******************************************************************************/
4898 /******************** Bit definition for PWR_CR register ********************/
4899 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
4900 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
4901 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
4902 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
4903 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
4904
4905 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
4906 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
4907 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
4908 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
4909
4910 /*!< PVD level configuration */
4911 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
4912 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
4913 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
4914 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
4915 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
4916 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
4917 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
4918 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
4919
4920 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
4921 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
4922 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
4923 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
4924 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
4925
4926 /* Legacy define */
4927 #define PWR_CR_PMODE PWR_CR_VOS
4928
4929 /******************* Bit definition for PWR_CSR register ********************/
4930 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
4931 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
4932 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
4933 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
4934 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
4935 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
4936 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
4937
4938 /* Legacy define */
4939 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
4940
4941 /******************************************************************************/
4942 /* */
4943 /* Reset and Clock Control */
4944 /* */
4945 /******************************************************************************/
4946 /******************** Bit definition for RCC_CR register ********************/
4947 #define RCC_CR_HSION ((uint32_t)0x00000001)
4948 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
4949
4950 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
4951 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
4952 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
4953 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
4954 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
4955 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
4956
4957 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
4958 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
4959 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
4960 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
4961 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
4962 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
4963 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
4964 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
4965 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
4966
4967 #define RCC_CR_HSEON ((uint32_t)0x00010000)
4968 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
4969 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
4970 #define RCC_CR_CSSON ((uint32_t)0x00080000)
4971 #define RCC_CR_PLLON ((uint32_t)0x01000000)
4972 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
4973 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
4974 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
4975
4976 /******************** Bit definition for RCC_PLLCFGR register ***************/
4977 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
4978 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
4979 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
4980 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
4981 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
4982 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
4983 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
4984
4985 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
4986 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
4987 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
4988 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
4989 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
4990 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
4991 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
4992 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
4993 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
4994 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
4995
4996 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
4997 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
4998 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
4999
5000 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
5001 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
5002 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
5003
5004 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
5005 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
5006 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
5007 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
5008 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
5009
5010 /******************** Bit definition for RCC_CFGR register ******************/
5011 /*!< SW configuration */
5012 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
5013 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5014 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5015
5016 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
5017 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
5018 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
5019
5020 /*!< SWS configuration */
5021 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
5022 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
5023 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
5024
5025 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
5026 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
5027 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
5028
5029 /*!< HPRE configuration */
5030 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
5031 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
5032 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
5033 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
5034 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
5035
5036 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
5037 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
5038 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
5039 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
5040 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
5041 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
5042 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
5043 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
5044 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
5045
5046 /*!< PPRE1 configuration */
5047 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
5048 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5049 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5050 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5051
5052 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5053 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
5054 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
5055 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
5056 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
5057
5058 /*!< PPRE2 configuration */
5059 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
5060 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
5061 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
5062 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
5063
5064 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5065 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
5066 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
5067 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
5068 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
5069
5070 /*!< RTCPRE configuration */
5071 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
5072 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
5073 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
5074 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
5075 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
5076 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
5077
5078 /*!< MCO1 configuration */
5079 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
5080 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
5081 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
5082
5083 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
5084
5085 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
5086 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
5087 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
5088 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
5089
5090 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
5091 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
5092 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
5093 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
5094
5095 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
5096 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
5097 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
5098
5099 /******************** Bit definition for RCC_CIR register *******************/
5100 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
5101 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
5102 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
5103 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
5104 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
5105 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
5106
5107 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
5108 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
5109 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
5110 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
5111 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
5112 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
5113 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
5114
5115 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
5116 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
5117 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
5118 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
5119 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
5120 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
5121
5122 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
5123
5124 /******************** Bit definition for RCC_AHB1RSTR register **************/
5125 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
5126 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
5127 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
5128 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
5129 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
5130 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
5131 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
5132 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
5133 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
5134 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
5135 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
5136 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
5137 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
5138 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
5139
5140 /******************** Bit definition for RCC_AHB2RSTR register **************/
5141 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
5142 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
5143 #define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
5144 /* maintained for legacy purpose */
5145 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
5146 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
5147 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
5148
5149 /******************** Bit definition for RCC_AHB3RSTR register **************/
5150
5151 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
5152
5153 /******************** Bit definition for RCC_APB1RSTR register **************/
5154 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
5155 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
5156 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
5157 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
5158 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
5159 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
5160 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
5161 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
5162 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
5163 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
5164 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
5165 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
5166 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
5167 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
5168 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
5169 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
5170 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
5171 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
5172 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
5173 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
5174 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
5175 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
5176 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
5177
5178 /******************** Bit definition for RCC_APB2RSTR register **************/
5179 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
5180 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
5181 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
5182 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
5183 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
5184 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
5185 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
5186 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
5187 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
5188 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
5189 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
5190
5191 /* Old SPI1RST bit definition, maintained for legacy purpose */
5192 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5193
5194 /******************** Bit definition for RCC_AHB1ENR register ***************/
5195 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
5196 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
5197 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
5198 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
5199 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
5200 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
5201 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
5202 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
5203 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
5204 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
5205 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
5206 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
5207 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
5208 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
5209
5210 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
5211 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
5212 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
5213 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
5214 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
5215 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
5216
5217 /******************** Bit definition for RCC_AHB2ENR register ***************/
5218 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
5219 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
5220 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
5221 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
5222 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
5223
5224 /******************** Bit definition for RCC_AHB3ENR register ***************/
5225
5226 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
5227
5228 /******************** Bit definition for RCC_APB1ENR register ***************/
5229 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
5230 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
5231 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
5232 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
5233 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
5234 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
5235 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
5236 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
5237 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
5238 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
5239 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
5240 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
5241 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
5242 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
5243 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
5244 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
5245 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
5246 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
5247 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
5248 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
5249 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
5250 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
5251 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
5252
5253 /******************** Bit definition for RCC_APB2ENR register ***************/
5254 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
5255 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
5256 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
5257 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
5258 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
5259 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
5260 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
5261 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
5262 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
5263 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
5264 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
5265 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
5266 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
5267 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
5268 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
5269
5270 /******************** Bit definition for RCC_AHB1LPENR register *************/
5271 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
5272 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
5273 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
5274 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
5275 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
5276 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
5277 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
5278 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
5279 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
5280 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
5281 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
5282 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
5283 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
5284 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
5285 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
5286 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
5287 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
5288 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
5289 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
5290 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
5291 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
5292 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
5293 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
5294
5295 /******************** Bit definition for RCC_AHB2LPENR register *************/
5296 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
5297 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
5298 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
5299 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
5300 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
5301
5302 /******************** Bit definition for RCC_AHB3LPENR register *************/
5303
5304 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
5305
5306 /******************** Bit definition for RCC_APB1LPENR register *************/
5307 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
5308 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
5309 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
5310 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
5311 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
5312 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
5313 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
5314 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
5315 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
5316 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
5317 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
5318 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
5319 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
5320 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
5321 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
5322 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
5323 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
5324 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
5325 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
5326 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
5327 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
5328 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
5329 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
5330
5331 /******************** Bit definition for RCC_APB2LPENR register *************/
5332 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
5333 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
5334 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
5335 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
5336 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
5337 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
5338 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
5339 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
5340 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
5341 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
5342 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
5343 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
5344 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
5345
5346 /******************** Bit definition for RCC_BDCR register ******************/
5347 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
5348 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
5349 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
5350
5351 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
5352 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
5353 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
5354
5355 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
5356 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
5357
5358 /******************** Bit definition for RCC_CSR register *******************/
5359 #define RCC_CSR_LSION ((uint32_t)0x00000001)
5360 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
5361 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
5362 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
5363 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
5364 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
5365 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
5366 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
5367 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
5368 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
5369
5370 /******************** Bit definition for RCC_SSCGR register *****************/
5371 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
5372 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
5373 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
5374 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
5375
5376 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5377 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
5378 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
5379 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
5380 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
5381 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
5382 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
5383 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
5384 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
5385 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
5386 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
5387
5388 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
5389 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
5390 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
5391 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
5392
5393 /******************************************************************************/
5394 /* */
5395 /* RNG */
5396 /* */
5397 /******************************************************************************/
5398 /******************** Bits definition for RNG_CR register *******************/
5399 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
5400 #define RNG_CR_IE ((uint32_t)0x00000008)
5401
5402 /******************** Bits definition for RNG_SR register *******************/
5403 #define RNG_SR_DRDY ((uint32_t)0x00000001)
5404 #define RNG_SR_CECS ((uint32_t)0x00000002)
5405 #define RNG_SR_SECS ((uint32_t)0x00000004)
5406 #define RNG_SR_CEIS ((uint32_t)0x00000020)
5407 #define RNG_SR_SEIS ((uint32_t)0x00000040)
5408
5409 /******************************************************************************/
5410 /* */
5411 /* Real-Time Clock (RTC) */
5412 /* */
5413 /******************************************************************************/
5414 /******************** Bits definition for RTC_TR register *******************/
5415 #define RTC_TR_PM ((uint32_t)0x00400000)
5416 #define RTC_TR_HT ((uint32_t)0x00300000)
5417 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
5418 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
5419 #define RTC_TR_HU ((uint32_t)0x000F0000)
5420 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
5421 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
5422 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
5423 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
5424 #define RTC_TR_MNT ((uint32_t)0x00007000)
5425 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5426 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5427 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5428 #define RTC_TR_MNU ((uint32_t)0x00000F00)
5429 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5430 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5431 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5432 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5433 #define RTC_TR_ST ((uint32_t)0x00000070)
5434 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
5435 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
5436 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
5437 #define RTC_TR_SU ((uint32_t)0x0000000F)
5438 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
5439 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
5440 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
5441 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
5442
5443 /******************** Bits definition for RTC_DR register *******************/
5444 #define RTC_DR_YT ((uint32_t)0x00F00000)
5445 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
5446 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
5447 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
5448 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
5449 #define RTC_DR_YU ((uint32_t)0x000F0000)
5450 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
5451 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
5452 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
5453 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
5454 #define RTC_DR_WDU ((uint32_t)0x0000E000)
5455 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
5456 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
5457 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
5458 #define RTC_DR_MT ((uint32_t)0x00001000)
5459 #define RTC_DR_MU ((uint32_t)0x00000F00)
5460 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
5461 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
5462 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
5463 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
5464 #define RTC_DR_DT ((uint32_t)0x00000030)
5465 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
5466 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
5467 #define RTC_DR_DU ((uint32_t)0x0000000F)
5468 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
5469 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
5470 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
5471 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
5472
5473 /******************** Bits definition for RTC_CR register *******************/
5474 #define RTC_CR_COE ((uint32_t)0x00800000)
5475 #define RTC_CR_OSEL ((uint32_t)0x00600000)
5476 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
5477 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
5478 #define RTC_CR_POL ((uint32_t)0x00100000)
5479 #define RTC_CR_COSEL ((uint32_t)0x00080000)
5480 #define RTC_CR_BCK ((uint32_t)0x00040000)
5481 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
5482 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
5483 #define RTC_CR_TSIE ((uint32_t)0x00008000)
5484 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
5485 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
5486 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
5487 #define RTC_CR_TSE ((uint32_t)0x00000800)
5488 #define RTC_CR_WUTE ((uint32_t)0x00000400)
5489 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
5490 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
5491 #define RTC_CR_DCE ((uint32_t)0x00000080)
5492 #define RTC_CR_FMT ((uint32_t)0x00000040)
5493 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
5494 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
5495 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
5496 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
5497 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
5498 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
5499 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
5500
5501 /******************** Bits definition for RTC_ISR register ******************/
5502 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
5503 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
5504 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
5505 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
5506 #define RTC_ISR_TSF ((uint32_t)0x00000800)
5507 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
5508 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
5509 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
5510 #define RTC_ISR_INIT ((uint32_t)0x00000080)
5511 #define RTC_ISR_INITF ((uint32_t)0x00000040)
5512 #define RTC_ISR_RSF ((uint32_t)0x00000020)
5513 #define RTC_ISR_INITS ((uint32_t)0x00000010)
5514 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
5515 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
5516 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
5517 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
5518
5519 /******************** Bits definition for RTC_PRER register *****************/
5520 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
5521 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
5522
5523 /******************** Bits definition for RTC_WUTR register *****************/
5524 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
5525
5526 /******************** Bits definition for RTC_CALIBR register ***************/
5527 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
5528 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
5529
5530 /******************** Bits definition for RTC_ALRMAR register ***************/
5531 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
5532 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
5533 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
5534 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
5535 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
5536 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
5537 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
5538 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
5539 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
5540 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
5541 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
5542 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
5543 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
5544 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
5545 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
5546 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
5547 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
5548 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
5549 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
5550 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
5551 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
5552 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
5553 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
5554 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
5555 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
5556 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
5557 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
5558 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
5559 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
5560 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
5561 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
5562 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
5563 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
5564 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
5565 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
5566 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
5567 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
5568 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
5569 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
5570 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
5571
5572 /******************** Bits definition for RTC_ALRMBR register ***************/
5573 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
5574 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
5575 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
5576 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
5577 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
5578 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
5579 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
5580 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
5581 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
5582 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
5583 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
5584 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
5585 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
5586 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
5587 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
5588 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
5589 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
5590 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
5591 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
5592 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
5593 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
5594 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
5595 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
5596 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
5597 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
5598 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
5599 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
5600 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
5601 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
5602 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
5603 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
5604 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
5605 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
5606 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
5607 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
5608 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
5609 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
5610 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
5611 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
5612 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
5613
5614 /******************** Bits definition for RTC_WPR register ******************/
5615 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
5616
5617 /******************** Bits definition for RTC_SSR register ******************/
5618 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
5619
5620 /******************** Bits definition for RTC_SHIFTR register ***************/
5621 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
5622 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
5623
5624 /******************** Bits definition for RTC_TSTR register *****************/
5625 #define RTC_TSTR_PM ((uint32_t)0x00400000)
5626 #define RTC_TSTR_HT ((uint32_t)0x00300000)
5627 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
5628 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
5629 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
5630 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
5631 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
5632 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
5633 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
5634 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
5635 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
5636 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
5637 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
5638 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
5639 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
5640 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
5641 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
5642 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
5643 #define RTC_TSTR_ST ((uint32_t)0x00000070)
5644 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
5645 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
5646 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
5647 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
5648 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
5649 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
5650 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
5651 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
5652
5653 /******************** Bits definition for RTC_TSDR register *****************/
5654 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
5655 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
5656 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
5657 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
5658 #define RTC_TSDR_MT ((uint32_t)0x00001000)
5659 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
5660 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
5661 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
5662 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
5663 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
5664 #define RTC_TSDR_DT ((uint32_t)0x00000030)
5665 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
5666 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
5667 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
5668 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
5669 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
5670 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
5671 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
5672
5673 /******************** Bits definition for RTC_TSSSR register ****************/
5674 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
5675
5676 /******************** Bits definition for RTC_CAL register *****************/
5677 #define RTC_CALR_CALP ((uint32_t)0x00008000)
5678 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
5679 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
5680 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
5681 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
5682 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
5683 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
5684 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
5685 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
5686 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
5687 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
5688 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
5689 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
5690
5691 /******************** Bits definition for RTC_TAFCR register ****************/
5692 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
5693 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
5694 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
5695 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
5696 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
5697 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
5698 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
5699 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
5700 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
5701 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
5702 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
5703 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
5704 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
5705 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
5706 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
5707 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
5708 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
5709 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
5710 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
5711 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
5712
5713 /******************** Bits definition for RTC_ALRMASSR register *************/
5714 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
5715 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
5716 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
5717 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
5718 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
5719 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
5720
5721 /******************** Bits definition for RTC_ALRMBSSR register *************/
5722 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
5723 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
5724 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
5725 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
5726 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
5727 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
5728
5729 /******************** Bits definition for RTC_BKP0R register ****************/
5730 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
5731
5732 /******************** Bits definition for RTC_BKP1R register ****************/
5733 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
5734
5735 /******************** Bits definition for RTC_BKP2R register ****************/
5736 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
5737
5738 /******************** Bits definition for RTC_BKP3R register ****************/
5739 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
5740
5741 /******************** Bits definition for RTC_BKP4R register ****************/
5742 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
5743
5744 /******************** Bits definition for RTC_BKP5R register ****************/
5745 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
5746
5747 /******************** Bits definition for RTC_BKP6R register ****************/
5748 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
5749
5750 /******************** Bits definition for RTC_BKP7R register ****************/
5751 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
5752
5753 /******************** Bits definition for RTC_BKP8R register ****************/
5754 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
5755
5756 /******************** Bits definition for RTC_BKP9R register ****************/
5757 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
5758
5759 /******************** Bits definition for RTC_BKP10R register ***************/
5760 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
5761
5762 /******************** Bits definition for RTC_BKP11R register ***************/
5763 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
5764
5765 /******************** Bits definition for RTC_BKP12R register ***************/
5766 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
5767
5768 /******************** Bits definition for RTC_BKP13R register ***************/
5769 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
5770
5771 /******************** Bits definition for RTC_BKP14R register ***************/
5772 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
5773
5774 /******************** Bits definition for RTC_BKP15R register ***************/
5775 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
5776
5777 /******************** Bits definition for RTC_BKP16R register ***************/
5778 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
5779
5780 /******************** Bits definition for RTC_BKP17R register ***************/
5781 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
5782
5783 /******************** Bits definition for RTC_BKP18R register ***************/
5784 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
5785
5786 /******************** Bits definition for RTC_BKP19R register ***************/
5787 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
5788
5789
5790
5791 /******************************************************************************/
5792 /* */
5793 /* SD host Interface */
5794 /* */
5795 /******************************************************************************/
5796 /****************** Bit definition for SDIO_POWER register ******************/
5797 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
5798 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
5799 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
5800
5801 /****************** Bit definition for SDIO_CLKCR register ******************/
5802 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
5803 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
5804 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
5805 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
5806
5807 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
5808 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
5809 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
5810
5811 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
5812 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
5813
5814 /******************* Bit definition for SDIO_ARG register *******************/
5815 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
5816
5817 /******************* Bit definition for SDIO_CMD register *******************/
5818 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
5819
5820 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
5821 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
5822 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
5823
5824 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
5825 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
5826 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
5827 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
5828 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
5829 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
5830 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
5831
5832 /***************** Bit definition for SDIO_RESPCMD register *****************/
5833 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
5834
5835 /****************** Bit definition for SDIO_RESP0 register ******************/
5836 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5837
5838 /****************** Bit definition for SDIO_RESP1 register ******************/
5839 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5840
5841 /****************** Bit definition for SDIO_RESP2 register ******************/
5842 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5843
5844 /****************** Bit definition for SDIO_RESP3 register ******************/
5845 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5846
5847 /****************** Bit definition for SDIO_RESP4 register ******************/
5848 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5849
5850 /****************** Bit definition for SDIO_DTIMER register *****************/
5851 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
5852
5853 /****************** Bit definition for SDIO_DLEN register *******************/
5854 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
5855
5856 /****************** Bit definition for SDIO_DCTRL register ******************/
5857 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
5858 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
5859 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
5860 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
5861
5862 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
5863 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
5864 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
5865 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
5866 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
5867
5868 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
5869 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
5870 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
5871 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
5872
5873 /****************** Bit definition for SDIO_DCOUNT register *****************/
5874 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
5875
5876 /****************** Bit definition for SDIO_STA register ********************/
5877 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
5878 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
5879 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
5880 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
5881 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
5882 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
5883 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
5884 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
5885 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
5886 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
5887 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
5888 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
5889 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
5890 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
5891 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5892 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
5893 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
5894 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
5895 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
5896 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
5897 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
5898 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
5899 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
5900 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
5901
5902 /******************* Bit definition for SDIO_ICR register *******************/
5903 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
5904 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
5905 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
5906 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
5907 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
5908 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
5909 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
5910 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
5911 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
5912 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
5913 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
5914 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
5915 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
5916
5917 /****************** Bit definition for SDIO_MASK register *******************/
5918 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
5919 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
5920 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
5921 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
5922 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
5923 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
5924 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
5925 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
5926 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
5927 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
5928 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
5929 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
5930 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
5931 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
5932 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
5933 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
5934 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
5935 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
5936 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
5937 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
5938 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
5939 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
5940 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
5941 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
5942
5943 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5944 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
5945
5946 /****************** Bit definition for SDIO_FIFO register *******************/
5947 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
5948
5949 /******************************************************************************/
5950 /* */
5951 /* Serial Peripheral Interface */
5952 /* */
5953 /******************************************************************************/
5954 /******************* Bit definition for SPI_CR1 register ********************/
5955 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
5956 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
5957 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
5958
5959 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
5960 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
5961 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
5962 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
5963
5964 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
5965 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
5966 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
5967 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
5968 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
5969 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
5970 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
5971 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
5972 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
5973 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
5974
5975 /******************* Bit definition for SPI_CR2 register ********************/
5976 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
5977 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
5978 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
5979 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
5980 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
5981 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
5982 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
5983
5984 /******************** Bit definition for SPI_SR register ********************/
5985 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
5986 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
5987 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
5988 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
5989 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
5990 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
5991 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
5992 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
5993 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
5994
5995 /******************** Bit definition for SPI_DR register ********************/
5996 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
5997
5998 /******************* Bit definition for SPI_CRCPR register ******************/
5999 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
6000
6001 /****************** Bit definition for SPI_RXCRCR register ******************/
6002 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
6003
6004 /****************** Bit definition for SPI_TXCRCR register ******************/
6005 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
6006
6007 /****************** Bit definition for SPI_I2SCFGR register *****************/
6008 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
6009
6010 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
6011 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
6012 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
6013
6014 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
6015
6016 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
6017 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6018 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6019
6020 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
6021
6022 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
6023 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6024 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6025
6026 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
6027 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
6028
6029 /****************** Bit definition for SPI_I2SPR register *******************/
6030 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
6031 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
6032 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
6033
6034 /******************************************************************************/
6035 /* */
6036 /* SYSCFG */
6037 /* */
6038 /******************************************************************************/
6039 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
6040 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
6041 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
6042 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
6043 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
6044
6045 /****************** Bit definition for SYSCFG_PMC register ******************/
6046 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
6047
6048 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6049 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
6050 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
6051 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
6052 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
6053 /**
6054 * @brief EXTI0 configuration
6055 */
6056 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
6057 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
6058 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
6059 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
6060 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
6061 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
6062 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
6063 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
6064 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
6065
6066 /**
6067 * @brief EXTI1 configuration
6068 */
6069 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
6070 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
6071 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
6072 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
6073 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
6074 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
6075 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
6076 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
6077 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
6078
6079 /**
6080 * @brief EXTI2 configuration
6081 */
6082 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
6083 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
6084 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
6085 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
6086 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
6087 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
6088 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
6089 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
6090 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
6091
6092 /**
6093 * @brief EXTI3 configuration
6094 */
6095 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
6096 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
6097 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
6098 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
6099 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
6100 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
6101 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
6102 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
6103 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
6104
6105 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6106 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
6107 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
6108 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
6109 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
6110 /**
6111 * @brief EXTI4 configuration
6112 */
6113 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
6114 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
6115 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
6116 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
6117 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
6118 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
6119 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
6120 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
6121 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
6122
6123 /**
6124 * @brief EXTI5 configuration
6125 */
6126 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
6127 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
6128 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
6129 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
6130 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
6131 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
6132 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
6133 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
6134 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
6135
6136 /**
6137 * @brief EXTI6 configuration
6138 */
6139 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
6140 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
6141 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
6142 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
6143 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
6144 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
6145 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
6146 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
6147 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
6148
6149 /**
6150 * @brief EXTI7 configuration
6151 */
6152 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
6153 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
6154 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
6155 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
6156 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
6157 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
6158 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
6159 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
6160 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
6161
6162
6163 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6164 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
6165 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
6166 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
6167 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
6168
6169 /**
6170 * @brief EXTI8 configuration
6171 */
6172 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
6173 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
6174 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
6175 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
6176 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
6177 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
6178 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
6179 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
6180 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
6181
6182 /**
6183 * @brief EXTI9 configuration
6184 */
6185 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
6186 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
6187 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
6188 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
6189 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
6190 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
6191 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
6192 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
6193 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
6194
6195 /**
6196 * @brief EXTI10 configuration
6197 */
6198 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
6199 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
6200 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
6201 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
6202 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
6203 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
6204 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
6205 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
6206 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
6207
6208 /**
6209 * @brief EXTI11 configuration
6210 */
6211 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
6212 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
6213 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
6214 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
6215 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
6216 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
6217 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
6218 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
6219 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
6220
6221 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
6222 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
6223 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
6224 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
6225 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
6226 /**
6227 * @brief EXTI12 configuration
6228 */
6229 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
6230 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
6231 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
6232 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
6233 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
6234 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
6235 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
6236 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
6237
6238 /**
6239 * @brief EXTI13 configuration
6240 */
6241 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
6242 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
6243 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
6244 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
6245 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
6246 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
6247 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
6248 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
6249
6250 /**
6251 * @brief EXTI14 configuration
6252 */
6253 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
6254 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
6255 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
6256 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
6257 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
6258 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
6259 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
6260 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
6261
6262 /**
6263 * @brief EXTI15 configuration
6264 */
6265 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
6266 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
6267 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
6268 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
6269 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
6270 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
6271 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
6272 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
6273
6274 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6275 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
6276 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
6277
6278 /******************************************************************************/
6279 /* */
6280 /* TIM */
6281 /* */
6282 /******************************************************************************/
6283 /******************* Bit definition for TIM_CR1 register ********************/
6284 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
6285 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
6286 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
6287 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
6288 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
6289
6290 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
6291 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
6292 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
6293
6294 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
6295
6296 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
6297 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
6298 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
6299
6300 /******************* Bit definition for TIM_CR2 register ********************/
6301 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
6302 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
6303 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
6304
6305 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
6306 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
6307 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
6308 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
6309
6310 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
6311 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
6312 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
6313 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
6314 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
6315 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
6316 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
6317 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
6318
6319 /******************* Bit definition for TIM_SMCR register *******************/
6320 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
6321 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
6322 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
6323 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
6324
6325 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
6326 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
6327 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
6328 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
6329
6330 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
6331
6332 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
6333 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
6334 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
6335 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
6336 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
6337
6338 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
6339 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
6340 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
6341
6342 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
6343 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
6344
6345 /******************* Bit definition for TIM_DIER register *******************/
6346 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
6347 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
6348 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
6349 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
6350 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
6351 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
6352 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
6353 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
6354 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
6355 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
6356 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
6357 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
6358 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
6359 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
6360 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
6361
6362 /******************** Bit definition for TIM_SR register ********************/
6363 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
6364 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
6365 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
6366 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
6367 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
6368 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
6369 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
6370 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
6371 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
6372 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
6373 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
6374 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
6375
6376 /******************* Bit definition for TIM_EGR register ********************/
6377 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
6378 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
6379 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
6380 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
6381 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
6382 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
6383 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
6384 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
6385
6386 /****************** Bit definition for TIM_CCMR1 register *******************/
6387 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6388 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
6389 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
6390
6391 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
6392 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
6393
6394 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6395 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
6396 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
6397 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
6398
6399 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
6400
6401 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6402 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
6403 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
6404
6405 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
6406 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
6407
6408 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6409 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
6410 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
6411 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
6412
6413 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
6414
6415 /*----------------------------------------------------------------------------*/
6416
6417 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6418 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
6419 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
6420
6421 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6422 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
6423 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
6424 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
6425 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
6426
6427 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6428 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
6429 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
6430
6431 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6432 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
6433 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
6434 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
6435 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
6436
6437 /****************** Bit definition for TIM_CCMR2 register *******************/
6438 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6439 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
6440 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
6441
6442 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
6443 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
6444
6445 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6446 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
6447 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
6448 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
6449
6450 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
6451
6452 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6453 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
6454 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
6455
6456 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
6457 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
6458
6459 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6460 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
6461 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
6462 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
6463
6464 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
6465
6466 /*----------------------------------------------------------------------------*/
6467
6468 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6469 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
6470 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
6471
6472 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6473 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
6474 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
6475 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
6476 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
6477
6478 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6479 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
6480 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
6481
6482 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6483 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
6484 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
6485 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
6486 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
6487
6488 /******************* Bit definition for TIM_CCER register *******************/
6489 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
6490 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
6491 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
6492 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
6493 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
6494 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
6495 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
6496 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
6497 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
6498 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
6499 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
6500 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
6501 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
6502 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
6503 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
6504
6505 /******************* Bit definition for TIM_CNT register ********************/
6506 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
6507
6508 /******************* Bit definition for TIM_PSC register ********************/
6509 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
6510
6511 /******************* Bit definition for TIM_ARR register ********************/
6512 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
6513
6514 /******************* Bit definition for TIM_RCR register ********************/
6515 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
6516
6517 /******************* Bit definition for TIM_CCR1 register *******************/
6518 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
6519
6520 /******************* Bit definition for TIM_CCR2 register *******************/
6521 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
6522
6523 /******************* Bit definition for TIM_CCR3 register *******************/
6524 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
6525
6526 /******************* Bit definition for TIM_CCR4 register *******************/
6527 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
6528
6529 /******************* Bit definition for TIM_BDTR register *******************/
6530 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6531 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
6532 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
6533 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
6534 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
6535 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
6536 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
6537 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
6538 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
6539
6540 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
6541 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
6542 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
6543
6544 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
6545 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
6546 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
6547 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
6548 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
6549 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
6550
6551 /******************* Bit definition for TIM_DCR register ********************/
6552 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
6553 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
6554 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
6555 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
6556 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
6557 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
6558
6559 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
6560 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
6561 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
6562 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
6563 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
6564 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
6565
6566 /******************* Bit definition for TIM_DMAR register *******************/
6567 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
6568
6569 /******************* Bit definition for TIM_OR register *********************/
6570 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
6571 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
6572 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
6573 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
6574 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
6575 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
6576
6577
6578 /******************************************************************************/
6579 /* */
6580 /* Universal Synchronous Asynchronous Receiver Transmitter */
6581 /* */
6582 /******************************************************************************/
6583 /******************* Bit definition for USART_SR register *******************/
6584 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
6585 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
6586 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
6587 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
6588 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
6589 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
6590 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
6591 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
6592 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
6593 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
6594
6595 /******************* Bit definition for USART_DR register *******************/
6596 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
6597
6598 /****************** Bit definition for USART_BRR register *******************/
6599 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
6600 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
6601
6602 /****************** Bit definition for USART_CR1 register *******************/
6603 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
6604 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
6605 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
6606 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
6607 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
6608 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
6609 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
6610 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
6611 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
6612 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
6613 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
6614 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
6615 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
6616 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
6617 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
6618
6619 /****************** Bit definition for USART_CR2 register *******************/
6620 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
6621 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
6622 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
6623 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
6624 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
6625 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
6626 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
6627
6628 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
6629 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
6630 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
6631
6632 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
6633
6634 /****************** Bit definition for USART_CR3 register *******************/
6635 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
6636 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
6637 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
6638 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
6639 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
6640 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
6641 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
6642 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
6643 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
6644 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
6645 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
6646 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
6647
6648 /****************** Bit definition for USART_GTPR register ******************/
6649 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
6650 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
6651 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
6652 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
6653 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
6654 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
6655 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
6656 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
6657 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
6658
6659 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
6660
6661 /******************************************************************************/
6662 /* */
6663 /* Window WATCHDOG */
6664 /* */
6665 /******************************************************************************/
6666 /******************* Bit definition for WWDG_CR register ********************/
6667 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
6668 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
6669 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
6670 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
6671 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
6672 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
6673 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
6674 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
6675
6676 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
6677
6678 /******************* Bit definition for WWDG_CFR register *******************/
6679 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
6680 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
6681 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
6682 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
6683 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
6684 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
6685 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
6686 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
6687
6688 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
6689 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
6690 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
6691
6692 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
6693
6694 /******************* Bit definition for WWDG_SR register ********************/
6695 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
6696
6697
6698 /******************************************************************************/
6699 /* */
6700 /* DBG */
6701 /* */
6702 /******************************************************************************/
6703 /******************** Bit definition for DBGMCU_IDCODE register *************/
6704 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
6705 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
6706
6707 /******************** Bit definition for DBGMCU_CR register *****************/
6708 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
6709 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
6710 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
6711 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
6712
6713 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
6714 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
6715 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
6716
6717 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6718 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
6719 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
6720 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
6721 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
6722 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
6723 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
6724 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
6725 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
6726 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
6727 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
6728 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
6729 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
6730 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
6731 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
6732 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
6733 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
6734 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
6735 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
6736 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
6737
6738 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6739 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
6740 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
6741 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
6742 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
6743 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
6744
6745 /******************************************************************************/
6746 /* */
6747 /* Ethernet MAC Registers bits definitions */
6748 /* */
6749 /******************************************************************************/
6750 /* Bit definition for Ethernet MAC Control Register register */
6751 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
6752 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
6753 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
6754 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
6755 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
6756 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
6757 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
6758 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
6759 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
6760 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
6761 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
6762 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
6763 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
6764 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
6765 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
6766 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
6767 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
6768 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
6769 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
6770 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
6771 a transmission attempt during retries after a collision: 0 =< r <2^k */
6772 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
6773 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
6774 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
6775 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
6776 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
6777 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
6778 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
6779
6780 /* Bit definition for Ethernet MAC Frame Filter Register */
6781 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
6782 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
6783 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
6784 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
6785 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
6786 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
6787 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
6788 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
6789 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
6790 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
6791 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
6792 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
6793 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
6794 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
6795
6796 /* Bit definition for Ethernet MAC Hash Table High Register */
6797 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
6798
6799 /* Bit definition for Ethernet MAC Hash Table Low Register */
6800 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
6801
6802 /* Bit definition for Ethernet MAC MII Address Register */
6803 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
6804 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
6805 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
6806 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
6807 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
6808 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
6809 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
6810 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
6811 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
6812 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
6813
6814 /* Bit definition for Ethernet MAC MII Data Register */
6815 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
6816
6817 /* Bit definition for Ethernet MAC Flow Control Register */
6818 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
6819 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
6820 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
6821 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
6822 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
6823 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
6824 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
6825 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
6826 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
6827 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
6828 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
6829
6830 /* Bit definition for Ethernet MAC VLAN Tag Register */
6831 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
6832 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
6833
6834 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
6835 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
6836 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
6837 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
6838 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
6839 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
6840 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
6841 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
6842 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
6843 RSVD - Filter1 Command - RSVD - Filter0 Command
6844 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
6845 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
6846 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
6847
6848 /* Bit definition for Ethernet MAC PMT Control and Status Register */
6849 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
6850 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
6851 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
6852 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
6853 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
6854 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
6855 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
6856
6857 /* Bit definition for Ethernet MAC Status Register */
6858 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
6859 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
6860 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
6861 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
6862 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
6863
6864 /* Bit definition for Ethernet MAC Interrupt Mask Register */
6865 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
6866 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
6867
6868 /* Bit definition for Ethernet MAC Address0 High Register */
6869 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
6870
6871 /* Bit definition for Ethernet MAC Address0 Low Register */
6872 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
6873
6874 /* Bit definition for Ethernet MAC Address1 High Register */
6875 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
6876 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
6877 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
6878 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6879 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6880 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6881 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6882 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6883 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
6884 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
6885
6886 /* Bit definition for Ethernet MAC Address1 Low Register */
6887 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
6888
6889 /* Bit definition for Ethernet MAC Address2 High Register */
6890 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
6891 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
6892 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
6893 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6894 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6895 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6896 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6897 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6898 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
6899 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
6900
6901 /* Bit definition for Ethernet MAC Address2 Low Register */
6902 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
6903
6904 /* Bit definition for Ethernet MAC Address3 High Register */
6905 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
6906 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
6907 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
6908 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6909 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6910 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6911 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6912 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6913 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
6914 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
6915
6916 /* Bit definition for Ethernet MAC Address3 Low Register */
6917 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
6918
6919 /******************************************************************************/
6920 /* Ethernet MMC Registers bits definition */
6921 /******************************************************************************/
6922
6923 /* Bit definition for Ethernet MMC Contol Register */
6924 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
6925 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
6926 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
6927 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
6928 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
6929 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
6930
6931 /* Bit definition for Ethernet MMC Receive Interrupt Register */
6932 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
6933 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
6934 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
6935
6936 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
6937 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
6938 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
6939 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
6940
6941 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
6942 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
6943 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
6944 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
6945
6946 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
6947 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
6948 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
6949 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
6950
6951 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
6952 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
6953
6954 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
6955 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
6956
6957 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
6958 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
6959
6960 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
6961 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
6962
6963 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
6964 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
6965
6966 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
6967 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
6968
6969 /******************************************************************************/
6970 /* Ethernet PTP Registers bits definition */
6971 /******************************************************************************/
6972
6973 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
6974 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
6975 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
6976 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
6977 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
6978 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
6979 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
6980 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
6981 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
6982 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
6983
6984 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
6985 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
6986 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
6987 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
6988 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
6989 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
6990
6991 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
6992 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
6993
6994 /* Bit definition for Ethernet PTP Time Stamp High Register */
6995 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
6996
6997 /* Bit definition for Ethernet PTP Time Stamp Low Register */
6998 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
6999 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
7000
7001 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
7002 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
7003
7004 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
7005 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
7006 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
7007
7008 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
7009 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
7010
7011 /* Bit definition for Ethernet PTP Target Time High Register */
7012 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
7013
7014 /* Bit definition for Ethernet PTP Target Time Low Register */
7015 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
7016
7017 /* Bit definition for Ethernet PTP Time Stamp Status Register */
7018 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
7019 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
7020
7021 /******************************************************************************/
7022 /* Ethernet DMA Registers bits definition */
7023 /******************************************************************************/
7024
7025 /* Bit definition for Ethernet DMA Bus Mode Register */
7026 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
7027 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
7028 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
7029 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
7030 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
7031 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
7032 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7033 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7034 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7035 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7036 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7037 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7038 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7039 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7040 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
7041 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
7042 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
7043 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
7044 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
7045 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
7046 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
7047 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
7048 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
7049 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
7050 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
7051 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7052 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7053 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7054 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7055 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7056 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7057 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7058 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7059 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
7060 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
7061 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
7062 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
7063 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
7064 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
7065
7066 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
7067 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
7068
7069 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
7070 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
7071
7072 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
7073 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
7074
7075 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
7076 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
7077
7078 /* Bit definition for Ethernet DMA Status Register */
7079 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
7080 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
7081 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
7082 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
7083 /* combination with EBS[2:0] for GetFlagStatus function */
7084 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
7085 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
7086 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
7087 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
7088 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
7089 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
7090 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
7091 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
7092 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
7093 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
7094 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
7095 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
7096 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
7097 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
7098 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
7099 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
7100 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
7101 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
7102 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
7103 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
7104 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
7105 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
7106 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
7107 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
7108 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
7109 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
7110 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
7111 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
7112 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
7113 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
7114 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
7115 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
7116
7117 /* Bit definition for Ethernet DMA Operation Mode Register */
7118 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
7119 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
7120 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
7121 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
7122 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
7123 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
7124 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
7125 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
7126 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
7127 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
7128 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
7129 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
7130 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
7131 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
7132 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
7133 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
7134 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
7135 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
7136 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
7137 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
7138 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
7139 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
7140 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
7141 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
7142
7143 /* Bit definition for Ethernet DMA Interrupt Enable Register */
7144 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
7145 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
7146 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
7147 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
7148 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
7149 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
7150 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
7151 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
7152 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
7153 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
7154 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
7155 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
7156 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
7157 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
7158 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
7159
7160 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
7161 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
7162 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
7163 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
7164 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
7165
7166 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
7167 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
7168
7169 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
7170 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
7171
7172 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
7173 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
7174
7175 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
7176 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
7177
7178 /******************************************************************************/
7179 /* */
7180 /* USB_OTG */
7181 /* */
7182 /******************************************************************************/
7183 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
7184 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
7185 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
7186 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
7187 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
7188 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
7189 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
7190 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
7191 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
7192 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
7193 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
7194
7195 /******************** Bit definition forUSB_OTG_HCFG register ********************/
7196
7197 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
7198 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7199 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7200 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
7201
7202 /******************** Bit definition forUSB_OTG_DCFG register ********************/
7203
7204 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
7205 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7206 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7207 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
7208
7209 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
7210 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7211 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7212 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7213 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
7214 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
7215 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
7216 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
7217
7218 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
7219 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
7220 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
7221
7222 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
7223 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
7224 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
7225
7226 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
7227 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
7228 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
7229 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
7230
7231 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
7232 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
7233 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
7234 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
7235 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
7236 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
7237 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
7238
7239 /******************** Bit definition forUSB_OTG_DCTL register ********************/
7240 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
7241 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
7242 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
7243 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
7244
7245 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
7246 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7247 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7248 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7249 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
7250 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
7251 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
7252 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
7253 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
7254
7255 /******************** Bit definition forUSB_OTG_HFIR register ********************/
7256 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
7257
7258 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
7259 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
7260 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
7261
7262 /******************** Bit definition forUSB_OTG_DSTS register ********************/
7263 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
7264
7265 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
7266 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
7267 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
7268 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
7269 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
7270
7271 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
7272 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
7273
7274 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
7275 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
7276 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
7277 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
7278 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
7279 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
7280 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
7281 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
7282
7283 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
7284
7285 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
7286 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7287 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7288 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7289 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
7290 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
7291 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
7292
7293 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
7294 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
7295 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
7296 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
7297 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
7298 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
7299 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
7300 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
7301 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
7302 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
7303 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
7304 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
7305 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
7306 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
7307 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
7308 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
7309 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
7310 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
7311
7312 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
7313 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
7314 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
7315 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
7316 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
7317 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
7318
7319 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
7320 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
7321 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
7322 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
7323 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
7324 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
7325 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
7326 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
7327
7328 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
7329 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
7330 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
7331 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
7332 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
7333 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
7334 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
7335 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
7336 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
7337
7338 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
7339 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
7340
7341 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
7342 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
7343 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
7344 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
7345 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
7346 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
7347 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
7348 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
7349 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
7350
7351 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
7352 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
7353 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
7354 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
7355 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
7356 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
7357 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
7358 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
7359 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
7360
7361 /******************** Bit definition forUSB_OTG_HAINT register ********************/
7362 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
7363
7364 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
7365 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
7366 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
7367 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
7368 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
7369 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
7370 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
7371 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
7372
7373 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
7374 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
7375 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
7376 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
7377 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
7378 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
7379 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
7380 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
7381 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
7382 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
7383 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
7384 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
7385 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
7386 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
7387 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
7388 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
7389 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
7390 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
7391 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
7392 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
7393 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
7394 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
7395 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
7396 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
7397 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
7398 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
7399 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
7400
7401 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
7402 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
7403 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
7404 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
7405 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
7406 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
7407 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
7408 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
7409 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
7410 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
7411 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
7412 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
7413 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
7414 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
7415 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
7416 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
7417 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
7418 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
7419 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
7420 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
7421 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
7422 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
7423 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
7424 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
7425 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
7426 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
7427 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
7428
7429 /******************** Bit definition forUSB_OTG_DAINT register ********************/
7430 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
7431 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
7432
7433 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
7434 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
7435
7436 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
7437 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
7438 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
7439 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
7440 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
7441
7442 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
7443 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
7444 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
7445
7446 /******************** Bit definition for OTG register ********************/
7447
7448 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
7449 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7450 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7451 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7452 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7453 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
7454
7455 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
7456 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
7457 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
7458
7459 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
7460 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
7461 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
7462 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
7463 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
7464
7465 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
7466 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7467 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7468 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7469 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7470
7471 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
7472 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
7473 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
7474 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
7475 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
7476
7477 /******************** Bit definition for OTG register ********************/
7478
7479 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
7480 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7481 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7482 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7483 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7484 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
7485
7486 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
7487 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
7488 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
7489
7490 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
7491 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
7492 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
7493 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
7494 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
7495
7496 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
7497 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7498 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7499 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7500 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7501
7502 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
7503 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
7504 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
7505 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
7506 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
7507
7508 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
7509 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
7510
7511 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
7512 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
7513
7514 /******************** Bit definition for OTG register ********************/
7515 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
7516 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
7517 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
7518 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
7519
7520 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
7521 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
7522
7523 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
7524 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
7525
7526 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
7527 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
7528 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
7529 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
7530 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
7531 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
7532 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
7533 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
7534 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
7535
7536 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
7537 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
7538 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
7539 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
7540 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
7541 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
7542 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
7543 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
7544
7545 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
7546 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
7547 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
7548
7549 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
7550 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
7551 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
7552 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
7553 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
7554 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
7555 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
7556 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
7557 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
7558 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
7559 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
7560
7561 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
7562 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
7563 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
7564 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
7565 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
7566 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
7567 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
7568 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
7569 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
7570 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
7571 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
7572
7573 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
7574 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
7575
7576 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
7577 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
7578 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
7579
7580 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
7581 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
7582 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
7583 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
7584 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
7585 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
7586 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
7587
7588 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
7589 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
7590 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
7591
7592 /******************** Bit definition forUSB_OTG_CID register ********************/
7593 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
7594
7595 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
7596 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
7597 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
7598 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
7599 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
7600 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
7601 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
7602 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
7603 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
7604 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
7605
7606 /******************** Bit definition forUSB_OTG_HPRT register ********************/
7607 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
7608 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
7609 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
7610 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
7611 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
7612 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
7613 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
7614 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
7615 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
7616
7617 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
7618 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
7619 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
7620 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
7621
7622 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
7623 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
7624 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
7625 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
7626 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
7627
7628 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
7629 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
7630 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
7631
7632 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
7633 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
7634 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
7635 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
7636 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
7637 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
7638 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
7639 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
7640 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
7641 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
7642 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
7643 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
7644
7645 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
7646 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
7647 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
7648
7649 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
7650 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
7651 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
7652 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
7653 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
7654
7655 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
7656 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
7657 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
7658 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
7659
7660 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
7661 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
7662 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
7663 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
7664 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
7665 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
7666 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
7667 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
7668 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
7669 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
7670 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
7671
7672 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
7673 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
7674
7675 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
7676 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
7677 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
7678 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
7679 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
7680 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
7681 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
7682
7683 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
7684 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
7685 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
7686
7687 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
7688 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
7689 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
7690
7691 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
7692 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
7693 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
7694 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
7695 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
7696 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
7697 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
7698 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
7699 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
7700 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
7701 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
7702
7703 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
7704
7705 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
7706 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7707 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7708 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7709 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7710 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
7711 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
7712 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
7713
7714 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
7715 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
7716 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
7717 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
7718 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
7719 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
7720 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
7721 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
7722
7723 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
7724 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
7725 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
7726 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
7727 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
7728
7729 /******************** Bit definition forUSB_OTG_HCINT register ********************/
7730 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
7731 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
7732 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
7733 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
7734 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
7735 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
7736 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
7737 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
7738 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
7739 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
7740 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
7741
7742 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
7743 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
7744 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
7745 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
7746 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
7747 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
7748 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
7749 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
7750 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
7751 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
7752 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
7753 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
7754
7755 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
7756 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
7757 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
7758 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
7759 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
7760 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
7761 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
7762 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
7763 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
7764 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
7765 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
7766 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
7767
7768 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
7769
7770 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
7771 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
7772 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
7773 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
7774 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
7775 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
7776 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
7777 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
7778 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
7779 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
7780
7781 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
7782 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
7783
7784 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
7785 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
7786
7787 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
7788 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
7789
7790 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
7791 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
7792 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
7793
7794 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
7795
7796 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
7797 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
7798 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
7799 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
7800 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
7801 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
7802 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
7803 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
7804 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
7805 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
7806 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
7807 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
7808 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
7809 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
7810
7811 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
7812 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
7813 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
7814 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
7815 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
7816 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
7817 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
7818
7819 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
7820
7821 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
7822 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
7823
7824 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
7825 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
7826 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
7827
7828 /******************** Bit definition for PCGCCTL register ********************/
7829 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
7830 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
7831 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
7832
7833 /**
7834 * @}
7835 */
7836
7837 /**
7838 * @}
7839 */
7840
7841 /** @addtogroup Exported_macros
7842 * @{
7843 */
7844
7845 /******************************* ADC Instances ********************************/
7846 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
7847 ((INSTANCE) == ADC2) || \
7848 ((INSTANCE) == ADC3))
7849
7850 /******************************* CAN Instances ********************************/
7851 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
7852 ((INSTANCE) == CAN2))
7853
7854 /******************************* CRC Instances ********************************/
7855 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7856
7857 /******************************* DAC Instances ********************************/
7858 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
7859
7860 /******************************* DCMI Instances *******************************/
7861 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
7862
7863 /******************************** DMA Instances *******************************/
7864 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
7865 ((INSTANCE) == DMA1_Stream1) || \
7866 ((INSTANCE) == DMA1_Stream2) || \
7867 ((INSTANCE) == DMA1_Stream3) || \
7868 ((INSTANCE) == DMA1_Stream4) || \
7869 ((INSTANCE) == DMA1_Stream5) || \
7870 ((INSTANCE) == DMA1_Stream6) || \
7871 ((INSTANCE) == DMA1_Stream7) || \
7872 ((INSTANCE) == DMA2_Stream0) || \
7873 ((INSTANCE) == DMA2_Stream1) || \
7874 ((INSTANCE) == DMA2_Stream2) || \
7875 ((INSTANCE) == DMA2_Stream3) || \
7876 ((INSTANCE) == DMA2_Stream4) || \
7877 ((INSTANCE) == DMA2_Stream5) || \
7878 ((INSTANCE) == DMA2_Stream6) || \
7879 ((INSTANCE) == DMA2_Stream7))
7880
7881 /******************************* GPIO Instances *******************************/
7882 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7883 ((INSTANCE) == GPIOB) || \
7884 ((INSTANCE) == GPIOC) || \
7885 ((INSTANCE) == GPIOD) || \
7886 ((INSTANCE) == GPIOE) || \
7887 ((INSTANCE) == GPIOF) || \
7888 ((INSTANCE) == GPIOG) || \
7889 ((INSTANCE) == GPIOH) || \
7890 ((INSTANCE) == GPIOI))
7891
7892 /******************************** I2C Instances *******************************/
7893 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7894 ((INSTANCE) == I2C2) || \
7895 ((INSTANCE) == I2C3))
7896
7897 /******************************** I2S Instances *******************************/
7898 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
7899 ((INSTANCE) == SPI3))
7900
7901 /*************************** I2S Extended Instances ***************************/
7902 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
7903 ((INSTANCE) == SPI3) || \
7904 ((INSTANCE) == I2S2ext) || \
7905 ((INSTANCE) == I2S3ext))
7906
7907 /******************************* RNG Instances ********************************/
7908 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
7909
7910 /****************************** RTC Instances *********************************/
7911 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7912
7913 /******************************** SPI Instances *******************************/
7914 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7915 ((INSTANCE) == SPI2) || \
7916 ((INSTANCE) == SPI3))
7917
7918 /*************************** SPI Extended Instances ***************************/
7919 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
7920 ((INSTANCE) == SPI2) || \
7921 ((INSTANCE) == SPI3) || \
7922 ((INSTANCE) == I2S2ext) || \
7923 ((INSTANCE) == I2S3ext))
7924
7925 /****************** TIM Instances : All supported instances *******************/
7926 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7927 ((INSTANCE) == TIM2) || \
7928 ((INSTANCE) == TIM3) || \
7929 ((INSTANCE) == TIM4) || \
7930 ((INSTANCE) == TIM5) || \
7931 ((INSTANCE) == TIM6) || \
7932 ((INSTANCE) == TIM7) || \
7933 ((INSTANCE) == TIM8) || \
7934 ((INSTANCE) == TIM9) || \
7935 ((INSTANCE) == TIM10) || \
7936 ((INSTANCE) == TIM11) || \
7937 ((INSTANCE) == TIM12) || \
7938 ((INSTANCE) == TIM13) || \
7939 ((INSTANCE) == TIM14))
7940
7941 /************* TIM Instances : at least 1 capture/compare channel *************/
7942 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7943 ((INSTANCE) == TIM2) || \
7944 ((INSTANCE) == TIM3) || \
7945 ((INSTANCE) == TIM4) || \
7946 ((INSTANCE) == TIM5) || \
7947 ((INSTANCE) == TIM8) || \
7948 ((INSTANCE) == TIM9) || \
7949 ((INSTANCE) == TIM10) || \
7950 ((INSTANCE) == TIM11) || \
7951 ((INSTANCE) == TIM12) || \
7952 ((INSTANCE) == TIM13) || \
7953 ((INSTANCE) == TIM14))
7954
7955 /************ TIM Instances : at least 2 capture/compare channels *************/
7956 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7957 ((INSTANCE) == TIM2) || \
7958 ((INSTANCE) == TIM3) || \
7959 ((INSTANCE) == TIM4) || \
7960 ((INSTANCE) == TIM5) || \
7961 ((INSTANCE) == TIM8) || \
7962 ((INSTANCE) == TIM9) || \
7963 ((INSTANCE) == TIM12))
7964
7965 /************ TIM Instances : at least 3 capture/compare channels *************/
7966 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7967 ((INSTANCE) == TIM2) || \
7968 ((INSTANCE) == TIM3) || \
7969 ((INSTANCE) == TIM4) || \
7970 ((INSTANCE) == TIM5) || \
7971 ((INSTANCE) == TIM8))
7972
7973 /************ TIM Instances : at least 4 capture/compare channels *************/
7974 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7975 ((INSTANCE) == TIM2) || \
7976 ((INSTANCE) == TIM3) || \
7977 ((INSTANCE) == TIM4) || \
7978 ((INSTANCE) == TIM5) || \
7979 ((INSTANCE) == TIM8))
7980
7981 /******************** TIM Instances : Advanced-control timers *****************/
7982 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7983 ((INSTANCE) == TIM8))
7984
7985 /******************* TIM Instances : Timer input XOR function *****************/
7986 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7987 ((INSTANCE) == TIM2) || \
7988 ((INSTANCE) == TIM3) || \
7989 ((INSTANCE) == TIM4) || \
7990 ((INSTANCE) == TIM5) || \
7991 ((INSTANCE) == TIM8))
7992
7993 /****************** TIM Instances : DMA requests generation (UDE) *************/
7994 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7995 ((INSTANCE) == TIM2) || \
7996 ((INSTANCE) == TIM3) || \
7997 ((INSTANCE) == TIM4) || \
7998 ((INSTANCE) == TIM5) || \
7999 ((INSTANCE) == TIM6) || \
8000 ((INSTANCE) == TIM7) || \
8001 ((INSTANCE) == TIM8))
8002
8003 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
8004 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8005 ((INSTANCE) == TIM2) || \
8006 ((INSTANCE) == TIM3) || \
8007 ((INSTANCE) == TIM4) || \
8008 ((INSTANCE) == TIM5) || \
8009 ((INSTANCE) == TIM8))
8010
8011 /************ TIM Instances : DMA requests generation (COMDE) *****************/
8012 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8013 ((INSTANCE) == TIM2) || \
8014 ((INSTANCE) == TIM3) || \
8015 ((INSTANCE) == TIM4) || \
8016 ((INSTANCE) == TIM5) || \
8017 ((INSTANCE) == TIM8))
8018
8019 /******************** TIM Instances : DMA burst feature ***********************/
8020 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8021 ((INSTANCE) == TIM2) || \
8022 ((INSTANCE) == TIM3) || \
8023 ((INSTANCE) == TIM4) || \
8024 ((INSTANCE) == TIM5) || \
8025 ((INSTANCE) == TIM8))
8026
8027 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8028 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8029 ((INSTANCE) == TIM2) || \
8030 ((INSTANCE) == TIM3) || \
8031 ((INSTANCE) == TIM4) || \
8032 ((INSTANCE) == TIM5) || \
8033 ((INSTANCE) == TIM6) || \
8034 ((INSTANCE) == TIM7) || \
8035 ((INSTANCE) == TIM8) || \
8036 ((INSTANCE) == TIM9) || \
8037 ((INSTANCE) == TIM12))
8038
8039 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8040 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8041 ((INSTANCE) == TIM2) || \
8042 ((INSTANCE) == TIM3) || \
8043 ((INSTANCE) == TIM4) || \
8044 ((INSTANCE) == TIM5) || \
8045 ((INSTANCE) == TIM8) || \
8046 ((INSTANCE) == TIM9) || \
8047 ((INSTANCE) == TIM12))
8048
8049 /********************** TIM Instances : 32 bit Counter ************************/
8050 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
8051 ((INSTANCE) == TIM5))
8052
8053 /***************** TIM Instances : external trigger input availabe ************/
8054 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8055 ((INSTANCE) == TIM2) || \
8056 ((INSTANCE) == TIM3) || \
8057 ((INSTANCE) == TIM4) || \
8058 ((INSTANCE) == TIM5) || \
8059 ((INSTANCE) == TIM8))
8060
8061 /****************** TIM Instances : remapping capability **********************/
8062 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
8063 ((INSTANCE) == TIM5) || \
8064 ((INSTANCE) == TIM11))
8065
8066 /******************* TIM Instances : output(s) available **********************/
8067 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8068 ((((INSTANCE) == TIM1) && \
8069 (((CHANNEL) == TIM_CHANNEL_1) || \
8070 ((CHANNEL) == TIM_CHANNEL_2) || \
8071 ((CHANNEL) == TIM_CHANNEL_3) || \
8072 ((CHANNEL) == TIM_CHANNEL_4))) \
8073 || \
8074 (((INSTANCE) == TIM2) && \
8075 (((CHANNEL) == TIM_CHANNEL_1) || \
8076 ((CHANNEL) == TIM_CHANNEL_2) || \
8077 ((CHANNEL) == TIM_CHANNEL_3) || \
8078 ((CHANNEL) == TIM_CHANNEL_4))) \
8079 || \
8080 (((INSTANCE) == TIM3) && \
8081 (((CHANNEL) == TIM_CHANNEL_1) || \
8082 ((CHANNEL) == TIM_CHANNEL_2) || \
8083 ((CHANNEL) == TIM_CHANNEL_3) || \
8084 ((CHANNEL) == TIM_CHANNEL_4))) \
8085 || \
8086 (((INSTANCE) == TIM4) && \
8087 (((CHANNEL) == TIM_CHANNEL_1) || \
8088 ((CHANNEL) == TIM_CHANNEL_2) || \
8089 ((CHANNEL) == TIM_CHANNEL_3) || \
8090 ((CHANNEL) == TIM_CHANNEL_4))) \
8091 || \
8092 (((INSTANCE) == TIM5) && \
8093 (((CHANNEL) == TIM_CHANNEL_1) || \
8094 ((CHANNEL) == TIM_CHANNEL_2) || \
8095 ((CHANNEL) == TIM_CHANNEL_3) || \
8096 ((CHANNEL) == TIM_CHANNEL_4))) \
8097 || \
8098 (((INSTANCE) == TIM8) && \
8099 (((CHANNEL) == TIM_CHANNEL_1) || \
8100 ((CHANNEL) == TIM_CHANNEL_2) || \
8101 ((CHANNEL) == TIM_CHANNEL_3) || \
8102 ((CHANNEL) == TIM_CHANNEL_4))) \
8103 || \
8104 (((INSTANCE) == TIM9) && \
8105 (((CHANNEL) == TIM_CHANNEL_1) || \
8106 ((CHANNEL) == TIM_CHANNEL_2))) \
8107 || \
8108 (((INSTANCE) == TIM10) && \
8109 (((CHANNEL) == TIM_CHANNEL_1))) \
8110 || \
8111 (((INSTANCE) == TIM11) && \
8112 (((CHANNEL) == TIM_CHANNEL_1))) \
8113 || \
8114 (((INSTANCE) == TIM12) && \
8115 (((CHANNEL) == TIM_CHANNEL_1) || \
8116 ((CHANNEL) == TIM_CHANNEL_2))) \
8117 || \
8118 (((INSTANCE) == TIM13) && \
8119 (((CHANNEL) == TIM_CHANNEL_1))) \
8120 || \
8121 (((INSTANCE) == TIM14) && \
8122 (((CHANNEL) == TIM_CHANNEL_1))))
8123
8124 /************ TIM Instances : complementary output(s) available ***************/
8125 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8126 ((((INSTANCE) == TIM1) && \
8127 (((CHANNEL) == TIM_CHANNEL_1) || \
8128 ((CHANNEL) == TIM_CHANNEL_2) || \
8129 ((CHANNEL) == TIM_CHANNEL_3))) \
8130 || \
8131 (((INSTANCE) == TIM8) && \
8132 (((CHANNEL) == TIM_CHANNEL_1) || \
8133 ((CHANNEL) == TIM_CHANNEL_2) || \
8134 ((CHANNEL) == TIM_CHANNEL_3))))
8135
8136 /******************** USART Instances : Synchronous mode **********************/
8137 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8138 ((INSTANCE) == USART2) || \
8139 ((INSTANCE) == USART3) || \
8140 ((INSTANCE) == USART6))
8141
8142 /******************** UART Instances : Asynchronous mode **********************/
8143 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8144 ((INSTANCE) == USART2) || \
8145 ((INSTANCE) == USART3) || \
8146 ((INSTANCE) == UART4) || \
8147 ((INSTANCE) == UART5) || \
8148 ((INSTANCE) == USART6))
8149
8150 /****************** UART Instances : Hardware Flow control ********************/
8151 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8152 ((INSTANCE) == USART2) || \
8153 ((INSTANCE) == USART3) || \
8154 ((INSTANCE) == USART6))
8155
8156 /********************* UART Instances : Smard card mode ***********************/
8157 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8158 ((INSTANCE) == USART2) || \
8159 ((INSTANCE) == USART3) || \
8160 ((INSTANCE) == USART6))
8161
8162 /*********************** UART Instances : IRDA mode ***************************/
8163 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8164 ((INSTANCE) == USART2) || \
8165 ((INSTANCE) == USART3) || \
8166 ((INSTANCE) == UART4) || \
8167 ((INSTANCE) == UART5) || \
8168 ((INSTANCE) == USART6))
8169
8170 /****************************** IWDG Instances ********************************/
8171 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
8172
8173 /****************************** WWDG Instances ********************************/
8174 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
8175
8176 /****************************** SDIO Instances ********************************/
8177 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
8178
8179 /****************************** USB Exported Constants ************************/
8180 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
8181 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
8182 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
8183 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
8184
8185 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
8186 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
8187 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
8188 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
8189
8190 /******************************************************************************/
8191 /* For a painless codes migration between the STM32F4xx device product */
8192 /* lines, the aliases defined below are put in place to overcome the */
8193 /* differences in the interrupt handlers and IRQn definitions. */
8194 /* No need to update developed interrupt code when moving across */
8195 /* product lines within the same STM32F4 Family */
8196 /******************************************************************************/
8197
8198 /* Aliases for __IRQn */
8199 #define FMC_IRQn FSMC_IRQn
8200
8201 /* Aliases for __IRQHandler */
8202 #define FMC_IRQHandler FSMC_IRQHandler
8203
8204 /**
8205 * @}
8206 */
8207
8208 /**
8209 * @}
8210 */
8211
8212 /**
8213 * @}
8214 */
8215
8216 #ifdef __cplusplus
8217 }
8218 #endif /* __cplusplus */
8219
8220 #endif /* __STM32F4xx_H */
8221
8222
8223
8224 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/