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1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_sdmmc.c
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 26-December-2014
7 * @brief SDMMC Low Layer HAL module driver.
8 *
9 * This file provides firmware functions to manage the following
10 * functionalities of the SDMMC peripheral:
11 * + Initialization/de-initialization functions
12 * + I/O operation functions
13 * + Peripheral Control functions
14 * + Peripheral State functions
15 *
16 @verbatim
17 ==============================================================================
18 ##### SDMMC peripheral features #####
19 ==============================================================================
20 [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
21 peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
22 devices.
23
24 [..] The SDIO features include the following:
25 (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
26 for three different databus modes: 1-bit (default), 4-bit and 8-bit
27 (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
28 (+) Full compliance with SD Memory Card Specifications Version 2.0
29 (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
30 different data bus modes: 1-bit (default) and 4-bit
31 (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
32 Rev1.1)
33 (+) Data transfer up to 48 MHz for the 8 bit mode
34 (+) Data and command output enable signals to control external bidirectional drivers.
35
36
37 ##### How to use this driver #####
38 ==============================================================================
39 [..]
40 This driver is a considered as a driver of service for external devices drivers
41 that interfaces with the SDIO peripheral.
42 According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs
43 is used in the device's driver to perform SDIO operations and functionalities.
44
45 This driver is almost transparent for the final user, it is only used to implement other
46 functionalities of the external device.
47
48 [..]
49 (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
50 (PLL48CLK). Before start working with SDIO peripheral make sure that the
51 PLL is well configured.
52 The SDIO peripheral uses two clock signals:
53 (++) SDIO adapter clock (SDIOCLK = 48 MHz)
54 (++) APB2 bus clock (PCLK2)
55
56 -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
57 Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
58
59 (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
60 peripheral.
61
62 (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
63 function and disable it using the function SDIO_PowerState_OFF(SDIOx).
64
65 (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
66
67 (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT)
68 and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode.
69
70 (+) When using the DMA mode
71 (++) Configure the DMA in the MSP layer of the external device
72 (++) Active the needed channel Request
73 (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
74 __SDIO_DMA_DISABLE().
75
76 (+) To control the CPSM (Command Path State Machine) and send
77 commands to the card use the SDIO_SendCommand(SDIOx),
78 SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
79 to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
80 to the selected command to be sent.
81 The parameters that should be filled are:
82 (++) Command Argument
83 (++) Command Index
84 (++) Command Response type
85 (++) Command Wait
86 (++) CPSM Status (Enable or Disable).
87
88 -@@- To check if the command is well received, read the SDIO_CMDRESP
89 register using the SDIO_GetCommandResponse().
90 The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
91 SDIO_GetResponse() function.
92
93 (+) To control the DPSM (Data Path State Machine) and send/receive
94 data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
95 SDIO_ReadFIFO(), DIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
96
97 *** Read Operations ***
98 =======================
99 [..]
100 (#) First, user has to fill the data structure (pointer to
101 SDIO_DataInitTypeDef) according to the selected data type to be received.
102 The parameters that should be filled are:
103 (++) Data Timeout
104 (++) Data Length
105 (++) Data Block size
106 (++) Data Transfer direction: should be from card (To SDIO)
107 (++) Data Transfer mode
108 (++) DPSM Status (Enable or Disable)
109
110 (#) Configure the SDIO resources to receive the data from the card
111 according to selected transfer mode (Refer to Step 8, 9 and 10).
112
113 (#) Send the selected Read command (refer to step 11).
114
115 (#) Use the SDIO flags/interrupts to check the transfer status.
116
117 *** Write Operations ***
118 ========================
119 [..]
120 (#) First, user has to fill the data structure (pointer to
121 SDIO_DataInitTypeDef) according to the selected data type to be received.
122 The parameters that should be filled are:
123 (++) Data Timeout
124 (++) Data Length
125 (++) Data Block size
126 (++) Data Transfer direction: should be to card (To CARD)
127 (++) Data Transfer mode
128 (++) DPSM Status (Enable or Disable)
129
130 (#) Configure the SDIO resources to send the data to the card according to
131 selected transfer mode.
132
133 (#) Send the selected Write command.
134
135 (#) Use the SDIO flags/interrupts to check the transfer status.
136
137 @endverbatim
138 ******************************************************************************
139 * @attention
140 *
141 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
142 *
143 * Redistribution and use in source and binary forms, with or without modification,
144 * are permitted provided that the following conditions are met:
145 * 1. Redistributions of source code must retain the above copyright notice,
146 * this list of conditions and the following disclaimer.
147 * 2. Redistributions in binary form must reproduce the above copyright notice,
148 * this list of conditions and the following disclaimer in the documentation
149 * and/or other materials provided with the distribution.
150 * 3. Neither the name of STMicroelectronics nor the names of its contributors
151 * may be used to endorse or promote products derived from this software
152 * without specific prior written permission.
153 *
154 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
155 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
156 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
157 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
158 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
159 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
160 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
161 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
162 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
163 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
164 *
165 ******************************************************************************
166 */
167
168 /* Includes ------------------------------------------------------------------*/
169 #include "stm32f4xx_hal.h"
170
171 /** @addtogroup STM32F4xx_HAL_Driver
172 * @{
173 */
174
175 /** @defgroup SDMMC_LL SDMMC Low Layer
176 * @brief Low layer module for SD and MMC driver
177 * @{
178 */
179
180 #if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
181
182 /* Private typedef -----------------------------------------------------------*/
183 /* Private define ------------------------------------------------------------*/
184 /* Private macro -------------------------------------------------------------*/
185 /* Private variables ---------------------------------------------------------*/
186 /* Private function prototypes -----------------------------------------------*/
187 /* Private functions ---------------------------------------------------------*/
188
189 /** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
190 * @{
191 */
192
193 /** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions
194 * @brief Initialization and Configuration functions
195 *
196 @verbatim
197 ===============================================================================
198 ##### Initialization/de-initialization functions #####
199 ===============================================================================
200 [..] This section provides functions allowing to:
201
202 @endverbatim
203 * @{
204 */
205
206 /**
207 * @brief Initializes the SDIO according to the specified
208 * parameters in the SDIO_InitTypeDef and create the associated handle.
209 * @param SDIOx: Pointer to SDIO register base
210 * @param Init: SDIO initialization structure
211 * @retval HAL status
212 */
213 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
214 {
215 uint32_t tmpreg = 0;
216
217 /* Check the parameters */
218 assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
219 assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
220 assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
221 assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
222 assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
223 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
224 assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
225
226 /* Set SDIO configuration parameters */
227 tmpreg |= (Init.ClockEdge |\
228 Init.ClockBypass |\
229 Init.ClockPowerSave |\
230 Init.BusWide |\
231 Init.HardwareFlowControl |\
232 Init.ClockDiv
233 );
234
235 /* Write to SDIO CLKCR */
236 MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
237
238 return HAL_OK;
239 }
240
241 /**
242 * @}
243 */
244
245 /** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions
246 * @brief Data transfers functions
247 *
248 @verbatim
249 ===============================================================================
250 ##### I/O operation functions #####
251 ===============================================================================
252 [..]
253 This subsection provides a set of functions allowing to manage the SDIO data
254 transfers.
255
256 @endverbatim
257 * @{
258 */
259
260 /**
261 * @brief Read data (word) from Rx FIFO in blocking mode (polling)
262 * @param SDIOx: Pointer to SDIO register base
263 * @retval HAL status
264 */
265 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
266 {
267 /* Read data from Rx FIFO */
268 return (SDIOx->FIFO);
269 }
270
271 /**
272 * @brief Write data (word) to Tx FIFO in blocking mode (polling)
273 * @param SDIOx: Pointer to SDIO register base
274 * @param pWriteData: pointer to data to write
275 * @retval HAL status
276 */
277 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
278 {
279 /* Write data to FIFO */
280 SDIOx->FIFO = *pWriteData;
281
282 return HAL_OK;
283 }
284
285 /**
286 * @}
287 */
288
289 /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
290 * @brief management functions
291 *
292 @verbatim
293 ===============================================================================
294 ##### Peripheral Control functions #####
295 ===============================================================================
296 [..]
297 This subsection provides a set of functions allowing to control the SDIO data
298 transfers.
299
300 @endverbatim
301 * @{
302 */
303
304 /**
305 * @brief Set SDIO Power state to ON.
306 * @param SDIOx: Pointer to SDIO register base
307 * @retval HAL status
308 */
309 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
310 {
311 /* Set power state to ON */
312 SDIOx->POWER = SDIO_POWER_PWRCTRL;
313
314 return HAL_OK;
315 }
316
317 /**
318 * @brief Set SDIO Power state to OFF.
319 * @param SDIOx: Pointer to SDIO register base
320 * @retval HAL status
321 */
322 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
323 {
324 /* Set power state to OFF */
325 SDIOx->POWER = (uint32_t)0x00000000;
326
327 return HAL_OK;
328 }
329
330 /**
331 * @brief Get SDIO Power state.
332 * @param SDIOx: Pointer to SDIO register base
333 * @retval Power status of the controller. The returned value can be one of the
334 * following values:
335 * - 0x00: Power OFF
336 * - 0x02: Power UP
337 * - 0x03: Power ON
338 */
339 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
340 {
341 return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
342 }
343
344 /**
345 * @brief Configure the SDIO command path according to the specified parameters in
346 * SDIO_CmdInitTypeDef structure and send the command
347 * @param SDIOx: Pointer to SDIO register base
348 * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains
349 * the configuration information for the SDIO command
350 * @retval HAL status
351 */
352 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
353 {
354 uint32_t tmpreg = 0;
355
356 /* Check the parameters */
357 assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
358 assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));
359 assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));
360 assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));
361
362 /* Set the SDIO Argument value */
363 SDIOx->ARG = SDIO_CmdInitStruct->Argument;
364
365 /* Set SDIO command parameters */
366 tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\
367 SDIO_CmdInitStruct->Response |\
368 SDIO_CmdInitStruct->WaitForInterrupt |\
369 SDIO_CmdInitStruct->CPSM);
370
371 /* Write to SDIO CMD register */
372 MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
373
374 return HAL_OK;
375 }
376
377 /**
378 * @brief Return the command index of last command for which response received
379 * @param SDIOx: Pointer to SDIO register base
380 * @retval Command index of the last command response received
381 */
382 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
383 {
384 return (uint8_t)(SDIOx->RESPCMD);
385 }
386
387
388 /**
389 * @brief Return the response received from the card for the last command
390 * @param SDIO_RESP: Specifies the SDIO response register.
391 * This parameter can be one of the following values:
392 * @arg SDIO_RESP1: Response Register 1
393 * @arg SDIO_RESP2: Response Register 2
394 * @arg SDIO_RESP3: Response Register 3
395 * @arg SDIO_RESP4: Response Register 4
396 * @retval The Corresponding response register value
397 */
398 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
399 {
400 __IO uint32_t tmp = 0;
401
402 /* Check the parameters */
403 assert_param(IS_SDIO_RESP(SDIO_RESP));
404
405 /* Get the response */
406 tmp = SDIO_RESP_ADDR + SDIO_RESP;
407
408 return (*(__IO uint32_t *) tmp);
409 }
410
411 /**
412 * @brief Configure the SDIO data path according to the specified
413 * parameters in the SDIO_DataInitTypeDef.
414 * @param SDIOx: Pointer to SDIO register base
415 * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
416 * that contains the configuration information for the SDIO command.
417 * @retval HAL status
418 */
419 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)
420 {
421 uint32_t tmpreg = 0;
422
423 /* Check the parameters */
424 assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));
425 assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));
426 assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));
427 assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
428 assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
429
430 /* Set the SDIO Data Timeout value */
431 SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
432
433 /* Set the SDIO DataLength value */
434 SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
435
436 /* Set the SDIO data configuration parameters */
437 tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
438 SDIO_DataInitStruct->TransferDir |\
439 SDIO_DataInitStruct->TransferMode |\
440 SDIO_DataInitStruct->DPSM);
441
442 /* Write to SDIO DCTRL */
443 MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
444
445 return HAL_OK;
446
447 }
448
449 /**
450 * @brief Returns number of remaining data bytes to be transferred.
451 * @param SDIOx: Pointer to SDIO register base
452 * @retval Number of remaining data bytes to be transferred
453 */
454 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
455 {
456 return (SDIOx->DCOUNT);
457 }
458
459 /**
460 * @brief Get the FIFO data
461 * @param SDIOx: Pointer to SDIO register base
462 * @retval Data received
463 */
464 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
465 {
466 return (SDIOx->FIFO);
467 }
468
469
470 /**
471 * @brief Sets one of the two options of inserting read wait interval.
472 * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
473 * This parameter can be:
474 * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
475 * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
476 * @retval None
477 */
478 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
479 {
480 /* Check the parameters */
481 assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
482
483 *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
484
485 return HAL_OK;
486 }
487
488 /**
489 * @}
490 */
491
492 /**
493 * @}
494 */
495
496 #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
497 /**
498 * @}
499 */
500
501 /**
502 * @}
503 */
504
505 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/