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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Src/stm32f4xx_ll_fsmc.c @ 38:5f11787b4f42
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author | heinrichsweikamp |
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date | Sat, 28 Apr 2018 11:52:34 +0200 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_fsmc.c | |
4 * @author MCD Application Team | |
5 * @version V1.2.0 | |
6 * @date 26-December-2014 | |
7 * @brief FSMC Low Layer HAL module driver. | |
8 * | |
9 * This file provides firmware functions to manage the following | |
10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: | |
11 * + Initialization/de-initialization functions | |
12 * + Peripheral Control functions | |
13 * + Peripheral State functions | |
14 * | |
15 @verbatim | |
16 ============================================================================== | |
17 ##### FSMC peripheral features ##### | |
18 ============================================================================== | |
19 [..] The Flexible static memory controller (FSMC) includes two memory controllers: | |
20 (+) The NOR/PSRAM memory controller | |
21 (+) The NAND/PC Card memory controller | |
22 | |
23 [..] The FSMC functional block makes the interface with synchronous and asynchronous static | |
24 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: | |
25 (+) to translate AHB transactions into the appropriate external device protocol. | |
26 (+) to meet the access time requirements of the external memory devices. | |
27 | |
28 [..] All external memories share the addresses, data and control signals with the controller. | |
29 Each external device is accessed by means of a unique Chip Select. The FSMC performs | |
30 only one access at a time to an external device. | |
31 The main features of the FSMC controller are the following: | |
32 (+) Interface with static-memory mapped devices including: | |
33 (++) Static random access memory (SRAM). | |
34 (++) Read-only memory (ROM). | |
35 (++) NOR Flash memory/OneNAND Flash memory. | |
36 (++) PSRAM (4 memory banks). | |
37 (++) 16-bit PC Card compatible devices. | |
38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of | |
39 data. | |
40 (+) Independent Chip Select control for each memory bank. | |
41 (+) Independent configuration for each memory bank. | |
42 | |
43 @endverbatim | |
44 ****************************************************************************** | |
45 * @attention | |
46 * | |
47 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> | |
48 * | |
49 * Redistribution and use in source and binary forms, with or without modification, | |
50 * are permitted provided that the following conditions are met: | |
51 * 1. Redistributions of source code must retain the above copyright notice, | |
52 * this list of conditions and the following disclaimer. | |
53 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
54 * this list of conditions and the following disclaimer in the documentation | |
55 * and/or other materials provided with the distribution. | |
56 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
57 * may be used to endorse or promote products derived from this software | |
58 * without specific prior written permission. | |
59 * | |
60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
70 * | |
71 ****************************************************************************** | |
72 */ | |
73 | |
74 /* Includes ------------------------------------------------------------------*/ | |
75 #include "stm32f4xx_hal.h" | |
76 | |
77 /** @addtogroup STM32F4xx_HAL_Driver | |
78 * @{ | |
79 */ | |
80 | |
81 /** @defgroup FSMC_LL FSMC Low Layer | |
82 * @brief FSMC driver modules | |
83 * @{ | |
84 */ | |
85 | |
86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) | |
87 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
88 /* Private typedef -----------------------------------------------------------*/ | |
89 /* Private define ------------------------------------------------------------*/ | |
90 /* Private macro -------------------------------------------------------------*/ | |
91 /* Private variables ---------------------------------------------------------*/ | |
92 /* Private function prototypes -----------------------------------------------*/ | |
93 /* Private functions ---------------------------------------------------------*/ | |
94 /** @addtogroup FSMC_LL_Private_Functions | |
95 * @{ | |
96 */ | |
97 | |
98 /** @addtogroup FSMC_LL_NORSRAM | |
99 * @brief NORSRAM Controller functions | |
100 * | |
101 @verbatim | |
102 ============================================================================== | |
103 ##### How to use NORSRAM device driver ##### | |
104 ============================================================================== | |
105 | |
106 [..] | |
107 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order | |
108 to run the NORSRAM external devices. | |
109 | |
110 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() | |
111 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() | |
112 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() | |
113 (+) FSMC NORSRAM bank extended timing configuration using the function | |
114 FSMC_NORSRAM_Extended_Timing_Init() | |
115 (+) FSMC NORSRAM bank enable/disable write operation using the functions | |
116 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() | |
117 | |
118 @endverbatim | |
119 * @{ | |
120 */ | |
121 | |
122 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1 | |
123 * @brief Initialization and Configuration functions | |
124 * | |
125 @verbatim | |
126 ============================================================================== | |
127 ##### Initialization and de_initialization functions ##### | |
128 ============================================================================== | |
129 [..] | |
130 This section provides functions allowing to: | |
131 (+) Initialize and configure the FSMC NORSRAM interface | |
132 (+) De-initialize the FSMC NORSRAM interface | |
133 (+) Configure the FSMC clock and associated GPIOs | |
134 | |
135 @endverbatim | |
136 * @{ | |
137 */ | |
138 | |
139 /** | |
140 * @brief Initialize the FSMC_NORSRAM device according to the specified | |
141 * control parameters in the FSMC_NORSRAM_InitTypeDef | |
142 * @param Device: Pointer to NORSRAM device instance | |
143 * @param Init: Pointer to NORSRAM Initialization structure | |
144 * @retval HAL status | |
145 */ | |
146 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) | |
147 { | |
148 uint32_t tmpr = 0; | |
149 | |
150 /* Check the parameters */ | |
151 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); | |
152 assert_param(IS_FSMC_MUX(Init->DataAddressMux)); | |
153 assert_param(IS_FSMC_MEMORY(Init->MemoryType)); | |
154 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); | |
155 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); | |
156 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); | |
157 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); | |
158 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); | |
159 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); | |
160 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); | |
161 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); | |
162 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); | |
163 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); | |
164 | |
165 /* Get the BTCR register value */ | |
166 tmpr = Device->BTCR[Init->NSBank]; | |
167 | |
168 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, | |
169 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ | |
170 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ | |
171 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ | |
172 FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \ | |
173 FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \ | |
174 FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW)); | |
175 /* Set NORSRAM device control parameters */ | |
176 tmpr |= (uint32_t)(Init->DataAddressMux |\ | |
177 Init->MemoryType |\ | |
178 Init->MemoryDataWidth |\ | |
179 Init->BurstAccessMode |\ | |
180 Init->WaitSignalPolarity |\ | |
181 Init->WrapMode |\ | |
182 Init->WaitSignalActive |\ | |
183 Init->WriteOperation |\ | |
184 Init->WaitSignal |\ | |
185 Init->ExtendedMode |\ | |
186 Init->AsynchronousWait |\ | |
187 Init->WriteBurst | |
188 ); | |
189 | |
190 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) | |
191 { | |
192 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; | |
193 } | |
194 | |
195 Device->BTCR[Init->NSBank] = tmpr; | |
196 | |
197 return HAL_OK; | |
198 } | |
199 | |
200 /** | |
201 * @brief DeInitialize the FSMC_NORSRAM peripheral | |
202 * @param Device: Pointer to NORSRAM device instance | |
203 * @param ExDevice: Pointer to NORSRAM extended mode device instance | |
204 * @param Bank: NORSRAM bank number | |
205 * @retval HAL status | |
206 */ | |
207 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) | |
208 { | |
209 /* Check the parameters */ | |
210 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); | |
211 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); | |
212 | |
213 /* Disable the FSMC_NORSRAM device */ | |
214 __FSMC_NORSRAM_DISABLE(Device, Bank); | |
215 | |
216 /* De-initialize the FSMC_NORSRAM device */ | |
217 /* FSMC_NORSRAM_BANK1 */ | |
218 if(Bank == FSMC_NORSRAM_BANK1) | |
219 { | |
220 Device->BTCR[Bank] = 0x000030DB; | |
221 } | |
222 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ | |
223 else | |
224 { | |
225 Device->BTCR[Bank] = 0x000030D2; | |
226 } | |
227 | |
228 Device->BTCR[Bank + 1] = 0x0FFFFFFF; | |
229 ExDevice->BWTR[Bank] = 0x0FFFFFFF; | |
230 | |
231 return HAL_OK; | |
232 } | |
233 | |
234 | |
235 /** | |
236 * @brief Initialize the FSMC_NORSRAM Timing according to the specified | |
237 * parameters in the FSMC_NORSRAM_TimingTypeDef | |
238 * @param Device: Pointer to NORSRAM device instance | |
239 * @param Timing: Pointer to NORSRAM Timing structure | |
240 * @param Bank: NORSRAM bank number | |
241 * @retval HAL status | |
242 */ | |
243 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) | |
244 { | |
245 uint32_t tmpr = 0; | |
246 | |
247 /* Check the parameters */ | |
248 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); | |
249 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); | |
250 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); | |
251 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); | |
252 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); | |
253 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); | |
254 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); | |
255 | |
256 /* Get the BTCR register value */ | |
257 tmpr = Device->BTCR[Bank + 1]; | |
258 | |
259 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ | |
260 tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \ | |
261 FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \ | |
262 FSMC_BTR1_ACCMOD)); | |
263 | |
264 /* Set FSMC_NORSRAM device timing parameters */ | |
265 tmpr |= (uint32_t)(Timing->AddressSetupTime |\ | |
266 ((Timing->AddressHoldTime) << 4) |\ | |
267 ((Timing->DataSetupTime) << 8) |\ | |
268 ((Timing->BusTurnAroundDuration) << 16) |\ | |
269 (((Timing->CLKDivision)-1) << 20) |\ | |
270 (((Timing->DataLatency)-2) << 24) |\ | |
271 (Timing->AccessMode)); | |
272 | |
273 Device->BTCR[Bank + 1] = tmpr; | |
274 | |
275 return HAL_OK; | |
276 } | |
277 | |
278 /** | |
279 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified | |
280 * parameters in the FSMC_NORSRAM_TimingTypeDef | |
281 * @param Device: Pointer to NORSRAM device instance | |
282 * @param Timing: Pointer to NORSRAM Timing structure | |
283 * @param Bank: NORSRAM bank number | |
284 * @retval HAL status | |
285 */ | |
286 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) | |
287 { | |
288 uint32_t tmpr = 0; | |
289 | |
290 /* Set NORSRAM device timing register for write configuration, if extended mode is used */ | |
291 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) | |
292 { | |
293 /* Check the parameters */ | |
294 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); | |
295 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); | |
296 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); | |
297 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); | |
298 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); | |
299 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); | |
300 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); | |
301 | |
302 /* Get the BWTR register value */ | |
303 tmpr = Device->BWTR[Bank]; | |
304 | |
305 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ | |
306 tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \ | |
307 FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \ | |
308 FSMC_BWTR1_ACCMOD)); | |
309 | |
310 tmpr |= (uint32_t)(Timing->AddressSetupTime |\ | |
311 ((Timing->AddressHoldTime) << 4) |\ | |
312 ((Timing->DataSetupTime) << 8) |\ | |
313 ((Timing->BusTurnAroundDuration) << 16) |\ | |
314 (((Timing->CLKDivision)-1) << 20) |\ | |
315 (((Timing->DataLatency)-2) << 24) |\ | |
316 (Timing->AccessMode)); | |
317 | |
318 Device->BWTR[Bank] = tmpr; | |
319 } | |
320 else | |
321 { | |
322 Device->BWTR[Bank] = 0x0FFFFFFF; | |
323 } | |
324 | |
325 return HAL_OK; | |
326 } | |
327 /** | |
328 * @} | |
329 */ | |
330 | |
331 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2 | |
332 * @brief management functions | |
333 * | |
334 @verbatim | |
335 ============================================================================== | |
336 ##### FSMC_NORSRAM Control functions ##### | |
337 ============================================================================== | |
338 [..] | |
339 This subsection provides a set of functions allowing to control dynamically | |
340 the FSMC NORSRAM interface. | |
341 | |
342 @endverbatim | |
343 * @{ | |
344 */ | |
345 | |
346 /** | |
347 * @brief Enables dynamically FSMC_NORSRAM write operation. | |
348 * @param Device: Pointer to NORSRAM device instance | |
349 * @param Bank: NORSRAM bank number | |
350 * @retval HAL status | |
351 */ | |
352 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) | |
353 { | |
354 /* Enable write operation */ | |
355 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; | |
356 | |
357 return HAL_OK; | |
358 } | |
359 | |
360 /** | |
361 * @brief Disables dynamically FSMC_NORSRAM write operation. | |
362 * @param Device: Pointer to NORSRAM device instance | |
363 * @param Bank: NORSRAM bank number | |
364 * @retval HAL status | |
365 */ | |
366 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) | |
367 { | |
368 /* Disable write operation */ | |
369 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; | |
370 | |
371 return HAL_OK; | |
372 } | |
373 /** | |
374 * @} | |
375 */ | |
376 | |
377 /** | |
378 * @} | |
379 */ | |
380 | |
381 /** @addtogroup FSMC_LL_NAND | |
382 * @brief NAND Controller functions | |
383 * | |
384 @verbatim | |
385 ============================================================================== | |
386 ##### How to use NAND device driver ##### | |
387 ============================================================================== | |
388 [..] | |
389 This driver contains a set of APIs to interface with the FSMC NAND banks in order | |
390 to run the NAND external devices. | |
391 | |
392 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() | |
393 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init() | |
394 (+) FSMC NAND bank common space timing configuration using the function | |
395 FSMC_NAND_CommonSpace_Timing_Init() | |
396 (+) FSMC NAND bank attribute space timing configuration using the function | |
397 FSMC_NAND_AttributeSpace_Timing_Init() | |
398 (+) FSMC NAND bank enable/disable ECC correction feature using the functions | |
399 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable() | |
400 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() | |
401 | |
402 @endverbatim | |
403 * @{ | |
404 */ | |
405 | |
406 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1 | |
407 * @brief Initialization and Configuration functions | |
408 * | |
409 @verbatim | |
410 ============================================================================== | |
411 ##### Initialization and de_initialization functions ##### | |
412 ============================================================================== | |
413 [..] | |
414 This section provides functions allowing to: | |
415 (+) Initialize and configure the FSMC NAND interface | |
416 (+) De-initialize the FSMC NAND interface | |
417 (+) Configure the FSMC clock and associated GPIOs | |
418 | |
419 @endverbatim | |
420 * @{ | |
421 */ | |
422 | |
423 /** | |
424 * @brief Initializes the FSMC_NAND device according to the specified | |
425 * control parameters in the FSMC_NAND_HandleTypeDef | |
426 * @param Device: Pointer to NAND device instance | |
427 * @param Init: Pointer to NAND Initialization structure | |
428 * @retval HAL status | |
429 */ | |
430 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) | |
431 { | |
432 uint32_t tmpr = 0; | |
433 | |
434 /* Check the parameters */ | |
435 assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); | |
436 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); | |
437 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); | |
438 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); | |
439 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); | |
440 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); | |
441 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); | |
442 | |
443 if(Init->NandBank == FSMC_NAND_BANK2) | |
444 { | |
445 /* Get the NAND bank 2 register value */ | |
446 tmpr = Device->PCR2; | |
447 } | |
448 else | |
449 { | |
450 /* Get the NAND bank 3 register value */ | |
451 tmpr = Device->PCR3; | |
452 } | |
453 | |
454 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ | |
455 tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \ | |
456 FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ | |
457 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)); | |
458 | |
459 /* Set NAND device control parameters */ | |
460 tmpr |= (uint32_t)(Init->Waitfeature |\ | |
461 FSMC_PCR_MEMORY_TYPE_NAND |\ | |
462 Init->MemoryDataWidth |\ | |
463 Init->EccComputation |\ | |
464 Init->ECCPageSize |\ | |
465 ((Init->TCLRSetupTime) << 9) |\ | |
466 ((Init->TARSetupTime) << 13)); | |
467 | |
468 if(Init->NandBank == FSMC_NAND_BANK2) | |
469 { | |
470 /* NAND bank 2 registers configuration */ | |
471 Device->PCR2 = tmpr; | |
472 } | |
473 else | |
474 { | |
475 /* NAND bank 3 registers configuration */ | |
476 Device->PCR3 = tmpr; | |
477 } | |
478 | |
479 return HAL_OK; | |
480 } | |
481 | |
482 /** | |
483 * @brief Initializes the FSMC_NAND Common space Timing according to the specified | |
484 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
485 * @param Device: Pointer to NAND device instance | |
486 * @param Timing: Pointer to NAND timing structure | |
487 * @param Bank: NAND bank number | |
488 * @retval HAL status | |
489 */ | |
490 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) | |
491 { | |
492 uint32_t tmpr = 0; | |
493 | |
494 /* Check the parameters */ | |
495 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
496 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
497 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
498 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
499 | |
500 if(Bank == FSMC_NAND_BANK2) | |
501 { | |
502 /* Get the NAND bank 2 register value */ | |
503 tmpr = Device->PMEM2; | |
504 } | |
505 else | |
506 { | |
507 /* Get the NAND bank 3 register value */ | |
508 tmpr = Device->PMEM3; | |
509 } | |
510 | |
511 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ | |
512 tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \ | |
513 FSMC_PMEM2_MEMHIZ2)); | |
514 | |
515 /* Set FSMC_NAND device timing parameters */ | |
516 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
517 ((Timing->WaitSetupTime) << 8) |\ | |
518 ((Timing->HoldSetupTime) << 16) |\ | |
519 ((Timing->HiZSetupTime) << 24) | |
520 ); | |
521 | |
522 if(Bank == FSMC_NAND_BANK2) | |
523 { | |
524 /* NAND bank 2 registers configuration */ | |
525 Device->PMEM2 = tmpr; | |
526 } | |
527 else | |
528 { | |
529 /* NAND bank 3 registers configuration */ | |
530 Device->PMEM3 = tmpr; | |
531 } | |
532 | |
533 return HAL_OK; | |
534 } | |
535 | |
536 /** | |
537 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified | |
538 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
539 * @param Device: Pointer to NAND device instance | |
540 * @param Timing: Pointer to NAND timing structure | |
541 * @param Bank: NAND bank number | |
542 * @retval HAL status | |
543 */ | |
544 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) | |
545 { | |
546 uint32_t tmpr = 0; | |
547 | |
548 /* Check the parameters */ | |
549 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
550 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
551 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
552 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
553 | |
554 if(Bank == FSMC_NAND_BANK2) | |
555 { | |
556 /* Get the NAND bank 2 register value */ | |
557 tmpr = Device->PATT2; | |
558 } | |
559 else | |
560 { | |
561 /* Get the NAND bank 3 register value */ | |
562 tmpr = Device->PATT3; | |
563 } | |
564 | |
565 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ | |
566 tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \ | |
567 FSMC_PATT2_ATTHIZ2)); | |
568 | |
569 /* Set FSMC_NAND device timing parameters */ | |
570 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
571 ((Timing->WaitSetupTime) << 8) |\ | |
572 ((Timing->HoldSetupTime) << 16) |\ | |
573 ((Timing->HiZSetupTime) << 24) | |
574 ); | |
575 | |
576 if(Bank == FSMC_NAND_BANK2) | |
577 { | |
578 /* NAND bank 2 registers configuration */ | |
579 Device->PATT2 = tmpr; | |
580 } | |
581 else | |
582 { | |
583 /* NAND bank 3 registers configuration */ | |
584 Device->PATT3 = tmpr; | |
585 } | |
586 | |
587 return HAL_OK; | |
588 } | |
589 | |
590 /** | |
591 * @brief DeInitializes the FSMC_NAND device | |
592 * @param Device: Pointer to NAND device instance | |
593 * @param Bank: NAND bank number | |
594 * @retval HAL status | |
595 */ | |
596 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) | |
597 { | |
598 /* Disable the NAND Bank */ | |
599 __FSMC_NAND_DISABLE(Device, Bank); | |
600 | |
601 /* De-initialize the NAND Bank */ | |
602 if(Bank == FSMC_NAND_BANK2) | |
603 { | |
604 /* Set the FSMC_NAND_BANK2 registers to their reset values */ | |
605 Device->PCR2 = 0x00000018; | |
606 Device->SR2 = 0x00000040; | |
607 Device->PMEM2 = 0xFCFCFCFC; | |
608 Device->PATT2 = 0xFCFCFCFC; | |
609 } | |
610 /* FSMC_Bank3_NAND */ | |
611 else | |
612 { | |
613 /* Set the FSMC_NAND_BANK3 registers to their reset values */ | |
614 Device->PCR3 = 0x00000018; | |
615 Device->SR3 = 0x00000040; | |
616 Device->PMEM3 = 0xFCFCFCFC; | |
617 Device->PATT3 = 0xFCFCFCFC; | |
618 } | |
619 | |
620 return HAL_OK; | |
621 } | |
622 /** | |
623 * @} | |
624 */ | |
625 | |
626 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2 | |
627 * @brief management functions | |
628 * | |
629 @verbatim | |
630 ============================================================================== | |
631 ##### FSMC_NAND Control functions ##### | |
632 ============================================================================== | |
633 [..] | |
634 This subsection provides a set of functions allowing to control dynamically | |
635 the FSMC NAND interface. | |
636 | |
637 @endverbatim | |
638 * @{ | |
639 */ | |
640 | |
641 /** | |
642 * @brief Enables dynamically FSMC_NAND ECC feature. | |
643 * @param Device: Pointer to NAND device instance | |
644 * @param Bank: NAND bank number | |
645 * @retval HAL status | |
646 */ | |
647 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) | |
648 { | |
649 /* Enable ECC feature */ | |
650 if(Bank == FSMC_NAND_BANK2) | |
651 { | |
652 Device->PCR2 |= FSMC_PCR2_ECCEN; | |
653 } | |
654 else | |
655 { | |
656 Device->PCR3 |= FSMC_PCR3_ECCEN; | |
657 } | |
658 | |
659 return HAL_OK; | |
660 } | |
661 | |
662 /** | |
663 * @brief Disables dynamically FSMC_NAND ECC feature. | |
664 * @param Device: Pointer to NAND device instance | |
665 * @param Bank: NAND bank number | |
666 * @retval HAL status | |
667 */ | |
668 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) | |
669 { | |
670 /* Disable ECC feature */ | |
671 if(Bank == FSMC_NAND_BANK2) | |
672 { | |
673 Device->PCR2 &= ~FSMC_PCR2_ECCEN; | |
674 } | |
675 else | |
676 { | |
677 Device->PCR3 &= ~FSMC_PCR3_ECCEN; | |
678 } | |
679 | |
680 return HAL_OK; | |
681 } | |
682 | |
683 /** | |
684 * @brief Disables dynamically FSMC_NAND ECC feature. | |
685 * @param Device: Pointer to NAND device instance | |
686 * @param ECCval: Pointer to ECC value | |
687 * @param Bank: NAND bank number | |
688 * @param Timeout: Timeout wait value | |
689 * @retval HAL status | |
690 */ | |
691 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) | |
692 { | |
693 uint32_t tickstart = 0; | |
694 | |
695 /* Check the parameters */ | |
696 assert_param(IS_FSMC_NAND_DEVICE(Device)); | |
697 assert_param(IS_FSMC_NAND_BANK(Bank)); | |
698 | |
699 /* Get tick */ | |
700 tickstart = HAL_GetTick(); | |
701 | |
702 /* Wait until FIFO is empty */ | |
703 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) | |
704 { | |
705 /* Check for the Timeout */ | |
706 if(Timeout != HAL_MAX_DELAY) | |
707 { | |
708 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) | |
709 { | |
710 return HAL_TIMEOUT; | |
711 } | |
712 } | |
713 } | |
714 | |
715 if(Bank == FSMC_NAND_BANK2) | |
716 { | |
717 /* Get the ECCR2 register value */ | |
718 *ECCval = (uint32_t)Device->ECCR2; | |
719 } | |
720 else | |
721 { | |
722 /* Get the ECCR3 register value */ | |
723 *ECCval = (uint32_t)Device->ECCR3; | |
724 } | |
725 | |
726 return HAL_OK; | |
727 } | |
728 | |
729 /** | |
730 * @} | |
731 */ | |
732 | |
733 /** | |
734 * @} | |
735 */ | |
736 | |
737 /** @addtogroup FSMC_LL_PCCARD | |
738 * @brief PCCARD Controller functions | |
739 * | |
740 @verbatim | |
741 ============================================================================== | |
742 ##### How to use PCCARD device driver ##### | |
743 ============================================================================== | |
744 [..] | |
745 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order | |
746 to run the PCCARD/compact flash external devices. | |
747 | |
748 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() | |
749 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init() | |
750 (+) FSMC PCCARD bank common space timing configuration using the function | |
751 FSMC_PCCARD_CommonSpace_Timing_Init() | |
752 (+) FSMC PCCARD bank attribute space timing configuration using the function | |
753 FSMC_PCCARD_AttributeSpace_Timing_Init() | |
754 (+) FSMC PCCARD bank IO space timing configuration using the function | |
755 FSMC_PCCARD_IOSpace_Timing_Init() | |
756 | |
757 @endverbatim | |
758 * @{ | |
759 */ | |
760 | |
761 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1 | |
762 * @brief Initialization and Configuration functions | |
763 * | |
764 @verbatim | |
765 ============================================================================== | |
766 ##### Initialization and de_initialization functions ##### | |
767 ============================================================================== | |
768 [..] | |
769 This section provides functions allowing to: | |
770 (+) Initialize and configure the FSMC PCCARD interface | |
771 (+) De-initialize the FSMC PCCARD interface | |
772 (+) Configure the FSMC clock and associated GPIOs | |
773 | |
774 @endverbatim | |
775 * @{ | |
776 */ | |
777 | |
778 /** | |
779 * @brief Initializes the FSMC_PCCARD device according to the specified | |
780 * control parameters in the FSMC_PCCARD_HandleTypeDef | |
781 * @param Device: Pointer to PCCARD device instance | |
782 * @param Init: Pointer to PCCARD Initialization structure | |
783 * @retval HAL status | |
784 */ | |
785 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) | |
786 { | |
787 uint32_t tmpr = 0; | |
788 | |
789 /* Check the parameters */ | |
790 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); | |
791 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); | |
792 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); | |
793 | |
794 /* Get PCCARD control register value */ | |
795 tmpr = Device->PCR4; | |
796 | |
797 /* Clear TAR, TCLR, PWAITEN and PWID bits */ | |
798 tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ | |
799 FSMC_PCR4_PWID)); | |
800 | |
801 /* Set FSMC_PCCARD device control parameters */ | |
802 tmpr |= (uint32_t)(Init->Waitfeature |\ | |
803 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ | |
804 (Init->TCLRSetupTime << 9) |\ | |
805 (Init->TARSetupTime << 13)); | |
806 | |
807 Device->PCR4 = tmpr; | |
808 | |
809 return HAL_OK; | |
810 } | |
811 | |
812 /** | |
813 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified | |
814 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
815 * @param Device: Pointer to PCCARD device instance | |
816 * @param Timing: Pointer to PCCARD timing structure | |
817 * @retval HAL status | |
818 */ | |
819 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) | |
820 { | |
821 uint32_t tmpr = 0; | |
822 | |
823 /* Check the parameters */ | |
824 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
825 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
826 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
827 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
828 | |
829 /* Get PCCARD common space timing register value */ | |
830 tmpr = Device->PMEM4; | |
831 | |
832 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ | |
833 tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \ | |
834 FSMC_PMEM4_MEMHIZ4)); | |
835 /* Set PCCARD timing parameters */ | |
836 tmpr |= (uint32_t)((Timing->SetupTime |\ | |
837 ((Timing->WaitSetupTime) << 8) |\ | |
838 (Timing->HoldSetupTime) << 16) |\ | |
839 ((Timing->HiZSetupTime) << 24)); | |
840 | |
841 Device->PMEM4 = tmpr; | |
842 | |
843 return HAL_OK; | |
844 } | |
845 | |
846 /** | |
847 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified | |
848 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
849 * @param Device: Pointer to PCCARD device instance | |
850 * @param Timing: Pointer to PCCARD timing structure | |
851 * @retval HAL status | |
852 */ | |
853 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) | |
854 { | |
855 uint32_t tmpr = 0; | |
856 | |
857 /* Check the parameters */ | |
858 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
859 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
860 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
861 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
862 | |
863 /* Get PCCARD timing parameters */ | |
864 tmpr = Device->PATT4; | |
865 | |
866 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ | |
867 tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \ | |
868 FSMC_PATT4_ATTHIZ4)); | |
869 | |
870 /* Set PCCARD timing parameters */ | |
871 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
872 ((Timing->WaitSetupTime) << 8) |\ | |
873 ((Timing->HoldSetupTime) << 16) |\ | |
874 ((Timing->HiZSetupTime) << 24)); | |
875 Device->PATT4 = tmpr; | |
876 | |
877 return HAL_OK; | |
878 } | |
879 | |
880 /** | |
881 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified | |
882 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
883 * @param Device: Pointer to PCCARD device instance | |
884 * @param Timing: Pointer to PCCARD timing structure | |
885 * @retval HAL status | |
886 */ | |
887 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) | |
888 { | |
889 uint32_t tmpr = 0; | |
890 | |
891 /* Check the parameters */ | |
892 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
893 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
894 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
895 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
896 | |
897 /* Get FSMC_PCCARD device timing parameters */ | |
898 tmpr = Device->PIO4; | |
899 | |
900 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ | |
901 tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \ | |
902 FSMC_PIO4_IOHIZ4)); | |
903 | |
904 /* Set FSMC_PCCARD device timing parameters */ | |
905 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
906 ((Timing->WaitSetupTime) << 8) |\ | |
907 ((Timing->HoldSetupTime) << 16) |\ | |
908 ((Timing->HiZSetupTime) << 24)); | |
909 | |
910 Device->PIO4 = tmpr; | |
911 | |
912 return HAL_OK; | |
913 } | |
914 | |
915 /** | |
916 * @brief DeInitializes the FSMC_PCCARD device | |
917 * @param Device: Pointer to PCCARD device instance | |
918 * @retval HAL status | |
919 */ | |
920 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) | |
921 { | |
922 /* Disable the FSMC_PCCARD device */ | |
923 __FSMC_PCCARD_DISABLE(Device); | |
924 | |
925 /* De-initialize the FSMC_PCCARD device */ | |
926 Device->PCR4 = 0x00000018; | |
927 Device->SR4 = 0x00000000; | |
928 Device->PMEM4 = 0xFCFCFCFC; | |
929 Device->PATT4 = 0xFCFCFCFC; | |
930 Device->PIO4 = 0xFCFCFCFC; | |
931 | |
932 return HAL_OK; | |
933 } | |
934 /** | |
935 * @} | |
936 */ | |
937 | |
938 /** | |
939 * @} | |
940 */ | |
941 | |
942 /** | |
943 * @} | |
944 */ | |
945 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
946 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */ | |
947 | |
948 /** | |
949 * @} | |
950 */ | |
951 | |
952 /** | |
953 * @} | |
954 */ | |
955 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |