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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Src/stm32f4xx_ll_fmc.c @ 38:5f11787b4f42
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author | heinrichsweikamp |
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date | Sat, 28 Apr 2018 11:52:34 +0200 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_fmc.c | |
4 * @author MCD Application Team | |
5 * @version V1.2.0 | |
6 * @date 26-December-2014 | |
7 * @brief FMC Low Layer HAL module driver. | |
8 * | |
9 * This file provides firmware functions to manage the following | |
10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories: | |
11 * + Initialization/de-initialization functions | |
12 * + Peripheral Control functions | |
13 * + Peripheral State functions | |
14 * | |
15 @verbatim | |
16 ============================================================================== | |
17 ##### FMC peripheral features ##### | |
18 ============================================================================== | |
19 [..] The Flexible memory controller (FMC) includes three memory controllers: | |
20 (+) The NOR/PSRAM memory controller | |
21 (+) The NAND/PC Card memory controller | |
22 (+) The Synchronous DRAM (SDRAM) controller | |
23 | |
24 [..] The FMC functional block makes the interface with synchronous and asynchronous static | |
25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: | |
26 (+) to translate AHB transactions into the appropriate external device protocol | |
27 (+) to meet the access time requirements of the external memory devices | |
28 | |
29 [..] All external memories share the addresses, data and control signals with the controller. | |
30 Each external device is accessed by means of a unique Chip Select. The FMC performs | |
31 only one access at a time to an external device. | |
32 The main features of the FMC controller are the following: | |
33 (+) Interface with static-memory mapped devices including: | |
34 (++) Static random access memory (SRAM) | |
35 (++) Read-only memory (ROM) | |
36 (++) NOR Flash memory/OneNAND Flash memory | |
37 (++) PSRAM (4 memory banks) | |
38 (++) 16-bit PC Card compatible devices | |
39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of | |
40 data | |
41 (+) Interface with synchronous DRAM (SDRAM) memories | |
42 (+) Independent Chip Select control for each memory bank | |
43 (+) Independent configuration for each memory bank | |
44 | |
45 @endverbatim | |
46 ****************************************************************************** | |
47 * @attention | |
48 * | |
49 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> | |
50 * | |
51 * Redistribution and use in source and binary forms, with or without modification, | |
52 * are permitted provided that the following conditions are met: | |
53 * 1. Redistributions of source code must retain the above copyright notice, | |
54 * this list of conditions and the following disclaimer. | |
55 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
56 * this list of conditions and the following disclaimer in the documentation | |
57 * and/or other materials provided with the distribution. | |
58 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
59 * may be used to endorse or promote products derived from this software | |
60 * without specific prior written permission. | |
61 * | |
62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
72 * | |
73 ****************************************************************************** | |
74 */ | |
75 | |
76 /* Includes ------------------------------------------------------------------*/ | |
77 #include "stm32f4xx_hal.h" | |
78 | |
79 /** @addtogroup STM32F4xx_HAL_Driver | |
80 * @{ | |
81 */ | |
82 | |
83 /** @defgroup FMC_LL FMC Low Layer | |
84 * @brief FMC driver modules | |
85 * @{ | |
86 */ | |
87 | |
88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) | |
89 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) | |
90 | |
91 /* Private typedef -----------------------------------------------------------*/ | |
92 /* Private define ------------------------------------------------------------*/ | |
93 /* Private macro -------------------------------------------------------------*/ | |
94 /* Private variables ---------------------------------------------------------*/ | |
95 /* Private function prototypes -----------------------------------------------*/ | |
96 /* Private functions ---------------------------------------------------------*/ | |
97 /** @addtogroup FMC_LL_Private_Functions | |
98 * @{ | |
99 */ | |
100 | |
101 /** @addtogroup FMC_LL_NORSRAM | |
102 * @brief NORSRAM Controller functions | |
103 * | |
104 @verbatim | |
105 ============================================================================== | |
106 ##### How to use NORSRAM device driver ##### | |
107 ============================================================================== | |
108 | |
109 [..] | |
110 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order | |
111 to run the NORSRAM external devices. | |
112 | |
113 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() | |
114 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() | |
115 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() | |
116 (+) FMC NORSRAM bank extended timing configuration using the function | |
117 FMC_NORSRAM_Extended_Timing_Init() | |
118 (+) FMC NORSRAM bank enable/disable write operation using the functions | |
119 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() | |
120 | |
121 | |
122 @endverbatim | |
123 * @{ | |
124 */ | |
125 | |
126 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1 | |
127 * @brief Initialization and Configuration functions | |
128 * | |
129 @verbatim | |
130 ============================================================================== | |
131 ##### Initialization and de_initialization functions ##### | |
132 ============================================================================== | |
133 [..] | |
134 This section provides functions allowing to: | |
135 (+) Initialize and configure the FMC NORSRAM interface | |
136 (+) De-initialize the FMC NORSRAM interface | |
137 (+) Configure the FMC clock and associated GPIOs | |
138 | |
139 @endverbatim | |
140 * @{ | |
141 */ | |
142 | |
143 /** | |
144 * @brief Initialize the FMC_NORSRAM device according to the specified | |
145 * control parameters in the FMC_NORSRAM_InitTypeDef | |
146 * @param Device: Pointer to NORSRAM device instance | |
147 * @param Init: Pointer to NORSRAM Initialization structure | |
148 * @retval HAL status | |
149 */ | |
150 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) | |
151 { | |
152 uint32_t tmpr = 0; | |
153 | |
154 /* Check the parameters */ | |
155 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); | |
156 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); | |
157 assert_param(IS_FMC_MUX(Init->DataAddressMux)); | |
158 assert_param(IS_FMC_MEMORY(Init->MemoryType)); | |
159 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); | |
160 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); | |
161 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); | |
162 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); | |
163 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); | |
164 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); | |
165 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); | |
166 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); | |
167 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); | |
168 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); | |
169 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); | |
170 | |
171 /* Get the BTCR register value */ | |
172 tmpr = Device->BTCR[Init->NSBank]; | |
173 | |
174 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, | |
175 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ | |
176 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ | |
177 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ | |
178 FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \ | |
179 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ | |
180 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN)); | |
181 | |
182 /* Set NORSRAM device control parameters */ | |
183 tmpr |= (uint32_t)(Init->DataAddressMux |\ | |
184 Init->MemoryType |\ | |
185 Init->MemoryDataWidth |\ | |
186 Init->BurstAccessMode |\ | |
187 Init->WaitSignalPolarity |\ | |
188 Init->WrapMode |\ | |
189 Init->WaitSignalActive |\ | |
190 Init->WriteOperation |\ | |
191 Init->WaitSignal |\ | |
192 Init->ExtendedMode |\ | |
193 Init->AsynchronousWait |\ | |
194 Init->WriteBurst |\ | |
195 Init->ContinuousClock); | |
196 | |
197 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) | |
198 { | |
199 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; | |
200 } | |
201 | |
202 Device->BTCR[Init->NSBank] = tmpr; | |
203 | |
204 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ | |
205 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) | |
206 { | |
207 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; | |
208 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\ | |
209 Init->ContinuousClock); | |
210 } | |
211 | |
212 return HAL_OK; | |
213 } | |
214 | |
215 /** | |
216 * @brief DeInitialize the FMC_NORSRAM peripheral | |
217 * @param Device: Pointer to NORSRAM device instance | |
218 * @param ExDevice: Pointer to NORSRAM extended mode device instance | |
219 * @param Bank: NORSRAM bank number | |
220 * @retval HAL status | |
221 */ | |
222 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) | |
223 { | |
224 /* Check the parameters */ | |
225 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); | |
226 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); | |
227 assert_param(IS_FMC_NORSRAM_BANK(Bank)); | |
228 | |
229 /* Disable the FMC_NORSRAM device */ | |
230 __FMC_NORSRAM_DISABLE(Device, Bank); | |
231 | |
232 /* De-initialize the FMC_NORSRAM device */ | |
233 /* FMC_NORSRAM_BANK1 */ | |
234 if(Bank == FMC_NORSRAM_BANK1) | |
235 { | |
236 Device->BTCR[Bank] = 0x000030DB; | |
237 } | |
238 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ | |
239 else | |
240 { | |
241 Device->BTCR[Bank] = 0x000030D2; | |
242 } | |
243 | |
244 Device->BTCR[Bank + 1] = 0x0FFFFFFF; | |
245 ExDevice->BWTR[Bank] = 0x0FFFFFFF; | |
246 | |
247 return HAL_OK; | |
248 } | |
249 | |
250 /** | |
251 * @brief Initialize the FMC_NORSRAM Timing according to the specified | |
252 * parameters in the FMC_NORSRAM_TimingTypeDef | |
253 * @param Device: Pointer to NORSRAM device instance | |
254 * @param Timing: Pointer to NORSRAM Timing structure | |
255 * @param Bank: NORSRAM bank number | |
256 * @retval HAL status | |
257 */ | |
258 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) | |
259 { | |
260 uint32_t tmpr = 0; | |
261 | |
262 /* Check the parameters */ | |
263 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); | |
264 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); | |
265 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); | |
266 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); | |
267 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); | |
268 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); | |
269 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); | |
270 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); | |
271 assert_param(IS_FMC_NORSRAM_BANK(Bank)); | |
272 | |
273 /* Get the BTCR register value */ | |
274 tmpr = Device->BTCR[Bank + 1]; | |
275 | |
276 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ | |
277 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ | |
278 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ | |
279 FMC_BTR1_ACCMOD)); | |
280 | |
281 /* Set FMC_NORSRAM device timing parameters */ | |
282 tmpr |= (uint32_t)(Timing->AddressSetupTime |\ | |
283 ((Timing->AddressHoldTime) << 4) |\ | |
284 ((Timing->DataSetupTime) << 8) |\ | |
285 ((Timing->BusTurnAroundDuration) << 16) |\ | |
286 (((Timing->CLKDivision)-1) << 20) |\ | |
287 (((Timing->DataLatency)-2) << 24) |\ | |
288 (Timing->AccessMode)); | |
289 | |
290 Device->BTCR[Bank + 1] = tmpr; | |
291 | |
292 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ | |
293 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) | |
294 { | |
295 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); | |
296 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20); | |
297 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr; | |
298 } | |
299 | |
300 return HAL_OK; | |
301 } | |
302 | |
303 /** | |
304 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified | |
305 * parameters in the FMC_NORSRAM_TimingTypeDef | |
306 * @param Device: Pointer to NORSRAM device instance | |
307 * @param Timing: Pointer to NORSRAM Timing structure | |
308 * @param Bank: NORSRAM bank number | |
309 * @retval HAL status | |
310 */ | |
311 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) | |
312 { | |
313 uint32_t tmpr = 0; | |
314 | |
315 /* Check the parameters */ | |
316 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); | |
317 | |
318 /* Set NORSRAM device timing register for write configuration, if extended mode is used */ | |
319 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) | |
320 { | |
321 /* Check the parameters */ | |
322 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); | |
323 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); | |
324 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); | |
325 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); | |
326 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); | |
327 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); | |
328 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); | |
329 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); | |
330 assert_param(IS_FMC_NORSRAM_BANK(Bank)); | |
331 | |
332 /* Get the BWTR register value */ | |
333 tmpr = Device->BWTR[Bank]; | |
334 | |
335 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ | |
336 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ | |
337 FMC_BWTR1_BUSTURN | FMC_BWTR1_CLKDIV | FMC_BWTR1_DATLAT | \ | |
338 FMC_BWTR1_ACCMOD)); | |
339 | |
340 tmpr |= (uint32_t)(Timing->AddressSetupTime |\ | |
341 ((Timing->AddressHoldTime) << 4) |\ | |
342 ((Timing->DataSetupTime) << 8) |\ | |
343 ((Timing->BusTurnAroundDuration) << 16) |\ | |
344 (((Timing->CLKDivision)-1) << 20) |\ | |
345 (((Timing->DataLatency)-2) << 24) |\ | |
346 (Timing->AccessMode)); | |
347 | |
348 Device->BWTR[Bank] = tmpr; | |
349 } | |
350 else | |
351 { | |
352 Device->BWTR[Bank] = 0x0FFFFFFF; | |
353 } | |
354 | |
355 return HAL_OK; | |
356 } | |
357 /** | |
358 * @} | |
359 */ | |
360 | |
361 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 | |
362 * @brief management functions | |
363 * | |
364 @verbatim | |
365 ============================================================================== | |
366 ##### FMC_NORSRAM Control functions ##### | |
367 ============================================================================== | |
368 [..] | |
369 This subsection provides a set of functions allowing to control dynamically | |
370 the FMC NORSRAM interface. | |
371 | |
372 @endverbatim | |
373 * @{ | |
374 */ | |
375 /** | |
376 * @brief Enables dynamically FMC_NORSRAM write operation. | |
377 * @param Device: Pointer to NORSRAM device instance | |
378 * @param Bank: NORSRAM bank number | |
379 * @retval HAL status | |
380 */ | |
381 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) | |
382 { | |
383 /* Check the parameters */ | |
384 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); | |
385 assert_param(IS_FMC_NORSRAM_BANK(Bank)); | |
386 | |
387 /* Enable write operation */ | |
388 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; | |
389 | |
390 return HAL_OK; | |
391 } | |
392 | |
393 /** | |
394 * @brief Disables dynamically FMC_NORSRAM write operation. | |
395 * @param Device: Pointer to NORSRAM device instance | |
396 * @param Bank: NORSRAM bank number | |
397 * @retval HAL status | |
398 */ | |
399 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) | |
400 { | |
401 /* Check the parameters */ | |
402 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); | |
403 assert_param(IS_FMC_NORSRAM_BANK(Bank)); | |
404 | |
405 /* Disable write operation */ | |
406 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; | |
407 | |
408 return HAL_OK; | |
409 } | |
410 | |
411 /** | |
412 * @} | |
413 */ | |
414 | |
415 /** | |
416 * @} | |
417 */ | |
418 | |
419 /** @addtogroup FMC_LL_NAND | |
420 * @brief PCCARD Controller functions | |
421 * | |
422 @verbatim | |
423 ============================================================================== | |
424 ##### How to use NAND device driver ##### | |
425 ============================================================================== | |
426 [..] | |
427 This driver contains a set of APIs to interface with the FMC NAND banks in order | |
428 to run the NAND external devices. | |
429 | |
430 (+) FMC NAND bank reset using the function FMC_NAND_DeInit() | |
431 (+) FMC NAND bank control configuration using the function FMC_NAND_Init() | |
432 (+) FMC NAND bank common space timing configuration using the function | |
433 FMC_NAND_CommonSpace_Timing_Init() | |
434 (+) FMC NAND bank attribute space timing configuration using the function | |
435 FMC_NAND_AttributeSpace_Timing_Init() | |
436 (+) FMC NAND bank enable/disable ECC correction feature using the functions | |
437 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() | |
438 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() | |
439 | |
440 @endverbatim | |
441 * @{ | |
442 */ | |
443 | |
444 /** @addtogroup FMC_LL_NAND_Private_Functions_Group1 | |
445 * @brief Initialization and Configuration functions | |
446 * | |
447 @verbatim | |
448 ============================================================================== | |
449 ##### Initialization and de_initialization functions ##### | |
450 ============================================================================== | |
451 [..] | |
452 This section provides functions allowing to: | |
453 (+) Initialize and configure the FMC NAND interface | |
454 (+) De-initialize the FMC NAND interface | |
455 (+) Configure the FMC clock and associated GPIOs | |
456 | |
457 @endverbatim | |
458 * @{ | |
459 */ | |
460 /** | |
461 * @brief Initializes the FMC_NAND device according to the specified | |
462 * control parameters in the FMC_NAND_HandleTypeDef | |
463 * @param Device: Pointer to NAND device instance | |
464 * @param Init: Pointer to NAND Initialization structure | |
465 * @retval HAL status | |
466 */ | |
467 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) | |
468 { | |
469 uint32_t tmpr = 0; | |
470 | |
471 /* Check the parameters */ | |
472 assert_param(IS_FMC_NAND_DEVICE(Device)); | |
473 assert_param(IS_FMC_NAND_BANK(Init->NandBank)); | |
474 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); | |
475 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); | |
476 assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); | |
477 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); | |
478 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); | |
479 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); | |
480 | |
481 if(Init->NandBank == FMC_NAND_BANK2) | |
482 { | |
483 /* Get the NAND bank 2 register value */ | |
484 tmpr = Device->PCR2; | |
485 } | |
486 else | |
487 { | |
488 /* Get the NAND bank 3 register value */ | |
489 tmpr = Device->PCR3; | |
490 } | |
491 | |
492 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ | |
493 tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \ | |
494 FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ | |
495 FMC_PCR2_TAR | FMC_PCR2_ECCPS)); | |
496 | |
497 /* Set NAND device control parameters */ | |
498 tmpr |= (uint32_t)(Init->Waitfeature |\ | |
499 FMC_PCR_MEMORY_TYPE_NAND |\ | |
500 Init->MemoryDataWidth |\ | |
501 Init->EccComputation |\ | |
502 Init->ECCPageSize |\ | |
503 ((Init->TCLRSetupTime) << 9) |\ | |
504 ((Init->TARSetupTime) << 13)); | |
505 | |
506 if(Init->NandBank == FMC_NAND_BANK2) | |
507 { | |
508 /* NAND bank 2 registers configuration */ | |
509 Device->PCR2 = tmpr; | |
510 } | |
511 else | |
512 { | |
513 /* NAND bank 3 registers configuration */ | |
514 Device->PCR3 = tmpr; | |
515 } | |
516 | |
517 return HAL_OK; | |
518 | |
519 } | |
520 | |
521 /** | |
522 * @brief Initializes the FMC_NAND Common space Timing according to the specified | |
523 * parameters in the FMC_NAND_PCC_TimingTypeDef | |
524 * @param Device: Pointer to NAND device instance | |
525 * @param Timing: Pointer to NAND timing structure | |
526 * @param Bank: NAND bank number | |
527 * @retval HAL status | |
528 */ | |
529 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) | |
530 { | |
531 uint32_t tmpr = 0; | |
532 | |
533 /* Check the parameters */ | |
534 assert_param(IS_FMC_NAND_DEVICE(Device)); | |
535 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); | |
536 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); | |
537 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); | |
538 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); | |
539 assert_param(IS_FMC_NAND_BANK(Bank)); | |
540 | |
541 if(Bank == FMC_NAND_BANK2) | |
542 { | |
543 /* Get the NAND bank 2 register value */ | |
544 tmpr = Device->PMEM2; | |
545 } | |
546 else | |
547 { | |
548 /* Get the NAND bank 3 register value */ | |
549 tmpr = Device->PMEM3; | |
550 } | |
551 | |
552 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ | |
553 tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \ | |
554 FMC_PMEM2_MEMHIZ2)); | |
555 | |
556 /* Set FMC_NAND device timing parameters */ | |
557 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
558 ((Timing->WaitSetupTime) << 8) |\ | |
559 ((Timing->HoldSetupTime) << 16) |\ | |
560 ((Timing->HiZSetupTime) << 24) | |
561 ); | |
562 | |
563 if(Bank == FMC_NAND_BANK2) | |
564 { | |
565 /* NAND bank 2 registers configuration */ | |
566 Device->PMEM2 = tmpr; | |
567 } | |
568 else | |
569 { | |
570 /* NAND bank 3 registers configuration */ | |
571 Device->PMEM3 = tmpr; | |
572 } | |
573 | |
574 return HAL_OK; | |
575 } | |
576 | |
577 /** | |
578 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified | |
579 * parameters in the FMC_NAND_PCC_TimingTypeDef | |
580 * @param Device: Pointer to NAND device instance | |
581 * @param Timing: Pointer to NAND timing structure | |
582 * @param Bank: NAND bank number | |
583 * @retval HAL status | |
584 */ | |
585 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) | |
586 { | |
587 uint32_t tmpr = 0; | |
588 | |
589 /* Check the parameters */ | |
590 assert_param(IS_FMC_NAND_DEVICE(Device)); | |
591 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); | |
592 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); | |
593 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); | |
594 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); | |
595 assert_param(IS_FMC_NAND_BANK(Bank)); | |
596 | |
597 if(Bank == FMC_NAND_BANK2) | |
598 { | |
599 /* Get the NAND bank 2 register value */ | |
600 tmpr = Device->PATT2; | |
601 } | |
602 else | |
603 { | |
604 /* Get the NAND bank 3 register value */ | |
605 tmpr = Device->PATT3; | |
606 } | |
607 | |
608 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ | |
609 tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \ | |
610 FMC_PATT2_ATTHIZ2)); | |
611 | |
612 /* Set FMC_NAND device timing parameters */ | |
613 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
614 ((Timing->WaitSetupTime) << 8) |\ | |
615 ((Timing->HoldSetupTime) << 16) |\ | |
616 ((Timing->HiZSetupTime) << 24)); | |
617 | |
618 if(Bank == FMC_NAND_BANK2) | |
619 { | |
620 /* NAND bank 2 registers configuration */ | |
621 Device->PATT2 = tmpr; | |
622 } | |
623 else | |
624 { | |
625 /* NAND bank 3 registers configuration */ | |
626 Device->PATT3 = tmpr; | |
627 } | |
628 | |
629 return HAL_OK; | |
630 } | |
631 | |
632 /** | |
633 * @brief DeInitializes the FMC_NAND device | |
634 * @param Device: Pointer to NAND device instance | |
635 * @param Bank: NAND bank number | |
636 * @retval HAL status | |
637 */ | |
638 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) | |
639 { | |
640 /* Check the parameters */ | |
641 assert_param(IS_FMC_NAND_DEVICE(Device)); | |
642 assert_param(IS_FMC_NAND_BANK(Bank)); | |
643 | |
644 /* Disable the NAND Bank */ | |
645 __FMC_NAND_DISABLE(Device, Bank); | |
646 | |
647 /* De-initialize the NAND Bank */ | |
648 if(Bank == FMC_NAND_BANK2) | |
649 { | |
650 /* Set the FMC_NAND_BANK2 registers to their reset values */ | |
651 Device->PCR2 = 0x00000018; | |
652 Device->SR2 = 0x00000040; | |
653 Device->PMEM2 = 0xFCFCFCFC; | |
654 Device->PATT2 = 0xFCFCFCFC; | |
655 } | |
656 /* FMC_Bank3_NAND */ | |
657 else | |
658 { | |
659 /* Set the FMC_NAND_BANK3 registers to their reset values */ | |
660 Device->PCR3 = 0x00000018; | |
661 Device->SR3 = 0x00000040; | |
662 Device->PMEM3 = 0xFCFCFCFC; | |
663 Device->PATT3 = 0xFCFCFCFC; | |
664 } | |
665 | |
666 return HAL_OK; | |
667 } | |
668 | |
669 /** | |
670 * @} | |
671 */ | |
672 | |
673 /** @addtogroup FMC_LL_NAND_Private_Functions_Group2 | |
674 * @brief management functions | |
675 * | |
676 @verbatim | |
677 ============================================================================== | |
678 ##### FMC_NAND Control functions ##### | |
679 ============================================================================== | |
680 [..] | |
681 This subsection provides a set of functions allowing to control dynamically | |
682 the FMC NAND interface. | |
683 | |
684 @endverbatim | |
685 * @{ | |
686 */ | |
687 /** | |
688 * @brief Enables dynamically FMC_NAND ECC feature. | |
689 * @param Device: Pointer to NAND device instance | |
690 * @param Bank: NAND bank number | |
691 * @retval HAL status | |
692 */ | |
693 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) | |
694 { | |
695 /* Check the parameters */ | |
696 assert_param(IS_FMC_NAND_DEVICE(Device)); | |
697 assert_param(IS_FMC_NAND_BANK(Bank)); | |
698 | |
699 /* Enable ECC feature */ | |
700 if(Bank == FMC_NAND_BANK2) | |
701 { | |
702 Device->PCR2 |= FMC_PCR2_ECCEN; | |
703 } | |
704 else | |
705 { | |
706 Device->PCR3 |= FMC_PCR3_ECCEN; | |
707 } | |
708 | |
709 return HAL_OK; | |
710 } | |
711 | |
712 /** | |
713 * @brief Disables dynamically FMC_NAND ECC feature. | |
714 * @param Device: Pointer to NAND device instance | |
715 * @param Bank: NAND bank number | |
716 * @retval HAL status | |
717 */ | |
718 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) | |
719 { | |
720 /* Check the parameters */ | |
721 assert_param(IS_FMC_NAND_DEVICE(Device)); | |
722 assert_param(IS_FMC_NAND_BANK(Bank)); | |
723 | |
724 /* Disable ECC feature */ | |
725 if(Bank == FMC_NAND_BANK2) | |
726 { | |
727 Device->PCR2 &= ~FMC_PCR2_ECCEN; | |
728 } | |
729 else | |
730 { | |
731 Device->PCR3 &= ~FMC_PCR3_ECCEN; | |
732 } | |
733 | |
734 return HAL_OK; | |
735 } | |
736 | |
737 /** | |
738 * @brief Disables dynamically FMC_NAND ECC feature. | |
739 * @param Device: Pointer to NAND device instance | |
740 * @param ECCval: Pointer to ECC value | |
741 * @param Bank: NAND bank number | |
742 * @param Timeout: Timeout wait value | |
743 * @retval HAL status | |
744 */ | |
745 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) | |
746 { | |
747 uint32_t tickstart = 0; | |
748 | |
749 /* Check the parameters */ | |
750 assert_param(IS_FMC_NAND_DEVICE(Device)); | |
751 assert_param(IS_FMC_NAND_BANK(Bank)); | |
752 | |
753 /* Get tick */ | |
754 tickstart = HAL_GetTick(); | |
755 | |
756 /* Wait until FIFO is empty */ | |
757 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) | |
758 { | |
759 /* Check for the Timeout */ | |
760 if(Timeout != HAL_MAX_DELAY) | |
761 { | |
762 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) | |
763 { | |
764 return HAL_TIMEOUT; | |
765 } | |
766 } | |
767 } | |
768 | |
769 if(Bank == FMC_NAND_BANK2) | |
770 { | |
771 /* Get the ECCR2 register value */ | |
772 *ECCval = (uint32_t)Device->ECCR2; | |
773 } | |
774 else | |
775 { | |
776 /* Get the ECCR3 register value */ | |
777 *ECCval = (uint32_t)Device->ECCR3; | |
778 } | |
779 | |
780 return HAL_OK; | |
781 } | |
782 | |
783 /** | |
784 * @} | |
785 */ | |
786 | |
787 /** | |
788 * @} | |
789 */ | |
790 | |
791 /** @addtogroup FMC_LL_PCCARD | |
792 * @brief PCCARD Controller functions | |
793 * | |
794 @verbatim | |
795 ============================================================================== | |
796 ##### How to use PCCARD device driver ##### | |
797 ============================================================================== | |
798 [..] | |
799 This driver contains a set of APIs to interface with the FMC PCCARD bank in order | |
800 to run the PCCARD/compact flash external devices. | |
801 | |
802 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit() | |
803 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init() | |
804 (+) FMC PCCARD bank common space timing configuration using the function | |
805 FMC_PCCARD_CommonSpace_Timing_Init() | |
806 (+) FMC PCCARD bank attribute space timing configuration using the function | |
807 FMC_PCCARD_AttributeSpace_Timing_Init() | |
808 (+) FMC PCCARD bank IO space timing configuration using the function | |
809 FMC_PCCARD_IOSpace_Timing_Init() | |
810 @endverbatim | |
811 * @{ | |
812 */ | |
813 | |
814 /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1 | |
815 * @brief Initialization and Configuration functions | |
816 * | |
817 @verbatim | |
818 ============================================================================== | |
819 ##### Initialization and de_initialization functions ##### | |
820 ============================================================================== | |
821 [..] | |
822 This section provides functions allowing to: | |
823 (+) Initialize and configure the FMC PCCARD interface | |
824 (+) De-initialize the FMC PCCARD interface | |
825 (+) Configure the FMC clock and associated GPIOs | |
826 | |
827 @endverbatim | |
828 * @{ | |
829 */ | |
830 | |
831 /** | |
832 * @brief Initializes the FMC_PCCARD device according to the specified | |
833 * control parameters in the FMC_PCCARD_HandleTypeDef | |
834 * @param Device: Pointer to PCCARD device instance | |
835 * @param Init: Pointer to PCCARD Initialization structure | |
836 * @retval HAL status | |
837 */ | |
838 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) | |
839 { | |
840 uint32_t tmpr = 0; | |
841 | |
842 /* Check the parameters */ | |
843 assert_param(IS_FMC_PCCARD_DEVICE(Device)); | |
844 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); | |
845 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); | |
846 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); | |
847 | |
848 /* Get PCCARD control register value */ | |
849 tmpr = Device->PCR4; | |
850 | |
851 /* Clear TAR, TCLR, PWAITEN and PWID bits */ | |
852 tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \ | |
853 FMC_PCR4_PWID)); | |
854 | |
855 /* Set FMC_PCCARD device control parameters */ | |
856 tmpr |= (uint32_t)(Init->Waitfeature |\ | |
857 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ | |
858 (Init->TCLRSetupTime << 9) |\ | |
859 (Init->TARSetupTime << 13)); | |
860 | |
861 Device->PCR4 = tmpr; | |
862 | |
863 return HAL_OK; | |
864 } | |
865 | |
866 /** | |
867 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified | |
868 * parameters in the FMC_NAND_PCC_TimingTypeDef | |
869 * @param Device: Pointer to PCCARD device instance | |
870 * @param Timing: Pointer to PCCARD timing structure | |
871 * @retval HAL status | |
872 */ | |
873 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) | |
874 { | |
875 uint32_t tmpr = 0; | |
876 | |
877 /* Check the parameters */ | |
878 assert_param(IS_FMC_PCCARD_DEVICE(Device)); | |
879 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); | |
880 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); | |
881 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); | |
882 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); | |
883 | |
884 /* Get PCCARD common space timing register value */ | |
885 tmpr = Device->PMEM4; | |
886 | |
887 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ | |
888 tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \ | |
889 FMC_PMEM4_MEMHIZ4)); | |
890 /* Set PCCARD timing parameters */ | |
891 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
892 ((Timing->WaitSetupTime) << 8) |\ | |
893 ((Timing->HoldSetupTime) << 16) |\ | |
894 ((Timing->HiZSetupTime) << 24)); | |
895 | |
896 Device->PMEM4 = tmpr; | |
897 | |
898 return HAL_OK; | |
899 } | |
900 | |
901 /** | |
902 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified | |
903 * parameters in the FMC_NAND_PCC_TimingTypeDef | |
904 * @param Device: Pointer to PCCARD device instance | |
905 * @param Timing: Pointer to PCCARD timing structure | |
906 * @retval HAL status | |
907 */ | |
908 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) | |
909 { | |
910 uint32_t tmpr = 0; | |
911 | |
912 /* Check the parameters */ | |
913 assert_param(IS_FMC_PCCARD_DEVICE(Device)); | |
914 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); | |
915 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); | |
916 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); | |
917 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); | |
918 | |
919 /* Get PCCARD timing parameters */ | |
920 tmpr = Device->PATT4; | |
921 | |
922 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ | |
923 tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \ | |
924 FMC_PATT4_ATTHIZ4)); | |
925 | |
926 /* Set PCCARD timing parameters */ | |
927 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
928 ((Timing->WaitSetupTime) << 8) |\ | |
929 ((Timing->HoldSetupTime) << 16) |\ | |
930 ((Timing->HiZSetupTime) << 24)); | |
931 Device->PATT4 = tmpr; | |
932 | |
933 return HAL_OK; | |
934 } | |
935 | |
936 /** | |
937 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified | |
938 * parameters in the FMC_NAND_PCC_TimingTypeDef | |
939 * @param Device: Pointer to PCCARD device instance | |
940 * @param Timing: Pointer to PCCARD timing structure | |
941 * @retval HAL status | |
942 */ | |
943 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) | |
944 { | |
945 uint32_t tmpr = 0; | |
946 | |
947 /* Check the parameters */ | |
948 assert_param(IS_FMC_PCCARD_DEVICE(Device)); | |
949 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); | |
950 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); | |
951 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); | |
952 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); | |
953 | |
954 /* Get FMC_PCCARD device timing parameters */ | |
955 tmpr = Device->PIO4; | |
956 | |
957 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ | |
958 tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \ | |
959 FMC_PIO4_IOHIZ4)); | |
960 | |
961 /* Set FMC_PCCARD device timing parameters */ | |
962 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
963 ((Timing->WaitSetupTime) << 8) |\ | |
964 ((Timing->HoldSetupTime) << 16) |\ | |
965 ((Timing->HiZSetupTime) << 24)); | |
966 | |
967 Device->PIO4 = tmpr; | |
968 | |
969 return HAL_OK; | |
970 } | |
971 | |
972 /** | |
973 * @brief DeInitializes the FMC_PCCARD device | |
974 * @param Device: Pointer to PCCARD device instance | |
975 * @retval HAL status | |
976 */ | |
977 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) | |
978 { | |
979 /* Check the parameters */ | |
980 assert_param(IS_FMC_PCCARD_DEVICE(Device)); | |
981 | |
982 /* Disable the FMC_PCCARD device */ | |
983 __FMC_PCCARD_DISABLE(Device); | |
984 | |
985 /* De-initialize the FMC_PCCARD device */ | |
986 Device->PCR4 = 0x00000018; | |
987 Device->SR4 = 0x00000000; | |
988 Device->PMEM4 = 0xFCFCFCFC; | |
989 Device->PATT4 = 0xFCFCFCFC; | |
990 Device->PIO4 = 0xFCFCFCFC; | |
991 | |
992 return HAL_OK; | |
993 } | |
994 | |
995 /** | |
996 * @} | |
997 */ | |
998 | |
999 | |
1000 /** @addtogroup FMC_LL_SDRAM | |
1001 * @brief SDRAM Controller functions | |
1002 * | |
1003 @verbatim | |
1004 ============================================================================== | |
1005 ##### How to use SDRAM device driver ##### | |
1006 ============================================================================== | |
1007 [..] | |
1008 This driver contains a set of APIs to interface with the FMC SDRAM banks in order | |
1009 to run the SDRAM external devices. | |
1010 | |
1011 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() | |
1012 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() | |
1013 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() | |
1014 (+) FMC SDRAM bank enable/disable write operation using the functions | |
1015 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() | |
1016 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() | |
1017 | |
1018 @endverbatim | |
1019 * @{ | |
1020 */ | |
1021 | |
1022 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 | |
1023 * @brief Initialization and Configuration functions | |
1024 * | |
1025 @verbatim | |
1026 ============================================================================== | |
1027 ##### Initialization and de_initialization functions ##### | |
1028 ============================================================================== | |
1029 [..] | |
1030 This section provides functions allowing to: | |
1031 (+) Initialize and configure the FMC SDRAM interface | |
1032 (+) De-initialize the FMC SDRAM interface | |
1033 (+) Configure the FMC clock and associated GPIOs | |
1034 | |
1035 @endverbatim | |
1036 * @{ | |
1037 */ | |
1038 | |
1039 /** | |
1040 * @brief Initializes the FMC_SDRAM device according to the specified | |
1041 * control parameters in the FMC_SDRAM_InitTypeDef | |
1042 * @param Device: Pointer to SDRAM device instance | |
1043 * @param Init: Pointer to SDRAM Initialization structure | |
1044 * @retval HAL status | |
1045 */ | |
1046 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) | |
1047 { | |
1048 uint32_t tmpr1 = 0; | |
1049 uint32_t tmpr2 = 0; | |
1050 | |
1051 /* Check the parameters */ | |
1052 assert_param(IS_FMC_SDRAM_DEVICE(Device)); | |
1053 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); | |
1054 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); | |
1055 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); | |
1056 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); | |
1057 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); | |
1058 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); | |
1059 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); | |
1060 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); | |
1061 assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); | |
1062 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); | |
1063 | |
1064 /* Set SDRAM bank configuration parameters */ | |
1065 if (Init->SDBank != FMC_SDRAM_BANK2) | |
1066 { | |
1067 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; | |
1068 | |
1069 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ | |
1070 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ | |
1071 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ | |
1072 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); | |
1073 | |
1074 | |
1075 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ | |
1076 Init->RowBitsNumber |\ | |
1077 Init->MemoryDataWidth |\ | |
1078 Init->InternalBankNumber |\ | |
1079 Init->CASLatency |\ | |
1080 Init->WriteProtection |\ | |
1081 Init->SDClockPeriod |\ | |
1082 Init->ReadBurst |\ | |
1083 Init->ReadPipeDelay | |
1084 ); | |
1085 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; | |
1086 } | |
1087 else /* FMC_Bank2_SDRAM */ | |
1088 { | |
1089 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; | |
1090 | |
1091 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ | |
1092 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ | |
1093 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ | |
1094 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); | |
1095 | |
1096 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ | |
1097 Init->ReadBurst |\ | |
1098 Init->ReadPipeDelay); | |
1099 | |
1100 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; | |
1101 | |
1102 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ | |
1103 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ | |
1104 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ | |
1105 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); | |
1106 | |
1107 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ | |
1108 Init->RowBitsNumber |\ | |
1109 Init->MemoryDataWidth |\ | |
1110 Init->InternalBankNumber |\ | |
1111 Init->CASLatency |\ | |
1112 Init->WriteProtection); | |
1113 | |
1114 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; | |
1115 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; | |
1116 } | |
1117 | |
1118 return HAL_OK; | |
1119 } | |
1120 | |
1121 /** | |
1122 * @brief Initializes the FMC_SDRAM device timing according to the specified | |
1123 * parameters in the FMC_SDRAM_TimingTypeDef | |
1124 * @param Device: Pointer to SDRAM device instance | |
1125 * @param Timing: Pointer to SDRAM Timing structure | |
1126 * @param Bank: SDRAM bank number | |
1127 * @retval HAL status | |
1128 */ | |
1129 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) | |
1130 { | |
1131 uint32_t tmpr1 = 0; | |
1132 uint32_t tmpr2 = 0; | |
1133 | |
1134 /* Check the parameters */ | |
1135 assert_param(IS_FMC_SDRAM_DEVICE(Device)); | |
1136 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); | |
1137 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); | |
1138 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); | |
1139 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); | |
1140 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); | |
1141 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); | |
1142 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); | |
1143 assert_param(IS_FMC_SDRAM_BANK(Bank)); | |
1144 | |
1145 /* Set SDRAM device timing parameters */ | |
1146 if (Bank != FMC_SDRAM_BANK2) | |
1147 { | |
1148 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; | |
1149 | |
1150 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ | |
1151 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ | |
1152 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ | |
1153 FMC_SDTR1_TRCD)); | |
1154 | |
1155 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ | |
1156 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ | |
1157 (((Timing->SelfRefreshTime)-1) << 8) |\ | |
1158 (((Timing->RowCycleDelay)-1) << 12) |\ | |
1159 (((Timing->WriteRecoveryTime)-1) <<16) |\ | |
1160 (((Timing->RPDelay)-1) << 20) |\ | |
1161 (((Timing->RCDDelay)-1) << 24)); | |
1162 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; | |
1163 } | |
1164 else /* FMC_Bank2_SDRAM */ | |
1165 { | |
1166 tmpr1 = Device->SDTR[FMC_SDRAM_BANK2]; | |
1167 | |
1168 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ | |
1169 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ | |
1170 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ | |
1171 FMC_SDTR1_TRCD)); | |
1172 | |
1173 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ | |
1174 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ | |
1175 (((Timing->SelfRefreshTime)-1) << 8) |\ | |
1176 (((Timing->WriteRecoveryTime)-1) <<16) |\ | |
1177 (((Timing->RCDDelay)-1) << 24)); | |
1178 | |
1179 tmpr2 = Device->SDTR[FMC_SDRAM_BANK1]; | |
1180 | |
1181 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ | |
1182 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ | |
1183 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ | |
1184 FMC_SDTR1_TRCD)); | |
1185 tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ | |
1186 (((Timing->RPDelay)-1) << 20)); | |
1187 | |
1188 Device->SDTR[FMC_SDRAM_BANK2] = tmpr1; | |
1189 Device->SDTR[FMC_SDRAM_BANK1] = tmpr2; | |
1190 } | |
1191 | |
1192 return HAL_OK; | |
1193 } | |
1194 | |
1195 /** | |
1196 * @brief DeInitializes the FMC_SDRAM peripheral | |
1197 * @param Device: Pointer to SDRAM device instance | |
1198 * @retval HAL status | |
1199 */ | |
1200 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) | |
1201 { | |
1202 /* Check the parameters */ | |
1203 assert_param(IS_FMC_SDRAM_DEVICE(Device)); | |
1204 assert_param(IS_FMC_SDRAM_BANK(Bank)); | |
1205 | |
1206 /* De-initialize the SDRAM device */ | |
1207 Device->SDCR[Bank] = 0x000002D0; | |
1208 Device->SDTR[Bank] = 0x0FFFFFFF; | |
1209 Device->SDCMR = 0x00000000; | |
1210 Device->SDRTR = 0x00000000; | |
1211 Device->SDSR = 0x00000000; | |
1212 | |
1213 return HAL_OK; | |
1214 } | |
1215 | |
1216 /** | |
1217 * @} | |
1218 */ | |
1219 | |
1220 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 | |
1221 * @brief management functions | |
1222 * | |
1223 @verbatim | |
1224 ============================================================================== | |
1225 ##### FMC_SDRAM Control functions ##### | |
1226 ============================================================================== | |
1227 [..] | |
1228 This subsection provides a set of functions allowing to control dynamically | |
1229 the FMC SDRAM interface. | |
1230 | |
1231 @endverbatim | |
1232 * @{ | |
1233 */ | |
1234 /** | |
1235 * @brief Enables dynamically FMC_SDRAM write protection. | |
1236 * @param Device: Pointer to SDRAM device instance | |
1237 * @param Bank: SDRAM bank number | |
1238 * @retval HAL status | |
1239 */ | |
1240 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) | |
1241 { | |
1242 /* Check the parameters */ | |
1243 assert_param(IS_FMC_SDRAM_DEVICE(Device)); | |
1244 assert_param(IS_FMC_SDRAM_BANK(Bank)); | |
1245 | |
1246 /* Enable write protection */ | |
1247 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; | |
1248 | |
1249 return HAL_OK; | |
1250 } | |
1251 | |
1252 /** | |
1253 * @brief Disables dynamically FMC_SDRAM write protection. | |
1254 * @param hsdram: FMC_SDRAM handle | |
1255 * @retval HAL status | |
1256 */ | |
1257 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) | |
1258 { | |
1259 /* Check the parameters */ | |
1260 assert_param(IS_FMC_SDRAM_DEVICE(Device)); | |
1261 assert_param(IS_FMC_SDRAM_BANK(Bank)); | |
1262 | |
1263 /* Disable write protection */ | |
1264 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; | |
1265 | |
1266 return HAL_OK; | |
1267 } | |
1268 | |
1269 /** | |
1270 * @brief Send Command to the FMC SDRAM bank | |
1271 * @param Device: Pointer to SDRAM device instance | |
1272 * @param Command: Pointer to SDRAM command structure | |
1273 * @param Timing: Pointer to SDRAM Timing structure | |
1274 * @param Timeout: Timeout wait value | |
1275 * @retval HAL state | |
1276 */ | |
1277 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) | |
1278 { | |
1279 __IO uint32_t tmpr = 0; | |
1280 uint32_t tickstart = 0; | |
1281 | |
1282 /* Check the parameters */ | |
1283 assert_param(IS_FMC_SDRAM_DEVICE(Device)); | |
1284 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); | |
1285 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); | |
1286 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); | |
1287 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); | |
1288 | |
1289 /* Set command register */ | |
1290 tmpr = (uint32_t)((Command->CommandMode) |\ | |
1291 (Command->CommandTarget) |\ | |
1292 (((Command->AutoRefreshNumber)-1) << 5) |\ | |
1293 ((Command->ModeRegisterDefinition) << 9) | |
1294 ); | |
1295 | |
1296 Device->SDCMR = tmpr; | |
1297 | |
1298 /* Get tick */ | |
1299 tickstart = HAL_GetTick(); | |
1300 | |
1301 /* wait until command is send */ | |
1302 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) | |
1303 { | |
1304 /* Check for the Timeout */ | |
1305 if(Timeout != HAL_MAX_DELAY) | |
1306 { | |
1307 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) | |
1308 { | |
1309 return HAL_TIMEOUT; | |
1310 } | |
1311 } | |
1312 | |
1313 return HAL_ERROR; | |
1314 } | |
1315 | |
1316 return HAL_OK; | |
1317 } | |
1318 | |
1319 /** | |
1320 * @brief Program the SDRAM Memory Refresh rate. | |
1321 * @param Device: Pointer to SDRAM device instance | |
1322 * @param RefreshRate: The SDRAM refresh rate value. | |
1323 * @retval HAL state | |
1324 */ | |
1325 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) | |
1326 { | |
1327 /* Check the parameters */ | |
1328 assert_param(IS_FMC_SDRAM_DEVICE(Device)); | |
1329 assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); | |
1330 | |
1331 /* Set the refresh rate in command register */ | |
1332 Device->SDRTR |= (RefreshRate<<1); | |
1333 | |
1334 return HAL_OK; | |
1335 } | |
1336 | |
1337 /** | |
1338 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. | |
1339 * @param Device: Pointer to SDRAM device instance | |
1340 * @param AutoRefreshNumber: Specifies the auto Refresh number. | |
1341 * @retval None | |
1342 */ | |
1343 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) | |
1344 { | |
1345 /* Check the parameters */ | |
1346 assert_param(IS_FMC_SDRAM_DEVICE(Device)); | |
1347 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); | |
1348 | |
1349 /* Set the Auto-refresh number in command register */ | |
1350 Device->SDCMR |= (AutoRefreshNumber << 5); | |
1351 | |
1352 return HAL_OK; | |
1353 } | |
1354 | |
1355 /** | |
1356 * @brief Returns the indicated FMC SDRAM bank mode status. | |
1357 * @param Device: Pointer to SDRAM device instance | |
1358 * @param Bank: Defines the FMC SDRAM bank. This parameter can be | |
1359 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. | |
1360 * @retval The FMC SDRAM bank mode status, could be on of the following values: | |
1361 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or | |
1362 * FMC_SDRAM_POWER_DOWN_MODE. | |
1363 */ | |
1364 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) | |
1365 { | |
1366 uint32_t tmpreg = 0; | |
1367 | |
1368 /* Check the parameters */ | |
1369 assert_param(IS_FMC_SDRAM_DEVICE(Device)); | |
1370 assert_param(IS_FMC_SDRAM_BANK(Bank)); | |
1371 | |
1372 /* Get the corresponding bank mode */ | |
1373 if(Bank == FMC_SDRAM_BANK1) | |
1374 { | |
1375 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); | |
1376 } | |
1377 else | |
1378 { | |
1379 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2); | |
1380 } | |
1381 | |
1382 /* Return the mode status */ | |
1383 return tmpreg; | |
1384 } | |
1385 | |
1386 /** | |
1387 * @} | |
1388 */ | |
1389 | |
1390 /** | |
1391 * @} | |
1392 */ | |
1393 | |
1394 /** | |
1395 * @} | |
1396 */ | |
1397 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ | |
1398 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ | |
1399 | |
1400 /** | |
1401 * @} | |
1402 */ | |
1403 | |
1404 /** | |
1405 * @} | |
1406 */ | |
1407 | |
1408 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |